--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.4 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and \r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety \r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting, \r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include <lpc21xx.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* =12.0MHz xtal multiplied by 5 using the PLL. */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 13 * 1024 )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.4 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and \r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety \r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting, \r
+ licensing and training services.\r
+*/\r
+\r
+\r
+#include "FreeRTOS.h"\r
+#include "portable.h"\r
+#include "partest.h"\r
+\r
+#define partstFIRST_IO ( ( unsigned portLONG ) 0x10000 )\r
+#define partstNUM_LEDS ( 8 )\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* This is performed from main() as the io bits are shared with other setup\r
+ functions. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portLONG ulLED = partstFIRST_IO;\r
+\r
+ if( uxLED < partstNUM_LEDS )\r
+ {\r
+ /* Rotate to the wanted bit of port 0. Only P16 to P23 have an LED\r
+ attached. */\r
+ ulLED <<= ( unsigned portLONG ) uxLED;\r
+\r
+ /* Set or clear the output. */\r
+ if( xValue )\r
+ {\r
+ IOSET1 = ulLED;\r
+ }\r
+ else\r
+ {\r
+ IOCLR1 = ulLED; \r
+ }\r
+ } \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState;\r
+\r
+ if( uxLED < partstNUM_LEDS )\r
+ {\r
+ /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED\r
+ attached. */\r
+ ulLED <<= ( unsigned portLONG ) uxLED;\r
+\r
+ /* If this bit is already set, clear it, and visa versa. */\r
+ ulCurrentState = IOPIN1;\r
+ if( ulCurrentState & ulLED )\r
+ {\r
+ IOCLR1 = ulLED;\r
+ }\r
+ else\r
+ {\r
+ IOSET1 = ulLED; \r
+ }\r
+ } \r
+}\r
+\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+ cExt (*.c)\r
+ aExt (*.s*; *.src; *.a*)\r
+ oExt (*.obj)\r
+ lExt (*.lib)\r
+ tExt (*.txt; *.h; *.inc)\r
+ pExt (*.plm)\r
+ CppX (*.cpp)\r
+ DaveTm { 0,0,0,0,0,0,0,0 }\r
+\r
+Target (RTOSDemo), 0x0004 // Tools: 'ARM-ADS'\r
+GRPOPT 1,(Other),1,0,0\r
+GRPOPT 2,(FreeRTOS),0,0,0\r
+GRPOPT 3,(Stadard Demo),0,0,0\r
+\r
+OPTFFF 1,1,2,0,0,0,0,0,<.\Startup.s><Startup.s> \r
+OPTFFF 1,2,1,0,0,0,0,0,<.\ParTest\ParTest.c><ParTest.c> \r
+OPTFFF 1,3,1,2,0,160,164,0,<.\main.c><main.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,154,0,0,0,161,0,0,0,23,5,0,0,111,2,0,0 }\r
+OPTFFF 1,4,1,234881024,0,0,0,0,<.\serial\serial.c><serial.c> \r
+OPTFFF 1,5,2,486539264,0,0,0,0,<.\serial\serialISR.s><serialISR.s> \r
+OPTFFF 2,6,1,0,0,0,0,0,<..\..\Source\tasks.c><tasks.c> \r
+OPTFFF 2,7,1,0,0,0,0,0,<..\..\Source\list.c><list.c> \r
+OPTFFF 2,8,1,0,0,0,0,0,<..\..\Source\queue.c><queue.c> \r
+OPTFFF 2,9,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM7_LPC21xx\port.c><port.c> \r
+OPTFFF 2,10,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> \r
+OPTFFF 2,11,2,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM7_LPC21xx\portASM.s><portASM.s> \r
+OPTFFF 3,12,1,0,0,0,0,0,<..\Common\Minimal\flash.c><flash.c> \r
+OPTFFF 3,13,1,0,0,0,0,0,<..\Common\Minimal\integer.c><integer.c> \r
+OPTFFF 3,14,1,0,0,0,0,0,<..\Common\Minimal\comtest.c><comtest.c> \r
+\r
+\r
+TARGOPT 1, (RTOSDemo)\r
+ ADSCLK=12000000\r
+ OPTTT 1,1,1,0\r
+ OPTHX 1,65535,0,0,0\r
+ OPTLX 79,66,8,<.\>\r
+ OPTOX 16\r
+ OPTLT 1,1,1,0,1,1,0,1,0,0,0,0\r
+ OPTXL 1,1,1,1,1,1,1,0,0\r
+ OPTFL 1,0,1\r
+ OPTAX 8\r
+ OPTBL 0,(Data Sheet)<DATASHTS\PHILIPS\LPC2119_2129.PDF>\r
+ OPTBL 1,(User Manual)<DATASHTS\PHILIPS\user_manual_LPC2119_2129_2194_2292_2294.PDF>\r
+ OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)\r
+ OPTDBG 48125,0,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()\r
+ OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))\r
+ OPTKEY 0,(ARMDBGFLAGS)(-T5F)\r
+ OPTDF 0x86\r
+ OPTLE <>\r
+ OPTLC <>\r
+EndOpt\r
+\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+Target (RTOSDemo), 0x0004 // Tools: 'ARM-ADS'\r
+\r
+Group (Other)\r
+Group (FreeRTOS)\r
+Group (Stadard Demo)\r
+\r
+File 1,2,<.\Startup.s><Startup.s>\r
+File 1,1,<.\ParTest\ParTest.c><ParTest.c>\r
+File 1,1,<.\main.c><main.c>\r
+File 1,1,<.\serial\serial.c><serial.c>\r
+File 1,2,<.\serial\serialISR.s><serialISR.s>\r
+File 2,1,<..\..\Source\tasks.c><tasks.c>\r
+File 2,1,<..\..\Source\list.c><list.c>\r
+File 2,1,<..\..\Source\queue.c><queue.c>\r
+File 2,1,<..\..\Source\portable\RVDS\ARM7_LPC21xx\port.c><port.c>\r
+File 2,1,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c>\r
+File 2,2,<..\..\Source\portable\RVDS\ARM7_LPC21xx\portASM.s><portASM.s>\r
+File 3,1,<..\Common\Minimal\flash.c><flash.c>\r
+File 3,1,<..\Common\Minimal\integer.c><integer.c>\r
+File 3,1,<..\Common\Minimal\comtest.c><comtest.c>\r
+\r
+\r
+Options 1,0,0 // Target 'RTOSDemo'\r
+ Device (LPC2129)\r
+ Vendor (NXP (founded by Philips))\r
+ Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI))\r
+ FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1))\r
+ StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code"))\r
+ FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000))\r
+ DevID (3648)\r
+ Rgf (LPC21xx.H)\r
+ Mem ()\r
+ C ()\r
+ A ()\r
+ RL ()\r
+ OH ()\r
+ DBC_IFX ()\r
+ DBC_CMS ()\r
+ DBC_AMS ()\r
+ DBC_LMS ()\r
+ UseEnv=0\r
+ EnvBin ()\r
+ EnvInc ()\r
+ EnvLib ()\r
+ EnvReg (ÿPhilips\)\r
+ OrgReg (ÿPhilips\)\r
+ TgStat=16\r
+ OutDir (.\)\r
+ OutName (RTOSDemo)\r
+ GenApp=1\r
+ GenLib=0\r
+ GenHex=0\r
+ Debug=1\r
+ Browse=1\r
+ LstDir (.\)\r
+ HexSel=1\r
+ MG32K=0\r
+ TGMORE=0\r
+ RunUsr 0 0 <>\r
+ RunUsr 1 0 <>\r
+ BrunUsr 0 0 <>\r
+ BrunUsr 1 0 <>\r
+ CrunUsr 0 0 <>\r
+ CrunUsr 1 0 <>\r
+ SVCSID <>\r
+ GLFLAGS=1790\r
+ ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ACPUTYP (ARM7TDMI)\r
+ RVDEV ()\r
+ ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ OCMADSIRAM { 0,0,0,0,64,0,64,0,0 }\r
+ OCMADSIROM { 1,0,0,0,0,0,0,4,0 }\r
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }\r
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0 }\r
+ RV_STAVEC ()\r
+ ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSCMISC ()\r
+ ADSCDEFN (ARM7_LPC21xx_KEIL_RVDS)\r
+ ADSCUDEF ()\r
+ ADSCINCD (.;..\..\Source\portable\RVDS\ARM7_LPC21xx;..\Common\include;..\..\Source\include)\r
+ ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSAMISC ()\r
+ ADSADEFN ()\r
+ ADSAUDEF ()\r
+ ADSAINCD (..\..\Source\portable\RVDS\ARM7_LPC21xx)\r
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ IncBld=1\r
+ AlwaysBuild=0\r
+ GenAsm=0\r
+ AsmAsm=0\r
+ PublicsOnly=0\r
+ StopCode=3\r
+ CustArgs ()\r
+ LibMods ()\r
+ ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSLDTA (0x00000000)\r
+ ADSLDDA (0x40000000)\r
+ ADSLDSC ()\r
+ ADSLDIB ()\r
+ ADSLDIC ()\r
+ ADSLDMC ()\r
+ ADSLDIF ()\r
+ ADSLDDW ()\r
+ OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)\r
+ OPTDBG 48125,0,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()\r
+ FLASH1 { 2,0,0,0,0,0,0,0,255,255,255,255,0,0,0,0,0,0,0,0 }\r
+ FLASH2 ()\r
+ FLASH3 (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1))\r
+ FLASH4 ()\r
+EndOpt\r
+\r
--- /dev/null
+<html>\r
+<body>\r
+<pre>\r
+<h1>µVision3 Build Log</h1>\r
+<h2>Project:</h2>\r
+C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\ARM7_LPC2129_Keil_RVDS\RTOSDemo.uv2\r
+Project File Date: 10/23/2008\r
+\r
+<h2>Output:</h2>\r
+Clean started: Project: 'RTOSDemo'\r
+ deleting intermediate output files for target 'RTOSDemo'\r
--- /dev/null
+; *************************************************************\r
+; *** Scatter-Loading Description File generated by uVision ***\r
+; *************************************************************\r
+\r
+LR_IROM1 0x00000000 0x00040000 { ; load region size_region\r
+ ER_IROM1 0x00000000 0x00040000 { ; load address = execution address\r
+ *.o (RESET, +First)\r
+ *(InRoot$$Sections)\r
+ .ANY (+RO)\r
+ }\r
+ RW_IRAM1 0x40000000 0x00004000 { ; RW data\r
+ .ANY (+RW +ZI)\r
+ }\r
+}\r
+\r
--- /dev/null
+*** Creating Trace Output File 'RTOSDemo.tra' Ok.\r
+### Preparing for ADS-LD.\r
+### Creating ADS-LD Command Line\r
+### List of Objects: adding '"startup.o"'\r
+### List of Objects: adding '"partest.o"'\r
+### List of Objects: adding '"main.o"'\r
+### List of Objects: adding '"serial.o"'\r
+### List of Objects: adding '"serialisr.o"'\r
+### List of Objects: adding '"tasks.o"'\r
+### List of Objects: adding '"list.o"'\r
+### List of Objects: adding '"queue.o"'\r
+### List of Objects: adding '"port.o"'\r
+### List of Objects: adding '"heap_2.o"'\r
+### List of Objects: adding '".\portasm.o"'\r
+### List of Objects: adding '"flash.o"'\r
+### List of Objects: adding '"integer.o"'\r
+### List of Objects: adding '"comtest.o"'\r
+### ADS-LD Command completed:\r
+"startup.o" "partest.o" "main.o" "serial.o" "serialisr.o" "tasks.o" "list.o" "queue.o" "port.o" "heap_2.o" ".\portasm.o" "flash.o" "integer.o" "comtest.o" --device DARMP --strict --scatter "RTOSDemo.sct" \r\r
+--autoat --summary_stderr --info summarysizes --map --xref --callgraph --symbols \r\r
+--info sizes --info totals --info unused --info veneers \r\r
+ --list ".\RTOSDemo.map" -o "RTOSDemo.axf"### Preparing Environment (PrepEnvAds)\r
+### ADS-LD Output File: 'RTOSDemo.axf'\r
+### ADS-LD Command File: 'RTOSDemo.lnp'\r
+### Checking for dirty Components...\r
+### Creating CmdFile 'RTOSDemo.lnp', Handle=0x0000044C\r
+### Writing '.lnp' file\r
+### ADS-LD Command file 'RTOSDemo.lnp' is ready.\r
+### ADS-LD: About to start ADS-LD Thread.\r
+### ADS-LD: executed with 0 errors\r
+### Updating obj list\r
+### LDADS_file() completed.\r
--- /dev/null
+[Signal 1]\r
+DispName=Port1\r
+PlotType=1\r
+Color=16711935\r
+MinDec=0\r
+MinVal=0.\r
+MaxDec=0\r
+MaxVal=-1.\r
+Mask=65536\r
+Offset=16\r
+[Signal 2]\r
+DispName=Port1\r
+PlotType=1\r
+Color=255\r
+MinDec=0\r
+MinVal=0.\r
+MaxDec=0\r
+MaxVal=-1.\r
+Mask=131072\r
+Offset=17\r
+[Signal 3]\r
+DispName=Port1\r
+PlotType=1\r
+Color=32768\r
+MinDec=0\r
+MinVal=0.\r
+MaxDec=0\r
+MaxVal=-1.\r
+Mask=262144\r
+Offset=18\r
+[Signal 4]\r
+DispName=Port1\r
+PlotType=1\r
+Color=16711680\r
+MinDec=0\r
+MinVal=0.\r
+MaxDec=0\r
+MaxVal=-1.\r
+Mask=524288\r
+Offset=19\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+ cExt (*.c)\r
+ aExt (*.s*; *.src; *.a*)\r
+ oExt (*.obj)\r
+ lExt (*.lib)\r
+ tExt (*.txt; *.h; *.inc)\r
+ pExt (*.plm)\r
+ CppX (*.cpp)\r
+ DaveTm { 0,0,0,0,0,0,0,0 }\r
+\r
+Target (RTOSDemo), 0x0004 // Tools: 'ARM-ADS'\r
+GRPOPT 1,(Other),0,0,0\r
+GRPOPT 2,(FreeRTOS),0,0,0\r
+GRPOPT 3,(Stadard Demo),0,0,0\r
+\r
+OPTFFF 1,1,2,0,0,1,1,0,<.\Startup.s><Startup.s> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,232,255,255,255,132,0,0,0,138,0,0,0,237,3,0,0,92,2,0,0 }\r
+OPTFFF 1,2,1,0,0,1,1,0,<.\ParTest\ParTest.c><ParTest.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,232,255,255,255,154,0,0,0,161,0,0,0,3,4,0,0,115,2,0,0 }\r
+OPTFFF 1,3,1,0,0,1,1,0,<.\main.c><main.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,232,255,255,255,133,0,0,0,3,0,0,0,24,5,0,0,214,2,0,0 }\r
+OPTFFF 1,4,1,0,0,1,1,0,<.\serial\serial.c><serial.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,232,255,255,255,88,0,0,0,92,0,0,0,189,3,0,0,42,2,0,0 }\r
+OPTFFF 2,5,1,0,0,0,0,0,<..\..\Source\tasks.c><tasks.c> \r
+OPTFFF 2,6,1,0,0,0,0,0,<..\..\Source\list.c><list.c> \r
+OPTFFF 2,7,1,0,0,0,0,0,<..\..\Source\queue.c><queue.c> \r
+OPTFFF 2,8,1,0,0,34,51,0,<..\..\Source\portable\RVDS\ARM7_LPC21xx\port.c><port.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,232,255,255,255,88,0,0,0,92,0,0,0,171,3,0,0,107,2,0,0 }\r
+OPTFFF 2,9,1,0,0,1,1,0,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,0,0,0,0,0,0,0,101,3,0,0,206,1,0,0 }\r
+OPTFFF 2,10,2,50331650,0,24,48,0,<.\serial\serialISRE.s><serialISRE.s> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,22,0,0,0,23,0,0,0,123,3,0,0,229,1,0,0 }\r
+OPTFFF 2,11,2,0,0,1,1,0,<..\..\Source\portable\RVDS\ARM7_LPC21xx\portASM.s><portASM.s> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,44,0,0,0,46,0,0,0,145,3,0,0,252,1,0,0 }\r
+OPTFFF 3,12,1,0,0,0,0,0,<..\Common\Minimal\flash.c><flash.c> \r
+OPTFFF 3,13,1,0,0,0,0,0,<..\Common\Minimal\integer.c><integer.c> \r
+OPTFFF 3,14,1,0,0,0,0,0,<..\Common\Minimal\comtest.c><comtest.c> \r
+\r
+ExtF <C:\E\Dev\FreeRTOS\WorkingCopy2\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h> 28,49,0,{ 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,66,0,0,0,69,0,0,0,167,3,0,0,19,2,0,0 }\r
+\r
+TARGOPT 1, (RTOSDemo)\r
+ ADSCLK=12000000\r
+ OPTTT 1,1,1,0\r
+ OPTHX 1,65535,0,0,0\r
+ OPTLX 79,66,8,<.\>\r
+ OPTOX 16\r
+ OPTLT 1,1,1,0,1,1,0,1,0,0,0,0\r
+ OPTXL 1,1,1,1,1,1,1,0,0\r
+ OPTFL 1,0,1\r
+ OPTAX 8\r
+ OPTBL 0,(Data Sheet)<DATASHTS\PHILIPS\LPC2119_2129.PDF>\r
+ OPTBL 1,(User Manual)<DATASHTS\PHILIPS\user_manual_LPC2119_2129_2194_2292_2294.PDF>\r
+ OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)\r
+ OPTDBG 48125,0,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()\r
+ OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))\r
+ OPTKEY 0,(ARMDBGFLAGS)(-T5F)\r
+ OPTBB 0,0,203,1,8560,0,0,0,0,1,<port.c>()()\r
+ OPTDF 0x86\r
+ OPTLE <>\r
+ OPTLC <>\r
+EndOpt\r
+\r
--- /dev/null
+Dependencies for Project 'RTOSDemo', Target 'Target 1': (DO NOT MODIFY !)\r
+F (.\Startup.s)(0x47F4A5D0)(--device DARMP -g --apcs=interwork -I "C:\Devtools\Keil305_2\ARM\INC\Philips" --list "Startup.lst" --xref -o "Startup.o")\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+Target (RTOSDemo), 0x0004 // Tools: 'ARM-ADS'\r
+\r
+Group (Other)\r
+Group (FreeRTOS)\r
+Group (Stadard Demo)\r
+\r
+File 1,2,<.\Startup.s><Startup.s>\r
+File 1,1,<.\ParTest\ParTest.c><ParTest.c>\r
+File 1,1,<.\main.c><main.c>\r
+File 1,1,<.\serial\serial.c><serial.c>\r
+File 2,1,<..\..\Source\tasks.c><tasks.c>\r
+File 2,1,<..\..\Source\list.c><list.c>\r
+File 2,1,<..\..\Source\queue.c><queue.c>\r
+File 2,1,<..\..\Source\portable\RVDS\ARM7_LPC21xx\port.c><port.c>\r
+File 2,1,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c>\r
+File 2,2,<.\serial\serialISRE.s><serialISRE.s>\r
+File 2,2,<..\..\Source\portable\RVDS\ARM7_LPC21xx\portASM.s><portASM.s>\r
+File 3,1,<..\Common\Minimal\flash.c><flash.c>\r
+File 3,1,<..\Common\Minimal\integer.c><integer.c>\r
+File 3,1,<..\Common\Minimal\comtest.c><comtest.c>\r
+\r
+\r
+Options 1,0,0 // Target 'RTOSDemo'\r
+ Device (LPC2129)\r
+ Vendor (NXP (founded by Philips))\r
+ Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI))\r
+ FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1))\r
+ StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code"))\r
+ FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000))\r
+ DevID (3648)\r
+ Rgf (LPC21xx.H)\r
+ Mem ()\r
+ C ()\r
+ A ()\r
+ RL ()\r
+ OH ()\r
+ DBC_IFX ()\r
+ DBC_CMS ()\r
+ DBC_AMS ()\r
+ DBC_LMS ()\r
+ UseEnv=0\r
+ EnvBin ()\r
+ EnvInc ()\r
+ EnvLib ()\r
+ EnvReg (ÿPhilips\)\r
+ OrgReg (ÿPhilips\)\r
+ TgStat=16\r
+ OutDir (.\)\r
+ OutName (RTOSDemo)\r
+ GenApp=1\r
+ GenLib=0\r
+ GenHex=0\r
+ Debug=1\r
+ Browse=1\r
+ LstDir (.\)\r
+ HexSel=1\r
+ MG32K=0\r
+ TGMORE=0\r
+ RunUsr 0 0 <>\r
+ RunUsr 1 0 <>\r
+ BrunUsr 0 0 <>\r
+ BrunUsr 1 0 <>\r
+ CrunUsr 0 0 <>\r
+ CrunUsr 1 0 <>\r
+ SVCSID <>\r
+ GLFLAGS=1790\r
+ ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ACPUTYP (ARM7TDMI)\r
+ RVDEV ()\r
+ ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ OCMADSIRAM { 0,0,0,0,64,0,64,0,0 }\r
+ OCMADSIROM { 1,0,0,0,0,0,0,4,0 }\r
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }\r
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0 }\r
+ RV_STAVEC ()\r
+ ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSCMISC ()\r
+ ADSCDEFN (ARM7_LPC21xx_KEIL_RVDS)\r
+ ADSCUDEF ()\r
+ ADSCINCD (.;..\..\Source\portable\RVDS\ARM7_LPC21xx;..\Common\include;..\..\Source\include)\r
+ ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSAMISC ()\r
+ ADSADEFN ()\r
+ ADSAUDEF ()\r
+ ADSAINCD (..\..\Source\portable\RVDS\ARM7_LPC21xx)\r
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ IncBld=1\r
+ AlwaysBuild=0\r
+ GenAsm=0\r
+ AsmAsm=0\r
+ PublicsOnly=0\r
+ StopCode=3\r
+ CustArgs ()\r
+ LibMods ()\r
+ ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSLDTA (0x00000000)\r
+ ADSLDDA (0x40000000)\r
+ ADSLDSC ()\r
+ ADSLDIB ()\r
+ ADSLDIC ()\r
+ ADSLDMC ()\r
+ ADSLDIF ()\r
+ ADSLDDW ()\r
+ OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)\r
+ OPTDBG 48125,0,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()\r
+ FLASH1 { 2,0,0,0,0,0,0,0,255,255,255,255,0,0,0,0,0,0,0,0 }\r
+ FLASH2 ()\r
+ FLASH3 (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1))\r
+ FLASH4 ()\r
+EndOpt\r
+\r
--- /dev/null
+;/*****************************************************************************/\r
+;/* STARTUP.S: Startup file for Philips LPC2000 */\r
+;/*****************************************************************************/\r
+;/* <<< Use Configuration Wizard in Context Menu >>> */ \r
+;/*****************************************************************************/\r
+;/* This file is part of the uVision/ARM development tools. */\r
+;/* Copyright (c) 2005-2007 Keil Software. All rights reserved. */\r
+;/* This software may only be used under the terms of a valid, current, */\r
+;/* end user licence from KEIL for a compatible version of KEIL software */\r
+;/* development tools. Nothing else gives you the right to use this software. */\r
+;/*****************************************************************************/\r
+\r
+\r
+;/*\r
+; * The STARTUP.S code is executed after CPU Reset. This file may be \r
+; * translated with the following SET symbols. In uVision these SET \r
+; * symbols are entered under Options - ASM - Define.\r
+; *\r
+; * REMAP: when set the startup code initializes the register MEMMAP \r
+; * which overwrites the settings of the CPU configuration pins. The \r
+; * startup and interrupt vectors are remapped from:\r
+; * 0x00000000 default setting (not remapped)\r
+; * 0x80000000 when EXTMEM_MODE is used\r
+; * 0x40000000 when RAM_MODE is used\r
+; *\r
+; * EXTMEM_MODE: when set the device is configured for code execution\r
+; * from external memory starting at address 0x80000000.\r
+; *\r
+; * RAM_MODE: when set the device is configured for code execution\r
+; * from on-chip RAM starting at address 0x40000000.\r
+; *\r
+; * EXTERNAL_MODE: when set the PIN2SEL values are written that enable\r
+; * the external BUS at startup.\r
+; */\r
+\r
+\r
+; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs\r
+\r
+Mode_USR EQU 0x10\r
+Mode_FIQ EQU 0x11\r
+Mode_IRQ EQU 0x12\r
+Mode_SVC EQU 0x13\r
+Mode_ABT EQU 0x17\r
+Mode_UND EQU 0x1B\r
+Mode_SYS EQU 0x1F\r
+\r
+I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled\r
+F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled\r
+\r
+\r
+;// <h> Stack Configuration (Stack Sizes in Bytes)\r
+;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>\r
+;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>\r
+;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>\r
+;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>\r
+;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>\r
+;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>\r
+;// </h>\r
+\r
+UND_Stack_Size EQU 0x00000008\r
+SVC_Stack_Size EQU 0x00000400\r
+ABT_Stack_Size EQU 0x00000008\r
+FIQ_Stack_Size EQU 0x00000008\r
+IRQ_Stack_Size EQU 0x00000400\r
+USR_Stack_Size EQU 0x00000008\r
+\r
+ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \\r
+ FIQ_Stack_Size + IRQ_Stack_Size)\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+\r
+Stack_Mem SPACE USR_Stack_Size\r
+__initial_sp SPACE ISR_Stack_Size\r
+\r
+Stack_Top\r
+\r
+\r
+;// <h> Heap Configuration\r
+;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>\r
+;// </h>\r
+\r
+Heap_Size EQU 0x00000000\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+\r
+; VPBDIV definitions\r
+VPBDIV EQU 0xE01FC100 ; VPBDIV Address\r
+\r
+;// <e> VPBDIV Setup\r
+;// <i> Peripheral Bus Clock Rate\r
+;// <o1.0..1> VPBDIV: VPB Clock\r
+;// <0=> VPB Clock = CPU Clock / 4\r
+;// <1=> VPB Clock = CPU Clock\r
+;// <2=> VPB Clock = CPU Clock / 2\r
+;// <o1.4..5> XCLKDIV: XCLK Pin\r
+;// <0=> XCLK Pin = CPU Clock / 4\r
+;// <1=> XCLK Pin = CPU Clock\r
+;// <2=> XCLK Pin = CPU Clock / 2\r
+;// </e>\r
+VPBDIV_SETUP EQU 0\r
+VPBDIV_Val EQU 0x00000000\r
+\r
+\r
+; Phase Locked Loop (PLL) definitions\r
+PLL_BASE EQU 0xE01FC080 ; PLL Base Address\r
+PLLCON_OFS EQU 0x00 ; PLL Control Offset\r
+PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset\r
+PLLSTAT_OFS EQU 0x08 ; PLL Status Offset\r
+PLLFEED_OFS EQU 0x0C ; PLL Feed Offset\r
+PLLCON_PLLE EQU (1<<0) ; PLL Enable\r
+PLLCON_PLLC EQU (1<<1) ; PLL Connect\r
+PLLCFG_MSEL EQU (0x1F<<0) ; PLL Multiplier\r
+PLLCFG_PSEL EQU (0x03<<5) ; PLL Divider\r
+PLLSTAT_PLOCK EQU (1<<10) ; PLL Lock Status\r
+\r
+;// <e> PLL Setup\r
+;// <o1.0..4> MSEL: PLL Multiplier Selection\r
+;// <1-32><#-1>\r
+;// <i> M Value\r
+;// <o1.5..6> PSEL: PLL Divider Selection\r
+;// <0=> 1 <1=> 2 <2=> 4 <3=> 8\r
+;// <i> P Value\r
+;// </e>\r
+PLL_SETUP EQU 1\r
+PLLCFG_Val EQU 0x00000024\r
+\r
+\r
+; Memory Accelerator Module (MAM) definitions\r
+MAM_BASE EQU 0xE01FC000 ; MAM Base Address\r
+MAMCR_OFS EQU 0x00 ; MAM Control Offset\r
+MAMTIM_OFS EQU 0x04 ; MAM Timing Offset\r
+\r
+;// <e> MAM Setup\r
+;// <o1.0..1> MAM Control\r
+;// <0=> Disabled\r
+;// <1=> Partially Enabled\r
+;// <2=> Fully Enabled\r
+;// <i> Mode\r
+;// <o2.0..2> MAM Timing\r
+;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3\r
+;// <4=> 4 <5=> 5 <6=> 6 <7=> 7\r
+;// <i> Fetch Cycles\r
+;// </e>\r
+MAM_SETUP EQU 1\r
+MAMCR_Val EQU 0x00000002\r
+MAMTIM_Val EQU 0x00000004\r
+\r
+\r
+; External Memory Controller (EMC) definitions\r
+EMC_BASE EQU 0xFFE00000 ; EMC Base Address\r
+BCFG0_OFS EQU 0x00 ; BCFG0 Offset\r
+BCFG1_OFS EQU 0x04 ; BCFG1 Offset\r
+BCFG2_OFS EQU 0x08 ; BCFG2 Offset\r
+BCFG3_OFS EQU 0x0C ; BCFG3 Offset\r
+\r
+;// <e> External Memory Controller (EMC)\r
+EMC_SETUP EQU 0\r
+\r
+;// <e> Bank Configuration 0 (BCFG0)\r
+;// <o1.0..3> IDCY: Idle Cycles <0-15>\r
+;// <o1.5..9> WST1: Wait States 1 <0-31>\r
+;// <o1.11..15> WST2: Wait States 2 <0-31>\r
+;// <o1.10> RBLE: Read Byte Lane Enable\r
+;// <o1.26> WP: Write Protect\r
+;// <o1.27> BM: Burst ROM\r
+;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit\r
+;// <2=> 32-bit <3=> Reserved\r
+;// </e>\r
+BCFG0_SETUP EQU 0\r
+BCFG0_Val EQU 0x0000FBEF\r
+\r
+;// <e> Bank Configuration 1 (BCFG1)\r
+;// <o1.0..3> IDCY: Idle Cycles <0-15>\r
+;// <o1.5..9> WST1: Wait States 1 <0-31>\r
+;// <o1.11..15> WST2: Wait States 2 <0-31>\r
+;// <o1.10> RBLE: Read Byte Lane Enable\r
+;// <o1.26> WP: Write Protect\r
+;// <o1.27> BM: Burst ROM\r
+;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit\r
+;// <2=> 32-bit <3=> Reserved\r
+;// </e>\r
+BCFG1_SETUP EQU 0\r
+BCFG1_Val EQU 0x0000FBEF\r
+\r
+;// <e> Bank Configuration 2 (BCFG2)\r
+;// <o1.0..3> IDCY: Idle Cycles <0-15>\r
+;// <o1.5..9> WST1: Wait States 1 <0-31>\r
+;// <o1.11..15> WST2: Wait States 2 <0-31>\r
+;// <o1.10> RBLE: Read Byte Lane Enable\r
+;// <o1.26> WP: Write Protect\r
+;// <o1.27> BM: Burst ROM\r
+;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit\r
+;// <2=> 32-bit <3=> Reserved\r
+;// </e>\r
+BCFG2_SETUP EQU 0\r
+BCFG2_Val EQU 0x0000FBEF\r
+\r
+;// <e> Bank Configuration 3 (BCFG3)\r
+;// <o1.0..3> IDCY: Idle Cycles <0-15>\r
+;// <o1.5..9> WST1: Wait States 1 <0-31>\r
+;// <o1.11..15> WST2: Wait States 2 <0-31>\r
+;// <o1.10> RBLE: Read Byte Lane Enable\r
+;// <o1.26> WP: Write Protect\r
+;// <o1.27> BM: Burst ROM\r
+;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit\r
+;// <2=> 32-bit <3=> Reserved\r
+;// </e>\r
+BCFG3_SETUP EQU 0\r
+BCFG3_Val EQU 0x0000FBEF\r
+\r
+;// </e> End of EMC\r
+\r
+\r
+; External Memory Pins definitions\r
+PINSEL2 EQU 0xE002C014 ; PINSEL2 Address\r
+PINSEL2_Val EQU 0x0E6149E4 ; CS0..3, OE, WE, BLS0..3, \r
+ ; D0..31, A2..23, JTAG Pins\r
+\r
+\r
+ PRESERVE8\r
+ \r
+\r
+; Area Definition and Entry Point\r
+; Startup Code must be linked first at Address at which it expects to run.\r
+\r
+ AREA RESET, CODE, READONLY\r
+ ARM\r
+\r
+\r
+; Exception Vectors\r
+; Mapped to Address 0.\r
+; Absolute addressing mode must be used.\r
+; Dummy Handlers are implemented as infinite loops which can be modified.\r
+ IMPORT vPortYieldProcessor\r
+\r
+Vectors LDR PC, Reset_Addr \r
+ LDR PC, Undef_Addr\r
+ LDR PC, SWI_Addr\r
+ LDR PC, PAbt_Addr\r
+ LDR PC, DAbt_Addr\r
+ NOP ; Reserved Vector \r
+; LDR PC, IRQ_Addr\r
+ LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr\r
+ LDR PC, FIQ_Addr\r
+\r
+Reset_Addr DCD Reset_Handler\r
+Undef_Addr DCD Undef_Handler\r
+SWI_Addr DCD vPortYieldProcessor\r
+PAbt_Addr DCD PAbt_Handler\r
+DAbt_Addr DCD DAbt_Handler\r
+ DCD 0 ; Reserved Address \r
+IRQ_Addr DCD IRQ_Handler\r
+FIQ_Addr DCD FIQ_Handler\r
+\r
+Undef_Handler B Undef_Handler\r
+SWI_Handler B SWI_Handler\r
+PAbt_Handler B PAbt_Handler\r
+DAbt_Handler B DAbt_Handler\r
+IRQ_Handler B IRQ_Handler\r
+FIQ_Handler B FIQ_Handler\r
+\r
+\r
+; Reset Handler\r
+\r
+ EXPORT Reset_Handler\r
+Reset_Handler \r
+\r
+\r
+; Setup External Memory Pins\r
+ IF :DEF:EXTERNAL_MODE\r
+ LDR R0, =PINSEL2\r
+ LDR R1, =PINSEL2_Val\r
+ STR R1, [R0]\r
+ ENDIF\r
+\r
+\r
+; Setup External Memory Controller\r
+ IF EMC_SETUP <> 0\r
+ LDR R0, =EMC_BASE\r
+\r
+ IF BCFG0_SETUP <> 0\r
+ LDR R1, =BCFG0_Val\r
+ STR R1, [R0, #BCFG0_OFS]\r
+ ENDIF\r
+\r
+ IF BCFG1_SETUP <> 0\r
+ LDR R1, =BCFG1_Val\r
+ STR R1, [R0, #BCFG1_OFS]\r
+ ENDIF\r
+\r
+ IF BCFG2_SETUP <> 0\r
+ LDR R1, =BCFG2_Val\r
+ STR R1, [R0, #BCFG2_OFS]\r
+ ENDIF\r
+\r
+ IF BCFG3_SETUP <> 0\r
+ LDR R1, =BCFG3_Val\r
+ STR R1, [R0, #BCFG3_OFS]\r
+ ENDIF\r
+\r
+ ENDIF ; EMC_SETUP\r
+\r
+\r
+; Setup VPBDIV\r
+ IF VPBDIV_SETUP <> 0\r
+ LDR R0, =VPBDIV\r
+ LDR R1, =VPBDIV_Val\r
+ STR R1, [R0]\r
+ ENDIF\r
+\r
+\r
+; Setup PLL\r
+ IF PLL_SETUP <> 0\r
+ LDR R0, =PLL_BASE\r
+ MOV R1, #0xAA\r
+ MOV R2, #0x55\r
+\r
+; Configure and Enable PLL\r
+ MOV R3, #PLLCFG_Val\r
+ STR R3, [R0, #PLLCFG_OFS] \r
+ MOV R3, #PLLCON_PLLE\r
+ STR R3, [R0, #PLLCON_OFS]\r
+ STR R1, [R0, #PLLFEED_OFS]\r
+ STR R2, [R0, #PLLFEED_OFS]\r
+\r
+; Wait until PLL Locked\r
+PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]\r
+ ANDS R3, R3, #PLLSTAT_PLOCK\r
+ BEQ PLL_Loop\r
+\r
+; Switch to PLL Clock\r
+ MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)\r
+ STR R3, [R0, #PLLCON_OFS]\r
+ STR R1, [R0, #PLLFEED_OFS]\r
+ STR R2, [R0, #PLLFEED_OFS]\r
+ ENDIF ; PLL_SETUP\r
+\r
+\r
+; Setup MAM\r
+ IF MAM_SETUP <> 0\r
+ LDR R0, =MAM_BASE\r
+ MOV R1, #MAMTIM_Val\r
+ STR R1, [R0, #MAMTIM_OFS] \r
+ MOV R1, #MAMCR_Val\r
+ STR R1, [R0, #MAMCR_OFS] \r
+ ENDIF ; MAM_SETUP\r
+\r
+\r
+; Memory Mapping (when Interrupt Vectors are in RAM)\r
+MEMMAP EQU 0xE01FC040 ; Memory Mapping Control\r
+ IF :DEF:REMAP\r
+ LDR R0, =MEMMAP\r
+ IF :DEF:EXTMEM_MODE\r
+ MOV R1, #3\r
+ ELIF :DEF:RAM_MODE\r
+ MOV R1, #2\r
+ ELSE\r
+ MOV R1, #1\r
+ ENDIF\r
+ STR R1, [R0]\r
+ ENDIF\r
+\r
+\r
+; Initialise Interrupt System\r
+; ...\r
+\r
+\r
+; Setup Stack for each mode\r
+\r
+ LDR R0, =Stack_Top\r
+\r
+; Enter Undefined Instruction Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #UND_Stack_Size\r
+\r
+; Enter Abort Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #ABT_Stack_Size\r
+\r
+; Enter FIQ Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #FIQ_Stack_Size\r
+\r
+; Enter IRQ Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #IRQ_Stack_Size\r
+\r
+; Enter Supervisor Mode and set its Stack Pointer\r
+ MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit\r
+ MOV SP, R0\r
+ SUB R0, R0, #SVC_Stack_Size\r
+\r
+; Enter the C code\r
+\r
+ IMPORT __main\r
+ LDR R0, =__main\r
+ BX R0\r
+\r
+\r
+ IF :DEF:__MICROLIB\r
+\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+\r
+ ELSE\r
+; User Initial Stack & Heap\r
+ AREA |.text|, CODE, READONLY\r
+\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + USR_Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+ ENDIF\r
+\r
+\r
+ END\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.4 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and \r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety \r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting, \r
+ licensing and training services.\r
+*/\r
+\r
+/* \r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used.\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the demo application tasks.\r
+ * \r
+ * Main.c also creates a task called "Check". This only executes every three \r
+ * seconds but has the highest priority so is guaranteed to get processor time. \r
+ * Its main function is to check that all the other tasks are still operational.\r
+ * Each task (other than the "flash" tasks) maintains a unique count that is \r
+ * incremented each time the task successfully completes its function. Should \r
+ * any error occur within such a task the count is permanently halted. The \r
+ * check task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have \r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles the onboard LED. Should any task contain an error at any time \r
+ * the LED toggle rate will change from 3 seconds to 500ms.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "integer.h"\r
+#include "comtest2.h"\r
+#include "serial.h"\r
+\r
+#ifdef KEIL_THUMB_INTERWORK\r
+\r
+ /* \r
+ THUMB mode allows more tasks to be created without the executable \r
+ binary exceeding the limits allowed by the evaluation version of \r
+ uVision3.\r
+ */\r
+ #include "PollQ.h"\r
+ #include "BlockQ.h"\r
+ #include "semtest.h"\r
+ #include "dynamic.h"\r
+\r
+#endif /* KEIL_THUMB_INTERWORK */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constants to setup I/O and processor. */\r
+#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 )\r
+#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 )\r
+#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 )\r
+#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 )\r
+\r
+/* Constants for the ComTest demo application tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )\r
+#define mainCOM_TEST_LED ( 3 )\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )\r
+\r
+/* Constants used by the "check" task. As described at the head of this file\r
+the check task toggles an LED. The rate at which the LED flashes is used to\r
+indicate whether an error has been detected or not. If the LED toggles every\r
+3 seconds then no errors have been detected. If the rate increases to 500ms\r
+then an error has been detected in at least one of the demo application tasks. */\r
+#define mainCHECK_LED ( 7 )\r
+#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Checks that all the demo application tasks are still executing without error\r
+ * - as described at the top of the file.\r
+ */\r
+static portLONG prvCheckOtherTasksAreStillRunning( void );\r
+\r
+/*\r
+ * The task that executes at the highest priority and calls \r
+ * prvCheckOtherTasksAreStillRunning(). See the description at the top\r
+ * of the file.\r
+ */\r
+static void vErrorChecks( void *pvParameters );\r
+\r
+/*\r
+ * Configure the processor for use with the Keil demo board. This is very\r
+ * minimal as most of the setup is managed by the settings in the project\r
+ * file.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+/*\r
+ * Application entry point:\r
+ * Starts all the other tasks, then starts the scheduler. \r
+ */\r
+int main( void )\r
+{\r
+ /* Setup the hardware for use with the Keil demo board. */\r
+ prvSetupHardware();\r
+\r
+ /* Start the demo/test application tasks. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+ vStartLEDFlashTasks( mainLED_TASK_PRIORITY );\r
+\r
+ #ifdef KEIL_THUMB_INTERWORK\r
+ /* When using THUMB mode we can start more tasks without the executable\r
+ exceeding the size limit imposed by the evaluation version of uVision3. */\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ #endif\r
+\r
+ /* Start the check task - which is defined in this file. This is the task\r
+ that periodically checks to see that all the other tasks are executing \r
+ without error. */\r
+ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Now all the tasks have been started - start the scheduler.\r
+\r
+ NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.\r
+ The processor MUST be in supervisor mode when vTaskStartScheduler is \r
+ called. The demo applications included in the FreeRTOS.org download switch\r
+ to supervisor mode prior to main being called. If you are not using one of\r
+ these demo application projects then ensure Supervisor mode is used here. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should never reach here! If you do then there was not enough heap\r
+ available for the idle task to be created. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;\r
+\r
+ /* Parameters are not used. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. If an error is detected then the delay period\r
+ is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so\r
+ the on board LED flash rate will increase.\r
+\r
+ This task runs at the highest priority. */\r
+\r
+ for( ;; )\r
+ {\r
+ /* The period of the delay depends on whether an error has been \r
+ detected or not. If an error has been detected then the period\r
+ is reduced to increase the LED flash rate. */\r
+ vTaskDelay( xDelayPeriod );\r
+\r
+ if( prvCheckOtherTasksAreStillRunning() != pdPASS )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash faster. */\r
+ xDelayPeriod = mainERROR_FLASH_PERIOD;\r
+ }\r
+\r
+ /* Toggle the LED before going back to wait for the next cycle. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Perform the hardware setup required. This is minimal as most of the\r
+ setup is managed by the settings in the project file. */\r
+\r
+ /* Configure the RS2332 pins. All other pins remain at their default of 0. */\r
+ PINSEL0 |= mainTX_ENABLE;\r
+ PINSEL0 |= mainRX_ENABLE;\r
+\r
+ /* LED pins need to be output. */\r
+ IODIR1 = mainLED_TO_OUTPUT;\r
+\r
+ /* Setup the peripheral bus to be the same as the PLL output. */\r
+ VPBDIV = mainBUS_CLK_FULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portLONG prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+portLONG lReturn = pdPASS;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none of them have detected\r
+ an error. */\r
+ if( xAreIntegerMathsTaskStillRunning() != pdPASS )\r
+ {\r
+ lReturn = pdFAIL;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdPASS )\r
+ {\r
+ lReturn = pdFAIL;\r
+ }\r
+\r
+ #ifdef KEIL_THUMB_INTERWORK\r
+\r
+ /* When using THUMB mode we can start more tasks without the executable\r
+ exceeding the size limit imposed by the evaluation version of uVision3. */\r
+ \r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = pdFAIL;\r
+ }\r
+ \r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = pdFAIL;\r
+ }\r
+ \r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = pdFAIL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ lReturn = pdFAIL;\r
+ }\r
+\r
+ #endif\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.4 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and \r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety \r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting, \r
+ licensing and training services.\r
+*/\r
+\r
+\r
+/* \r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. \r
+\r
+ Note this driver is used to test the FreeRTOS port. It is NOT intended to\r
+ be an example of an efficient implementation!\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Constants to setup and access the UART. */\r
+#define serDLAB ( ( unsigned portCHAR ) 0x80 )\r
+#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 )\r
+#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 )\r
+#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 )\r
+#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 )\r
+#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 )\r
+#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 )\r
+#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 )\r
+\r
+/* Constants to setup and access the VIC. */\r
+#define serU0VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 )\r
+#define serU0VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 )\r
+#define serU0VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )\r
+\r
+/* Misc. */\r
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )\r
+#define serHANDLE ( ( xComPortHandle ) 1 )\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/* Constant to access the VIC. */\r
+#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )\r
+\r
+/* Constants to determine the ISR source. */\r
+#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 )\r
+#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c )\r
+#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 )\r
+#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 )\r
+#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The asm wrapper for the interrupt service routine.\r
+ */\r
+extern void vUART_ISREntry(void);\r
+\r
+/* \r
+ * The C function called from the asm wrapper. \r
+ */\r
+void vUART_ISRHandler( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Queues used to hold received characters, and characters waiting to be\r
+transmitted. */\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+\r
+/* Communication flag between the interrupt service routine and serial API. */\r
+static volatile portLONG lTHREEmpty;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+unsigned portLONG ulDivisor, ulWantedClock;\r
+xComPortHandle xReturn = serHANDLE;\r
+\r
+ /* Create the queues used to hold Rx and Tx characters. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ /* Initialise the THRE empty flag. */\r
+ lTHREEmpty = pdTRUE;\r
+\r
+ if( \r
+ ( xRxedChars != serINVALID_QUEUE ) && \r
+ ( xCharsForTx != serINVALID_QUEUE ) && \r
+ ( ulWantedBaud != ( unsigned portLONG ) 0 ) \r
+ )\r
+ {\r
+ portENTER_CRITICAL()\r
+ {\r
+ /* Setup the baud rate: Calculate the divisor value. */\r
+ ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;\r
+ ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;\r
+\r
+ /* Set the DLAB bit so we can access the divisor. */\r
+ U0LCR |= serDLAB;\r
+\r
+ /* Setup the divisor. */\r
+ U0DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );\r
+ ulDivisor >>= 8;\r
+ U0DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );\r
+\r
+ /* Turn on the FIFO's and clear the buffers. */\r
+ U0FCR = ( serFIFO_ON | serCLEAR_FIFO );\r
+\r
+ /* Setup transmission format. */\r
+ U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;\r
+\r
+ /* Setup the VIC for the UART. */\r
+ VICIntSelect &= ~( serU0VIC_CHANNEL_BIT );\r
+ VICIntEnable |= serU0VIC_CHANNEL_BIT;\r
+ VICVectAddr1 = ( unsigned portLONG ) vUART_ISREntry;\r
+ VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE;\r
+\r
+ /* Enable UART0 interrupts. */\r
+ U0IER |= serENABLE_INTERRUPTS;\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ xReturn = ( xComPortHandle ) 0;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+signed portCHAR *pxNext;\r
+\r
+ /* NOTE: This implementation does not handle the queue being full as no\r
+ block time is used! */\r
+\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+ ( void ) usStringLength;\r
+\r
+ /* Send each character in the string, one at a time. */\r
+ pxNext = ( signed portCHAR * ) pcString;\r
+ while( *pxNext )\r
+ {\r
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+ pxNext++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* The port handle is not required as this driver only supports UART0. */\r
+ ( void ) pxPort;\r
+\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Is there space to write directly to the UART? */\r
+ if( lTHREEmpty == ( portLONG ) pdTRUE )\r
+ {\r
+ /* We wrote the character directly to the UART, so was \r
+ successful. */\r
+ lTHREEmpty = pdFALSE;\r
+ U0THR = cOutChar;\r
+ xReturn = pdPASS;\r
+ }\r
+ else \r
+ {\r
+ /* We cannot write directly to the UART, so queue the character.\r
+ Block for a maximum of xBlockTime if there is no space in the\r
+ queue. It is ok to block within a critical section as each\r
+ task has it's own critical section management. */\r
+ xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );\r
+\r
+ /* Depending on queue sizing and task prioritisation: While we \r
+ were blocked waiting to post interrupts were not disabled. It is \r
+ possible that the serial ISR has emptied the Tx queue, in which\r
+ case we need to start the Tx off again. */\r
+ if( lTHREEmpty == ( portLONG ) pdTRUE )\r
+ {\r
+ xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );\r
+ lTHREEmpty = pdFALSE;\r
+ U0THR = cOutChar;\r
+ }\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUART_ISRHandler( void )\r
+{\r
+signed portCHAR cChar;\r
+portBASE_TYPE xTaskWokenByRx, xTaskWokenByTx;\r
+\r
+ xTaskWokenByTx = pdFALSE;\r
+ xTaskWokenByRx = pdFALSE;\r
+\r
+ /* What caused the interrupt? */\r
+ switch( U0IIR & serINTERRUPT_SOURCE_MASK )\r
+ {\r
+ case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */\r
+ cChar = U0LSR;\r
+ break;\r
+\r
+ case serSOURCE_THRE : /* The THRE is empty. If there is another\r
+ character in the Tx queue, send it now. */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )\r
+ {\r
+ U0THR = cChar;\r
+ }\r
+ else\r
+ {\r
+ /* There are no further characters \r
+ queued to send so we can indicate \r
+ that the THRE is available. */\r
+ lTHREEmpty = pdTRUE;\r
+ }\r
+ break;\r
+\r
+ case serSOURCE_RX_TIMEOUT :\r
+ case serSOURCE_RX : /* A character was received. Place it in \r
+ the queue of received characters. */\r
+ cChar = U0RBR;\r
+ if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )\r
+ {\r
+ xTaskWokenByRx = pdTRUE;\r
+ }\r
+ break;\r
+\r
+ default : /* There is nothing to do, leave the ISR. */\r
+ break;\r
+ }\r
+\r
+ /* Clear the ISR in the VIC. */\r
+ VICVectAddr = serCLEAR_VIC_INTERRUPT;\r
+\r
+ /* Exit the ISR. If a task was woken by either a character being received\r
+ or transmitted then a context switch will occur. */\r
+ portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+ \r
--- /dev/null
+;/*\r
+; FreeRTOS.org V5.0.4 - Copyright (C) 2003-2008 Richard Barry.\r
+;\r
+; This file is part of the FreeRTOS.org distribution.\r
+;\r
+; FreeRTOS.org is free software; you can redistribute it and/or modify\r
+; it under the terms of the GNU General Public License as published by\r
+; the Free Software Foundation; either version 2 of the License, or\r
+; (at your option) any later version.\r
+; \r
+; FreeRTOS.org is distributed in the hope that it will be useful,\r
+; but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+; GNU General Public License for more details.\r
+;\r
+; You should have received a copy of the GNU General Public License\r
+; along with FreeRTOS.org; if not, write to the Free Software\r
+; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+;\r
+; A special exception to the GPL can be applied should you wish to distribute\r
+; a combined work that includes FreeRTOS.org, without being obliged to provide\r
+; the source code for any proprietary components. See the licensing section \r
+; of http://www.FreeRTOS.org for full details of how and when the exception\r
+; can be applied.\r
+;\r
+; ***************************************************************************\r
+; ***************************************************************************\r
+; * *\r
+; * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+; * and even write all or part of your application on your behalf. *\r
+; * See http://www.OpenRTOS.com for details of the services we provide to *\r
+; * expedite your project. *\r
+; * *\r
+; ***************************************************************************\r
+; ***************************************************************************\r
+;\r
+; Please ensure to read the configuration and relevant port sections of the\r
+; online documentation.\r
+;\r
+; http://www.FreeRTOS.org - Documentation, latest information, license and \r
+; contact details.\r
+;\r
+; http://www.SafeRTOS.com - A version that is certified for use in safety \r
+; critical systems.\r
+;\r
+; http://www.OpenRTOS.com - Commercial support, development, porting, \r
+; licensing and training services.\r
+;*/ \r
+ \r
+ INCLUDE portmacro.inc\r
+ \r
+ ;The UART interrupt entry point is defined within an assembly wrapper\r
+ ;within this file. This takes care of the task context saving before it\r
+ ;calls the main handler (vUART_ISRHandler()) which is written in C within\r
+ ;serial.c. The execution of the handler can unblock tasks that were blocked\r
+ ;waiting for UART events. Once the handler completes the asm wrapper \r
+ ;finishes off by restoring the context of whichever task is now selected to \r
+ ;enter the RUNNING state (which might now be a different task to that which\r
+ ;was originally interrupted.\r
+ IMPORT vUART_ISRHandler\r
+ EXPORT vUART_ISREntry\r
+\r
+ ;/* Interrupt entry must always be in ARM mode. */\r
+ AREA |.text|, CODE, READONLY\r
+ ARM\r
+ PRESERVE8\r
+\r
+\r
+\r
+vUART_ISREntry\r
+\r
+ ; Save the context of the interrupted task.\r
+ portSAVE_CONTEXT \r
+\r
+ ; Call the C handler function - defined within serial.c.\r
+ LDR R0, =vUART_ISRHandler\r
+ MOV LR, PC \r
+ BX R0\r
+\r
+ ; Finish off by restoring the context of the task that has been chosen to \r
+ ; run next - which might be a different task to that which was originally\r
+ ; interrupted.\r
+ portRESTORE_CONTEXT\r
+\r
+ END\r
projects / freertos / commitdiff