Add additional memory barriers into ARM GCC asm code to ensure no re-ordering across...

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2487 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
index 3933d277f013b6fec11c7efc2ee3ceace8505c44..1bacd3fbc3a313652e42fc4660e2ad9e4e7274c2 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
@@ -448,7 +448,7 @@ void FreeRTOS_Tick_Handler( void )
        {\r
                uint32_t ulMaskBits;\r
 \r
-               __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) );\r
+               __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) :: "memory" );\r
                configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );\r
        }\r
        #endif /* configASSERT_DEFINED */\r
@@ -460,7 +460,7 @@ void FreeRTOS_Tick_Handler( void )
        updated. */\r
        portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
        __asm volatile (        "dsb sy         \n"\r
-                                               "isb sy         \n" );\r
+                                               "isb sy         \n" ::: "memory" );\r
 \r
        /* Ok to enable interrupts after the interrupt source has been cleared. */\r
        configCLEAR_TICK_INTERRUPT();\r
@@ -514,7 +514,7 @@ uint32_t ulReturn;
                ulReturn = pdFALSE;\r
                portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
                __asm volatile (        "dsb sy         \n"\r
-                                                       "isb sy         \n" );\r
+                                                       "isb sy         \n" ::: "memory" );\r
        }\r
        portENABLE_INTERRUPTS();\r
 \r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
index 5c7af61e9526920176d43b442de373638d7180ca..78aed1e4824333bde15774dd648a9c1fa3f9d14d 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
@@ -129,9 +129,9 @@ extern uint64_t ullPortYieldRequired;                       \
 \r
 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
 #if defined( GUEST )\r
-       #define portYIELD() __asm volatile ( "SVC 0" )\r
+       #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" )\r
 #else\r
-       #define portYIELD() __asm volatile ( "SMC 0" )\r
+       #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )\r
 #endif\r
 /*-----------------------------------------------------------\r
  * Critical section control\r
@@ -144,12 +144,12 @@ extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
 extern void vPortInstallFreeRTOSVectorTable( void );\r
 \r
 #define portDISABLE_INTERRUPTS()                                                                       \\r
-       __asm volatile ( "MSR DAIFSET, #2" );                                                   \\r
+       __asm volatile ( "MSR DAIFSET, #2" ::: "memory" );                              \\r
        __asm volatile ( "DSB SY" );                                                                    \\r
        __asm volatile ( "ISB SY" );\r
 \r
 #define portENABLE_INTERRUPTS()                                                                                \\r
-       __asm volatile ( "MSR DAIFCLR, #2" );                                                   \\r
+       __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" );                              \\r
        __asm volatile ( "DSB SY" );                                                                    \\r
        __asm volatile ( "ISB SY" );\r
 \r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c b/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c
index 4447dcbacd13a916d640f48d04d7ec6f1fbcb1ba..90e626e79e4624cda475898c1c2a4986031bce31 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c
@@ -156,12 +156,12 @@ mode. */
 determined priority level.  Sometimes it is necessary to turn interrupt off in\r
 the CPU itself before modifying certain hardware registers. */\r
 #define portCPU_IRQ_DISABLE()                                                                          \\r
-       __asm volatile ( "CPSID i" );                                                                   \\r
+       __asm volatile ( "CPSID i" ::: "memory" );                                              \\r
        __asm volatile ( "DSB" );                                                                               \\r
        __asm volatile ( "ISB" );\r
 \r
 #define portCPU_IRQ_ENABLE()                                                                           \\r
-       __asm volatile ( "CPSIE i" );                                                                   \\r
+       __asm volatile ( "CPSIE i" ::: "memory" );                                              \\r
        __asm volatile ( "DSB" );                                                                               \\r
        __asm volatile ( "ISB" );\r
 \r
@@ -209,18 +209,18 @@ static void prvTaskExitError( void );
 /*\r
  * If the application provides an implementation of vApplicationIRQHandler(),\r
  * then it will get called directly without saving the FPU registers on\r
- * interrupt entry, and this weak implementation of \r
+ * interrupt entry, and this weak implementation of\r
  * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -\r
  * it should never actually get called so its implementation contains a\r
  * call to configASSERT() that will always fail.\r
  *\r
- * If the application provides its own implementation of \r
- * vApplicationFPUSafeIRQHandler() then the implementation of \r
+ * If the application provides its own implementation of\r
+ * vApplicationFPUSafeIRQHandler() then the implementation of\r
  * vApplicationIRQHandler() provided in portASM.S will save the FPU registers\r
  * before calling it.\r
  *\r
  * Therefore, if the application writer wants FPU registers to be saved on\r
- * interrupt entry their IRQ handler must be called \r
+ * interrupt entry their IRQ handler must be called\r
  * vApplicationFPUSafeIRQHandler(), and if the application writer does not want\r
  * FPU registers to be saved on interrupt entry their IRQ handler must be\r
  * called vApplicationIRQHandler().\r
@@ -344,7 +344,7 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
                #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.\r
        }\r
        #endif\r
-       \r
+\r
        return pxTopOfStack;\r
 }\r
 /*-----------------------------------------------------------*/\r
@@ -404,7 +404,7 @@ uint32_t ulAPSR;
 \r
        /* Only continue if the CPU is not in User mode.  The CPU must be in a\r
        Privileged mode for the scheduler to start. */\r
-       __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );\r
+       __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );\r
        ulAPSR &= portAPSR_MODE_BITS_MASK;\r
        configASSERT( ulAPSR != portAPSR_USER_MODE );\r
 \r
@@ -501,7 +501,7 @@ void FreeRTOS_Tick_Handler( void )
        portCPU_IRQ_DISABLE();\r
        portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
        __asm volatile (        "dsb            \n"\r
-                                               "isb            \n" );\r
+                                               "isb            \n" ::: "memory" );\r
        portCPU_IRQ_ENABLE();\r
 \r
        /* Increment the RTOS tick. */\r
@@ -527,7 +527,7 @@ void FreeRTOS_Tick_Handler( void )
                ulPortTaskHasFPUContext = pdTRUE;\r
 \r
                /* Initialise the floating point status register. */\r
-               __asm volatile ( "FMXR  FPSCR, %0" :: "r" (ulInitialFPSCR) );\r
+               __asm volatile ( "FMXR  FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );\r
        }\r
 \r
 #endif /* configUSE_TASK_FPU_SUPPORT */\r
@@ -559,7 +559,7 @@ uint32_t ulReturn;
                ulReturn = pdFALSE;\r
                portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
                __asm volatile (        "dsb            \n"\r
-                                                       "isb            \n" );\r
+                                                       "isb            \n" ::: "memory" );\r
        }\r
        portCPU_IRQ_ENABLE();\r
 \r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h
index 11b058d4c5754ac36426d0fd1c232bd54ff96f54..36b6562b7db27f78777ff31b195446bb712313dc 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h
@@ -127,7 +127,7 @@ extern uint32_t ulPortYieldRequired;                        \
 }\r
 \r
 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
-#define portYIELD() __asm volatile ( "SWI 0" );\r
+#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );\r
 \r
 \r
 /*-----------------------------------------------------------\r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
index b70a49af20a58a2eccc145cb6f4b92c5ca034284..559883f5805a3120c65ddb99628adad7d6e4b9e0 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
@@ -79,15 +79,15 @@
 #define portNVIC_SYSTICK_CTRL                  ( ( volatile uint32_t * ) 0xe000e010 )\r
 #define portNVIC_SYSTICK_LOAD                  ( ( volatile uint32_t * ) 0xe000e014 )\r
 #define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
-#define portNVIC_INT_CTRL                      ( ( volatile uint32_t *) 0xe000ed04 )\r
-#define portNVIC_SYSPRI2                       ( ( volatile uint32_t *) 0xe000ed20 )\r
-#define portNVIC_SYSTICK_CLK           0x00000004\r
-#define portNVIC_SYSTICK_INT           0x00000002\r
-#define portNVIC_SYSTICK_ENABLE                0x00000001\r
-#define portNVIC_PENDSVSET                     0x10000000\r
-#define portMIN_INTERRUPT_PRIORITY     ( 255UL )\r
-#define portNVIC_PENDSV_PRI                    ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
-#define portNVIC_SYSTICK_PRI           ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+#define portNVIC_INT_CTRL                              ( ( volatile uint32_t *) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2                               ( ( volatile uint32_t *) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK                   0x00000004\r
+#define portNVIC_SYSTICK_INT                   0x00000002\r
+#define portNVIC_SYSTICK_ENABLE                        0x00000001\r
+#define portNVIC_PENDSVSET                             0x10000000\r
+#define portMIN_INTERRUPT_PRIORITY             ( 255UL )\r
+#define portNVIC_PENDSV_PRI                            ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI                   ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
 \r
 /* Constants required to set up the initial stack. */\r
 #define portINITIAL_XPSR                       ( 0x01000000 )\r
@@ -243,7 +243,7 @@ void vPortYield( void )
 \r
        /* Barriers are normally not required but do ensure the code is completely\r
        within the specified behaviour for the architecture. */\r
-       __asm volatile( "dsb" );\r
+       __asm volatile( "dsb" ::: "memory" );\r
        __asm volatile( "isb" );\r
 }\r
 /*-----------------------------------------------------------*/\r
@@ -252,7 +252,7 @@ void vPortEnterCritical( void )
 {\r
     portDISABLE_INTERRUPTS();\r
     uxCriticalNesting++;\r
-       __asm volatile( "dsb" );\r
+       __asm volatile( "dsb" ::: "memory" );\r
        __asm volatile( "isb" );\r
 }\r
 /*-----------------------------------------------------------*/\r
@@ -274,6 +274,7 @@ uint32_t ulSetInterruptMaskFromISR( void )
                                        " mrs r0, PRIMASK       \n"\r
                                        " cpsid i                       \n"\r
                                        " bx lr                           "\r
+                                       ::: "memory"\r
                                  );\r
 \r
        /* To avoid compiler warnings.  This line will never be reached. */\r
@@ -286,6 +287,7 @@ void vClearInterruptMaskFromISR( uint32_t ulMask )
        __asm volatile(\r
                                        " msr PRIMASK, r0       \n"\r
                                        " bx lr                           "\r
+                                       ::: "memory"\r
                                  );\r
 \r
        /* Just to avoid compiler warning. */\r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
index f6eb71f94ae9bb4d89775c7635073019af8c33f1..81537783c9006fb8fcab9ecc98da27edfba79a11 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
@@ -136,8 +136,8 @@ extern void vClearInterruptMaskFromISR( uint32_t ulMask )  __attribute__((naked)
 \r
 #define portSET_INTERRUPT_MASK_FROM_ISR()              ulSetInterruptMaskFromISR()\r
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)   vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS()                               __asm volatile  ( " cpsid i " )\r
-#define portENABLE_INTERRUPTS()                                        __asm volatile  ( " cpsie i " )\r
+#define portDISABLE_INTERRUPTS()                               __asm volatile  ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS()                                        __asm volatile  ( " cpsie i " ::: "memory" )\r
 #define portENTER_CRITICAL()                                   vPortEnterCritical()\r
 #define portEXIT_CRITICAL()                                            vPortExitCritical()\r
 \r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
index f61ce66ea94c92817216cc0131098abeaf33d875..ba512f0b42ce9b8c35bca32440f68a27de7d0dce 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
@@ -436,7 +436,7 @@ void xPortPendSVHandler( void )
        "       mov r0, #0                                                      \n"\r
        "       msr basepri, r0                                         \n"\r
        "       ldmia sp!, {r3, r14}                            \n"\r
-       "                                                                               \n"     /* Restore the context, including the critical nesting count. */\r
+       "                                                                               \n" /* Restore the context, including the critical nesting count. */\r
        "       ldr r1, [r3]                                            \n"\r
        "       ldr r0, [r1]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
        "       ldmia r0!, {r4-r11}                                     \n" /* Pop the registers. */\r
@@ -501,7 +501,7 @@ void xPortSysTickHandler( void )
 \r
                /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
                method as that will mask interrupts that should exit sleep mode. */\r
-               __asm volatile( "cpsid i" );\r
+               __asm volatile( "cpsid i" ::: "memory" );\r
                __asm volatile( "dsb" );\r
                __asm volatile( "isb" );\r
 \r
@@ -522,7 +522,7 @@ void xPortSysTickHandler( void )
 \r
                        /* Re-enable interrupts - see comments above the cpsid instruction()\r
                        above. */\r
-                       __asm volatile( "cpsie i" );\r
+                       __asm volatile( "cpsie i" ::: "memory" );\r
                }\r
                else\r
                {\r
@@ -545,7 +545,7 @@ void xPortSysTickHandler( void )
                        configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
                        if( xModifiableIdleTime > 0 )\r
                        {\r
-                               __asm volatile( "dsb" );\r
+                               __asm volatile( "dsb" ::: "memory" );\r
                                __asm volatile( "wfi" );\r
                                __asm volatile( "isb" );\r
                        }\r
@@ -553,10 +553,10 @@ void xPortSysTickHandler( void )
 \r
                        /* Re-enable interrupts - see comments above the cpsid instruction()\r
                        above. */\r
-                       __asm volatile( "cpsie i" );\r
-                       \r
-                       /* Disable the SysTick clock without reading the \r
-                       portNVIC_SYSTICK_CTRL_REG register to ensure the \r
+                       __asm volatile( "cpsie i" ::: "memory" );\r
+\r
+                       /* Disable the SysTick clock without reading the\r
+                       portNVIC_SYSTICK_CTRL_REG register to ensure the\r
                        portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. */\r
                        portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );\r
 \r
@@ -661,7 +661,7 @@ __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
        uint8_t ucCurrentPriority;\r
 \r
                /* Obtain the number of the currently executing interrupt. */\r
-               __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+               __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
 \r
                /* Is the interrupt number a user defined interrupt? */\r
                if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
index 34a4cb5d7c150399fba7a0a3d736b10079a12ab7..7d9cedb02e47be375bf45f9952b47a9f9acb46c3 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
@@ -125,7 +125,7 @@ typedef unsigned long UBaseType_t;
                                                                                                                                                                \\r
        /* Barriers are normally not required but do ensure the code is completely      \\r
        within the specified behaviour for the architecture. */                                         \\r
-       __asm volatile( "dsb" );                                                                                                        \\r
+       __asm volatile( "dsb" ::: "memory" );                                                                           \\r
        __asm volatile( "isb" );                                                                                                        \\r
 }\r
 \r
@@ -173,7 +173,7 @@ not necessary for to use this port.  They are defined so the common demo files
        {\r
        uint8_t ucReturn;\r
 \r
-               __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );\r
+               __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );\r
                return ucReturn;\r
        }\r
 \r
@@ -214,7 +214,7 @@ uint32_t ulCurrentInterrupt;
 BaseType_t xReturn;\r
 \r
        /* Obtain the number of the currently executing interrupt. */\r
-       __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+       __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
 \r
        if( ulCurrentInterrupt == 0 )\r
        {\r
@@ -236,11 +236,11 @@ uint32_t ulNewBASEPRI;
 \r
        __asm volatile\r
        (\r
-               "       mov %0, %1                                                                                              \n"     \\r
+               "       mov %0, %1                                                                                              \n" \\r
                "       msr basepri, %0                                                                                 \n" \\r
                "       isb                                                                                                             \n" \\r
                "       dsb                                                                                                             \n" \\r
-               :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+               :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
        );\r
 }\r
 \r
@@ -253,11 +253,11 @@ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
        __asm volatile\r
        (\r
                "       mrs %0, basepri                                                                                 \n" \\r
-               "       mov %1, %2                                                                                              \n"     \\r
+               "       mov %1, %2                                                                                              \n" \\r
                "       msr basepri, %1                                                                                 \n" \\r
                "       isb                                                                                                             \n" \\r
                "       dsb                                                                                                             \n" \\r
-               :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+               :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
        );\r
 \r
        /* This return will not be reached but is necessary to prevent compiler\r
@@ -270,7 +270,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 {\r
        __asm volatile\r
        (\r
-               "       msr basepri, %0 " :: "r" ( ulNewMaskValue )\r
+               "       msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"\r
        );\r
 }\r
 /*-----------------------------------------------------------*/\r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
index bf589c0ab6122685322c2b73463583ee0fdb0ea6..1813e4ee591578f7f67d9463fd09a9a1ee290177 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -132,7 +132,7 @@ typedef unsigned long UBaseType_t;
 #define portNUM_CONFIGURABLE_REGIONS           ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
 #define portTOTAL_NUM_REGIONS                          ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
 \r
-#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " :::"r0" )\r
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )\r
 \r
 typedef struct MPU_REGION_REGISTERS\r
 {\r
@@ -159,7 +159,7 @@ typedef struct MPU_SETTINGS
 \r
 /* Scheduler utilities. */\r
 \r
-#define portYIELD()                            __asm volatile ( "      SVC     %0      \n" :: "i" (portSVC_YIELD) )\r
+#define portYIELD()                            __asm volatile ( "      SVC     %0      \n" :: "i" (portSVC_YIELD) : "memory" )\r
 #define portYIELD_WITHIN_API()                                                                                                         \\r
 {                                                                                                                                                              \\r
        /* Set a PendSV to request a context switch. */                                                         \\r
@@ -167,7 +167,7 @@ typedef struct MPU_SETTINGS
                                                                                                                                                                \\r
        /* Barriers are normally not required but do ensure the code is completely      \\r
        within the specified behaviour for the architecture. */                                         \\r
-       __asm volatile( "dsb" );                                                                                                        \\r
+       __asm volatile( "dsb" ::: "memory" );                                                                           \\r
        __asm volatile( "isb" );                                                                                                        \\r
 }\r
 \r
@@ -208,7 +208,7 @@ not necessary for to use this port.  They are defined so the common demo files
        {\r
        uint8_t ucReturn;\r
 \r
-               __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );\r
+               __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );\r
                return ucReturn;\r
        }\r
 \r
@@ -251,7 +251,7 @@ portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged
                __asm volatile ( " mrs r0, control      \n" \\r
                                                 " orr r0, #1           \n" \\r
                                                 " msr control, r0      \n"     \\r
-                                                :::"r0" );\r
+                                                :::"r0", "memory" );\r
        }\r
 }\r
 /*-----------------------------------------------------------*/\r
@@ -262,7 +262,7 @@ uint32_t ulCurrentInterrupt;
 BaseType_t xReturn;\r
 \r
        /* Obtain the number of the currently executing interrupt. */\r
-       __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+       __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
 \r
        if( ulCurrentInterrupt == 0 )\r
        {\r
@@ -288,7 +288,7 @@ uint32_t ulNewBASEPRI;
                "       msr basepri, %0                                                                                 \n" \\r
                "       isb                                                                                                             \n" \\r
                "       dsb                                                                                                             \n" \\r
-               :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+               :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
        );\r
 }\r
 \r
@@ -305,7 +305,7 @@ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
                "       msr basepri, %1                                                                                 \n" \\r
                "       isb                                                                                                             \n" \\r
                "       dsb                                                                                                             \n" \\r
-               :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+               :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
        );\r
 \r
        /* This return will not be reached but is necessary to prevent compiler\r
@@ -318,7 +318,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 {\r
        __asm volatile\r
        (\r
-               "       msr basepri, %0 " :: "r" ( ulNewMaskValue )\r
+               "       msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"\r
        );\r
 }\r
 /*-----------------------------------------------------------*/\r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
index 75f8f22d3c1c4aabba2bfe31c69da6a23197f6c2..54cb9a754b9bc3c28ce4876bb8351b741f229cf3 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
@@ -563,7 +563,7 @@ void xPortSysTickHandler( void )
 \r
                /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
                method as that will mask interrupts that should exit sleep mode. */\r
-               __asm volatile( "cpsid i" );\r
+               __asm volatile( "cpsid i" ::: "memory" );\r
                __asm volatile( "dsb" );\r
                __asm volatile( "isb" );\r
 \r
@@ -584,7 +584,7 @@ void xPortSysTickHandler( void )
 \r
                        /* Re-enable interrupts - see comments above the cpsid instruction()\r
                        above. */\r
-                       __asm volatile( "cpsie i" );\r
+                       __asm volatile( "cpsie i" ::: "memory" );\r
                }\r
                else\r
                {\r
@@ -607,7 +607,7 @@ void xPortSysTickHandler( void )
                        configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
                        if( xModifiableIdleTime > 0 )\r
                        {\r
-                               __asm volatile( "dsb" );\r
+                               __asm volatile( "dsb" ::: "memory" );\r
                                __asm volatile( "wfi" );\r
                                __asm volatile( "isb" );\r
                        }\r
@@ -622,7 +622,7 @@ void xPortSysTickHandler( void )
 \r
                        /* Re-enable interrupts - see comments above the cpsid instruction()\r
                        above. */\r
-                       __asm volatile( "cpsie i" );\r
+                       __asm volatile( "cpsie i" ::: "memory" );\r
 \r
                        if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
                        {\r
@@ -735,7 +735,7 @@ static void vPortEnableVFP( void )
        uint8_t ucCurrentPriority;\r
 \r
                /* Obtain the number of the currently executing interrupt. */\r
-               __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+               __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
 \r
                /* Is the interrupt number a user defined interrupt? */\r
                if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
index 34a4cb5d7c150399fba7a0a3d736b10079a12ab7..8aca22292bfc2a8fce8e46223a02b671cc68945d 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
@@ -125,7 +125,7 @@ typedef unsigned long UBaseType_t;
                                                                                                                                                                \\r
        /* Barriers are normally not required but do ensure the code is completely      \\r
        within the specified behaviour for the architecture. */                                         \\r
-       __asm volatile( "dsb" );                                                                                                        \\r
+       __asm volatile( "dsb" ::: "memory" );                                                                           \\r
        __asm volatile( "isb" );                                                                                                        \\r
 }\r
 \r
@@ -173,7 +173,7 @@ not necessary for to use this port.  They are defined so the common demo files
        {\r
        uint8_t ucReturn;\r
 \r
-               __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );\r
+               __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );\r
                return ucReturn;\r
        }\r
 \r
@@ -214,7 +214,7 @@ uint32_t ulCurrentInterrupt;
 BaseType_t xReturn;\r
 \r
        /* Obtain the number of the currently executing interrupt. */\r
-       __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+       __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
 \r
        if( ulCurrentInterrupt == 0 )\r
        {\r
@@ -240,7 +240,7 @@ uint32_t ulNewBASEPRI;
                "       msr basepri, %0                                                                                 \n" \\r
                "       isb                                                                                                             \n" \\r
                "       dsb                                                                                                             \n" \\r
-               :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+               :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
        );\r
 }\r
 \r
@@ -257,7 +257,7 @@ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
                "       msr basepri, %1                                                                                 \n" \\r
                "       isb                                                                                                             \n" \\r
                "       dsb                                                                                                             \n" \\r
-               :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+               :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
        );\r
 \r
        /* This return will not be reached but is necessary to prevent compiler\r
@@ -270,7 +270,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 {\r
        __asm volatile\r
        (\r
-               "       msr basepri, %0 " :: "r" ( ulNewMaskValue )\r
+               "       msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"\r
        );\r
 }\r
 /*-----------------------------------------------------------*/\r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
index bf589c0ab6122685322c2b73463583ee0fdb0ea6..1813e4ee591578f7f67d9463fd09a9a1ee290177 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -132,7 +132,7 @@ typedef unsigned long UBaseType_t;
 #define portNUM_CONFIGURABLE_REGIONS           ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
 #define portTOTAL_NUM_REGIONS                          ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
 \r
-#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " :::"r0" )\r
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )\r
 \r
 typedef struct MPU_REGION_REGISTERS\r
 {\r
@@ -159,7 +159,7 @@ typedef struct MPU_SETTINGS
 \r
 /* Scheduler utilities. */\r
 \r
-#define portYIELD()                            __asm volatile ( "      SVC     %0      \n" :: "i" (portSVC_YIELD) )\r
+#define portYIELD()                            __asm volatile ( "      SVC     %0      \n" :: "i" (portSVC_YIELD) : "memory" )\r
 #define portYIELD_WITHIN_API()                                                                                                         \\r
 {                                                                                                                                                              \\r
        /* Set a PendSV to request a context switch. */                                                         \\r
@@ -167,7 +167,7 @@ typedef struct MPU_SETTINGS
                                                                                                                                                                \\r
        /* Barriers are normally not required but do ensure the code is completely      \\r
        within the specified behaviour for the architecture. */                                         \\r
-       __asm volatile( "dsb" );                                                                                                        \\r
+       __asm volatile( "dsb" ::: "memory" );                                                                           \\r
        __asm volatile( "isb" );                                                                                                        \\r
 }\r
 \r
@@ -208,7 +208,7 @@ not necessary for to use this port.  They are defined so the common demo files
        {\r
        uint8_t ucReturn;\r
 \r
-               __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );\r
+               __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );\r
                return ucReturn;\r
        }\r
 \r
@@ -251,7 +251,7 @@ portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged
                __asm volatile ( " mrs r0, control      \n" \\r
                                                 " orr r0, #1           \n" \\r
                                                 " msr control, r0      \n"     \\r
-                                                :::"r0" );\r
+                                                :::"r0", "memory" );\r
        }\r
 }\r
 /*-----------------------------------------------------------*/\r
@@ -262,7 +262,7 @@ uint32_t ulCurrentInterrupt;
 BaseType_t xReturn;\r
 \r
        /* Obtain the number of the currently executing interrupt. */\r
-       __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+       __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
 \r
        if( ulCurrentInterrupt == 0 )\r
        {\r
@@ -288,7 +288,7 @@ uint32_t ulNewBASEPRI;
                "       msr basepri, %0                                                                                 \n" \\r
                "       isb                                                                                                             \n" \\r
                "       dsb                                                                                                             \n" \\r
-               :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+               :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
        );\r
 }\r
 \r
@@ -305,7 +305,7 @@ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
                "       msr basepri, %1                                                                                 \n" \\r
                "       isb                                                                                                             \n" \\r
                "       dsb                                                                                                             \n" \\r
-               :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+               :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
        );\r
 \r
        /* This return will not be reached but is necessary to prevent compiler\r
@@ -318,7 +318,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 {\r
        __asm volatile\r
        (\r
-               "       msr basepri, %0 " :: "r" ( ulNewMaskValue )\r
+               "       msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"\r
        );\r
 }\r
 /*-----------------------------------------------------------*/\r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
index 0a8f2d24ece5abe781ab37393d0152759faf224b..132333daa1c73ce1f7f98612d209e2a5959f6c6b 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
@@ -553,7 +553,7 @@ void xPortSysTickHandler( void )
 \r
                /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
                method as that will mask interrupts that should exit sleep mode. */\r
-               __asm volatile( "cpsid i" );\r
+               __asm volatile( "cpsid i" ::: "memory" );\r
                __asm volatile( "dsb" );\r
                __asm volatile( "isb" );\r
 \r
@@ -574,7 +574,7 @@ void xPortSysTickHandler( void )
 \r
                        /* Re-enable interrupts - see comments above the cpsid instruction()\r
                        above. */\r
-                       __asm volatile( "cpsie i" );\r
+                       __asm volatile( "cpsie i" ::: "memory" );\r
                }\r
                else\r
                {\r
@@ -597,7 +597,7 @@ void xPortSysTickHandler( void )
                        configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
                        if( xModifiableIdleTime > 0 )\r
                        {\r
-                               __asm volatile( "dsb" );\r
+                               __asm volatile( "dsb" ::: "memory" );\r
                                __asm volatile( "wfi" );\r
                                __asm volatile( "isb" );\r
                        }\r
@@ -612,7 +612,7 @@ void xPortSysTickHandler( void )
 \r
                        /* Re-enable interrupts - see comments above the cpsid instruction()\r
                        above. */\r
-                       __asm volatile( "cpsie i" );\r
+                       __asm volatile( "cpsie i" ::: "memory" );\r
 \r
                        if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
                        {\r
@@ -725,7 +725,7 @@ static void vPortEnableVFP( void )
        uint8_t ucCurrentPriority;\r
 \r
                /* Obtain the number of the currently executing interrupt. */\r
-               __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+               __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
 \r
                /* Is the interrupt number a user defined interrupt? */\r
                if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
index 30b0081fafb19b1c4875441ab50e58b28d39d943..3b9a9e4a21c5b8c22dccbc5a53c295f482668c3d 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
@@ -125,7 +125,7 @@ typedef unsigned long UBaseType_t;
                                                                                                                                                                \\r
        /* Barriers are normally not required but do ensure the code is completely      \\r
        within the specified behaviour for the architecture. */                                         \\r
-       __asm volatile( "dsb" );                                                                                                        \\r
+       __asm volatile( "dsb" ::: "memory" );                                                                           \\r
        __asm volatile( "isb" );                                                                                                        \\r
 }\r
 \r
@@ -173,7 +173,7 @@ not necessary for to use this port.  They are defined so the common demo files
        {\r
        uint8_t ucReturn;\r
 \r
-               __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );\r
+               __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );\r
                return ucReturn;\r
        }\r
 \r
@@ -214,7 +214,7 @@ uint32_t ulCurrentInterrupt;
 BaseType_t xReturn;\r
 \r
        /* Obtain the number of the currently executing interrupt. */\r
-       __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+       __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
 \r
        if( ulCurrentInterrupt == 0 )\r
        {\r
@@ -242,7 +242,7 @@ uint32_t ulNewBASEPRI;
                "       isb                                                                                                             \n" \\r
                "       dsb                                                                                                             \n" \\r
                "       cpsie i                                                                                                 \n" \\r
-               :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+               :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
        );\r
 }\r
 \r
@@ -261,7 +261,7 @@ uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
                "       isb                                                                                                             \n" \\r
                "       dsb                                                                                                             \n" \\r
                "       cpsie i                                                                                                 \n" \\r
-               :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+               :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
        );\r
 \r
        /* This return will not be reached but is necessary to prevent compiler\r
@@ -274,7 +274,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 {\r
        __asm volatile\r
        (\r
-               "       msr basepri, %0 " :: "r" ( ulNewMaskValue )\r
+               "       msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"\r
        );\r
 }\r
 /*-----------------------------------------------------------*/\r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c b/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
index 82c4d2711de02b014f407bb842281e5e798ea89d..351d42203d80bff80b667f74ec508ab2e6a273ce 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
@@ -156,12 +156,12 @@ mode. */
 determined priority level.  Sometimes it is necessary to turn interrupt off in\r
 the CPU itself before modifying certain hardware registers. */\r
 #define portCPU_IRQ_DISABLE()                                                                          \\r
-       __asm volatile ( "CPSID i" );                                                                   \\r
+       __asm volatile ( "CPSID i" ::: "memory" );                                              \\r
        __asm volatile ( "DSB" );                                                                               \\r
        __asm volatile ( "ISB" );\r
 \r
 #define portCPU_IRQ_ENABLE()                                                                           \\r
-       __asm volatile ( "CPSIE i" );                                                                   \\r
+       __asm volatile ( "CPSIE i" ::: "memory" );                                              \\r
        __asm volatile ( "DSB" );                                                                               \\r
        __asm volatile ( "ISB" );\r
 \r
@@ -171,8 +171,8 @@ the CPU itself before modifying certain hardware registers. */
 {                                                                                                                                      \\r
        portCPU_IRQ_DISABLE();                                                                                  \\r
        portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;                   \\r
-       __asm(  "DSB            \n"                                                                                     \\r
-                       "ISB            \n" );                                                                          \\r
+       __asm volatile (        "DSB            \n"                                                             \\r
+                                               "ISB            \n" );                                                  \\r
        portCPU_IRQ_ENABLE();                                                                                   \\r
 }\r
 \r
@@ -367,7 +367,7 @@ uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */
 \r
        /* Only continue if the CPU is not in User mode.  The CPU must be in a\r
        Privileged mode for the scheduler to start. */\r
-       __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );\r
+       __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );\r
        ulAPSR &= portAPSR_MODE_BITS_MASK;\r
        configASSERT( ulAPSR != portAPSR_USER_MODE );\r
 \r
@@ -464,7 +464,7 @@ void FreeRTOS_Tick_Handler( void )
        portCPU_IRQ_DISABLE();\r
        portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
        __asm volatile (        "dsb            \n"\r
-                                               "isb            \n" );\r
+                                               "isb            \n" ::: "memory" );\r
        portCPU_IRQ_ENABLE();\r
 \r
        /* Increment the RTOS tick. */\r
@@ -488,7 +488,7 @@ uint32_t ulInitialFPSCR = 0;
        ulPortTaskHasFPUContext = pdTRUE;\r
 \r
        /* Initialise the floating point status register. */\r
-       __asm volatile ( "FMXR  FPSCR, %0" :: "r" (ulInitialFPSCR) );\r
+       __asm volatile ( "FMXR  FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -518,7 +518,7 @@ uint32_t ulReturn;
                ulReturn = pdFALSE;\r
                portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
                __asm volatile (        "dsb            \n"\r
-                                                       "isb            \n" );\r
+                                                       "isb            \n" ::: "memory" );\r
        }\r
        portCPU_IRQ_ENABLE();\r
 \r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h
index be745514096a7ae1481d5e6f8193864c3d391441..08ac40756e456c6628169fa2c08c4a26e6c36197 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h
@@ -123,7 +123,7 @@ extern uint32_t ulPortYieldRequired;                        \
 }\r
 \r
 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
-#define portYIELD() __asm volatile ( "SWI 0" );\r
+#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );\r
 \r
 \r
 /*-----------------------------------------------------------\r