--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file misc.c\r
+ * @author MCD Application Team\r
+ * @version V3.0.0\r
+ * @date 04/06/2009\r
+ * @brief This file provides all the miscellaneous firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "misc.h"\r
+\r
+/** @addtogroup StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MISC \r
+ * @brief MISC driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MISC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup MISC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the priority grouping: pre-emption priority and \r
+ * subpriority.\r
+ * @param NVIC_PriorityGroup: specifies the priority grouping bits length. \r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority\r
+ * 4 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority\r
+ * 0 bits for subpriority\r
+ * @retval : None\r
+ */\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r
+ \r
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the NVIC peripheral according to the specified\r
+ * parameters in the NVIC_InitStruct.\r
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure\r
+ * that contains the configuration information for the\r
+ * specified NVIC peripheral.\r
+ * @retval : None\r
+ */\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
+{\r
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); \r
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r
+ \r
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
+ {\r
+ /* Compute the Corresponding IRQ Priority --------------------------------*/ \r
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;\r
+ tmppre = (0x4 - tmppriority);\r
+ tmpsub = tmpsub >> tmppriority;\r
+\r
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;\r
+ tmppriority = tmppriority << 0x04;\r
+ \r
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;\r
+ \r
+ /* Enable the Selected IRQ Channels --------------------------------------*/\r
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Selected IRQ Channels -------------------------------------*/\r
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the vector table location and Offset.\r
+ * @param NVIC_VectTab: specifies if the vector table is in RAM or\r
+ * FLASH memory.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_VectTab_RAM\r
+ * @arg NVIC_VectTab_FLASH\r
+ * @param Offset: Vector Table base offset field. \r
+ * This value must be a multiple of 0x100.\r
+ * @retval : None\r
+ */\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));\r
+ assert_param(IS_NVIC_OFFSET(Offset)); \r
+ \r
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);\r
+}\r
+\r
+/**\r
+ * @brief Selects the condition for the system to enter low power mode.\r
+ * @param LowPowerMode: Specifies the new mode for the system to enter\r
+ * low power mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_LP_SEVONPEND\r
+ * @arg NVIC_LP_SLEEPDEEP\r
+ * @arg NVIC_LP_SLEEPONEXIT\r
+ * @param NewState: new state of LP condition.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval : None\r
+ */\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_LP(LowPowerMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ SCB->SCR |= LowPowerMode;\r
+ }\r
+ else\r
+ {\r
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the SysTick clock source.\r
+ * @param SysTick_CLKSource: specifies the SysTick clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8\r
+ * selected as SysTick clock source.\r
+ * @arg SysTick_CLKSource_HCLK: AHB clock selected as\r
+ * SysTick clock source.\r
+ * @retval : None\r
+ */\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
+ {\r
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_crc.c\r
+ * @author MCD Application Team\r
+ * @version V3.0.0\r
+ * @date 04/06/2009\r
+ * @brief This file provides all the CRC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_crc.h"\r
+\r
+/** @addtogroup StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC \r
+ * @brief CRC driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* CR register bit mask */\r
+\r
+#define CR_RESET_Set ((uint32_t)0x00000001)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the CRC Data register (DR).\r
+ * @param None\r
+ * @retval : None\r
+ */\r
+void CRC_ResetDR(void)\r
+{\r
+ /* Reset CRC generator */\r
+ CRC->CR = CR_RESET_Set;\r
+}\r
+\r
+/**\r
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).\r
+ * @param Data: data word(32-bit) to compute its CRC\r
+ * @retval : 32-bit CRC\r
+ */\r
+uint32_t CRC_CalcCRC(uint32_t Data)\r
+{\r
+ CRC->DR = Data;\r
+ \r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).\r
+ * @param pBuffer: pointer to the buffer containing the data to be \r
+ * computed\r
+ * @param BufferLength: length of the buffer to be computed \r
+ * @retval : 32-bit CRC\r
+ */\r
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)\r
+{\r
+ uint32_t index = 0;\r
+ \r
+ for(index = 0; index < BufferLength; index++)\r
+ {\r
+ CRC->DR = pBuffer[index];\r
+ }\r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Returns the current CRC value.\r
+ * @param None\r
+ * @retval : 32-bit CRC\r
+ */\r
+uint32_t CRC_GetCRC(void)\r
+{\r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.\r
+ * @param IDValue: 8-bit value to be stored in the ID register \r
+ * @retval : None\r
+ */\r
+void CRC_SetIDRegister(uint8_t IDValue)\r
+{\r
+ CRC->IDR = IDValue;\r
+}\r
+\r
+/**\r
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register\r
+ * @param None\r
+ * @retval : 8-bit value of the ID register \r
+ */\r
+uint8_t CRC_GetIDRegister(void)\r
+{\r
+ return (CRC->IDR);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dac.c\r
+ * @author MCD Application Team\r
+ * @version V3.0.0\r
+ * @date 04/06/2009\r
+ * @brief This file provides all the DAC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_dac.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC \r
+ * @brief DAC driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup DAC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* DAC EN mask */\r
+#define CR_EN_Set ((uint32_t)0x00000001)\r
+\r
+/* DAC DMAEN mask */\r
+#define CR_DMAEN_Set ((uint32_t)0x00001000)\r
+\r
+/* CR register Mask */\r
+#define CR_CLEAR_Mask ((uint32_t)0x00000FFE)\r
+\r
+/* DAC SWTRIG mask */\r
+#define SWTRIGR_SWTRIG_Set ((uint32_t)0x00000001)\r
+\r
+/* DAC Dual Channels SWTRIG masks */\r
+#define DUAL_SWTRIG_Set ((uint32_t)0x00000003)\r
+#define DUAL_SWTRIG_Reset ((uint32_t)0xFFFFFFFC)\r
+\r
+/* DHR registers offsets */\r
+#define DHR12R1_Offset ((uint32_t)0x00000008)\r
+#define DHR12R2_Offset ((uint32_t)0x00000014)\r
+#define DHR12RD_Offset ((uint32_t)0x00000020)\r
+\r
+/* DOR register offset */\r
+#define DOR_Offset ((uint32_t)0x0000002C)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the DAC peripheral registers to their default\r
+ * reset values.\r
+ * @param None\r
+ * @retval : None\r
+ */\r
+void DAC_DeInit(void)\r
+{\r
+ /* Enable DAC reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);\r
+ /* Release DAC from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DAC peripheral according to the specified \r
+ * parameters in the DAC_InitStruct.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that\r
+ * contains the configuration information for the specified\r
+ * DAC channel.\r
+ * @retval : None\r
+ */\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+ /* Check the DAC parameters */\r
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));\r
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));\r
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));\r
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));\r
+/*---------------------------- DAC CR Configuration --------------------------*/\r
+ /* Get the DAC CR value */\r
+ tmpreg1 = DAC->CR;\r
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */\r
+ tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel);\r
+ /* Configure for the selected DAC channel: buffer output, trigger, wave genration,\r
+ mask/amplitude for wave genration */\r
+ /* Set TSELx and TENx bits according to DAC_Trigger value */\r
+ /* Set WAVEx bits according to DAC_WaveGeneration value */\r
+ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ \r
+ /* Set BOFFx bit according to DAC_OutputBuffer value */ \r
+ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |\r
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);\r
+ /* Calculate CR register value depending on DAC_Channel */\r
+ tmpreg1 |= tmpreg2 << DAC_Channel;\r
+ /* Write to DAC CR */\r
+ DAC->CR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Fills each DAC_InitStruct member with its default value.\r
+ * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure\r
+ * which will be initialized.\r
+ * @retval : None\r
+ */\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+/*--------------- Reset DAC init structure parameters values -----------------*/\r
+ /* Initialize the DAC_Trigger member */\r
+ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;\r
+ /* Initialize the DAC_WaveGeneration member */\r
+ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;\r
+ /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */\r
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;\r
+ /* Initialize the DAC_OutputBuffer member */\r
+ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the DAC channel. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval : None\r
+ */\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel */\r
+ DAC->CR |= CR_EN_Set << DAC_Channel;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel */\r
+ DAC->CR &= ~(CR_EN_Set << DAC_Channel);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel DMA request.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the selected DAC channel DMA request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval : None\r
+ */\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel DMA request */\r
+ DAC->CR |= CR_DMAEN_Set << DAC_Channel;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel DMA request */\r
+ DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel software trigger.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the selected DAC channel software trigger.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval : None\r
+ */\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4);\r
+ }\r
+ else\r
+ {\r
+ /* Disable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables simultaneously the two DAC channels software\r
+ * triggers.\r
+ * @param NewState: new state of the DAC channels software triggers.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval : None\r
+ */\r
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable software trigger for both DAC channels */\r
+ DAC->SWTRIGR |= DUAL_SWTRIG_Set ;\r
+ }\r
+ else\r
+ {\r
+ /* Disable software trigger for both DAC channels */\r
+ DAC->SWTRIGR &= DUAL_SWTRIG_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel wave generation.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_Wave: Specifies the wave type to enable or disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Wave_Noise: noise wave generation\r
+ * @arg DAC_Wave_Triangle: triangle wave generation\r
+ * @param NewState: new state of the selected DAC channel wave generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval : None\r
+ */\r
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_WAVE(DAC_Wave)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected wave generation for the selected DAC channel */\r
+ DAC->CR |= DAC_Wave << DAC_Channel;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected wave generation for the selected DAC channel */\r
+ DAC->CR &= ~(DAC_Wave << DAC_Channel);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel1.\r
+ * @param DAC_Align: Specifies the data alignement for DAC channel1.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
+ * @param Data : Data to be loaded in the selected data holding \r
+ * register.\r
+ * @retval : None\r
+ */\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ /* Set the DAC channel1 selected data holding register */\r
+ *((__IO uint32_t *)(DAC_BASE + DHR12R1_Offset + DAC_Align)) = (uint32_t)Data;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel2.\r
+ * @param DAC_Align: Specifies the data alignement for DAC channel2.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
+ * @param Data : Data to be loaded in the selected data holding \r
+ * register.\r
+ * @retval : None\r
+ */\r
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ /* Set the DAC channel2 selected data holding register */\r
+ *((__IO uint32_t *)(DAC_BASE + DHR12R2_Offset + DAC_Align)) = (uint32_t)Data;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for dual channel\r
+ * DAC.\r
+ * @param DAC_Align: Specifies the data alignement for dual channel DAC.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
+ * @param Data2: Data for DAC Channel2 to be loaded in the selected data \r
+ * holding register.\r
+ * @param Data1: Data for DAC Channel1 to be loaded in the selected data \r
+ * holding register.\r
+ * @retval : None\r
+ */\r
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)\r
+{\r
+ uint32_t data = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data1));\r
+ assert_param(IS_DAC_DATA(Data2));\r
+ \r
+ /* Calculate and set dual DAC data holding register value */\r
+ if (DAC_Align == DAC_Align_8b_R)\r
+ {\r
+ data = ((uint32_t)Data2 << 8) | Data1; \r
+ }\r
+ else\r
+ {\r
+ data = ((uint32_t)Data2 << 16) | Data1;\r
+ }\r
+ /* Set the dual DAC selected data holding register */\r
+ *((__IO uint32_t *)(DAC_BASE + DHR12RD_Offset + DAC_Align)) = data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the last data output value of the selected DAC cahnnel.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @retval : The selected DAC channel data output value.\r
+ */\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ /* Returns the DAC channel data output register value */\r
+ return (uint16_t) (*(__IO uint32_t*)(DAC_BASE + DOR_Offset + ((uint32_t)DAC_Channel >> 2)));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dbgmcu.c\r
+ * @author MCD Application Team\r
+ * @version V3.0.0\r
+ * @date 04/06/2009\r
+ * @brief This file provides all the DBGMCU firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_dbgmcu.h"\r
+\r
+/** @addtogroup StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DBGMCU \r
+ * @brief DBGMCU driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup DBGMCU_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Private_Defines\r
+ * @{\r
+ */\r
+\r
+#define IDCODE_DEVID_Mask ((uint32_t)0x00000FFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the device revision identifier.\r
+ * @param None\r
+ * @retval : Device revision identifier\r
+ */\r
+uint32_t DBGMCU_GetREVID(void)\r
+{\r
+ return(DBGMCU->IDCODE >> 16);\r
+}\r
+\r
+/**\r
+ * @brief Returns the device identifier.\r
+ * @param None\r
+ * @retval : Device identifier\r
+ */\r
+uint32_t DBGMCU_GetDEVID(void)\r
+{\r
+ return(DBGMCU->IDCODE & IDCODE_DEVID_Mask);\r
+}\r
+\r
+/**\r
+ * @brief Configures the specified peripheral and low power mode behavior\r
+ * when the MCU under Debug mode.\r
+ * @param DBGMCU_Periph: specifies the peripheral and low power mode.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode \r
+ * @arg DBGMCU_STOP: Keep debugger connection during STOP mode \r
+ * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode \r
+ * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted \r
+ * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted \r
+ * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted \r
+ * @arg DBGMCU_CAN1_STOP: Debug CAN 1 stopped when Core is halted \r
+ * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is \r
+ * halted\r
+ * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is \r
+ * halted\r
+ * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted \r
+ * @param NewState: new state of the specified peripheral in Debug mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval : None\r
+ */\r
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ DBGMCU->CR |= DBGMCU_Periph;\r
+ }\r
+ else\r
+ {\r
+ DBGMCU->CR &= ~DBGMCU_Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_flash.c\r
+ * @author MCD Application Team\r
+ * @version V3.0.0\r
+ * @date 04/06/2009\r
+ * @brief This file provides all the FLASH firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_flash.h"\r
+\r
+/** @addtogroup StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH \r
+ * @brief FLASH driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup FLASH_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Private_Defines\r
+ * @{\r
+ */ \r
+\r
+/* Flash Access Control Register bits */\r
+#define ACR_LATENCY_Mask ((uint32_t)0x00000038)\r
+#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)\r
+#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)\r
+\r
+/* Flash Access Control Register bits */\r
+#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) \r
+\r
+/* Flash Control Register bits */\r
+#define CR_PG_Set ((uint32_t)0x00000001)\r
+#define CR_PG_Reset ((uint32_t)0x00001FFE) \r
+#define CR_PER_Set ((uint32_t)0x00000002)\r
+#define CR_PER_Reset ((uint32_t)0x00001FFD)\r
+#define CR_MER_Set ((uint32_t)0x00000004)\r
+#define CR_MER_Reset ((uint32_t)0x00001FFB)\r
+#define CR_OPTPG_Set ((uint32_t)0x00000010)\r
+#define CR_OPTPG_Reset ((uint32_t)0x00001FEF)\r
+#define CR_OPTER_Set ((uint32_t)0x00000020)\r
+#define CR_OPTER_Reset ((uint32_t)0x00001FDF)\r
+#define CR_STRT_Set ((uint32_t)0x00000040)\r
+#define CR_LOCK_Set ((uint32_t)0x00000080)\r
+\r
+/* FLASH Mask */\r
+#define RDPRT_Mask ((uint32_t)0x00000002)\r
+#define WRP0_Mask ((uint32_t)0x000000FF)\r
+#define WRP1_Mask ((uint32_t)0x0000FF00)\r
+#define WRP2_Mask ((uint32_t)0x00FF0000)\r
+#define WRP3_Mask ((uint32_t)0xFF000000)\r
+\r
+/* FLASH Keys */\r
+#define RDP_Key ((uint16_t)0x00A5)\r
+#define FLASH_KEY1 ((uint32_t)0x45670123)\r
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)\r
+\r
+/* Delay definition */ \r
+#define EraseTimeout ((uint32_t)0x00000FFF)\r
+#define ProgramTimeout ((uint32_t)0x0000000F)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+static void delay(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the code latency value.\r
+ * @param FLASH_Latency: specifies the FLASH Latency value.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_Latency_0: FLASH Zero Latency cycle\r
+ * @arg FLASH_Latency_1: FLASH One Latency cycle\r
+ * @arg FLASH_Latency_2: FLASH Two Latency cycles\r
+ * @retval : None\r
+ */\r
+void FLASH_SetLatency(uint32_t FLASH_Latency)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));\r
+ \r
+ /* Read the ACR register */\r
+ tmpreg = FLASH->ACR; \r
+ \r
+ /* Sets the Latency value */\r
+ tmpreg &= ACR_LATENCY_Mask;\r
+ tmpreg |= FLASH_Latency;\r
+ \r
+ /* Write the ACR register */\r
+ FLASH->ACR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Half cycle flash access.\r
+ * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable\r
+ * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable\r
+ * @retval : None\r
+ */\r
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));\r
+ \r
+ /* Enable or disable the Half cycle access */\r
+ FLASH->ACR &= ACR_HLFCYA_Mask;\r
+ FLASH->ACR |= FLASH_HalfCycleAccess;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Prefetch Buffer.\r
+ * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable\r
+ * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable\r
+ * @retval : None\r
+ */\r
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));\r
+ \r
+ /* Enable or disable the Prefetch Buffer */\r
+ FLASH->ACR &= ACR_PRFTBE_Mask;\r
+ FLASH->ACR |= FLASH_PrefetchBuffer;\r
+}\r
+\r
+/**\r
+ * @brief Unlocks the FLASH Program Erase Controller.\r
+ * @param None\r
+ * @retval : None\r
+ */\r
+void FLASH_Unlock(void)\r
+{\r
+ /* Authorize the FPEC Access */\r
+ FLASH->KEYR = FLASH_KEY1;\r
+ FLASH->KEYR = FLASH_KEY2;\r
+}\r
+\r
+/**\r
+ * @brief Locks the FLASH Program Erase Controller.\r
+ * @param None\r
+ * @retval : None\r
+ */\r
+void FLASH_Lock(void)\r
+{\r
+ /* Set the Lock Bit to lock the FPEC and the FCR */\r
+ FLASH->CR |= CR_LOCK_Set;\r
+}\r
+\r
+/**\r
+ * @brief Erases a specified FLASH page.\r
+ * @param Page_Address: The page address to be erased.\r
+ * @retval : FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or \r
+ * FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Page_Address));\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* if the previous operation is completed, proceed to erase the page */\r
+ FLASH->CR|= CR_PER_Set;\r
+ FLASH->AR = Page_Address; \r
+ FLASH->CR|= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ if(status != FLASH_BUSY)\r
+ {\r
+ /* if the erase operation is completed, disable the PER Bit */\r
+ FLASH->CR &= CR_PER_Reset;\r
+ }\r
+ }\r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Erases all FLASH pages.\r
+ * @param None\r
+ * @retval : FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or \r
+ * FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_EraseAllPages(void)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to erase all pages */\r
+ FLASH->CR |= CR_MER_Set;\r
+ FLASH->CR |= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ if(status != FLASH_BUSY)\r
+ {\r
+ /* if the erase operation is completed, disable the MER Bit */\r
+ FLASH->CR &= CR_MER_Reset;\r
+ }\r
+ } \r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Erases the FLASH option bytes.\r
+ * @param None\r
+ * @retval : FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or \r
+ * FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_EraseOptionBytes(void)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Authorize the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ \r
+ /* if the previous operation is completed, proceed to erase the option bytes */\r
+ FLASH->CR |= CR_OPTER_Set;\r
+ FLASH->CR |= CR_STRT_Set;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the erase operation is completed, disable the OPTER Bit */\r
+ FLASH->CR &= CR_OPTER_Reset;\r
+ \r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= CR_OPTPG_Set;\r
+ /* Enable the readout access */\r
+ OB->RDP= RDP_Key; \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status != FLASH_BUSY)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (status != FLASH_BUSY)\r
+ {\r
+ /* Disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ } \r
+ }\r
+ /* Return the erase status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a word at a specified address.\r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval : FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or \r
+ * FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new first \r
+ half word */\r
+ FLASH->CR |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = (uint16_t)Data;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new second \r
+ half word */\r
+ *(__IO uint16_t*)(Address + 2) = Data >> 16;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status != FLASH_BUSY)\r
+ {\r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (status != FLASH_BUSY)\r
+ {\r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+ }\r
+ }\r
+ /* Return the Program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a half word at a specified address.\r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval : FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or \r
+ * FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = Data;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ if(status != FLASH_BUSY)\r
+ {\r
+ /* if the program operation is completed, disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+ } \r
+ /* Return the Program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a half word at a specified Option Byte Data address.\r
+ * @param Address: specifies the address to be programmed.\r
+ * This parameter can be 0x1FFFF804 or 0x1FFFF806. \r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval : FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or \r
+ * FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_DATA_ADDRESS(Address));\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Authorize the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ /* Enables the Option Bytes Programming operation */\r
+ FLASH->CR |= CR_OPTPG_Set; \r
+ *(__IO uint16_t*)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ if(status != FLASH_BUSY)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ } \r
+ /* Return the Option Byte Data Program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Write protects the desired pages\r
+ * @param FLASH_Pages: specifies the address of the pages to be \r
+ * write protected. This parameter can be:\r
+ * @arg For STM32F10Xxx Medium-density devices (FLASH page size equal to 1 KB)\r
+ * A value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages124to127\r
+ * @arg For STM32F10Xxx High-density devices (FLASH page size equal to 2 KB) \r
+ * A value between FLASH_WRProt_Pages0to1 and FLASH_WRProt_Pages60to61 \r
+ * or FLASH_WRProt_Pages62to255 \r
+ * @arg FLASH_WRProt_AllPages\r
+ * @retval : FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or \r
+ * FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)\r
+{\r
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;\r
+ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));\r
+ \r
+ FLASH_Pages = (uint32_t)(~FLASH_Pages);\r
+ WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);\r
+ WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);\r
+ WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);\r
+ WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Authorizes the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ FLASH->CR |= CR_OPTPG_Set;\r
+ if(WRP0_Data != 0xFF)\r
+ {\r
+ OB->WRP0 = WRP0_Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ }\r
+ if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))\r
+ {\r
+ OB->WRP1 = WRP1_Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ }\r
+ if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))\r
+ {\r
+ OB->WRP2 = WRP2_Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ }\r
+ \r
+ if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))\r
+ {\r
+ OB->WRP3 = WRP3_Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ }\r
+ \r
+ if(status != FLASH_BUSY)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ } \r
+ /* Return the write protection operation Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the read out protection.\r
+ * If the user has already programmed the other option bytes before \r
+ * calling this function, he must re-program them since this \r
+ * function erases all option bytes.\r
+ * @param Newstate: new state of the ReadOut Protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval : FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or \r
+ * FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Authorizes the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ FLASH->CR |= CR_OPTER_Set;\r
+ FLASH->CR |= CR_STRT_Set;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the erase operation is completed, disable the OPTER Bit */\r
+ FLASH->CR &= CR_OPTER_Reset;\r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= CR_OPTPG_Set; \r
+ if(NewState != DISABLE)\r
+ {\r
+ OB->RDP = 0x00;\r
+ }\r
+ else\r
+ {\r
+ OB->RDP = RDP_Key; \r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout); \r
+ \r
+ if(status != FLASH_BUSY)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ }\r
+ else \r
+ {\r
+ if(status != FLASH_BUSY)\r
+ {\r
+ /* Disable the OPTER Bit */\r
+ FLASH->CR &= CR_OPTER_Reset;\r
+ }\r
+ }\r
+ }\r
+ /* Return the protection operation Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP /\r
+ * RST_STDBY.\r
+ * @param OB_IWDG: Selects the IWDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_SW: Software IWDG selected\r
+ * @arg OB_IWDG_HW: Hardware IWDG selected\r
+ * @param OB_STOP: Reset event when entering STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STOP_NoRST: No reset generated when entering in STOP\r
+ * @arg OB_STOP_RST: Reset generated when entering in STOP\r
+ * @param OB_STDBY: Reset event when entering Standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY\r
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
+ * @retval : FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or \r
+ * FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE; \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));\r
+ assert_param(IS_OB_STOP_SOURCE(OB_STOP));\r
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));\r
+ /* Authorize the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= CR_OPTPG_Set; \r
+ \r
+ OB->USER = ( OB_IWDG | OB_STOP |OB_STDBY) | (uint16_t)0xF8; \r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ if(status != FLASH_BUSY)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ } \r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH User Option Bytes values.\r
+ * @param None\r
+ * @retval : The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)\r
+ * and RST_STDBY(Bit2).\r
+ */\r
+uint32_t FLASH_GetUserOptionByte(void)\r
+{\r
+ /* Return the User Option Byte */\r
+ return (uint32_t)(FLASH->OBR >> 2);\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Write Protection Option Bytes Register value.\r
+ * @param None\r
+ * @retval : The FLASH Write Protection Option Bytes Register value\r
+ */\r
+uint32_t FLASH_GetWriteProtectionOptionByte(void)\r
+{\r
+ /* Return the Falsh write protection Register value */\r
+ return (uint32_t)(FLASH->WRPR);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the FLASH Read Out Protection Status is set \r
+ * or not.\r
+ * @param None\r
+ * @retval : FLASH ReadOut Protection Status(SET or RESET)\r
+ */\r
+FlagStatus FLASH_GetReadOutProtectionStatus(void)\r
+{\r
+ FlagStatus readoutstatus = RESET;\r
+ if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)\r
+ {\r
+ readoutstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ readoutstatus = RESET;\r
+ }\r
+ return readoutstatus;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the FLASH Prefetch Buffer status is set or not.\r
+ * @param None\r
+ * @retval : FLASH Prefetch Buffer Status (SET or RESET).\r
+ */\r
+FlagStatus FLASH_GetPrefetchBufferStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */\r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified FLASH interrupts.\r
+ * @param FLASH_IT: specifies the FLASH interrupt sources to be \r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_IT_ERROR: FLASH Error Interrupt\r
+ * @arg FLASH_IT_EOP: FLASH end of operation Interrupt\r
+ * @param NewState: new state of the specified Flash interrupts.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval : None \r
+ */\r
+void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_IT(FLASH_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if(NewState != DISABLE)\r
+ {\r
+ /* Enable the interrupt sources */\r
+ FLASH->CR |= FLASH_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the interrupt sources */\r
+ FLASH->CR &= ~(uint32_t)FLASH_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified FLASH flag is set or not.\r
+ * @param FLASH_FLAG: specifies the FLASH flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_FLAG_BSY: FLASH Busy flag \r
+ * @arg FLASH_FLAG_PGERR: FLASH Program error flag \r
+ * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag \r
+ * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag \r
+ * @retval : The new state of FLASH_FLAG (SET or RESET).\r
+ */\r
+FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;\r
+ if(FLASH_FLAG == FLASH_FLAG_OPTERR) \r
+ {\r
+ if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ /* Return the new state of FLASH_FLAG (SET or RESET) */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the FLASH\92s pending flags.\r
+ * @param FLASH_FLAG: specifies the FLASH flags to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_FLAG_BSY: FLASH Busy flag \r
+ * @arg FLASH_FLAG_PGERR: FLASH Program error flag \r
+ * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag \r
+ * @retval : None\r
+ */\r
+void FLASH_ClearFlag(uint16_t FLASH_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;\r
+ \r
+ /* Clear the flags */\r
+ FLASH->SR = FLASH_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Status.\r
+ * @param None\r
+ * @retval : FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE\r
+ */\r
+FLASH_Status FLASH_GetStatus(void)\r
+{\r
+ FLASH_Status flashstatus = FLASH_COMPLETE;\r
+ \r
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
+ {\r
+ flashstatus = FLASH_BUSY;\r
+ }\r
+ else \r
+ { \r
+ if(FLASH->SR & FLASH_FLAG_PGERR)\r
+ { \r
+ flashstatus = FLASH_ERROR_PG;\r
+ }\r
+ else \r
+ {\r
+ if(FLASH->SR & FLASH_FLAG_WRPRTERR)\r
+ {\r
+ flashstatus = FLASH_ERROR_WRP;\r
+ }\r
+ else\r
+ {\r
+ flashstatus = FLASH_COMPLETE;\r
+ }\r
+ }\r
+ }\r
+ /* Return the Flash Status */\r
+ return flashstatus;\r
+}\r
+\r
+/**\r
+ * @brief Waits for a Flash operation to complete or a TIMEOUT to occur.\r
+ * @param Timeout: FLASH progamming Timeout\r
+ * @retval : FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or \r
+ * FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)\r
+{ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check for the Flash Status */\r
+ status = FLASH_GetStatus();\r
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */\r
+ while((status == FLASH_BUSY) && (Timeout != 0x00))\r
+ {\r
+ delay();\r
+ status = FLASH_GetStatus();\r
+ Timeout--;\r
+ }\r
+ if(Timeout == 0x00 )\r
+ {\r
+ status = FLASH_TIMEOUT;\r
+ }\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Inserts a time delay.\r
+ * @param None\r
+ * @retval : None\r
+ */\r
+static void delay(void)\r
+{\r
+ __IO uint32_t i = 0;\r
+ for(i = 0xFF; i != 0; i--)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_fsmc.c\r
+ * @author MCD Application Team\r
+ * @version V3.0.0\r
+ * @date 04/06/2009\r
+ * @brief This file provides all the FSMC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_fsmc.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC \r
+ * @brief FSMC driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup FSMC_Private_TypesDefinitions\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* --------------------- FSMC registers bit mask ---------------------------- */\r
+\r
+/* FSMC BCRx Mask */\r
+#define BCR_MBKEN_Set ((uint32_t)0x00000001)\r
+#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)\r
+#define BCR_FACCEN_Set ((uint32_t)0x00000040)\r
+\r
+/* FSMC PCRx Mask */\r
+#define PCR_PBKEN_Set ((uint32_t)0x00000004)\r
+#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)\r
+#define PCR_ECCEN_Set ((uint32_t)0x00000040)\r
+#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)\r
+#define PCR_MemoryType_NAND ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default \r
+ * reset values.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
+ * @retval : None\r
+ */\r
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
+ \r
+ /* FSMC_Bank1_NORSRAM1 */\r
+ if(FSMC_Bank == FSMC_Bank1_NORSRAM1)\r
+ {\r
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; \r
+ }\r
+ /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */\r
+ else\r
+ { \r
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; \r
+ }\r
+ FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;\r
+ FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; \r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the FSMC NAND Banks registers to their default \r
+ * reset values.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND \r
+ * @retval : None\r
+ */\r
+void FSMC_NANDDeInit(uint32_t FSMC_Bank)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ /* Set the FSMC_Bank2 registers to their reset values */\r
+ FSMC_Bank2->PCR2 = 0x00000018;\r
+ FSMC_Bank2->SR2 = 0x00000040;\r
+ FSMC_Bank2->PMEM2 = 0xFCFCFCFC;\r
+ FSMC_Bank2->PATT2 = 0xFCFCFCFC; \r
+ }\r
+ /* FSMC_Bank3_NAND */ \r
+ else\r
+ {\r
+ /* Set the FSMC_Bank3 registers to their reset values */\r
+ FSMC_Bank3->PCR3 = 0x00000018;\r
+ FSMC_Bank3->SR3 = 0x00000040;\r
+ FSMC_Bank3->PMEM3 = 0xFCFCFCFC;\r
+ FSMC_Bank3->PATT3 = 0xFCFCFCFC; \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the FSMC PCCARD Bank registers to their default \r
+ * reset values.\r
+ * @param None \r
+ * @retval : None\r
+ */\r
+void FSMC_PCCARDDeInit(void)\r
+{\r
+ /* Set the FSMC_Bank4 registers to their reset values */\r
+ FSMC_Bank4->PCR4 = 0x00000018; \r
+ FSMC_Bank4->SR4 = 0x00000000; \r
+ FSMC_Bank4->PMEM4 = 0xFCFCFCFC;\r
+ FSMC_Bank4->PATT4 = 0xFCFCFCFC;\r
+ FSMC_Bank4->PIO4 = 0xFCFCFCFC;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the FSMC NOR/SRAM Banks according to the \r
+ * specified parameters in the FSMC_NORSRAMInitStruct.\r
+ * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef\r
+ * structure that contains the configuration information for \r
+ * the FSMC NOR/SRAM specified Banks. \r
+ * @retval : None\r
+ */\r
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));\r
+ assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));\r
+ assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));\r
+ assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));\r
+ assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));\r
+ assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));\r
+ assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));\r
+ assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));\r
+ assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));\r
+ assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));\r
+ assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));\r
+ assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); \r
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));\r
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));\r
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));\r
+ assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));\r
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));\r
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));\r
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); \r
+ \r
+ /* Bank1 NOR/SRAM control register configuration */ \r
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType |\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |\r
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |\r
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode |\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation |\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal |\r
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst;\r
+ if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)\r
+ {\r
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;\r
+ }\r
+ /* Bank1 NOR/SRAM timing register configuration */\r
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = \r
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;\r
+ \r
+ \r
+ /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */\r
+ if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)\r
+ {\r
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));\r
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));\r
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));\r
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));\r
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));\r
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));\r
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the FSMC NAND Banks according to the specified \r
+ * parameters in the FSMC_NANDInitStruct.\r
+ * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef \r
+ * structure that contains the configuration information for \r
+ * the FSMC NAND specified Banks. \r
+ * @retval : None\r
+ */\r
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
+{\r
+ uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; \r
+ \r
+ /* Check the parameters */\r
+ assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));\r
+ assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));\r
+ assert_param( IS_FSMC_DATA_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));\r
+ assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));\r
+ assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));\r
+ assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));\r
+ assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));\r
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
+ \r
+ /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */\r
+ tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |\r
+ PCR_MemoryType_NAND |\r
+ FSMC_NANDInitStruct->FSMC_MemoryDataWidth |\r
+ FSMC_NANDInitStruct->FSMC_ECC |\r
+ FSMC_NANDInitStruct->FSMC_ECCPageSize |\r
+ (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|\r
+ (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);\r
+ \r
+ /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */\r
+ tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
+ \r
+ /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */\r
+ tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);\r
+ \r
+ if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ /* FSMC_Bank2_NAND registers configuration */\r
+ FSMC_Bank2->PCR2 = tmppcr;\r
+ FSMC_Bank2->PMEM2 = tmppmem;\r
+ FSMC_Bank2->PATT2 = tmppatt;\r
+ }\r
+ else\r
+ {\r
+ /* FSMC_Bank3_NAND registers configuration */\r
+ FSMC_Bank3->PCR3 = tmppcr;\r
+ FSMC_Bank3->PMEM3 = tmppmem;\r
+ FSMC_Bank3->PATT3 = tmppatt;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the FSMC PCCARD Bank according to the specified \r
+ * parameters in the FSMC_PCCARDInitStruct.\r
+ * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef\r
+ * structure that contains the configuration information for \r
+ * the FSMC PCCARD Bank. \r
+ * @retval : None\r
+ */\r
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));\r
+ assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));\r
+ assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));\r
+ \r
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
+ \r
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));\r
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));\r
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));\r
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));\r
+ \r
+ /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */\r
+ FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |\r
+ FSMC_MemoryDataWidth_16b | \r
+ (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |\r
+ (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);\r
+ \r
+ /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */\r
+ FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
+ \r
+ /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */\r
+ FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
+ \r
+ /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */\r
+ FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |\r
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
+}\r
+\r
+/**\r
+ * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.\r
+ * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef \r
+ * structure which will be initialized.\r
+ * @retval : None\r
+ */\r
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
+{ \r
+ /* Reset NOR/SRAM Init structure parameters values */\r
+ FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;\r
+ FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;\r
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; \r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;\r
+}\r
+\r
+/**\r
+ * @brief Fills each FSMC_NANDInitStruct member with its default value.\r
+ * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef \r
+ * structure which will be initialized.\r
+ * @retval : None\r
+ */\r
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
+{ \r
+ /* Reset NAND Init structure parameters values */\r
+ FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;\r
+ FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
+ FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
+ FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;\r
+ FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;\r
+ FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
+ FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;\r
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; \r
+}\r
+\r
+/**\r
+ * @brief Fills each FSMC_PCCARDInitStruct member with its default value.\r
+ * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef \r
+ * structure which will be initialized.\r
+ * @retval : None\r
+ */\r
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
+{\r
+ /* Reset PCCARD Init structure parameters values */\r
+ FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
+ FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
+ FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;\r
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; \r
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified NOR/SRAM Memory Bank.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
+ * @param NewState: new state of the FSMC_Bank.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval : None\r
+ */\r
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
+{\r
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */\r
+ FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */\r
+ FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified NAND Memory Bank.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @param NewState: new state of the FSMC_Bank.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval : None\r
+ */\r
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
+{\r
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PCCARD Memory Bank.\r
+ * @param NewState: new state of the PCCARD Memory Bank. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval : None\r
+ */\r
+void FSMC_PCCARDCmd(FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */\r
+ FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */\r
+ FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the FSMC NAND ECC feature.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @param NewState: new state of the FSMC NAND ECC feature. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval : None\r
+ */\r
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
+{\r
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the error correction code register value.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @retval : The Error Correction Code (ECC) value.\r
+ */\r
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank)\r
+{\r
+ uint32_t eccval = 0x00000000;\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ /* Get the ECCR2 register value */\r
+ eccval = FSMC_Bank2->ECCR2;\r
+ }\r
+ else\r
+ {\r
+ /* Get the ECCR3 register value */\r
+ eccval = FSMC_Bank3->ECCR3;\r
+ }\r
+ /* Return the error correction code value */\r
+ return(eccval);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified FSMC interrupts.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
+ * @param FSMC_IT: specifies the FSMC interrupt sources to be\r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
+ * @arg FSMC_IT_Level: Level edge detection interrupt.\r
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
+ * @param NewState: new state of the specified FSMC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval : None\r
+ */\r
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)\r
+{\r
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
+ assert_param(IS_FSMC_IT(FSMC_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected FSMC_Bank2 interrupts */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->SR2 |= FSMC_IT;\r
+ }\r
+ /* Enable the selected FSMC_Bank3 interrupts */\r
+ else if (FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ FSMC_Bank3->SR3 |= FSMC_IT;\r
+ }\r
+ /* Enable the selected FSMC_Bank4 interrupts */\r
+ else\r
+ {\r
+ FSMC_Bank4->SR4 |= FSMC_IT; \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected FSMC_Bank2 interrupts */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ \r
+ FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;\r
+ }\r
+ /* Disable the selected FSMC_Bank3 interrupts */\r
+ else if (FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;\r
+ }\r
+ /* Disable the selected FSMC_Bank4 interrupts */\r
+ else\r
+ {\r
+ FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; \r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified FSMC flag is set or not.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
+ * @param FSMC_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
+ * @arg FSMC_FLAG_Level: Level detection Flag.\r
+ * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
+ * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. \r
+ * @retval : The new state of FSMC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t tmpsr = 0x00000000;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
+ assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ tmpsr = FSMC_Bank2->SR2;\r
+ } \r
+ else if(FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ tmpsr = FSMC_Bank3->SR3;\r
+ }\r
+ /* FSMC_Bank4_PCCARD*/\r
+ else\r
+ {\r
+ tmpsr = FSMC_Bank4->SR4;\r
+ } \r
+ \r
+ /* Get the flag status */\r
+ if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the FSMC\92s pending flags.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
+ * @param FSMC_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
+ * @arg FSMC_FLAG_Level: Level detection Flag.\r
+ * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
+ * @retval : None\r
+ */\r
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
+ assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->SR2 &= ~FSMC_FLAG; \r
+ } \r
+ else if(FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ FSMC_Bank3->SR3 &= ~FSMC_FLAG;\r
+ }\r
+ /* FSMC_Bank4_PCCARD*/\r
+ else\r
+ {\r
+ FSMC_Bank4->SR4 &= ~FSMC_FLAG;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified FSMC interrupt has occurred or not.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
+ * @param FSMC_IT: specifies the FSMC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
+ * @arg FSMC_IT_Level: Level edge detection interrupt.\r
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. \r
+ * @retval : The new state of FSMC_IT (SET or RESET).\r
+ */\r
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
+ assert_param(IS_FSMC_GET_IT(FSMC_IT));\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ tmpsr = FSMC_Bank2->SR2;\r
+ } \r
+ else if(FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ tmpsr = FSMC_Bank3->SR3;\r
+ }\r
+ /* FSMC_Bank4_PCCARD*/\r
+ else\r
+ {\r
+ tmpsr = FSMC_Bank4->SR4;\r
+ } \r
+ \r
+ itstatus = tmpsr & FSMC_IT;\r
+ \r
+ itenable = tmpsr & (FSMC_IT >> 3);\r
+ if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Clears the FSMC\92s interrupt pending bits.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
+ * @param FSMC_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
+ * @arg FSMC_IT_Level: Level edge detection interrupt.\r
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
+ * @retval : None\r
+ */\r
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
+ assert_param(IS_FSMC_IT(FSMC_IT));\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); \r
+ } \r
+ else if(FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);\r
+ }\r
+ /* FSMC_Bank4_PCCARD*/\r
+ else\r
+ {\r
+ FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
projects / freertos / commitdiff