\r
\r
/* Time delay between repeated attempts to initialise the network hardware. */\r
-#define ipINITIALISATION_RETRY_DELAY ( pdMS_TO_TICKS( 3000 ) )\r
+#ifndef ipINITIALISATION_RETRY_DELAY\r
+ #define ipINITIALISATION_RETRY_DELAY ( pdMS_TO_TICKS( 3000 ) )\r
+#endif\r
\r
/* Defines how often the ARP timer callback function is executed. The time is\r
shorted in the Windows simulator as simulated time is not real time. */\r
\r
/* Added to prevent ARP flood to gateway. Ensure the\r
gateway is on the same subnet as the IP address. */\r
- configASSERT( ( ( *ipLOCAL_IP_ADDRESS_POINTER ) & xNetworkAddressing.ulNetMask ) == ( xNetworkAddressing.ulGatewayAddress & xNetworkAddressing.ulNetMask ) );\r
+ if( xNetworkAddressing.ulGatewayAddress != 0ul )\r
+ {\r
+ configASSERT( ( ( *ipLOCAL_IP_ADDRESS_POINTER ) & xNetworkAddressing.ulNetMask ) == ( xNetworkAddressing.ulGatewayAddress & xNetworkAddressing.ulNetMask ) );\r
+ }\r
}\r
#endif /* ipconfigUSE_DHCP == 1 */\r
\r
creation, it could still be changed with setsockopt(). */\r
if( xIsInputStream != pdFALSE )\r
{\r
+ /* Flow control for input streams works with a low- and a high-water mark.\r
+ 1) If the RX-space becomes less than uxLittleSpace, the flag 'bLowWater' will\r
+ be set, and a TCP window update message will be sent to the peer.\r
+ 2) The data will be read from the socket by recv() and when RX-space becomes\r
+ larger than or equal to than 'uxEnoughSpace', a new TCP window update\r
+ message will be sent to the peer, and 'bLowWater' will get cleared again.\r
+ By default:\r
+ uxLittleSpace == 1/5 x uxRxStreamSize\r
+ uxEnoughSpace == 4/5 x uxRxStreamSize\r
+ How-ever it is very inefficient to make 'uxLittleSpace' smaller than the actual MSS.\r
+ */\r
uxLength = pxSocket->u.xTCP.uxRxStreamSize;\r
\r
if( pxSocket->u.xTCP.uxLittleSpace == 0ul )\r
{\r
pxSocket->u.xTCP.uxLittleSpace = ( 1ul * pxSocket->u.xTCP.uxRxStreamSize ) / 5u; /*_RB_ Why divide by 5? Can this be changed to a #define? */\r
+ if( (pxSocket->u.xTCP.uxLittleSpace < pxSocket->u.xTCP.usCurMSS ) && ( pxSocket->u.xTCP.uxRxStreamSize >= 2 * pxSocket->u.xTCP.usCurMSS ) )\r
+ {\r
+ pxSocket->u.xTCP.uxLittleSpace = pxSocket->u.xTCP.usCurMSS;\r
+ }\r
}\r
\r
if( pxSocket->u.xTCP.uxEnoughSpace == 0ul )\r
\r
xTempBuffer.pucEthernetBuffer = pxSocket->u.xTCP.xPacket.u.ucLastPacket;\r
xTempBuffer.xDataLength = sizeof( pxSocket->u.xTCP.xPacket.u.ucLastPacket );\r
+ /* A pseudo network buffer can not be released. */\r
+ xReleaseAfterSend = pdFALSE;\r
}\r
\r
#if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
--- /dev/null
+/*\r
+ * Handling of Ethernet PHY's\r
+ * PHY's communicate with an EMAC either through\r
+ * a Media-Independent Interface (MII), or a Reduced Media-Independent Interface (RMII).\r
+ * The EMAC can poll for PHY ports on 32 different addresses. Each of the PHY ports\r
+ * shall be treated independently.\r
+ * \r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* FreeRTOS+TCP includes. */\r
+#include "FreeRTOS_IP.h"\r
+#include "FreeRTOS_Sockets.h"\r
+\r
+#include "phyHandling.h"\r
+\r
+#include "eventLogging.h"\r
+\r
+#define phyMIN_PHY_ADDRESS 0\r
+#define phyMAX_PHY_ADDRESS 31\r
+\r
+#if defined( PHY_LS_HIGH_CHECK_TIME_MS ) || defined( PHY_LS_LOW_CHECK_TIME_MS )\r
+ #warning please use the new defines with 'ipconfig' prefix\r
+#endif\r
+\r
+#ifndef ipconfigPHY_LS_HIGH_CHECK_TIME_MS\r
+ /* Check if the LinkSStatus in the PHY is still high after 15 seconds of not\r
+ receiving packets. */\r
+ #define ipconfigPHY_LS_HIGH_CHECK_TIME_MS 15000\r
+#endif\r
+\r
+#ifndef ipconfigPHY_LS_LOW_CHECK_TIME_MS\r
+ /* Check if the LinkSStatus in the PHY is still low every second. */\r
+ #define ipconfigPHY_LS_LOW_CHECK_TIME_MS 1000\r
+#endif\r
+\r
+/* Naming and numbering of basic PHY registers. */\r
+#define phyREG_00_BMCR 0x00u /* Basic Mode Control Register. */\r
+#define phyREG_01_BMSR 0x01u /* Basic Mode Status Register. */\r
+#define phyREG_02_PHYSID1 0x02u /* PHYS ID 1 */\r
+#define phyREG_03_PHYSID2 0x03u /* PHYS ID 2 */\r
+#define phyREG_04_ADVERTISE 0x04u /* Advertisement control reg */\r
+\r
+/* Naming and numbering of extended PHY registers. */\r
+#define PHYREG_10_PHYSTS 0x10u /* 16 PHY status register Offset */\r
+#define phyREG_19_PHYCR 0x19u /* 25 RW PHY Control Register */\r
+#define phyREG_1F_PHYSPCS 0x1Fu /* 31 RW PHY Special Control Status */\r
+\r
+/* Bit fields for 'phyREG_00_BMCR', the 'Basic Mode Control Register'. */\r
+#define phyBMCR_FULL_DUPLEX 0x0100u /* Full duplex. */\r
+#define phyBMCR_AN_RESTART 0x0200u /* Auto negotiation restart. */\r
+#define phyBMCR_AN_ENABLE 0x1000u /* Enable auto negotiation. */\r
+#define phyBMCR_SPEED_100 0x2000u /* Select 100Mbps. */\r
+#define phyBMCR_RESET 0x8000u /* Reset the PHY. */\r
+\r
+/* Bit fields for 'phyREG_19_PHYCR', the 'PHY Control Register'. */\r
+#define PHYCR_MDIX_EN 0x8000u /* Enable Auto MDIX. */\r
+#define PHYCR_MDIX_FORCE 0x4000u /* Force MDIX crossed. */\r
+\r
+#define phyBMSR_AN_COMPLETE 0x0020u /* Auto-Negotiation process completed */\r
+\r
+#define phyBMSR_LINK_STATUS 0x0004u\r
+\r
+#define phyPHYSTS_LINK_STATUS 0x0001u /* PHY Link mask */\r
+#define phyPHYSTS_SPEED_STATUS 0x0002u /* PHY Speed mask */\r
+#define phyPHYSTS_DUPLEX_STATUS 0x0004u /* PHY Duplex mask */\r
+\r
+/* Bit fields for 'phyREG_1F_PHYSPCS\r
+ 001 = 10BASE-T half-duplex\r
+ 101 = 10BASE-T full-duplex\r
+ 010 = 100BASE-TX half-duplex\r
+ 110 = 100BASE-TX full-duplex\r
+*/\r
+#define phyPHYSPCS_SPEED_MASK 0x000Cu\r
+#define phyPHYSPCS_SPEED_10 0x0004u\r
+#define phyPHYSPCS_FULL_DUPLEX 0x0010u\r
+\r
+/*\r
+ * Description of all capabilities that can be advertised to\r
+ * the peer (usually a switch or router).\r
+ */\r
+#define phyADVERTISE_CSMA 0x0001u /* Only selector supported. */\r
+#define phyADVERTISE_10HALF 0x0020u /* Try for 10mbps half-duplex. */\r
+#define phyADVERTISE_10FULL 0x0040u /* Try for 10mbps full-duplex. */\r
+#define phyADVERTISE_100HALF 0x0080u /* Try for 100mbps half-duplex. */\r
+#define phyADVERTISE_100FULL 0x0100u /* Try for 100mbps full-duplex. */\r
+\r
+#define phyADVERTISE_ALL ( phyADVERTISE_10HALF | phyADVERTISE_10FULL | \\r
+ phyADVERTISE_100HALF | phyADVERTISE_100FULL )\r
+\r
+/* Send a reset commando to a set of PHY-ports. */\r
+static uint32_t xPhyReset( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask );\r
+\r
+static BaseType_t xHas_1F_PHYSPCS( uint32_t ulPhyID )\r
+{\r
+BaseType_t xResult;\r
+\r
+ switch( ulPhyID )\r
+ {\r
+ case PHY_ID_LAN8720:\r
+ case PHY_ID_LAN8742A:\r
+ case PHY_ID_KSZ8041:\r
+/*\r
+ case PHY_ID_KSZ8051: // same ID as 8041\r
+ case PHY_ID_KSZ8081: // same ID as 8041\r
+*/\r
+ case PHY_ID_KSZ8863:\r
+ default:\r
+ /* Most PHY's have a 1F_PHYSPCS */\r
+ xResult = pdTRUE;\r
+ break;\r
+ case PHY_ID_DP83848I:\r
+ xResult = pdFALSE;\r
+ break;\r
+ }\r
+ return xResult;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static BaseType_t xHas_19_PHYCR( uint32_t ulPhyID )\r
+{\r
+BaseType_t xResult;\r
+\r
+ switch( ulPhyID )\r
+ {\r
+ case PHY_ID_LAN8742A:\r
+ case PHY_ID_DP83848I:\r
+ xResult = pdTRUE;\r
+ break;\r
+ default:\r
+ /* Most PHY's do not have a 19_PHYCR */\r
+ xResult = pdFALSE;\r
+ break;\r
+ }\r
+ return xResult;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Initialise the struct and assign a PHY-read and -write function. */\r
+void vPhyInitialise( EthernetPhy_t *pxPhyObject, xApplicationPhyReadHook_t fnPhyRead, xApplicationPhyWriteHook_t fnPhyWrite )\r
+{\r
+ memset( ( void * )pxPhyObject, '\0', sizeof( *pxPhyObject ) );\r
+\r
+ pxPhyObject->fnPhyRead = fnPhyRead;\r
+ pxPhyObject->fnPhyWrite = fnPhyWrite;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Discover all PHY's connected by polling 32 indexes ( zero-based ) */\r
+BaseType_t xPhyDiscover( EthernetPhy_t *pxPhyObject )\r
+{\r
+BaseType_t xPhyAddress;\r
+\r
+ pxPhyObject->xPortCount = 0;\r
+\r
+ for( xPhyAddress = phyMIN_PHY_ADDRESS; xPhyAddress <= phyMAX_PHY_ADDRESS; xPhyAddress++ )\r
+ {\r
+ uint32_t ulLowerID;\r
+\r
+ pxPhyObject->fnPhyRead( xPhyAddress, phyREG_03_PHYSID2, &ulLowerID );\r
+ /* A valid PHY id can not be all zeros or all ones. */\r
+ if( ( ulLowerID != ( uint16_t )~0u ) && ( ulLowerID != ( uint16_t )0u ) )\r
+ {\r
+ uint32_t ulUpperID;\r
+ uint32_t ulPhyID;\r
+\r
+ pxPhyObject->fnPhyRead( xPhyAddress, phyREG_02_PHYSID1, &ulUpperID );\r
+ ulPhyID = ( ( ( uint32_t ) ulUpperID ) << 16 ) | ( ulLowerID & 0xFFF0 );\r
+\r
+ pxPhyObject->ucPhyIndexes[ pxPhyObject->xPortCount ] = xPhyAddress;\r
+ pxPhyObject->ulPhyIDs[ pxPhyObject->xPortCount ] = ulPhyID;\r
+\r
+ pxPhyObject->xPortCount++;\r
+\r
+ /* See if there is more storage space. */\r
+ if( pxPhyObject->xPortCount == ipconfigPHY_MAX_PORTS )\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ if( pxPhyObject->xPortCount > 0 )\r
+ {\r
+ FreeRTOS_printf( ( "PHY ID %lX\n", pxPhyObject->ulPhyIDs[ 0 ] ) );\r
+ eventLogAdd( "PHY ID 0x%lX", pxPhyObject->ulPhyIDs[ 0 ] );\r
+ }\r
+\r
+ return pxPhyObject->xPortCount;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Send a reset commando to a set of PHY-ports. */\r
+static uint32_t xPhyReset( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask )\r
+{\r
+uint32_t ulDoneMask, ulConfig;\r
+TickType_t xRemainingTime;\r
+TimeOut_t xTimer;\r
+BaseType_t xPhyIndex;\r
+\r
+ /* A bit-mask ofPHY ports that are ready. */\r
+ ulDoneMask = 0ul;\r
+\r
+ /* Set the RESET bits high. */\r
+ for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ )\r
+ {\r
+ BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
+\r
+ /* Read Control register. */\r
+ pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig );\r
+ pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, ulConfig | phyBMCR_RESET );\r
+ }\r
+\r
+ xRemainingTime = ( TickType_t ) pdMS_TO_TICKS( 1000UL );\r
+ vTaskSetTimeOutState( &xTimer );\r
+\r
+ /* The reset should last less than a second. */\r
+ for( ;; )\r
+ {\r
+ for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ )\r
+ {\r
+ BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
+\r
+ pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig );\r
+ if( ( ulConfig & phyBMCR_RESET ) == 0 )\r
+ {\r
+ FreeRTOS_printf( ( "xPhyReset: phyBMCR_RESET %d ready\n", (int)xPhyIndex ) );\r
+ ulDoneMask |= ( 1ul << xPhyIndex );\r
+ }\r
+ }\r
+ if( ulDoneMask == ulPhyMask )\r
+ {\r
+ break;\r
+ }\r
+ if( xTaskCheckForTimeOut( &xTimer, &xRemainingTime ) != pdFALSE )\r
+ {\r
+ FreeRTOS_printf( ( "xPhyReset: phyBMCR_RESET timed out ( done 0x%02lX )\n", ulDoneMask ) );\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Clear the reset bits. */\r
+ for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ )\r
+ {\r
+ BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
+\r
+ pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig );\r
+ pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, ulConfig & ~phyBMCR_RESET );\r
+ }\r
+\r
+ vTaskDelay( pdMS_TO_TICKS( 50ul ) );\r
+ eventLogAdd( "PHY reset %d ports", (int)pxPhyObject->xPortCount );\r
+ return ulDoneMask;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPhyConfigure( EthernetPhy_t *pxPhyObject, const PhyProperties_t *pxPhyProperties )\r
+{\r
+uint32_t ulConfig, ulAdvertise;\r
+BaseType_t xPhyIndex;\r
+\r
+ if( pxPhyObject->xPortCount < 1 )\r
+ {\r
+ FreeRTOS_printf( ( "xPhyResetAll: No PHY's detected.\n" ) );\r
+ return -1;\r
+ }\r
+\r
+ /* The expected ID for the 'LAN8742A' is 0x0007c130. */\r
+ /* The expected ID for the 'LAN8720' is 0x0007c0f0. */\r
+ /* The expected ID for the 'DP83848I' is 0x20005C90. */\r
+\r
+ /* Set advertise register. */\r
+ if( ( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_AUTO ) && ( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_AUTO ) )\r
+ {\r
+ ulAdvertise = phyADVERTISE_CSMA | phyADVERTISE_ALL;\r
+ /* Reset auto-negotiation capability. */\r
+ }\r
+ else\r
+ {\r
+ ulAdvertise = phyADVERTISE_CSMA;\r
+\r
+ if( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_AUTO )\r
+ {\r
+ if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_FULL )\r
+ {\r
+ ulAdvertise |= phyADVERTISE_10FULL | phyADVERTISE_100FULL;\r
+ }\r
+ else\r
+ {\r
+ ulAdvertise |= phyADVERTISE_10HALF | phyADVERTISE_100HALF;\r
+ }\r
+ }\r
+ else if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_AUTO )\r
+ {\r
+ if( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_10 )\r
+ {\r
+ ulAdvertise |= phyADVERTISE_10FULL | phyADVERTISE_10HALF;\r
+ }\r
+ else\r
+ {\r
+ ulAdvertise |= phyADVERTISE_100FULL | phyADVERTISE_100HALF;\r
+ }\r
+ }\r
+ else if( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_100 )\r
+ {\r
+ if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_FULL )\r
+ {\r
+ ulAdvertise |= phyADVERTISE_100FULL;\r
+ }\r
+ else\r
+ {\r
+ ulAdvertise |= phyADVERTISE_100HALF;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_FULL )\r
+ {\r
+ ulAdvertise |= phyADVERTISE_10FULL;\r
+ }\r
+ else\r
+ {\r
+ ulAdvertise |= phyADVERTISE_10HALF;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Send a reset commando to a set of PHY-ports. */\r
+ xPhyReset( pxPhyObject, xPhyGetMask( pxPhyObject ) );\r
+\r
+ for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ )\r
+ {\r
+ BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
+ uint32_t ulPhyID = pxPhyObject->ulPhyIDs[ xPhyIndex ];\r
+\r
+ /* Write advertise register. */\r
+ pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_04_ADVERTISE, ulAdvertise );\r
+\r
+ /*\r
+ AN_EN AN1 AN0 Forced Mode\r
+ 0 0 0 10BASE-T, Half-Duplex\r
+ 0 0 1 10BASE-T, Full-Duplex\r
+ 0 1 0 100BASE-TX, Half-Duplex\r
+ 0 1 1 100BASE-TX, Full-Duplex\r
+ AN_EN AN1 AN0 Advertised Mode\r
+ 1 0 0 10BASE-T, Half/Full-Duplex\r
+ 1 0 1 100BASE-TX, Half/Full-Duplex\r
+ 1 1 0 10BASE-T Half-Duplex\r
+ 100BASE-TX, Half-Duplex\r
+ 1 1 1 10BASE-T, Half/Full-Duplex\r
+ 100BASE-TX, Half/Full-Duplex\r
+ */\r
+\r
+ /* Read Control register. */\r
+ pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig );\r
+\r
+ ulConfig &= ~( phyBMCR_SPEED_100 | phyBMCR_FULL_DUPLEX );\r
+\r
+ ulConfig |= phyBMCR_AN_ENABLE;\r
+\r
+ if( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_100 )\r
+ {\r
+ ulConfig |= phyBMCR_SPEED_100;\r
+ }\r
+ else if( pxPhyProperties->ucSpeed == ( uint8_t )PHY_SPEED_10 )\r
+ {\r
+ ulConfig &= ~phyBMCR_SPEED_100;\r
+ }\r
+\r
+ if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_FULL )\r
+ {\r
+ ulConfig |= phyBMCR_FULL_DUPLEX;\r
+ }\r
+ else if( pxPhyProperties->ucDuplex == ( uint8_t )PHY_DUPLEX_HALF )\r
+ {\r
+ ulConfig &= ~phyBMCR_FULL_DUPLEX;\r
+ }\r
+\r
+ if( xHas_19_PHYCR( ulPhyID ) )\r
+ {\r
+ uint32_t ulPhyControl;\r
+ /* Read PHY Control register. */\r
+ pxPhyObject->fnPhyRead( xPhyAddress, phyREG_19_PHYCR, &ulPhyControl );\r
+\r
+ /* Clear bits which might get set: */\r
+ ulPhyControl &= ~( PHYCR_MDIX_EN|PHYCR_MDIX_FORCE );\r
+\r
+ if( pxPhyProperties->ucMDI_X == PHY_MDIX_AUTO )\r
+ {\r
+ ulPhyControl |= PHYCR_MDIX_EN;\r
+ }\r
+ else if( pxPhyProperties->ucMDI_X == PHY_MDIX_CROSSED )\r
+ {\r
+ /* Force direct link = Use crossed RJ45 cable. */\r
+ ulPhyControl &= ~PHYCR_MDIX_FORCE;\r
+ }\r
+ else\r
+ {\r
+ /* Force crossed link = Use direct RJ45 cable. */\r
+ ulPhyControl |= PHYCR_MDIX_FORCE;\r
+ }\r
+ /* update PHY Control Register. */\r
+ pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_19_PHYCR, ulPhyControl );\r
+ }\r
+\r
+ FreeRTOS_printf( ( "+TCP: advertise: %04lX config %04lX\n", ulAdvertise, ulConfig ) );\r
+ eventLogAdd( "adv: %04lX config %04lX", ulAdvertise, ulConfig );\r
+ }\r
+\r
+ /* Keep these values for later use. */\r
+ pxPhyObject->ulBCRValue = ulConfig;\r
+ pxPhyObject->ulACRValue = ulAdvertise;\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPhyFixedValue( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask )\r
+{\r
+BaseType_t xPhyIndex;\r
+uint32_t ulValue, ulBitMask = ( uint32_t )1u;\r
+\r
+ ulValue = ( uint32_t )0u;\r
+\r
+ if( pxPhyObject->xPhyPreferences.ucDuplex == PHY_DUPLEX_FULL )\r
+ {\r
+ ulValue |= phyBMCR_FULL_DUPLEX;\r
+ }\r
+ if( pxPhyObject->xPhyPreferences.ucSpeed == PHY_SPEED_100 )\r
+ {\r
+ ulValue |= phyBMCR_SPEED_100;\r
+ }\r
+\r
+ for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )\r
+ {\r
+ if( ( ulPhyMask & ulBitMask ) != 0lu )\r
+ {\r
+ BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
+\r
+ /* Enable Auto-Negotiation. */\r
+ pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, ulValue );\r
+ }\r
+ }\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPhyStartAutoNegotiation( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask )\r
+{\r
+uint32_t xPhyIndex, ulDoneMask, ulBitMask;\r
+uint32_t ulPHYLinkStatus, ulRegValue;\r
+TickType_t xRemainingTime;\r
+TimeOut_t xTimer;\r
+\r
+ if( ulPhyMask == ( uint32_t )0u )\r
+ {\r
+ return 0;\r
+ }\r
+ for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ )\r
+ {\r
+ if( ( ulPhyMask & ( 1lu << xPhyIndex ) ) != 0lu )\r
+ {\r
+ BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
+\r
+ /* Enable Auto-Negotiation. */\r
+ pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_04_ADVERTISE, pxPhyObject->ulACRValue);\r
+ pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, pxPhyObject->ulBCRValue | phyBMCR_AN_RESTART );\r
+ }\r
+ }\r
+eventLogAdd( "AN start" );\r
+ xRemainingTime = ( TickType_t ) pdMS_TO_TICKS( 3000UL );\r
+ vTaskSetTimeOutState( &xTimer );\r
+ ulDoneMask = 0;\r
+ /* Wait until the auto-negotiation will be completed */\r
+ for( ;; )\r
+ {\r
+ ulBitMask = ( uint32_t )1u;\r
+ for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )\r
+ {\r
+ if( ( ulPhyMask & ulBitMask ) != 0lu )\r
+ {\r
+ if( ( ulDoneMask & ulBitMask ) == 0lu )\r
+ {\r
+ BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
+\r
+ pxPhyObject->fnPhyRead( xPhyAddress, phyREG_01_BMSR, &ulRegValue );\r
+ if( ( ulRegValue & phyBMSR_AN_COMPLETE ) != 0 )\r
+ {\r
+ ulDoneMask |= ulBitMask;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ if( ulPhyMask == ulDoneMask )\r
+ {\r
+ break;\r
+ }\r
+ if( xTaskCheckForTimeOut( &xTimer, &xRemainingTime ) != pdFALSE )\r
+ {\r
+ FreeRTOS_printf( ( "xPhyReset: phyBMCR_RESET timed out ( done 0x%02lX )\n", ulDoneMask ) );\r
+ eventLogAdd( "ANtimed out");\r
+ break;\r
+ }\r
+ }\r
+eventLogAdd( "AN done %02lX / %02lX", ulDoneMask, ulPhyMask );\r
+\r
+ if( ulDoneMask != ( uint32_t)0u )\r
+ {\r
+ ulBitMask = ( uint32_t )1u;\r
+ pxPhyObject->ulLinkStatusMask &= ~( ulDoneMask );\r
+ for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )\r
+ {\r
+ BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
+ uint32_t ulPhyID = pxPhyObject->ulPhyIDs[ xPhyIndex ];\r
+\r
+ if( ( ulDoneMask & ulBitMask ) == ( uint32_t )0u )\r
+ {\r
+ continue;\r
+ }\r
+\r
+ /* Clear the 'phyBMCR_AN_RESTART' bit. */\r
+ pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, pxPhyObject->ulBCRValue );\r
+\r
+ pxPhyObject->fnPhyRead( xPhyAddress, phyREG_01_BMSR, &ulRegValue);\r
+ if( ( ulRegValue & phyBMSR_LINK_STATUS ) != 0 )\r
+ {\r
+ ulPHYLinkStatus |= phyBMSR_LINK_STATUS;\r
+ pxPhyObject->ulLinkStatusMask |= ulBitMask;\r
+ }\r
+ else\r
+ {\r
+ ulPHYLinkStatus &= ~( phyBMSR_LINK_STATUS );\r
+ }\r
+\r
+ if( xHas_1F_PHYSPCS( ulPhyID ) )\r
+ {\r
+ /* 31 RW PHY Special Control Status */\r
+ uint32_t ulControlStatus;\r
+\r
+ pxPhyObject->fnPhyRead( xPhyAddress, phyREG_1F_PHYSPCS, &ulControlStatus);\r
+ ulRegValue = 0;\r
+ if( ( ulControlStatus & phyPHYSPCS_FULL_DUPLEX ) != 0 )\r
+ {\r
+ ulRegValue |= phyPHYSTS_DUPLEX_STATUS;\r
+ }\r
+ if( ( ulControlStatus & phyPHYSPCS_SPEED_MASK ) == phyPHYSPCS_SPEED_10 )\r
+ {\r
+ ulRegValue |= phyPHYSTS_SPEED_STATUS;\r
+ }\r
+\r
+ }\r
+ else\r
+ {\r
+ /* Read the result of the auto-negotiation. */\r
+ pxPhyObject->fnPhyRead( xPhyAddress, PHYREG_10_PHYSTS, &ulRegValue);\r
+ }\r
+\r
+ FreeRTOS_printf( ( ">> Autonego ready: %08lx: %s duplex %u mbit %s status\n",\r
+ ulRegValue,\r
+ ( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) ? "full" : "half",\r
+ ( ulRegValue & phyPHYSTS_SPEED_STATUS ) ? 10 : 100,\r
+ ( ( ulPHYLinkStatus |= phyBMSR_LINK_STATUS ) != 0) ? "high" : "low" ) );\r
+ eventLogAdd( "%s duplex %u mbit %s st",\r
+ ( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) ? "full" : "half",\r
+ ( ulRegValue & phyPHYSTS_SPEED_STATUS ) ? 10 : 100,\r
+ ( ( ulPHYLinkStatus |= phyBMSR_LINK_STATUS ) != 0) ? "high" : "low" );\r
+{\r
+ uint32_t regs[4];\r
+ int i,j;\r
+ int address = 0x10;\r
+ for (i = 0; i < 4; i++)\r
+ {\r
+ for (j = 0; j < 4; j++)\r
+ {\r
+ pxPhyObject->fnPhyRead( xPhyAddress, address, regs + j );\r
+ address++;\r
+ }\r
+ eventLogAdd("%04lX %04lX %04lX %04lX",\r
+ regs[0], regs[1], regs[2], regs[3]);\r
+ }\r
+}\r
+ if( ( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) != ( uint32_t )0u )\r
+ {\r
+ pxPhyObject->xPhyProperties.ucDuplex = PHY_DUPLEX_FULL;\r
+ }\r
+ else\r
+ {\r
+ pxPhyObject->xPhyProperties.ucDuplex = PHY_DUPLEX_HALF;\r
+ }\r
+\r
+ if( ( ulRegValue & phyPHYSTS_SPEED_STATUS ) != 0 )\r
+ {\r
+ pxPhyObject->xPhyProperties.ucSpeed = PHY_SPEED_10;\r
+ }\r
+ else\r
+ {\r
+ pxPhyObject->xPhyProperties.ucSpeed = PHY_SPEED_100;\r
+ }\r
+ }\r
+ } /* if( ulDoneMask != ( uint32_t)0u ) */\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPhyCheckLinkStatus( EthernetPhy_t *pxPhyObject, BaseType_t xHadReception )\r
+{\r
+uint32_t ulStatus, ulBitMask = 1u;\r
+BaseType_t xPhyIndex;\r
+BaseType_t xNeedCheck = pdFALSE;\r
+\r
+ if( xHadReception > 0 )\r
+ {\r
+ /* A packet was received. No need to check for the PHY status now,\r
+ but set a timer to check it later on. */\r
+ vTaskSetTimeOutState( &( pxPhyObject->xLinkStatusTimer ) );\r
+ pxPhyObject->xLinkStatusRemaining = pdMS_TO_TICKS( ipconfigPHY_LS_HIGH_CHECK_TIME_MS );\r
+ }\r
+ else if( xTaskCheckForTimeOut( &( pxPhyObject->xLinkStatusTimer ), &( pxPhyObject->xLinkStatusRemaining ) ) != pdFALSE )\r
+ {\r
+ for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )\r
+ {\r
+ BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];\r
+\r
+ if( pxPhyObject->fnPhyRead( xPhyAddress, phyREG_01_BMSR, &ulStatus ) == 0 )\r
+ {\r
+ if( !!( pxPhyObject->ulLinkStatusMask & ulBitMask ) != !!( ulStatus & phyBMSR_LINK_STATUS ) )\r
+ {\r
+ if( ( ulStatus & phyBMSR_LINK_STATUS ) != 0 )\r
+ {\r
+ pxPhyObject->ulLinkStatusMask |= ulBitMask;\r
+ }\r
+ else\r
+ {\r
+ pxPhyObject->ulLinkStatusMask &= ~( ulBitMask );\r
+ }\r
+ FreeRTOS_printf( ( "xPhyCheckLinkStatus: PHY LS now %02lX\n", pxPhyObject->ulLinkStatusMask ) );\r
+ eventLogAdd( "PHY LS now %02lX", pxPhyObject->ulLinkStatusMask );\r
+ xNeedCheck = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ vTaskSetTimeOutState( &( pxPhyObject->xLinkStatusTimer ) );\r
+ if( ( pxPhyObject->ulLinkStatusMask & phyBMSR_LINK_STATUS ) != 0 )\r
+ {\r
+ pxPhyObject->xLinkStatusRemaining = pdMS_TO_TICKS( ipconfigPHY_LS_HIGH_CHECK_TIME_MS );\r
+ }\r
+ else\r
+ {\r
+ pxPhyObject->xLinkStatusRemaining = pdMS_TO_TICKS( ipconfigPHY_LS_LOW_CHECK_TIME_MS );\r
+ }\r
+ }\r
+ return xNeedCheck;\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * Some constants, hardware definitions and comments taken from ST's HAL driver\r
+ * library, COPYRIGHT(c) 2015 STMicroelectronics.\r
+ */\r
+\r
+/*\r
+ * FreeRTOS+TCP Labs Build 160919 (C) 2016 Real Time Engineers ltd.\r
+ * Authors include Hein Tibosch and Richard Barry\r
+ *\r
+ *******************************************************************************\r
+ ***** NOTE ******* NOTE ******* NOTE ******* NOTE ******* NOTE ******* NOTE ***\r
+ *** ***\r
+ *** ***\r
+ *** FREERTOS+TCP IS STILL IN THE LAB (mainly because the FTP and HTTP ***\r
+ *** demos have a dependency on FreeRTOS+FAT, which is only in the Labs ***\r
+ *** download): ***\r
+ *** ***\r
+ *** FreeRTOS+TCP is functional and has been used in commercial products ***\r
+ *** for some time. Be aware however that we are still refining its ***\r
+ *** design, the source code does not yet quite conform to the strict ***\r
+ *** coding and style standards mandated by Real Time Engineers ltd., and ***\r
+ *** the documentation and testing is not necessarily complete. ***\r
+ *** ***\r
+ *** PLEASE REPORT EXPERIENCES USING THE SUPPORT RESOURCES FOUND ON THE ***\r
+ *** URL: http://www.FreeRTOS.org/contact Active early adopters may, at ***\r
+ *** the sole discretion of Real Time Engineers Ltd., be offered versions ***\r
+ *** under a license other than that described below. ***\r
+ *** ***\r
+ *** ***\r
+ ***** NOTE ******* NOTE ******* NOTE ******* NOTE ******* NOTE ******* NOTE ***\r
+ *******************************************************************************\r
+ *\r
+ * FreeRTOS+TCP can be used under two different free open source licenses. The\r
+ * license that applies is dependent on the processor on which FreeRTOS+TCP is\r
+ * executed, as follows:\r
+ *\r
+ * If FreeRTOS+TCP is executed on one of the processors listed under the Special\r
+ * License Arrangements heading of the FreeRTOS+TCP license information web\r
+ * page, then it can be used under the terms of the FreeRTOS Open Source\r
+ * License. If FreeRTOS+TCP is used on any other processor, then it can be used\r
+ * under the terms of the GNU General Public License V2. Links to the relevant\r
+ * licenses follow:\r
+ *\r
+ * The FreeRTOS+TCP License Information Page: http://www.FreeRTOS.org/tcp_license\r
+ * The FreeRTOS Open Source License: http://www.FreeRTOS.org/license\r
+ * The GNU General Public License Version 2: http://www.FreeRTOS.org/gpl-2.0.txt\r
+ *\r
+ * FreeRTOS+TCP is distributed in the hope that it will be useful. You cannot\r
+ * use FreeRTOS+TCP unless you agree that you use the software 'as is'.\r
+ * FreeRTOS+TCP is provided WITHOUT ANY WARRANTY; without even the implied\r
+ * warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A PARTICULAR\r
+ * PURPOSE. Real Time Engineers Ltd. disclaims all conditions and terms, be they\r
+ * implied, expressed, or statutory.\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://www.FreeRTOS.org/plus\r
+ * http://www.FreeRTOS.org/labs\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdint.h>\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* FreeRTOS+TCP includes. */\r
+#include "FreeRTOS_IP.h"\r
+#include "FreeRTOS_Sockets.h"\r
+#include "FreeRTOS_IP_Private.h"\r
+#include "FreeRTOS_DNS.h"\r
+#include "NetworkBufferManagement.h"\r
+#include "NetworkInterface.h"\r
+\r
+#include "phyHandling.h"\r
+\r
+/* ST includes. */\r
+#ifdef STM32F7xx\r
+ #include "stm32f7xx_hal.h"\r
+#else\r
+ #include "stm32f4xx_hal.h"\r
+#endif\r
+\r
+/* Interrupt events to process. Currently only the Rx event is processed\r
+although code for other events is included to allow for possible future\r
+expansion. */\r
+#define EMAC_IF_RX_EVENT 1UL\r
+#define EMAC_IF_TX_EVENT 2UL\r
+#define EMAC_IF_ERR_EVENT 4UL\r
+#define EMAC_IF_ALL_EVENT ( EMAC_IF_RX_EVENT | EMAC_IF_TX_EVENT | EMAC_IF_ERR_EVENT )\r
+\r
+#define ETH_DMA_ALL_INTS \\r
+ ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_ER | \\r
+ ETH_DMA_IT_FBE | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \\r
+ ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T )\r
+\r
+\r
+\r
+#define ipFRAGMENT_OFFSET_BIT_MASK ( ( uint16_t ) 0x0fff ) /* The bits in the two byte IP header field that make up the fragment offset value. */\r
+\r
+/*\r
+ * Most users will want a PHY that negotiates about\r
+ * the connection properties: speed, dmix and duplex.\r
+ * On some rare cases, you want to select what is being\r
+ * advertised, properties like MDIX and duplex.\r
+ */\r
+\r
+#if !defined( ipconfigETHERNET_AN_ENABLE )\r
+ /* Enable auto-negotiation */\r
+ #define ipconfigETHERNET_AN_ENABLE 1\r
+#endif\r
+\r
+#if !defined( ipconfigETHERNET_AUTO_CROSS_ENABLE )\r
+ #define ipconfigETHERNET_AUTO_CROSS_ENABLE 1\r
+#endif\r
+\r
+#if( ipconfigETHERNET_AN_ENABLE == 0 )\r
+ /*\r
+ * The following three defines are only used in case there\r
+ * is no auto-negotiation.\r
+ */\r
+ #if !defined( ipconfigETHERNET_CROSSED_LINK )\r
+ #define ipconfigETHERNET_CROSSED_LINK 1\r
+ #endif\r
+\r
+ #if !defined( ipconfigETHERNET_USE_100MB )\r
+ #define ipconfigETHERNET_USE_100MB 1\r
+ #endif\r
+\r
+ #if !defined( ipconfigETHERNET_USE_FULL_DUPLEX )\r
+ #define ipconfigETHERNET_USE_FULL_DUPLEX 1\r
+ #endif\r
+#endif /* ipconfigETHERNET_AN_ENABLE == 0 */\r
+\r
+/* Default the size of the stack used by the EMAC deferred handler task to twice\r
+the size of the stack used by the idle task - but allow this to be overridden in\r
+FreeRTOSConfig.h as configMINIMAL_STACK_SIZE is a user definable constant. */\r
+#ifndef configEMAC_TASK_STACK_SIZE\r
+ #define configEMAC_TASK_STACK_SIZE ( 2 * configMINIMAL_STACK_SIZE )\r
+#endif\r
+\r
+/* Two choices must be made: RMII versus MII,\r
+and the index of the PHY in use ( between 0 and 31 ). */\r
+#ifndef ipconfigUSE_RMII\r
+ #ifdef STM32F7xx\r
+ #define ipconfigUSE_RMII 1\r
+ #else\r
+ #define ipconfigUSE_RMII 0\r
+ #endif /* STM32F7xx */\r
+#endif /* ipconfigUSE_RMII */\r
+\r
+#ifndef ipconfigPHY_INDEX\r
+ #ifdef STM32F7xx\r
+ #define ipconfigPHY_INDEX 0\r
+ #else\r
+ #define ipconfigPHY_INDEX 1\r
+ #endif /* STM32F7xx */\r
+#endif /* ipconfigPHY_INDEX */\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * A deferred interrupt handler task that processes\r
+ */\r
+static void prvEMACHandlerTask( void *pvParameters );\r
+\r
+/*\r
+ * Force a negotiation with the Switch or Router and wait for LS.\r
+ */\r
+static void prvEthernetUpdateConfig( BaseType_t xForce );\r
+\r
+/*\r
+ * See if there is a new packet and forward it to the IP-task.\r
+ */\r
+static BaseType_t prvNetworkInterfaceInput( void );\r
+\r
+#if( ipconfigUSE_LLMNR != 0 )\r
+ /*\r
+ * For LLMNR, an extra MAC-address must be configured to\r
+ * be able to receive the multicast messages.\r
+ */\r
+ static void prvMACAddressConfig(ETH_HandleTypeDef *heth, uint32_t ulIndex, uint8_t *Addr);\r
+#endif\r
+\r
+/*\r
+ * Check if a given packet should be accepted.\r
+ */\r
+static BaseType_t xMayAcceptPacket( uint8_t *pcBuffer );\r
+\r
+/*\r
+ * Initialise the TX descriptors.\r
+ */\r
+static void prvDMATxDescListInit( void );\r
+\r
+/*\r
+ * Initialise the RX descriptors.\r
+ */\r
+static void prvDMARxDescListInit( void );\r
+\r
+/* After packets have been sent, the network\r
+buffers will be released. */\r
+static void vClearTXBuffers( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Bit map of outstanding ETH interrupt events for processing. Currently only\r
+the Rx interrupt is handled, although code is included for other events to\r
+enable future expansion. */\r
+static volatile uint32_t ulISREvents;\r
+\r
+#if( ipconfigUSE_LLMNR == 1 )\r
+ static const uint8_t xLLMNR_MACAddress[] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0xFC };\r
+#endif\r
+\r
+static EthernetPhy_t xPhyObject;\r
+\r
+/* Ethernet handle. */\r
+static ETH_HandleTypeDef xETH;\r
+\r
+/* xTXDescriptorSemaphore is a counting semaphore with\r
+a maximum count of ETH_TXBUFNB, which is the number of\r
+DMA TX descriptors. */\r
+static SemaphoreHandle_t xTXDescriptorSemaphore = NULL;\r
+\r
+/*\r
+ * Note: it is adviced to define both\r
+ *\r
+ * #define ipconfigZERO_COPY_RX_DRIVER 1\r
+ * #define ipconfigZERO_COPY_TX_DRIVER 1\r
+ *\r
+ * The method using memcpy is slower and probaly uses more RAM memory.\r
+ * The possibility is left in the code just for comparison.\r
+ *\r
+ * It is adviced to define ETH_TXBUFNB at least 4. Note that no\r
+ * TX buffers are allocated in a zero-copy driver.\r
+ */\r
+/* MAC buffers: ---------------------------------------------------------*/\r
+\r
+/* Put the DMA descriptors in '.first_data'.\r
+This is important for STM32F7, which has an L1 data cache.\r
+The first 64KB of the SRAM is not cached. */\r
+\r
+/* Ethernet Rx MA Descriptor */\r
+__attribute__ ((aligned (32)))\r
+__attribute__ ((section(".first_data")))\r
+ ETH_DMADescTypeDef DMARxDscrTab[ ETH_RXBUFNB ];\r
+\r
+#if( ipconfigZERO_COPY_RX_DRIVER == 0 )\r
+ /* Ethernet Receive Buffer */\r
+ __ALIGN_BEGIN uint8_t Rx_Buff[ ETH_RXBUFNB ][ ETH_RX_BUF_SIZE ] __ALIGN_END;\r
+#endif\r
+\r
+/* Ethernet Tx DMA Descriptor */\r
+__attribute__ ((aligned (32)))\r
+__attribute__ ((section(".first_data")))\r
+ ETH_DMADescTypeDef DMATxDscrTab[ ETH_TXBUFNB ];\r
+\r
+#if( ipconfigZERO_COPY_TX_DRIVER == 0 )\r
+ /* Ethernet Transmit Buffer */\r
+ __ALIGN_BEGIN uint8_t Tx_Buff[ ETH_TXBUFNB ][ ETH_TX_BUF_SIZE ] __ALIGN_END;\r
+#endif\r
+\r
+#if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
+ /* DMATxDescToClear points to the next TX DMA descriptor\r
+ that must be cleared by vClearTXBuffers(). */\r
+ static __IO ETH_DMADescTypeDef *DMATxDescToClear;\r
+#endif\r
+\r
+/* ucMACAddress as it appears in main.c */\r
+extern const uint8_t ucMACAddress[ 6 ];\r
+\r
+/* Holds the handle of the task used as a deferred interrupt processor. The\r
+handle is used so direct notifications can be sent to the task for all EMAC/DMA\r
+related interrupts. */\r
+static TaskHandle_t xEMACTaskHandle = NULL;\r
+\r
+/* For local use only: describe the PHY's properties: */\r
+const PhyProperties_t xPHYProperties =\r
+{\r
+ #if( ipconfigETHERNET_AN_ENABLE != 0 )\r
+ .ucSpeed = PHY_SPEED_AUTO,\r
+ .ucDuplex = PHY_DUPLEX_AUTO,\r
+ #else\r
+ #if( ipconfigETHERNET_USE_100MB != 0 )\r
+ .ucSpeed = PHY_SPEED_100,\r
+ #else\r
+ .ucSpeed = PHY_SPEED_10,\r
+ #endif\r
+\r
+ #if( ipconfigETHERNET_USE_FULL_DUPLEX != 0 )\r
+ .duplex = PHY_DUPLEX_FULL,\r
+ #else\r
+ .duplex = PHY_DUPLEX_HALF,\r
+ #endif\r
+ #endif\r
+\r
+ #if( ipconfigETHERNET_AN_ENABLE != 0 ) && ( ipconfigETHERNET_AUTO_CROSS_ENABLE != 0 )\r
+ .ucMDI_X = PHY_MDIX_AUTO,\r
+ #elif( ipconfigETHERNET_CROSSED_LINK != 0 )\r
+ .ucMDI_X = PHY_MDIX_CROSSED,\r
+ #else\r
+ .ucMDI_X = PHY_MDIX_DIRECT,\r
+ #endif\r
+};\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef *heth )\r
+{\r
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* Ethernet RX-Complete callback function, elsewhere declared as weak. */\r
+ ulISREvents |= EMAC_IF_RX_EVENT;\r
+ /* Wakeup the prvEMACHandlerTask. */\r
+ if( xEMACTaskHandle != NULL )\r
+ {\r
+ vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken );\r
+ portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef *heth )\r
+{\r
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* This call-back is only useful in case packets are being sent\r
+ zero-copy. Once they're sent, the buffers will be released\r
+ by the function vClearTXBuffers(). */\r
+ ulISREvents |= EMAC_IF_TX_EVENT;\r
+ /* Wakeup the prvEMACHandlerTask. */\r
+ if( xEMACTaskHandle != NULL )\r
+ {\r
+ vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken );\r
+ portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r
+ }\r
+\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vClearTXBuffers()\r
+{\r
+__IO ETH_DMADescTypeDef *txLastDescriptor = xETH.TxDesc;\r
+size_t uxCount = ( ( UBaseType_t ) ETH_TXBUFNB ) - uxSemaphoreGetCount( xTXDescriptorSemaphore );\r
+#if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
+ NetworkBufferDescriptor_t *pxNetworkBuffer;\r
+ uint8_t *ucPayLoad;\r
+#endif\r
+\r
+ /* This function is called after a TX-completion interrupt.\r
+ It will release each Network Buffer used in xNetworkInterfaceOutput().\r
+ 'uxCount' represents the number of descriptors given to DMA for transmission.\r
+ After sending a packet, the DMA will clear the 'ETH_DMATXDESC_OWN' bit. */\r
+ while( ( uxCount > 0 ) && ( ( DMATxDescToClear->Status & ETH_DMATXDESC_OWN ) == 0 ) )\r
+ {\r
+ if( ( DMATxDescToClear == txLastDescriptor ) && ( uxCount != ETH_TXBUFNB ) )\r
+ {\r
+ break;\r
+ }\r
+ #if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
+ {\r
+ ucPayLoad = ( uint8_t * )DMATxDescToClear->Buffer1Addr;\r
+\r
+ if( ucPayLoad != NULL )\r
+ {\r
+ pxNetworkBuffer = pxPacketBuffer_to_NetworkBuffer( ucPayLoad );\r
+ if( pxNetworkBuffer != NULL )\r
+ {\r
+ vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ) ;\r
+ }\r
+ DMATxDescToClear->Buffer1Addr = ( uint32_t )0u;\r
+ }\r
+ }\r
+ #endif /* ipconfigZERO_COPY_TX_DRIVER */\r
+\r
+ DMATxDescToClear = ( ETH_DMADescTypeDef * )( DMATxDescToClear->Buffer2NextDescAddr );\r
+\r
+ uxCount--;\r
+ /* Tell the counting semaphore that one more TX descriptor is available. */\r
+ xSemaphoreGive( xTXDescriptorSemaphore );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xNetworkInterfaceInitialise( void )\r
+{\r
+HAL_StatusTypeDef hal_eth_init_status;\r
+BaseType_t xResult;\r
+\r
+ if( xEMACTaskHandle == NULL )\r
+ {\r
+ if( xTXDescriptorSemaphore == NULL )\r
+ {\r
+ xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ETH_TXBUFNB, ( UBaseType_t ) ETH_TXBUFNB );\r
+ configASSERT( xTXDescriptorSemaphore );\r
+ }\r
+\r
+ /* Initialise ETH */\r
+\r
+ xETH.Instance = ETH;\r
+//#warning Enable auto-nego again\r
+ xETH.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;\r
+// xETH.Init.AutoNegotiation = ETH_AUTONEGOTIATION_DISABLE;\r
+ xETH.Init.Speed = ETH_SPEED_100M;\r
+ xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX;\r
+ xETH.Init.PhyAddress = ipconfigPHY_INDEX;\r
+\r
+ xETH.Init.MACAddr = ( uint8_t *) ucMACAddress;\r
+ xETH.Init.RxMode = ETH_RXINTERRUPT_MODE;\r
+\r
+ /* using the ETH_CHECKSUM_BY_HARDWARE option:\r
+ both the IP and the protocol checksums will be calculated\r
+ by the peripheral. */\r
+ xETH.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;\r
+\r
+ #if( ipconfigUSE_RMII != 0 )\r
+ {\r
+ xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;\r
+ }\r
+ #else\r
+ {\r
+ xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_MII;\r
+ }\r
+ #endif /* ipconfigUSE_RMII */\r
+\r
+ hal_eth_init_status = HAL_ETH_Init( &xETH );\r
+\r
+ /* Only for inspection by debugger. */\r
+ ( void ) hal_eth_init_status;\r
+\r
+ /* Set the TxDesc and RxDesc pointers. */\r
+ xETH.TxDesc = DMATxDscrTab;\r
+ xETH.RxDesc = DMARxDscrTab;\r
+\r
+ /* Make sure that all unused fields are cleared. */\r
+ memset( &DMATxDscrTab, '\0', sizeof( DMATxDscrTab ) );\r
+ memset( &DMARxDscrTab, '\0', sizeof( DMARxDscrTab ) );\r
+\r
+ /* Initialize Tx Descriptors list: Chain Mode */\r
+ DMATxDescToClear = DMATxDscrTab;\r
+\r
+ /* Initialise TX-descriptors. */\r
+ prvDMATxDescListInit();\r
+\r
+ /* Initialise RX-descriptors. */\r
+ prvDMARxDescListInit();\r
+\r
+ #if( ipconfigUSE_LLMNR != 0 )\r
+ {\r
+ /* Program the LLMNR address at index 1. */\r
+ prvMACAddressConfig( &xETH, ETH_MAC_ADDRESS1, ( uint8_t *) xLLMNR_MACAddress );\r
+ }\r
+ #endif\r
+\r
+ /* Force a negotiation with the Switch or Router and wait for LS. */\r
+ prvEthernetUpdateConfig( pdTRUE );\r
+\r
+ /* The deferred interrupt handler task is created at the highest\r
+ possible priority to ensure the interrupt handler can return directly\r
+ to it. The task's handle is stored in xEMACTaskHandle so interrupts can\r
+ notify the task when there is something to process. */\r
+ xTaskCreate( prvEMACHandlerTask, "EMAC", configEMAC_TASK_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, &xEMACTaskHandle );\r
+ } /* if( xEMACTaskHandle == NULL ) */\r
+\r
+ if( xPhyObject.ulLinkStatusMask != 0 )\r
+ {\r
+ xETH.Instance->DMAIER |= ETH_DMA_ALL_INTS;\r
+ xResult = pdPASS;\r
+ FreeRTOS_printf( ( "Link Status is high\n" ) ) ;\r
+ }\r
+ else\r
+ {\r
+ /* For now pdFAIL will be returned. But prvEMACHandlerTask() is running\r
+ and it will keep on checking the PHY and set 'ulLinkStatusMask' when necessary. */\r
+ xResult = pdFAIL;\r
+ FreeRTOS_printf( ( "Link Status still low\n" ) ) ;\r
+ }\r
+ /* When returning non-zero, the stack will become active and\r
+ start DHCP (in configured) */\r
+ return xResult;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvDMATxDescListInit()\r
+{\r
+ETH_DMADescTypeDef *pxDMADescriptor;\r
+BaseType_t xIndex;\r
+\r
+ /* Get the pointer on the first member of the descriptor list */\r
+ pxDMADescriptor = DMATxDscrTab;\r
+\r
+ /* Fill each DMA descriptor with the right values */\r
+ for( xIndex = 0; xIndex < ETH_TXBUFNB; xIndex++, pxDMADescriptor++ )\r
+ {\r
+ /* Set Second Address Chained bit */\r
+ pxDMADescriptor->Status = ETH_DMATXDESC_TCH;\r
+\r
+ #if( ipconfigZERO_COPY_TX_DRIVER == 0 )\r
+ {\r
+ /* Set Buffer1 address pointer */\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )( Tx_Buff[ xIndex ] );\r
+ }\r
+ #endif\r
+\r
+ if( xETH.Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE )\r
+ {\r
+ /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */\r
+ pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;\r
+ }\r
+\r
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
+ if( xIndex < ETH_TXBUFNB - 1 )\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMADescriptor + 1 );\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) DMATxDscrTab;\r
+ }\r
+ }\r
+\r
+ /* Set Transmit Descriptor List Address Register */\r
+ xETH.Instance->DMATDLAR = ( uint32_t ) DMATxDscrTab;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvDMARxDescListInit()\r
+{\r
+ETH_DMADescTypeDef *pxDMADescriptor;\r
+BaseType_t xIndex;\r
+ /*\r
+ * RX-descriptors.\r
+ */\r
+\r
+ /* Get the pointer on the first member of the descriptor list */\r
+ pxDMADescriptor = DMARxDscrTab;\r
+\r
+ /* Fill each DMA descriptor with the right values */\r
+ for( xIndex = 0; xIndex < ETH_RXBUFNB; xIndex++, pxDMADescriptor++ )\r
+ {\r
+\r
+ /* Set Buffer1 size and Second Address Chained bit */\r
+ pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | (uint32_t)ETH_RX_BUF_SIZE; \r
+\r
+ #if( ipconfigZERO_COPY_RX_DRIVER != 0 )\r
+ {\r
+ /* Set Buffer1 address pointer */\r
+ NetworkBufferDescriptor_t *pxBuffer;\r
+\r
+ pxBuffer = pxGetNetworkBufferWithDescriptor( ETH_RX_BUF_SIZE, 100ul );\r
+ /* If the assert below fails, make sure that there are at least 'ETH_RXBUFNB'\r
+ Network Buffers available during start-up ( ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ) */\r
+ configASSERT( pxBuffer != NULL );\r
+ if( pxBuffer != NULL )\r
+ {\r
+ pxDMADescriptor->Buffer1Addr = (uint32_t)pxBuffer->pucEthernetBuffer;\r
+ pxDMADescriptor->Status = ETH_DMARXDESC_OWN;\r
+ }\r
+ }\r
+ #else\r
+ {\r
+ /* Set Buffer1 address pointer */\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )( Rx_Buff[ xIndex ] );\r
+ /* Set Own bit of the Rx descriptor Status */\r
+ pxDMADescriptor->Status = ETH_DMARXDESC_OWN;\r
+ }\r
+ #endif\r
+\r
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
+ if( xIndex < ETH_RXBUFNB - 1 )\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t )( pxDMADescriptor + 1 );\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) DMARxDscrTab;\r
+ }\r
+\r
+ }\r
+ /* Set Receive Descriptor List Address Register */\r
+ xETH.Instance->DMARDLAR = ( uint32_t ) DMARxDscrTab;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvMACAddressConfig(ETH_HandleTypeDef *heth, uint32_t ulIndex, uint8_t *Addr)\r
+{\r
+uint32_t ulTempReg;\r
+\r
+ /* Calculate the selected MAC address high register. */\r
+ ulTempReg = 0x80000000ul | ( ( uint32_t ) Addr[ 5 ] << 8 ) | ( uint32_t ) Addr[ 4 ];\r
+\r
+ /* Load the selected MAC address high register. */\r
+ ( *(__IO uint32_t *)( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + ulIndex ) ) ) = ulTempReg;\r
+\r
+ /* Calculate the selected MAC address low register. */\r
+ ulTempReg = ( ( uint32_t ) Addr[ 3 ] << 24 ) | ( ( uint32_t ) Addr[ 2 ] << 16 ) | ( ( uint32_t ) Addr[ 1 ] << 8 ) | Addr[ 0 ];\r
+\r
+ /* Load the selected MAC address low register */\r
+ ( *(__IO uint32_t *) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + ulIndex ) ) ) = ulTempReg;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxDescriptor, BaseType_t bReleaseAfterSend )\r
+{\r
+BaseType_t xReturn = pdFAIL;\r
+uint32_t ulTransmitSize = 0;\r
+__IO ETH_DMADescTypeDef *pxDmaTxDesc;\r
+/* Do not wait too long for a free TX DMA buffer. */\r
+const TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 50u );\r
+\r
+ #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 )\r
+ {\r
+ ProtocolPacket_t *pxPacket;\r
+\r
+ #if( ipconfigZERO_COPY_RX_DRIVER != 0 )\r
+ {\r
+ configASSERT( bReleaseAfterSend != 0 );\r
+ }\r
+ #endif /* ipconfigZERO_COPY_RX_DRIVER */\r
+\r
+ /* If the peripheral must calculate the checksum, it wants\r
+ the protocol checksum to have a value of zero. */\r
+ pxPacket = ( ProtocolPacket_t * ) ( pxDescriptor->pucEthernetBuffer );\r
+\r
+ if( pxPacket->xICMPPacket.xIPHeader.ucProtocol == ipPROTOCOL_ICMP )\r
+ {\r
+ pxPacket->xICMPPacket.xICMPHeader.usChecksum = ( uint16_t )0u;\r
+ }\r
+ }\r
+ #endif\r
+\r
+ /* Open a do {} while ( 0 ) loop to be able to call break. */\r
+ do\r
+ {\r
+ if( xPhyObject.ulLinkStatusMask != 0 )\r
+ {\r
+ if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS )\r
+ {\r
+ /* Time-out waiting for a free TX descriptor. */\r
+ break;\r
+ }\r
+\r
+ /* This function does the actual transmission of the packet. The packet is\r
+ contained in 'pxDescriptor' that is passed to the function. */\r
+ pxDmaTxDesc = xETH.TxDesc;\r
+\r
+ /* Is this buffer available? */\r
+ configASSERT ( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) == 0 );\r
+\r
+ {\r
+ /* Is this buffer available? */\r
+ /* Get bytes in current buffer. */\r
+ ulTransmitSize = pxDescriptor->xDataLength;\r
+\r
+ if( ulTransmitSize > ETH_TX_BUF_SIZE )\r
+ {\r
+ ulTransmitSize = ETH_TX_BUF_SIZE;\r
+ }\r
+\r
+ #if( ipconfigZERO_COPY_TX_DRIVER == 0 )\r
+ {\r
+ /* Copy the bytes. */\r
+ memcpy( ( void * ) pxDmaTxDesc->Buffer1Addr, pxDescriptor->pucEthernetBuffer, ulTransmitSize );\r
+ }\r
+ #else\r
+ {\r
+ /* Move the buffer. */\r
+ pxDmaTxDesc->Buffer1Addr = ( uint32_t )pxDescriptor->pucEthernetBuffer;\r
+ /* The Network Buffer has been passed to DMA, no need to release it. */\r
+ bReleaseAfterSend = pdFALSE_UNSIGNED;\r
+ }\r
+ #endif /* ipconfigZERO_COPY_TX_DRIVER */\r
+\r
+ /* Ask to set the IPv4 checksum.\r
+ Also need an Interrupt on Completion so that 'vClearTXBuffers()' will be called.. */\r
+ pxDmaTxDesc->Status |= ETH_DMATXDESC_CIC_TCPUDPICMP_FULL | ETH_DMATXDESC_IC;\r
+\r
+ /* Prepare transmit descriptors to give to DMA. */\r
+\r
+ /* Set LAST and FIRST segment */\r
+ pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;\r
+ /* Set frame size */\r
+ pxDmaTxDesc->ControlBufferSize = ( ulTransmitSize & ETH_DMATXDESC_TBS1 );\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN;\r
+\r
+ /* Point to next descriptor */\r
+ xETH.TxDesc = ( ETH_DMADescTypeDef * ) ( xETH.TxDesc->Buffer2NextDescAddr );\r
+ /* Ensure completion of memory access */\r
+ __DSB();\r
+ /* Resume DMA transmission*/\r
+ xETH.Instance->DMATPDR = 0;\r
+ iptraceNETWORK_INTERFACE_TRANSMIT();\r
+ xReturn = pdPASS;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* The PHY has no Link Status, packet shall be dropped. */\r
+ }\r
+ } while( 0 );\r
+ /* The buffer has been sent so can be released. */\r
+ if( bReleaseAfterSend != pdFALSE )\r
+ {\r
+ vReleaseNetworkBufferAndDescriptor( pxDescriptor );\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static BaseType_t xMayAcceptPacket( uint8_t *pcBuffer )\r
+{\r
+const ProtocolPacket_t *pxProtPacket = ( const ProtocolPacket_t * )pcBuffer;\r
+\r
+ switch( pxProtPacket->xTCPPacket.xEthernetHeader.usFrameType )\r
+ {\r
+ case ipARP_FRAME_TYPE:\r
+ /* Check it later. */\r
+ return pdTRUE;\r
+ case ipIPv4_FRAME_TYPE:\r
+ /* Check it here. */\r
+ break;\r
+ default:\r
+ /* Refuse the packet. */\r
+ return pdFALSE;\r
+ }\r
+\r
+ #if( ipconfigETHERNET_DRIVER_FILTERS_PACKETS == 1 )\r
+ {\r
+ const IPHeader_t *pxIPHeader = &(pxProtPacket->xTCPPacket.xIPHeader);\r
+ uint32_t ulDestinationIPAddress;\r
+\r
+ /* Ensure that the incoming packet is not fragmented (only outgoing packets\r
+ * can be fragmented) as these are the only handled IP frames currently. */\r
+ if( ( pxIPHeader->usFragmentOffset & FreeRTOS_ntohs( ipFRAGMENT_OFFSET_BIT_MASK ) ) != 0U )\r
+ {\r
+ return pdFALSE;\r
+ }\r
+ /* HT: Might want to make the following configurable because\r
+ * most IP messages have a standard length of 20 bytes */\r
+\r
+ /* 0x45 means: IPv4 with an IP header of 5 x 4 = 20 bytes\r
+ * 0x47 means: IPv4 with an IP header of 7 x 4 = 28 bytes */\r
+ if( pxIPHeader->ucVersionHeaderLength < 0x45 || pxIPHeader->ucVersionHeaderLength > 0x4F )\r
+ {\r
+ return pdFALSE;\r
+ }\r
+\r
+ ulDestinationIPAddress = pxIPHeader->ulDestinationIPAddress;\r
+ /* Is the packet for this node? */\r
+ if( ( ulDestinationIPAddress != *ipLOCAL_IP_ADDRESS_POINTER ) &&\r
+ /* Is it a broadcast address x.x.x.255 ? */\r
+ ( ( FreeRTOS_ntohl( ulDestinationIPAddress ) & 0xff ) != 0xff ) &&\r
+ #if( ipconfigUSE_LLMNR == 1 )\r
+ ( ulDestinationIPAddress != ipLLMNR_IP_ADDR ) &&\r
+ #endif\r
+ ( *ipLOCAL_IP_ADDRESS_POINTER != 0 ) ) {\r
+ FreeRTOS_printf( ( "Drop IP %lxip\n", FreeRTOS_ntohl( ulDestinationIPAddress ) ) );\r
+ return pdFALSE;\r
+ }\r
+\r
+ if( pxIPHeader->ucProtocol == ipPROTOCOL_UDP )\r
+ {\r
+ uint16_t port = pxProtPacket->xUDPPacket.xUDPHeader.usDestinationPort;\r
+\r
+ if( ( xPortHasUDPSocket( port ) == pdFALSE )\r
+ #if ipconfigUSE_LLMNR == 1\r
+ && ( port != FreeRTOS_ntohs( ipLLMNR_PORT ) )\r
+ #endif\r
+ #if ipconfigUSE_NBNS == 1\r
+ && ( port != FreeRTOS_ntohs( ipNBNS_PORT ) )\r
+ #endif\r
+ #if ipconfigUSE_DNS == 1\r
+ && ( pxProtPacket->xUDPPacket.xUDPHeader.usSourcePort != FreeRTOS_ntohs( ipDNS_PORT ) )\r
+ #endif\r
+ ) {\r
+ /* Drop this packet, not for this device. */\r
+ return pdFALSE;\r
+ }\r
+ }\r
+ }\r
+ #endif /* ipconfigETHERNET_DRIVER_FILTERS_PACKETS */\r
+ return pdTRUE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static BaseType_t prvNetworkInterfaceInput( void )\r
+{\r
+NetworkBufferDescriptor_t *pxCurDescriptor;\r
+NetworkBufferDescriptor_t *pxNewDescriptor = NULL;\r
+BaseType_t xReceivedLength, xAccepted;\r
+__IO ETH_DMADescTypeDef *pxDMARxDescriptor;\r
+xIPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL };\r
+const TickType_t xDescriptorWaitTime = pdMS_TO_TICKS( 250 );\r
+uint8_t *pucBuffer;\r
+\r
+ pxDMARxDescriptor = xETH.RxDesc;\r
+\r
+ if( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_OWN) == 0 )\r
+ {\r
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r
+ xReceivedLength = ( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4;\r
+\r
+ pucBuffer = (uint8_t *) pxDMARxDescriptor->Buffer1Addr;\r
+\r
+ /* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */\r
+ /* Chained Mode */ \r
+ /* Selects the next DMA Rx descriptor list for next buffer to read */ \r
+ xETH.RxDesc = ( ETH_DMADescTypeDef* )pxDMARxDescriptor->Buffer2NextDescAddr;\r
+ }\r
+ else\r
+ {\r
+ xReceivedLength = 0;\r
+ }\r
+\r
+ /* Obtain the size of the packet and put it into the "usReceivedLength" variable. */\r
+\r
+ /* get received frame */\r
+ if( xReceivedLength > 0ul )\r
+ {\r
+ /* In order to make the code easier and faster, only packets in a single buffer\r
+ will be accepted. This can be done by making the buffers large enough to\r
+ hold a complete Ethernet packet (1536 bytes).\r
+ Therefore, two sanity checks: */\r
+ configASSERT( xReceivedLength <= ETH_RX_BUF_SIZE );\r
+\r
+ if( ( pxDMARxDescriptor->Status & ( ETH_DMARXDESC_CE | ETH_DMARXDESC_IPV4HCE | ETH_DMARXDESC_FT ) ) != ETH_DMARXDESC_FT )\r
+ {\r
+ /* Not an Ethernet frame-type or a checmsum error. */\r
+ xAccepted = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ /* See if this packet must be handled. */\r
+ xAccepted = xMayAcceptPacket( pucBuffer );\r
+ }\r
+\r
+ if( xAccepted != pdFALSE )\r
+ {\r
+ /* The packet wil be accepted, but check first if a new Network Buffer can\r
+ be obtained. If not, the packet will still be dropped. */\r
+ pxNewDescriptor = pxGetNetworkBufferWithDescriptor( ETH_RX_BUF_SIZE, xDescriptorWaitTime );\r
+\r
+ if( pxNewDescriptor == NULL )\r
+ {\r
+ /* A new descriptor can not be allocated now. This packet will be dropped. */\r
+ xAccepted = pdFALSE;\r
+ }\r
+ }\r
+ #if( ipconfigZERO_COPY_RX_DRIVER != 0 )\r
+ {\r
+ /* Find out which Network Buffer was originally passed to the descriptor. */\r
+ pxCurDescriptor = pxPacketBuffer_to_NetworkBuffer( pucBuffer );\r
+ configASSERT( pxCurDescriptor != NULL );\r
+ }\r
+ #else\r
+ {\r
+ /* In this mode, the two descriptors are the same. */\r
+ pxCurDescriptor = pxNewDescriptor;\r
+ if( pxNewDescriptor != NULL )\r
+ {\r
+ /* The packet is acepted and a new Network Buffer was created,\r
+ copy data to the Network Bufffer. */\r
+ memcpy( pxNewDescriptor->pucEthernetBuffer, pucBuffer, xReceivedLength );\r
+ }\r
+ }\r
+ #endif\r
+\r
+ if( xAccepted != pdFALSE )\r
+ {\r
+ pxCurDescriptor->xDataLength = xReceivedLength;\r
+ xRxEvent.pvData = ( void * ) pxCurDescriptor;\r
+\r
+ /* Pass the data to the TCP/IP task for processing. */\r
+ if( xSendEventStructToIPTask( &xRxEvent, xDescriptorWaitTime ) == pdFALSE )\r
+ {\r
+ /* Could not send the descriptor into the TCP/IP stack, it\r
+ must be released. */\r
+ vReleaseNetworkBufferAndDescriptor( pxCurDescriptor );\r
+ iptraceETHERNET_RX_EVENT_LOST();\r
+ }\r
+ else\r
+ {\r
+ iptraceNETWORK_INTERFACE_RECEIVE();\r
+ }\r
+ }\r
+\r
+ /* Release descriptors to DMA */\r
+ #if( ipconfigZERO_COPY_RX_DRIVER != 0 )\r
+ {\r
+ /* Set Buffer1 address pointer */\r
+ if( pxNewDescriptor != NULL )\r
+ {\r
+ pxDMARxDescriptor->Buffer1Addr = (uint32_t)pxNewDescriptor->pucEthernetBuffer;\r
+ }\r
+ else\r
+ {\r
+ /* The packet was dropped and the same Network\r
+ Buffer will be used to receive a new packet. */\r
+ }\r
+ }\r
+ #endif /* ipconfigZERO_COPY_RX_DRIVER */\r
+\r
+ /* Set Buffer1 size and Second Address Chained bit */\r
+ pxDMARxDescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | (uint32_t)ETH_RX_BUF_SIZE; \r
+ pxDMARxDescriptor->Status = ETH_DMARXDESC_OWN;\r
+\r
+ /* Ensure completion of memory access */\r
+ __DSB();\r
+ /* When Rx Buffer unavailable flag is set clear it and resume\r
+ reception. */\r
+ if( ( xETH.Instance->DMASR & ETH_DMASR_RBUS ) != 0 )\r
+ {\r
+ /* Clear RBUS ETHERNET DMA flag. */\r
+ xETH.Instance->DMASR = ETH_DMASR_RBUS;\r
+\r
+ /* Resume DMA reception. */\r
+ xETH.Instance->DMARPDR = 0;\r
+ }\r
+ }\r
+\r
+ return ( xReceivedLength > 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+BaseType_t xSTM32_PhyRead( BaseType_t xAddress, BaseType_t xRegister, uint32_t *pulValue )\r
+{\r
+uint16_t usPrevAddress = xETH.Init.PhyAddress;\r
+BaseType_t xResult;\r
+HAL_StatusTypeDef xHALResult;\r
+\r
+ xETH.Init.PhyAddress = xAddress;\r
+ xHALResult = HAL_ETH_ReadPHYRegister( &xETH, ( uint16_t )xRegister, pulValue );\r
+ xETH.Init.PhyAddress = usPrevAddress;\r
+\r
+ if( xHALResult == HAL_OK )\r
+ {\r
+ xResult = 0;\r
+ }\r
+ else\r
+ {\r
+ xResult = -1;\r
+ }\r
+ return xResult;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xSTM32_PhyWrite( BaseType_t xAddress, BaseType_t xRegister, uint32_t ulValue )\r
+{\r
+uint16_t usPrevAddress = xETH.Init.PhyAddress;\r
+BaseType_t xResult;\r
+HAL_StatusTypeDef xHALResult;\r
+\r
+ xETH.Init.PhyAddress = xAddress;\r
+ xHALResult = HAL_ETH_WritePHYRegister( &xETH, ( uint16_t )xRegister, ulValue );\r
+ xETH.Init.PhyAddress = usPrevAddress;\r
+\r
+ if( xHALResult == HAL_OK )\r
+ {\r
+ xResult = 0;\r
+ }\r
+ else\r
+ {\r
+ xResult = -1;\r
+ }\r
+ return xResult;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void phy_test()\r
+{\r
+BaseType_t xPhyCount;\r
+BaseType_t xPhyIndex;\r
+\r
+ vPhyInitialise( &xPhyObject, xSTM32_PhyRead, xSTM32_PhyWrite );\r
+ xPhyCount = xPhyDiscover( &xPhyObject );\r
+ FreeRTOS_printf( ( "PHY count %ld\n", xPhyCount ) );\r
+ for( xPhyIndex = 0; xPhyIndex < xPhyCount; xPhyIndex++ )\r
+ {\r
+ FreeRTOS_printf( ( "PHY[%d] at address %d ( 0x%08X )\n",\r
+ xPhyIndex,\r
+ xPhyObject.ucPhyIndexes[ xPhyIndex ],\r
+ xPhyObject.ulPhyIDs[ xPhyIndex ] ) );\r
+\r
+ }\r
+ \r
+}\r
+\r
+void vMACBProbePhy( void )\r
+{\r
+ vPhyInitialise( &xPhyObject, xSTM32_PhyRead, xSTM32_PhyWrite );\r
+ xPhyDiscover( &xPhyObject );\r
+ xPhyConfigure( &xPhyObject, &xPHYProperties );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvEthernetUpdateConfig( BaseType_t xForce )\r
+{\r
+ FreeRTOS_printf( ( "prvEthernetUpdateConfig: LS mask %02X Force %d\n",\r
+ xPhyObject.ulLinkStatusMask,\r
+ ( int )xForce ) );\r
+\r
+ if( ( xForce != pdFALSE ) || ( xPhyObject.ulLinkStatusMask != 0 ) )\r
+ {\r
+ /* Restart the auto-negotiation. */\r
+ if( xETH.Init.AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE )\r
+ {\r
+ xPhyStartAutoNegotiation( &xPhyObject, xPhyGetMask( &xPhyObject ) );\r
+\r
+ /* Configure the MAC with the Duplex Mode fixed by the\r
+ auto-negotiation process. */\r
+ if( xPhyObject.xPhyProperties.ucDuplex == PHY_DUPLEX_FULL )\r
+ {\r
+ xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX;\r
+ }\r
+ else\r
+ {\r
+ xETH.Init.DuplexMode = ETH_MODE_HALFDUPLEX;\r
+ }\r
+\r
+ /* Configure the MAC with the speed fixed by the\r
+ auto-negotiation process. */\r
+ if( xPhyObject.xPhyProperties.ucSpeed == PHY_SPEED_10 )\r
+ {\r
+ xETH.Init.Speed = ETH_SPEED_10M;\r
+ }\r
+ else\r
+ {\r
+ xETH.Init.Speed = ETH_SPEED_100M;\r
+ }\r
+ }\r
+ else /* AutoNegotiation Disable */\r
+ {\r
+ /* Check parameters */\r
+ assert_param( IS_ETH_SPEED( xETH.Init.Speed ) );\r
+ assert_param( IS_ETH_DUPLEX_MODE( xETH.Init.DuplexMode ) );\r
+\r
+ if( xETH.Init.DuplexMode == ETH_MODE_FULLDUPLEX )\r
+ {\r
+ xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_HALF;\r
+ }\r
+ else\r
+ {\r
+ xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_FULL;\r
+ }\r
+\r
+ if( xETH.Init.Speed == ETH_SPEED_10M )\r
+ {\r
+ xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_10;\r
+ }\r
+ else\r
+ {\r
+ xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_100;\r
+ }\r
+\r
+ xPhyObject.xPhyPreferences.ucMDI_X = PHY_MDIX_AUTO;\r
+\r
+ /* Use predefined (fixed) configuration. */\r
+ xPhyFixedValue( &xPhyObject, xPhyGetMask( &xPhyObject ) );\r
+ }\r
+\r
+ /* ETHERNET MAC Re-Configuration */\r
+ HAL_ETH_ConfigMAC( &xETH, (ETH_MACInitTypeDef *) NULL);\r
+\r
+ /* Restart MAC interface */\r
+ HAL_ETH_Start( &xETH);\r
+ }\r
+ else\r
+ {\r
+ /* Stop MAC interface */\r
+ HAL_ETH_Stop( &xETH );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xGetPhyLinkStatus( void )\r
+{\r
+BaseType_t xReturn;\r
+\r
+ if( xPhyObject.ulLinkStatusMask != 0 )\r
+ {\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#define niBUFFER_1_PACKET_SIZE 1536\r
+\r
+static __attribute__ ((section(".first_data"))) uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS * niBUFFER_1_PACKET_SIZE ] __attribute__ ( ( aligned( 32 ) ) );\r
+\r
+void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] )\r
+{\r
+\r
+uint8_t *ucRAMBuffer = ucNetworkPackets;\r
+uint32_t ul;\r
+\r
+ for( ul = 0; ul < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; ul++ )\r
+ {\r
+ pxNetworkBuffers[ ul ].pucEthernetBuffer = ucRAMBuffer + ipBUFFER_PADDING;\r
+ *( ( unsigned * ) ucRAMBuffer ) = ( unsigned ) ( &( pxNetworkBuffers[ ul ] ) );\r
+ ucRAMBuffer += niBUFFER_1_PACKET_SIZE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvEMACHandlerTask( void *pvParameters )\r
+{\r
+UBaseType_t uxLastMinBufferCount = 0;\r
+#if( ipconfigCHECK_IP_QUEUE_SPACE != 0 )\r
+UBaseType_t uxLastMinQueueSpace = 0;\r
+#endif\r
+UBaseType_t uxCurrentCount;\r
+BaseType_t xResult;\r
+const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL );\r
+\r
+ /* Remove compiler warnings about unused parameters. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ xResult = 0;\r
+ uxCurrentCount = uxGetMinimumFreeNetworkBuffers();\r
+ if( uxLastMinBufferCount != uxCurrentCount )\r
+ {\r
+ /* The logging produced below may be helpful\r
+ while tuning +TCP: see how many buffers are in use. */\r
+ uxLastMinBufferCount = uxCurrentCount;\r
+ FreeRTOS_printf( ( "Network buffers: %lu lowest %lu\n",\r
+ uxGetNumberOfFreeNetworkBuffers(), uxCurrentCount ) );\r
+ }\r
+\r
+ if( xTXDescriptorSemaphore != NULL )\r
+ {\r
+ static UBaseType_t uxLowestSemCount = ( UBaseType_t ) ETH_TXBUFNB - 1;\r
+\r
+ uxCurrentCount = uxSemaphoreGetCount( xTXDescriptorSemaphore );\r
+ if( uxLowestSemCount > uxCurrentCount )\r
+ {\r
+ uxLowestSemCount = uxCurrentCount;\r
+ FreeRTOS_printf( ( "TX DMA buffers: lowest %lu\n", uxLowestSemCount ) );\r
+ }\r
+\r
+ }\r
+\r
+ #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 )\r
+ {\r
+ uxCurrentCount = uxGetMinimumIPQueueSpace();\r
+ if( uxLastMinQueueSpace != uxCurrentCount )\r
+ {\r
+ /* The logging produced below may be helpful\r
+ while tuning +TCP: see how many buffers are in use. */\r
+ uxLastMinQueueSpace = uxCurrentCount;\r
+ FreeRTOS_printf( ( "Queue space: lowest %lu\n", uxCurrentCount ) );\r
+ }\r
+ }\r
+ #endif /* ipconfigCHECK_IP_QUEUE_SPACE */\r
+\r
+ if( ( ulISREvents & EMAC_IF_ALL_EVENT ) == 0 )\r
+ {\r
+ /* No events to process now, wait for the next. */\r
+ ulTaskNotifyTake( pdFALSE, ulMaxBlockTime );\r
+ }\r
+\r
+ if( ( ulISREvents & EMAC_IF_RX_EVENT ) != 0 )\r
+ {\r
+ ulISREvents &= ~EMAC_IF_RX_EVENT;\r
+\r
+ xResult = prvNetworkInterfaceInput();\r
+ if( xResult > 0 )\r
+ {\r
+ while( prvNetworkInterfaceInput() > 0 )\r
+ {\r
+ }\r
+ }\r
+ }\r
+\r
+ if( ( ulISREvents & EMAC_IF_TX_EVENT ) != 0 )\r
+ {\r
+ /* Code to release TX buffers if zero-copy is used. */\r
+ ulISREvents &= ~EMAC_IF_TX_EVENT;\r
+ /* Check if DMA packets have been delivered. */\r
+ vClearTXBuffers();\r
+ }\r
+\r
+ if( ( ulISREvents & EMAC_IF_ERR_EVENT ) != 0 )\r
+ {\r
+ /* Future extension: logging about errors that occurred. */\r
+ ulISREvents &= ~EMAC_IF_ERR_EVENT;\r
+ }\r
+ if( xPhyCheckLinkStatus( &xPhyObject, xResult ) != 0 )\r
+ {\r
+ /* Something has changed to a Link Status, need re-check. */\r
+ prvEthernetUpdateConfig( pdFALSE );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void ETH_IRQHandler( void )\r
+{\r
+ HAL_ETH_IRQHandler( &xETH );\r
+}\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_eth.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 26-June-2015\r
+ * @brief ETH HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Ethernet (ETH) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions \r
+ * + Peripheral State and Errors functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#)Declare a ETH_HandleTypeDef handle structure, for example:\r
+ ETH_HandleTypeDef heth;\r
+ \r
+ (#)Fill parameters of Init structure in heth handle\r
+ \r
+ (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) \r
+\r
+ (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:\r
+ (##) Enable the Ethernet interface clock using \r
+ (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();\r
+ (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();\r
+ (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();\r
+ \r
+ (##) Initialize the related GPIO clocks\r
+ (##) Configure Ethernet pin-out\r
+ (##) Configure Ethernet NVIC interrupt (IT mode) \r
+ \r
+ (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:\r
+ (##) HAL_ETH_DMATxDescListInit(); for Transmission process\r
+ (##) HAL_ETH_DMARxDescListInit(); for Reception process\r
+\r
+ (#)Enable MAC and DMA transmission and reception:\r
+ (##) HAL_ETH_Start();\r
+\r
+ (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer \r
+ the frame to MAC TX FIFO:\r
+ (##) HAL_ETH_TransmitFrame();\r
+\r
+ (#)Poll for a received frame in ETH RX DMA Descriptors and get received \r
+ frame parameters\r
+ (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)\r
+\r
+ (#) Get a received frame when an ETH RX interrupt occurs:\r
+ (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)\r
+\r
+ (#) Communicate with external PHY device:\r
+ (##) Read a specific register from the PHY \r
+ HAL_ETH_ReadPHYRegister();\r
+ (##) Write data to a specific RHY register:\r
+ HAL_ETH_WritePHYRegister();\r
+\r
+ (#) Configure the Ethernet MAC after ETH peripheral initialization\r
+ HAL_ETH_ConfigMAC(); all MAC parameters should be filled.\r
+ \r
+ (#) Configure the Ethernet DMA after ETH peripheral initialization\r
+ HAL_ETH_ConfigDMA(); all DMA parameters should be filled.\r
+\r
+ -@- The PTP protocol and the DMA descriptors ring mode are not supported\r
+ in this driver\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+\r
+int lUDPLoggingPrintf( const char *pcFormatString, ... );\r
+\r
+/** @addtogroup STM32F4xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH ETH\r
+ * @brief ETH HAL module driver\r
+ * @{\r
+ */\r
+\r
+#if !defined( ARRAY_SIZE )\r
+ #define ARRAY_SIZE( x ) ( sizeof ( x ) / sizeof ( x )[ 0 ] )\r
+#endif\r
+\r
+#ifdef HAL_ETH_MODULE_ENABLED\r
+\r
+#if defined(STM32F7xx)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup ETH_Private_Constants ETH Private Constants\r
+ * @{\r
+ */\r
+#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */\r
+#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup ETH_Private_Functions ETH Private Functions\r
+ * @{\r
+ */\r
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);\r
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);\r
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup ETH_Exported_Functions ETH Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the Ethernet peripheral\r
+ (+) De-initialize the Ethernet peripheral\r
+\r
+ @endverbatim\r
+ * @{\r
+ */\r
+extern void vMACBProbePhy ( void );\r
+\r
+/**\r
+ * @brief Initializes the Ethernet MAC and DMA according to default\r
+ * parameters.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ uint32_t hclk = 60000000;\r
+ uint32_t err = ETH_SUCCESS;\r
+\r
+ /* Check the ETH peripheral state */\r
+ if( heth == NULL )\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));\r
+ assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));\r
+ assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));\r
+ assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));\r
+\r
+ if( heth->State == HAL_ETH_STATE_RESET )\r
+ {\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC. */\r
+ HAL_ETH_MspInit( heth );\r
+ }\r
+\r
+ /* Enable SYSCFG Clock */\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+\r
+ /* Select MII or RMII Mode*/\r
+ SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);\r
+ SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;\r
+\r
+ /* Ethernet Software reset */\r
+ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */\r
+ /* After reset all the registers holds their respective reset values */\r
+ /* Also enable EDFE: Enhanced descriptor format enable. */\r
+// heth->Instance->DMABMR |= ETH_DMABMR_SR | ETH_DMABMR_EDE;\r
+ heth->Instance->DMABMR |= ETH_DMABMR_SR;\r
+\r
+ /* Wait for software reset */\r
+ while ((heth->Instance->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)\r
+ {\r
+ }\r
+\r
+ /*-------------------------------- MAC Initialization ----------------------*/\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+ /* Clear CSR Clock Range CR[2:0] bits */\r
+ tmpreg &= ETH_MACMIIAR_CR_MASK;\r
+\r
+ /* Get hclk frequency value (168,000,000) */\r
+ hclk = HAL_RCC_GetHCLKFreq();\r
+\r
+ /* Set CR bits depending on hclk value */\r
+ if( ( hclk >= 20000000 ) && ( hclk < 35000000 ) )\r
+ {\r
+ /* CSR Clock Range between 20-35 MHz */\r
+ tmpreg |= (uint32_t) ETH_MACMIIAR_CR_Div16;\r
+ }\r
+ else if( ( hclk >= 35000000 ) && ( hclk < 60000000 ) )\r
+ {\r
+ /* CSR Clock Range between 35-60 MHz */\r
+ tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div26;\r
+ }\r
+ else if((hclk >= 60000000 ) && ( hclk < 100000000 ) )\r
+ {\r
+ /* CSR Clock Range between 60-100 MHz */\r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;\r
+ }\r
+ else if((hclk >= 100000000 ) && ( hclk < 150000000))\r
+ {\r
+ /* CSR Clock Range between 100-150 MHz */\r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;\r
+ }\r
+ else /* ((hclk >= 150000000 ) && ( hclk <= 168000000)) */\r
+ {\r
+ /* CSR Clock Range between 150-168 MHz */\r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;\r
+ }\r
+\r
+ /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */\r
+ heth->Instance->MACMIIAR = (uint32_t)tmpreg;\r
+\r
+ /* Initialise the MACB and set all PHY properties */\r
+ vMACBProbePhy();\r
+\r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief De-Initializes the ETH peripheral.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */\r
+ HAL_ETH_MspDeInit( heth );\r
+\r
+ /* Set ETH HAL state to Disabled */\r
+ heth->State= HAL_ETH_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Tx descriptors in chain mode.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param DMATxDescTab: Pointer to the first Tx desc list\r
+ * @param TxBuff: Pointer to the first TxBuffer list\r
+ * @param TxBuffCount: Number of the used Tx desc in the list\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADescTypeDef *pxDMADescriptor;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Set the TxDesc pointer with the first one of the pxDMATable list */\r
+ heth->TxDesc = pxDMATable;\r
+\r
+ /* Fill each DMA descriptor with the right values */\r
+ for( i=0; i < ulBufferCount; i++ )\r
+ {\r
+ /* Get the pointer on the ith member of the descriptor list */\r
+ pxDMADescriptor = pxDMATable + i;\r
+\r
+ /* Set Second Address Chained bit */\r
+ pxDMADescriptor->Status = ETH_DMATXDESC_TCH;\r
+\r
+ pxDMADescriptor->ControlBufferSize = 0;\r
+\r
+ /* Set Buffer1 address pointer */\r
+ if( ucDataBuffer != NULL )\r
+ {\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_TX_BUF_SIZE ] );\r
+ }\r
+ else\r
+ {\r
+ /* Buffer space is not provided because it uses zero-copy transmissions. */\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )0u;\r
+ }\r
+\r
+ if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)\r
+ {\r
+ /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */\r
+ pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;\r
+ }\r
+\r
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
+ if(i < ( ulBufferCount - 1 ) )\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMATable + i + 1 );\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable;\r
+ }\r
+ }\r
+\r
+ /* Set Transmit Descriptor List Address Register */\r
+ heth->Instance->DMATDLAR = ( uint32_t ) pxDMATable;\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Rx descriptors in chain mode.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param DMARxDescTab: Pointer to the first Rx desc list\r
+ * @param RxBuff: Pointer to the first RxBuffer list\r
+ * @param RxBuffCount: Number of the used Rx desc in the list\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADescTypeDef *pxDMADescriptor;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Set the RxDesc pointer with the first one of the pxDMATable list */\r
+ heth->RxDesc = pxDMATable;\r
+\r
+ /* Fill each DMA descriptor with the right values */\r
+ for(i=0; i < ulBufferCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the descriptor list */\r
+ pxDMADescriptor = pxDMATable+i;\r
+\r
+ /* Set Own bit of the Rx descriptor Status */\r
+ pxDMADescriptor->Status = ETH_DMARXDESC_OWN;\r
+\r
+ /* Set Buffer1 size and Second Address Chained bit */\r
+ pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;\r
+\r
+ /* Set Buffer1 address pointer */\r
+ if( ucDataBuffer != NULL )\r
+ {\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_RX_BUF_SIZE ] );\r
+ }\r
+ else\r
+ {\r
+ /* Buffer space is not provided because it uses zero-copy reception. */\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )0u;\r
+ }\r
+\r
+ if( heth->Init.RxMode == ETH_RXINTERRUPT_MODE )\r
+ {\r
+ /* Enable Ethernet DMA Rx Descriptor interrupt */\r
+ pxDMADescriptor->ControlBufferSize &= ~ETH_DMARXDESC_DIC;\r
+ }\r
+\r
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
+ if(i < (ulBufferCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = (uint32_t)(pxDMATable+i+1);\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable;\r
+ }\r
+ }\r
+\r
+ /* Set Receive Descriptor List Address Register */\r
+ heth->Instance->DMARDLAR = ( uint32_t ) pxDMATable;\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ETH MSP.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes ETH MSP.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group2 IO operation functions\r
+ * @brief Data transfers functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Transmit a frame\r
+ HAL_ETH_TransmitFrame();\r
+ (+) Receive a frame\r
+ HAL_ETH_GetReceivedFrame();\r
+ HAL_ETH_GetReceivedFrame_IT();\r
+ (+) Read from an External PHY register\r
+ HAL_ETH_ReadPHYRegister();\r
+ (+) Write to an External PHY register\r
+ HAL_ETH_WritePHYRegister();\r
+\r
+ @endverbatim\r
+\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sends an Ethernet frame.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param FrameLength: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)\r
+{\r
+ uint32_t bufcount = 0, size = 0, i = 0;\r
+ __IO ETH_DMADescTypeDef *pxDmaTxDesc = heth->TxDesc;\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ if( FrameLength == 0 )\r
+ {\r
+ /* Set ETH HAL state to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */\r
+ if( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) != ( uint32_t ) RESET )\r
+ {\r
+ /* OWN bit set */\r
+ heth->State = HAL_ETH_STATE_BUSY_TX;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Get the number of needed Tx buffers for the current frame, rounding up. */\r
+ bufcount = ( FrameLength + ETH_TX_BUF_SIZE - 1 ) / ETH_TX_BUF_SIZE;\r
+\r
+ if (bufcount == 1)\r
+ {\r
+ /* Set LAST and FIRST segment */\r
+ pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;\r
+ /* Set frame size */\r
+ pxDmaTxDesc->ControlBufferSize = ( FrameLength & ETH_DMATXDESC_TBS1 );\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN;\r
+ /* Point to next descriptor */\r
+ heth->TxDesc = ( ETH_DMADescTypeDef * ) ( heth->TxDesc->Buffer2NextDescAddr );\r
+ }\r
+ else\r
+ {\r
+ for( i = 0; i < bufcount; i++ )\r
+ {\r
+ /* Clear FIRST and LAST segment bits */\r
+ uint32_t ulStatus = heth->TxDesc->Status & ~( ETH_DMATXDESC_FS | ETH_DMATXDESC_LS );\r
+\r
+ if( i == 0 )\r
+ {\r
+ /* Setting the first segment bit */\r
+ heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_FS;\r
+ }\r
+\r
+ /* Program size */\r
+ if (i < (bufcount-1))\r
+ {\r
+ heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);\r
+ }\r
+ else\r
+ {\r
+ /* Setting the last segment bit */\r
+ heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_LS;\r
+ size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;\r
+ heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);\r
+ }\r
+\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ heth->TxDesc->Status |= ETH_DMATXDESC_OWN;\r
+ /* point to next descriptor */\r
+ heth->TxDesc = (ETH_DMADescTypeDef *)( heth->TxDesc->Buffer2NextDescAddr );\r
+ }\r
+ }\r
+\r
+ __DSB();\r
+\r
+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */\r
+ if( ( heth->Instance->DMASR & ETH_DMASR_TBUS ) != ( uint32_t )RESET )\r
+ {\r
+ heth->Instance->DMACHTDR = ( uint32_t )pxDmaTxDesc;\r
+\r
+ /* Clear TBUS ETHERNET DMA flag */\r
+ heth->Instance->DMASR = ETH_DMASR_TBUS;\r
+ /* Resume DMA transmission*/\r
+ heth->Instance->DMATPDR = 0;\r
+ }\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Checks for received frames.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT( ETH_HandleTypeDef *heth )\r
+{\r
+ return HAL_ETH_GetReceivedFrame( heth );\r
+}\r
+\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame( ETH_HandleTypeDef *heth )\r
+{\r
+uint32_t ulCounter = 0;\r
+ETH_DMADescTypeDef *pxDescriptor = heth->RxDesc;\r
+HAL_StatusTypeDef xResult = HAL_ERROR;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Check the ETH state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Scan descriptors owned by CPU */\r
+ while( ( ( pxDescriptor->Status & ETH_DMARXDESC_OWN ) == 0ul ) && ( ulCounter < ETH_RXBUFNB ) )\r
+ {\r
+ uint32_t ulStatus = pxDescriptor->Status;\r
+\r
+ /* Just for security. */\r
+ ulCounter++;\r
+\r
+ if( ( ulStatus & ( ETH_DMARXDESC_FS | ETH_DMARXDESC_LS ) ) == ( uint32_t )ETH_DMARXDESC_FS )\r
+ {\r
+ /* First segment in frame, but not the last. */\r
+ heth->RxFrameInfos.FSRxDesc = pxDescriptor;\r
+ heth->RxFrameInfos.LSRxDesc = ( ETH_DMADescTypeDef *)NULL;\r
+ heth->RxFrameInfos.SegCount = 1;\r
+ /* Point to next descriptor. */\r
+ pxDescriptor = (ETH_DMADescTypeDef*) (pxDescriptor->Buffer2NextDescAddr);\r
+ heth->RxDesc = pxDescriptor;\r
+ }\r
+ else if( ( ulStatus & ( ETH_DMARXDESC_LS | ETH_DMARXDESC_FS ) ) == 0ul )\r
+ {\r
+ /* This is an intermediate segment, not first, not last. */\r
+ /* Increment segment count. */\r
+ heth->RxFrameInfos.SegCount++;\r
+ /* Move to the next descriptor. */\r
+ pxDescriptor = ( ETH_DMADescTypeDef * ) ( pxDescriptor->Buffer2NextDescAddr );\r
+ heth->RxDesc = pxDescriptor;\r
+ }\r
+ /* Must be a last segment */\r
+ else\r
+ {\r
+ /* This is the last segment. */\r
+ /* Check if last segment is first segment: one segment contains the frame */\r
+ if( heth->RxFrameInfos.SegCount == 0 )\r
+ {\r
+ /* Remember the first segment. */\r
+ heth->RxFrameInfos.FSRxDesc = pxDescriptor;\r
+ }\r
+\r
+ /* Increment segment count */\r
+ heth->RxFrameInfos.SegCount++;\r
+\r
+ /* Remember the last segment. */\r
+ heth->RxFrameInfos.LSRxDesc = pxDescriptor;\r
+\r
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r
+ heth->RxFrameInfos.length =\r
+ ( ( ulStatus & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4;\r
+\r
+ /* Get the address of the buffer start address */\r
+ heth->RxFrameInfos.buffer = heth->RxFrameInfos.FSRxDesc->Buffer1Addr;\r
+\r
+ /* Point to next descriptor */\r
+ heth->RxDesc = ( ETH_DMADescTypeDef * ) pxDescriptor->Buffer2NextDescAddr;\r
+\r
+ /* Return OK status: a packet was received. */\r
+ xResult = HAL_OK;\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return xResult;\r
+}\r
+\r
+#if( STM32_ETHERNET_STATS != 0 )\r
+\r
+ volatile int rx_count, tx_count, int_count;\r
+ /**\r
+ * @brief This function handles ETH interrupt request.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+ volatile int int_counts[32];\r
+ volatile int tx_status[8];\r
+ volatile unsigned sr_history[32];\r
+ volatile int sr_head;\r
+ #define STM32_STAT_INC( x ) do { ( x )++; } while( 0 )\r
+\r
+#else\r
+ #define STM32_STAT_INC( x ) do { } while( 0 )\r
+#endif /* STM32_ETHERNET_STATS */\r
+\r
+#define ETH_DMA_ALL_INTS \\r
+ ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_AIS | ETH_DMA_IT_ER | \\r
+ ETH_DMA_IT_FBE | ETH_DMA_IT_ET | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \\r
+ ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T )\r
+\r
+//#define ETH_DMA_ALL_INTS ETH_DMA_IT_RBU | ETH_DMA_FLAG_T | ETH_DMA_FLAG_AIS\r
+\r
+#define INT_MASK ( ( uint32_t ) ~ ( ETH_DMA_IT_TBU ) )\r
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t dmasr;\r
+\r
+ STM32_STAT_INC( int_count );\r
+\r
+ dmasr = heth->Instance->DMASR & ETH_DMA_ALL_INTS;\r
+ heth->Instance->DMASR = dmasr;\r
+\r
+#if( STM32_ETHERNET_STATS != 0 )\r
+ if( sr_head < ARRAY_SIZE( sr_history ) )\r
+ {\r
+ sr_history[ sr_head++ ] = dmasr;\r
+ }\r
+\r
+ {\r
+ int i;\r
+ for (i = 0; i < 32; i++) {\r
+ if (dmasr & (1u << i)) {\r
+ int_counts[i]++;\r
+ }\r
+ }\r
+ tx_status[ ( dmasr >> 20 ) & 0x07 ]++;\r
+ }\r
+#endif\r
+\r
+ /* Frame received */\r
+ if( ( dmasr & ( ETH_DMA_FLAG_R | ETH_DMA_IT_RBU ) ) != 0 )\r
+ {\r
+ /* Receive complete callback */\r
+ HAL_ETH_RxCpltCallback( heth );\r
+ STM32_STAT_INC( rx_count );\r
+ }\r
+ /* Frame transmitted */\r
+ if( ( dmasr & ( ETH_DMA_FLAG_T ) ) != 0 )\r
+ {\r
+ /* Transfer complete callback */\r
+ HAL_ETH_TxCpltCallback( heth );\r
+ STM32_STAT_INC( tx_count );\r
+ }\r
+\r
+ /* ETH DMA Error */\r
+ if( ( dmasr & ( ETH_DMA_FLAG_AIS ) ) != 0 )\r
+ {\r
+ /* Ethernet Error callback */\r
+ HAL_ETH_ErrorCallback( heth );\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Ethernet transfer error callbacks\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Reads a PHY register\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.\r
+ * This parameter can be one of the following values:\r
+ * PHY_BCR: Transceiver Basic Control Register,\r
+ * PHY_BSR: Transceiver Basic Status Register.\r
+ * More PHY register could be read depending on the used PHY\r
+ * @param RegValue: PHY register value\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)\r
+{\r
+uint32_t tmpreg = 0;\r
+uint32_t tickstart = 0;\r
+HAL_StatusTypeDef xResult;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));\r
+\r
+ /* Check the ETH peripheral state */\r
+ if( heth->State == HAL_ETH_STATE_BUSY_RD )\r
+ {\r
+ xResult = HAL_BUSY;\r
+ }\r
+ else\r
+ {\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set ETH HAL State to BUSY_RD */\r
+ heth->State = HAL_ETH_STATE_BUSY_RD;\r
+\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~ETH_MACMIIAR_CR_MASK;\r
+\r
+ /* Prepare the MII address register value */\r
+ tmpreg |= ( ( ( uint32_t )heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA ); /* Set the PHY device address */\r
+ tmpreg |= ( ( ( uint32_t )PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */\r
+ tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+\r
+ /* Write the result value into the MII Address register */\r
+ heth->Instance->MACMIIAR = tmpreg;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check for the Busy flag */\r
+ while( 1 )\r
+ {\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul )\r
+ {\r
+ /* Get MACMIIDR value */\r
+ *RegValue = ( uint32_t ) heth->Instance->MACMIIDR;\r
+ xResult = HAL_OK;\r
+ break;\r
+ }\r
+ /* Check for the Timeout */\r
+ if( ( HAL_GetTick( ) - tickstart ) > PHY_READ_TO )\r
+ {\r
+ xResult = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+\r
+ }\r
+\r
+ /* Set ETH HAL State to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+ }\r
+\r
+ if( xResult != HAL_OK )\r
+ {\r
+ lUDPLoggingPrintf( "ReadPHY: %d\n", xResult );\r
+ }\r
+ /* Return function status */\r
+ return xResult;\r
+}\r
+\r
+/**\r
+ * @brief Writes to a PHY register.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.\r
+ * This parameter can be one of the following values:\r
+ * PHY_BCR: Transceiver Control Register.\r
+ * More PHY register could be written depending on the used PHY\r
+ * @param RegValue: the value to write\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)\r
+{\r
+uint32_t tmpreg = 0;\r
+uint32_t tickstart = 0;\r
+HAL_StatusTypeDef xResult;\r
+\r
+ /* Check parameters */\r
+ assert_param( IS_ETH_PHY_ADDRESS( heth->Init.PhyAddress ) );\r
+\r
+ /* Check the ETH peripheral state */\r
+ if( heth->State == HAL_ETH_STATE_BUSY_WR )\r
+ {\r
+ xResult = HAL_BUSY;\r
+ }\r
+ else\r
+ {\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set ETH HAL State to BUSY_WR */\r
+ heth->State = HAL_ETH_STATE_BUSY_WR;\r
+\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~ETH_MACMIIAR_CR_MASK;\r
+\r
+ /* Prepare the MII register address value */\r
+ tmpreg |= ( ( ( uint32_t ) heth->Init.PhyAddress << 11 ) & ETH_MACMIIAR_PA ); /* Set the PHY device address */\r
+ tmpreg |= ( ( ( uint32_t ) PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */\r
+ tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+\r
+ /* Give the value to the MII data register */\r
+ heth->Instance->MACMIIDR = ( uint16_t ) RegValue;\r
+\r
+ /* Write the result value into the MII Address register */\r
+ heth->Instance->MACMIIAR = tmpreg;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check for the Busy flag */\r
+ while( 1 )\r
+ {\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul )\r
+ {\r
+ xResult = HAL_OK;\r
+ break;\r
+ }\r
+ /* Check for the Timeout */\r
+ if( ( HAL_GetTick( ) - tickstart ) > PHY_WRITE_TO )\r
+ {\r
+ xResult = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Set ETH HAL State to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+ }\r
+\r
+ if( xResult != HAL_OK )\r
+ {\r
+ lUDPLoggingPrintf( "WritePHY: %d\n", xResult );\r
+ }\r
+ /* Return function status */\r
+ return xResult;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Enable MAC and DMA transmission and reception.\r
+ HAL_ETH_Start();\r
+ (+) Disable MAC and DMA transmission and reception.\r
+ HAL_ETH_Stop();\r
+ (+) Set the MAC configuration in runtime mode\r
+ HAL_ETH_ConfigMAC();\r
+ (+) Set the DMA configuration in runtime mode\r
+ HAL_ETH_ConfigDMA();\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Enables Ethernet MAC and DMA reception/transmission\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef *heth )\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Enable transmit state machine of the MAC for transmission on the MII */\r
+ ETH_MACTransmissionEnable( heth );\r
+\r
+ /* Enable receive state machine of the MAC for reception from the MII */\r
+ ETH_MACReceptionEnable( heth );\r
+\r
+ /* Flush Transmit FIFO */\r
+ ETH_FlushTransmitFIFO( heth );\r
+\r
+ /* Start DMA transmission */\r
+ ETH_DMATransmissionEnable( heth );\r
+\r
+ /* Start DMA reception */\r
+ ETH_DMAReceptionEnable( heth );\r
+\r
+ /* Set the ETH state to READY*/\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop Ethernet MAC and DMA reception/transmission\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Stop DMA transmission */\r
+ ETH_DMATransmissionDisable( heth );\r
+\r
+ /* Stop DMA reception */\r
+ ETH_DMAReceptionDisable( heth );\r
+\r
+ /* Disable receive state machine of the MAC for reception from the MII */\r
+ ETH_MACReceptionDisable( heth );\r
+\r
+ /* Flush Transmit FIFO */\r
+ ETH_FlushTransmitFIFO( heth );\r
+\r
+ /* Disable transmit state machine of the MAC for transmission on the MII */\r
+ ETH_MACTransmissionDisable( heth );\r
+\r
+ /* Set the ETH state*/\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+static void prvWriteMACFCR( ETH_HandleTypeDef *heth, uint32_t ulValue)\r
+{\r
+ /* Enable the MAC transmission */\r
+ heth->Instance->MACFCR = ulValue;\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles.\r
+ Read it back, wait a ms and */\r
+ ( void ) heth->Instance->MACFCR;\r
+\r
+ HAL_Delay( ETH_REG_WRITE_DELAY );\r
+\r
+ heth->Instance->MACFCR = ulValue;\r
+}\r
+\r
+static void prvWriteDMAOMR( ETH_HandleTypeDef *heth, uint32_t ulValue)\r
+{\r
+ /* Enable the MAC transmission */\r
+ heth->Instance->DMAOMR = ulValue;\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles.\r
+ Read it back, wait a ms and */\r
+ ( void ) heth->Instance->DMAOMR;\r
+\r
+ HAL_Delay( ETH_REG_WRITE_DELAY );\r
+\r
+ heth->Instance->DMAOMR = ulValue;\r
+}\r
+\r
+static void prvWriteMACCR( ETH_HandleTypeDef *heth, uint32_t ulValue)\r
+{\r
+ /* Enable the MAC transmission */\r
+ heth->Instance->MACCR = ulValue;\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles.\r
+ Read it back, wait a ms and */\r
+ ( void ) heth->Instance->MACCR;\r
+\r
+ HAL_Delay( ETH_REG_WRITE_DELAY );\r
+\r
+ heth->Instance->MACCR = ulValue;\r
+}\r
+\r
+/**\r
+ * @brief Set ETH MAC Configuration.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param macconf: MAC Configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State= HAL_ETH_STATE_BUSY;\r
+\r
+ assert_param(IS_ETH_SPEED(heth->Init.Speed));\r
+ assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));\r
+\r
+ if (macconf != NULL)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));\r
+ assert_param(IS_ETH_JABBER(macconf->Jabber));\r
+ assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));\r
+ assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));\r
+ assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));\r
+ assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));\r
+ assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));\r
+ assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));\r
+ assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));\r
+ assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));\r
+ assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));\r
+ assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));\r
+ assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));\r
+ assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));\r
+ assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));\r
+ assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));\r
+ assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));\r
+ assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));\r
+ assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));\r
+ assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));\r
+ assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));\r
+ assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));\r
+ assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));\r
+ assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));\r
+ assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));\r
+ assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));\r
+ assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));\r
+\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = heth->Instance->MACCR;\r
+ /* Clear WD, PCE, PS, TE and RE bits */\r
+ tmpreg &= ETH_MACCR_CLEAR_MASK;\r
+\r
+ tmpreg |= (uint32_t)(\r
+ macconf->Watchdog |\r
+ macconf->Jabber |\r
+ macconf->InterFrameGap |\r
+ macconf->CarrierSense |\r
+ heth->Init.Speed |\r
+ macconf->ReceiveOwn |\r
+ macconf->LoopbackMode |\r
+ heth->Init.DuplexMode |\r
+ macconf->ChecksumOffload |\r
+ macconf->RetryTransmission |\r
+ macconf->AutomaticPadCRCStrip |\r
+ macconf->BackOffLimit |\r
+ macconf->DeferralCheck);\r
+\r
+ /* Write to ETHERNET MACCR */\r
+ prvWriteMACCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/\r
+ /* Write to ETHERNET MACFFR */\r
+ heth->Instance->MACFFR = (uint32_t)(\r
+ macconf->ReceiveAll |\r
+ macconf->SourceAddrFilter |\r
+ macconf->PassControlFrames |\r
+ macconf->BroadcastFramesReception |\r
+ macconf->DestinationAddrFilter |\r
+ macconf->PromiscuousMode |\r
+ macconf->MulticastFramesFilter |\r
+ macconf->UnicastFramesFilter);\r
+\r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACFFR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACFFR = tmpreg;\r
+\r
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/\r
+ /* Write to ETHERNET MACHTHR */\r
+ heth->Instance->MACHTHR = (uint32_t)macconf->HashTableHigh;\r
+\r
+ /* Write to ETHERNET MACHTLR */\r
+ heth->Instance->MACHTLR = (uint32_t)macconf->HashTableLow;\r
+ /*----------------------- ETHERNET MACFCR Configuration --------------------*/\r
+\r
+ /* Get the ETHERNET MACFCR value */\r
+ tmpreg = heth->Instance->MACFCR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_MACFCR_CLEAR_MASK;\r
+\r
+ tmpreg |= (uint32_t)((\r
+ macconf->PauseTime << 16) |\r
+ macconf->ZeroQuantaPause |\r
+ macconf->PauseLowThreshold |\r
+ macconf->UnicastPauseFrameDetect |\r
+ macconf->ReceiveFlowControl |\r
+ macconf->TransmitFlowControl);\r
+\r
+ /* Write to ETHERNET MACFCR */\r
+ prvWriteMACFCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/\r
+ heth->Instance->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |\r
+ macconf->VLANTagIdentifier);\r
+\r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACVLANTR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACVLANTR = tmpreg;\r
+ }\r
+ else /* macconf == NULL : here we just configure Speed and Duplex mode */\r
+ {\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = heth->Instance->MACCR;\r
+\r
+ /* Clear FES and DM bits */\r
+ tmpreg &= ~((uint32_t)0x00004800);\r
+\r
+ tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);\r
+\r
+ /* Write to ETHERNET MACCR */\r
+ prvWriteMACCR( heth, tmpreg );\r
+ }\r
+\r
+ /* Set the ETH state to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets ETH DMA Configuration.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param dmaconf: DMA Configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State= HAL_ETH_STATE_BUSY;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));\r
+ assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));\r
+ assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));\r
+ assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));\r
+ assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));\r
+ assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));\r
+ assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));\r
+ assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));\r
+ assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));\r
+ assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));\r
+ assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));\r
+ assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));\r
+ assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));\r
+ assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));\r
+ assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));\r
+ assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));\r
+\r
+ /*----------------------- ETHERNET DMAOMR Configuration --------------------*/\r
+ /* Get the ETHERNET DMAOMR value */\r
+ tmpreg = heth->Instance->DMAOMR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_DMAOMR_CLEAR_MASK;\r
+\r
+ tmpreg |= (uint32_t)(\r
+ dmaconf->DropTCPIPChecksumErrorFrame |\r
+ dmaconf->ReceiveStoreForward |\r
+ dmaconf->FlushReceivedFrame |\r
+ dmaconf->TransmitStoreForward |\r
+ dmaconf->TransmitThresholdControl |\r
+ dmaconf->ForwardErrorFrames |\r
+ dmaconf->ForwardUndersizedGoodFrames |\r
+ dmaconf->ReceiveThresholdControl |\r
+ dmaconf->SecondFrameOperate);\r
+\r
+ /* Write to ETHERNET DMAOMR */\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET DMABMR Configuration --------------------*/\r
+ heth->Instance->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |\r
+ dmaconf->FixedBurst |\r
+ dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r
+ dmaconf->TxDMABurstLength |\r
+ dmaconf->EnhancedDescriptorFormat |\r
+ (dmaconf->DescriptorSkipLength << 2) |\r
+ dmaconf->DMAArbitration |\r
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->DMABMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->DMABMR = tmpreg;\r
+\r
+ /* Set the ETH state to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions\r
+ * @brief Peripheral State functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral\r
+ and the data flow.\r
+ (+) Get the ETH handle state:\r
+ HAL_ETH_GetState();\r
+\r
+\r
+ @endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the ETH HAL state\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL state\r
+ */\r
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Return ETH state */\r
+ return heth->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ETH_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures Ethernet MAC and DMA with default parameters.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param err: Ethernet Init error\r
+ * @retval HAL status\r
+ */\r
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)\r
+{\r
+ ETH_MACInitTypeDef macinit;\r
+ ETH_DMAInitTypeDef dmainit;\r
+ uint32_t tmpreg = 0;\r
+\r
+ if (err != ETH_SUCCESS) /* Auto-negotiation failed */\r
+ {\r
+ /* Set Ethernet duplex mode to Full-duplex */\r
+ heth->Init.DuplexMode = ETH_MODE_FULLDUPLEX;\r
+\r
+ /* Set Ethernet speed to 100M */\r
+ heth->Init.Speed = ETH_SPEED_100M;\r
+ }\r
+\r
+ /* Ethernet MAC default initialization **************************************/\r
+ macinit.Watchdog = ETH_WATCHDOG_ENABLE;\r
+ macinit.Jabber = ETH_JABBER_ENABLE;\r
+ macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;\r
+ macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;\r
+ macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;\r
+ macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;\r
+ if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)\r
+ {\r
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;\r
+ }\r
+ else\r
+ {\r
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;\r
+ }\r
+ macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;\r
+ macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;\r
+ macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;\r
+ macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;\r
+ macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;\r
+ macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;\r
+ macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;\r
+ macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;\r
+ macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;\r
+ macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;\r
+ macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;\r
+ macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;\r
+ macinit.HashTableHigh = 0x0;\r
+ macinit.HashTableLow = 0x0;\r
+ macinit.PauseTime = 0x0;\r
+ macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;\r
+ macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;\r
+ macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;\r
+ macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;\r
+ macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;\r
+ macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;\r
+ macinit.VLANTagIdentifier = 0x0;\r
+\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = heth->Instance->MACCR;\r
+ /* Clear WD, PCE, PS, TE and RE bits */\r
+ tmpreg &= ETH_MACCR_CLEAR_MASK;\r
+ /* Set the WD bit according to ETH Watchdog value */\r
+ /* Set the JD: bit according to ETH Jabber value */\r
+ /* Set the IFG bit according to ETH InterFrameGap value */\r
+ /* Set the DCRS bit according to ETH CarrierSense value */\r
+ /* Set the FES bit according to ETH Speed value */\r
+ /* Set the DO bit according to ETH ReceiveOwn value */\r
+ /* Set the LM bit according to ETH LoopbackMode value */\r
+ /* Set the DM bit according to ETH Mode value */\r
+ /* Set the IPCO bit according to ETH ChecksumOffload value */\r
+ /* Set the DR bit according to ETH RetryTransmission value */\r
+ /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */\r
+ /* Set the BL bit according to ETH BackOffLimit value */\r
+ /* Set the DC bit according to ETH DeferralCheck value */\r
+ tmpreg |= (uint32_t)(macinit.Watchdog |\r
+ macinit.Jabber |\r
+ macinit.InterFrameGap |\r
+ macinit.CarrierSense |\r
+ heth->Init.Speed |\r
+ macinit.ReceiveOwn |\r
+ macinit.LoopbackMode |\r
+ heth->Init.DuplexMode |\r
+ macinit.ChecksumOffload |\r
+ macinit.RetryTransmission |\r
+ macinit.AutomaticPadCRCStrip |\r
+ macinit.BackOffLimit |\r
+ macinit.DeferralCheck);\r
+\r
+ /* Write to ETHERNET MACCR */\r
+ prvWriteMACCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/\r
+ /* Set the RA bit according to ETH ReceiveAll value */\r
+ /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */\r
+ /* Set the PCF bit according to ETH PassControlFrames value */\r
+ /* Set the DBF bit according to ETH BroadcastFramesReception value */\r
+ /* Set the DAIF bit according to ETH DestinationAddrFilter value */\r
+ /* Set the PR bit according to ETH PromiscuousMode value */\r
+ /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */\r
+ /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */\r
+ /* Write to ETHERNET MACFFR */\r
+ heth->Instance->MACFFR = (uint32_t)(macinit.ReceiveAll |\r
+ macinit.SourceAddrFilter |\r
+ macinit.PassControlFrames |\r
+ macinit.BroadcastFramesReception |\r
+ macinit.DestinationAddrFilter |\r
+ macinit.PromiscuousMode |\r
+ macinit.MulticastFramesFilter |\r
+ macinit.UnicastFramesFilter);\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACFFR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACFFR = tmpreg;\r
+\r
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/\r
+ /* Write to ETHERNET MACHTHR */\r
+ heth->Instance->MACHTHR = (uint32_t)macinit.HashTableHigh;\r
+\r
+ /* Write to ETHERNET MACHTLR */\r
+ heth->Instance->MACHTLR = (uint32_t)macinit.HashTableLow;\r
+ /*----------------------- ETHERNET MACFCR Configuration -------------------*/\r
+\r
+ /* Get the ETHERNET MACFCR value */\r
+ tmpreg = heth->Instance->MACFCR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_MACFCR_CLEAR_MASK;\r
+\r
+ /* Set the PT bit according to ETH PauseTime value */\r
+ /* Set the DZPQ bit according to ETH ZeroQuantaPause value */\r
+ /* Set the PLT bit according to ETH PauseLowThreshold value */\r
+ /* Set the UP bit according to ETH UnicastPauseFrameDetect value */\r
+ /* Set the RFE bit according to ETH ReceiveFlowControl value */\r
+ /* Set the TFE bit according to ETH TransmitFlowControl value */\r
+ tmpreg |= (uint32_t)((macinit.PauseTime << 16) |\r
+ macinit.ZeroQuantaPause |\r
+ macinit.PauseLowThreshold |\r
+ macinit.UnicastPauseFrameDetect |\r
+ macinit.ReceiveFlowControl |\r
+ macinit.TransmitFlowControl);\r
+\r
+ /* Write to ETHERNET MACFCR */\r
+ prvWriteMACFCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/\r
+ /* Set the ETV bit according to ETH VLANTagComparison value */\r
+ /* Set the VL bit according to ETH VLANTagIdentifier value */\r
+ heth->Instance->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |\r
+ macinit.VLANTagIdentifier);\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACVLANTR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACVLANTR = tmpreg;\r
+\r
+ /* Ethernet DMA default initialization ************************************/\r
+ dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;\r
+ dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;\r
+ dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;\r
+ dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;\r
+ dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;\r
+ dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;\r
+ dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;\r
+ dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;\r
+ dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;\r
+ dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;\r
+ dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;\r
+ dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;\r
+ dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;\r
+ dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;\r
+ dmainit.DescriptorSkipLength = 0x0;\r
+ dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;\r
+\r
+ /* Get the ETHERNET DMAOMR value */\r
+ tmpreg = heth->Instance->DMAOMR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_DMAOMR_CLEAR_MASK;\r
+\r
+ /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */\r
+ /* Set the RSF bit according to ETH ReceiveStoreForward value */\r
+ /* Set the DFF bit according to ETH FlushReceivedFrame value */\r
+ /* Set the TSF bit according to ETH TransmitStoreForward value */\r
+ /* Set the TTC bit according to ETH TransmitThresholdControl value */\r
+ /* Set the FEF bit according to ETH ForwardErrorFrames value */\r
+ /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */\r
+ /* Set the RTC bit according to ETH ReceiveThresholdControl value */\r
+ /* Set the OSF bit according to ETH SecondFrameOperate value */\r
+ tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |\r
+ dmainit.ReceiveStoreForward |\r
+ dmainit.FlushReceivedFrame |\r
+ dmainit.TransmitStoreForward |\r
+ dmainit.TransmitThresholdControl |\r
+ dmainit.ForwardErrorFrames |\r
+ dmainit.ForwardUndersizedGoodFrames |\r
+ dmainit.ReceiveThresholdControl |\r
+ dmainit.SecondFrameOperate);\r
+\r
+ /* Write to ETHERNET DMAOMR */\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET DMABMR Configuration ------------------*/\r
+ /* Set the AAL bit according to ETH AddressAlignedBeats value */\r
+ /* Set the FB bit according to ETH FixedBurst value */\r
+ /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */\r
+ /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */\r
+ /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/\r
+ /* Set the DSL bit according to ETH DesciptorSkipLength value */\r
+ /* Set the PR and DA bits according to ETH DMAArbitration value */\r
+ heth->Instance->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |\r
+ dmainit.FixedBurst |\r
+ dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r
+ dmainit.TxDMABurstLength |\r
+ dmainit.EnhancedDescriptorFormat |\r
+ (dmainit.DescriptorSkipLength << 2) |\r
+ dmainit.DMAArbitration |\r
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->DMABMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->DMABMR = tmpreg;\r
+\r
+ if(heth->Init.RxMode == ETH_RXINTERRUPT_MODE)\r
+ {\r
+ /* Enable the Ethernet Rx Interrupt */\r
+ __HAL_ETH_DMA_ENABLE_IT(( heth ), ETH_DMA_IT_NIS | ETH_DMA_IT_R);\r
+ }\r
+\r
+ /* Initialize MAC address in ethernet MAC */\r
+ ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);\r
+}\r
+\r
+/**\r
+ * @brief Configures the selected MAC address.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param MacAddr: The MAC address to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_Address0: MAC Address0\r
+ * @arg ETH_MAC_Address1: MAC Address1\r
+ * @arg ETH_MAC_Address2: MAC Address2\r
+ * @arg ETH_MAC_Address3: MAC Address3\r
+ * @param Addr: Pointer to MAC address buffer data (6 bytes)\r
+ * @retval HAL status\r
+ */\r
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)\r
+{\r
+ uint32_t tmpreg;\r
+\r
+ /* Check the parameters */\r
+ assert_param( IS_ETH_MAC_ADDRESS0123( MacAddr ) );\r
+\r
+ /* Calculate the selected MAC address high register */\r
+ tmpreg = 0x80000000ul | ( ( uint32_t )Addr[ 5 ] << 8) | (uint32_t)Addr[ 4 ];\r
+ /* Load the selected MAC address high register */\r
+ ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + MacAddr ) ) ) = tmpreg;\r
+ /* Calculate the selected MAC address low register */\r
+ tmpreg = ( ( uint32_t )Addr[ 3 ] << 24 ) | ( ( uint32_t )Addr[ 2 ] << 16 ) | ( ( uint32_t )Addr[ 1 ] << 8 ) | Addr[ 0 ];\r
+\r
+ /* Load the selected MAC address low register */\r
+ ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + MacAddr ) ) ) = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the MAC transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_TE;\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the MAC transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_TE );\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Enables the MAC reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ __IO uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_RE;\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the MAC reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ __IO uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_RE );\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Enables the DMA transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Enable the DMA transmission */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_ST;\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the DMA transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Disable the DMA transmission */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_ST );\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Enables the DMA reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Enable the DMA reception */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_SR;\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the DMA reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Disable the DMA reception */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_SR );\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Clears the ETHERNET transmit FIFO.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Set the Flush Transmit FIFO bit */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_FTF;\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* STM32F7xx */\r
+#endif /* HAL_ETH_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_eth.h\r
+ * @author MCD Application Team\r
+ * @version V1.2.2\r
+ * @date 14-April-2017\r
+ * @brief Header file of ETH HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_ETH_H\r
+#define __STM32F7xx_HAL_ETH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ETH\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup ETH_Private_Macros\r
+ * @{\r
+ */\r
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)\r
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \\r
+ ((CMD) == ETH_AUTONEGOTIATION_DISABLE))\r
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \\r
+ ((SPEED) == ETH_SPEED_100M))\r
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \\r
+ ((MODE) == ETH_MODE_HALFDUPLEX))\r
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
+ ((MODE) == ETH_RXINTERRUPT_MODE))\r
+#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \\r
+ ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))\r
+#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \\r
+ ((MODE) == ETH_MEDIA_INTERFACE_RMII))\r
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \\r
+ ((CMD) == ETH_WATCHDOG_DISABLE))\r
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \\r
+ ((CMD) == ETH_JABBER_DISABLE))\r
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_40BIT))\r
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \\r
+ ((CMD) == ETH_CARRIERSENCE_DISABLE))\r
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVEOWN_DISABLE))\r
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \\r
+ ((CMD) == ETH_LOOPBACKMODE_DISABLE))\r
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \\r
+ ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))\r
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \\r
+ ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))\r
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \\r
+ ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))\r
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \\r
+ ((LIMIT) == ETH_BACKOFFLIMIT_8) || \\r
+ ((LIMIT) == ETH_BACKOFFLIMIT_4) || \\r
+ ((LIMIT) == ETH_BACKOFFLIMIT_1))\r
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \\r
+ ((CMD) == ETH_DEFFERRALCHECK_DISABLE))\r
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVEAll_DISABLE))\r
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \\r
+ ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \\r
+ ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))\r
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \\r
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \\r
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))\r
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \\r
+ ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))\r
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \\r
+ ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))\r
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \\r
+ ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))\r
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \\r
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \\r
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \\r
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))\r
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \\r
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \\r
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))\r
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)\r
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \\r
+ ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))\r
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \\r
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \\r
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \\r
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))\r
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \\r
+ ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))\r
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))\r
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \\r
+ ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))\r
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \\r
+ ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))\r
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)\r
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS1) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS3))\r
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS3))\r
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \\r
+ ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))\r
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))\r
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \\r
+ ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))\r
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))\r
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \\r
+ ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))\r
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \\r
+ ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))\r
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))\r
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \\r
+ ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))\r
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \\r
+ ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))\r
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \\r
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \\r
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \\r
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))\r
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \\r
+ ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))\r
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \\r
+ ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))\r
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \\r
+ ((CMD) == ETH_FIXEDBURST_DISABLE))\r
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))\r
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))\r
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)\r
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))\r
+#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \\r
+ ((FLAG) == ETH_DMATXDESC_IC) || \\r
+ ((FLAG) == ETH_DMATXDESC_LS) || \\r
+ ((FLAG) == ETH_DMATXDESC_FS) || \\r
+ ((FLAG) == ETH_DMATXDESC_DC) || \\r
+ ((FLAG) == ETH_DMATXDESC_DP) || \\r
+ ((FLAG) == ETH_DMATXDESC_TTSE) || \\r
+ ((FLAG) == ETH_DMATXDESC_TER) || \\r
+ ((FLAG) == ETH_DMATXDESC_TCH) || \\r
+ ((FLAG) == ETH_DMATXDESC_TTSS) || \\r
+ ((FLAG) == ETH_DMATXDESC_IHE) || \\r
+ ((FLAG) == ETH_DMATXDESC_ES) || \\r
+ ((FLAG) == ETH_DMATXDESC_JT) || \\r
+ ((FLAG) == ETH_DMATXDESC_FF) || \\r
+ ((FLAG) == ETH_DMATXDESC_PCE) || \\r
+ ((FLAG) == ETH_DMATXDESC_LCA) || \\r
+ ((FLAG) == ETH_DMATXDESC_NC) || \\r
+ ((FLAG) == ETH_DMATXDESC_LCO) || \\r
+ ((FLAG) == ETH_DMATXDESC_EC) || \\r
+ ((FLAG) == ETH_DMATXDESC_VF) || \\r
+ ((FLAG) == ETH_DMATXDESC_CC) || \\r
+ ((FLAG) == ETH_DMATXDESC_ED) || \\r
+ ((FLAG) == ETH_DMATXDESC_UF) || \\r
+ ((FLAG) == ETH_DMATXDESC_DB))\r
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \\r
+ ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))\r
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \\r
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \\r
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \\r
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))\r
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)\r
+#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \\r
+ ((FLAG) == ETH_DMARXDESC_AFM) || \\r
+ ((FLAG) == ETH_DMARXDESC_ES) || \\r
+ ((FLAG) == ETH_DMARXDESC_DE) || \\r
+ ((FLAG) == ETH_DMARXDESC_SAF) || \\r
+ ((FLAG) == ETH_DMARXDESC_LE) || \\r
+ ((FLAG) == ETH_DMARXDESC_OE) || \\r
+ ((FLAG) == ETH_DMARXDESC_VLAN) || \\r
+ ((FLAG) == ETH_DMARXDESC_FS) || \\r
+ ((FLAG) == ETH_DMARXDESC_LS) || \\r
+ ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \\r
+ ((FLAG) == ETH_DMARXDESC_LC) || \\r
+ ((FLAG) == ETH_DMARXDESC_FT) || \\r
+ ((FLAG) == ETH_DMARXDESC_RWT) || \\r
+ ((FLAG) == ETH_DMARXDESC_RE) || \\r
+ ((FLAG) == ETH_DMARXDESC_DBE) || \\r
+ ((FLAG) == ETH_DMARXDESC_CE) || \\r
+ ((FLAG) == ETH_DMARXDESC_MAMPCE))\r
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \\r
+ ((BUFFER) == ETH_DMARXDESC_BUFFER2))\r
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \\r
+ ((FLAG) == ETH_PMT_FLAG_MPR))\r
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00)) \r
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \\r
+ ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \\r
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_T))\r
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \\r
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \\r
+ ((IT) == ETH_MAC_IT_PMT))\r
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \\r
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \\r
+ ((FLAG) == ETH_MAC_FLAG_PMT))\r
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \\r
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \\r
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \\r
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \\r
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \\r
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \\r
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \\r
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \\r
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))\r
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \\r
+ ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))\r
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \\r
+ ((IT) != 0x00))\r
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \\r
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \\r
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))\r
+#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \\r
+ ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ETH_Private_Defines\r
+ * @{\r
+ */\r
+/* Delay to wait when writing to some Ethernet registers */\r
+#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U)\r
+\r
+/* Ethernet Errors */\r
+#define ETH_SUCCESS ((uint32_t)0U)\r
+#define ETH_ERROR ((uint32_t)1U)\r
+\r
+/* Ethernet DMA Tx descriptors Collision Count Shift */\r
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3U)\r
+\r
+/* Ethernet DMA Tx descriptors Buffer2 Size Shift */\r
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U)\r
+\r
+/* Ethernet DMA Rx descriptors Frame Length Shift */\r
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16U)\r
+\r
+/* Ethernet DMA Rx descriptors Buffer2 Size Shift */\r
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U)\r
+\r
+/* Ethernet DMA Rx descriptors Frame length Shift */\r
+#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)\r
+\r
+/* Ethernet MAC address offsets */\r
+#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U) /* Ethernet MAC address high offset */\r
+#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U) /* Ethernet MAC address low offset */\r
+\r
+/* Ethernet MACMIIAR register Mask */\r
+#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U)\r
+\r
+/* Ethernet MACCR register Mask */\r
+#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810FU) \r
+\r
+/* Ethernet MACFCR register Mask */\r
+#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41U)\r
+\r
+/* Ethernet DMAOMR register Mask */\r
+#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23U)\r
+\r
+/* Ethernet Remote Wake-up frame register length */\r
+#define ETH_WAKEUP_REGISTER_LENGTH 8U\r
+\r
+/* Ethernet Missed frames counter Shift */\r
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/** @defgroup ETH_Exported_Types ETH Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief HAL State structures definition \r
+ */ \r
+typedef enum\r
+{\r
+ HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */\r
+ HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */\r
+ HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */\r
+ HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */\r
+ HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */\r
+ HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */\r
+ HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */\r
+ HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */\r
+ HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */\r
+ HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */\r
+}HAL_ETH_StateTypeDef;\r
+\r
+/** \r
+ * @brief ETH Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY\r
+ The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)\r
+ and the mode (half/full-duplex).\r
+ This parameter can be a value of @ref ETH_AutoNegotiation */\r
+\r
+ uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.\r
+ This parameter can be a value of @ref ETH_Speed */\r
+\r
+ uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode\r
+ This parameter can be a value of @ref ETH_Duplex_Mode */\r
+ \r
+ uint16_t PhyAddress; /*!< Ethernet PHY address.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */\r
+ \r
+ uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */\r
+ \r
+ uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.\r
+ This parameter can be a value of @ref ETH_Rx_Mode */\r
+ \r
+ uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. \r
+ This parameter can be a value of @ref ETH_Checksum_Mode */\r
+ \r
+ uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface. \r
+ This parameter can be a value of @ref ETH_Media_Interface */\r
+\r
+} ETH_InitTypeDef;\r
+\r
+\r
+ /** \r
+ * @brief ETH MAC Configuration Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t Watchdog; /*!< Selects or not the Watchdog timer\r
+ When enabled, the MAC allows no more then 2048 bytes to be received.\r
+ When disabled, the MAC can receive up to 16384 bytes.\r
+ This parameter can be a value of @ref ETH_Watchdog */ \r
+\r
+ uint32_t Jabber; /*!< Selects or not Jabber timer\r
+ When enabled, the MAC allows no more then 2048 bytes to be sent.\r
+ When disabled, the MAC can send up to 16384 bytes.\r
+ This parameter can be a value of @ref ETH_Jabber */\r
+\r
+ uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.\r
+ This parameter can be a value of @ref ETH_Inter_Frame_Gap */ \r
+\r
+ uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.\r
+ This parameter can be a value of @ref ETH_Carrier_Sense */\r
+\r
+ uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,\r
+ ReceiveOwn allows the reception of frames when the TX_EN signal is asserted\r
+ in Half-Duplex mode.\r
+ This parameter can be a value of @ref ETH_Receive_Own */ \r
+\r
+ uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.\r
+ This parameter can be a value of @ref ETH_Loop_Back_Mode */ \r
+\r
+ uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.\r
+ This parameter can be a value of @ref ETH_Checksum_Offload */ \r
+\r
+ uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,\r
+ when a collision occurs (Half-Duplex mode).\r
+ This parameter can be a value of @ref ETH_Retry_Transmission */\r
+\r
+ uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.\r
+ This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ \r
+\r
+ uint32_t BackOffLimit; /*!< Selects the BackOff limit value.\r
+ This parameter can be a value of @ref ETH_Back_Off_Limit */\r
+\r
+ uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).\r
+ This parameter can be a value of @ref ETH_Deferral_Check */ \r
+\r
+ uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).\r
+ This parameter can be a value of @ref ETH_Receive_All */ \r
+\r
+ uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. \r
+ This parameter can be a value of @ref ETH_Source_Addr_Filter */ \r
+\r
+ uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) \r
+ This parameter can be a value of @ref ETH_Pass_Control_Frames */ \r
+\r
+ uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.\r
+ This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */\r
+\r
+ uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.\r
+ This parameter can be a value of @ref ETH_Destination_Addr_Filter */ \r
+\r
+ uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode\r
+ This parameter can be a value of @ref ETH_Promiscuous_Mode */\r
+\r
+ uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r
+ This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ \r
+\r
+ uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r
+ This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ \r
+\r
+ uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.\r
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */\r
+\r
+ uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.\r
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ \r
+\r
+ uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. \r
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.\r
+ This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ \r
+\r
+ uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for\r
+ automatic retransmission of PAUSE Frame.\r
+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */\r
+ \r
+ uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0\r
+ unicast address and unique multicast address).\r
+ This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ \r
+\r
+ uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and\r
+ disable its transmitter for a specified time (Pause Time)\r
+ This parameter can be a value of @ref ETH_Receive_Flow_Control */\r
+\r
+ uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)\r
+ or the MAC back-pressure operation (Half-Duplex mode)\r
+ This parameter can be a value of @ref ETH_Transmit_Flow_Control */ \r
+\r
+ uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for\r
+ comparison and filtering.\r
+ This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ \r
+\r
+ uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */\r
+\r
+} ETH_MACInitTypeDef;\r
+\r
+\r
+/** \r
+ * @brief ETH DMA Configuration Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.\r
+ This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ \r
+\r
+ uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.\r
+ This parameter can be a value of @ref ETH_Receive_Store_Forward */ \r
+\r
+ uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.\r
+ This parameter can be a value of @ref ETH_Flush_Received_Frame */ \r
+\r
+ uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.\r
+ This parameter can be a value of @ref ETH_Transmit_Store_Forward */ \r
+\r
+ uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.\r
+ This parameter can be a value of @ref ETH_Transmit_Threshold_Control */\r
+\r
+ uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.\r
+ This parameter can be a value of @ref ETH_Forward_Error_Frames */\r
+\r
+ uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error\r
+ and length less than 64 bytes) including pad-bytes and CRC)\r
+ This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */\r
+\r
+ uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.\r
+ This parameter can be a value of @ref ETH_Receive_Threshold_Control */\r
+\r
+ uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second\r
+ frame of Transmit data even before obtaining the status for the first frame.\r
+ This parameter can be a value of @ref ETH_Second_Frame_Operate */\r
+\r
+ uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.\r
+ This parameter can be a value of @ref ETH_Address_Aligned_Beats */\r
+\r
+ uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.\r
+ This parameter can be a value of @ref ETH_Fixed_Burst */\r
+ \r
+ uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.\r
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ \r
+\r
+ uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.\r
+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */\r
+ \r
+ uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.\r
+ This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */\r
+\r
+ uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ \r
+\r
+ uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.\r
+ This parameter can be a value of @ref ETH_DMA_Arbitration */ \r
+} ETH_DMAInitTypeDef;\r
+\r
+\r
+/** \r
+ * @brief ETH DMA Descriptors data structure definition\r
+ */ \r
+\r
+typedef struct \r
+{\r
+ __IO uint32_t Status; /*!< Status */\r
+ \r
+ uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */\r
+ \r
+ uint32_t Buffer1Addr; /*!< Buffer1 address pointer */\r
+ \r
+ uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */\r
+ \r
+ /*!< Enhanced Ethernet DMA PTP Descriptors */\r
+ uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */\r
+ \r
+ uint32_t Reserved1; /*!< Reserved */\r
+ \r
+ uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */\r
+ \r
+ uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */\r
+\r
+} ETH_DMADescTypeDef;\r
+\r
+\r
+/** \r
+ * @brief Received Frame Informations structure definition\r
+ */ \r
+typedef struct \r
+{\r
+ ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */\r
+ \r
+ ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */\r
+ \r
+ uint32_t SegCount; /*!< Segment count */\r
+ \r
+ uint32_t length; /*!< Frame length */\r
+ \r
+ uint32_t buffer; /*!< Frame buffer */\r
+\r
+} ETH_DMARxFrameInfos;\r
+\r
+\r
+/** \r
+ * @brief ETH Handle Structure definition \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ ETH_TypeDef *Instance; /*!< Register base address */\r
+ \r
+ ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */\r
+ \r
+ uint32_t LinkStatus; /*!< Ethernet link status */\r
+ \r
+ ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */\r
+ \r
+ ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */\r
+ \r
+ ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */\r
+ \r
+ __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */\r
+ \r
+ HAL_LockTypeDef Lock; /*!< ETH Lock */\r
+\r
+} ETH_HandleTypeDef;\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup ETH_Exported_Constants ETH Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH_Buffers_setting ETH Buffers setting\r
+ * @{\r
+ */ \r
+#define ETH_MAX_PACKET_SIZE ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */\r
+#define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */\r
+#define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */\r
+#define ETH_EXTRA ((uint32_t)2U) /*!< Extra bytes in some cases */ \r
+#define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */\r
+#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */\r
+#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */\r
+#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */ \r
+\r
+ /* Ethernet driver receive buffers are organized in a chained linked-list, when\r
+ an Ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO\r
+ to the driver receive buffers memory.\r
+\r
+ Depending on the size of the received Ethernet packet and the size of \r
+ each Ethernet driver receive buffer, the received packet can take one or more\r
+ Ethernet driver receive buffer. \r
+\r
+ In below are defined the size of one Ethernet driver receive buffer ETH_RX_BUF_SIZE \r
+ and the total count of the driver receive buffers ETH_RXBUFNB.\r
+\r
+ The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as \r
+ example, they can be reconfigured in the application layer to fit the application \r
+ needs */ \r
+\r
+/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet\r
+ packet */\r
+#ifndef ETH_RX_BUF_SIZE\r
+ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE \r
+#endif\r
+\r
+/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ \r
+#ifndef ETH_RXBUFNB\r
+ #define ETH_RXBUFNB ((uint32_t)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */\r
+#endif\r
+\r
+\r
+ /* Ethernet driver transmit buffers are organized in a chained linked-list, when\r
+ an Ethernet packet is transmitted, Tx-DMA will transfer the packet from the \r
+ driver transmit buffers memory to the TxFIFO.\r
+\r
+ Depending on the size of the Ethernet packet to be transmitted and the size of \r
+ each Ethernet driver transmit buffer, the packet to be transmitted can take \r
+ one or more Ethernet driver transmit buffer. \r
+\r
+ In below are defined the size of one Ethernet driver transmit buffer ETH_TX_BUF_SIZE \r
+ and the total count of the driver transmit buffers ETH_TXBUFNB.\r
+\r
+ The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as \r
+ example, they can be reconfigured in the application layer to fit the application \r
+ needs */ \r
+\r
+/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet\r
+ packet */\r
+#ifndef ETH_TX_BUF_SIZE \r
+ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE\r
+#endif\r
+\r
+/* 5 Ethernet driver transmit buffers are used (in a chained linked list)*/ \r
+#ifndef ETH_TXBUFNB\r
+ #define ETH_TXBUFNB ((uint32_t)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */\r
+#endif\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor\r
+ * @{\r
+ */\r
+\r
+/*\r
+ DMA Tx Descriptor\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES2 | Buffer1 Address [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+*/\r
+\r
+/** \r
+ * @brief Bit definition of TDES0 register: DMA Tx descriptor status register\r
+ */ \r
+#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMATXDESC_IC ((uint32_t)0x40000000U) /*!< Interrupt on Completion */\r
+#define ETH_DMATXDESC_LS ((uint32_t)0x20000000U) /*!< Last Segment */\r
+#define ETH_DMATXDESC_FS ((uint32_t)0x10000000U) /*!< First Segment */\r
+#define ETH_DMATXDESC_DC ((uint32_t)0x08000000U) /*!< Disable CRC */\r
+#define ETH_DMATXDESC_DP ((uint32_t)0x04000000U) /*!< Disable Padding */\r
+#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) /*!< Transmit Time Stamp Enable */\r
+#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) /*!< Checksum Insertion Control: 4 cases */\r
+#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is bypassed */ \r
+#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) /*!< IPV4 header Checksum Insertion */ \r
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ \r
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ \r
+#define ETH_DMATXDESC_TER ((uint32_t)0x00200000U) /*!< Transmit End of Ring */\r
+#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) /*!< Second Address Chained */\r
+#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) /*!< Tx Time Stamp Status */\r
+#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) /*!< IP Header Error */\r
+#define ETH_DMATXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */\r
+#define ETH_DMATXDESC_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */\r
+#define ETH_DMATXDESC_FF ((uint32_t)0x00002000U) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */\r
+#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */\r
+#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */\r
+#define ETH_DMATXDESC_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */\r
+#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */\r
+#define ETH_DMATXDESC_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */\r
+#define ETH_DMATXDESC_VF ((uint32_t)0x00000080U) /*!< VLAN Frame */\r
+#define ETH_DMATXDESC_CC ((uint32_t)0x00000078U) /*!< Collision Count */\r
+#define ETH_DMATXDESC_ED ((uint32_t)0x00000004U) /*!< Excessive Deferral */\r
+#define ETH_DMATXDESC_UF ((uint32_t)0x00000002U) /*!< Underflow Error: late data arrival from the memory */\r
+#define ETH_DMATXDESC_DB ((uint32_t)0x00000001U) /*!< Deferred Bit */\r
+\r
+/** \r
+ * @brief Bit definition of TDES1 register\r
+ */ \r
+#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) /*!< Transmit Buffer2 Size */\r
+#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) /*!< Transmit Buffer1 Size */\r
+\r
+/** \r
+ * @brief Bit definition of TDES2 register\r
+ */ \r
+#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */\r
+\r
+/** \r
+ * @brief Bit definition of TDES3 register\r
+ */ \r
+#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */\r
+\r
+ /*---------------------------------------------------------------------------------------------\r
+ TDES6 | Transmit Time Stamp Low [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES7 | Transmit Time Stamp High [31:0] |\r
+ ----------------------------------------------------------------------------------------------*/\r
+\r
+/* Bit definition of TDES6 register */\r
+ #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */\r
+\r
+/* Bit definition of TDES7 register */\r
+ #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor\r
+ * @{\r
+ */\r
+\r
+/*\r
+ DMA Rx Descriptor\r
+ --------------------------------------------------------------------------------------------------------------------\r
+ RDES0 | OWN(31) | Status [30:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES2 | Buffer1 Address [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+*/\r
+\r
+/** \r
+ * @brief Bit definition of RDES0 register: DMA Rx descriptor status register\r
+ */ \r
+#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) /*!< DA Filter Fail for the rx frame */\r
+#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) /*!< Receive descriptor frame length */\r
+#define ETH_DMARXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */\r
+#define ETH_DMARXDESC_DE ((uint32_t)0x00004000U) /*!< Descriptor error: no more descriptors for receive frame */\r
+#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) /*!< SA Filter Fail for the received frame */\r
+#define ETH_DMARXDESC_LE ((uint32_t)0x00001000U) /*!< Frame size not matching with length field */\r
+#define ETH_DMARXDESC_OE ((uint32_t)0x00000800U) /*!< Overflow Error: Frame was damaged due to buffer overflow */\r
+#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) /*!< VLAN Tag: received frame is a VLAN frame */\r
+#define ETH_DMARXDESC_FS ((uint32_t)0x00000200U) /*!< First descriptor of the frame */\r
+#define ETH_DMARXDESC_LS ((uint32_t)0x00000100U) /*!< Last descriptor of the frame */ \r
+#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ \r
+#define ETH_DMARXDESC_LC ((uint32_t)0x00000040U) /*!< Late collision occurred during reception */\r
+#define ETH_DMARXDESC_FT ((uint32_t)0x00000020U) /*!< Frame type - Ethernet, otherwise 802.3 */\r
+#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */\r
+#define ETH_DMARXDESC_RE ((uint32_t)0x00000008U) /*!< Receive error: error reported by MII interface */\r
+#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) /*!< Dribble bit error: frame contains non int multiple of 8 bits */\r
+#define ETH_DMARXDESC_CE ((uint32_t)0x00000002U) /*!< CRC error */\r
+#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */\r
+\r
+/** \r
+ * @brief Bit definition of RDES1 register\r
+ */ \r
+#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) /*!< Disable Interrupt on Completion */\r
+#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) /*!< Receive Buffer2 Size */\r
+#define ETH_DMARXDESC_RER ((uint32_t)0x00008000U) /*!< Receive End of Ring */\r
+#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) /*!< Second Address Chained */\r
+#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) /*!< Receive Buffer1 Size */\r
+\r
+/** \r
+ * @brief Bit definition of RDES2 register \r
+ */ \r
+#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */\r
+\r
+/** \r
+ * @brief Bit definition of RDES3 register \r
+ */ \r
+#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------------------\r
+ RDES4 | Reserved[31:15] | Extended Status [14:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES5 | Reserved[31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES6 | Receive Time Stamp Low [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES7 | Receive Time Stamp High [31:0] |\r
+ --------------------------------------------------------------------------------------------------------------------*/\r
+\r
+/* Bit definition of RDES4 register */\r
+#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */\r
+#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */\r
+#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */\r
+#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message (all clock types) */\r
+#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message (all clock types) */ \r
+#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message (all clock types) */ \r
+#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message (all clock types) */ \r
+#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ \r
+#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ \r
+#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ \r
+#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */\r
+#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */\r
+#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */\r
+#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */\r
+#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */\r
+#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */\r
+#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in the IP datagram */\r
+#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in the IP datagram */ \r
+#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in the IP datagram */\r
+\r
+/* Bit definition of RDES6 register */\r
+#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */\r
+\r
+/* Bit definition of RDES7 register */\r
+#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */\r
+/**\r
+ * @}\r
+ */\r
+ /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation \r
+ * @{\r
+ */ \r
+#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001U)\r
+#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_Speed ETH Speed \r
+ * @{\r
+ */ \r
+#define ETH_SPEED_10M ((uint32_t)0x00000000U)\r
+#define ETH_SPEED_100M ((uint32_t)0x00004000U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode\r
+ * @{\r
+ */ \r
+#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800U)\r
+#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_Rx_Mode ETH Rx Mode\r
+ * @{\r
+ */ \r
+#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000U)\r
+#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Checksum_Mode ETH Checksum Mode\r
+ * @{\r
+ */ \r
+#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000U)\r
+#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Media_Interface ETH Media Interface\r
+ * @{\r
+ */ \r
+#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000U)\r
+#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Watchdog ETH Watchdog \r
+ * @{\r
+ */ \r
+#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Jabber ETH Jabber\r
+ * @{\r
+ */ \r
+#define ETH_JABBER_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_JABBER_DISABLE ((uint32_t)0x00400000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap \r
+ * @{\r
+ */ \r
+#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000U) /*!< minimum IFG between frames during transmission is 96Bit */\r
+#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000U) /*!< minimum IFG between frames during transmission is 88Bit */\r
+#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000U) /*!< minimum IFG between frames during transmission is 80Bit */\r
+#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000U) /*!< minimum IFG between frames during transmission is 72Bit */\r
+#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000U) /*!< minimum IFG between frames during transmission is 64Bit */\r
+#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000U) /*!< minimum IFG between frames during transmission is 56Bit */\r
+#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000U) /*!< minimum IFG between frames during transmission is 48Bit */\r
+#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000U) /*!< minimum IFG between frames during transmission is 40Bit */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Carrier_Sense ETH Carrier Sense\r
+ * @{\r
+ */ \r
+#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Own ETH Receive Own \r
+ * @{\r
+ */ \r
+#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode \r
+ * @{\r
+ */ \r
+#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000U)\r
+#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Checksum_Offload ETH Checksum Offload\r
+ * @{\r
+ */ \r
+#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400U)\r
+#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Retry_Transmission ETH Retry Transmission\r
+ * @{\r
+ */ \r
+#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip\r
+ * @{\r
+ */ \r
+#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080U)\r
+#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit\r
+ * @{\r
+ */ \r
+#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000U)\r
+#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020U)\r
+#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040U)\r
+#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Deferral_Check ETH Deferral Check\r
+ * @{\r
+ */\r
+#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010U)\r
+#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_All ETH Receive All\r
+ * @{\r
+ */ \r
+#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000U)\r
+#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter\r
+ * @{\r
+ */ \r
+#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200U)\r
+#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300U)\r
+#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames\r
+ * @{\r
+ */ \r
+#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040U) /*!< MAC filters all control frames from reaching the application */\r
+#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080U) /*!< MAC forwards all control frames to application even if they fail the Address Filter */\r
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U) /*!< MAC forwards control frames that pass the Address Filter. */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception\r
+ * @{\r
+ */ \r
+#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter\r
+ * @{\r
+ */ \r
+#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000U)\r
+#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode\r
+ * @{\r
+ */ \r
+#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001U)\r
+#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter\r
+ * @{\r
+ */ \r
+#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404U)\r
+#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004U)\r
+#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U)\r
+#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter\r
+ * @{\r
+ */ \r
+#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U)\r
+#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002U)\r
+#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause \r
+ * @{\r
+ */ \r
+#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold\r
+ * @{\r
+ */ \r
+#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000U) /*!< Pause time minus 4 slot times */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010U) /*!< Pause time minus 28 slot times */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020U) /*!< Pause time minus 144 slot times */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030U) /*!< Pause time minus 256 slot times */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect\r
+ * @{\r
+ */ \r
+#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008U)\r
+#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control\r
+ * @{\r
+ */ \r
+#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004U)\r
+#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control\r
+ * @{\r
+ */ \r
+#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002U)\r
+#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison\r
+ * @{\r
+ */ \r
+#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000U)\r
+#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses ETH MAC addresses\r
+ * @{\r
+ */ \r
+#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)\r
+#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)\r
+#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)\r
+#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA \r
+ * @{\r
+ */ \r
+#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000U)\r
+#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes\r
+ * @{\r
+ */ \r
+#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000U) /*!< Mask MAC Address high reg bits [15:8] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000U) /*!< Mask MAC Address high reg bits [7:0] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000U) /*!< Mask MAC Address low reg bits [31:24] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000U) /*!< Mask MAC Address low reg bits [23:16] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000U) /*!< Mask MAC Address low reg bits [15:8] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000U) /*!< Mask MAC Address low reg bits [70] */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags\r
+ * @{\r
+ */ \r
+#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */\r
+#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */\r
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */\r
+#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */\r
+#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */\r
+#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */\r
+#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */\r
+#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */\r
+#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */\r
+#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */\r
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */\r
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */\r
+#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */\r
+#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */\r
+#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */\r
+#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */\r
+#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */\r
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */\r
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */\r
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */\r
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame\r
+ * @{\r
+ */ \r
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward\r
+ * @{\r
+ */ \r
+#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000U)\r
+#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame\r
+ * @{\r
+ */ \r
+#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000U)\r
+#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward\r
+ * @{\r
+ */ \r
+#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000U)\r
+#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control\r
+ * @{\r
+ */ \r
+#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000U) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000U) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000U) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000U) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000U) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000U) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000U) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames\r
+ * @{\r
+ */ \r
+#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080U)\r
+#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames\r
+ * @{\r
+ */ \r
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040U)\r
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000U) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control\r
+ * @{\r
+ */ \r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008U) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010U) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018U) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate\r
+ * @{\r
+ */ \r
+#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004U)\r
+#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000U) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats \r
+ * @{\r
+ */ \r
+#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000U)\r
+#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000U) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Fixed_Burst ETH Fixed Burst\r
+ * @{\r
+ */ \r
+#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000U)\r
+#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000U) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length\r
+ * @{\r
+ */ \r
+#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ \r
+#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length\r
+ * @{\r
+ */ \r
+#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ \r
+#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format\r
+ * @{\r
+ */ \r
+#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080U)\r
+#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration\r
+ * @{\r
+ */ \r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000U)\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000U)\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000U)\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000U)\r
+#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment\r
+ * @{\r
+ */ \r
+#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000U) /*!< Last Segment */\r
+#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000U) /*!< First Segment */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control\r
+ * @{\r
+ */ \r
+#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000U) /*!< Checksum engine bypass */\r
+#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000U) /*!< IPv4 header checksum insertion */\r
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */\r
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers \r
+ * @{\r
+ */ \r
+#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000U) /*!< DMA Rx Desc Buffer1 */\r
+#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001U) /*!< DMA Rx Desc Buffer2 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_PMT_Flags ETH PMT Flags\r
+ * @{\r
+ */ \r
+#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000U) /*!< Wake-Up Frame Filter Register Pointer Reset */\r
+#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040U) /*!< Wake-Up Frame Received */\r
+#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020U) /*!< Magic Packet Received */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts\r
+ * @{\r
+ */ \r
+#define ETH_MMC_IT_TGF ((uint32_t)0x00200000U) /*!< When Tx good frame counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000U) /*!< When Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000U) /*!< When Tx good single col counter reaches half the maximum value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts\r
+ * @{\r
+ */\r
+#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000U) /*!< When Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040U) /*!< When Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020U) /*!< When Rx crc error counter reaches half the maximum value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Flags ETH MAC Flags\r
+ * @{\r
+ */ \r
+#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger flag (on MAC) */\r
+#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit flag */\r
+#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020U) /*!< MMC receive flag */\r
+#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010U) /*!< MMC flag (on MAC) */\r
+#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008U) /*!< PMT flag (on MAC) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Flags ETH DMA Flags\r
+ * @{\r
+ */ \r
+#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U) /*!< Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000U) /*!< Error bits 0-write transfer, 1-read transfer */\r
+#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000U) /*!< Error bits 0-data buffer, 1-desc. access */\r
+#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary flag */\r
+#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary flag */\r
+#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000U) /*!< Early receive flag */\r
+#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error flag */\r
+#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400U) /*!< Early transmit flag */\r
+#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout flag */\r
+#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped flag */\r
+#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable flag */\r
+#define ETH_DMA_FLAG_R ((uint32_t)0x00000040U) /*!< Receive flag */\r
+#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020U) /*!< Underflow flag */\r
+#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010U) /*!< Overflow flag */\r
+#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout flag */\r
+#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable flag */\r
+#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped flag */\r
+#define ETH_DMA_FLAG_T ((uint32_t)0x00000001U) /*!< Transmit flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts \r
+ * @{\r
+ */ \r
+#define ETH_MAC_IT_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger interrupt (on MAC) */\r
+#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit interrupt */\r
+#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020U) /*!< MMC receive interrupt */\r
+#define ETH_MAC_IT_MMC ((uint32_t)0x00000010U) /*!< MMC interrupt (on MAC) */\r
+#define ETH_MAC_IT_PMT ((uint32_t)0x00000008U) /*!< PMT interrupt (on MAC) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts \r
+ * @{\r
+ */ \r
+#define ETH_DMA_IT_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_IT_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */\r
+#define ETH_DMA_IT_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */\r
+#define ETH_DMA_IT_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary */\r
+#define ETH_DMA_IT_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary */\r
+#define ETH_DMA_IT_ER ((uint32_t)0x00004000U) /*!< Early receive interrupt */\r
+#define ETH_DMA_IT_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error interrupt */\r
+#define ETH_DMA_IT_ET ((uint32_t)0x00000400U) /*!< Early transmit interrupt */\r
+#define ETH_DMA_IT_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout interrupt */\r
+#define ETH_DMA_IT_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped interrupt */\r
+#define ETH_DMA_IT_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable interrupt */\r
+#define ETH_DMA_IT_R ((uint32_t)0x00000040U) /*!< Receive interrupt */\r
+#define ETH_DMA_IT_TU ((uint32_t)0x00000020U) /*!< Underflow interrupt */\r
+#define ETH_DMA_IT_RO ((uint32_t)0x00000010U) /*!< Overflow interrupt */\r
+#define ETH_DMA_IT_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout interrupt */\r
+#define ETH_DMA_IT_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable interrupt */\r
+#define ETH_DMA_IT_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped interrupt */\r
+#define ETH_DMA_IT_T ((uint32_t)0x00000001U) /*!< Transmit interrupt */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state \r
+ * @{\r
+ */ \r
+#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Tx Command issued */\r
+#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000U) /*!< Running - fetching the Tx descriptor */\r
+#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000U) /*!< Running - waiting for status */\r
+#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000U) /*!< Running - reading the data from host memory */\r
+#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000U) /*!< Suspended - Tx Descriptor unavailable */\r
+#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000U) /*!< Running - closing Rx descriptor */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state \r
+ * @{\r
+ */ \r
+#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Rx Command issued */\r
+#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000U) /*!< Running - fetching the Rx descriptor */\r
+#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000U) /*!< Running - waiting for packet */\r
+#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000U) /*!< Suspended - Rx Descriptor unavailable */\r
+#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000U) /*!< Running - closing descriptor */\r
+#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000U) /*!< Running - queuing the receive frame into host memory */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_overflow ETH DMA overflow\r
+ * @{\r
+ */ \r
+#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000U) /*!< Overflow bit for FIFO overflow counter */\r
+#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U) /*!< Overflow bit for missed frame counter */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP\r
+ * @{\r
+ */ \r
+#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000U) /*!< External interrupt line 19 Connected to the ETH EXTI Line */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup ETH_Exported_Macros ETH Exported Macros\r
+ * @brief macros to handle interrupts and specific clock configurations\r
+ * @{\r
+ */\r
+ \r
+/** @brief Reset ETH handle state\r
+ * @param __HANDLE__: specifies the ETH handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)\r
+\r
+/** \r
+ * @brief Checks whether the specified Ethernet DMA Tx Desc flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag of TDES0 to check.\r
+ * @retval the ETH_DMATxDescFlag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet DMA Rx Desc flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag of RDES0 to check.\r
+ * @retval the ETH_DMATxDescFlag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Enables the specified DMA Rx Desc receive interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))\r
+\r
+/**\r
+ * @brief Disables the specified DMA Rx Desc receive interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)\r
+\r
+/**\r
+ * @brief Set the specified DMA Rx Desc Own bit.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)\r
+\r
+/**\r
+ * @brief Returns the specified Ethernet DMA Tx Desc collision count.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @retval The Transmit descriptor collision counter value.\r
+ */\r
+#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)\r
+\r
+/**\r
+ * @brief Set the specified DMA Tx Desc Own bit.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)\r
+\r
+/**\r
+ * @brief Enables the specified DMA Tx Desc Transmit interrupt.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)\r
+\r
+/**\r
+ * @brief Disables the specified DMA Tx Desc Transmit interrupt.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)\r
+\r
+/**\r
+ * @brief Selects the specified Ethernet DMA Tx Desc Checksum Insertion.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass\r
+ * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum\r
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present\r
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))\r
+\r
+/**\r
+ * @brief Enables the DMA Tx Desc CRC.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)\r
+\r
+/**\r
+ * @brief Disables the DMA Tx Desc CRC.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)\r
+\r
+/**\r
+ * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)\r
+\r
+/**\r
+ * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.\r
+ * @param __HANDLE__: ETH Handle \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)\r
+\r
+/** \r
+ * @brief Enables the specified Ethernet MAC interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be\r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt \r
+ * @arg ETH_MAC_IT_PMT : PMT interrupt \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified Ethernet MAC interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be\r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt \r
+ * @arg ETH_MAC_IT_PMT : PMT interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Initiate a Pause Control Frame (Full-duplex only).\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Checks whether the Ethernet flow control busy bit is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval The new state of flow control busy status bit (SET or RESET).\r
+ */\r
+#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Disables the MAC BackPressure operation activation (Half-duplex only).\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet MAC flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag \r
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag \r
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag \r
+ * @arg ETH_MAC_FLAG_MMC : MMC flag \r
+ * @arg ETH_MAC_FLAG_PMT : PMT flag \r
+ * @retval The state of Ethernet MAC flag.\r
+ */\r
+#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))\r
+\r
+/** \r
+ * @brief Enables the specified Ethernet DMA interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be\r
+ * enabled @ref ETH_DMA_Interrupts\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified Ethernet DMA interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be\r
+ * disabled. @ref ETH_DMA_Interrupts\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Clears the Ethernet DMA IT pending bit.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet DMA flag is set or not.\r
+* @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags\r
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet DMA flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags\r
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet DMA overflow flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __OVERFLOW__: specifies the DMA overflow flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter\r
+ * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter\r
+ * @retval The state of Ethernet DMA overflow Flag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))\r
+\r
+/**\r
+ * @brief Set the DMA Receive status watchdog timer register value\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __VALUE__: DMA Receive status watchdog timer register value \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))\r
+\r
+/** \r
+ * @brief Enables any unicast packet filtered by the MAC address\r
+ * recognition to be a wake-up frame.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)\r
+\r
+/**\r
+ * @brief Disables any unicast packet filtered by the MAC address\r
+ * recognition to be a wake-up frame.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)\r
+\r
+/**\r
+ * @brief Enables the MAC Wake-Up Frame Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)\r
+\r
+/**\r
+ * @brief Disables the MAC Wake-Up Frame Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)\r
+\r
+/**\r
+ * @brief Enables the MAC Magic Packet Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)\r
+\r
+/**\r
+ * @brief Disables the MAC Magic Packet Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)\r
+\r
+/**\r
+ * @brief Enables the MAC Power Down.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)\r
+\r
+/**\r
+ * @brief Disables the MAC Power Down.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)\r
+\r
+/**\r
+ * @brief Checks whether the specified Ethernet PMT flag is set or not.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset \r
+ * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received \r
+ * @arg ETH_PMT_FLAG_MPR : Magic Packet Received\r
+ * @retval The new state of Ethernet PMT Flag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))\r
+\r
+/** \r
+ * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))\r
+\r
+/**\r
+ * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\\r
+ (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)\r
+\r
+/**\r
+ * @brief Enables the MMC Counter Freeze.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)\r
+\r
+/**\r
+ * @brief Disables the MMC Counter Freeze.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)\r
+\r
+/**\r
+ * @brief Enables the MMC Reset On Read.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)\r
+\r
+/**\r
+ * @brief Disables the MMC Reset On Read.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)\r
+\r
+/**\r
+ * @brief Enables the MMC Counter Stop Rollover.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)\r
+\r
+/**\r
+ * @brief Disables the MMC Counter Stop Rollover.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)\r
+\r
+/**\r
+ * @brief Resets the MMC Counters.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)\r
+\r
+/**\r
+ * @brief Enables the specified Ethernet MMC Rx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)\r
+/**\r
+ * @brief Disables the specified Ethernet MMC Rx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)\r
+/**\r
+ * @brief Enables the specified Ethernet MMC Tx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified Ethernet MMC Tx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value \r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Enables the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Disables the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enable event on ETH External event line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Disable event on ETH External event line\r
+ * @retval None.\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Get flag of the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Clear flag of the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enables rising edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP\r
+ \r
+/**\r
+ * @brief Disables the rising edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) \r
+\r
+/**\r
+ * @brief Enables falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */ \r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Disables falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enables rising/falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\\r
+ EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP\r
+\r
+/**\r
+ * @brief Disables rising/falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\\r
+ EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Generate a Software interrupt on selected EXTI line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup ETH_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ****************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);\r
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* IO operation functions ****************************************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);\r
+/* Communication with PHY functions*/\r
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);\r
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);\r
+/* Callback in non blocking modes (Interrupt) */\r
+void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Peripheral Control functions **********************************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);\r
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Peripheral State functions ************************************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group4\r
+ * @{\r
+ */\r
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_ETH_H */\r
+\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
#include "FreeRTOS_DNS.h"\r
#include "NetworkBufferManagement.h"\r
#include "NetworkInterface.h"\r
+#include "phyHandling.h"\r
\r
/* ST includes. */\r
-#include "stm32f4xx_hal.h"\r
-\r
-#ifndef BMSR_LINK_STATUS\r
- #define BMSR_LINK_STATUS 0x0004UL\r
-#endif\r
-\r
-#ifndef PHY_LS_HIGH_CHECK_TIME_MS\r
- /* Check if the LinkSStatus in the PHY is still high after 15 seconds of not\r
- receiving packets. */\r
- #define PHY_LS_HIGH_CHECK_TIME_MS 15000\r
-#endif\r
-\r
-#ifndef PHY_LS_LOW_CHECK_TIME_MS\r
- /* Check if the LinkSStatus in the PHY is still low every second. */\r
- #define PHY_LS_LOW_CHECK_TIME_MS 1000\r
+#ifdef STM32F7xx\r
+ #include "stm32f7xx_hal.h"\r
+#else\r
+ #include "stm32f4xx_hal.h"\r
#endif\r
\r
/* Interrupt events to process. Currently only the Rx event is processed\r
ETH_DMA_IT_FBE | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \\r
ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T )\r
\r
-/* Naming and numbering of PHY registers. */\r
-#define PHY_REG_00_BMCR 0x00 /* Basic Mode Control Register. */\r
-#define PHY_REG_01_BMSR 0x01 /* Basic Mode Status Register. */\r
-#define PHY_REG_02_PHYSID1 0x02 /* PHYS ID 1 */\r
-#define PHY_REG_03_PHYSID2 0x03 /* PHYS ID 2 */\r
-#define PHY_REG_04_ADVERTISE 0x04 /* Advertisement control reg */\r
-\r
-#define PHY_ID_LAN8720 0x0007c0f0\r
-#define PHY_ID_DP83848I 0x20005C90\r
-\r
-#ifndef USE_STM324xG_EVAL\r
- #define USE_STM324xG_EVAL 1\r
-#endif\r
-\r
-#if( USE_STM324xG_EVAL == 0 )\r
- #define EXPECTED_PHY_ID PHY_ID_LAN8720\r
- #define PHY_REG_1F_PHYSPCS 0x1F /* 31 RW PHY Special Control Status */\r
- /* Use 3 bits in register 31 */\r
- #define PHYSPCS_SPEED_MASK 0x0C\r
- #define PHYSPCS_SPEED_10 0x04\r
- #define PHYSPCS_SPEED_100 0x08\r
- #define PHYSPCS_FULL_DUPLEX 0x10\r
-#else\r
- #define EXPECTED_PHY_ID PHY_ID_DP83848I\r
-\r
- #define PHY_REG_10_PHY_SR 0x10 /* PHY status register Offset */\r
- #define PHY_REG_19_PHYCR 0x19 /* 25 RW PHY Control Register */\r
-#endif\r
-\r
-/* Some defines used internally here to indicate preferences about speed, MDIX\r
-(wired direct or crossed), and duplex (half or full). */\r
-#define PHY_SPEED_10 1\r
-#define PHY_SPEED_100 2\r
-#define PHY_SPEED_AUTO (PHY_SPEED_10|PHY_SPEED_100)\r
-\r
-#define PHY_MDIX_DIRECT 1\r
-#define PHY_MDIX_CROSSED 2\r
-#define PHY_MDIX_AUTO (PHY_MDIX_CROSSED|PHY_MDIX_DIRECT)\r
-\r
-#define PHY_DUPLEX_HALF 1\r
-#define PHY_DUPLEX_FULL 2\r
-#define PHY_DUPLEX_AUTO (PHY_DUPLEX_FULL|PHY_DUPLEX_HALF)\r
\r
-#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */\r
-\r
-/*\r
- * Description of all capabilities that can be advertised to\r
- * the peer (usually a switch or router).\r
- */\r
-#define ADVERTISE_CSMA 0x0001 /* Only selector supported. */\r
-#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex. */\r
-#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex. */\r
-#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex. */\r
-#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex. */\r
-\r
-#define ADVERTISE_ALL ( ADVERTISE_10HALF | ADVERTISE_10FULL | \\r
- ADVERTISE_100HALF | ADVERTISE_100FULL)\r
-\r
-/*\r
- * Value for the 'PHY_REG_00_BMCR', the PHY's Basic Mode Control Register.\r
- */\r
-#define BMCR_FULLDPLX 0x0100 /* Full duplex. */\r
-#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart. */\r
-#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation. */\r
-#define BMCR_SPEED100 0x2000 /* Select 100Mbps. */\r
-#define BMCR_RESET 0x8000 /* Reset the PHY. */\r
-\r
-#define PHYCR_MDIX_EN 0x8000 /* Enable Auto MDIX. */\r
-#define PHYCR_MDIX_FORCE 0x4000 /* Force MDIX crossed. */\r
\r
#define ipFRAGMENT_OFFSET_BIT_MASK ( ( uint16_t ) 0x0fff ) /* The bits in the two byte IP header field that make up the fragment offset value. */\r
\r
#define configEMAC_TASK_STACK_SIZE ( 2 * configMINIMAL_STACK_SIZE )\r
#endif\r
\r
+/* Two choices must be made: RMII versus MII,\r
+and the index of the PHY in use ( between 0 and 31 ). */\r
+#ifndef ipconfigUSE_RMII\r
+ #ifdef STM32F7xx\r
+ #define ipconfigUSE_RMII 1\r
+ #else\r
+ #define ipconfigUSE_RMII 0\r
+ #endif /* STM32F7xx */\r
+#endif /* ipconfigUSE_RMII */\r
+\r
+\r
+\r
/*-----------------------------------------------------------*/\r
\r
/*\r
*/\r
static void prvDMARxDescListInit( void );\r
\r
-#if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
- /* After packets have been sent, the network\r
- buffers will be released. */\r
- static void vClearTXBuffers( void );\r
-#endif /* ipconfigZERO_COPY_TX_DRIVER */\r
+/* After packets have been sent, the network\r
+buffers will be released. */\r
+static void vClearTXBuffers( void );\r
\r
/*-----------------------------------------------------------*/\r
\r
-typedef struct _PhyProperties_t\r
-{\r
- uint8_t speed;\r
- uint8_t mdix;\r
- uint8_t duplex;\r
- uint8_t spare;\r
-} PhyProperties_t;\r
-\r
/* Bit map of outstanding ETH interrupt events for processing. Currently only\r
the Rx interrupt is handled, although code is included for other events to\r
enable future expansion. */\r
static volatile uint32_t ulISREvents;\r
\r
-/* A copy of PHY register 1: 'PHY_REG_01_BMSR' */\r
-static uint32_t ulPHYLinkStatus = 0;\r
-\r
#if( ipconfigUSE_LLMNR == 1 )\r
static const uint8_t xLLMNR_MACAddress[] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0xFC };\r
#endif\r
\r
+static EthernetPhy_t xPhyObject;\r
+\r
/* Ethernet handle. */\r
static ETH_HandleTypeDef xETH;\r
\r
-#if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
- /* xTXDescriptorSemaphore is a counting semaphore with\r
- a maximum count of ETH_TXBUFNB, which is the number of\r
- DMA TX descriptors. */\r
- static SemaphoreHandle_t xTXDescriptorSemaphore = NULL;\r
-#endif /* ipconfigZERO_COPY_TX_DRIVER */\r
+/* xTXDescriptorSemaphore is a counting semaphore with\r
+a maximum count of ETH_TXBUFNB, which is the number of\r
+DMA TX descriptors. */\r
+static SemaphoreHandle_t xTXDescriptorSemaphore = NULL;\r
\r
/*\r
* Note: it is adviced to define both\r
* TX buffers are allocated in a zero-copy driver.\r
*/\r
/* MAC buffers: ---------------------------------------------------------*/\r
-__ALIGN_BEGIN ETH_DMADescTypeDef DMARxDscrTab[ ETH_RXBUFNB ] __ALIGN_END;/* Ethernet Rx MA Descriptor */\r
+\r
+/* Put the DMA descriptors in '.first_data'.\r
+This is important for STM32F7, which has an L1 data cache.\r
+The first 64KB of the SRAM is not cached. */\r
+\r
+/* Ethernet Rx MA Descriptor */\r
+__attribute__ ((aligned (32)))\r
+__attribute__ ((section(".first_data")))\r
+ ETH_DMADescTypeDef DMARxDscrTab[ ETH_RXBUFNB ];\r
+\r
#if( ipconfigZERO_COPY_RX_DRIVER == 0 )\r
- __ALIGN_BEGIN uint8_t Rx_Buff[ ETH_RXBUFNB ][ ETH_RX_BUF_SIZE ] __ALIGN_END; /* Ethernet Receive Buffer */\r
+ /* Ethernet Receive Buffer */\r
+ __ALIGN_BEGIN uint8_t Rx_Buff[ ETH_RXBUFNB ][ ETH_RX_BUF_SIZE ] __ALIGN_END;\r
#endif\r
\r
-__ALIGN_BEGIN ETH_DMADescTypeDef DMATxDscrTab[ ETH_TXBUFNB ] __ALIGN_END;/* Ethernet Tx DMA Descriptor */\r
+/* Ethernet Tx DMA Descriptor */\r
+__attribute__ ((aligned (32)))\r
+__attribute__ ((section(".first_data")))\r
+ ETH_DMADescTypeDef DMATxDscrTab[ ETH_TXBUFNB ];\r
+\r
#if( ipconfigZERO_COPY_TX_DRIVER == 0 )\r
- __ALIGN_BEGIN uint8_t Tx_Buff[ ETH_TXBUFNB ][ ETH_TX_BUF_SIZE ] __ALIGN_END; /* Ethernet Transmit Buffer */\r
+ /* Ethernet Transmit Buffer */\r
+ __ALIGN_BEGIN uint8_t Tx_Buff[ ETH_TXBUFNB ][ ETH_TX_BUF_SIZE ] __ALIGN_END;\r
#endif\r
\r
#if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
static __IO ETH_DMADescTypeDef *DMATxDescToClear;\r
#endif\r
\r
-/* Value to be written into the 'Basic mode Control Register'. */\r
-static uint32_t ulBCRvalue;\r
-\r
-/* Value to be written into the 'Advertisement Control Register'. */\r
-static uint32_t ulACRValue;\r
-\r
/* ucMACAddress as it appears in main.c */\r
extern const uint8_t ucMACAddress[ 6 ];\r
\r
const PhyProperties_t xPHYProperties =\r
{\r
#if( ipconfigETHERNET_AN_ENABLE != 0 )\r
- .speed = PHY_SPEED_AUTO,\r
- .duplex = PHY_DUPLEX_AUTO,\r
+ .ucSpeed = PHY_SPEED_AUTO,\r
+ .ucDuplex = PHY_DUPLEX_AUTO,\r
#else\r
#if( ipconfigETHERNET_USE_100MB != 0 )\r
- .speed = PHY_SPEED_100,\r
+ .ucSpeed = PHY_SPEED_100,\r
#else\r
- .speed = PHY_SPEED_10,\r
+ .ucSpeed = PHY_SPEED_10,\r
#endif\r
\r
#if( ipconfigETHERNET_USE_FULL_DUPLEX != 0 )\r
#endif\r
\r
#if( ipconfigETHERNET_AN_ENABLE != 0 ) && ( ipconfigETHERNET_AUTO_CROSS_ENABLE != 0 )\r
- .mdix = PHY_MDIX_AUTO,\r
+ .ucMDI_X = PHY_MDIX_AUTO,\r
#elif( ipconfigETHERNET_CROSSED_LINK != 0 )\r
- .mdix = PHY_MDIX_CROSSED,\r
+ .ucMDI_X = PHY_MDIX_CROSSED,\r
#else\r
- .mdix = PHY_MDIX_DIRECT,\r
+ .ucMDI_X = PHY_MDIX_DIRECT,\r
#endif\r
};\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-#if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
- void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef *heth )\r
- {\r
- BaseType_t xHigherPriorityTaskWoken = pdFALSE;\r
-\r
- /* This call-back is only useful in case packets are being sent\r
- zero-copy. Once they're sent, the buffers will be released\r
- by the function vClearTXBuffers(). */\r
- ulISREvents |= EMAC_IF_TX_EVENT;\r
- /* Wakeup the prvEMACHandlerTask. */\r
- if( xEMACTaskHandle != NULL )\r
- {\r
- vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken );\r
- portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r
- }\r
+void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef *heth )\r
+{\r
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;\r
\r
+ /* This call-back is only useful in case packets are being sent\r
+ zero-copy. Once they're sent, the buffers will be released\r
+ by the function vClearTXBuffers(). */\r
+ ulISREvents |= EMAC_IF_TX_EVENT;\r
+ /* Wakeup the prvEMACHandlerTask. */\r
+ if( xEMACTaskHandle != NULL )\r
+ {\r
+ vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken );\r
+ portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r
}\r
-#endif /* ipconfigZERO_COPY_TX_DRIVER */\r
\r
+}\r
/*-----------------------------------------------------------*/\r
\r
+static void vClearTXBuffers()\r
+{\r
+__IO ETH_DMADescTypeDef *txLastDescriptor = xETH.TxDesc;\r
+size_t uxCount = ( ( UBaseType_t ) ETH_TXBUFNB ) - uxSemaphoreGetCount( xTXDescriptorSemaphore );\r
#if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
- static void vClearTXBuffers()\r
- {\r
- __IO ETH_DMADescTypeDef *txLastDescriptor = xETH.TxDesc;\r
NetworkBufferDescriptor_t *pxNetworkBuffer;\r
uint8_t *ucPayLoad;\r
- size_t uxCount = ( ( UBaseType_t ) ETH_TXBUFNB ) - uxSemaphoreGetCount( xTXDescriptorSemaphore );\r
+#endif\r
\r
- /* This function is called after a TX-completion interrupt.\r
- It will release each Network Buffer used in xNetworkInterfaceOutput().\r
- 'uxCount' represents the number of descriptors given to DMA for transmission.\r
- After sending a packet, the DMA will clear the 'ETH_DMATXDESC_OWN' bit. */\r
- while( ( uxCount > 0 ) && ( ( DMATxDescToClear->Status & ETH_DMATXDESC_OWN ) == 0 ) )\r
+ /* This function is called after a TX-completion interrupt.\r
+ It will release each Network Buffer used in xNetworkInterfaceOutput().\r
+ 'uxCount' represents the number of descriptors given to DMA for transmission.\r
+ After sending a packet, the DMA will clear the 'ETH_DMATXDESC_OWN' bit. */\r
+ while( ( uxCount > 0 ) && ( ( DMATxDescToClear->Status & ETH_DMATXDESC_OWN ) == 0 ) )\r
+ {\r
+ if( ( DMATxDescToClear == txLastDescriptor ) && ( uxCount != ETH_TXBUFNB ) )\r
+ {\r
+ break;\r
+ }\r
+ #if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
{\r
- if( ( DMATxDescToClear == txLastDescriptor ) && ( uxCount != ETH_TXBUFNB ) )\r
- {\r
- break;\r
- }\r
-\r
ucPayLoad = ( uint8_t * )DMATxDescToClear->Buffer1Addr;\r
\r
if( ucPayLoad != NULL )\r
}\r
DMATxDescToClear->Buffer1Addr = ( uint32_t )0u;\r
}\r
+ }\r
+ #endif /* ipconfigZERO_COPY_TX_DRIVER */\r
\r
- DMATxDescToClear = ( ETH_DMADescTypeDef * )( DMATxDescToClear->Buffer2NextDescAddr );\r
+ DMATxDescToClear = ( ETH_DMADescTypeDef * )( DMATxDescToClear->Buffer2NextDescAddr );\r
\r
- uxCount--;\r
- /* Tell the counting semaphore that one more TX descriptor is available. */\r
- xSemaphoreGive( xTXDescriptorSemaphore );\r
- }\r
+ uxCount--;\r
+ /* Tell the counting semaphore that one more TX descriptor is available. */\r
+ xSemaphoreGive( xTXDescriptorSemaphore );\r
}\r
-#endif /* ipconfigZERO_COPY_TX_DRIVER */\r
+}\r
/*-----------------------------------------------------------*/\r
\r
BaseType_t xNetworkInterfaceInitialise( void )\r
\r
if( xEMACTaskHandle == NULL )\r
{\r
- #if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
+ if( xTXDescriptorSemaphore == NULL )\r
{\r
- if( xTXDescriptorSemaphore == NULL )\r
- {\r
- xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ETH_TXBUFNB, ( UBaseType_t ) ETH_TXBUFNB );\r
- configASSERT( xTXDescriptorSemaphore );\r
- }\r
+ xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ETH_TXBUFNB, ( UBaseType_t ) ETH_TXBUFNB );\r
+ configASSERT( xTXDescriptorSemaphore );\r
}\r
- #endif /* ipconfigZERO_COPY_TX_DRIVER */\r
\r
/* Initialise ETH */\r
\r
xETH.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;\r
xETH.Init.Speed = ETH_SPEED_100M;\r
xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX;\r
- xETH.Init.PhyAddress = 1;\r
+ /* Value of PhyAddress doesn't matter, will be probed for. */\r
+ xETH.Init.PhyAddress = 0;\r
\r
xETH.Init.MACAddr = ( uint8_t *) ucMACAddress;\r
xETH.Init.RxMode = ETH_RXINTERRUPT_MODE;\r
by the peripheral. */\r
xETH.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;\r
\r
- xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_MII;\r
+ #if( ipconfigUSE_RMII != 0 )\r
+ {\r
+ xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;\r
+ }\r
+ #else\r
+ {\r
+ xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_MII;\r
+ }\r
+ #endif /* ipconfigUSE_RMII */\r
+\r
hal_eth_init_status = HAL_ETH_Init( &xETH );\r
\r
/* Only for inspection by debugger. */\r
memset( &DMATxDscrTab, '\0', sizeof( DMATxDscrTab ) );\r
memset( &DMARxDscrTab, '\0', sizeof( DMARxDscrTab ) );\r
\r
- #if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
- {\r
- /* Initialize Tx Descriptors list: Chain Mode */\r
- DMATxDescToClear = DMATxDscrTab;\r
- }\r
- #endif /* ipconfigZERO_COPY_TX_DRIVER */\r
+ /* Initialize Tx Descriptors list: Chain Mode */\r
+ DMATxDescToClear = DMATxDscrTab;\r
\r
/* Initialise TX-descriptors. */\r
prvDMATxDescListInit();\r
xTaskCreate( prvEMACHandlerTask, "EMAC", configEMAC_TASK_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, &xEMACTaskHandle );\r
} /* if( xEMACTaskHandle == NULL ) */\r
\r
- if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 )\r
+ if( xPhyObject.ulLinkStatusMask != 0 )\r
{\r
xETH.Instance->DMAIER |= ETH_DMA_ALL_INTS;\r
xResult = pdPASS;\r
else\r
{\r
/* For now pdFAIL will be returned. But prvEMACHandlerTask() is running\r
- and it will keep on checking the PHY and set ulPHYLinkStatus when necessary. */\r
+ and it will keep on checking the PHY and set 'ulLinkStatusMask' when necessary. */\r
xResult = pdFAIL;\r
FreeRTOS_printf( ( "Link Status still low\n" ) ) ;\r
}\r
{\r
ProtocolPacket_t *pxPacket;\r
\r
+ #if( ipconfigZERO_COPY_RX_DRIVER != 0 )\r
+ {\r
+ configASSERT( bReleaseAfterSend != 0 );\r
+ }\r
+ #endif /* ipconfigZERO_COPY_RX_DRIVER */\r
+\r
/* If the peripheral must calculate the checksum, it wants\r
the protocol checksum to have a value of zero. */\r
pxPacket = ( ProtocolPacket_t * ) ( pxDescriptor->pucEthernetBuffer );\r
/* Open a do {} while ( 0 ) loop to be able to call break. */\r
do\r
{\r
- if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 )\r
+ if( xPhyObject.ulLinkStatusMask != 0 )\r
{\r
- #if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
+ if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS )\r
{\r
- if( xTXDescriptorSemaphore == NULL )\r
- {\r
- break;\r
- }\r
- if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS )\r
- {\r
- /* Time-out waiting for a free TX descriptor. */\r
- break;\r
- }\r
+ /* Time-out waiting for a free TX descriptor. */\r
+ break;\r
}\r
- #endif /* ipconfigZERO_COPY_TX_DRIVER */\r
\r
/* This function does the actual transmission of the packet. The packet is\r
contained in 'pxDescriptor' that is passed to the function. */\r
pxDmaTxDesc = xETH.TxDesc;\r
\r
/* Is this buffer available? */\r
- if( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) == 0 )\r
+ configASSERT ( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) == 0 );\r
+\r
{\r
/* Is this buffer available? */\r
/* Get bytes in current buffer. */\r
{\r
/* Copy the bytes. */\r
memcpy( ( void * ) pxDmaTxDesc->Buffer1Addr, pxDescriptor->pucEthernetBuffer, ulTransmitSize );\r
- pxDmaTxDesc->Status |= ETH_DMATXDESC_CIC_TCPUDPICMP_FULL;\r
}\r
#else\r
{\r
/* Move the buffer. */\r
pxDmaTxDesc->Buffer1Addr = ( uint32_t )pxDescriptor->pucEthernetBuffer;\r
- /* Ask to set the IPv4 checksum.\r
- Also need an Interrupt on Completion so that 'vClearTXBuffers()' will be called.. */\r
- pxDmaTxDesc->Status |= ETH_DMATXDESC_CIC_TCPUDPICMP_FULL | ETH_DMATXDESC_IC;\r
/* The Network Buffer has been passed to DMA, no need to release it. */\r
bReleaseAfterSend = pdFALSE_UNSIGNED;\r
}\r
#endif /* ipconfigZERO_COPY_TX_DRIVER */\r
\r
+ /* Ask to set the IPv4 checksum.\r
+ Also need an Interrupt on Completion so that 'vClearTXBuffers()' will be called.. */\r
+ pxDmaTxDesc->Status |= ETH_DMATXDESC_CIC_TCPUDPICMP_FULL | ETH_DMATXDESC_IC;\r
+\r
/* Prepare transmit descriptors to give to DMA. */\r
\r
/* Set LAST and FIRST segment */\r
\r
/* Point to next descriptor */\r
xETH.TxDesc = ( ETH_DMADescTypeDef * ) ( xETH.TxDesc->Buffer2NextDescAddr );\r
- \r
+ /* Ensure completion of memory access */\r
+ __DSB();\r
/* Resume DMA transmission*/\r
xETH.Instance->DMATPDR = 0;\r
iptraceNETWORK_INTERFACE_TRANSMIT();\r
pxDMARxDescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | (uint32_t)ETH_RX_BUF_SIZE; \r
pxDMARxDescriptor->Status = ETH_DMARXDESC_OWN;\r
\r
+ /* Ensure completion of memory access */\r
+ __DSB();\r
/* When Rx Buffer unavailable flag is set clear it and resume\r
reception. */\r
if( ( xETH.Instance->DMASR & ETH_DMASR_RBUS ) != 0 )\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vMACBProbePhy( void )\r
-{\r
-uint32_t ulConfig, ulAdvertise, ulLower, ulUpper, ulMACPhyID, ulValue;\r
-TimeOut_t xPhyTime;\r
-TickType_t xRemTime = 0;\r
-#if( EXPECTED_PHY_ID == PHY_ID_DP83848I )\r
- uint32_t ulPhyControl;\r
-#endif\r
-\r
- HAL_ETH_ReadPHYRegister(&xETH, PHY_REG_03_PHYSID2, &ulLower);\r
- HAL_ETH_ReadPHYRegister(&xETH, PHY_REG_02_PHYSID1, &ulUpper);\r
-\r
- ulMACPhyID = ( ( ulUpper << 16 ) & 0xFFFF0000 ) | ( ulLower & 0xFFF0 );\r
\r
- /* The expected ID for the 'LAN8720' is 0x0007c0f0. */\r
- /* The expected ID for the 'DP83848I' is 0x20005C90. */\r
-\r
- FreeRTOS_printf( ( "PHY ID %lX (%s)\n", ulMACPhyID,\r
- ( ulMACPhyID == EXPECTED_PHY_ID ) ? "OK" : "Unknown" ) );\r
+BaseType_t xSTM32_PhyRead( BaseType_t xAddress, BaseType_t xRegister, uint32_t *pulValue )\r
+{\r
+uint16_t usPrevAddress = xETH.Init.PhyAddress;\r
+BaseType_t xResult;\r
+HAL_StatusTypeDef xHALResult;\r
\r
- /* Remove compiler warning if FreeRTOS_printf() is not defined. */\r
- ( void ) ulMACPhyID;\r
+ xETH.Init.PhyAddress = xAddress;\r
+ xHALResult = HAL_ETH_ReadPHYRegister( &xETH, ( uint16_t )xRegister, pulValue );\r
+ xETH.Init.PhyAddress = usPrevAddress;\r
\r
- /* Set advertise register. */\r
- if( ( xPHYProperties.speed == PHY_SPEED_AUTO ) && ( xPHYProperties.duplex == PHY_DUPLEX_AUTO ) )\r
+ if( xHALResult == HAL_OK )\r
{\r
- ulAdvertise = ADVERTISE_CSMA | ADVERTISE_ALL;\r
- /* Reset auto-negotiation capability. */\r
+ xResult = 0;\r
}\r
else\r
{\r
- ulAdvertise = ADVERTISE_CSMA;\r
-\r
- if( xPHYProperties.speed == PHY_SPEED_AUTO )\r
- {\r
- if( xPHYProperties.duplex == PHY_DUPLEX_FULL )\r
- {\r
- ulAdvertise |= ADVERTISE_10FULL | ADVERTISE_100FULL;\r
- }\r
- else\r
- {\r
- ulAdvertise |= ADVERTISE_10HALF | ADVERTISE_100HALF;\r
- }\r
- }\r
- else if( xPHYProperties.duplex == PHY_DUPLEX_AUTO )\r
- {\r
- if( xPHYProperties.speed == PHY_SPEED_10 )\r
- {\r
- ulAdvertise |= ADVERTISE_10FULL | ADVERTISE_10HALF;\r
- }\r
- else\r
- {\r
- ulAdvertise |= ADVERTISE_100FULL | ADVERTISE_100HALF;\r
- }\r
- }\r
- else if( xPHYProperties.speed == PHY_SPEED_100 )\r
- {\r
- if( xPHYProperties.duplex == PHY_DUPLEX_FULL )\r
- {\r
- ulAdvertise |= ADVERTISE_100FULL;\r
- }\r
- else\r
- {\r
- ulAdvertise |= ADVERTISE_100HALF;\r
- }\r
- }\r
- else\r
- {\r
- if( xPHYProperties.duplex == PHY_DUPLEX_FULL )\r
- {\r
- ulAdvertise |= ADVERTISE_10FULL;\r
- }\r
- else\r
- {\r
- ulAdvertise |= ADVERTISE_10HALF;\r
- }\r
- }\r
- }\r
-\r
- /* Read Control register. */\r
- HAL_ETH_ReadPHYRegister( &xETH, PHY_REG_00_BMCR, &ulConfig );\r
-\r
- HAL_ETH_WritePHYRegister( &xETH, PHY_REG_00_BMCR, ulConfig | BMCR_RESET );\r
- xRemTime = ( TickType_t ) pdMS_TO_TICKS( 1000UL );\r
- vTaskSetTimeOutState( &xPhyTime );\r
-\r
- for( ; ; )\r
- {\r
- HAL_ETH_ReadPHYRegister( &xETH, PHY_REG_00_BMCR, &ulValue );\r
- if( ( ulValue & BMCR_RESET ) == 0 )\r
- {\r
- FreeRTOS_printf( ( "BMCR_RESET ready\n" ) );\r
- break;\r
- }\r
- if( xTaskCheckForTimeOut( &xPhyTime, &xRemTime ) != pdFALSE )\r
- {\r
- FreeRTOS_printf( ( "BMCR_RESET timed out\n" ) );\r
- break;\r
- }\r
+ xResult = -1;\r
}\r
- HAL_ETH_WritePHYRegister( &xETH, PHY_REG_00_BMCR, ulConfig & ~BMCR_RESET );\r
+ return xResult;\r
+}\r
+/*-----------------------------------------------------------*/\r
\r
- vTaskDelay( pdMS_TO_TICKS( 50ul ) );\r
+BaseType_t xSTM32_PhyWrite( BaseType_t xAddress, BaseType_t xRegister, uint32_t ulValue )\r
+{\r
+uint16_t usPrevAddress = xETH.Init.PhyAddress;\r
+BaseType_t xResult;\r
+HAL_StatusTypeDef xHALResult;\r
\r
- /* Write advertise register. */\r
- HAL_ETH_WritePHYRegister( &xETH, PHY_REG_04_ADVERTISE, ulAdvertise );\r
+ xETH.Init.PhyAddress = xAddress;\r
+ xHALResult = HAL_ETH_WritePHYRegister( &xETH, ( uint16_t )xRegister, ulValue );\r
+ xETH.Init.PhyAddress = usPrevAddress;\r
\r
- /*\r
- AN_EN AN1 AN0 Forced Mode\r
- 0 0 0 10BASE-T, Half-Duplex\r
- 0 0 1 10BASE-T, Full-Duplex\r
- 0 1 0 100BASE-TX, Half-Duplex\r
- 0 1 1 100BASE-TX, Full-Duplex\r
- AN_EN AN1 AN0 Advertised Mode\r
- 1 0 0 10BASE-T, Half/Full-Duplex\r
- 1 0 1 100BASE-TX, Half/Full-Duplex\r
- 1 1 0 10BASE-T Half-Duplex\r
- 100BASE-TX, Half-Duplex\r
- 1 1 1 10BASE-T, Half/Full-Duplex\r
- 100BASE-TX, Half/Full-Duplex\r
- */\r
-\r
- /* Read Control register. */\r
- HAL_ETH_ReadPHYRegister( &xETH, PHY_REG_00_BMCR, &ulConfig );\r
-\r
- ulConfig &= ~( BMCR_ANRESTART | BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX );\r
-\r
- /* HT 12/9/14: always set AN-restart and AN-enable, even though the choices\r
- are limited. */\r
- ulConfig |= (BMCR_ANRESTART | BMCR_ANENABLE);\r
-\r
- if( xPHYProperties.speed == PHY_SPEED_100 )\r
+ if( xHALResult == HAL_OK )\r
{\r
- ulConfig |= BMCR_SPEED100;\r
+ xResult = 0;\r
}\r
- else if( xPHYProperties.speed == PHY_SPEED_10 )\r
+ else\r
{\r
- ulConfig &= ~BMCR_SPEED100;\r
+ xResult = -1;\r
}\r
+ return xResult;\r
+}\r
+/*-----------------------------------------------------------*/\r
\r
- if( xPHYProperties.duplex == PHY_DUPLEX_FULL )\r
- {\r
- ulConfig |= BMCR_FULLDPLX;\r
- }\r
- else if( xPHYProperties.duplex == PHY_DUPLEX_HALF )\r
- {\r
- ulConfig &= ~BMCR_FULLDPLX;\r
- }\r
+void phy_test()\r
+{\r
+BaseType_t xPhyCount;\r
+BaseType_t xPhyIndex;\r
\r
- #if( EXPECTED_PHY_ID == PHY_ID_LAN8720 )\r
- {\r
- }\r
- #elif( EXPECTED_PHY_ID == PHY_ID_DP83848I )\r
+ vPhyInitialise( &xPhyObject, xSTM32_PhyRead, xSTM32_PhyWrite );\r
+ xPhyCount = xPhyDiscover( &xPhyObject );\r
+ FreeRTOS_printf( ( "PHY count %ld\n", xPhyCount ) );\r
+ for( xPhyIndex = 0; xPhyIndex < xPhyCount; xPhyIndex++ )\r
{\r
- /* Read PHY Control register. */\r
- HAL_ETH_ReadPHYRegister( &xETH, PHY_REG_19_PHYCR, &ulPhyControl );\r
+ FreeRTOS_printf( ( "PHY[%d] at address %d ( 0x%08X )\n",\r
+ xPhyIndex,\r
+ xPhyObject.ucPhyIndexes[ xPhyIndex ],\r
+ xPhyObject.ulPhyIDs[ xPhyIndex ] ) );\r
\r
- /* Clear bits which might get set: */\r
- ulPhyControl &= ~( PHYCR_MDIX_EN|PHYCR_MDIX_FORCE );\r
-\r
- if( xPHYProperties.mdix == PHY_MDIX_AUTO )\r
- {\r
- ulPhyControl |= PHYCR_MDIX_EN;\r
- }\r
- else if( xPHYProperties.mdix == PHY_MDIX_CROSSED )\r
- {\r
- /* Force direct link = Use crossed RJ45 cable. */\r
- ulPhyControl &= ~PHYCR_MDIX_FORCE;\r
- }\r
- else\r
- {\r
- /* Force crossed link = Use direct RJ45 cable. */\r
- ulPhyControl |= PHYCR_MDIX_FORCE;\r
- }\r
- /* update PHY Control Register. */\r
- HAL_ETH_WritePHYRegister( &xETH, PHY_REG_19_PHYCR, ulPhyControl );\r
}\r
- #endif\r
- FreeRTOS_printf( ( "+TCP: advertise: %lX config %lX\n", ulAdvertise, ulConfig ) );\r
+ \r
+}\r
\r
- /* Now the two values to global values for later use. */\r
- ulBCRvalue = ulConfig;\r
- ulACRValue = ulAdvertise;\r
+void vMACBProbePhy( void )\r
+{\r
+ vPhyInitialise( &xPhyObject, xSTM32_PhyRead, xSTM32_PhyWrite );\r
+ xPhyDiscover( &xPhyObject );\r
+ xPhyConfigure( &xPhyObject, &xPHYProperties );\r
}\r
/*-----------------------------------------------------------*/\r
\r
static void prvEthernetUpdateConfig( BaseType_t xForce )\r
{\r
-__IO uint32_t ulTimeout = 0;\r
-uint32_t ulRegValue = 0;\r
-\r
- FreeRTOS_printf( ( "prvEthernetUpdateConfig: LS %d Force %d\n",\r
- ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 ,\r
- xForce ) );\r
+ FreeRTOS_printf( ( "prvEthernetUpdateConfig: LS mask %02lX Force %d\n",\r
+ xPhyObject.ulLinkStatusMask,\r
+ ( int )xForce ) );\r
\r
- if( ( xForce != pdFALSE ) || ( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 ) )\r
+ if( ( xForce != pdFALSE ) || ( xPhyObject.ulLinkStatusMask != 0 ) )\r
{\r
/* Restart the auto-negotiation. */\r
if( xETH.Init.AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE )\r
{\r
- /* Enable Auto-Negotiation. */\r
- HAL_ETH_WritePHYRegister( &xETH, PHY_REG_00_BMCR, ulBCRvalue | BMCR_ANRESTART );\r
- HAL_ETH_WritePHYRegister( &xETH, PHY_REG_04_ADVERTISE, ulACRValue);\r
+ xPhyStartAutoNegotiation( &xPhyObject, xPhyGetMask( &xPhyObject ) );\r
\r
- /* Wait until the auto-negotiation will be completed */\r
- do\r
+ /* Configure the MAC with the Duplex Mode fixed by the\r
+ auto-negotiation process. */\r
+ if( xPhyObject.xPhyProperties.ucDuplex == PHY_DUPLEX_FULL )\r
{\r
- ulTimeout++;\r
- HAL_ETH_ReadPHYRegister( &xETH, PHY_REG_01_BMSR, &ulRegValue );\r
- } while( ( ( ulRegValue & PHY_AUTONEGO_COMPLETE) == 0 ) && ( ulTimeout < PHY_READ_TO ) );\r
-\r
- HAL_ETH_WritePHYRegister( &xETH, PHY_REG_00_BMCR, ulBCRvalue & ~BMCR_ANRESTART );\r
-\r
- if( ulTimeout < PHY_READ_TO )\r
+ xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX;\r
+ }\r
+ else\r
{\r
- /* Reset Timeout counter. */\r
- ulTimeout = 0;\r
-\r
- HAL_ETH_ReadPHYRegister( &xETH, PHY_REG_01_BMSR, &ulRegValue);\r
- if( ( ulRegValue & BMSR_LINK_STATUS ) != 0 )\r
- {\r
- ulPHYLinkStatus |= BMSR_LINK_STATUS;\r
- }\r
- else\r
- {\r
- ulPHYLinkStatus &= ~( BMSR_LINK_STATUS );\r
- }\r
-\r
- #if( EXPECTED_PHY_ID == PHY_ID_LAN8720 )\r
- {\r
- /* 31 RW PHY Special Control Status */\r
- uint32_t ulControlStatus;\r
-\r
- HAL_ETH_ReadPHYRegister( &xETH, PHY_REG_1F_PHYSPCS, &ulControlStatus);\r
- ulRegValue = 0;\r
- if( ( ulControlStatus & PHYSPCS_FULL_DUPLEX ) != 0 )\r
- {\r
- ulRegValue |= PHY_DUPLEX_STATUS;\r
- }\r
- if( ( ulControlStatus & PHYSPCS_SPEED_MASK ) == PHYSPCS_SPEED_10 )\r
- {\r
- ulRegValue |= PHY_SPEED_STATUS;\r
- }\r
-\r
- }\r
- #elif( EXPECTED_PHY_ID == PHY_ID_DP83848I )\r
- {\r
- /* Read the result of the auto-negotiation. */\r
- HAL_ETH_ReadPHYRegister( &xETH, PHY_REG_10_PHY_SR, &ulRegValue);\r
- }\r
- #endif\r
- FreeRTOS_printf( ( ">> Autonego ready: %08lx: %s duplex %u mbit %s status\n",\r
- ulRegValue,\r
- (ulRegValue & PHY_DUPLEX_STATUS) ? "full" : "half",\r
- (ulRegValue & PHY_SPEED_STATUS) ? 10 : 100,\r
- ((ulPHYLinkStatus |= BMSR_LINK_STATUS) != 0) ? "high" : "low" ) );\r
-\r
- /* Configure the MAC with the Duplex Mode fixed by the\r
- auto-negotiation process. */\r
- if( ( ulRegValue & PHY_DUPLEX_STATUS ) != ( uint32_t ) RESET )\r
- {\r
- /* Set Ethernet duplex mode to Full-duplex following the\r
- auto-negotiation. */\r
- xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX;\r
- }\r
- else\r
- {\r
- /* Set Ethernet duplex mode to Half-duplex following the\r
- auto-negotiation. */\r
- xETH.Init.DuplexMode = ETH_MODE_HALFDUPLEX;\r
- }\r
+ xETH.Init.DuplexMode = ETH_MODE_HALFDUPLEX;\r
+ }\r
\r
- /* Configure the MAC with the speed fixed by the\r
- auto-negotiation process. */\r
- if( ( ulRegValue & PHY_SPEED_STATUS) != 0 )\r
- {\r
- /* Set Ethernet speed to 10M following the\r
- auto-negotiation. */\r
- xETH.Init.Speed = ETH_SPEED_10M;\r
- }\r
- else\r
- {\r
- /* Set Ethernet speed to 100M following the\r
- auto-negotiation. */\r
- xETH.Init.Speed = ETH_SPEED_100M;\r
- }\r
- } /* if( ulTimeout < PHY_READ_TO ) */\r
+ /* Configure the MAC with the speed fixed by the\r
+ auto-negotiation process. */\r
+ if( xPhyObject.xPhyProperties.ucSpeed == PHY_SPEED_10 )\r
+ {\r
+ xETH.Init.Speed = ETH_SPEED_10M;\r
+ }\r
+ else\r
+ {\r
+ xETH.Init.Speed = ETH_SPEED_100M;\r
+ }\r
}\r
else /* AutoNegotiation Disable */\r
{\r
- uint16_t usValue;\r
-\r
/* Check parameters */\r
assert_param( IS_ETH_SPEED( xETH.Init.Speed ) );\r
assert_param( IS_ETH_DUPLEX_MODE( xETH.Init.DuplexMode ) );\r
\r
- /* Set MAC Speed and Duplex Mode to PHY */\r
- usValue = ( uint16_t ) ( xETH.Init.DuplexMode >> 3 ) | ( uint16_t ) ( xETH.Init.Speed >> 1 );\r
- HAL_ETH_WritePHYRegister( &xETH, PHY_REG_00_BMCR, usValue );\r
+ if( xETH.Init.DuplexMode == ETH_MODE_FULLDUPLEX )\r
+ {\r
+ xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_HALF;\r
+ }\r
+ else\r
+ {\r
+ xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_FULL;\r
+ }\r
+\r
+ if( xETH.Init.Speed == ETH_SPEED_10M )\r
+ {\r
+ xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_10;\r
+ }\r
+ else\r
+ {\r
+ xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_100;\r
+ }\r
+\r
+ xPhyObject.xPhyPreferences.ucMDI_X = PHY_MDIX_AUTO;\r
+\r
+ /* Use predefined (fixed) configuration. */\r
+ xPhyFixedValue( &xPhyObject, xPhyGetMask( &xPhyObject ) );\r
}\r
\r
/* ETHERNET MAC Re-Configuration */\r
{\r
BaseType_t xReturn;\r
\r
- if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 )\r
+ if( xPhyObject.ulLinkStatusMask != 0 )\r
{\r
xReturn = pdPASS;\r
}\r
}\r
/*-----------------------------------------------------------*/\r
\r
+/* Uncomment this in case BufferAllocation_1.c is used. */\r
+\r
+/*\r
+#define niBUFFER_1_PACKET_SIZE 1536\r
+\r
+static __attribute__ ((section(".first_data"))) uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS * niBUFFER_1_PACKET_SIZE ] __attribute__ ( ( aligned( 32 ) ) );\r
+\r
+void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] )\r
+{\r
+\r
+uint8_t *ucRAMBuffer = ucNetworkPackets;\r
+uint32_t ul;\r
+\r
+ for( ul = 0; ul < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; ul++ )\r
+ {\r
+ pxNetworkBuffers[ ul ].pucEthernetBuffer = ucRAMBuffer + ipBUFFER_PADDING;\r
+ *( ( unsigned * ) ucRAMBuffer ) = ( unsigned ) ( &( pxNetworkBuffers[ ul ] ) );\r
+ ucRAMBuffer += niBUFFER_1_PACKET_SIZE;\r
+ }\r
+}\r
+*/\r
+/*-----------------------------------------------------------*/\r
+\r
static void prvEMACHandlerTask( void *pvParameters )\r
{\r
-TimeOut_t xPhyTime;\r
-TickType_t xPhyRemTime;\r
UBaseType_t uxLastMinBufferCount = 0;\r
#if( ipconfigCHECK_IP_QUEUE_SPACE != 0 )\r
UBaseType_t uxLastMinQueueSpace = 0;\r
#endif\r
UBaseType_t uxCurrentCount;\r
-BaseType_t xResult = 0;\r
-uint32_t xStatus;\r
+BaseType_t xResult;\r
const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL );\r
\r
/* Remove compiler warnings about unused parameters. */\r
( void ) pvParameters;\r
\r
- vTaskSetTimeOutState( &xPhyTime );\r
- xPhyRemTime = pdMS_TO_TICKS( PHY_LS_LOW_CHECK_TIME_MS );\r
-\r
for( ;; )\r
{\r
+ xResult = 0;\r
uxCurrentCount = uxGetMinimumFreeNetworkBuffers();\r
if( uxLastMinBufferCount != uxCurrentCount )\r
{\r
uxGetNumberOfFreeNetworkBuffers(), uxCurrentCount ) );\r
}\r
\r
- #if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
if( xTXDescriptorSemaphore != NULL )\r
{\r
static UBaseType_t uxLowestSemCount = ( UBaseType_t ) ETH_TXBUFNB - 1;\r
}\r
\r
}\r
- #endif\r
+\r
#if( ipconfigCHECK_IP_QUEUE_SPACE != 0 )\r
{\r
uxCurrentCount = uxGetMinimumIPQueueSpace();\r
{\r
/* Code to release TX buffers if zero-copy is used. */\r
ulISREvents &= ~EMAC_IF_TX_EVENT;\r
- #if( ipconfigZERO_COPY_TX_DRIVER != 0 )\r
- {\r
- /* Check if DMA packets have been delivered. */\r
- vClearTXBuffers();\r
- }\r
- #endif\r
+ /* Check if DMA packets have been delivered. */\r
+ vClearTXBuffers();\r
}\r
\r
if( ( ulISREvents & EMAC_IF_ERR_EVENT ) != 0 )\r
/* Future extension: logging about errors that occurred. */\r
ulISREvents &= ~EMAC_IF_ERR_EVENT;\r
}\r
-\r
- if( xResult > 0 )\r
+ if( xPhyCheckLinkStatus( &xPhyObject, xResult ) != 0 )\r
{\r
- /* A packet was received. No need to check for the PHY status now,\r
- but set a timer to check it later on. */\r
- vTaskSetTimeOutState( &xPhyTime );\r
- xPhyRemTime = pdMS_TO_TICKS( PHY_LS_HIGH_CHECK_TIME_MS );\r
- xResult = 0;\r
- }\r
- else if( xTaskCheckForTimeOut( &xPhyTime, &xPhyRemTime ) != pdFALSE )\r
- {\r
- HAL_ETH_ReadPHYRegister( &xETH, PHY_REG_01_BMSR, &xStatus );\r
- if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != ( xStatus & BMSR_LINK_STATUS ) )\r
- {\r
- ulPHYLinkStatus = xStatus;\r
- FreeRTOS_printf( ( "prvEMACHandlerTask: PHY LS now %d\n", ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 ) );\r
- prvEthernetUpdateConfig( pdFALSE );\r
- }\r
-\r
- vTaskSetTimeOutState( &xPhyTime );\r
- if( ( ulPHYLinkStatus & BMSR_LINK_STATUS ) != 0 )\r
- {\r
- xPhyRemTime = pdMS_TO_TICKS( PHY_LS_HIGH_CHECK_TIME_MS );\r
- }\r
- else\r
- {\r
- xPhyRemTime = pdMS_TO_TICKS( PHY_LS_LOW_CHECK_TIME_MS );\r
- }\r
+ /* Something has changed to a Link Status, need re-check. */\r
+ prvEthernetUpdateConfig( pdFALSE );\r
}\r
}\r
}\r
{\r
HAL_ETH_IRQHandler( &xETH );\r
}\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_hal_eth.c\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 26-June-2015\r
+ * @brief ETH HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Ethernet (ETH) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral Control functions\r
+ * + Peripheral State and Errors functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#)Declare a ETH_HandleTypeDef handle structure, for example:\r
+ ETH_HandleTypeDef heth;\r
+\r
+ (#)Fill parameters of Init structure in heth handle\r
+\r
+ (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)\r
+\r
+ (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:\r
+ (##) Enable the Ethernet interface clock using\r
+ (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();\r
+ (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();\r
+ (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();\r
+\r
+ (##) Initialize the related GPIO clocks\r
+ (##) Configure Ethernet pin-out\r
+ (##) Configure Ethernet NVIC interrupt (IT mode)\r
+\r
+ (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:\r
+ (##) HAL_ETH_DMATxDescListInit(); for Transmission process\r
+ (##) HAL_ETH_DMARxDescListInit(); for Reception process\r
+\r
+ (#)Enable MAC and DMA transmission and reception:\r
+ (##) HAL_ETH_Start();\r
+\r
+ (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer\r
+ the frame to MAC TX FIFO:\r
+ (##) HAL_ETH_TransmitFrame();\r
+\r
+ (#)Poll for a received frame in ETH RX DMA Descriptors and get received\r
+ frame parameters\r
+ (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)\r
+\r
+ (#) Get a received frame when an ETH RX interrupt occurs:\r
+ (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)\r
+\r
+ (#) Communicate with external PHY device:\r
+ (##) Read a specific register from the PHY\r
+ HAL_ETH_ReadPHYRegister();\r
+ (##) Write data to a specific RHY register:\r
+ HAL_ETH_WritePHYRegister();\r
+\r
+ (#) Configure the Ethernet MAC after ETH peripheral initialization\r
+ HAL_ETH_ConfigMAC(); all MAC parameters should be filled.\r
+\r
+ (#) Configure the Ethernet DMA after ETH peripheral initialization\r
+ HAL_ETH_ConfigDMA(); all DMA parameters should be filled.\r
+\r
+ -@- The PTP protocol and the DMA descriptors ring mode are not supported\r
+ in this driver\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx_hal.h"\r
+\r
+int lUDPLoggingPrintf( const char *pcFormatString, ... );\r
+\r
+/** @addtogroup STM32F4xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH ETH\r
+ * @brief ETH HAL module driver\r
+ * @{\r
+ */\r
+\r
+#if !defined( ARRAY_SIZE )\r
+ #define ARRAY_SIZE( x ) ( sizeof ( x ) / sizeof ( x )[ 0 ] )\r
+#endif\r
+\r
+#ifdef HAL_ETH_MODULE_ENABLED\r
+\r
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup ETH_Private_Constants ETH Private Constants\r
+ * @{\r
+ */\r
+#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */\r
+#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @defgroup ETH_Private_Functions ETH Private Functions\r
+ * @{\r
+ */\r
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);\r
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);\r
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);\r
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);\r
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup ETH_Exported_Functions ETH Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the Ethernet peripheral\r
+ (+) De-initialize the Ethernet peripheral\r
+\r
+ @endverbatim\r
+ * @{\r
+ */\r
+extern void vMACBProbePhy ( void );\r
+\r
+/**\r
+ * @brief Initializes the Ethernet MAC and DMA according to default\r
+ * parameters.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ uint32_t hclk = 60000000;\r
+ uint32_t err = ETH_SUCCESS;\r
+\r
+ /* Check the ETH peripheral state */\r
+ if( heth == NULL )\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));\r
+ assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));\r
+ assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));\r
+ assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));\r
+\r
+ if( heth->State == HAL_ETH_STATE_RESET )\r
+ {\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC. */\r
+ HAL_ETH_MspInit( heth );\r
+ }\r
+\r
+ /* Enable SYSCFG Clock */\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+\r
+ /* Select MII or RMII Mode*/\r
+ SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);\r
+ SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;\r
+\r
+ /* Ethernet Software reset */\r
+ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */\r
+ /* After reset all the registers holds their respective reset values */\r
+ /* Also enable EDFE: Enhanced descriptor format enable. */\r
+ heth->Instance->DMABMR |= ETH_DMABMR_SR | ETH_DMABMR_EDE;\r
+\r
+ /* Wait for software reset */\r
+ while ((heth->Instance->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)\r
+ {\r
+ }\r
+\r
+ /*-------------------------------- MAC Initialization ----------------------*/\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+ /* Clear CSR Clock Range CR[2:0] bits */\r
+ tmpreg &= ETH_MACMIIAR_CR_MASK;\r
+\r
+ /* Get hclk frequency value (168,000,000) */\r
+ hclk = HAL_RCC_GetHCLKFreq();\r
+\r
+ /* Set CR bits depending on hclk value */\r
+ if( ( hclk >= 20000000 ) && ( hclk < 35000000 ) )\r
+ {\r
+ /* CSR Clock Range between 20-35 MHz */\r
+ tmpreg |= (uint32_t) ETH_MACMIIAR_CR_Div16;\r
+ }\r
+ else if( ( hclk >= 35000000 ) && ( hclk < 60000000 ) )\r
+ {\r
+ /* CSR Clock Range between 35-60 MHz */\r
+ tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div26;\r
+ }\r
+ else if((hclk >= 60000000 ) && ( hclk < 100000000 ) )\r
+ {\r
+ /* CSR Clock Range between 60-100 MHz */\r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;\r
+ }\r
+ else if((hclk >= 100000000 ) && ( hclk < 150000000))\r
+ {\r
+ /* CSR Clock Range between 100-150 MHz */\r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;\r
+ }\r
+ else /* ((hclk >= 150000000 ) && ( hclk <= 168000000)) */\r
+ {\r
+ /* CSR Clock Range between 150-168 MHz */\r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;\r
+ }\r
+\r
+ /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */\r
+ heth->Instance->MACMIIAR = (uint32_t)tmpreg;\r
+\r
+ /* Initialise the MACB and set all PHY properties */\r
+ vMACBProbePhy();\r
+\r
+ /* Config MAC and DMA */\r
+ ETH_MACDMAConfig(heth, err);\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief De-Initializes the ETH peripheral.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */\r
+ HAL_ETH_MspDeInit( heth );\r
+\r
+ /* Set ETH HAL state to Disabled */\r
+ heth->State= HAL_ETH_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Tx descriptors in chain mode.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param DMATxDescTab: Pointer to the first Tx desc list\r
+ * @param TxBuff: Pointer to the first TxBuffer list\r
+ * @param TxBuffCount: Number of the used Tx desc in the list\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADescTypeDef *pxDMADescriptor;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Set the TxDesc pointer with the first one of the pxDMATable list */\r
+ heth->TxDesc = pxDMATable;\r
+\r
+ /* Fill each DMA descriptor with the right values */\r
+ for( i=0; i < ulBufferCount; i++ )\r
+ {\r
+ /* Get the pointer on the ith member of the descriptor list */\r
+ pxDMADescriptor = pxDMATable + i;\r
+\r
+ /* Set Second Address Chained bit */\r
+ pxDMADescriptor->Status = ETH_DMATXDESC_TCH;\r
+\r
+ pxDMADescriptor->ControlBufferSize = 0;\r
+\r
+ /* Set Buffer1 address pointer */\r
+ if( ucDataBuffer != NULL )\r
+ {\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_TX_BUF_SIZE ] );\r
+ }\r
+ else\r
+ {\r
+ /* Buffer space is not provided because it uses zero-copy transmissions. */\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )0u;\r
+ }\r
+\r
+ if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)\r
+ {\r
+ /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */\r
+ pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;\r
+ }\r
+\r
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
+ if(i < ( ulBufferCount - 1 ) )\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMATable + i + 1 );\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable;\r
+ }\r
+ }\r
+\r
+ /* Set Transmit Descriptor List Address Register */\r
+ heth->Instance->DMATDLAR = ( uint32_t ) pxDMATable;\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Rx descriptors in chain mode.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param DMARxDescTab: Pointer to the first Rx desc list\r
+ * @param RxBuff: Pointer to the first RxBuffer list\r
+ * @param RxBuffCount: Number of the used Rx desc in the list\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADescTypeDef *pxDMADescriptor;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Set the RxDesc pointer with the first one of the pxDMATable list */\r
+ heth->RxDesc = pxDMATable;\r
+\r
+ /* Fill each DMA descriptor with the right values */\r
+ for(i=0; i < ulBufferCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the descriptor list */\r
+ pxDMADescriptor = pxDMATable+i;\r
+\r
+ /* Set Own bit of the Rx descriptor Status */\r
+ pxDMADescriptor->Status = ETH_DMARXDESC_OWN;\r
+\r
+ /* Set Buffer1 size and Second Address Chained bit */\r
+ pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;\r
+\r
+ /* Set Buffer1 address pointer */\r
+ if( ucDataBuffer != NULL )\r
+ {\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_RX_BUF_SIZE ] );\r
+ }\r
+ else\r
+ {\r
+ /* Buffer space is not provided because it uses zero-copy reception. */\r
+ pxDMADescriptor->Buffer1Addr = ( uint32_t )0u;\r
+ }\r
+\r
+ if( heth->Init.RxMode == ETH_RXINTERRUPT_MODE )\r
+ {\r
+ /* Enable Ethernet DMA Rx Descriptor interrupt */\r
+ pxDMADescriptor->ControlBufferSize &= ~ETH_DMARXDESC_DIC;\r
+ }\r
+\r
+ /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r
+ if(i < (ulBufferCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = (uint32_t)(pxDMATable+i+1);\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */\r
+ pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable;\r
+ }\r
+ }\r
+\r
+ /* Set Receive Descriptor List Address Register */\r
+ heth->Instance->DMARDLAR = ( uint32_t ) pxDMATable;\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ETH MSP.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes ETH MSP.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group2 IO operation functions\r
+ * @brief Data transfers functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### IO operation functions #####\r
+ ==============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Transmit a frame\r
+ HAL_ETH_TransmitFrame();\r
+ (+) Receive a frame\r
+ HAL_ETH_GetReceivedFrame();\r
+ HAL_ETH_GetReceivedFrame_IT();\r
+ (+) Read from an External PHY register\r
+ HAL_ETH_ReadPHYRegister();\r
+ (+) Write to an External PHY register\r
+ HAL_ETH_WritePHYRegister();\r
+\r
+ @endverbatim\r
+\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sends an Ethernet frame.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param FrameLength: Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)\r
+{\r
+ uint32_t bufcount = 0, size = 0, i = 0;\r
+ __IO ETH_DMADescTypeDef *pxDmaTxDesc = heth->TxDesc;\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ if( FrameLength == 0 )\r
+ {\r
+ /* Set ETH HAL state to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */\r
+ if( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) != ( uint32_t ) RESET )\r
+ {\r
+ /* OWN bit set */\r
+ heth->State = HAL_ETH_STATE_BUSY_TX;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Get the number of needed Tx buffers for the current frame, rounding up. */\r
+ bufcount = ( FrameLength + ETH_TX_BUF_SIZE - 1 ) / ETH_TX_BUF_SIZE;\r
+\r
+ if (bufcount == 1)\r
+ {\r
+ /* Set LAST and FIRST segment */\r
+ pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;\r
+ /* Set frame size */\r
+ pxDmaTxDesc->ControlBufferSize = ( FrameLength & ETH_DMATXDESC_TBS1 );\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN;\r
+ /* Point to next descriptor */\r
+ heth->TxDesc = ( ETH_DMADescTypeDef * ) ( heth->TxDesc->Buffer2NextDescAddr );\r
+ }\r
+ else\r
+ {\r
+ for( i = 0; i < bufcount; i++ )\r
+ {\r
+ /* Clear FIRST and LAST segment bits */\r
+ uint32_t ulStatus = heth->TxDesc->Status & ~( ETH_DMATXDESC_FS | ETH_DMATXDESC_LS );\r
+\r
+ if( i == 0 )\r
+ {\r
+ /* Setting the first segment bit */\r
+ heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_FS;\r
+ }\r
+\r
+ /* Program size */\r
+ if (i < (bufcount-1))\r
+ {\r
+ heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);\r
+ }\r
+ else\r
+ {\r
+ /* Setting the last segment bit */\r
+ heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_LS;\r
+ size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;\r
+ heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);\r
+ }\r
+\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ heth->TxDesc->Status |= ETH_DMATXDESC_OWN;\r
+ /* point to next descriptor */\r
+ heth->TxDesc = (ETH_DMADescTypeDef *)( heth->TxDesc->Buffer2NextDescAddr );\r
+ }\r
+ }\r
+\r
+ __DSB();\r
+\r
+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */\r
+ if( ( heth->Instance->DMASR & ETH_DMASR_TBUS ) != ( uint32_t )RESET )\r
+ {\r
+ heth->Instance->DMACHTDR = ( uint32_t )pxDmaTxDesc;\r
+\r
+ /* Clear TBUS ETHERNET DMA flag */\r
+ heth->Instance->DMASR = ETH_DMASR_TBUS;\r
+ /* Resume DMA transmission*/\r
+ heth->Instance->DMATPDR = 0;\r
+ }\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Checks for received frames.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT( ETH_HandleTypeDef *heth )\r
+{\r
+ return HAL_ETH_GetReceivedFrame( heth );\r
+}\r
+\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame( ETH_HandleTypeDef *heth )\r
+{\r
+uint32_t ulCounter = 0;\r
+ETH_DMADescTypeDef *pxDescriptor = heth->RxDesc;\r
+HAL_StatusTypeDef xResult = HAL_ERROR;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Check the ETH state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Scan descriptors owned by CPU */\r
+ while( ( ( pxDescriptor->Status & ETH_DMARXDESC_OWN ) == 0ul ) && ( ulCounter < ETH_RXBUFNB ) )\r
+ {\r
+ uint32_t ulStatus = pxDescriptor->Status;\r
+\r
+ /* Just for security. */\r
+ ulCounter++;\r
+\r
+ if( ( ulStatus & ( ETH_DMARXDESC_FS | ETH_DMARXDESC_LS ) ) == ( uint32_t )ETH_DMARXDESC_FS )\r
+ {\r
+ /* First segment in frame, but not the last. */\r
+ heth->RxFrameInfos.FSRxDesc = pxDescriptor;\r
+ heth->RxFrameInfos.LSRxDesc = ( ETH_DMADescTypeDef *)NULL;\r
+ heth->RxFrameInfos.SegCount = 1;\r
+ /* Point to next descriptor. */\r
+ pxDescriptor = (ETH_DMADescTypeDef*) (pxDescriptor->Buffer2NextDescAddr);\r
+ heth->RxDesc = pxDescriptor;\r
+ }\r
+ else if( ( ulStatus & ( ETH_DMARXDESC_LS | ETH_DMARXDESC_FS ) ) == 0ul )\r
+ {\r
+ /* This is an intermediate segment, not first, not last. */\r
+ /* Increment segment count. */\r
+ heth->RxFrameInfos.SegCount++;\r
+ /* Move to the next descriptor. */\r
+ pxDescriptor = ( ETH_DMADescTypeDef * ) ( pxDescriptor->Buffer2NextDescAddr );\r
+ heth->RxDesc = pxDescriptor;\r
+ }\r
+ /* Must be a last segment */\r
+ else\r
+ {\r
+ /* This is the last segment. */\r
+ /* Check if last segment is first segment: one segment contains the frame */\r
+ if( heth->RxFrameInfos.SegCount == 0 )\r
+ {\r
+ /* Remember the first segment. */\r
+ heth->RxFrameInfos.FSRxDesc = pxDescriptor;\r
+ }\r
+\r
+ /* Increment segment count */\r
+ heth->RxFrameInfos.SegCount++;\r
+\r
+ /* Remember the last segment. */\r
+ heth->RxFrameInfos.LSRxDesc = pxDescriptor;\r
+\r
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r
+ heth->RxFrameInfos.length =\r
+ ( ( ulStatus & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4;\r
+\r
+ /* Get the address of the buffer start address */\r
+ heth->RxFrameInfos.buffer = heth->RxFrameInfos.FSRxDesc->Buffer1Addr;\r
+\r
+ /* Point to next descriptor */\r
+ heth->RxDesc = ( ETH_DMADescTypeDef * ) pxDescriptor->Buffer2NextDescAddr;\r
+\r
+ /* Return OK status: a packet was received. */\r
+ xResult = HAL_OK;\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Set ETH HAL State to Ready */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return xResult;\r
+}\r
+\r
+#if( STM32_ETHERNET_STATS != 0 )\r
+\r
+ volatile int rx_count, tx_count, int_count;\r
+ /**\r
+ * @brief This function handles ETH interrupt request.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+ volatile int int_counts[32];\r
+ volatile int tx_status[8];\r
+ volatile unsigned sr_history[32];\r
+ volatile int sr_head;\r
+ #define STM32_STAT_INC( x ) do { ( x )++; } while( 0 )\r
+\r
+#else\r
+ #define STM32_STAT_INC( x ) do { } while( 0 )\r
+#endif /* STM32_ETHERNET_STATS */\r
+\r
+#define ETH_DMA_ALL_INTS \\r
+ ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_AIS | ETH_DMA_IT_ER | \\r
+ ETH_DMA_IT_FBE | ETH_DMA_IT_ET | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \\r
+ ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T )\r
+\r
+//#define ETH_DMA_ALL_INTS ETH_DMA_IT_RBU | ETH_DMA_FLAG_T | ETH_DMA_FLAG_AIS\r
+\r
+#define INT_MASK ( ( uint32_t ) ~ ( ETH_DMA_IT_TBU ) )\r
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t dmasr;\r
+\r
+ STM32_STAT_INC( int_count );\r
+\r
+ dmasr = heth->Instance->DMASR & ETH_DMA_ALL_INTS;\r
+ heth->Instance->DMASR = dmasr;\r
+\r
+#if( STM32_ETHERNET_STATS != 0 )\r
+ if( sr_head < ARRAY_SIZE( sr_history ) )\r
+ {\r
+ sr_history[ sr_head++ ] = dmasr;\r
+ }\r
+\r
+ {\r
+ int i;\r
+ for (i = 0; i < 32; i++) {\r
+ if (dmasr & (1u << i)) {\r
+ int_counts[i]++;\r
+ }\r
+ }\r
+ tx_status[ ( dmasr >> 20 ) & 0x07 ]++;\r
+ }\r
+#endif\r
+\r
+ /* Frame received */\r
+ if( ( dmasr & ( ETH_DMA_FLAG_R | ETH_DMA_IT_RBU ) ) != 0 )\r
+ {\r
+ /* Receive complete callback */\r
+ HAL_ETH_RxCpltCallback( heth );\r
+ STM32_STAT_INC( rx_count );\r
+ }\r
+ /* Frame transmitted */\r
+ if( ( dmasr & ( ETH_DMA_FLAG_T ) ) != 0 )\r
+ {\r
+ /* Transfer complete callback */\r
+ HAL_ETH_TxCpltCallback( heth );\r
+ STM32_STAT_INC( tx_count );\r
+ }\r
+\r
+ /* ETH DMA Error */\r
+ if( ( dmasr & ( ETH_DMA_FLAG_AIS ) ) != 0 )\r
+ {\r
+ /* Ethernet Error callback */\r
+ HAL_ETH_ErrorCallback( heth );\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Tx Transfer completed callbacks.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Rx Transfer completed callbacks.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Ethernet transfer error callbacks\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_ETH_TxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Reads a PHY register\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.\r
+ * This parameter can be one of the following values:\r
+ * PHY_BCR: Transceiver Basic Control Register,\r
+ * PHY_BSR: Transceiver Basic Status Register.\r
+ * More PHY register could be read depending on the used PHY\r
+ * @param RegValue: PHY register value\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)\r
+{\r
+uint32_t tmpreg = 0;\r
+uint32_t tickstart = 0;\r
+HAL_StatusTypeDef xResult;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));\r
+\r
+ /* Check the ETH peripheral state */\r
+ if( heth->State == HAL_ETH_STATE_BUSY_RD )\r
+ {\r
+ xResult = HAL_BUSY;\r
+ }\r
+ else\r
+ {\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set ETH HAL State to BUSY_RD */\r
+ heth->State = HAL_ETH_STATE_BUSY_RD;\r
+\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~ETH_MACMIIAR_CR_MASK;\r
+\r
+ /* Prepare the MII address register value */\r
+ tmpreg |= ( ( ( uint32_t )heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA ); /* Set the PHY device address */\r
+ tmpreg |= ( ( ( uint32_t )PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */\r
+ tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+\r
+ /* Write the result value into the MII Address register */\r
+ heth->Instance->MACMIIAR = tmpreg;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check for the Busy flag */\r
+ while( 1 )\r
+ {\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul )\r
+ {\r
+ /* Get MACMIIDR value */\r
+ *RegValue = ( uint32_t ) heth->Instance->MACMIIDR;\r
+ xResult = HAL_OK;\r
+ break;\r
+ }\r
+ /* Check for the Timeout */\r
+ if( ( HAL_GetTick( ) - tickstart ) > PHY_READ_TO )\r
+ {\r
+ xResult = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+\r
+ }\r
+\r
+ /* Set ETH HAL State to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+ }\r
+\r
+ if( xResult != HAL_OK )\r
+ {\r
+ lUDPLoggingPrintf( "ReadPHY: %d\n", xResult );\r
+ }\r
+ /* Return function status */\r
+ return xResult;\r
+}\r
+\r
+/**\r
+ * @brief Writes to a PHY register.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.\r
+ * This parameter can be one of the following values:\r
+ * PHY_BCR: Transceiver Control Register.\r
+ * More PHY register could be written depending on the used PHY\r
+ * @param RegValue: the value to write\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)\r
+{\r
+uint32_t tmpreg = 0;\r
+uint32_t tickstart = 0;\r
+HAL_StatusTypeDef xResult;\r
+\r
+ /* Check parameters */\r
+ assert_param( IS_ETH_PHY_ADDRESS( heth->Init.PhyAddress ) );\r
+\r
+ /* Check the ETH peripheral state */\r
+ if( heth->State == HAL_ETH_STATE_BUSY_WR )\r
+ {\r
+ xResult = HAL_BUSY;\r
+ }\r
+ else\r
+ {\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set ETH HAL State to BUSY_WR */\r
+ heth->State = HAL_ETH_STATE_BUSY_WR;\r
+\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~ETH_MACMIIAR_CR_MASK;\r
+\r
+ /* Prepare the MII register address value */\r
+ tmpreg |= ( ( ( uint32_t ) heth->Init.PhyAddress << 11 ) & ETH_MACMIIAR_PA ); /* Set the PHY device address */\r
+ tmpreg |= ( ( ( uint32_t ) PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */\r
+ tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+\r
+ /* Give the value to the MII data register */\r
+ heth->Instance->MACMIIDR = ( uint16_t ) RegValue;\r
+\r
+ /* Write the result value into the MII Address register */\r
+ heth->Instance->MACMIIAR = tmpreg;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Check for the Busy flag */\r
+ while( 1 )\r
+ {\r
+ tmpreg = heth->Instance->MACMIIAR;\r
+\r
+ if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul )\r
+ {\r
+ xResult = HAL_OK;\r
+ break;\r
+ }\r
+ /* Check for the Timeout */\r
+ if( ( HAL_GetTick( ) - tickstart ) > PHY_WRITE_TO )\r
+ {\r
+ xResult = HAL_TIMEOUT;\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Set ETH HAL State to READY */\r
+ heth->State = HAL_ETH_STATE_READY;\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+ }\r
+\r
+ if( xResult != HAL_OK )\r
+ {\r
+ lUDPLoggingPrintf( "WritePHY: %d\n", xResult );\r
+ }\r
+ /* Return function status */\r
+ return xResult;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions\r
+ * @brief Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Enable MAC and DMA transmission and reception.\r
+ HAL_ETH_Start();\r
+ (+) Disable MAC and DMA transmission and reception.\r
+ HAL_ETH_Stop();\r
+ (+) Set the MAC configuration in runtime mode\r
+ HAL_ETH_ConfigMAC();\r
+ (+) Set the DMA configuration in runtime mode\r
+ HAL_ETH_ConfigDMA();\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Enables Ethernet MAC and DMA reception/transmission\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef *heth )\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Enable transmit state machine of the MAC for transmission on the MII */\r
+ ETH_MACTransmissionEnable( heth );\r
+\r
+ /* Enable receive state machine of the MAC for reception from the MII */\r
+ ETH_MACReceptionEnable( heth );\r
+\r
+ /* Flush Transmit FIFO */\r
+ ETH_FlushTransmitFIFO( heth );\r
+\r
+ /* Start DMA transmission */\r
+ ETH_DMATransmissionEnable( heth );\r
+\r
+ /* Start DMA reception */\r
+ ETH_DMAReceptionEnable( heth );\r
+\r
+ /* Set the ETH state to READY*/\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop Ethernet MAC and DMA reception/transmission\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State = HAL_ETH_STATE_BUSY;\r
+\r
+ /* Stop DMA transmission */\r
+ ETH_DMATransmissionDisable( heth );\r
+\r
+ /* Stop DMA reception */\r
+ ETH_DMAReceptionDisable( heth );\r
+\r
+ /* Disable receive state machine of the MAC for reception from the MII */\r
+ ETH_MACReceptionDisable( heth );\r
+\r
+ /* Flush Transmit FIFO */\r
+ ETH_FlushTransmitFIFO( heth );\r
+\r
+ /* Disable transmit state machine of the MAC for transmission on the MII */\r
+ ETH_MACTransmissionDisable( heth );\r
+\r
+ /* Set the ETH state*/\r
+ heth->State = HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+static void prvWriteMACFCR( ETH_HandleTypeDef *heth, uint32_t ulValue)\r
+{\r
+ /* Enable the MAC transmission */\r
+ heth->Instance->MACFCR = ulValue;\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles.\r
+ Read it back, wait a ms and */\r
+ ( void ) heth->Instance->MACFCR;\r
+\r
+ HAL_Delay( ETH_REG_WRITE_DELAY );\r
+\r
+ heth->Instance->MACFCR = ulValue;\r
+}\r
+\r
+static void prvWriteDMAOMR( ETH_HandleTypeDef *heth, uint32_t ulValue)\r
+{\r
+ /* Enable the MAC transmission */\r
+ heth->Instance->DMAOMR = ulValue;\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles.\r
+ Read it back, wait a ms and */\r
+ ( void ) heth->Instance->DMAOMR;\r
+\r
+ HAL_Delay( ETH_REG_WRITE_DELAY );\r
+\r
+ heth->Instance->DMAOMR = ulValue;\r
+}\r
+\r
+static void prvWriteMACCR( ETH_HandleTypeDef *heth, uint32_t ulValue)\r
+{\r
+ /* Enable the MAC transmission */\r
+ heth->Instance->MACCR = ulValue;\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles.\r
+ Read it back, wait a ms and */\r
+ ( void ) heth->Instance->MACCR;\r
+\r
+ HAL_Delay( ETH_REG_WRITE_DELAY );\r
+\r
+ heth->Instance->MACCR = ulValue;\r
+}\r
+\r
+/**\r
+ * @brief Set ETH MAC Configuration.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param macconf: MAC Configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State= HAL_ETH_STATE_BUSY;\r
+\r
+ assert_param(IS_ETH_SPEED(heth->Init.Speed));\r
+ assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));\r
+\r
+ if (macconf != NULL)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));\r
+ assert_param(IS_ETH_JABBER(macconf->Jabber));\r
+ assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));\r
+ assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));\r
+ assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));\r
+ assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));\r
+ assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));\r
+ assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));\r
+ assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));\r
+ assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));\r
+ assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));\r
+ assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));\r
+ assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));\r
+ assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));\r
+ assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));\r
+ assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));\r
+ assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));\r
+ assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));\r
+ assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));\r
+ assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));\r
+ assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));\r
+ assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));\r
+ assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));\r
+ assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));\r
+ assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));\r
+ assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));\r
+ assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));\r
+\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = heth->Instance->MACCR;\r
+ /* Clear WD, PCE, PS, TE and RE bits */\r
+ tmpreg &= ETH_MACCR_CLEAR_MASK;\r
+\r
+ tmpreg |= (uint32_t)(\r
+ macconf->Watchdog |\r
+ macconf->Jabber |\r
+ macconf->InterFrameGap |\r
+ macconf->CarrierSense |\r
+ heth->Init.Speed |\r
+ macconf->ReceiveOwn |\r
+ macconf->LoopbackMode |\r
+ heth->Init.DuplexMode |\r
+ macconf->ChecksumOffload |\r
+ macconf->RetryTransmission |\r
+ macconf->AutomaticPadCRCStrip |\r
+ macconf->BackOffLimit |\r
+ macconf->DeferralCheck);\r
+\r
+ /* Write to ETHERNET MACCR */\r
+ prvWriteMACCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/\r
+ /* Write to ETHERNET MACFFR */\r
+ heth->Instance->MACFFR = (uint32_t)(\r
+ macconf->ReceiveAll |\r
+ macconf->SourceAddrFilter |\r
+ macconf->PassControlFrames |\r
+ macconf->BroadcastFramesReception |\r
+ macconf->DestinationAddrFilter |\r
+ macconf->PromiscuousMode |\r
+ macconf->MulticastFramesFilter |\r
+ macconf->UnicastFramesFilter);\r
+\r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACFFR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACFFR = tmpreg;\r
+\r
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/\r
+ /* Write to ETHERNET MACHTHR */\r
+ heth->Instance->MACHTHR = (uint32_t)macconf->HashTableHigh;\r
+\r
+ /* Write to ETHERNET MACHTLR */\r
+ heth->Instance->MACHTLR = (uint32_t)macconf->HashTableLow;\r
+ /*----------------------- ETHERNET MACFCR Configuration --------------------*/\r
+\r
+ /* Get the ETHERNET MACFCR value */\r
+ tmpreg = heth->Instance->MACFCR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_MACFCR_CLEAR_MASK;\r
+\r
+ tmpreg |= (uint32_t)((\r
+ macconf->PauseTime << 16) |\r
+ macconf->ZeroQuantaPause |\r
+ macconf->PauseLowThreshold |\r
+ macconf->UnicastPauseFrameDetect |\r
+ macconf->ReceiveFlowControl |\r
+ macconf->TransmitFlowControl);\r
+\r
+ /* Write to ETHERNET MACFCR */\r
+ prvWriteMACFCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/\r
+ heth->Instance->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |\r
+ macconf->VLANTagIdentifier);\r
+\r
+ /* Wait until the write operation will be taken into account :\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACVLANTR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACVLANTR = tmpreg;\r
+ }\r
+ else /* macconf == NULL : here we just configure Speed and Duplex mode */\r
+ {\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = heth->Instance->MACCR;\r
+\r
+ /* Clear FES and DM bits */\r
+ tmpreg &= ~((uint32_t)0x00004800);\r
+\r
+ tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);\r
+\r
+ /* Write to ETHERNET MACCR */\r
+ prvWriteMACCR( heth, tmpreg );\r
+ }\r
+\r
+ /* Set the ETH state to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Sets ETH DMA Configuration.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param dmaconf: DMA Configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK( heth );\r
+\r
+ /* Set the ETH peripheral state to BUSY */\r
+ heth->State= HAL_ETH_STATE_BUSY;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));\r
+ assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));\r
+ assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));\r
+ assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));\r
+ assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));\r
+ assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));\r
+ assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));\r
+ assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));\r
+ assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));\r
+ assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));\r
+ assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));\r
+ assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));\r
+ assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));\r
+ assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));\r
+ assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));\r
+ assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));\r
+\r
+ /*----------------------- ETHERNET DMAOMR Configuration --------------------*/\r
+ /* Get the ETHERNET DMAOMR value */\r
+ tmpreg = heth->Instance->DMAOMR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_DMAOMR_CLEAR_MASK;\r
+\r
+ tmpreg |= (uint32_t)(\r
+ dmaconf->DropTCPIPChecksumErrorFrame |\r
+ dmaconf->ReceiveStoreForward |\r
+ dmaconf->FlushReceivedFrame |\r
+ dmaconf->TransmitStoreForward |\r
+ dmaconf->TransmitThresholdControl |\r
+ dmaconf->ForwardErrorFrames |\r
+ dmaconf->ForwardUndersizedGoodFrames |\r
+ dmaconf->ReceiveThresholdControl |\r
+ dmaconf->SecondFrameOperate);\r
+\r
+ /* Write to ETHERNET DMAOMR */\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET DMABMR Configuration --------------------*/\r
+ heth->Instance->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |\r
+ dmaconf->FixedBurst |\r
+ dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r
+ dmaconf->TxDMABurstLength |\r
+ dmaconf->EnhancedDescriptorFormat |\r
+ (dmaconf->DescriptorSkipLength << 2) |\r
+ dmaconf->DMAArbitration |\r
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->DMABMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->DMABMR = tmpreg;\r
+\r
+ /* Set the ETH state to Ready */\r
+ heth->State= HAL_ETH_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK( heth );\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions\r
+ * @brief Peripheral State functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### Peripheral State functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral\r
+ and the data flow.\r
+ (+) Get the ETH handle state:\r
+ HAL_ETH_GetState();\r
+\r
+\r
+ @endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the ETH HAL state\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval HAL state\r
+ */\r
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Return ETH state */\r
+ return heth->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ETH_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures Ethernet MAC and DMA with default parameters.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param err: Ethernet Init error\r
+ * @retval HAL status\r
+ */\r
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)\r
+{\r
+ ETH_MACInitTypeDef macinit;\r
+ ETH_DMAInitTypeDef dmainit;\r
+ uint32_t tmpreg = 0;\r
+\r
+ if (err != ETH_SUCCESS) /* Auto-negotiation failed */\r
+ {\r
+ /* Set Ethernet duplex mode to Full-duplex */\r
+ heth->Init.DuplexMode = ETH_MODE_FULLDUPLEX;\r
+\r
+ /* Set Ethernet speed to 100M */\r
+ heth->Init.Speed = ETH_SPEED_100M;\r
+ }\r
+\r
+ /* Ethernet MAC default initialization **************************************/\r
+ macinit.Watchdog = ETH_WATCHDOG_ENABLE;\r
+ macinit.Jabber = ETH_JABBER_ENABLE;\r
+ macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;\r
+ macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;\r
+ macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;\r
+ macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;\r
+ if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)\r
+ {\r
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;\r
+ }\r
+ else\r
+ {\r
+ macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;\r
+ }\r
+ macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;\r
+ macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;\r
+ macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;\r
+ macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;\r
+ macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;\r
+ macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;\r
+ macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;\r
+ macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;\r
+ macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;\r
+ macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;\r
+ macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;\r
+ macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;\r
+ macinit.HashTableHigh = 0x0;\r
+ macinit.HashTableLow = 0x0;\r
+ macinit.PauseTime = 0x0;\r
+ macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;\r
+ macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;\r
+ macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;\r
+ macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;\r
+ macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;\r
+ macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;\r
+ macinit.VLANTagIdentifier = 0x0;\r
+\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */\r
+ tmpreg = heth->Instance->MACCR;\r
+ /* Clear WD, PCE, PS, TE and RE bits */\r
+ tmpreg &= ETH_MACCR_CLEAR_MASK;\r
+ /* Set the WD bit according to ETH Watchdog value */\r
+ /* Set the JD: bit according to ETH Jabber value */\r
+ /* Set the IFG bit according to ETH InterFrameGap value */\r
+ /* Set the DCRS bit according to ETH CarrierSense value */\r
+ /* Set the FES bit according to ETH Speed value */\r
+ /* Set the DO bit according to ETH ReceiveOwn value */\r
+ /* Set the LM bit according to ETH LoopbackMode value */\r
+ /* Set the DM bit according to ETH Mode value */\r
+ /* Set the IPCO bit according to ETH ChecksumOffload value */\r
+ /* Set the DR bit according to ETH RetryTransmission value */\r
+ /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */\r
+ /* Set the BL bit according to ETH BackOffLimit value */\r
+ /* Set the DC bit according to ETH DeferralCheck value */\r
+ tmpreg |= (uint32_t)(macinit.Watchdog |\r
+ macinit.Jabber |\r
+ macinit.InterFrameGap |\r
+ macinit.CarrierSense |\r
+ heth->Init.Speed |\r
+ macinit.ReceiveOwn |\r
+ macinit.LoopbackMode |\r
+ heth->Init.DuplexMode |\r
+ macinit.ChecksumOffload |\r
+ macinit.RetryTransmission |\r
+ macinit.AutomaticPadCRCStrip |\r
+ macinit.BackOffLimit |\r
+ macinit.DeferralCheck);\r
+\r
+ /* Write to ETHERNET MACCR */\r
+ prvWriteMACCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/\r
+ /* Set the RA bit according to ETH ReceiveAll value */\r
+ /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */\r
+ /* Set the PCF bit according to ETH PassControlFrames value */\r
+ /* Set the DBF bit according to ETH BroadcastFramesReception value */\r
+ /* Set the DAIF bit according to ETH DestinationAddrFilter value */\r
+ /* Set the PR bit according to ETH PromiscuousMode value */\r
+ /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */\r
+ /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */\r
+ /* Write to ETHERNET MACFFR */\r
+ heth->Instance->MACFFR = (uint32_t)(macinit.ReceiveAll |\r
+ macinit.SourceAddrFilter |\r
+ macinit.PassControlFrames |\r
+ macinit.BroadcastFramesReception |\r
+ macinit.DestinationAddrFilter |\r
+ macinit.PromiscuousMode |\r
+ macinit.MulticastFramesFilter |\r
+ macinit.UnicastFramesFilter);\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACFFR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACFFR = tmpreg;\r
+\r
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/\r
+ /* Write to ETHERNET MACHTHR */\r
+ heth->Instance->MACHTHR = (uint32_t)macinit.HashTableHigh;\r
+\r
+ /* Write to ETHERNET MACHTLR */\r
+ heth->Instance->MACHTLR = (uint32_t)macinit.HashTableLow;\r
+ /*----------------------- ETHERNET MACFCR Configuration -------------------*/\r
+\r
+ /* Get the ETHERNET MACFCR value */\r
+ tmpreg = heth->Instance->MACFCR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_MACFCR_CLEAR_MASK;\r
+\r
+ /* Set the PT bit according to ETH PauseTime value */\r
+ /* Set the DZPQ bit according to ETH ZeroQuantaPause value */\r
+ /* Set the PLT bit according to ETH PauseLowThreshold value */\r
+ /* Set the UP bit according to ETH UnicastPauseFrameDetect value */\r
+ /* Set the RFE bit according to ETH ReceiveFlowControl value */\r
+ /* Set the TFE bit according to ETH TransmitFlowControl value */\r
+ tmpreg |= (uint32_t)((macinit.PauseTime << 16) |\r
+ macinit.ZeroQuantaPause |\r
+ macinit.PauseLowThreshold |\r
+ macinit.UnicastPauseFrameDetect |\r
+ macinit.ReceiveFlowControl |\r
+ macinit.TransmitFlowControl);\r
+\r
+ /* Write to ETHERNET MACFCR */\r
+ prvWriteMACFCR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/\r
+ /* Set the ETV bit according to ETH VLANTagComparison value */\r
+ /* Set the VL bit according to ETH VLANTagIdentifier value */\r
+ heth->Instance->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |\r
+ macinit.VLANTagIdentifier);\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->MACVLANTR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->MACVLANTR = tmpreg;\r
+\r
+ /* Ethernet DMA default initialization ************************************/\r
+ dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;\r
+ dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;\r
+ dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;\r
+ dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;\r
+ dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;\r
+ dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;\r
+ dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;\r
+ dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;\r
+ dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;\r
+ dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;\r
+ dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;\r
+ dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;\r
+ dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;\r
+ dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;\r
+ dmainit.DescriptorSkipLength = 0x0;\r
+ dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;\r
+\r
+ /* Get the ETHERNET DMAOMR value */\r
+ tmpreg = heth->Instance->DMAOMR;\r
+ /* Clear xx bits */\r
+ tmpreg &= ETH_DMAOMR_CLEAR_MASK;\r
+\r
+ /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */\r
+ /* Set the RSF bit according to ETH ReceiveStoreForward value */\r
+ /* Set the DFF bit according to ETH FlushReceivedFrame value */\r
+ /* Set the TSF bit according to ETH TransmitStoreForward value */\r
+ /* Set the TTC bit according to ETH TransmitThresholdControl value */\r
+ /* Set the FEF bit according to ETH ForwardErrorFrames value */\r
+ /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */\r
+ /* Set the RTC bit according to ETH ReceiveThresholdControl value */\r
+ /* Set the OSF bit according to ETH SecondFrameOperate value */\r
+ tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |\r
+ dmainit.ReceiveStoreForward |\r
+ dmainit.FlushReceivedFrame |\r
+ dmainit.TransmitStoreForward |\r
+ dmainit.TransmitThresholdControl |\r
+ dmainit.ForwardErrorFrames |\r
+ dmainit.ForwardUndersizedGoodFrames |\r
+ dmainit.ReceiveThresholdControl |\r
+ dmainit.SecondFrameOperate);\r
+\r
+ /* Write to ETHERNET DMAOMR */\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+\r
+ /*----------------------- ETHERNET DMABMR Configuration ------------------*/\r
+ /* Set the AAL bit according to ETH AddressAlignedBeats value */\r
+ /* Set the FB bit according to ETH FixedBurst value */\r
+ /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */\r
+ /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */\r
+ /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/\r
+ /* Set the DSL bit according to ETH DesciptorSkipLength value */\r
+ /* Set the PR and DA bits according to ETH DMAArbitration value */\r
+ heth->Instance->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |\r
+ dmainit.FixedBurst |\r
+ dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r
+ dmainit.TxDMABurstLength |\r
+ dmainit.EnhancedDescriptorFormat |\r
+ (dmainit.DescriptorSkipLength << 2) |\r
+ dmainit.DMAArbitration |\r
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */\r
+\r
+ /* Wait until the write operation will be taken into account:\r
+ at least four TX_CLK/RX_CLK clock cycles */\r
+ tmpreg = heth->Instance->DMABMR;\r
+ HAL_Delay(ETH_REG_WRITE_DELAY);\r
+ heth->Instance->DMABMR = tmpreg;\r
+\r
+ if(heth->Init.RxMode == ETH_RXINTERRUPT_MODE)\r
+ {\r
+ /* Enable the Ethernet Rx Interrupt */\r
+ __HAL_ETH_DMA_ENABLE_IT(( heth ), ETH_DMA_IT_NIS | ETH_DMA_IT_R);\r
+ }\r
+\r
+ /* Initialize MAC address in ethernet MAC */\r
+ ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);\r
+}\r
+\r
+/**\r
+ * @brief Configures the selected MAC address.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @param MacAddr: The MAC address to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_Address0: MAC Address0\r
+ * @arg ETH_MAC_Address1: MAC Address1\r
+ * @arg ETH_MAC_Address2: MAC Address2\r
+ * @arg ETH_MAC_Address3: MAC Address3\r
+ * @param Addr: Pointer to MAC address buffer data (6 bytes)\r
+ * @retval HAL status\r
+ */\r
+static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)\r
+{\r
+ uint32_t tmpreg;\r
+\r
+ /* Check the parameters */\r
+ assert_param( IS_ETH_MAC_ADDRESS0123( MacAddr ) );\r
+\r
+ /* Calculate the selected MAC address high register */\r
+ tmpreg = 0x80000000ul | ( ( uint32_t )Addr[ 5 ] << 8) | (uint32_t)Addr[ 4 ];\r
+ /* Load the selected MAC address high register */\r
+ ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + MacAddr ) ) ) = tmpreg;\r
+ /* Calculate the selected MAC address low register */\r
+ tmpreg = ( ( uint32_t )Addr[ 3 ] << 24 ) | ( ( uint32_t )Addr[ 2 ] << 16 ) | ( ( uint32_t )Addr[ 1 ] << 8 ) | Addr[ 0 ];\r
+\r
+ /* Load the selected MAC address low register */\r
+ ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + MacAddr ) ) ) = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the MAC transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_TE;\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the MAC transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_TE );\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Enables the MAC reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ __IO uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_RE;\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the MAC reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ __IO uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_RE );\r
+\r
+ prvWriteMACCR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Enables the DMA transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Enable the DMA transmission */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_ST;\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the DMA transmission.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Disable the DMA transmission */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_ST );\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Enables the DMA reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Enable the DMA reception */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_SR;\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Disables the DMA reception.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Disable the DMA reception */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_SR );\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @brief Clears the ETHERNET transmit FIFO.\r
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains\r
+ * the configuration information for ETHERNET module\r
+ * @retval None\r
+ */\r
+static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)\r
+{\r
+ /* Set the Flush Transmit FIFO bit */\r
+ __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_FTF;\r
+\r
+ prvWriteDMAOMR( heth, tmpreg );\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */\r
+#endif /* HAL_ETH_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx_hal_eth.h\r
+ * @author MCD Application Team\r
+ * @version V1.3.2\r
+ * @date 26-June-2015\r
+ * @brief Header file of ETH HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4xx_HAL_ETH_H\r
+#define __STM32F4xx_HAL_ETH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f4xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F4xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ETH\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ETH_Private_Macros\r
+ * @{\r
+ */\r
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)\r
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \\r
+ ((CMD) == ETH_AUTONEGOTIATION_DISABLE))\r
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \\r
+ ((SPEED) == ETH_SPEED_100M))\r
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \\r
+ ((MODE) == ETH_MODE_HALFDUPLEX))\r
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \\r
+ ((MODE) == ETH_MODE_HALFDUPLEX))\r
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
+ ((MODE) == ETH_RXINTERRUPT_MODE))\r
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
+ ((MODE) == ETH_RXINTERRUPT_MODE))\r
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \\r
+ ((MODE) == ETH_RXINTERRUPT_MODE))\r
+#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \\r
+ ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))\r
+#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \\r
+ ((MODE) == ETH_MEDIA_INTERFACE_RMII))\r
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \\r
+ ((CMD) == ETH_WATCHDOG_DISABLE))\r
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \\r
+ ((CMD) == ETH_JABBER_DISABLE))\r
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \\r
+ ((GAP) == ETH_INTERFRAMEGAP_40BIT))\r
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \\r
+ ((CMD) == ETH_CARRIERSENCE_DISABLE))\r
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVEOWN_DISABLE))\r
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \\r
+ ((CMD) == ETH_LOOPBACKMODE_DISABLE))\r
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \\r
+ ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))\r
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \\r
+ ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))\r
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \\r
+ ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))\r
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \\r
+ ((LIMIT) == ETH_BACKOFFLIMIT_8) || \\r
+ ((LIMIT) == ETH_BACKOFFLIMIT_4) || \\r
+ ((LIMIT) == ETH_BACKOFFLIMIT_1))\r
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \\r
+ ((CMD) == ETH_DEFFERRALCHECK_DISABLE))\r
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVEAll_DISABLE))\r
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \\r
+ ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \\r
+ ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))\r
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \\r
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \\r
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))\r
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \\r
+ ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))\r
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \\r
+ ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))\r
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \\r
+ ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))\r
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \\r
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \\r
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \\r
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))\r
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \\r
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \\r
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))\r
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)\r
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \\r
+ ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))\r
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \\r
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \\r
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \\r
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))\r
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \\r
+ ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))\r
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))\r
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \\r
+ ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))\r
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \\r
+ ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))\r
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)\r
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS1) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS3))\r
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \\r
+ ((ADDRESS) == ETH_MAC_ADDRESS3))\r
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \\r
+ ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))\r
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \\r
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))\r
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \\r
+ ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))\r
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \\r
+ ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))\r
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \\r
+ ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))\r
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \\r
+ ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))\r
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \\r
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))\r
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \\r
+ ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))\r
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \\r
+ ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))\r
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \\r
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \\r
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \\r
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))\r
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \\r
+ ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))\r
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \\r
+ ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))\r
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \\r
+ ((CMD) == ETH_FIXEDBURST_DISABLE))\r
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \\r
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))\r
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \\r
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))\r
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)\r
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \\r
+ ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))\r
+#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \\r
+ ((FLAG) == ETH_DMATXDESC_IC) || \\r
+ ((FLAG) == ETH_DMATXDESC_LS) || \\r
+ ((FLAG) == ETH_DMATXDESC_FS) || \\r
+ ((FLAG) == ETH_DMATXDESC_DC) || \\r
+ ((FLAG) == ETH_DMATXDESC_DP) || \\r
+ ((FLAG) == ETH_DMATXDESC_TTSE) || \\r
+ ((FLAG) == ETH_DMATXDESC_TER) || \\r
+ ((FLAG) == ETH_DMATXDESC_TCH) || \\r
+ ((FLAG) == ETH_DMATXDESC_TTSS) || \\r
+ ((FLAG) == ETH_DMATXDESC_IHE) || \\r
+ ((FLAG) == ETH_DMATXDESC_ES) || \\r
+ ((FLAG) == ETH_DMATXDESC_JT) || \\r
+ ((FLAG) == ETH_DMATXDESC_FF) || \\r
+ ((FLAG) == ETH_DMATXDESC_PCE) || \\r
+ ((FLAG) == ETH_DMATXDESC_LCA) || \\r
+ ((FLAG) == ETH_DMATXDESC_NC) || \\r
+ ((FLAG) == ETH_DMATXDESC_LCO) || \\r
+ ((FLAG) == ETH_DMATXDESC_EC) || \\r
+ ((FLAG) == ETH_DMATXDESC_VF) || \\r
+ ((FLAG) == ETH_DMATXDESC_CC) || \\r
+ ((FLAG) == ETH_DMATXDESC_ED) || \\r
+ ((FLAG) == ETH_DMATXDESC_UF) || \\r
+ ((FLAG) == ETH_DMATXDESC_DB))\r
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \\r
+ ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))\r
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \\r
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \\r
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \\r
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))\r
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)\r
+#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \\r
+ ((FLAG) == ETH_DMARXDESC_AFM) || \\r
+ ((FLAG) == ETH_DMARXDESC_ES) || \\r
+ ((FLAG) == ETH_DMARXDESC_DE) || \\r
+ ((FLAG) == ETH_DMARXDESC_SAF) || \\r
+ ((FLAG) == ETH_DMARXDESC_LE) || \\r
+ ((FLAG) == ETH_DMARXDESC_OE) || \\r
+ ((FLAG) == ETH_DMARXDESC_VLAN) || \\r
+ ((FLAG) == ETH_DMARXDESC_FS) || \\r
+ ((FLAG) == ETH_DMARXDESC_LS) || \\r
+ ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \\r
+ ((FLAG) == ETH_DMARXDESC_LC) || \\r
+ ((FLAG) == ETH_DMARXDESC_FT) || \\r
+ ((FLAG) == ETH_DMARXDESC_RWT) || \\r
+ ((FLAG) == ETH_DMARXDESC_RE) || \\r
+ ((FLAG) == ETH_DMARXDESC_DBE) || \\r
+ ((FLAG) == ETH_DMARXDESC_CE) || \\r
+ ((FLAG) == ETH_DMARXDESC_MAMPCE))\r
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \\r
+ ((BUFFER) == ETH_DMARXDESC_BUFFER2))\r
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \\r
+ ((FLAG) == ETH_PMT_FLAG_MPR))\r
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))\r
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \\r
+ ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \\r
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_T))\r
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \\r
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \\r
+ ((IT) == ETH_MAC_IT_PMT))\r
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \\r
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \\r
+ ((FLAG) == ETH_MAC_FLAG_PMT))\r
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \\r
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \\r
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \\r
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \\r
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \\r
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \\r
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \\r
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \\r
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))\r
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \\r
+ ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))\r
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \\r
+ ((IT) != 0x00))\r
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \\r
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \\r
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))\r
+#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \\r
+ ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ETH_Private_Defines\r
+ * @{\r
+ */\r
+/* Delay to wait when writing to some Ethernet registers */\r
+#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)\r
+\r
+/* ETHERNET Errors */\r
+#define ETH_SUCCESS ((uint32_t)0)\r
+#define ETH_ERROR ((uint32_t)1)\r
+\r
+/* ETHERNET DMA Tx descriptors Collision Count Shift */\r
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)\r
+\r
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */\r
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)\r
+\r
+/* ETHERNET DMA Rx descriptors Frame Length Shift */\r
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)\r
+\r
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */\r
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)\r
+\r
+/* ETHERNET DMA Rx descriptors Frame length Shift */\r
+#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)\r
+\r
+/* ETHERNET MAC address offsets */\r
+#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */\r
+#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */\r
+\r
+/* ETHERNET MACMIIAR register Mask */\r
+#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)\r
+\r
+/* ETHERNET MACCR register Mask */\r
+#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)\r
+\r
+/* ETHERNET MACFCR register Mask */\r
+#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)\r
+\r
+/* ETHERNET DMAOMR register Mask */\r
+#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)\r
+\r
+/* ETHERNET Remote Wake-up frame register length */\r
+#define ETH_WAKEUP_REGISTER_LENGTH 8\r
+\r
+/* ETHERNET Missed frames counter Shift */\r
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup ETH_Exported_Types ETH Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief HAL State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */\r
+ HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */\r
+ HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */\r
+ HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */\r
+ HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */\r
+ HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */\r
+ HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */\r
+ HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */\r
+ HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */\r
+ HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */\r
+}HAL_ETH_StateTypeDef;\r
+\r
+/**\r
+ * @brief ETH Init Structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY\r
+ The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)\r
+ and the mode (half/full-duplex).\r
+ This parameter can be a value of @ref ETH_AutoNegotiation */\r
+\r
+ uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.\r
+ This parameter can be a value of @ref ETH_Speed */\r
+\r
+ uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode\r
+ This parameter can be a value of @ref ETH_Duplex_Mode */\r
+\r
+ uint16_t PhyAddress; /*!< Ethernet PHY address.\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */\r
+\r
+ uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */\r
+\r
+ uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.\r
+ This parameter can be a value of @ref ETH_Rx_Mode */\r
+\r
+ uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.\r
+ This parameter can be a value of @ref ETH_Checksum_Mode */\r
+\r
+ uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.\r
+ This parameter can be a value of @ref ETH_Media_Interface */\r
+\r
+} ETH_InitTypeDef;\r
+\r
+\r
+ /**\r
+ * @brief ETH MAC Configuration Structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t Watchdog; /*!< Selects or not the Watchdog timer\r
+ When enabled, the MAC allows no more then 2048 bytes to be received.\r
+ When disabled, the MAC can receive up to 16384 bytes.\r
+ This parameter can be a value of @ref ETH_Watchdog */\r
+\r
+ uint32_t Jabber; /*!< Selects or not Jabber timer\r
+ When enabled, the MAC allows no more then 2048 bytes to be sent.\r
+ When disabled, the MAC can send up to 16384 bytes.\r
+ This parameter can be a value of @ref ETH_Jabber */\r
+\r
+ uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.\r
+ This parameter can be a value of @ref ETH_Inter_Frame_Gap */\r
+\r
+ uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.\r
+ This parameter can be a value of @ref ETH_Carrier_Sense */\r
+\r
+ uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,\r
+ ReceiveOwn allows the reception of frames when the TX_EN signal is asserted\r
+ in Half-Duplex mode.\r
+ This parameter can be a value of @ref ETH_Receive_Own */\r
+\r
+ uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.\r
+ This parameter can be a value of @ref ETH_Loop_Back_Mode */\r
+\r
+ uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.\r
+ This parameter can be a value of @ref ETH_Checksum_Offload */\r
+\r
+ uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,\r
+ when a collision occurs (Half-Duplex mode).\r
+ This parameter can be a value of @ref ETH_Retry_Transmission */\r
+\r
+ uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.\r
+ This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */\r
+\r
+ uint32_t BackOffLimit; /*!< Selects the BackOff limit value.\r
+ This parameter can be a value of @ref ETH_Back_Off_Limit */\r
+\r
+ uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).\r
+ This parameter can be a value of @ref ETH_Deferral_Check */\r
+\r
+ uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).\r
+ This parameter can be a value of @ref ETH_Receive_All */\r
+\r
+ uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.\r
+ This parameter can be a value of @ref ETH_Source_Addr_Filter */\r
+\r
+ uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)\r
+ This parameter can be a value of @ref ETH_Pass_Control_Frames */\r
+\r
+ uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.\r
+ This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */\r
+\r
+ uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.\r
+ This parameter can be a value of @ref ETH_Destination_Addr_Filter */\r
+\r
+ uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode\r
+ This parameter can be a value of @ref ETH_Promiscuous_Mode */\r
+\r
+ uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r
+ This parameter can be a value of @ref ETH_Multicast_Frames_Filter */\r
+\r
+ uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r
+ This parameter can be a value of @ref ETH_Unicast_Frames_Filter */\r
+\r
+ uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.\r
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */\r
+\r
+ uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.\r
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */\r
+\r
+ uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.\r
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.\r
+ This parameter can be a value of @ref ETH_Zero_Quanta_Pause */\r
+\r
+ uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for\r
+ automatic retransmission of PAUSE Frame.\r
+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */\r
+\r
+ uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0\r
+ unicast address and unique multicast address).\r
+ This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */\r
+\r
+ uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and\r
+ disable its transmitter for a specified time (Pause Time)\r
+ This parameter can be a value of @ref ETH_Receive_Flow_Control */\r
+\r
+ uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)\r
+ or the MAC back-pressure operation (Half-Duplex mode)\r
+ This parameter can be a value of @ref ETH_Transmit_Flow_Control */\r
+\r
+ uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for\r
+ comparison and filtering.\r
+ This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */\r
+\r
+ uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */\r
+\r
+} ETH_MACInitTypeDef;\r
+\r
+\r
+/**\r
+ * @brief ETH DMA Configuration Structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.\r
+ This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */\r
+\r
+ uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.\r
+ This parameter can be a value of @ref ETH_Receive_Store_Forward */\r
+\r
+ uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.\r
+ This parameter can be a value of @ref ETH_Flush_Received_Frame */\r
+\r
+ uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.\r
+ This parameter can be a value of @ref ETH_Transmit_Store_Forward */\r
+\r
+ uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.\r
+ This parameter can be a value of @ref ETH_Transmit_Threshold_Control */\r
+\r
+ uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.\r
+ This parameter can be a value of @ref ETH_Forward_Error_Frames */\r
+\r
+ uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error\r
+ and length less than 64 bytes) including pad-bytes and CRC)\r
+ This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */\r
+\r
+ uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.\r
+ This parameter can be a value of @ref ETH_Receive_Threshold_Control */\r
+\r
+ uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second\r
+ frame of Transmit data even before obtaining the status for the first frame.\r
+ This parameter can be a value of @ref ETH_Second_Frame_Operate */\r
+\r
+ uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.\r
+ This parameter can be a value of @ref ETH_Address_Aligned_Beats */\r
+\r
+ uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.\r
+ This parameter can be a value of @ref ETH_Fixed_Burst */\r
+\r
+ uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.\r
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */\r
+\r
+ uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.\r
+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */\r
+\r
+ uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.\r
+ This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */\r
+\r
+ uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)\r
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */\r
+\r
+ uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.\r
+ This parameter can be a value of @ref ETH_DMA_Arbitration */\r
+} ETH_DMAInitTypeDef;\r
+\r
+\r
+/**\r
+ * @brief ETH DMA Descriptors data structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t Status; /*!< Status */\r
+\r
+ uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */\r
+\r
+ uint32_t Buffer1Addr; /*!< Buffer1 address pointer */\r
+\r
+ uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */\r
+\r
+ /*!< Enhanced ETHERNET DMA PTP Descriptors */\r
+ uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */\r
+\r
+ uint32_t Reserved1; /*!< Reserved */\r
+\r
+ uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */\r
+\r
+ uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */\r
+\r
+} ETH_DMADescTypeDef;\r
+\r
+\r
+/**\r
+ * @brief Received Frame Informations structure definition\r
+ */\r
+typedef struct\r
+{\r
+ ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */\r
+\r
+ ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */\r
+\r
+ uint32_t SegCount; /*!< Segment count */\r
+\r
+ uint32_t length; /*!< Frame length */\r
+\r
+ uint32_t buffer; /*!< Frame buffer */\r
+\r
+} ETH_DMARxFrameInfos;\r
+\r
+\r
+/**\r
+ * @brief ETH Handle Structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ ETH_TypeDef *Instance; /*!< Register base address */\r
+\r
+ ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */\r
+\r
+ uint32_t LinkStatus; /*!< Ethernet link status */\r
+\r
+ ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */\r
+\r
+ ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */\r
+\r
+ ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */\r
+\r
+ __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */\r
+\r
+ HAL_LockTypeDef Lock; /*!< ETH Lock */\r
+\r
+} ETH_HandleTypeDef;\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup ETH_Exported_Constants ETH Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH_Buffers_setting ETH Buffers setting\r
+ * @{\r
+ */\r
+#define ETH_MAX_PACKET_SIZE (1536u) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */\r
+#define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */\r
+#define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */\r
+#define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */\r
+#define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */\r
+#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */\r
+#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */\r
+#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */\r
+\r
+ /* Ethernet driver receive buffers are organized in a chained linked-list, when\r
+ an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO\r
+ to the driver receive buffers memory.\r
+\r
+ Depending on the size of the received ethernet packet and the size of\r
+ each ethernet driver receive buffer, the received packet can take one or more\r
+ ethernet driver receive buffer.\r
+\r
+ In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE\r
+ and the total count of the driver receive buffers ETH_RXBUFNB.\r
+\r
+ The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as\r
+ example, they can be reconfigured in the application layer to fit the application\r
+ needs */\r
+\r
+/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet\r
+ packet */\r
+#ifndef ETH_RX_BUF_SIZE\r
+ #error please define ETH_RX_BUF_SIZE\r
+ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE\r
+#endif\r
+\r
+/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/\r
+#ifndef ETH_RXBUFNB\r
+ #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */\r
+#endif\r
+\r
+\r
+ /* Ethernet driver transmit buffers are organized in a chained linked-list, when\r
+ an ethernet packet is transmitted, Tx-DMA will transfer the packet from the\r
+ driver transmit buffers memory to the TxFIFO.\r
+\r
+ Depending on the size of the Ethernet packet to be transmitted and the size of\r
+ each ethernet driver transmit buffer, the packet to be transmitted can take\r
+ one or more ethernet driver transmit buffer.\r
+\r
+ In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE\r
+ and the total count of the driver transmit buffers ETH_TXBUFNB.\r
+\r
+ The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as\r
+ example, they can be reconfigured in the application layer to fit the application\r
+ needs */\r
+\r
+/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet\r
+ packet */\r
+#ifndef ETH_TX_BUF_SIZE\r
+ #error please define ETH_TX_BUF_SIZE\r
+ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE\r
+#endif\r
+\r
+/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/\r
+#ifndef ETH_TXBUFNB\r
+ #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */\r
+#endif\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor\r
+ * @{\r
+ */\r
+\r
+/*\r
+ DMA Tx Descriptor\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES2 | Buffer1 Address [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+*/\r
+\r
+/**\r
+ * @brief Bit definition of TDES0 register: DMA Tx descriptor status register\r
+ */\r
+#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */\r
+#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */\r
+#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */\r
+#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */\r
+#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */\r
+#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */\r
+#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */\r
+#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */\r
+#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */\r
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */\r
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */\r
+#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */\r
+#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */\r
+#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */\r
+#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */\r
+#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */\r
+#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */\r
+#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */\r
+#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */\r
+#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */\r
+#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */\r
+#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */\r
+#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */\r
+#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */\r
+#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */\r
+#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */\r
+#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */\r
+#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */\r
+\r
+/**\r
+ * @brief Bit definition of TDES1 register\r
+ */\r
+#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */\r
+#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */\r
+\r
+/**\r
+ * @brief Bit definition of TDES2 register\r
+ */\r
+#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */\r
+\r
+/**\r
+ * @brief Bit definition of TDES3 register\r
+ */\r
+#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */\r
+\r
+ /*---------------------------------------------------------------------------------------------\r
+ TDES6 | Transmit Time Stamp Low [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES7 | Transmit Time Stamp High [31:0] |\r
+ ----------------------------------------------------------------------------------------------*/\r
+\r
+/* Bit definition of TDES6 register */\r
+ #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */\r
+\r
+/* Bit definition of TDES7 register */\r
+ #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor\r
+ * @{\r
+ */\r
+\r
+/*\r
+ DMA Rx Descriptor\r
+ --------------------------------------------------------------------------------------------------------------------\r
+ RDES0 | OWN(31) | Status [30:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES2 | Buffer1 Address [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+*/\r
+\r
+/**\r
+ * @brief Bit definition of RDES0 register: DMA Rx descriptor status register\r
+ */\r
+#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */\r
+#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */\r
+#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */\r
+#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */\r
+#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */\r
+#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */\r
+#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */\r
+#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */\r
+#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */\r
+#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */\r
+#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */\r
+#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */\r
+#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */\r
+#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */\r
+#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */\r
+#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */\r
+#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */\r
+#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */\r
+\r
+/**\r
+ * @brief Bit definition of RDES1 register\r
+ */\r
+#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */\r
+#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */\r
+#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */\r
+#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */\r
+#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */\r
+\r
+/**\r
+ * @brief Bit definition of RDES2 register\r
+ */\r
+#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */\r
+\r
+/**\r
+ * @brief Bit definition of RDES3 register\r
+ */\r
+#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */\r
+\r
+/*---------------------------------------------------------------------------------------------------------------------\r
+ RDES4 | Reserved[31:15] | Extended Status [14:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES5 | Reserved[31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES6 | Receive Time Stamp Low [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES7 | Receive Time Stamp High [31:0] |\r
+ --------------------------------------------------------------------------------------------------------------------*/\r
+\r
+/* Bit definition of RDES4 register */\r
+#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */\r
+#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */\r
+#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */\r
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */\r
+#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */\r
+#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */\r
+#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */\r
+#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */\r
+#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */\r
+#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */\r
+ #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */\r
+ #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */\r
+ #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */\r
+\r
+/* Bit definition of RDES6 register */\r
+#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */\r
+\r
+/* Bit definition of RDES7 register */\r
+#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */\r
+/**\r
+ * @}\r
+ */\r
+ /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation\r
+ * @{\r
+ */\r
+#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)\r
+#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_Speed ETH Speed\r
+ * @{\r
+ */\r
+#define ETH_SPEED_10M ((uint32_t)0x00000000)\r
+#define ETH_SPEED_100M ((uint32_t)0x00004000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode\r
+ * @{\r
+ */\r
+#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)\r
+#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup ETH_Rx_Mode ETH Rx Mode\r
+ * @{\r
+ */\r
+#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)\r
+#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Checksum_Mode ETH Checksum Mode\r
+ * @{\r
+ */\r
+#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)\r
+#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Media_Interface ETH Media Interface\r
+ * @{\r
+ */\r
+#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)\r
+#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Watchdog ETH Watchdog\r
+ * @{\r
+ */\r
+#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Jabber ETH Jabber\r
+ * @{\r
+ */\r
+#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap\r
+ * @{\r
+ */\r
+#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */\r
+#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */\r
+#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */\r
+#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */\r
+#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */\r
+#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */\r
+#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */\r
+#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Carrier_Sense ETH Carrier Sense\r
+ * @{\r
+ */\r
+#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Own ETH Receive Own\r
+ * @{\r
+ */\r
+#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode\r
+ * @{\r
+ */\r
+#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)\r
+#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Checksum_Offload ETH Checksum Offload\r
+ * @{\r
+ */\r
+#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)\r
+#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Retry_Transmission ETH Retry Transmission\r
+ * @{\r
+ */\r
+#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip\r
+ * @{\r
+ */\r
+#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)\r
+#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit\r
+ * @{\r
+ */\r
+#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)\r
+#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)\r
+#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)\r
+#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Deferral_Check ETH Deferral Check\r
+ * @{\r
+ */\r
+#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)\r
+#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_All ETH Receive All\r
+ * @{\r
+ */\r
+#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)\r
+#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter\r
+ * @{\r
+ */\r
+#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)\r
+#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)\r
+#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames\r
+ * @{\r
+ */\r
+#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */\r
+#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */\r
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception\r
+ * @{\r
+ */\r
+#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter\r
+ * @{\r
+ */\r
+#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)\r
+#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode\r
+ * @{\r
+ */\r
+#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)\r
+#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter\r
+ * @{\r
+ */\r
+#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)\r
+#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)\r
+#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)\r
+#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter\r
+ * @{\r
+ */\r
+#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)\r
+#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)\r
+#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause\r
+ * @{\r
+ */\r
+#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold\r
+ * @{\r
+ */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */\r
+#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect\r
+ * @{\r
+ */\r
+#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)\r
+#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control\r
+ * @{\r
+ */\r
+#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)\r
+#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control\r
+ * @{\r
+ */\r
+#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)\r
+#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison\r
+ * @{\r
+ */\r
+#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)\r
+#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses ETH MAC addresses\r
+ * @{\r
+ */\r
+#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)\r
+#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)\r
+#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)\r
+#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA\r
+ * @{\r
+ */\r
+#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)\r
+#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes\r
+ * @{\r
+ */\r
+#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */\r
+#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags\r
+ * @{\r
+ */\r
+#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */\r
+#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */\r
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */\r
+#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */\r
+#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */\r
+#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */\r
+#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */\r
+#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */\r
+#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */\r
+#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */\r
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */\r
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */\r
+#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */\r
+#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */\r
+#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */\r
+#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */\r
+#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */\r
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */\r
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */\r
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */\r
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame\r
+ * @{\r
+ */\r
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward\r
+ * @{\r
+ */\r
+#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)\r
+#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame\r
+ * @{\r
+ */\r
+#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)\r
+#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward\r
+ * @{\r
+ */\r
+#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)\r
+#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control\r
+ * @{\r
+ */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames\r
+ * @{\r
+ */\r
+#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)\r
+#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames\r
+ * @{\r
+ */\r
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)\r
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control\r
+ * @{\r
+ */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */\r
+#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate\r
+ * @{\r
+ */\r
+#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)\r
+#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats\r
+ * @{\r
+ */\r
+#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)\r
+#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Fixed_Burst ETH Fixed Burst\r
+ * @{\r
+ */\r
+#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)\r
+#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length\r
+ * @{\r
+ */\r
+#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length\r
+ * @{\r
+ */\r
+#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format\r
+ * @{\r
+ */\r
+#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)\r
+#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration\r
+ * @{\r
+ */\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)\r
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)\r
+#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment\r
+ * @{\r
+ */\r
+#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */\r
+#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control\r
+ * @{\r
+ */\r
+#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */\r
+#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */\r
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */\r
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers\r
+ * @{\r
+ */\r
+#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */\r
+#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_PMT_Flags ETH PMT Flags\r
+ * @{\r
+ */\r
+#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */\r
+#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */\r
+#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts\r
+ * @{\r
+ */\r
+#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts\r
+ * @{\r
+ */\r
+#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Flags ETH MAC Flags\r
+ * @{\r
+ */\r
+#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */\r
+#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */\r
+#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */\r
+#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */\r
+#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Flags ETH DMA Flags\r
+ * @{\r
+ */\r
+#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write transfer, 1-read transfer */\r
+#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */\r
+#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */\r
+#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */\r
+#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */\r
+#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */\r
+#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */\r
+#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */\r
+#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */\r
+#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */\r
+#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */\r
+#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */\r
+#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */\r
+#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */\r
+#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */\r
+#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */\r
+#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts\r
+ * @{\r
+ */\r
+#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */\r
+#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */\r
+#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */\r
+#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */\r
+#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts\r
+ * @{\r
+ */\r
+#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */\r
+#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */\r
+#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */\r
+#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */\r
+#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */\r
+#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */\r
+#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */\r
+#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */\r
+#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */\r
+#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */\r
+#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */\r
+#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */\r
+#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */\r
+#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */\r
+#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */\r
+#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */\r
+#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state\r
+ * @{\r
+ */\r
+#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */\r
+#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */\r
+#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */\r
+#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */\r
+#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */\r
+#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state\r
+ * @{\r
+ */\r
+#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */\r
+#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */\r
+#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */\r
+#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */\r
+#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */\r
+#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_overflow ETH DMA overflow\r
+ * @{\r
+ */\r
+#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */\r
+#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP\r
+ * @{\r
+ */\r
+#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup ETH_Exported_Macros ETH Exported Macros\r
+ * @brief macros to handle interrupts and specific clock configurations\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset ETH handle state\r
+ * @param __HANDLE__: specifies the ETH handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag of TDES0 to check.\r
+ * @retval the ETH_DMATxDescFlag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag of RDES0 to check.\r
+ * @retval the ETH_DMATxDescFlag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))\r
+\r
+/**\r
+ * @brief Enables the specified DMA Rx Desc receive interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))\r
+\r
+/**\r
+ * @brief Disables the specified DMA Rx Desc receive interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)\r
+\r
+/**\r
+ * @brief Set the specified DMA Rx Desc Own bit.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)\r
+\r
+/**\r
+ * @brief Returns the specified ETHERNET DMA Tx Desc collision count.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval The Transmit descriptor collision counter value.\r
+ */\r
+#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)\r
+\r
+/**\r
+ * @brief Set the specified DMA Tx Desc Own bit.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)\r
+\r
+/**\r
+ * @brief Enables the specified DMA Tx Desc Transmit interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)\r
+\r
+/**\r
+ * @brief Disables the specified DMA Tx Desc Transmit interrupt.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)\r
+\r
+/**\r
+ * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass\r
+ * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum\r
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present\r
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))\r
+\r
+/**\r
+ * @brief Enables the DMA Tx Desc CRC.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)\r
+\r
+/**\r
+ * @brief Disables the DMA Tx Desc CRC.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)\r
+\r
+/**\r
+ * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)\r
+\r
+/**\r
+ * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)\r
+\r
+/**\r
+ * @brief Enables the specified ETHERNET MAC interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be\r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt\r
+ * @arg ETH_MAC_IT_PMT : PMT interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified ETHERNET MAC interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be\r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt\r
+ * @arg ETH_MAC_IT_PMT : PMT interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Initiate a Pause Control Frame (Full-duplex only).\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Checks whether the ETHERNET flow control busy bit is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval The new state of flow control busy status bit (SET or RESET).\r
+ */\r
+#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Disables the MAC BackPressure operation activation (Half-duplex only).\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET MAC flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag\r
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag\r
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag\r
+ * @arg ETH_MAC_FLAG_MMC : MMC flag\r
+ * @arg ETH_MAC_FLAG_PMT : PMT flag\r
+ * @retval The state of ETHERNET MAC flag.\r
+ */\r
+#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))\r
+\r
+/**\r
+ * @brief Enables the specified ETHERNET DMA interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be\r
+ * enabled @ref ETH_DMA_Interrupts\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified ETHERNET DMA interrupts.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be\r
+ * disabled. @ref ETH_DMA_Interrupts\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Clears the ETHERNET DMA IT pending bit.\r
+ * @param __HANDLE__ : ETH Handle\r
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.\r
+* @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags\r
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags\r
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r
+ */\r
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __OVERFLOW__: specifies the DMA overflow flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter\r
+ * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter\r
+ * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))\r
+\r
+/**\r
+ * @brief Set the DMA Receive status watchdog timer register value\r
+ * @param __HANDLE__: ETH Handle\r
+ * @param __VALUE__: DMA Receive status watchdog timer register value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))\r
+\r
+/**\r
+ * @brief Enables any unicast packet filtered by the MAC address\r
+ * recognition to be a wake-up frame.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)\r
+\r
+/**\r
+ * @brief Disables any unicast packet filtered by the MAC address\r
+ * recognition to be a wake-up frame.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)\r
+\r
+/**\r
+ * @brief Enables the MAC Wake-Up Frame Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)\r
+\r
+/**\r
+ * @brief Disables the MAC Wake-Up Frame Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)\r
+\r
+/**\r
+ * @brief Enables the MAC Magic Packet Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)\r
+\r
+/**\r
+ * @brief Disables the MAC Magic Packet Detection.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)\r
+\r
+/**\r
+ * @brief Enables the MAC Power Down.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)\r
+\r
+/**\r
+ * @brief Disables the MAC Power Down.\r
+ * @param __HANDLE__: ETH Handle\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET PMT flag is set or not.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __FLAG__: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset\r
+ * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received\r
+ * @arg ETH_PMT_FLAG_MPR : Magic Packet Received\r
+ * @retval The new state of ETHERNET PMT Flag (SET or RESET).\r
+ */\r
+#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))\r
+\r
+/**\r
+ * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))\r
+\r
+/**\r
+ * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\\r
+ (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)\r
+\r
+/**\r
+ * @brief Enables the MMC Counter Freeze.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)\r
+\r
+/**\r
+ * @brief Disables the MMC Counter Freeze.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)\r
+\r
+/**\r
+ * @brief Enables the MMC Reset On Read.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)\r
+\r
+/**\r
+ * @brief Disables the MMC Reset On Read.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)\r
+\r
+/**\r
+ * @brief Enables the MMC Counter Stop Rollover.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)\r
+\r
+/**\r
+ * @brief Disables the MMC Counter Stop Rollover.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)\r
+\r
+/**\r
+ * @brief Resets the MMC Counters.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)\r
+\r
+/**\r
+ * @brief Enables the specified ETHERNET MMC Rx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)\r
+/**\r
+ * @brief Disables the specified ETHERNET MMC Rx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)\r
+/**\r
+ * @brief Enables the specified ETHERNET MMC Tx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disables the specified ETHERNET MMC Tx interrupts.\r
+ * @param __HANDLE__: ETH Handle.\r
+ * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value\r
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Enables the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Disables the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enable event on ETH External event line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Disable event on ETH External event line\r
+ * @retval None.\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Get flag of the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Clear flag of the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enables rising edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP\r
+\r
+/**\r
+ * @brief Disables the rising edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enables falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Disables falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Enables rising/falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\\r
+ EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP\r
+\r
+/**\r
+ * @brief Disables rising/falling edge trigger to the ETH External interrupt line.\r
+ * @retval None\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\\r
+ EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r
+\r
+/**\r
+ * @brief Generate a Software interrupt on selected EXTI line.\r
+ * @retval None.\r
+ */\r
+#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup ETH_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/* Initialization and de-initialization functions ****************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);\r
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* IO operation functions ****************************************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);\r
+/* Communication with PHY functions*/\r
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);\r
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);\r
+/* Callback in non blocking modes (Interrupt) */\r
+void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);\r
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Peripheral Control functions **********************************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);\r
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);\r
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Peripheral State functions ************************************************/\r
+\r
+/** @addtogroup ETH_Exported_Functions_Group4\r
+ * @{\r
+ */\r
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F4xx_HAL_ETH_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+#warning Temoporary file and a dependent on the Zynq network interface.\r
+\r
+/*\r
+ * uncached_memory.c\r
+ *\r
+ * This module will declare 1 MB of memory and switch off the caching for it.\r
+ *\r
+ * pucGetUncachedMemory( ulSize ) returns a trunc of this memory with a length\r
+ * rounded up to a multiple of 4 KB\r
+ *\r
+ * ucIsCachedMemory( pucBuffer ) returns non-zero if a given pointer is NOT\r
+ * within the range of the 1 MB non-cached memory.\r
+ *\r
+ */\r
+\r
+/*\r
+ * After "_end", 1 MB of uncached memory will be allocated for DMA transfers.\r
+ * Both the DMA descriptors as well as all EMAC TX-buffers will be allocated in\r
+ * uncached memory.\r
+ */\r
+\r
+#include "Zynq/x_emacpsif.h"\r
+#include "Zynq/x_topology.h"\r
+#include "xstatus.h"\r
+\r
+#include "xparameters.h"\r
+#include "xparameters_ps.h"\r
+#include "xil_exception.h"\r
+#include "xil_mmu.h"\r
+\r
+#include "FreeRTOS.h"\r
+\r
+#include "uncached_memory.h"\r
+\r
+#include "Demo_Logging.h"\r
+\r
+#define UNCACHED_MEMORY_SIZE 0x100000ul\r
+\r
+#define DDR_MEMORY_END (XPAR_PS7_DDR_0_S_AXI_HIGHADDR+1)\r
+\r
+static void vInitialiseUncachedMemory( void );\r
+\r
+static uint8_t *pucHeadOfMemory;\r
+static uint32_t ulMemorySize;\r
+static uint8_t *pucStartOfMemory = NULL;\r
+\r
+uint8_t ucIsCachedMemory( const uint8_t *pucBuffer )\r
+{\r
+uint8_t ucReturn;\r
+\r
+ if( ( pucStartOfMemory != NULL ) &&\r
+ ( pucBuffer >= pucStartOfMemory ) &&\r
+ ( pucBuffer < ( pucStartOfMemory + UNCACHED_MEMORY_SIZE ) ) )\r
+ {\r
+ ucReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ ucReturn = pdTRUE;\r
+ }\r
+\r
+ return ucReturn;\r
+}\r
+\r
+uint8_t *pucGetUncachedMemory( uint32_t ulSize )\r
+{\r
+uint8_t *pucReturn;\r
+\r
+ if( pucStartOfMemory == NULL )\r
+ {\r
+ vInitialiseUncachedMemory( );\r
+ }\r
+ if( ( pucStartOfMemory == NULL ) || ( ulSize > ulMemorySize ) )\r
+ {\r
+ pucReturn = NULL;\r
+ }\r
+ else\r
+ {\r
+ uint32_t ulSkipSize;\r
+\r
+ pucReturn = pucHeadOfMemory;\r
+ ulSkipSize = ( ulSize + 0x1000ul ) & ~0xffful;\r
+ pucHeadOfMemory += ulSkipSize;\r
+ ulMemorySize -= ulSkipSize;\r
+ }\r
+\r
+ return pucReturn;\r
+}\r
+\r
+extern u8 _end;\r
+\r
+static void vInitialiseUncachedMemory( )\r
+{\r
+ /* At the end of program's space... */\r
+ pucStartOfMemory = (uint8_t *) &_end;\r
+ /*\r
+ * Align the start address to 1 MB boundary.\r
+ */\r
+ pucStartOfMemory = (uint8_t *)( ( ( uint32_t )pucStartOfMemory + UNCACHED_MEMORY_SIZE ) & ( ~( UNCACHED_MEMORY_SIZE - 1 ) ) );\r
+\r
+ if( ( ( u32 )pucStartOfMemory ) + UNCACHED_MEMORY_SIZE > DDR_MEMORY_END )\r
+ {\r
+ vLoggingPrintf("vInitialiseUncachedMemory: Can not allocate uncached memory\n" );\r
+ }\r
+ else\r
+ {\r
+ /*\r
+ * Some objects want to be stored in uncached memory. Hence the 1 MB\r
+ * address range that starts after "_end" is made uncached\r
+ * by setting appropriate attributes in the translation table.\r
+ */\r
+ Xil_SetTlbAttributes( ( uint32_t )pucStartOfMemory, 0xc02 ); // addr, attr\r
+\r
+ /* For experiments in the SDIO driver, make the remaining uncached memory public */\r
+ pucHeadOfMemory = pucStartOfMemory;\r
+ ulMemorySize = UNCACHED_MEMORY_SIZE;\r
+ memset( pucStartOfMemory, '\0', UNCACHED_MEMORY_SIZE );\r
+ }\r
+}\r
--- /dev/null
+/*\r
+ * uncached_memory.h\r
+ *\r
+ * This module will declare 1 MB of memory and switch off the caching for it.\r
+ *\r
+ * pucGetUncachedMemory( ulSize ) returns a trunc of this memory with a length\r
+ * rounded up to a multiple of 4 KB\r
+ *\r
+ * ucIsCachedMemory( pucBuffer ) returns non-zero if a given pointer is NOT\r
+ * within the range of the 1 MB non-cached memory.\r
+ *\r
+ */\r
+\r
+#ifndef UNCACHEMEMORY_H\r
+\r
+#define UNCACHEMEMORY_H\r
+\r
+uint8_t *pucGetUncachedMemory( uint32_t ulSize );\r
+\r
+uint8_t ucIsCachedMemory( const uint8_t *pucBuffer );\r
+\r
+#endif /* UNCACHEMEMORY_H */\r
+\r
--- /dev/null
+/*\r
+ * Handling of Ethernet PHY's\r
+ * PHY's communicate with an EMAC either through\r
+ * a Media-Independent Interface (MII), or a Reduced Media-Independent Interface (RMII).\r
+ * The EMAC can poll for PHY ports on 32 different addresses. Each of the PHY ports\r
+ * shall be treated independently.\r
+ * \r
+ */\r
+\r
+#ifndef PHYHANDLING_H\r
+\r
+#define PHYHANDLING_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+#ifndef ipconfigPHY_MAX_PORTS\r
+ /* There can be at most 32 PHY ports, but in most cases there are 4 or less. */\r
+ #define ipconfigPHY_MAX_PORTS 4\r
+#endif\r
+\r
+/* A generic user-provided function that reads from the PHY-port at 'xAddress'( 0-based ). A 16-bit value shall be stored in\r
+ '*pusValue'. xRegister is the register number ( 0 .. 31 ). In fact all PHY registers are 16-bit.\r
+ Return non-zero in case the action failed. */\r
+typedef BaseType_t ( *xApplicationPhyReadHook_t )( BaseType_t xAddress, BaseType_t xRegister, uint32_t *pulValue );\r
+\r
+/* A generic user-provided function that writes 'usValue' to the\r
+ PHY-port at 'xAddress' ( 0-based ). xRegister is the register number ( 0 .. 31 ).\r
+ Return non-zero in case the action failed. */\r
+typedef BaseType_t ( *xApplicationPhyWriteHook_t )( BaseType_t xAddress, BaseType_t xRegister, uint32_t ulValue );\r
+\r
+typedef struct xPhyProperties\r
+{\r
+ uint8_t ucSpeed;\r
+ uint8_t ucMDI_X; /* MDI-X : Medium Dependent Interface - Crossover */\r
+ uint8_t ucDuplex;\r
+ uint8_t ucSpare;\r
+} PhyProperties_t;\r
+\r
+typedef struct xEthernetPhy\r
+{\r
+ xApplicationPhyReadHook_t fnPhyRead;\r
+ xApplicationPhyWriteHook_t fnPhyWrite;\r
+ uint32_t ulPhyIDs[ ipconfigPHY_MAX_PORTS ];\r
+ uint8_t ucPhyIndexes[ ipconfigPHY_MAX_PORTS ];\r
+ TimeOut_t xLinkStatusTimer;\r
+ TickType_t xLinkStatusRemaining;\r
+ BaseType_t xPortCount;\r
+ uint32_t ulBCRValue;\r
+ uint32_t ulACRValue;\r
+ uint32_t ulLinkStatusMask;\r
+ PhyProperties_t xPhyPreferences;\r
+ PhyProperties_t xPhyProperties;\r
+} EthernetPhy_t;\r
+\r
+/* Some defines used internally here to indicate preferences about speed, MDIX\r
+(wired direct or crossed), and duplex (half or full). */\r
+\r
+/* Values for PhyProperties_t::ucSpeed : */\r
+#define PHY_SPEED_10 1\r
+#define PHY_SPEED_100 2\r
+#define PHY_SPEED_AUTO 3\r
+\r
+/* Values for PhyProperties_t::ucMDI_X : */\r
+#define PHY_MDIX_DIRECT 1\r
+#define PHY_MDIX_CROSSED 2\r
+#define PHY_MDIX_AUTO 3\r
+\r
+/* Values for PhyProperties_t::ucDuplex : */\r
+#define PHY_DUPLEX_HALF 1\r
+#define PHY_DUPLEX_FULL 2\r
+#define PHY_DUPLEX_AUTO 3\r
+\r
+/* ID's of supported PHY's : */\r
+#define PHY_ID_LAN8742A 0x0007c130\r
+#define PHY_ID_LAN8720 0x0007c0f0\r
+\r
+#define PHY_ID_KSZ8041 0x000010A1\r
+#define PHY_ID_KSZ8051 0x000010A1\r
+#define PHY_ID_KSZ8081 0x000010A1\r
+\r
+#define PHY_ID_KSZ8863 0x00221430\r
+\r
+#define PHY_ID_DP83848I 0x20005C90\r
+\r
+\r
+/* Initialise the struct and assign a PHY-read and -write function. */\r
+void vPhyInitialise( EthernetPhy_t *pxPhyObject, xApplicationPhyReadHook_t fnPhyRead, xApplicationPhyWriteHook_t fnPhyWrite );\r
+\r
+/* Discover all PHY's connected by polling 32 indexes ( zero-based ) */\r
+BaseType_t xPhyDiscover( EthernetPhy_t *pxPhyObject );\r
+\r
+/* Send a reset commando to the connected PHY ports and send configuration. */\r
+BaseType_t xPhyConfigure( EthernetPhy_t *pxPhyObject, const PhyProperties_t *pxPhyProperties );\r
+\r
+/* Give a commando to start auto negotiation on a set of PHY port's. */\r
+BaseType_t xPhyStartAutoNegotiation( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask );\r
+\r
+/* Do not use auto negotiation but use predefined values from 'pxPhyObject->xPhyPreferences'. */\r
+BaseType_t xPhyFixedValue( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask );\r
+\r
+/* Check the current Link Status.\r
+'xHadReception' : make this true if a packet has been received since the\r
+last call to this function. */\r
+BaseType_t xPhyCheckLinkStatus( EthernetPhy_t *pxPhyObject, BaseType_t xHadReception );\r
+\r
+static __inline uint32_t xPhyGetMask( EthernetPhy_t *pxPhyObject )\r
+{\r
+ return ( ( ( uint32_t ) 1u ) << pxPhyObject-> xPortCount ) - 1;\r
+}\r
+\r
+#ifdef __cplusplus\r
+} /* extern "C" */\r
+#endif\r
+\r
+#endif\r
--- /dev/null
+/**\r
+ *\r
+ * \file\r
+ *\r
+ * \brief KS8851SNL driver for SAM.\r
+ *\r
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+#include "spi_master.h"\r
+#include "ksz8851snl.h"\r
+#include "ksz8851snl_reg.h"\r
+#include "delay.h"\r
+#include "pio.h"\r
+#include "pio_handler.h"\r
+#include "pdc.h"\r
+#include "conf_eth.h"\r
+\r
+/* Clock polarity. */\r
+#define SPI_CLK_POLARITY 0\r
+\r
+/* Clock phase. */\r
+#define SPI_CLK_PHASE 1\r
+\r
+/* SPI PDC register base. */\r
+Pdc *g_p_spi_pdc = 0;\r
+\r
+int lUDPLoggingPrintf( const char *pcFormatString, ... );\r
+\r
+/* Temporary buffer for PDC reception. */\r
+uint8_t tmpbuf[1536] __attribute__ ((aligned (16)));\r
+\r
+union {\r
+ uint64_t ul[2];\r
+ uint8_t uc[16];\r
+} cmdBuf, respBuf;\r
+\r
+void dbg_add_line( const char *pcFormat, ... );\r
+\r
+static void spi_clear_ovres( void );\r
+\r
+/**\r
+ * \brief Read register content, set bitmask and write back to register.\r
+ *\r
+ * \param reg the register address to modify.\r
+ * \param bits_to_set bitmask to apply.\r
+ */\r
+void ksz8851_reg_setbits(uint16_t reg, uint16_t bits_to_set)\r
+{\r
+ uint16_t temp;\r
+\r
+ temp = ksz8851_reg_read(reg);\r
+ temp |= bits_to_set;\r
+ ksz8851_reg_write(reg, temp);\r
+}\r
+\r
+/**\r
+ * \brief Read register content, clear bitmask and write back to register.\r
+ *\r
+ * \param reg the register address to modify.\r
+ * \param bits_to_set bitmask to apply.\r
+ */\r
+void ksz8851_reg_clrbits(uint16_t reg, uint16_t bits_to_clr)\r
+{\r
+ uint16_t temp;\r
+\r
+ temp = ksz8851_reg_read(reg);\r
+ temp &= ~(uint32_t) bits_to_clr;\r
+ ksz8851_reg_write(reg, temp);\r
+}\r
+\r
+/**\r
+ * \brief Configure the INTN interrupt.\r
+ */\r
+void configure_intn(void (*p_handler) (uint32_t, uint32_t))\r
+{\r
+// gpio_configure_pin(KSZ8851SNL_INTN_GPIO, PIO_INPUT);\r
+// pio_set_input(PIOA, PIO_PA11_IDX, PIO_PULLUP);\r
+\r
+ /* Configure PIO clock. */\r
+ pmc_enable_periph_clk(INTN_ID);\r
+\r
+ /* Adjust PIO debounce filter parameters, uses 10 Hz filter. */\r
+ pio_set_debounce_filter(INTN_PIO, INTN_PIN_MSK, 10);\r
+\r
+ /* Initialize PIO interrupt handlers, see PIO definition in board.h. */\r
+ pio_handler_set(INTN_PIO, INTN_ID, INTN_PIN_MSK,\r
+ INTN_ATTR, p_handler);\r
+\r
+ /* Enable NVIC interrupts. */\r
+ NVIC_SetPriority(INTN_IRQn, INT_PRIORITY_PIO);\r
+ NVIC_EnableIRQ((IRQn_Type)INTN_ID);\r
+\r
+ /* Enable PIO interrupts. */\r
+ pio_enable_interrupt(INTN_PIO, INTN_PIN_MSK);\r
+}\r
+\r
+/**\r
+ * \brief Read a register value.\r
+ *\r
+ * \param reg the register address to modify.\r
+ *\r
+ * \return the register value.\r
+ */\r
+uint16_t ksz8851_reg_read(uint16_t reg)\r
+{\r
+pdc_packet_t g_pdc_spi_tx_packet;\r
+pdc_packet_t g_pdc_spi_rx_packet;\r
+uint16_t cmd = 0;\r
+uint16_t res = 0;\r
+int iTryCount = 3;\r
+\r
+ while( iTryCount-- > 0 )\r
+ {\r
+ uint32_t ulStatus;\r
+\r
+ spi_clear_ovres();\r
+ /* Move register address to cmd bits 9-2, make 32-bit address. */\r
+ cmd = (reg << 2) & REG_ADDR_MASK;\r
+\r
+ /* Last 2 bits still under "don't care bits" handled with byte enable. */\r
+ /* Select byte enable for command. */\r
+ if (reg & 2) {\r
+ /* Odd word address writes bytes 2 and 3 */\r
+ cmd |= (0xc << 10);\r
+ } else {\r
+ /* Even word address write bytes 0 and 1 */\r
+ cmd |= (0x3 << 10);\r
+ }\r
+\r
+ /* Add command read code. */\r
+ cmd |= CMD_READ;\r
+ cmdBuf.uc[0] = cmd >> 8;\r
+ cmdBuf.uc[1] = cmd & 0xff;\r
+ cmdBuf.uc[2] = CONFIG_SPI_MASTER_DUMMY;\r
+ cmdBuf.uc[3] = CONFIG_SPI_MASTER_DUMMY;\r
+\r
+ /* Prepare PDC transfer. */\r
+ g_pdc_spi_tx_packet.ul_addr = (uint32_t) cmdBuf.uc;\r
+ g_pdc_spi_tx_packet.ul_size = 4;\r
+ g_pdc_spi_rx_packet.ul_addr = (uint32_t) tmpbuf;\r
+ g_pdc_spi_rx_packet.ul_size = 4;\r
+ pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);\r
+ pdc_tx_init(g_p_spi_pdc, &g_pdc_spi_tx_packet, NULL);\r
+ pdc_rx_init(g_p_spi_pdc, &g_pdc_spi_rx_packet, NULL);\r
+ gpio_set_pin_low(KSZ8851SNL_CSN_GPIO);\r
+\r
+ spi_disable_interrupt( KSZ8851SNL_SPI, ~0ul );\r
+ pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);\r
+ for( ;; )\r
+ {\r
+ ulStatus = spi_read_status( KSZ8851SNL_SPI );\r
+ if( ( ulStatus & ( SPI_SR_OVRES | SPI_SR_ENDRX ) ) != 0 )\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ gpio_set_pin_high( KSZ8851SNL_CSN_GPIO );\r
+ if( ( ulStatus & SPI_SR_OVRES ) == 0 )\r
+ {\r
+ break;\r
+ }\r
+ pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);\r
+ lUDPLoggingPrintf( "ksz8851_reg_read: SPI_SR_OVRES\n" );\r
+ }\r
+\r
+ res = (tmpbuf[3] << 8) | tmpbuf[2];\r
+ return res;\r
+}\r
+\r
+/**\r
+ * \brief Write a register value.\r
+ *\r
+ * \param reg the register address to modify.\r
+ * \param wrdata the new register value.\r
+ */\r
+void ksz8851_reg_write(uint16_t reg, uint16_t wrdata)\r
+{\r
+pdc_packet_t g_pdc_spi_tx_packet;\r
+pdc_packet_t g_pdc_spi_rx_packet;\r
+uint16_t cmd = 0;\r
+int iTryCount = 3;\r
+\r
+ while( iTryCount-- > 0 )\r
+ {\r
+ uint32_t ulStatus;\r
+\r
+\r
+ spi_clear_ovres();\r
+ /* Move register address to cmd bits 9-2, make 32-bit address. */\r
+ cmd = (reg << 2) & REG_ADDR_MASK;\r
+\r
+ /* Last 2 bits still under "don't care bits" handled with byte enable. */\r
+ /* Select byte enable for command. */\r
+ if (reg & 2) {\r
+ /* Odd word address writes bytes 2 and 3 */\r
+ cmd |= (0xc << 10);\r
+ } else {\r
+ /* Even word address write bytes 0 and 1 */\r
+ cmd |= (0x3 << 10);\r
+ }\r
+\r
+ /* Add command write code. */\r
+ cmd |= CMD_WRITE;\r
+ cmdBuf.uc[0] = cmd >> 8;\r
+ cmdBuf.uc[1] = cmd & 0xff;\r
+ cmdBuf.uc[2] = wrdata & 0xff;\r
+ cmdBuf.uc[3] = wrdata >> 8;\r
+\r
+ /* Prepare PDC transfer. */\r
+ g_pdc_spi_tx_packet.ul_addr = (uint32_t) cmdBuf.uc;\r
+ g_pdc_spi_tx_packet.ul_size = 4;\r
+ g_pdc_spi_rx_packet.ul_addr = (uint32_t) tmpbuf;\r
+ g_pdc_spi_rx_packet.ul_size = 4;\r
+ pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);\r
+ pdc_tx_init(g_p_spi_pdc, &g_pdc_spi_tx_packet, NULL);\r
+ pdc_rx_init(g_p_spi_pdc, &g_pdc_spi_rx_packet, NULL);\r
+ gpio_set_pin_low(KSZ8851SNL_CSN_GPIO);\r
+\r
+ spi_disable_interrupt( KSZ8851SNL_SPI, ~0ul );\r
+\r
+ pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);\r
+ for( ;; )\r
+ {\r
+ ulStatus = spi_read_status( KSZ8851SNL_SPI );\r
+ if( ( ulStatus & ( SPI_SR_OVRES | SPI_SR_ENDRX ) ) != 0 )\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ gpio_set_pin_high( KSZ8851SNL_CSN_GPIO );\r
+ if( ( ulStatus & SPI_SR_OVRES ) == 0 )\r
+ {\r
+ break;\r
+ }\r
+ pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);\r
+ lUDPLoggingPrintf( "ksz8851_reg_write: SPI_SR_OVRES\n" );\r
+ }\r
+}\r
+\r
+static void spi_clear_ovres( void )\r
+{\r
+volatile uint32_t rc;\r
+ rc = KSZ8851SNL_SPI->SPI_RDR;\r
+\r
+ spi_read_status( KSZ8851SNL_SPI );\r
+}\r
+\r
+/**\r
+ * \brief Read internal fifo buffer.\r
+ *\r
+ * \param buf the buffer to store the data from the fifo buffer.\r
+ * \param len the amount of data to read.\r
+ */\r
+void ksz8851_fifo_read(uint8_t *buf, uint32_t len)\r
+{\r
+ pdc_packet_t g_pdc_spi_tx_packet;\r
+ pdc_packet_t g_pdc_spi_rx_packet;\r
+ pdc_packet_t g_pdc_spi_tx_npacket;\r
+ pdc_packet_t g_pdc_spi_rx_npacket;\r
+\r
+ memset( cmdBuf.uc, '\0', sizeof cmdBuf );\r
+ cmdBuf.uc[0] = FIFO_READ;\r
+ spi_clear_ovres();\r
+\r
+ /* Prepare PDC transfer. */\r
+ g_pdc_spi_tx_packet.ul_addr = (uint32_t) cmdBuf.uc;\r
+ g_pdc_spi_tx_packet.ul_size = 9;\r
+ g_pdc_spi_rx_packet.ul_addr = (uint32_t) respBuf.uc;\r
+ g_pdc_spi_rx_packet.ul_size = 9;\r
+\r
+ g_pdc_spi_tx_npacket.ul_addr = (uint32_t) buf;\r
+ g_pdc_spi_tx_npacket.ul_size = len;\r
+ g_pdc_spi_rx_npacket.ul_addr = (uint32_t) buf;\r
+ g_pdc_spi_rx_npacket.ul_size = len;\r
+ pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);\r
+ pdc_tx_init(g_p_spi_pdc, &g_pdc_spi_tx_packet, &g_pdc_spi_tx_npacket);\r
+ pdc_rx_init(g_p_spi_pdc, &g_pdc_spi_rx_packet, &g_pdc_spi_rx_npacket);\r
+\r
+spi_enable_interrupt(KSZ8851SNL_SPI, SPI_IER_RXBUFF | SPI_IER_OVRES);\r
+\r
+ pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);\r
+}\r
+\r
+/**\r
+ * \brief Write internal fifo buffer.\r
+ *\r
+ * \param buf the buffer to send to the fifo buffer.\r
+ * \param ulActualLength the total amount of data to write.\r
+ * \param ulFIFOLength the size of the first pbuf to write from the pbuf chain.\r
+ */\r
+void ksz8851_fifo_write(uint8_t *buf, uint32_t ulActualLength, uint32_t ulFIFOLength)\r
+{\r
+ static uint8_t frameID = 0;\r
+\r
+ pdc_packet_t g_pdc_spi_tx_packet;\r
+ pdc_packet_t g_pdc_spi_rx_packet;\r
+ pdc_packet_t g_pdc_spi_tx_npacket;\r
+ pdc_packet_t g_pdc_spi_rx_npacket;\r
+\r
+ /* Prepare control word and byte count. */\r
+ cmdBuf.uc[0] = FIFO_WRITE;\r
+ cmdBuf.uc[1] = frameID++ & 0x3f;\r
+ cmdBuf.uc[2] = 0;\r
+ cmdBuf.uc[3] = ulActualLength & 0xff;\r
+ cmdBuf.uc[4] = ulActualLength >> 8;\r
+\r
+ spi_clear_ovres();\r
+\r
+ /* Prepare PDC transfer. */\r
+ g_pdc_spi_tx_packet.ul_addr = (uint32_t) cmdBuf.uc;\r
+ g_pdc_spi_tx_packet.ul_size = 5;\r
+\r
+ g_pdc_spi_rx_packet.ul_addr = (uint32_t) respBuf.uc;\r
+ g_pdc_spi_rx_packet.ul_size = 5;\r
+\r
+ g_pdc_spi_tx_npacket.ul_addr = (uint32_t) buf;\r
+ g_pdc_spi_tx_npacket.ul_size = ulFIFOLength;\r
+\r
+ g_pdc_spi_rx_npacket.ul_addr = (uint32_t) tmpbuf;\r
+ g_pdc_spi_rx_npacket.ul_size = ulFIFOLength;\r
+\r
+ pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);\r
+ pdc_tx_init(g_p_spi_pdc, &g_pdc_spi_tx_packet, &g_pdc_spi_tx_npacket);\r
+ #if( TX_USES_RECV == 1 )\r
+ pdc_rx_init(g_p_spi_pdc, &g_pdc_spi_rx_packet, &g_pdc_spi_rx_npacket);\r
+ spi_enable_interrupt(KSZ8851SNL_SPI, SPI_IER_ENDRX | SPI_IER_OVRES);\r
+ pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);\r
+ #else\r
+ spi_enable_interrupt(KSZ8851SNL_SPI, SPI_SR_TXBUFE | SPI_IER_OVRES);\r
+ pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_TXTEN);\r
+ #endif\r
+}\r
+\r
+/**\r
+ * \brief Write dummy data to the internal fifo buffer.\r
+ *\r
+ * \param len the amount of dummy data to write.\r
+ */\r
+void ksz8851_fifo_dummy(uint32_t len)\r
+{\r
+ pdc_packet_t g_pdc_spi_tx_packet;\r
+ pdc_packet_t g_pdc_spi_rx_packet;\r
+\r
+ /* Prepare PDC transfer. */\r
+ g_pdc_spi_tx_packet.ul_addr = (uint32_t) tmpbuf;\r
+ g_pdc_spi_tx_packet.ul_size = len;\r
+ g_pdc_spi_rx_packet.ul_addr = (uint32_t) tmpbuf;\r
+ g_pdc_spi_rx_packet.ul_size = len;\r
+ pdc_disable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);\r
+ pdc_tx_init(g_p_spi_pdc, &g_pdc_spi_tx_packet, NULL);\r
+ pdc_rx_init(g_p_spi_pdc, &g_pdc_spi_rx_packet, NULL);\r
+ pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);\r
+\r
+ while (!(spi_read_status(KSZ8851SNL_SPI) & SPI_SR_ENDRX))\r
+ ;\r
+}\r
+\r
+void ksz8851snl_set_registers(void)\r
+{\r
+ /* Init step2-4: write QMU MAC address (low, middle then high). */\r
+ ksz8851_reg_write(REG_MAC_ADDR_0, (ETHERNET_CONF_ETHADDR4 << 8) | ETHERNET_CONF_ETHADDR5);\r
+ ksz8851_reg_write(REG_MAC_ADDR_2, (ETHERNET_CONF_ETHADDR2 << 8) | ETHERNET_CONF_ETHADDR3);\r
+ ksz8851_reg_write(REG_MAC_ADDR_4, (ETHERNET_CONF_ETHADDR0 << 8) | ETHERNET_CONF_ETHADDR1);\r
+\r
+ /* Init step5: enable QMU Transmit Frame Data Pointer Auto Increment. */\r
+ ksz8851_reg_write(REG_TX_ADDR_PTR, ADDR_PTR_AUTO_INC);\r
+\r
+ /* Init step6: configure QMU transmit control register. */\r
+ ksz8851_reg_write(REG_TX_CTRL,\r
+ TX_CTRL_ICMP_CHECKSUM |\r
+ TX_CTRL_UDP_CHECKSUM |\r
+ TX_CTRL_TCP_CHECKSUM |\r
+ TX_CTRL_IP_CHECKSUM |\r
+ TX_CTRL_FLOW_ENABLE |\r
+ TX_CTRL_PAD_ENABLE |\r
+ TX_CTRL_CRC_ENABLE\r
+ );\r
+\r
+ /* Init step7: enable QMU Receive Frame Data Pointer Auto Increment. */\r
+ ksz8851_reg_write(REG_RX_ADDR_PTR, ADDR_PTR_AUTO_INC);\r
+\r
+ /* Init step8: configure QMU Receive Frame Threshold for one frame. */\r
+ ksz8851_reg_write(REG_RX_FRAME_CNT_THRES, 1);\r
+\r
+ /* Init step9: configure QMU receive control register1. */\r
+ ksz8851_reg_write(REG_RX_CTRL1,\r
+ RX_CTRL_UDP_CHECKSUM |\r
+ RX_CTRL_TCP_CHECKSUM |\r
+ RX_CTRL_IP_CHECKSUM |\r
+ RX_CTRL_MAC_FILTER |\r
+ RX_CTRL_FLOW_ENABLE |\r
+ RX_CTRL_BROADCAST |\r
+ RX_CTRL_ALL_MULTICAST|\r
+ RX_CTRL_UNICAST);\r
+// ksz8851_reg_write(REG_RX_CTRL1,\r
+// RX_CTRL_UDP_CHECKSUM |\r
+// RX_CTRL_TCP_CHECKSUM |\r
+// RX_CTRL_IP_CHECKSUM |\r
+// RX_CTRL_FLOW_ENABLE |\r
+// RX_CTRL_PROMISCUOUS);\r
+\r
+ ksz8851_reg_write(REG_RX_CTRL2,\r
+ RX_CTRL_IPV6_UDP_NOCHECKSUM |\r
+ RX_CTRL_UDP_LITE_CHECKSUM |\r
+ RX_CTRL_ICMP_CHECKSUM |\r
+ RX_CTRL_BURST_LEN_FRAME);\r
+\r
+\r
+//#define RXQ_TWOBYTE_OFFSET (0x0200) /* Enable adding 2-byte before frame header for IP aligned with DWORD */\r
+#warning Remember to try the above option to get a 2-byte offset\r
+\r
+ /* Init step11: configure QMU receive queue: trigger INT and auto-dequeue frame. */\r
+ ksz8851_reg_write( REG_RXQ_CMD, RXQ_CMD_CNTL | RXQ_TWOBYTE_OFFSET );\r
+\r
+ /* Init step12: adjust SPI data output delay. */\r
+ ksz8851_reg_write(REG_BUS_CLOCK_CTRL, BUS_CLOCK_166 | BUS_CLOCK_DIVIDEDBY_1);\r
+\r
+ /* Init step13: restart auto-negotiation. */\r
+ ksz8851_reg_setbits(REG_PORT_CTRL, PORT_AUTO_NEG_RESTART);\r
+\r
+ /* Init step13.1: force link in half duplex if auto-negotiation failed. */\r
+ if ((ksz8851_reg_read(REG_PORT_CTRL) & PORT_AUTO_NEG_RESTART) != PORT_AUTO_NEG_RESTART)\r
+ {\r
+ ksz8851_reg_clrbits(REG_PORT_CTRL, PORT_FORCE_FULL_DUPLEX);\r
+ }\r
+\r
+ /* Init step14: clear interrupt status. */\r
+ ksz8851_reg_write(REG_INT_STATUS, 0xFFFF);\r
+\r
+ /* Init step15: set interrupt mask. */\r
+ ksz8851_reg_write(REG_INT_MASK, INT_RX);\r
+\r
+ /* Init step16: enable QMU Transmit. */\r
+ ksz8851_reg_setbits(REG_TX_CTRL, TX_CTRL_ENABLE);\r
+\r
+ /* Init step17: enable QMU Receive. */\r
+ ksz8851_reg_setbits(REG_RX_CTRL1, RX_CTRL_ENABLE);\r
+}\r
+/**\r
+ * \brief KSZ8851SNL initialization function.\r
+ *\r
+ * \return 0 on success, 1 on communication error.\r
+ */\r
+uint32_t ksz8851snl_init(void)\r
+{\r
+uint32_t count = 10;\r
+uint16_t dev_id = 0;\r
+uint8_t id_ok = 0;\r
+\r
+ /* Configure the SPI peripheral. */\r
+ spi_enable_clock(KSZ8851SNL_SPI);\r
+ spi_disable(KSZ8851SNL_SPI);\r
+ spi_reset(KSZ8851SNL_SPI);\r
+ spi_set_master_mode(KSZ8851SNL_SPI);\r
+ spi_disable_mode_fault_detect(KSZ8851SNL_SPI);\r
+ spi_set_peripheral_chip_select_value(KSZ8851SNL_SPI, ~(uint32_t)(1UL << KSZ8851SNL_CS_PIN));\r
+spi_set_fixed_peripheral_select(KSZ8851SNL_SPI);\r
+//spi_disable_peripheral_select_decode(KSZ8851SNL_SPI);\r
+\r
+ spi_set_clock_polarity(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_POLARITY);\r
+ spi_set_clock_phase(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_PHASE);\r
+ spi_set_bits_per_transfer(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN,\r
+ SPI_CSR_BITS_8_BIT);\r
+ spi_set_baudrate_div(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, (sysclk_get_cpu_hz() / KSZ8851SNL_CLOCK_SPEED));\r
+// spi_set_transfer_delay(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, CONFIG_SPI_MASTER_DELAY_BS,\r
+// CONFIG_SPI_MASTER_DELAY_BCT);\r
+\r
+\r
+ spi_set_transfer_delay(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, 0, 0);\r
+\r
+ spi_enable(KSZ8851SNL_SPI);\r
+\r
+ /* Get pointer to UART PDC register base. */\r
+ g_p_spi_pdc = spi_get_pdc_base(KSZ8851SNL_SPI);\r
+ pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);\r
+\r
+ /* Control RSTN and CSN pin from the driver. */\r
+ gpio_configure_pin(KSZ8851SNL_CSN_GPIO, KSZ8851SNL_CSN_FLAGS);\r
+ gpio_set_pin_high(KSZ8851SNL_CSN_GPIO);\r
+ gpio_configure_pin(KSZ8851SNL_RSTN_GPIO, KSZ8851SNL_RSTN_FLAGS);\r
+\r
+ /* Reset the Micrel in a proper state. */\r
+ while( count-- )\r
+ {\r
+ /* Perform hardware reset with respect to the reset timing from the datasheet. */\r
+ gpio_set_pin_low(KSZ8851SNL_RSTN_GPIO);\r
+ vTaskDelay(2);\r
+ gpio_set_pin_high(KSZ8851SNL_RSTN_GPIO);\r
+ vTaskDelay(2);\r
+\r
+ /* Init step1: read chip ID. */\r
+ dev_id = ksz8851_reg_read(REG_CHIP_ID);\r
+ if( ( dev_id & 0xFFF0 ) == CHIP_ID_8851_16 )\r
+ {\r
+ id_ok = 1;\r
+ break;\r
+ }\r
+ }\r
+ if( id_ok != 0 )\r
+ {\r
+ ksz8851snl_set_registers();\r
+ }\r
+\r
+ return id_ok ? 1 : -1;\r
+}\r
+\r
+uint32_t ksz8851snl_reinit(void)\r
+{\r
+uint32_t count = 10;\r
+uint16_t dev_id = 0;\r
+uint8_t id_ok = 0;\r
+ /* Reset the Micrel in a proper state. */\r
+ while( count-- )\r
+ {\r
+ /* Perform hardware reset with respect to the reset timing from the datasheet. */\r
+ gpio_set_pin_low(KSZ8851SNL_RSTN_GPIO);\r
+ vTaskDelay(2);\r
+ gpio_set_pin_high(KSZ8851SNL_RSTN_GPIO);\r
+ vTaskDelay(2);\r
+\r
+ /* Init step1: read chip ID. */\r
+ dev_id = ksz8851_reg_read(REG_CHIP_ID);\r
+ if( ( dev_id & 0xFFF0 ) == CHIP_ID_8851_16 )\r
+ {\r
+ id_ok = 1;\r
+ break;\r
+ }\r
+ }\r
+ if( id_ok != 0 )\r
+ {\r
+ ksz8851snl_set_registers();\r
+ }\r
+\r
+ return id_ok ? 1 : -1;\r
+}\r
+\r
+uint32_t ksz8851snl_reset_rx( void )\r
+{\r
+uint16_t usValue;\r
+\r
+ usValue = ksz8851_reg_read(REG_RX_CTRL1);\r
+\r
+ usValue &= ~( ( uint16_t ) RX_CTRL_ENABLE | RX_CTRL_FLUSH_QUEUE );\r
+\r
+ ksz8851_reg_write( REG_RX_CTRL1, usValue ); vTaskDelay( 2 );\r
+ ksz8851_reg_write( REG_RX_CTRL1, usValue | RX_CTRL_FLUSH_QUEUE ); vTaskDelay( 1 );\r
+ ksz8851_reg_write( REG_RX_CTRL1, usValue ); vTaskDelay( 1 );\r
+ ksz8851_reg_write( REG_RX_CTRL1, usValue | RX_CTRL_ENABLE ); vTaskDelay( 1 );\r
+\r
+ return ( uint32_t )usValue;\r
+}\r
+\r
+uint32_t ksz8851snl_reset_tx( void )\r
+{\r
+uint16_t usValue;\r
+\r
+ usValue = ksz8851_reg_read( REG_TX_CTRL );\r
+\r
+ usValue &= ~( ( uint16_t ) TX_CTRL_ENABLE | TX_CTRL_FLUSH_QUEUE );\r
+\r
+ ksz8851_reg_write( REG_TX_CTRL, usValue ); vTaskDelay( 2 );\r
+ ksz8851_reg_write( REG_TX_CTRL, usValue | TX_CTRL_FLUSH_QUEUE ); vTaskDelay( 1 );\r
+ ksz8851_reg_write( REG_TX_CTRL, usValue ); vTaskDelay( 1 );\r
+ ksz8851_reg_write( REG_TX_CTRL, usValue | TX_CTRL_ENABLE ); vTaskDelay( 1 );\r
+\r
+ return ( uint32_t )usValue;\r
+}\r
--- /dev/null
+/**\r
+ *\r
+ * \file\r
+ *\r
+ * \brief KS8851SNL driver for SAM.\r
+ *\r
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+#ifndef KSZ8851SNL_H_INCLUDED\r
+#define KSZ8851SNL_H_INCLUDED\r
+\r
+#include "gpio.h"\r
+\r
+void configure_intn(void (*p_handler) (uint32_t, uint32_t));\r
+void ksz8851_reg_setbits(uint16_t reg, uint16_t bits_to_set);\r
+void ksz8851_reg_clrbits(uint16_t reg, uint16_t bits_to_clr);\r
+void ksz8851_fifo_read(uint8_t *buf, uint32_t len);\r
+void ksz8851_fifo_write(uint8_t *buf, uint32_t ulActualLength, uint32_t ulFIFOLength);\r
+void ksz8851_fifo_dummy(uint32_t len);\r
+void ksz8851_reg_write(uint16_t reg, uint16_t wrdata);\r
+uint16_t ksz8851_reg_read(uint16_t reg);\r
+uint32_t ksz8851snl_init(void);\r
+uint32_t ksz8851snl_reinit(void);\r
+\r
+uint32_t ksz8851snl_reset_rx( void );\r
+uint32_t ksz8851snl_reset_tx( void );\r
+\r
+#endif /* KSZ8851SNL_H_INCLUDED */\r
--- /dev/null
+/**\r
+ *\r
+ * \file\r
+ *\r
+ * \brief KS8851SNL registers definitions.\r
+ *\r
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+/*\r
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>\r
+ */\r
+\r
+#ifndef KSZ8851SNL_REG_H_INCLUDED\r
+#define KSZ8851SNL_REG_H_INCLUDED\r
+\r
+#define REG_ADDR_MASK (0x3F0) /* Register address mask */\r
+#define OPCODE_MASK (3 << 14)\r
+#define CMD_READ (0 << 14)\r
+#define CMD_WRITE (1 << 14)\r
+#define FIFO_READ (0x80)\r
+#define FIFO_WRITE (0xC0)\r
+\r
+/*\r
+ * MAC Registers\r
+ * (Offset 0x00 - 0x25)\r
+ */\r
+#define REG_BUS_ERROR_STATUS (0x06) /* BESR */\r
+#define BUS_ERROR_IBEC (0x8000)\r
+#define BUS_ERROR_IBECV_MASK (0x7800) /* Default IPSec clock at 166Mhz */\r
+\r
+#define REG_CHIP_CFG_STATUS (0x08) /* CCFG */\r
+#define LITTLE_ENDIAN_BUS_MODE (0x0400) /* Bus in little endian mode */\r
+#define EEPROM_PRESENCE (0x0200) /* External EEPROM is used */\r
+#define SPI_BUS_MODE (0x0100) /* In SPI bus mode */\r
+#define DATA_BUS_8BIT (0x0080) /* In 8-bit bus mode operation */\r
+#define DATA_BUS_16BIT (0x0040) /* In 16-bit bus mode operation */\r
+#define DATA_BUS_32BIT (0x0020) /* In 32-bit bus mode operation */\r
+#define MULTIPLEX_MODE (0x0010) /* Data and address bus are shared */\r
+#define CHIP_PACKAGE_128PIN (0x0008) /* 128-pin package */\r
+#define CHIP_PACKAGE_80PIN (0x0004) /* 80-pin package */\r
+#define CHIP_PACKAGE_48PIN (0x0002) /* 48-pin package */\r
+#define CHIP_PACKAGE_32PIN (0x0001) /* 32-pin package for SPI host interface only */\r
+\r
+#define REG_MAC_ADDR_0 (0x10) /* MARL */\r
+#define REG_MAC_ADDR_1 (0x11) /* MARL */\r
+#define REG_MAC_ADDR_2 (0x12) /* MARM */\r
+#define REG_MAC_ADDR_3 (0x13) /* MARM */\r
+#define REG_MAC_ADDR_4 (0x14) /* MARH */\r
+#define REG_MAC_ADDR_5 (0x15) /* MARH */\r
+\r
+#define REG_BUS_CLOCK_CTRL (0x20) /* OBCR */\r
+#define BUS_CLOCK_166 (0x0004) /* 166 MHz on-chip bus clock (defaul is 125MHz) */\r
+#define BUS_CLOCK_DIVIDEDBY_5 (0x0003) /* Bus clock devided by 5 */\r
+#define BUS_CLOCK_DIVIDEDBY_3 (0x0002) /* Bus clock devided by 3 */\r
+#define BUS_CLOCK_DIVIDEDBY_2 (0x0001) /* Bus clock devided by 2 */\r
+#define BUS_CLOCK_DIVIDEDBY_1 (0x0000) /* Bus clock devided by 1 */\r
+#define BUS_CLOCK_DIVIDED_MASK (0x0003) /* Bus clock devider mask */\r
+\r
+#define BUS_SPEED_166_MHZ (0x0004) /* Set bus speed to 166 MHz */\r
+#define BUS_SPEED_125_MHZ (0x0000) /* Set bus speed to 125 MHz */\r
+#define BUS_SPEED_83_MHZ (0x0005) /* Set bus speed to 83 MHz (166/2)*/\r
+#define BUS_SPEED_62_5_MHZ (0x0001) /* Set bus speed to 62.5 MHz (125/2) */\r
+#define BUS_SPEED_53_3_MHZ (0x0006) /* Set bus speed to 53.3 MHz (166/3) */\r
+#define BUS_SPEED_41_7_MHZ (0x0002) /* Set bus speed to 41.67 MHz (125/3) */\r
+#define BUS_SPEED_33_2_MHZ (0x0007) /* Set bus speed to 33.2 MHz (166/5) */\r
+#define BUS_SPEED_25_MHZ (0x0003) /* Set bus speed to 25 MHz (125/5) */\r
+\r
+#define REG_EEPROM_CTRL (0x22) /* EEPCR */\r
+#define EEPROM_ACCESS_ENABLE (0x0010) /* Enable software to access EEPROM through bit 3 to bit 0 */\r
+#define EEPROM_DATA_IN (0x0008) /* Data receive from EEPROM (EEDI pin) */\r
+#define EEPROM_DATA_OUT (0x0004) /* Data transmit to EEPROM (EEDO pin) */\r
+#define EEPROM_SERIAL_CLOCK (0x0002) /* Serial clock (EESK pin) */\r
+#define EEPROM_CHIP_SELECT (0x0001) /* EEPROM chip select (EECS pin) */\r
+\r
+#define REG_MEM_BIST_INFO (0x24) /* MBIR */\r
+#define TX_MEM_TEST_FINISHED (0x1000) /* TX memeory BIST test finish */\r
+#define TX_MEM_TEST_FAILED (0x0800) /* TX memory BIST test fail */\r
+#define TX_MEM_TEST_FAILED_COUNT (0x0700) /* TX memory BIST test fail count */\r
+#define RX_MEM_TEST_FINISHED (0x0010) /* RX memory BIST test finish */\r
+#define RX_MEM_TEST_FAILED (0x0008) /* RX memory BIST test fail */\r
+#define RX_MEM_TEST_FAILED_COUNT (0x0003) /* RX memory BIST test fail count */\r
+\r
+#define REG_RESET_CTRL (0x26) /* GRR */\r
+#define QMU_SOFTWARE_RESET (0x0002) /* QMU soft reset (clear TxQ, RxQ) */\r
+#define GLOBAL_SOFTWARE_RESET (0x0001) /* Global soft reset (PHY, MAC, QMU) */\r
+\r
+/*\r
+ * Wake On Lan Control Registers\r
+ * (Offset 0x2A - 0x6B)\r
+ */\r
+#define REG_WOL_CTRL (0x2A) /* WFCR */\r
+#define WOL_MAGIC_ENABLE (0x0080) /* Enable the magic packet pattern detection */\r
+#define WOL_FRAME3_ENABLE (0x0008) /* Enable the wake up frame 3 pattern detection */\r
+#define WOL_FRAME2_ENABLE (0x0004) /* Enable the wake up frame 2 pattern detection */\r
+#define WOL_FRAME1_ENABLE (0x0002) /* Enable the wake up frame 1 pattern detection */\r
+#define WOL_FRAME0_ENABLE (0x0001) /* Enable the wake up frame 0 pattern detection */\r
+\r
+#define REG_WOL_FRAME0_CRC0 (0x30) /* WF0CRC0 */\r
+#define REG_WOL_FRAME0_CRC1 (0x32) /* WF0CRC1 */\r
+#define REG_WOL_FRAME0_BYTE_MASK0 (0x34) /* WF0BM0 */\r
+#define REG_WOL_FRAME0_BYTE_MASK1 (0x36) /* WF0BM1 */\r
+#define REG_WOL_FRAME0_BYTE_MASK2 (0x38) /* WF0BM2 */\r
+#define REG_WOL_FRAME0_BYTE_MASK3 (0x3A) /* WF0BM3 */\r
+\r
+#define REG_WOL_FRAME1_CRC0 (0x40) /* WF1CRC0 */\r
+#define REG_WOL_FRAME1_CRC1 (0x42) /* WF1CRC1 */\r
+#define REG_WOL_FRAME1_BYTE_MASK0 (0x44) /* WF1BM0 */\r
+#define REG_WOL_FRAME1_BYTE_MASK1 (0x46) /* WF1BM1 */\r
+#define REG_WOL_FRAME1_BYTE_MASK2 (0x48) /* WF1BM2 */\r
+#define REG_WOL_FRAME1_BYTE_MASK3 (0x4A) /* WF1BM3 */\r
+\r
+#define REG_WOL_FRAME2_CRC0 (0x50) /* WF2CRC0 */\r
+#define REG_WOL_FRAME2_CRC1 (0x52) /* WF2CRC1 */\r
+#define REG_WOL_FRAME2_BYTE_MASK0 (0x54) /* WF2BM0 */\r
+#define REG_WOL_FRAME2_BYTE_MASK1 (0x56) /* WF2BM1 */\r
+#define REG_WOL_FRAME2_BYTE_MASK2 (0x58) /* WF2BM2 */\r
+#define REG_WOL_FRAME2_BYTE_MASK3 (0x5A) /* WF2BM3 */\r
+\r
+#define REG_WOL_FRAME3_CRC0 (0x60) /* WF3CRC0 */\r
+#define REG_WOL_FRAME3_CRC1 (0x62) /* WF3CRC1 */\r
+#define REG_WOL_FRAME3_BYTE_MASK0 (0x64) /* WF3BM0 */\r
+#define REG_WOL_FRAME3_BYTE_MASK1 (0x66) /* WF3BM1 */\r
+#define REG_WOL_FRAME3_BYTE_MASK2 (0x68) /* WF3BM2 */\r
+#define REG_WOL_FRAME3_BYTE_MASK3 (0x6A) /* WF3BM3 */\r
+\r
+/*\r
+ * Transmit/Receive Control Registers\r
+ * (Offset 0x70 - 0x9F)\r
+ */\r
+\r
+/* Transmit Frame Header */\r
+#define REG_QDR_DUMMY (0x00) /* Dummy address to access QMU RxQ, TxQ */\r
+#define TX_CTRL_INTERRUPT_ON (0x8000) /* Transmit Interrupt on Completion */\r
+\r
+#define REG_TX_CTRL (0x70) /* TXCR */\r
+#define TX_CTRL_ICMP_CHECKSUM (0x0100) /* Enable ICMP frame checksum generation */\r
+#define TX_CTRL_UDP_CHECKSUM (0x0080) /* Enable UDP frame checksum generation */\r
+#define TX_CTRL_TCP_CHECKSUM (0x0040) /* Enable TCP frame checksum generation */\r
+#define TX_CTRL_IP_CHECKSUM (0x0020) /* Enable IP frame checksum generation */\r
+#define TX_CTRL_FLUSH_QUEUE (0x0010) /* Clear transmit queue, reset tx frame pointer */\r
+#define TX_CTRL_FLOW_ENABLE (0x0008) /* Enable transmit flow control */\r
+#define TX_CTRL_PAD_ENABLE (0x0004) /* Eanble adding a padding to a packet shorter than 64 bytes */\r
+#define TX_CTRL_CRC_ENABLE (0x0002) /* Enable adding a CRC to the end of transmit frame */\r
+#define TX_CTRL_ENABLE (0x0001) /* Enable tranmsit */\r
+\r
+#define REG_TX_STATUS (0x72) /* TXSR */\r
+#define TX_STAT_LATE_COL (0x2000) /* Tranmsit late collision occurs */\r
+#define TX_STAT_MAX_COL (0x1000) /* Tranmsit maximum collision is reached */\r
+#define TX_FRAME_ID_MASK (0x003F) /* Transmit frame ID mask */\r
+#define TX_STAT_ERRORS ( TX_STAT_MAX_COL | TX_STAT_LATE_COL )\r
+\r
+#define REG_RX_CTRL1 (0x74) /* RXCR1 */\r
+#define RX_CTRL_FLUSH_QUEUE (0x8000) /* Clear receive queue, reset rx frame pointer */\r
+#define RX_CTRL_UDP_CHECKSUM (0x4000) /* Enable UDP frame checksum verification */\r
+#define RX_CTRL_TCP_CHECKSUM (0x2000) /* Enable TCP frame checksum verification */\r
+#define RX_CTRL_IP_CHECKSUM (0x1000) /* Enable IP frame checksum verification */\r
+#define RX_CTRL_MAC_FILTER (0x0800) /* Receive with address that pass MAC address filtering */\r
+#define RX_CTRL_FLOW_ENABLE (0x0400) /* Enable receive flow control */\r
+#define RX_CTRL_BAD_PACKET (0x0200) /* Eanble receive CRC error frames */\r
+#define RX_CTRL_MULTICAST (0x0100) /* Receive multicast frames that pass the CRC hash filtering */\r
+#define RX_CTRL_BROADCAST (0x0080) /* Receive all the broadcast frames */\r
+#define RX_CTRL_ALL_MULTICAST (0x0040) /* Receive all the multicast frames (including broadcast frames) */\r
+#define RX_CTRL_UNICAST (0x0020) /* Receive unicast frames that match the device MAC address */\r
+#define RX_CTRL_PROMISCUOUS (0x0010) /* Receive all incoming frames, regardless of frame's DA */\r
+#define RX_CTRL_STRIP_CRC (0x0008) /* Enable strip CRC on the received frames */\r
+#define RX_CTRL_INVERSE_FILTER (0x0002) /* Receive with address check in inverse filtering mode */\r
+#define RX_CTRL_ENABLE (0x0001) /* Enable receive */\r
+\r
+/* Address filtering scheme mask */\r
+#define RX_CTRL_FILTER_MASK ( RX_CTRL_INVERSE_FILTER | RX_CTRL_PROMISCUOUS | RX_CTRL_MULTICAST | RX_CTRL_MAC_FILTER )\r
+\r
+#define REG_RX_CTRL2 (0x76) /* RXCR2 */\r
+#define RX_CTRL_IPV6_UDP_NOCHECKSUM (0x0010) /* No checksum generation and verification if IPv6 UDP is fragment */\r
+#define RX_CTRL_IPV6_UDP_CHECKSUM (0x0008) /* Receive pass IPv6 UDP frame with UDP checksum is zero */\r
+#define RX_CTRL_UDP_LITE_CHECKSUM (0x0004) /* Enable UDP Lite frame checksum generation and verification */\r
+#define RX_CTRL_ICMP_CHECKSUM (0x0002) /* Enable ICMP frame checksum verification */\r
+#define RX_CTRL_BLOCK_MAC (0x0001) /* Receive drop frame if the SA is same as device MAC address */\r
+#define RX_CTRL_BURST_LEN_MASK (0x00e0) /* SRDBL SPI Receive Data Burst Length */\r
+#define RX_CTRL_BURST_LEN_4 (0x0000)\r
+#define RX_CTRL_BURST_LEN_8 (0x0020)\r
+#define RX_CTRL_BURST_LEN_16 (0x0040)\r
+#define RX_CTRL_BURST_LEN_32 (0x0060)\r
+#define RX_CTRL_BURST_LEN_FRAME (0x0080)\r
+\r
+#define REG_TX_MEM_INFO (0x78) /* TXMIR */\r
+#define TX_MEM_AVAILABLE_MASK (0x1FFF) /* The amount of memory available in TXQ */\r
+\r
+#define REG_RX_FHR_STATUS (0x7C) /* RXFHSR */\r
+#define RX_VALID (0x8000) /* Frame in the receive packet memory is valid */\r
+#define RX_ICMP_ERROR (0x2000) /* ICMP checksum field doesn't match */\r
+#define RX_IP_ERROR (0x1000) /* IP checksum field doesn't match */\r
+#define RX_TCP_ERROR (0x0800) /* TCP checksum field doesn't match */\r
+#define RX_UDP_ERROR (0x0400) /* UDP checksum field doesn't match */\r
+#define RX_BROADCAST (0x0080) /* Received frame is a broadcast frame */\r
+#define RX_MULTICAST (0x0040) /* Received frame is a multicast frame */\r
+#define RX_UNICAST (0x0020) /* Received frame is a unicast frame */\r
+#define RX_PHY_ERROR (0x0010) /* Received frame has runt error */\r
+#define RX_FRAME_ETHER (0x0008) /* Received frame is an Ethernet-type frame */\r
+#define RX_TOO_LONG (0x0004) /* Received frame length exceeds max size 0f 2048 bytes */\r
+#define RX_RUNT_ERROR (0x0002) /* Received frame was demaged by a collision */\r
+#define RX_BAD_CRC (0x0001) /* Received frame has a CRC error */\r
+#define RX_ERRORS ( RX_BAD_CRC | RX_TOO_LONG | RX_RUNT_ERROR | RX_PHY_ERROR | \\r
+ RX_ICMP_ERROR | RX_IP_ERROR | RX_TCP_ERROR | RX_UDP_ERROR )\r
+\r
+#define REG_RX_FHR_BYTE_CNT (0x7E) /* RXFHBCR */\r
+#define RX_BYTE_CNT_MASK (0x0FFF) /* Received frame byte size mask */\r
+\r
+#define REG_TXQ_CMD (0x80) /* TXQCR */\r
+#define TXQ_AUTO_ENQUEUE (0x0004) /* Enable enqueue tx frames from tx buffer automatically */\r
+#define TXQ_MEM_AVAILABLE_INT (0x0002) /* Enable generate interrupt when tx memory is available */\r
+#define TXQ_ENQUEUE (0x0001) /* Enable enqueue tx frames one frame at a time */\r
+\r
+#define REG_RXQ_CMD (0x82) /* RXQCR */\r
+#define RXQ_STAT_TIME_INT (0x1000) /* RX interrupt is occured by timer duration */\r
+#define RXQ_STAT_BYTE_CNT_INT (0x0800) /* RX interrupt is occured by byte count threshold */\r
+#define RXQ_STAT_FRAME_CNT_INT (0x0400) /* RX interrupt is occured by frame count threshold */\r
+#define RXQ_TWOBYTE_OFFSET (0x0200) /* Enable adding 2-byte before frame header for IP aligned with DWORD */\r
+#define RXQ_TIME_INT (0x0080) /* Enable RX interrupt by timer duration */\r
+#define RXQ_BYTE_CNT_INT (0x0040) /* Enable RX interrupt by byte count threshold */\r
+#define RXQ_FRAME_CNT_INT (0x0020) /* Enable RX interrupt by frame count threshold */\r
+#define RXQ_AUTO_DEQUEUE (0x0010) /* Enable release rx frames from rx buffer automatically */\r
+#define RXQ_START (0x0008) /* Start QMU transfer operation */\r
+#define RXQ_CMD_FREE_PACKET (0x0001) /* Manual dequeue (release the current frame from RxQ) */\r
+\r
+#define RXQ_CMD_CNTL (RXQ_FRAME_CNT_INT|RXQ_AUTO_DEQUEUE)\r
+\r
+#define REG_TX_ADDR_PTR (0x84) /* TXFDPR */\r
+#define REG_RX_ADDR_PTR (0x86) /* RXFDPR */\r
+#define ADDR_PTR_AUTO_INC (0x4000) /* Enable Frame data pointer increments automatically */\r
+#define ADDR_PTR_MASK (0x03ff) /* Address pointer mask */\r
+\r
+#define REG_RX_TIME_THRES (0x8C) /* RXDTTR */\r
+#define RX_TIME_THRESHOLD_MASK (0xFFFF) /* Set receive timer duration threshold */\r
+\r
+#define REG_RX_BYTE_CNT_THRES (0x8E) /* RXDBCTR */\r
+#define RX_BYTE_THRESHOLD_MASK (0xFFFF) /* Set receive byte count threshold */\r
+\r
+#define REG_INT_MASK (0x90) /* IER */\r
+#define INT_PHY (0x8000) /* Enable link change interrupt */\r
+#define INT_TX (0x4000) /* Enable transmit done interrupt */\r
+#define INT_RX (0x2000) /* Enable receive interrupt */\r
+#define INT_RX_OVERRUN (0x0800) /* Enable receive overrun interrupt */\r
+#define INT_TX_STOPPED (0x0200) /* Enable transmit process stopped interrupt */\r
+#define INT_RX_STOPPED (0x0100) /* Enable receive process stopped interrupt */\r
+#define INT_TX_SPACE (0x0040) /* Enable transmit space available interrupt */\r
+#define INT_RX_WOL_FRAME (0x0020) /* Enable WOL on receive wake-up frame detect interrupt */\r
+#define INT_RX_WOL_MAGIC (0x0010) /* Enable WOL on receive magic packet detect interrupt */\r
+#define INT_RX_WOL_LINKUP (0x0008) /* Enable WOL on link up detect interrupt */\r
+#define INT_RX_WOL_ENERGY (0x0004) /* Enable WOL on energy detect interrupt */\r
+#define INT_RX_SPI_ERROR (0x0002) /* Enable receive SPI bus error interrupt */\r
+#define INT_RX_WOL_DELAY_ENERGY (0x0001) /* Enable WOL on delay energy detect interrupt */\r
+#define INT_MASK ( INT_RX | INT_TX | INT_PHY )\r
+\r
+#define REG_INT_STATUS (0x92) /* ISR */\r
+\r
+#define REG_RX_FRAME_CNT_THRES (0x9C) /* RXFCTFC */\r
+#define RX_FRAME_CNT_MASK (0xFF00) /* Received frame count mask */\r
+#define RX_FRAME_THRESHOLD_MASK (0x00FF) /* Set receive frame count threshold mask */\r
+\r
+#define REG_TX_TOTAL_FRAME_SIZE (0x9E) /* TXNTFSR */\r
+#define TX_TOTAL_FRAME_SIZE_MASK (0xFFFF) /* Set next total tx frame size mask */\r
+\r
+/*\r
+ * MAC Address Hash Table Control Registers\r
+ * (Offset 0xA0 - 0xA7)\r
+ */\r
+#define REG_MAC_HASH_0 (0xA0) /* MAHTR0 */\r
+#define REG_MAC_HASH_1 (0xA1)\r
+\r
+#define REG_MAC_HASH_2 (0xA2) /* MAHTR1 */\r
+#define REG_MAC_HASH_3 (0xA3)\r
+\r
+#define REG_MAC_HASH_4 (0xA4) /* MAHTR2 */\r
+#define REG_MAC_HASH_5 (0xA5)\r
+\r
+#define REG_MAC_HASH_6 (0xA6) /* MAHTR3 */\r
+#define REG_MAC_HASH_7 (0xA7)\r
+\r
+/*\r
+ * QMU Receive Queue Watermark Control Registers\r
+ * (Offset 0xB0 - 0xB5)\r
+ */\r
+#define REG_RX_LOW_WATERMARK (0xB0) /* FCLWR */\r
+#define RX_LOW_WATERMARK_MASK (0x0FFF) /* Set QMU RxQ low watermark mask */\r
+\r
+#define REG_RX_HIGH_WATERMARK (0xB2) /* FCHWR */\r
+#define RX_HIGH_WATERMARK_MASK (0x0FFF) /* Set QMU RxQ high watermark mask */\r
+\r
+#define REG_RX_OVERRUN_WATERMARK (0xB4) /* FCOWR */\r
+#define RX_OVERRUN_WATERMARK_MASK (0x0FFF) /* Set QMU RxQ overrun watermark mask */\r
+\r
+/*\r
+ * Global Control Registers\r
+ * (Offset 0xC0 - 0xD3)\r
+ */\r
+#define REG_CHIP_ID (0xC0) /* CIDER */\r
+#define CHIP_ID_MASK (0xFFF0) /* Family ID and chip ID mask */\r
+#define REVISION_MASK (0x000E) /* Chip revision mask */\r
+#define CHIP_ID_SHIFT (4)\r
+#define REVISION_SHIFT (1)\r
+#define CHIP_ID_8851_16 (0x8870) /* KS8851-16/32MQL chip ID */\r
+\r
+#define REG_LED_CTRL (0xC6) /* CGCR */\r
+#define LED_CTRL_SEL1 (0x8000) /* Select LED3/LED2/LED1/LED0 indication */\r
+#define LED_CTRL_SEL0 (0x0200) /* Select LED3/LED2/LED1/LED0 indication */\r
+\r
+#define REG_IND_IACR (0xC8) /* IACR */\r
+#define TABLE_READ (0x1000) /* Indirect read */\r
+#define TABLE_MIB (0x0C00) /* Select MIB counter table */\r
+#define TABLE_ENTRY_MASK (0x001F) /* Set table entry to access */\r
+\r
+#define REG_IND_DATA_LOW (0xD0) /* IADLR */\r
+#define REG_IND_DATA_HIGH (0xD2) /* IADHR */\r
+\r
+/*\r
+ * Power Management Control Registers\r
+ * (Offset 0xD4 - 0xD7)\r
+ */\r
+#define REG_POWER_CNTL (0xD4) /* PMECR */\r
+#define PME_DELAY_ENABLE (0x4000) /* Enable the PME output pin assertion delay */\r
+#define PME_ACTIVE_HIGHT (0x1000) /* PME output pin is active high */\r
+#define PME_FROM_WKFRAME (0x0800) /* PME asserted when wake-up frame is detected */\r
+#define PME_FROM_MAGIC (0x0400) /* PME asserted when magic packet is detected */\r
+#define PME_FROM_LINKUP (0x0200) /* PME asserted when link up is detected */\r
+#define PME_FROM_ENERGY (0x0100) /* PME asserted when energy is detected */\r
+#define PME_EVENT_MASK (0x0F00) /* PME asserted event mask */\r
+#define WAKEUP_AUTO_ENABLE (0x0080) /* Enable auto wake-up in energy mode */\r
+#define WAKEUP_NORMAL_AUTO_ENABLE (0x0040) /* Enable auto goto normal mode from energy detecion mode */\r
+#define WAKEUP_FROM_WKFRAME (0x0020) /* Wake-up from wake-up frame event detected */\r
+#define WAKEUP_FROM_MAGIC (0x0010) /* Wake-up from magic packet event detected */\r
+#define WAKEUP_FROM_LINKUP (0x0008) /* Wake-up from link up event detected */\r
+#define WAKEUP_FROM_ENERGY (0x0004) /* Wake-up from energy event detected */\r
+#define WAKEUP_EVENT_MASK (0x003C) /* Wake-up event mask */\r
+#define POWER_STATE_D1 (0x0003) /* Power saving mode */\r
+#define POWER_STATE_D3 (0x0002) /* Power down mode */\r
+#define POWER_STATE_D2 (0x0001) /* Power detection mode */\r
+#define POWER_STATE_D0 (0x0000) /* Normal operation mode (default) */\r
+#define POWER_STATE_MASK (0x0003) /* Power management mode mask */\r
+\r
+#define REG_WAKEUP_TIME (0xD6) /* GSWUTR */\r
+#define WAKEUP_TIME (0xFF00) /* Min time (sec) wake-uo after detected energy */\r
+#define GOSLEEP_TIME (0x00FF) /* Min time (sec) before goto sleep when in energy mode */\r
+\r
+/*\r
+ * PHY Control Registers\r
+ * (Offset 0xD8 - 0xF9)\r
+ */\r
+#define REG_PHY_RESET (0xD8) /* PHYRR */\r
+#define PHY_RESET (0x0001) /* Reset PHY */\r
+\r
+#define REG_PHY_CNTL (0xE4) /* P1MBCR */\r
+#define PHY_SPEED_100MBIT (0x2000) /* Force PHY 100Mbps */\r
+#define PHY_AUTO_NEG_ENABLE (0x1000) /* Enable PHY auto-negotiation */\r
+#define PHY_POWER_DOWN (0x0800) /* Set PHY power-down */\r
+#define PHY_AUTO_NEG_RESTART (0x0200) /* Restart PHY auto-negotiation */\r
+#define PHY_FULL_DUPLEX (0x0100) /* Force PHY in full duplex mode */\r
+#define PHY_HP_MDIX (0x0020) /* Set PHY in HP auto MDI-X mode */\r
+#define PHY_FORCE_MDIX (0x0010) /* Force MDI-X */\r
+#define PHY_AUTO_MDIX_DISABLE (0x0008) /* Disable auto MDI-X */\r
+#define PHY_TRANSMIT_DISABLE (0x0002) /* Disable PHY transmit */\r
+#define PHY_LED_DISABLE (0x0001) /* Disable PHY LED */\r
+\r
+#define REG_PHY_STATUS (0xE6) /* P1MBSR */\r
+#define PHY_100BT4_CAPABLE (0x8000) /* 100 BASE-T4 capable */\r
+#define PHY_100BTX_FD_CAPABLE (0x4000) /* 100BASE-TX full duplex capable */\r
+#define PHY_100BTX_CAPABLE (0x2000) /* 100BASE-TX half duplex capable */\r
+#define PHY_10BT_FD_CAPABLE (0x1000) /* 10BASE-TX full duplex capable */\r
+#define PHY_10BT_CAPABLE (0x0800) /* 10BASE-TX half duplex capable */\r
+#define PHY_AUTO_NEG_ACKNOWLEDGE (0x0020) /* Auto-negotiation complete */\r
+#define PHY_AUTO_NEG_CAPABLE (0x0008) /* Auto-negotiation capable */\r
+#define PHY_LINK_UP (0x0004) /* PHY link is up */\r
+#define PHY_EXTENDED_CAPABILITY (0x0001) /* PHY extended register capable */\r
+\r
+#define REG_PHY_ID_LOW (0xE8) /* PHY1ILR */\r
+#define REG_PHY_ID_HIGH (0xEA) /* PHY1IHR */\r
+\r
+#define REG_PHY_AUTO_NEGOTIATION (0xEC) /* P1ANAR */\r
+#define PHY_AUTO_NEG_SYM_PAUSE (0x0400) /* Advertise pause capability */\r
+#define PHY_AUTO_NEG_100BTX_FD (0x0100) /* Advertise 100 full-duplex capability */\r
+#define PHY_AUTO_NEG_100BTX (0x0080) /* Advertise 100 half-duplex capability */\r
+#define PHY_AUTO_NEG_10BT_FD (0x0040) /* Advertise 10 full-duplex capability */\r
+#define PHY_AUTO_NEG_10BT (0x0020) /* Advertise 10 half-duplex capability */\r
+#define PHY_AUTO_NEG_SELECTOR (0x001F) /* Selector field mask */\r
+#define PHY_AUTO_NEG_802_3 (0x0001) /* 802.3 */\r
+\r
+#define REG_PHY_REMOTE_CAPABILITY (0xEE) /* P1ANLPR */\r
+#define PHY_REMOTE_SYM_PAUSE (0x0400) /* Link partner pause capability */\r
+#define PHY_REMOTE_100BTX_FD (0x0100) /* Link partner 100 full-duplex capability */\r
+#define PHY_REMOTE_100BTX (0x0080) /* Link partner 100 half-duplex capability */\r
+#define PHY_REMOTE_10BT_FD (0x0040) /* Link partner 10 full-duplex capability */\r
+#define PHY_REMOTE_10BT (0x0020) /* Link partner 10 half-duplex capability */\r
+\r
+#define REG_PORT_LINK_MD (0xF4) /* P1SCLMD */\r
+#define PORT_CABLE_10M_SHORT (0x8000) /* Cable length is less than 10m short */\r
+#define PORT_CABLE_STAT_FAILED (0x6000) /* Cable diagnostic test fail */\r
+#define PORT_CABLE_STAT_SHORT (0x4000) /* Short condition detected in the cable */\r
+#define PORT_CABLE_STAT_OPEN (0x2000) /* Open condition detected in the cable */\r
+#define PORT_CABLE_STAT_NORMAL (0x0000) /* Normal condition */\r
+#define PORT_CABLE_DIAG_RESULT (0x6000) /* Cable diagnostic test result mask */\r
+#define PORT_START_CABLE_DIAG (0x1000) /* Enable cable diagnostic test */\r
+#define PORT_FORCE_LINK (0x0800) /* Enable force link pass */\r
+#define PORT_POWER_SAVING (0x0400) /* Disable power saving */\r
+#define PORT_REMOTE_LOOPBACK (0x0200) /* Enable remote loopback at PHY */\r
+#define PORT_CABLE_FAULT_COUNTER (0x01FF) /* Cable length distance to the fault */\r
+\r
+#define REG_PORT_CTRL (0xF6) /* P1CR */\r
+#define PORT_LED_OFF (0x8000) /* Turn off all the port LEDs (LED3/LED2/LED1/LED0) */\r
+#define PORT_TX_DISABLE (0x4000) /* Disable port transmit */\r
+#define PORT_AUTO_NEG_RESTART (0x2000) /* Restart auto-negotiation */\r
+#define PORT_POWER_DOWN (0x0800) /* Set port power-down */\r
+#define PORT_AUTO_MDIX_DISABLE (0x0400) /* Disable auto MDI-X */\r
+#define PORT_FORCE_MDIX (0x0200) /* Force MDI-X */\r
+#define PORT_AUTO_NEG_ENABLE (0x0080) /* Enable auto-negotiation */\r
+#define PORT_FORCE_100_MBIT (0x0040) /* Force PHY 100Mbps */\r
+#define PORT_FORCE_FULL_DUPLEX (0x0020) /* Force PHY in full duplex mode */\r
+#define PORT_AUTO_NEG_SYM_PAUSE (0x0010) /* Advertise pause capability */\r
+#define PORT_AUTO_NEG_100BTX_FD (0x0008) /* Advertise 100 full-duplex capability */\r
+#define PORT_AUTO_NEG_100BTX (0x0004) /* Advertise 100 half-duplex capability */\r
+#define PORT_AUTO_NEG_10BT_FD (0x0002) /* Advertise 10 full-duplex capability */\r
+#define PORT_AUTO_NEG_10BT (0x0001) /* Advertise 10 half-duplex capability */\r
+\r
+#define REG_PORT_STATUS (0xF8) /* P1SR */\r
+#define PORT_HP_MDIX (0x8000) /* Set PHY in HP auto MDI-X mode */\r
+#define PORT_REVERSED_POLARITY (0x2000) /* Polarity is reversed */\r
+#define PORT_RX_FLOW_CTRL (0x1000) /* Reeive flow control feature is active */\r
+#define PORT_TX_FLOW_CTRL (0x0800) /* Transmit flow control feature is active */\r
+#define PORT_STAT_SPEED_100MBIT (0x0400) /* Link is 100Mbps */\r
+#define PORT_STAT_FULL_DUPLEX (0x0200) /* Link is full duplex mode */\r
+#define PORT_MDIX_STATUS (0x0080) /* Is MDI */\r
+#define PORT_AUTO_NEG_COMPLETE (0x0040) /* Auto-negotiation complete */\r
+#define PORT_STATUS_LINK_GOOD (0x0020) /* PHY link is up */\r
+#define PORT_REMOTE_SYM_PAUSE (0x0010) /* Link partner pause capability */\r
+#define PORT_REMOTE_100BTX_FD (0x0008) /* Link partner 100 full-duplex capability */\r
+#define PORT_REMOTE_100BTX (0x0004) /* Link partner 100 half-duplex capability */\r
+#define PORT_REMOTE_10BT_FD (0x0002) /* Link partner 10 full-duplex capability */\r
+#define PORT_REMOTE_10BT (0x0001) /* Link partner 10 half-duplex capability */\r
+\r
+#endif /* KSZ8851SNL_REG_H_INCLUDED */\r
#include "FreeRTOS_server_private.h"\r
\r
/* Remove the entire file if TCP is not being used. */\r
-#if( ipconfigUSE_TCP == 1 )\r
+#if( ipconfigUSE_TCP == 1 ) && ( ( ipconfigUSE_HTTP == 1 ) || ( ipconfigUSE_FTP == 1 ) )\r
\r
#if !defined( ARRAY_SIZE )\r
#define ARRAY_SIZE(x) ( BaseType_t ) (sizeof( x ) / sizeof( x )[ 0 ] )\r
pcType = "closed";\r
FreeRTOS_closesocket( xNexSocket );\r
}\r
-\r
- FreeRTOS_printf( ( "TPC-server: new %s client\n", pcType ) );\r
+ {\r
+ struct freertos_sockaddr xRemoteAddress;\r
+ FreeRTOS_GetRemoteAddress( pxClient->xSocket, &xRemoteAddress );\r
+ FreeRTOS_printf( ( "TPC-server: new %s client %xip\n", pcType, (unsigned)FreeRTOS_ntohl( xRemoteAddress.sin_addr ) ) );\r
+ }\r
\r
/* Remove compiler warnings in case FreeRTOS_printf() is not used. */\r
( void ) pcType;\r
#endif /* ipconfigSUPPORT_SIGNALS */\r
/*-----------------------------------------------------------*/\r
\r
-#endif /* ipconfigUSE_TCP != 1 */\r
+#endif /* ( ipconfigUSE_TCP == 1 ) && ( ( ipconfigUSE_HTTP == 1 ) || ( ipconfigUSE_FTP == 1 ) ) */\r
#include "FreeRTOS_TCP_server.h"\r
#include "FreeRTOS_server_private.h"\r
\r
+/* Remove the whole file if HTTP is not supported. */\r
+#if( ipconfigUSE_HTTP == 1 )\r
+\r
/* FreeRTOS+FAT includes. */\r
#include "ff_stdio.h"\r
\r
return pcResult;\r
}\r
\r
+#endif /* ipconfigUSE_HTTP */\r
+\r
projects / freertos / commitdiff