--- /dev/null
+_WDWORD(0xE0002008, 0x00000000); // Clear FPB 0 (FP_COMP0)\r
+\r
--- /dev/null
+/*----------------------------------------------------------------------------\r
+ * Name: Dbg_RAM.ini\r
+ * Purpose: RAM Debug Initialization File\r
+ * Note(s):\r
+ *----------------------------------------------------------------------------\r
+ * This file is part of the uVision/ARM development tools.\r
+ * This software may only be used under the terms of a valid, current,\r
+ * end user licence from KEIL for a compatible version of KEIL software\r
+ * development tools. Nothing else gives you the right to use this software.\r
+ *\r
+ * This software is supplied "AS IS" without warranties of any kind.\r
+ *\r
+ * Copyright (c) 2008-2011 Keil - An ARM Company. All rights reserved.\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ Setup() configure PC & SP for RAM Debug\r
+ *----------------------------------------------------------------------------*/\r
+FUNC void Setup (void) {\r
+ SP = _RDWORD(0x10000000); // Setup Stack Pointer\r
+ PC = _RDWORD(0x10000004); // Setup Program Counter\r
+ _WDWORD(0xE000ED08, 0x10000000); // Setup Vector Table Offset Register\r
+}\r
+\r
+_WDWORD(0x5000413C, 0x001F3700); // Enable RAM\r
+\r
+_WDWORD(0x48028674, 0x00001405); // Enable ETM Pins P6\r
+\r
+_WDWORD(0x48028274, 0x00401405); // Enable ETM Pins P2\r
+ \r
+LOAD %L INCREMENTAL // load the application\r
+\r
+Setup(); // Setup for Running\r
+\r
+/*g, main*/\r
+
\ No newline at end of file
--- /dev/null
+/*----------------------------------------------------------------------------\r
+ * Name: Dbg_RAM.ini\r
+ * Purpose: RAM Debug Initialization File\r
+ * Note(s):\r
+ *----------------------------------------------------------------------------\r
+ * This file is part of the uVision/ARM development tools.\r
+ * This software may only be used under the terms of a valid, current,\r
+ * end user licence from KEIL for a compatible version of KEIL software\r
+ * development tools. Nothing else gives you the right to use this software.\r
+ *\r
+ * This software is supplied "AS IS" without warranties of any kind.\r
+ *\r
+ * Copyright (c) 2008-2011 Keil - An ARM Company. All rights reserved.\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ Setup() configure PC & SP for RAM Debug\r
+ *----------------------------------------------------------------------------*/\r
+FUNC void Setup (void) {\r
+ SP = _RDWORD(0x10000000); // Setup Stack Pointer\r
+ PC = _RDWORD(0x10000004); // Setup Program Counter\r
+ _WDWORD(0xE000ED08, 0x10000000); // Setup Vector Table Offset Register\r
+}\r
+\r
+_WDWORD(0x5000413C, 0x001F3700); // Enable RAM\r
+ \r
+LOAD %L INCREMENTAL // load the application\r
+\r
+Setup(); // Setup for Running\r
+\r
+/*g, main*/\r
+
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+extern uint32_t SystemCoreClock;\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( SystemCoreClock )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40960 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 6 /* 63 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x3f\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+ \r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } \r
+ \r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>RTOSDemo</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>0</CpuCode>
+ <Books>
+ <Book>
+ <Number>0</Number>
+ <Title>Data Sheet</Title>
+ <Path>DATASHTS\Infineon\comming.pdf</Path>
+ </Book>
+ <Book>
+ <Number>1</Number>
+ <Title>User Manual</Title>
+ <Path>DATASHTS\Infineon\comming.pdf</Path>
+ </Book>
+ </Books>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments>-MPU</SimDllArguments>
+ <SimDlgDllName>DARMP1.DLL</SimDlgDllName>
+ <SimDlgDllArguments>-pLPC1785</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments>-MPU</TargetDllArguments>
+ <TargetDlgDllName>TARMP1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments>-pLPC1785</TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(350=-1,-1,-1,-1,0)(250=-1,-1,-1,-1,0)(270=-1,-1,-1,-1,0)(314=-1,-1,-1,-1,0)(292=-1,-1,-1,-1,0)(303=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(410=-1,-1,-1,-1,0)(320=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(362=-1,-1,-1,-1,0)(363=-1,-1,-1,-1,0)(364=-1,-1,-1,-1,0)(365=-1,-1,-1,-1,0)(366=-1,-1,-1,-1,0)(367=-1,-1,-1,-1,0)(332=-1,-1,-1,-1,0)(333=-1,-1,-1,-1,0)(334=-1,-1,-1,-1,0)(335=-1,-1,-1,-1,0)(336=-1,-1,-1,-1,0)(337=-1,-1,-1,-1,0)(345=-1,-1,-1,-1,0)(346=-1,-1,-1,-1,0)(390=-1,-1,-1,-1,0)(381=-1,-1,-1,-1,0)(382=-1,-1,-1,-1,0)(383=-1,-1,-1,-1,0)(384=-1,-1,-1,-1,0)(385=-1,-1,-1,-1,0)(197=-1,-1,-1,-1,0)(198=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(192=-1,-1,-1,-1,0)(199=-1,-1,-1,-1,0)(261=-1,-1,-1,-1,0)(262=-1,-1,-1,-1,0)(263=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(141=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(400=-1,-1,-1,-1,0)(370=-1,-1,-1,-1,0)(280=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGTARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(350=-1,-1,-1,-1,0)(250=-1,-1,-1,-1,0)(270=-1,-1,-1,-1,0)(314=-1,-1,-1,-1,0)(292=-1,-1,-1,-1,0)(303=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(410=-1,-1,-1,-1,0)(320=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(362=-1,-1,-1,-1,0)(363=-1,-1,-1,-1,0)(364=-1,-1,-1,-1,0)(365=-1,-1,-1,-1,0)(366=-1,-1,-1,-1,0)(367=-1,-1,-1,-1,0)(332=-1,-1,-1,-1,0)(333=-1,-1,-1,-1,0)(334=-1,-1,-1,-1,0)(335=-1,-1,-1,-1,0)(336=-1,-1,-1,-1,0)(337=-1,-1,-1,-1,0)(345=-1,-1,-1,-1,0)(346=-1,-1,-1,-1,0)(390=-1,-1,-1,-1,0)(381=-1,-1,-1,-1,0)(382=-1,-1,-1,-1,0)(383=-1,-1,-1,-1,0)(384=-1,-1,-1,-1,0)(385=-1,-1,-1,-1,0)(197=-1,-1,-1,-1,0)(198=-1,-1,-1,-1,0)(191=-1,-1,-1,-1,0)(192=-1,-1,-1,-1,0)(261=-1,-1,-1,-1,0)(262=-1,-1,-1,-1,0)(263=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(141=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(400=-1,-1,-1,-1,0)(370=-1,-1,-1,-1,0)(280=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGUARM</Key>
+ <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ULP2CM3</Key>
+ <Name>-UP1048084 -O143 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(001DB083) -L01(8) -TO18 -TC10000000 -TP28 -TDX0 -TDD0 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN2 -FF0XMC4500 -FS0C000000 -FL0100000 -FF1XMC4500c -FS18000000 -FL1100000</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>-UM1129BUE -O142 -S9 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(001DB083) -L01(8) -TO16 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN2 -FF0XMC4500 -FS0C000000 -FL0100000 -FF1XMC4500c -FS18000000 -FL1100000</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <MemoryWindow1>
+ <Mm>
+ <WinNumber>1</WinNumber>
+ <SubType>5</SubType>
+ <ItemText>0x0C000000</ItemText>
+ </Mm>
+ </MemoryWindow1>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>213</TopLine>
+ <CurrentLine>213</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\startup_XMC4500.s</PathWithFileName>
+ <FilenameWithoutPath>startup_XMC4500.s</FilenameWithoutPath>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>32</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\System_XMC4500.c</PathWithFileName>
+ <FilenameWithoutPath>System_XMC4500.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Demo_Source</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>161</TopLine>
+ <CurrentLine>174</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\main.c</PathWithFileName>
+ <FilenameWithoutPath>main.c</FilenameWithoutPath>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>5</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>47</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\FreeRTOSConfig.h</PathWithFileName>
+ <FilenameWithoutPath>FreeRTOSConfig.h</FilenameWithoutPath>
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+ <Size>0x10000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>0</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls>--cpu Cortex-M4.fp --no_allow_fpreg_for_nonfpdata</MiscControls>
+ <Define>rvkdm PART_XMC4500</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\CORTEX_M4F_Infineon_XMC4500_Keil;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F;..\Common\include</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x0C000000</TextAddressRange>
+ <DataAddressRange>0x10000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc>--entry=Reset_Handler</Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_XMC4500.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_XMC4500.s</FilePath>
+ </File>
+ <File>
+ <FileName>System_XMC4500.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\System_XMC4500.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Demo_Source</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ <File>
+ <FileName>FreeRTOSConfig.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\FreeRTOSConfig.h</FilePath>
+ </File>
+ <File>
+ <FileName>RegTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\RegTest.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>FreeRTOS_Source</GroupName>
+ <Files>
+ <File>
+ <FileName>timers.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\timers.c</FilePath>
+ </File>
+ <File>
+ <FileName>list.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\list.c</FilePath>
+ </File>
+ <File>
+ <FileName>queue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\queue.c</FilePath>
+ </File>
+ <File>
+ <FileName>tasks.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\tasks.c</FilePath>
+ </File>
+ <File>
+ <FileName>heap_2.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\MemMang\heap_2.c</FilePath>
+ </File>
+ <File>
+ <FileName>port.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Other</GroupName>
+ <Files>
+ <File>
+ <FileName>readme.txt</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\readme.txt</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Common_Demo_Source</GroupName>
+ <Files>
+ <File>
+ <FileName>semtest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\semtest.c</FilePath>
+ </File>
+ <File>
+ <FileName>sp_flop.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\sp_flop.c</FilePath>
+ </File>
+ <File>
+ <FileName>BlockQ.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\BlockQ.c</FilePath>
+ </File>
+ <File>
+ <FileName>blocktim.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\blocktim.c</FilePath>
+ </File>
+ <File>
+ <FileName>countsem.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\countsem.c</FilePath>
+ </File>
+ <File>
+ <FileName>death.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\death.c</FilePath>
+ </File>
+ <File>
+ <FileName>dynamic.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\dynamic.c</FilePath>
+ </File>
+ <File>
+ <FileName>GenQTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\GenQTest.c</FilePath>
+ </File>
+ <File>
+ <FileName>integer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\integer.c</FilePath>
+ </File>
+ <File>
+ <FileName>PollQ.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\PollQ.c</FilePath>
+ </File>
+ <File>
+ <FileName>recmutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\recmutex.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
--- /dev/null
+/*\r
+ FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+__asm vRegTest1Task( void )\r
+{\r
+ PRESERVE8\r
+ IMPORT ulRegTest1LoopCounter\r
+\r
+ /* Fill the core registers with known values. */\r
+ mov r0, #100\r
+ mov r1, #101\r
+ mov r2, #102\r
+ mov r3, #103\r
+ mov r4, #104\r
+ mov r5, #105\r
+ mov r6, #106\r
+ mov r7, #107\r
+ mov r8, #108\r
+ mov r9, #109\r
+ mov r10, #110\r
+ mov r11, #111\r
+ mov r12, #112\r
+\r
+ /* Fill the VFP registers with known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg1_loop\r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+ \r
+ vmov r0, r1, d0\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ \r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+ \r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg1_loopf_pass\r
+\r
+reg1_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg1_error_loopf\r
+\r
+reg1_loopf_pass\r
+\r
+ cmp r0, #100\r
+ bne reg1_error_loop\r
+ cmp r1, #101\r
+ bne reg1_error_loop\r
+ cmp r2, #102\r
+ bne reg1_error_loop\r
+ cmp r3, #103\r
+ bne reg1_error_loop\r
+ cmp r4, #104\r
+ bne reg1_error_loop\r
+ cmp r5, #105\r
+ bne reg1_error_loop\r
+ cmp r6, #106\r
+ bne reg1_error_loop\r
+ cmp r7, #107\r
+ bne reg1_error_loop\r
+ cmp r8, #108\r
+ bne reg1_error_loop\r
+ cmp r9, #109\r
+ bne reg1_error_loop\r
+ cmp r10, #110\r
+ bne reg1_error_loop\r
+ cmp r11, #111\r
+ bne reg1_error_loop\r
+ cmp r12, #112\r
+ bne reg1_error_loop\r
+ \r
+ /* Everything passed, increment the loop counter. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest1LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+ \r
+ /* Start again. */\r
+ b reg1_loop\r
+\r
+reg1_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ b reg1_error_loop\r
+ nop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm vRegTest2Task( void )\r
+{\r
+ PRESERVE8\r
+ IMPORT ulRegTest2LoopCounter\r
+\r
+ /* Set all the core registers to known values. */\r
+ mov r0, #-1\r
+ mov r1, #1\r
+ mov r2, #2\r
+ mov r3, #3\r
+ mov r4, #4\r
+ mov r5, #5\r
+ mov r6, #6\r
+ mov r7, #7\r
+ mov r8, #8\r
+ mov r9, #9\r
+ mov r10, #10\r
+ mov r11, #11\r
+ mov r12, #12\r
+\r
+ /* Set all the VFP to known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg2_loop\r
+ \r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+ \r
+ vmov r0, r1, d0\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ \r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+ \r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg2_loopf_pass\r
+\r
+reg2_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg2_error_loopf\r
+\r
+reg2_loopf_pass\r
+\r
+ cmp r0, #-1\r
+ bne reg2_error_loop\r
+ cmp r1, #1\r
+ bne reg2_error_loop\r
+ cmp r2, #2\r
+ bne reg2_error_loop\r
+ cmp r3, #3\r
+ bne reg2_error_loop\r
+ cmp r4, #4\r
+ bne reg2_error_loop\r
+ cmp r5, #5\r
+ bne reg2_error_loop\r
+ cmp r6, #6\r
+ bne reg2_error_loop\r
+ cmp r7, #7\r
+ bne reg2_error_loop\r
+ cmp r8, #8\r
+ bne reg2_error_loop\r
+ cmp r9, #9\r
+ bne reg2_error_loop\r
+ cmp r10, #10\r
+ bne reg2_error_loop\r
+ cmp r11, #11\r
+ bne reg2_error_loop\r
+ cmp r12, #12\r
+ bne reg2_error_loop\r
+ \r
+ /* Increment the loop counter to indicate this test is still functioning\r
+ correctly. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest2LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+ \r
+ /* Start again. */\r
+ b reg2_loop\r
+\r
+reg2_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ This loop ensures the loop counter variable stops incrementing. */\r
+ b reg2_error_loop\r
+ nop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue )\r
+{\r
+ PRESERVE8\r
+\r
+ /* Clobber the auto saved registers. */\r
+ vmov d0, r0, r0\r
+ vmov d1, r0, r0\r
+ vmov d2, r0, r0\r
+ vmov d3, r0, r0\r
+ vmov d4, r0, r0\r
+ vmov d5, r0, r0\r
+ vmov d6, r0, r0\r
+ vmov d7, r0, r0\r
+ bx lr\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue )\r
+{\r
+ PRESERVE8\r
+\r
+ vmov r1, s0\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s1\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s2\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s3\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s4\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s5\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s6\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s7\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s8\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s9\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s10\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s11\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s12\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s13\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s14\r
+ cmp r0, r1\r
+ bne return_error\r
+ vmov r1, s15\r
+ cmp r0, r1\r
+ bne return_error\r
+ \r
+return_pass\r
+ mov r0, #1\r
+ bx lr\r
+\r
+return_error\r
+ mov r0, #0\r
+ bx lr\r
+}\r
+\r
+ \r
--- /dev/null
+/**************************************************************************//**\r
+ * @file system_XMC4500.h\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
+ * for the Infineon XMC4500 Device Series\r
+ * @version V2.1\r
+ * @date 20. December 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include "System_XMC4500.h"\r
+#include <XMC4500.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ Define clocks is located in System_XMC4500.h\r
+ *----------------------------------------------------------------------------*/\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+uint32_t SystemCoreClock = CLOCK_OSC_HP;/*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+ static functions declarations\r
+ *----------------------------------------------------------------------------*/\r
+static int SystemClockSetup(void);\r
+static void USBClockSetup(void);\r
+\r
+/*----------------------------------------------------------------------------\r
+ Keil pragma to prevent warnings\r
+ *----------------------------------------------------------------------------*/\r
+#pragma diag_suppress 177\r
+\r
+\r
+/*\r
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+*/\r
+\r
+\r
+\r
+/*--------------------- Watchdog Configuration -------------------------------\r
+//\r
+// <e> Watchdog Configuration\r
+// <o1.0> Disable Watchdog\r
+//\r
+// </e>\r
+*/\r
+#define WDT_SETUP 1\r
+#define WDTENB_nVal 0x00000001\r
+\r
+/*--------------------- CLOCK Configuration -------------------------------\r
+//\r
+// <e> Main Clock Configuration\r
+// <o1.0..1> CPU clock divider\r
+// <0=> fCPU = fSYS \r
+// <1=> fCPU = fSYS / 2\r
+// <o2.0..1> Peripheral Bus clock divider\r
+// <0=> fPB = fCPU\r
+// <1=> fPB = fCPU / 2\r
+// <o3.0..1> CCU Bus clock divider\r
+// <0=> fCCU = fCPU\r
+// <1=> fCCU = fCPU / 2\r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_CLOCK_SETUP 1\r
+#define SCU_CPUCLKCR_DIV 0x00000000\r
+#define SCU_PBCLKCR_DIV 0x00000000\r
+#define SCU_CCUCLKCR_DIV 0x00000000\r
+\r
+\r
+\r
+/*--------------------- USB CLOCK Configuration ---------------------------\r
+//\r
+// <e> USB Clock Configuration\r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_USB_CLOCK_SETUP 0\r
+\r
+\r
+/*--------------------- CLOCKOUT Configuration -------------------------------\r
+//\r
+// <e> Clock OUT Configuration\r
+// <o1.0..1> Clockout Source Selection\r
+// <0=> System Clock\r
+// <2=> USB Clock\r
+// <3=> Divided value of PLL Clock\r
+// <o2.0..1> Clockout Pin Selection\r
+// <0=> P1.15\r
+// <1=> P0.8\r
+// \r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_CLOCKOUT_SETUP 0\r
+#define SCU_CLOCKOUT_SOURCE 0x00000000\r
+#define SCU_CLOCKOUT_PIN 0x00000000\r
+\r
+\r
+\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the PLL and update the \r
+ * SystemCoreClock variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+/* Setup the WDT */\r
+ #if WDT_SETUP\r
+ WDT->CTR &= ~WDTENB_nVal; \r
+ #endif\r
+\r
+/* enable coprocessor FPU */\r
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */\r
+ (3UL << 11*2) ); /* set CP11 Full Access */\r
+ #endif\r
+\r
+/* Disable branch prediction - PCON.PBS = 1 */\r
+ PREF->PCON |= (PREF_PCON_PBS_Msk << PREF_PCON_PBS_Pos);\r
+\r
+/* Setup the clockout */\r
+ #if SCU_CLOCKOUT_SETUP\r
+ SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE;\r
+ if (SCU_CLOCKOUT_PIN) {\r
+ PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */\r
+ PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
+ }\r
+ else PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */\r
+ #endif\r
+\r
+/* Setup the System clock */ \r
+ #if SCU_CLOCK_SETUP\r
+ SystemClockSetup();\r
+ #endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+ SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/\r
+\r
+/* Setup the USB PL */ \r
+ #if SCU_USB_CLOCK_SETUP\r
+ USBClockSetup();\r
+ #endif\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+ SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief -\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+static int SystemClockSetup(void)\r
+{\r
+/* enable PLL first */\r
+ SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+\r
+/* Enable OSC_HP */\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
+ {\r
+\r
+ SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); /*enable the OSC_HP*/\r
+ /* setup OSC WDG devider */\r
+ SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16); \r
+ /* select external OSC as PLL input */\r
+ SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ /* restart OSC Watchdog */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
+\r
+ do \r
+ {\r
+ ; /* here a timeout need to be added */\r
+ }while(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk))); \r
+\r
+ }\r
+\r
+/* Setup Main PLL */\r
+ /* select FOFI as system clock */\r
+ if(SCU_CLK->SYSCLKCR != 0X000000)SCU_CLK->SYSCLKCR = 0x00000000; /*Select FOFI*/\r
+ /* Go to bypass the Main PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+ /* disconnect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV_STEP_1<<16) | (PLL_PDIV<<24));\r
+ /* we may have to set OSCDISCDIS */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+ /* connect OSC_HP to PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
+ /* restart PLL Lock detection */\r
+ SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
+ /* wait for PLL Lock */\r
+ while (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk));\r
+ /* Go back to the Main PLL */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+\r
+ /*********************************************************\r
+ here we need to setup the system clock divider\r
+ *********************************************************/\r
+\r
+ SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
+ SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; \r
+ SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
+\r
+ /* Switch system clock to PLL */\r
+ SCU_CLK->SYSCLKCR |= 0x00010000; \r
+ \r
+ /*********************************************************\r
+ here the ramp up of the system clock starts\r
+ *********************************************************/\r
+ /* Delay for next K2 step ~50µs */\r
+ /********************************/\r
+ SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+\r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV_STEP_2<<16) | (PLL_PDIV<<24));\r
+\r
+ /* Delay for next K2 step ~50µs */\r
+ /********************************/\r
+ SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+\r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV_STEP_3<<16) | (PLL_PDIV<<24));\r
+\r
+ /* Delay for next K2 step ~50µs */\r
+ /********************************/\r
+ SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+\r
+ while (SysTick->VAL >= 100); /* wait for ~50µs */\r
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */\r
+ /********************************/\r
+\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV<<16) | (PLL_PDIV<<24));\r
+\r
+ SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */\r
+\r
+ return(1);\r
+\r
+}\r
+\r
+/**\r
+ * @brief -\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void USBClockSetup(void)\r
+{\r
+/* enable PLL first */\r
+ SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
+\r
+/* check and if not already running enable OSC_HP */\r
+ if(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)))\r
+ {\r
+ if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
+ {\r
+ \r
+ SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); /*enable the OSC_HP*/\r
+ /* setup OSC WDG devider */\r
+ SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16); \r
+ /* select external OSC as PLL input */\r
+ SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+ /* restart OSC Watchdog */\r
+ SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; \r
+ \r
+ do \r
+ {\r
+ ; /* here a timeout need to be added */\r
+ }while(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk))); \r
+ \r
+ }\r
+ }\r
+\r
+\r
+/* Setup USB PLL */\r
+ /* Go to bypass the Main PLL */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;\r
+ /* disconnect OSC_FI to PLL */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+ /* Setup devider settings for main PLL */\r
+ SCU_PLL->USBPLLCON = ((USBPLL_NDIV<<8) | (USBPLL_PDIV<<24));\r
+ /* we may have to set OSCDISCDIS */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
+ /* connect OSC_FI to PLL */\r
+ SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+ /* restart PLL Lock detection */\r
+ SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
+ /* wait for PLL Lock */\r
+ while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
+ \r
+}\r
+\r
+\r
--- /dev/null
+; *************************************************************\r
+; *** Scatter-Loading Description File generated by uVision ***\r
+; *************************************************************\r
+\r
+LR_IROM1 0x0C000000 0x00100000 { ; load region size_region\r
+ ER_IROM1 0x0C000000 0x00100000 { ; load address = execution address\r
+ *.o (RESET, +First)\r
+ *(InRoot$$Sections)\r
+ .ANY (+RO)\r
+ }\r
+ RW_IRAM1 0x10000000 0x00010000 { ; RW data\r
+ .ANY (+RW +ZI)\r
+ }\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*\r
+ * main() creates all the demo application tasks and a software timer, then \r
+ * starts the scheduler. The web documentation provides more details of the \r
+ * standard demo application tasks, which provide no particular functionality, \r
+ * but do provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill both the core and floating point registers with\r
+ * known values, then check that each register maintains its expected value for\r
+ * the lifetime of the task. Each task uses a different set of values. The reg\r
+ * test tasks execute with a very low priority, so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ * "Check" timer - The check software timer period is initially set to three\r
+ * seconds. The callback function associated with the check software timer\r
+ * checks that all the standard demo tasks, and the register check tasks, are\r
+ * not only still executing, but are executing without reporting any errors. If\r
+ * the check software timer discovers that a task has either stalled, or\r
+ * reported an error, then it changes its own execution period from the initial\r
+ * three seconds, to just 200ms. The check software timer callback function\r
+ * also toggles the single LED each time it is called. This provides a visual\r
+ * indication of the system status: If the LED toggles every three seconds,\r
+ * then no issues have been discovered. If the LED toggles every 200ms, then\r
+ * an issue has been discovered with at least one task.\r
+ *\r
+ * \r
+ * Additional code:\r
+ * \r
+ * This demo does not contain a non-kernel interrupt service routine that\r
+ * can be used as an example for application writers to use as a reference.\r
+ * Therefore, the framework of a dummy (not installed) handler is provided\r
+ * in this file. The dummy function is called Dummy_IRQHandler(). Please\r
+ * ensure to read the comments in the function itself, but more importantly,\r
+ * the notes on the function contained on the documentation page for this demo\r
+ * that is found on the FreeRTOS.org web site.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo application includes. */\r
+#include "flop.h"\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+\r
+/* Hardware includes. */\r
+#include "XMC4500.h"\r
+#include "System_XMC4500.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* To toggle the single LED */\r
+#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The period after which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_RATE_MS constant. */\r
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_RATE_MS constant. */\r
+#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Set up the hardware ready to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * The check timer callback function, as described at the top of this file.\r
+ */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer );\r
+\r
+/*\r
+ * Register check tasks, and the tasks used to write over and check the contents\r
+ * of the FPU registers, as described at the top of this file. The nature of\r
+ * these files necessitates that they are written in an assembly file.\r
+ */\r
+extern void vRegTest1Task( void *pvParameters );\r
+extern void vRegTest2Task( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The following two variables are used to communicate the status of the\r
+register check tasks to the check software timer. If the variables keep\r
+incrementing, then the register check tasks has not discovered any errors. If\r
+a variable stops incrementing, then an error has been found. */\r
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+xTimerHandle xCheckTimer = NULL;\r
+\r
+ /* Configure the hardware ready to run the test. */\r
+ prvSetupHardware();\r
+\r
+ /* Start all the other standard demo/test tasks. The have not particular\r
+ functionality, but do demonstrate how to use the FreeRTOS API and test the\r
+ kernel port. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
+ \r
+ /* Create the register check tasks, as described at the top of this\r
+ file */\r
+ xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the software timer that performs the 'check' functionality,\r
+ as described at the top of this file. */\r
+ xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
+ ); \r
+ \r
+ if( xCheckTimer != NULL )\r
+ {\r
+ xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
+ }\r
+\r
+ /* The set of tasks created by the following function call have to be \r
+ created last as they keep account of the number of tasks they expect to see \r
+ running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+ \r
+ /* If all is well, the scheduler will now be running, and the following line\r
+ will never be reached. If the following line does execute, then there was\r
+ insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
+ to be created. See the memory management section on the FreeRTOS web site\r
+ for more details. */\r
+ for( ;; ); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTimerCallback( xTimerHandle xTimer )\r
+{\r
+static long lChangedTimerPeriodAlready = pdFALSE;\r
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none have detected an error. */\r
+\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+ \r
+ /* Check that the register test 1 task is still running. */\r
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+ ulLastRegTest1Value = ulRegTest1LoopCounter;\r
+\r
+ /* Check that the register test 2 task is still running. */\r
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+ ulLastRegTest2Value = ulRegTest2LoopCounter;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ mainTOGGLE_LED(); \r
+ \r
+ /* Have any errors been latch in ulErrorFound? If so, shorten the\r
+ period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.\r
+ This will result in an increase in the rate at which mainCHECK_LED\r
+ toggles. */\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ if( lChangedTimerPeriodAlready == pdFALSE )\r
+ {\r
+ lChangedTimerPeriodAlready = pdTRUE;\r
+ \r
+ /* This call to xTimerChangePeriod() uses a zero block time.\r
+ Functions called from inside of a timer callback function must\r
+ *never* attempt to block. */\r
+ xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+extern void SystemCoreClockUpdate( void );\r
+\r
+ /* Ensure SystemCoreClock variable is set. */\r
+ SystemCoreClockUpdate();\r
+\r
+ /* Configure pin P3.9 for the LED. */\r
+ PORT3->IOCR8 = 0x00008000;\r
+\r
+ /* Ensure all priority bits are assigned as preemption priority bits. */\r
+ NVIC_SetPriorityGrouping( 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* vApplicationMallocFailedHook() will only be called if\r
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ function that will get called if a call to pvPortMalloc() fails.\r
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+ timer or semaphore is created. It is also called by various parts of the\r
+ demo application. If heap_1.c or heap_2.c are used, then the size of the\r
+ heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+ FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+ to query the size of free heap space that remains (although it does not\r
+ provide information on how the remaining heap might be fragmented). */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
+ task. It is essential that code added to this hook function never attempts\r
+ to block in any way (for example, call xQueueReceive() with a block time\r
+ specified, or call vTaskDelay()). If the application makes use of the\r
+ vTaskDelete() API function (as this demo application does) then it is also\r
+ important that vApplicationIdleHook() is permitted to return to its calling\r
+ function, because it is the responsibility of the idle task to clean up\r
+ memory allocated by the kernel to any task that has since been deleted. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ /* This function will be called by each tick interrupt if \r
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
+ added here, but the tick hook is called from an interrupt context, so\r
+ code must not attempt to block, and only the interrupt safe FreeRTOS API\r
+ functions can be used (those that end in FromISR()). */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef JUST_AN_EXAMPLE_ISR\r
+\r
+void Dummy_IRQHandler(void)\r
+{\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* Clear the interrupt if necessary. */\r
+ Dummy_ClearITPendingBit();\r
+ \r
+ /* This interrupt does nothing more than demonstrate how to synchronise a\r
+ task with an interrupt. A semaphore is used for this purpose. Note\r
+ lHigherPriorityTaskWoken is initialised to zero. */\r
+ xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );\r
+ \r
+ /* If there was a task that was blocked on the semaphore, and giving the\r
+ semaphore caused the task to unblock, and the unblocked task has a priority\r
+ higher than the current Running state task (the task that this interrupt\r
+ interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE\r
+ internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the \r
+ portEND_SWITCHING_ISR() macro will result in a context switch being pended to\r
+ ensure this interrupt returns directly to the unblocked, higher priority, \r
+ task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */\r
+ portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );\r
+}\r
+\r
+#endif /* JUST_AN_EXAMPLE_ISR */\r
--- /dev/null
+;*****************************************************************************/
+; * @file startup_XMC4500.s\r
+; * @brief CMSIS Cortex-M4 Core Device Startup File for\r
+; * Infineon XMC4500 Device Series\r
+; * @version V1.02\r
+; * @date 6. December 2011\r
+; *\r
+; * @note\r
+; * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+; *\r
+; * @par\r
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+; * processor based microcontrollers. This file can be freely distributed\r
+; * within development tools that are supporting such ARM based processors.\r
+; *\r
+; * @par\r
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+; *\r
+; ******************************************************************************/\r
+
+
+;* <<< Use Configuration Wizard in Context Menu >>>
+
+; Amount of memory (in bytes) allocated for Stack\r
+; Tailor this value to your application needs\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000400\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000200\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+
+;* ================== START OF VECTOR TABLE DEFINITION ====================== */
+;* Vector Table - This gets programed into VTOR register */
+ AREA RESET, DATA, READONLY\r
+ EXPORT __cs3_interrupt_vector_cortex_m\r
+ EXPORT __cs3_interrupt_vector_cortex_m_End\r
+ EXPORT __cs3_interrupt_vector_cortex_m_Size\r
+\r
+\r
+
+__cs3_interrupt_vector_cortex_m
+ DCD __initial_sp ;* Top of Stack */
+ DCD Reset_Handler ;* Reset Handler */
+ DCD NMI_Handler ;* NMI Handler */
+ DCD HardFault_Handler ;* Hard Fault Handler */
+ DCD MemManage_Handler ;* MPU Fault Handler */
+ DCD BusFault_Handler ;* Bus Fault Handler */
+ DCD UsageFault_Handler ;* Usage Fault Handler */
+ DCD 0 ;* Reserved */
+ DCD 0 ;* Reserved */
+ DCD 0 ;* Reserved */
+ DCD 0 ;* Reserved */
+ DCD SVC_Handler ;* SVCall Handler */
+ DCD DebugMon_Handler ;* Debug Monitor Handler */
+ DCD 0 ;* Reserved */
+ DCD PendSV_Handler ;* PendSV Handler */
+ DCD SysTick_Handler ;* SysTick Handler */
+
+ ;* Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals */
+ DCD SCU_0_IRQHandler ;* Handler name for SR SCU_0 */
+ DCD ERU0_0_IRQHandler ;* Handler name for SR ERU0_0 */
+ DCD ERU0_1_IRQHandler ;* Handler name for SR ERU0_1 */
+ DCD ERU0_2_IRQHandler ;* Handler name for SR ERU0_2 */
+ DCD ERU0_3_IRQHandler ;* Handler name for SR ERU0_3 */
+ DCD ERU1_0_IRQHandler ;* Handler name for SR ERU1_0 */
+ DCD ERU1_1_IRQHandler ;* Handler name for SR ERU1_1 */
+ DCD ERU1_2_IRQHandler ;* Handler name for SR ERU1_2 */
+ DCD ERU1_3_IRQHandler ;* Handler name for SR ERU1_3 */
+ DCD 0 ;* Not Available */
+ DCD 0 ;* Not Available */
+ DCD 0 ;* Not Available */
+ DCD PMU0_0_IRQHandler ;* Handler name for SR PMU0_0 */
+ DCD 0 ;* Not Available */
+ DCD VADC0_C0_0_IRQHandler ;* Handler name for SR VADC0_C0_0 */
+ DCD VADC0_C0_1_IRQHandler ;* Handler name for SR VADC0_C0_1 */
+ DCD VADC0_C0_2_IRQHandler ;* Handler name for SR VADC0_C0_1 */
+ DCD VADC0_C0_3_IRQHandler ;* Handler name for SR VADC0_C0_3 */
+ DCD VADC0_G0_0_IRQHandler ;* Handler name for SR VADC0_G0_0 */
+ DCD VADC0_G0_1_IRQHandler ;* Handler name for SR VADC0_G0_1 */
+ DCD VADC0_G0_2_IRQHandler ;* Handler name for SR VADC0_G0_2 */
+ DCD VADC0_G0_3_IRQHandler ;* Handler name for SR VADC0_G0_3 */
+ DCD VADC0_G1_0_IRQHandler ;* Handler name for SR VADC0_G1_0 */
+ DCD VADC0_G1_1_IRQHandler ;* Handler name for SR VADC0_G1_1 */
+ DCD VADC0_G1_2_IRQHandler ;* Handler name for SR VADC0_G1_2 */
+ DCD VADC0_G1_3_IRQHandler ;* Handler name for SR VADC0_G1_3 */
+ DCD VADC0_G2_0_IRQHandler ;* Handler name for SR VADC0_G2_0 */
+ DCD VADC0_G2_1_IRQHandler ;* Handler name for SR VADC0_G2_1 */
+ DCD VADC0_G2_2_IRQHandler ;* Handler name for SR VADC0_G2_2 */
+ DCD VADC0_G2_3_IRQHandler ;* Handler name for SR VADC0_G2_3 */
+ DCD VADC0_G3_0_IRQHandler ;* Handler name for SR VADC0_G3_0 */
+ DCD VADC0_G3_1_IRQHandler ;* Handler name for SR VADC0_G3_1 */
+ DCD VADC0_G3_2_IRQHandler ;* Handler name for SR VADC0_G3_2 */
+ DCD VADC0_G3_3_IRQHandler ;* Handler name for SR VADC0_G3_3 */
+ DCD DSD0_0_IRQHandler ;* Handler name for SR DSD0_0 */
+ DCD DSD0_1_IRQHandler ;* Handler name for SR DSD0_1 */
+ DCD DSD0_2_IRQHandler ;* Handler name for SR DSD0_2 */
+ DCD DSD0_3_IRQHandler ;* Handler name for SR DSD0_3 */
+ DCD DSD0_4_IRQHandler ;* Handler name for SR DSD0_4 */
+ DCD DSD0_5_IRQHandler ;* Handler name for SR DSD0_5 */
+ DCD DSD0_6_IRQHandler ;* Handler name for SR DSD0_6 */
+ DCD DSD0_7_IRQHandler ;* Handler name for SR DSD0_7 */
+ DCD DAC0_0_IRQHandler ;* Handler name for SR DAC0_0 */
+ DCD DAC0_1_IRQHandler ;* Handler name for SR DAC0_0 */
+ DCD CCU40_0_IRQHandler ;* Handler name for SR CCU40_0 */
+ DCD CCU40_1_IRQHandler ;* Handler name for SR CCU40_1 */
+ DCD CCU40_2_IRQHandler ;* Handler name for SR CCU40_2 */
+ DCD CCU40_3_IRQHandler ;* Handler name for SR CCU40_3 */
+ DCD CCU41_0_IRQHandler ;* Handler name for SR CCU41_0 */
+ DCD CCU41_1_IRQHandler ;* Handler name for SR CCU41_1 */
+ DCD CCU41_2_IRQHandler ;* Handler name for SR CCU41_2 */
+ DCD CCU41_3_IRQHandler ;* Handler name for SR CCU41_3 */
+ DCD CCU42_0_IRQHandler ;* Handler name for SR CCU42_0 */
+ DCD CCU42_1_IRQHandler ;* Handler name for SR CCU42_1 */
+ DCD CCU42_2_IRQHandler ;* Handler name for SR CCU42_2 */
+ DCD CCU42_3_IRQHandler ;* Handler name for SR CCU42_3 */
+ DCD CCU43_0_IRQHandler ;* Handler name for SR CCU43_0 */
+ DCD CCU43_1_IRQHandler ;* Handler name for SR CCU43_1 */
+ DCD CCU43_2_IRQHandler ;* Handler name for SR CCU43_2 */
+ DCD CCU43_3_IRQHandler ;* Handler name for SR CCU43_3 */
+ DCD CCU80_0_IRQHandler ;* Handler name for SR CCU80_0 */
+ DCD CCU80_1_IRQHandler ;* Handler name for SR CCU80_1 */
+ DCD CCU80_2_IRQHandler ;* Handler name for SR CCU80_2 */
+ DCD CCU80_3_IRQHandler ;* Handler name for SR CCU80_3 */
+ DCD CCU81_0_IRQHandler ;* Handler name for SR CCU81_0 */
+ DCD CCU81_1_IRQHandler ;* Handler name for SR CCU81_1 */
+ DCD CCU81_2_IRQHandler ;* Handler name for SR CCU81_2 */
+ DCD CCU81_3_IRQHandler ;* Handler name for SR CCU81_3 */
+ DCD POSIF0_0_IRQHandler ;* Handler name for SR POSIF0_0 */
+ DCD POSIF0_1_IRQHandler ;* Handler name for SR POSIF0_1 */
+ DCD POSIF1_0_IRQHandler ;* Handler name for SR POSIF1_0 */
+ DCD POSIF1_1_IRQHandler ;* Handler name for SR POSIF1_1 */
+ DCD 0 ;* Not Available */
+ DCD 0 ;* Not Available */
+ DCD 0 ;* Not Available */
+ DCD 0 ;* Not Available */
+ DCD CAN0_0_IRQHandler ;* Handler name for SR CAN0_0 */
+ DCD CAN0_1_IRQHandler ;* Handler name for SR CAN0_1 */
+ DCD CAN0_2_IRQHandler ;* Handler name for SR CAN0_2 */
+ DCD CAN0_3_IRQHandler ;* Handler name for SR CAN0_3 */
+ DCD CAN0_4_IRQHandler ;* Handler name for SR CAN0_4 */
+ DCD CAN0_5_IRQHandler ;* Handler name for SR CAN0_5 */
+ DCD CAN0_6_IRQHandler ;* Handler name for SR CAN0_6 */
+ DCD CAN0_7_IRQHandler ;* Handler name for SR CAN0_7 */
+ DCD USIC0_0_IRQHandler ;* Handler name for SR USIC0_0 */
+ DCD USIC0_1_IRQHandler ;* Handler name for SR USIC0_1 */
+ DCD USIC0_2_IRQHandler ;* Handler name for SR USIC0_2 */
+ DCD USIC0_3_IRQHandler ;* Handler name for SR USIC0_3 */
+ DCD USIC0_4_IRQHandler ;* Handler name for SR USIC0_4 */
+ DCD USIC0_5_IRQHandler ;* Handler name for SR USIC0_5 */
+ DCD USIC1_0_IRQHandler ;* Handler name for SR USIC1_0 */
+ DCD USIC1_1_IRQHandler ;* Handler name for SR USIC1_1 */
+ DCD USIC1_2_IRQHandler ;* Handler name for SR USIC1_2 */
+ DCD USIC1_3_IRQHandler ;* Handler name for SR USIC1_3 */
+ DCD USIC1_4_IRQHandler ;* Handler name for SR USIC1_4 */
+ DCD USIC1_5_IRQHandler ;* Handler name for SR USIC1_5 */
+ DCD USIC2_0_IRQHandler ;* Handler name for SR USIC2_0 */
+ DCD USIC2_1_IRQHandler ;* Handler name for SR USIC2_1 */
+ DCD USIC2_2_IRQHandler ;* Handler name for SR USIC2_2 */
+ DCD USIC2_3_IRQHandler ;* Handler name for SR USIC2_3 */
+ DCD USIC2_4_IRQHandler ;* Handler name for SR USIC2_4 */
+ DCD USIC2_5_IRQHandler ;* Handler name for SR USIC2_5 */
+ DCD LEDTS0_0_IRQHandler ;* Handler name for SR LEDTS0_0 */
+ DCD 0 ;* Not Available */
+ DCD FCE0_0_IRQHandler ;* Handler name for SR FCE0_0 */
+ DCD GPDMA0_0_IRQHandler ;* Handler name for SR GPDMA0_0 */
+ DCD SDMMC0_0_IRQHandler ;* Handler name for SR SDMMC0_0 */
+ DCD USB0_0_IRQHandler ;* Handler name for SR USB0_0 */
+ DCD ETH0_0_IRQHandler ;* Handler name for SR ETH0_0 */
+ DCD 0 ;* Not Available */
+ DCD GPDMA1_0_IRQHandler ;* Handler name for SR GPDMA1_0 */
+ DCD 0 ;* Not Available */
+__cs3_interrupt_vector_cortex_m_End\r
+\r
+__cs3_interrupt_vector_cortex_m_Size EQU __cs3_interrupt_vector_cortex_m_End - __cs3_interrupt_vector_cortex_m
+
+;* ================== END OF VECTOR TABLE DEFINITION ======================= */
+
+;* ================== START OF VECTOR ROUTINES ============================= */\r
+
+ AREA |.text|, CODE, READONLY\r
+
+;* Reset Handler */
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT SystemInit \r
+ IMPORT __main\r
+\r
+ ;* Remap vector table
+ LDR R0, =__cs3_interrupt_vector_cortex_m
+ LDR R1, =0xE000ED08 ;*VTOR register\r
+ STR R0,[R1]\r
+\r
+ ;enable un-aligned memory access \r
+ LDR R1, =0xE000ED14 \r
+ LDR.W R0,[R1,#0x0]\r
+ BIC R0,R0,#0x8\r
+ STR.W R0,[R1,#0x0]\r
+\r
+\r
+ ;* C routines are likely to be called. Setup the stack now \r
+ LDR SP,=__initial_sp\r
+\r
+
+ LDR R0, = SystemInit
+ BLX R0
+
+ \r
+ ;* Reset stack pointer before zipping off to user application
+ LDR SP,=__initial_sp
+ \r
+ LDR R0, =__main
+ BX R0\r
+\r
+ ENDP\r
+\r
+
+
+
+;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
+
+;* Default exception Handlers - Users may override this default functionality by
+
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+MemManage_Handler\\r
+ PROC\r
+ EXPORT MemManage_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+BusFault_Handler\\r
+ PROC\r
+ EXPORT BusFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+UsageFault_Handler\\r
+ PROC\r
+ EXPORT UsageFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SVC_Handler PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+DebugMon_Handler\\r
+ PROC\r
+ EXPORT DebugMon_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+PendSV_Handler PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SysTick_Handler PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+
+;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */
+
+;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
+
+;* IRQ Handlers */
+ EXPORT SCU_0_IRQHandler [WEAK]
+ EXPORT ERU0_0_IRQHandler [WEAK]
+ EXPORT ERU0_1_IRQHandler [WEAK]
+ EXPORT ERU0_2_IRQHandler [WEAK]
+ EXPORT ERU0_3_IRQHandler [WEAK]
+ EXPORT ERU1_0_IRQHandler [WEAK]
+ EXPORT ERU1_1_IRQHandler [WEAK]
+ EXPORT ERU1_2_IRQHandler [WEAK]
+ EXPORT ERU1_3_IRQHandler [WEAK]
+ EXPORT PMU0_0_IRQHandler [WEAK]
+ EXPORT VADC0_C0_0_IRQHandler [WEAK]
+ EXPORT VADC0_C0_1_IRQHandler [WEAK]
+ EXPORT VADC0_C0_2_IRQHandler [WEAK]
+ EXPORT VADC0_C0_3_IRQHandler [WEAK]
+ EXPORT VADC0_G0_0_IRQHandler [WEAK]
+ EXPORT VADC0_G0_1_IRQHandler [WEAK]
+ EXPORT VADC0_G0_2_IRQHandler [WEAK]
+ EXPORT VADC0_G0_3_IRQHandler [WEAK]
+ EXPORT VADC0_G1_0_IRQHandler [WEAK]
+ EXPORT VADC0_G1_1_IRQHandler [WEAK]
+ EXPORT VADC0_G1_2_IRQHandler [WEAK]
+ EXPORT VADC0_G1_3_IRQHandler [WEAK]
+ EXPORT VADC0_G2_0_IRQHandler [WEAK]
+ EXPORT VADC0_G2_1_IRQHandler [WEAK]
+ EXPORT VADC0_G2_2_IRQHandler [WEAK]
+ EXPORT VADC0_G2_3_IRQHandler [WEAK]
+ EXPORT VADC0_G3_0_IRQHandler [WEAK]
+ EXPORT VADC0_G3_1_IRQHandler [WEAK]
+ EXPORT VADC0_G3_2_IRQHandler [WEAK]
+ EXPORT VADC0_G3_3_IRQHandler [WEAK]
+ EXPORT DSD0_0_IRQHandler [WEAK]
+ EXPORT DSD0_1_IRQHandler [WEAK]
+ EXPORT DSD0_2_IRQHandler [WEAK]
+ EXPORT DSD0_3_IRQHandler [WEAK]
+ EXPORT DSD0_4_IRQHandler [WEAK]
+ EXPORT DSD0_5_IRQHandler [WEAK]
+ EXPORT DSD0_6_IRQHandler [WEAK]
+ EXPORT DSD0_7_IRQHandler [WEAK]
+ EXPORT DAC0_0_IRQHandler [WEAK]
+ EXPORT DAC0_1_IRQHandler [WEAK]
+ EXPORT CCU40_0_IRQHandler [WEAK]
+ EXPORT CCU40_1_IRQHandler [WEAK]
+ EXPORT CCU40_2_IRQHandler [WEAK]
+ EXPORT CCU40_3_IRQHandler [WEAK]
+ EXPORT CCU41_0_IRQHandler [WEAK]
+ EXPORT CCU41_1_IRQHandler [WEAK]
+ EXPORT CCU41_2_IRQHandler [WEAK]
+ EXPORT CCU41_3_IRQHandler [WEAK]
+ EXPORT CCU42_0_IRQHandler [WEAK]
+ EXPORT CCU42_1_IRQHandler [WEAK]
+ EXPORT CCU42_2_IRQHandler [WEAK]
+ EXPORT CCU42_3_IRQHandler [WEAK]
+ EXPORT CCU43_0_IRQHandler [WEAK]
+ EXPORT CCU43_1_IRQHandler [WEAK]
+ EXPORT CCU43_2_IRQHandler [WEAK]
+ EXPORT CCU43_3_IRQHandler [WEAK]
+ EXPORT CCU80_0_IRQHandler [WEAK]
+ EXPORT CCU80_1_IRQHandler [WEAK]
+ EXPORT CCU80_2_IRQHandler [WEAK]
+ EXPORT CCU80_3_IRQHandler [WEAK]
+ EXPORT CCU81_0_IRQHandler [WEAK]
+ EXPORT CCU81_1_IRQHandler [WEAK]
+ EXPORT CCU81_2_IRQHandler [WEAK]
+ EXPORT CCU81_3_IRQHandler [WEAK]
+ EXPORT POSIF0_0_IRQHandler [WEAK]
+ EXPORT POSIF0_1_IRQHandler [WEAK]
+ EXPORT POSIF1_0_IRQHandler [WEAK]
+ EXPORT POSIF1_1_IRQHandler [WEAK]
+ EXPORT CAN0_0_IRQHandler [WEAK]
+ EXPORT CAN0_1_IRQHandler [WEAK]
+ EXPORT CAN0_2_IRQHandler [WEAK]
+ EXPORT CAN0_3_IRQHandler [WEAK]
+ EXPORT CAN0_4_IRQHandler [WEAK]
+ EXPORT CAN0_5_IRQHandler [WEAK]
+ EXPORT CAN0_6_IRQHandler [WEAK]
+ EXPORT CAN0_7_IRQHandler [WEAK]
+ EXPORT USIC0_0_IRQHandler [WEAK]
+ EXPORT USIC0_1_IRQHandler [WEAK]
+ EXPORT USIC0_2_IRQHandler [WEAK]
+ EXPORT USIC0_3_IRQHandler [WEAK]
+ EXPORT USIC0_4_IRQHandler [WEAK]
+ EXPORT USIC0_5_IRQHandler [WEAK]
+ EXPORT USIC1_0_IRQHandler [WEAK]
+ EXPORT USIC1_1_IRQHandler [WEAK]
+ EXPORT USIC1_2_IRQHandler [WEAK]
+ EXPORT USIC1_3_IRQHandler [WEAK]
+ EXPORT USIC1_4_IRQHandler [WEAK]
+ EXPORT USIC1_5_IRQHandler [WEAK]
+ EXPORT USIC2_0_IRQHandler [WEAK]
+ EXPORT USIC2_1_IRQHandler [WEAK]
+ EXPORT USIC2_2_IRQHandler [WEAK]
+ EXPORT USIC2_3_IRQHandler [WEAK]
+ EXPORT USIC2_4_IRQHandler [WEAK]
+ EXPORT USIC2_5_IRQHandler [WEAK]
+ EXPORT LEDTS0_0_IRQHandler [WEAK]
+ EXPORT FCE0_0_IRQHandler [WEAK]
+ EXPORT GPDMA0_0_IRQHandler [WEAK]
+ EXPORT SDMMC0_0_IRQHandler [WEAK]
+ EXPORT USB0_0_IRQHandler [WEAK]
+ EXPORT ETH0_0_IRQHandler [WEAK]
+ EXPORT GPDMA1_0_IRQHandler [WEAK]\r
+\r
+
+SCU_0_IRQHandler
+ERU0_0_IRQHandler
+ERU0_1_IRQHandler
+ERU0_2_IRQHandler
+ERU0_3_IRQHandler
+ERU1_0_IRQHandler
+ERU1_1_IRQHandler
+ERU1_2_IRQHandler
+ERU1_3_IRQHandler
+PMU0_0_IRQHandler
+VADC0_C0_0_IRQHandler
+VADC0_C0_1_IRQHandler
+VADC0_C0_2_IRQHandler
+VADC0_C0_3_IRQHandler
+VADC0_G0_0_IRQHandler
+VADC0_G0_1_IRQHandler
+VADC0_G0_2_IRQHandler
+VADC0_G0_3_IRQHandler
+VADC0_G1_0_IRQHandler
+VADC0_G1_1_IRQHandler
+VADC0_G1_2_IRQHandler
+VADC0_G1_3_IRQHandler
+VADC0_G2_0_IRQHandler
+VADC0_G2_1_IRQHandler
+VADC0_G2_2_IRQHandler
+VADC0_G2_3_IRQHandler
+VADC0_G3_0_IRQHandler
+VADC0_G3_1_IRQHandler
+VADC0_G3_2_IRQHandler
+VADC0_G3_3_IRQHandler
+DSD0_0_IRQHandler
+DSD0_1_IRQHandler
+DSD0_2_IRQHandler
+DSD0_3_IRQHandler
+DSD0_4_IRQHandler
+DSD0_5_IRQHandler
+DSD0_6_IRQHandler
+DSD0_7_IRQHandler
+DAC0_0_IRQHandler
+DAC0_1_IRQHandler
+CCU40_0_IRQHandler
+CCU40_1_IRQHandler
+CCU40_2_IRQHandler
+CCU40_3_IRQHandler
+CCU41_0_IRQHandler
+CCU41_1_IRQHandler
+CCU41_2_IRQHandler
+CCU41_3_IRQHandler
+CCU42_0_IRQHandler
+CCU42_1_IRQHandler
+CCU42_2_IRQHandler
+CCU42_3_IRQHandler
+CCU43_0_IRQHandler
+CCU43_1_IRQHandler
+CCU43_2_IRQHandler
+CCU43_3_IRQHandler
+CCU80_0_IRQHandler
+CCU80_1_IRQHandler
+CCU80_2_IRQHandler
+CCU80_3_IRQHandler
+CCU81_0_IRQHandler
+CCU81_1_IRQHandler
+CCU81_2_IRQHandler
+CCU81_3_IRQHandler
+POSIF0_0_IRQHandler
+POSIF0_1_IRQHandler
+POSIF1_0_IRQHandler
+POSIF1_1_IRQHandler
+CAN0_0_IRQHandler
+CAN0_1_IRQHandler
+CAN0_2_IRQHandler
+CAN0_3_IRQHandler
+CAN0_4_IRQHandler
+CAN0_5_IRQHandler
+CAN0_6_IRQHandler
+CAN0_7_IRQHandler
+USIC0_0_IRQHandler
+USIC0_1_IRQHandler
+USIC0_2_IRQHandler
+USIC0_3_IRQHandler
+USIC0_4_IRQHandler
+USIC0_5_IRQHandler
+USIC1_0_IRQHandler
+USIC1_1_IRQHandler
+USIC1_2_IRQHandler
+USIC1_3_IRQHandler
+USIC1_4_IRQHandler
+USIC1_5_IRQHandler
+USIC2_0_IRQHandler
+USIC2_1_IRQHandler
+USIC2_2_IRQHandler
+USIC2_3_IRQHandler
+USIC2_4_IRQHandler
+USIC2_5_IRQHandler
+LEDTS0_0_IRQHandler
+FCE0_0_IRQHandler
+GPDMA0_0_IRQHandler
+SDMMC0_0_IRQHandler
+USB0_0_IRQHandler
+ETH0_0_IRQHandler
+GPDMA1_0_IRQHandler \r
+
+
+;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
+
+;* Definition of the default weak SystemInit_DAVE3 function.
+;* This function will be called by the CMSIS SystemInit function.
+;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3
+;* which will overule this weak definition
+
+;*SystemInit_DAVE3
+;* NOP
+;* BX LR
+
+;*******************************************************************************\r
+; User Stack and Heap initialization\r
+;*******************************************************************************\r
+ IF :DEF:__MICROLIB \r
+ \r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+ \r
+ ELSE\r
+ \r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+ \r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+\r
+ ENDIF\r
+\r
+ ALIGN\r
+ END\r
+\r
+;******************* (C) COPYRIGHT 2011 Infineon Techonlogies *****END OF FILE*****\r
+\r
+
projects / freertos / commitdiff