#
/MLO
+/SPL
/System.map
/u-boot
/u-boot.hex
/u-boot.imx
+/u-boot-with-spl.imx
+/u-boot-with-nand-spl.imx
/u-boot.map
/u-boot.srec
/u-boot.ldr
mx53smd i.MX53
mx6qsabresd i.MX6Q
mx6qsabreauto i.MX6Q
+ wandboard i.MX6DL/S
Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
devkit3250 lpc32xx
-Zhong Hongbo <bocui107@gmail.com>
-
- SMDK6400 ARM1176 (S3C6400 SoC)
-
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Tetsuyuki Kobayashi <koba@kmckk.co.jp>
HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \
sed -e 's/\(cygwin\).*/cygwin/')
-# Set shell to bash if possible, otherwise fall back to sh
-SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
- else if [ -x /bin/bash ]; then echo /bin/bash; \
- else echo sh; fi; fi)
-
-export HOSTARCH HOSTOS SHELL
+export HOSTARCH HOSTOS
# Deal with colliding definitions from tcsh etc.
VENDOR=
LIBS-y += drivers/bios_emulator/libatibiosemu.o
LIBS-y += drivers/block/libblock.o
LIBS-$(CONFIG_BOOTCOUNT_LIMIT) += drivers/bootcount/libbootcount.o
+LIBS-y += drivers/crypto/libcrypto.o
LIBS-y += drivers/dma/libdma.o
LIBS-y += drivers/fpga/libfpga.o
LIBS-y += drivers/gpio/libgpio.o
$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(or $(CONFIG_SPL_PAD_TO),0) \
- -O binary $(obj)spl/u-boot-spl \
- $(obj)spl/u-boot-spl-pad.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
+ -I binary -O binary $< $(obj)spl/u-boot-spl-pad.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
rm $(obj)spl/u-boot-spl-pad.bin
+$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
+ $(OBJTREE)/u-boot-with-spl.imx
+
+$(obj)u-boot-with-nand-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
+ $(OBJTREE)/u-boot-with-nand-spl.imx
+
$(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin
$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
-e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl
lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
-#########################################################################
-## ARM1176 Systems
-#########################################################################
-smdk6400_noUSB_config \
-smdk6400_config : unconfig
- @mkdir -p $(obj)include $(obj)board/samsung/smdk6400
- @mkdir -p $(obj)nand_spl/board/samsung/smdk6400
- @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
- @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
- @if [ -z "$(findstring smdk6400_noUSB_config,$@)" ]; then \
- echo "RAM_TEXT = 0x57e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\
- else \
- echo "RAM_TEXT = 0xc7e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\
- fi
- @$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx
- @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
-
#########################################################################
#########################################################################
@rm -f $(obj)u-boot.kwb
@rm -f $(obj)u-boot.pbl
@rm -f $(obj)u-boot.imx
+ @rm -f $(obj)u-boot-with-spl.imx
+ @rm -f $(obj)u-boot-with-nand-spl.imx
@rm -f $(obj)u-boot.ubl
@rm -f $(obj)u-boot.ais
@rm -f $(obj)u-boot.dtb
boot loader that has already initialized the UART. Define this
variable to flush the UART at init time.
- CONFIG_SYS_NS16550_BROKEN_TEMT
-
- 16550 UART set the Transmitter Empty (TEMT) Bit when all output
- has finished and the transmitter is totally empty. U-Boot waits
- for this bit to be set to initialize the serial console. On some
- broken platforms this bit is not set in SPL making U-Boot to
- hang while waiting for TEMT. Define this option to avoid it.
-
- Console Interface:
Depending on board, define exactly one serial port
Support for lib/libgeneric.o in SPL binary
CONFIG_SPL_PAD_TO
- Linker address to which the SPL should be padded before
- appending the SPL payload.
+ Image offset to which the SPL should be padded before appending
+ the SPL payload. By default, this is defined as
+ CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
+ CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
+ payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
CONFIG_SPL_TARGET
Final target image containing SPL and payload. Some SPLs
- CONFIG_SYS_SRIOn_MEM_SIZE:
Size of SRIO port 'n' memory region
-- CONFIG_SYS_NDFC_16
- Defined to tell the NDFC that the NAND chip is using a
- 16 bit bus.
+- CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ Defined to tell the NAND controller that the NAND chip is using
+ a 16 bit bus.
+ Not all NAND drivers use this symbol.
+ Example of drivers that use it:
+ - drivers/mtd/nand/ndfc.c
+ - drivers/mtd/nand/mxc_nand.c
- CONFIG_SYS_NDFC_EBC0_CFG
Sets the EBC0_CFG register for the NDFC. If not defined
endif
# needed for relocation
-ifndef CONFIG_NAND_SPL
LDFLAGS_u-boot += -pie
-endif
#
# FIXME: binutils versions < 2.22 have a bug in the assembler where
# =========================================================================
PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+
+ifneq ($(CONFIG_IMX_CONFIG),)
+ifdef CONFIG_SPL
ifdef CONFIG_SPL_BUILD
ALL-y += $(OBJTREE)/SPL
endif
+else
+ALL-y += $(obj)u-boot.imx
+endif
+endif
*/
#include <common.h>
+#include <asm/io.h>
#include <asm/arch/bits.h>
#include <asm/arch/omap2420.h>
+#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
#define TIMER_LOAD_VAL 0
/* macro to read the 32 bit timer */
-#define READ_TIMER (*((volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR)))
+#define READ_TIMER readl(CONFIG_SYS_TIMERBASE+TCRR) \
+ / (TIMER_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
gd->arch.tbl += (now - gd->arch.lastinc);
} else {
/* we have rollover of incrementer */
- gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
+ gd->arch.tbl += ((0xFFFFFFFF / (TIMER_CLOCK / CONFIG_SYS_HZ))
+ - gd->arch.lastinc) + now;
}
gd->arch.lastinc = now;
return gd->arch.tbl;
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
-.global _image_copy_end_ofs
+.globl _image_copy_end_ofs
_image_copy_end_ofs:
- .word __image_copy_end - _start
+ .word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
blo fixloop
- bx lr
-
#endif
relocate_done:
.text :
{
__start = .;
- arch/arm/cpu/arm1136/start.o (.text)
+ arch/arm/cpu/arm1136/start.o (.text*)
*(.text*)
} >.sram
return 0;
}
-ulong get_timer(ulong base)
+ulong get_timer_us(ulong base)
{
struct bcm2835_timer_regs *regs =
(struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR;
return readl(®s->clo) - base;
}
+ulong get_timer(ulong base)
+{
+ ulong us = get_timer_us(0);
+ us /= (1000000 / CONFIG_SYS_HZ);
+ us -= base;
+ return us;
+}
+
unsigned long long get_ticks(void)
{
return get_timer(0);
ulong endtime;
signed long diff;
- endtime = get_timer(0) + usec;
+ endtime = get_timer_us(0) + usec;
do {
- ulong now = get_timer(0);
+ ulong now = get_timer_us(0);
diff = endtime - now;
} while (diff >= 0);
}
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(SOC).o
-
-SOBJS = reset.o
-
-COBJS-$(CONFIG_S3C6400) += cpu_init.o speed.o
-COBJS-y += timer.o init.o
-
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all: $(obj).depend $(START) $(LIB)
-
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-# Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -march=armv5t
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
- $(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+++ /dev/null
-/*
- * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
- *
- * Copyright (C) 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/s3c6400.h>
-
- .globl mem_ctrl_asm_init
-mem_ctrl_asm_init:
- /* DMC1 base address 0x7e001000 */
- ldr r0, =ELFIN_DMC1_BASE
-
- ldr r1, =0x4
- str r1, [r0, #INDEX_DMC_MEMC_CMD]
-
- ldr r1, =DMC_DDR_REFRESH_PRD
- str r1, [r0, #INDEX_DMC_REFRESH_PRD]
-
- ldr r1, =DMC_DDR_CAS_LATENCY
- str r1, [r0, #INDEX_DMC_CAS_LATENCY]
-
- ldr r1, =DMC_DDR_t_DQSS
- str r1, [r0, #INDEX_DMC_T_DQSS]
-
- ldr r1, =DMC_DDR_t_MRD
- str r1, [r0, #INDEX_DMC_T_MRD]
-
- ldr r1, =DMC_DDR_t_RAS
- str r1, [r0, #INDEX_DMC_T_RAS]
-
- ldr r1, =DMC_DDR_t_RC
- str r1, [r0, #INDEX_DMC_T_RC]
-
- ldr r1, =DMC_DDR_t_RCD
- ldr r2, =DMC_DDR_schedule_RCD
- orr r1, r1, r2
- str r1, [r0, #INDEX_DMC_T_RCD]
-
- ldr r1, =DMC_DDR_t_RFC
- ldr r2, =DMC_DDR_schedule_RFC
- orr r1, r1, r2
- str r1, [r0, #INDEX_DMC_T_RFC]
-
- ldr r1, =DMC_DDR_t_RP
- ldr r2, =DMC_DDR_schedule_RP
- orr r1, r1, r2
- str r1, [r0, #INDEX_DMC_T_RP]
-
- ldr r1, =DMC_DDR_t_RRD
- str r1, [r0, #INDEX_DMC_T_RRD]
-
- ldr r1, =DMC_DDR_t_WR
- str r1, [r0, #INDEX_DMC_T_WR]
-
- ldr r1, =DMC_DDR_t_WTR
- str r1, [r0, #INDEX_DMC_T_WTR]
-
- ldr r1, =DMC_DDR_t_XP
- str r1, [r0, #INDEX_DMC_T_XP]
-
- ldr r1, =DMC_DDR_t_XSR
- str r1, [r0, #INDEX_DMC_T_XSR]
-
- ldr r1, =DMC_DDR_t_ESR
- str r1, [r0, #INDEX_DMC_T_ESR]
-
- ldr r1, =DMC1_MEM_CFG
- str r1, [r0, #INDEX_DMC_MEMORY_CFG]
-
- ldr r1, =DMC1_MEM_CFG2
- str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
-
- ldr r1, =DMC1_CHIP0_CFG
- str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
-
- ldr r1, =DMC_DDR_32_CFG
- str r1, [r0, #INDEX_DMC_USER_CONFIG]
-
- /* DMC0 DDR Chip 0 configuration direct command reg */
- ldr r1, =DMC_NOP0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
- /* Precharge All */
- ldr r1, =DMC_PA0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
- /* Auto Refresh 2 time */
- ldr r1, =DMC_AR0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
- /* MRS */
- ldr r1, =DMC_mDDR_EMR0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
- /* Mode Reg */
- ldr r1, =DMC_mDDR_MR0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
- /* Enable DMC1 */
- mov r1, #0x0
- str r1, [r0, #INDEX_DMC_MEMC_CMD]
-
-check_dmc1_ready:
- ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
- mov r2, #0x3
- and r1, r1, r2
- cmp r1, #0x1
- bne check_dmc1_ready
- nop
-
- mov pc, lr
-
- .ltorg
+++ /dev/null
-/*
- * (C) Copyright 2012 Ashok Kumar Reddy Kourla
- * ashokkourla2000@gmail.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include<common.h>
-
-int arch_cpu_init(void)
-{
- icache_enable();
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (c) 2009 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/s3c6400.h>
-
-.globl reset_cpu
-reset_cpu:
- ldr r1, =ELFIN_CLOCK_POWER_BASE
- ldr r2, [r1, #SYS_ID_OFFSET]
- ldr r3, =0xffff
- and r2, r3, r2, lsr #12
- str r2, [r1, #SW_RST_OFFSET]
-_loop_forever:
- b _loop_forever
+++ /dev/null
-/*
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This code should work for both the S3C2400 and the S3C2410
- * as they seem to have the same PLL and clock machinery inside.
- * The different address mapping is handled by the s3c24xx.h files below.
- */
-
-#include <common.h>
-#include <asm/arch/s3c6400.h>
-
-#define APLL 0
-#define MPLL 1
-#define EPLL 2
-
-/* ------------------------------------------------------------------------- */
-/*
- * NOTE: This describes the proper use of this file.
- *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- * the specified bus in HZ.
- */
-/* ------------------------------------------------------------------------- */
-
-static ulong get_PLLCLK(int pllreg)
-{
- ulong r, m, p, s;
-
- switch (pllreg) {
- case APLL:
- r = APLL_CON_REG;
- break;
- case MPLL:
- r = MPLL_CON_REG;
- break;
- case EPLL:
- r = EPLL_CON0_REG;
- break;
- default:
- hang();
- }
-
- m = (r >> 16) & 0x3ff;
- p = (r >> 8) & 0x3f;
- s = r & 0x7;
-
- return m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s)));
-}
-
-/* return ARMCORE frequency */
-ulong get_ARMCLK(void)
-{
- ulong div;
-
- div = CLK_DIV0_REG;
-
- return get_PLLCLK(APLL) / ((div & 0x7) + 1);
-}
-
-/* return FCLK frequency */
-ulong get_FCLK(void)
-{
- return get_PLLCLK(APLL);
-}
-
-/* return HCLK frequency */
-ulong get_HCLK(void)
-{
- ulong fclk;
-
- uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
- uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1;
-
- /*
- * Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on
- * s3c6400 and is always 0, and it is indeed running in ASYNC mode
- */
- if (OTHERS_REG & 0x80)
- fclk = get_FCLK(); /* SYNC Mode */
- else
- fclk = get_PLLCLK(MPLL); /* ASYNC Mode */
-
- return fclk / (hclk_div * hclkx2_div);
-}
-
-/* return PCLK frequency */
-ulong get_PCLK(void)
-{
- ulong fclk;
- uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
- uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1;
-
- if (OTHERS_REG & 0x80)
- fclk = get_FCLK(); /* SYNC Mode */
- else
- fclk = get_PLLCLK(MPLL); /* ASYNC Mode */
-
- return fclk / (hclkx2_div * pre_div);
-}
-
-/* return UCLK frequency */
-ulong get_UCLK(void)
-{
- return get_PLLCLK(EPLL);
-}
-
-int print_cpuinfo(void)
-{
- printf("\nCPU: S3C6400@%luMHz\n", get_ARMCLK() / 1000000);
- printf(" Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ",
- get_FCLK() / 1000000, get_HCLK() / 1000000,
- get_PCLK() / 1000000);
-
- if (OTHERS_REG & 0x80)
- printf("(SYNC Mode) \n");
- else
- printf("(ASYNC Mode) \n");
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/proc-armv/ptrace.h>
-#include <asm/arch/s3c6400.h>
-#include <div64.h>
-
-static ulong timer_load_val;
-
-#define PRESCALER 167
-
-static s3c64xx_timers *s3c64xx_get_base_timers(void)
-{
- return (s3c64xx_timers *)ELFIN_TIMER_BASE;
-}
-
-/* macro to read the 16 bit timer */
-static inline ulong read_timer(void)
-{
- s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
- return timers->TCNTO4;
-}
-
-/* Internal tick units */
-/* Last decremneter snapshot */
-static unsigned long lastdec;
-/* Monotonic incrementing timer */
-static unsigned long long timestamp;
-
-int timer_init(void)
-{
- s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
- /* use PWM Timer 4 because it has no output */
- /*
- * We use the following scheme for the timer:
- * Prescaler is hard fixed at 167, divider at 1/4.
- * This gives at PCLK frequency 66MHz approx. 10us ticks
- * The timer is set to wrap after 100s, at 66MHz this obviously
- * happens after 10,000,000 ticks. A long variable can thus
- * keep values up to 40,000s, i.e., 11 hours. This should be
- * enough for most uses:-) Possible optimizations: select a
- * binary-friendly frequency, e.g., 1ms / 128. Also calculate
- * the prescaler automatically for other PCLK frequencies.
- */
- timers->TCFG0 = PRESCALER << 8;
- if (timer_load_val == 0) {
- timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
- timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000;
- }
-
- /* load value for 10 ms timeout */
- lastdec = timers->TCNTB4 = timer_load_val;
- /* auto load, manual update of Timer 4 */
- timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
- TCON_4_UPDATE;
-
- /* auto load, start Timer 4 */
- timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
- timestamp = 0;
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- ulong now = read_timer();
-
- if (lastdec >= now) {
- /* normal mode */
- timestamp += lastdec - now;
- } else {
- /* we have an overflow ... */
- timestamp += lastdec + timer_load_val - now;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- /* We overrun in 100s */
- return (ulong)(timer_load_val / 100);
-}
-
-ulong get_timer_masked(void)
-{
- unsigned long long res = get_ticks();
- do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ)));
- return res;
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long tmp;
- ulong tmo;
-
- tmo = (usec + 9) / 10;
- tmp = get_ticks() + tmo; /* get current timestamp */
-
- while (get_ticks() < tmp)/* loop till event */
- /*NOP*/;
-}
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
-#ifdef CONFIG_ENABLE_MMU
-#include <asm/proc/domain.h>
-#endif
-#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
+#ifndef CONFIG_SYS_PHY_UBOOT_BASE
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
#endif
.globl _start
_start: b reset
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
-
-/*
- * Below variable is very important because we use MMU in U-Boot.
- * Without it, we cannot run code correctly before MMU is ON.
- * by scsuh.
- */
-_TEXT_PHY_BASE:
- .word CONFIG_SYS_PHY_UBOOT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
* When booting from NAND - it has definitely been a reset, so, no need
* to flush caches and disable the MMU
*/
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
/*
* flush v4 I/D caches
*/
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
blo fixloop
#endif
-#ifdef CONFIG_ENABLE_MMU
-enable_mmu:
- /* enable domain access */
- ldr r5, =0x0000ffff
- mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
-
- /* Set the TTB register */
- ldr r0, _mmu_table_base
- ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
- ldr r2, =0xfff00000
- bic r0, r0, r2
- orr r1, r0, r1
- mcr p15, 0, r1, c2, c0, 0
-
- /* Enable the MMU */
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #1 /* Set CR_M to enable MMU */
-
- /* Prepare to enable the MMU */
- adr r1, skip_hw_init
- and r1, r1, #0x3fc
- ldr r2, _TEXT_BASE
- ldr r3, =0xfff00000
- and r2, r2, r3
- orr r2, r2, r1
- b mmu_enable
-
- .align 5
- /* Run in a single cache-line */
-mmu_enable:
-
- mcr p15, 0, r0, c1, c0, 0
- nop
- nop
- mov pc, r2
-skip_hw_init:
-#endif
-
relocate_done:
bx lr
_dynsym_start_ofs:
.word __dynsym_start - _start
-#ifdef CONFIG_ENABLE_MMU
-_mmu_table_base:
- .word mmu_table
-#endif
-
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
mov pc, lr
-#ifndef CONFIG_NAND_SPL
-/*
- * we assume that cache operation is done before. (eg. cleanup_before_linux())
- * actually, we don't need to do anything about cache if not use d-cache in
- * U-Boot. So, in this function we clean only MMU. by scsuh
- *
- * void theLastJump(void *kernel, int arch_num, uint boot_params);
- */
-#ifdef CONFIG_ENABLE_MMU
- .globl theLastJump
-theLastJump:
- mov r9, r0
- ldr r3, =0xfff00000
- ldr r4, _TEXT_PHY_BASE
- adr r5, phy_last_jump
- bic r5, r5, r3
- orr r5, r5, r4
- mov pc, r5
-phy_last_jump:
- /*
- * disable MMU stuff
- */
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
- bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
- orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
- orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
- mcr p15, 0, r0, c1, c0, 0
-
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
-
- mov r0, #0
- mov pc, r9
-#endif
-
-
+#ifndef CONFIG_SPL_BUILD
/*
*************************************************************************
*
get_bad_stack
bad_save_user_regs
bl do_fiq
-#endif /* CONFIG_NAND_SPL */
+#endif /* CONFIG_SPL_BUILD */
.globl _TEXT_BASE
_TEXT_BASE:
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm920t/start.o (.text)
+ arch/arm/cpu/arm920t/start.o (.text*)
/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
. = 0x1000;
LONG(0x53555243)
- *(.text)
+ *(.text*)
}
. = ALIGN(4);
- .rodata : { *(.rodata) }
+ .rodata : { *(.rodata*) }
. = ALIGN(4);
- .data : { *(.data) }
+ .data : { *(.data*) }
. = ALIGN(4);
.got : { *(.got) }
}
. = ALIGN(4);
+
+ __image_copy_end = .;
+
__bss_start = .;
- .bss : { *(.bss) }
+ .bss : { *(.bss*) }
__bss_end = .;
_end = .;
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
ifneq ($(CONFIG_IMX_CONFIG),)
-
+ifdef CONFIG_SPL
+ifdef CONFIG_SPL_BUILD
+ALL-y += $(OBJTREE)/SPL
+endif
+else
ALL-y += $(obj)u-boot.imx
-
+endif
endif
0x00000000, 0x00000000, 0x00010101, 0x01010101,
0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
0x00000100, 0x00000100, 0x00000000, 0x00000002,
- 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
- 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612,
+ 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
+ 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
0x00000003, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000612, 0x01000F02,
- 0x06120612, 0x00000200, 0x00020007, 0xf5014b27,
- 0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300,
- 0x07000300, 0x07000300, 0x07000300, 0x00000006,
+ 0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
+ 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300,
+ 0x07000300, 0x07400300, 0x07400300, 0x00000005,
0x00000000, 0x00000000, 0x01000000, 0x01020408,
0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00010000, 0x00020304,
- 0x00000004, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00010000, 0x00030404,
+ 0x00000003, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x01010000,
0x01000000, 0x03030000, 0x00010303, 0x01020202,
0x00000000, 0x02040303, 0x21002103, 0x00061200,
- 0x06120612, 0x04320432, 0x04320432, 0x00040004,
+ 0x06120612, 0x04420442, 0x04420442, 0x00040004,
0x00040004, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00010001
+ 0x00000000, 0xffffffff
/*
* i.MX23 DDR at 133MHz
.globl _TEXT_BASE
_TEXT_BASE:
+#ifdef CONFIG_SPL_TEXT_BASE
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm926ejs/mxs/start.o (.text)
- *(.text)
+ arch/arm/cpu/arm926ejs/mxs/start.o (.text*)
+ *(.text*)
}
. = ALIGN(4);
. = ALIGN(4);
.data : {
- *(.data)
+ *(.data*)
}
. = ALIGN(4);
*/
#include <common.h>
+#include <asm/io.h>
-#define TIMER_LOAD_VAL 0xffffffff
+#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
+#define TIMER_LOAD_VAL 0xffffffff
/* macro to read the 32 bit timer */
-#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8))
+#define READ_TIMER readl(CONFIG_SYS_TIMERBASE+8) \
+ / (TIMER_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
* (TLV-now) amount of time after passing though -1
* nts = new "advancing time stamp"...it could also roll and cause problems.
*/
- timestamp += lastdec + TIMER_LOAD_VAL - now;
+ timestamp += lastdec + (TIMER_LOAD_VAL / (TIMER_CLOCK /
+ CONFIG_SYS_HZ)) - now;
}
lastdec = now;
*/
ulong get_tbclk (void)
{
- ulong tbclk;
-
- tbclk = CONFIG_SYS_HZ;
- return tbclk;
+ return CONFIG_SYS_HZ;
}
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm926ejs/spear/start.o (.text)
- *(.text)
+ arch/arm/cpu/arm926ejs/spear/start.o (.text*)
+ *(.text*)
}
. = ALIGN(4);
. = ALIGN(4);
.data : {
- *(.data)
+ *(.data*)
}
. = ALIGN(4);
.globl _TEXT_BASE
_TEXT_BASE:
-#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
- .word CONFIG_SYS_TEXT_BASE
-#else
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
#endif
-#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
_end_ofs:
.word _end - _start
-#ifdef CONFIG_NAND_U_BOOT
-.globl _end
-_end:
- .word __bss_end
-#endif
-
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
/*------------------------------------------------------------------------------*/
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL)
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- sub r9, r6, r0 /* r9 <- relocation offset */
- cmp r0, r6
- moveq r9, #0 /* no relocation. offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
bx lr
+#ifndef CONFIG_SPL_BUILD
+
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
.globl _TEXT_BASE
_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE /* address of _start in the linked image */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
+ .word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
;
+ /* MMC1 */
+ writel(PRCM_MOD_EN, &cmper->mmc1clkctrl);
+ while (readl(&cmper->mmc1clkctrl) != PRCM_MOD_EN)
+ ;
+
/* i2c0 */
writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/cpu.h>
-#include <asm/arch/omap_gpmc.h>
+#include <asm/omap_gpmc.h>
#include <asm/arch/elm.h>
#define ELM_DEFAULT_POLY (0)
PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
ifneq ($(CONFIG_IMX_CONFIG),)
+ifdef CONFIG_SPL
+ifdef CONFIG_SPL_BUILD
+ALL-y += $(OBJTREE)/SPL
+endif
+else
ALL-y += $(obj)u-boot.imx
endif
+endif
#include <asm/arch/clk.h>
#include <asm/arch/periph.h>
+/* *
+ * This structure is to store the src bit, div bit and prediv bit
+ * positions of the peripheral clocks of the src and div registers
+ */
+struct clk_bit_info {
+ int8_t src_bit;
+ int8_t div_bit;
+ int8_t prediv_bit;
+};
+
+/* src_bit div_bit prediv_bit */
+static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
+ {0, 0, -1},
+ {4, 4, -1},
+ {8, 8, -1},
+ {12, 12, -1},
+ {0, 0, 8},
+ {4, 16, 24},
+ {8, 0, 8},
+ {12, 16, 24},
+ {-1, -1, -1},
+ {16, 0, 8},
+ {20, 16, 24},
+ {24, 0, 8},
+ {0, 0, 4},
+ {4, 12, 16},
+ {-1, -1, -1},
+ {-1, -1, -1},
+ {-1, 24, 0},
+ {-1, 24, 0},
+ {-1, 24, 0},
+ {-1, 24, 0},
+ {-1, 24, 0},
+ {-1, 24, 0},
+ {-1, 24, 0},
+ {-1, 24, 0},
+ {24, 0, -1},
+ {24, 0, -1},
+ {24, 0, -1},
+ {24, 0, -1},
+ {24, 0, -1},
+};
+
/* Epll Clock division values to achive different frequency output */
static struct set_epll_con_val exynos5_epll_div[] = {
{ 192000000, 0, 48, 3, 1, 0 },
return fout;
}
+static unsigned long exynos5_get_periph_rate(int peripheral)
+{
+ struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
+ unsigned long sclk, sub_clk;
+ unsigned int src, div, sub_div;
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ src = readl(&clk->src_peric0);
+ div = readl(&clk->div_peric0);
+ break;
+ case PERIPH_ID_PWM0:
+ case PERIPH_ID_PWM1:
+ case PERIPH_ID_PWM2:
+ case PERIPH_ID_PWM3:
+ case PERIPH_ID_PWM4:
+ src = readl(&clk->src_peric0);
+ div = readl(&clk->div_peric3);
+ break;
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ src = readl(&clk->src_peric1);
+ div = readl(&clk->div_peric1);
+ break;
+ case PERIPH_ID_SPI2:
+ src = readl(&clk->src_peric1);
+ div = readl(&clk->div_peric2);
+ break;
+ case PERIPH_ID_SPI3:
+ case PERIPH_ID_SPI4:
+ src = readl(&clk->sclk_src_isp);
+ div = readl(&clk->sclk_div_isp);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC3:
+ src = readl(&clk->src_fsys);
+ div = readl(&clk->div_fsys1);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ sclk = exynos5_get_pll_clk(MPLL);
+ sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
+ & 0x7) + 1;
+ div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
+ & 0x7) + 1;
+ return (sclk / sub_div) / div;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ };
+
+ src = (src >> bit_info->src_bit) & 0xf;
+
+ switch (src) {
+ case EXYNOS_SRC_MPLL:
+ sclk = exynos5_get_pll_clk(MPLL);
+ break;
+ case EXYNOS_SRC_EPLL:
+ sclk = exynos5_get_pll_clk(EPLL);
+ break;
+ case EXYNOS_SRC_VPLL:
+ sclk = exynos5_get_pll_clk(VPLL);
+ break;
+ default:
+ return 0;
+ }
+
+ /* Ratio clock division for this peripheral */
+ sub_div = (div >> bit_info->div_bit) & 0xf;
+ sub_clk = sclk / (sub_div + 1);
+
+ /* Pre-ratio clock division for SDMMC0 and 2 */
+ if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
+ div = (div >> bit_info->prediv_bit) & 0xff;
+ return sub_clk / (div + 1);
+ }
+
+ return sub_clk;
+}
+
+unsigned long clock_get_periph_rate(int peripheral)
+{
+ if (cpu_is_exynos5())
+ return exynos5_get_periph_rate(peripheral);
+ else
+ return 0;
+}
+
/* exynos4: return ARM clock frequency */
static unsigned long exynos4_get_arm_clk(void)
{
return pclk;
}
-/* exynos5: return pwm clock frequency */
-static unsigned long exynos5_get_pwm_clk(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long pclk, sclk;
- unsigned int ratio;
-
- /*
- * CLK_DIV_PERIC3
- * PWM_RATIO [3:0]
- */
- ratio = readl(&clk->div_peric3);
- ratio = ratio & 0xf;
- sclk = get_pll_clk(MPLL);
-
- pclk = sclk / (ratio + 1);
-
- return pclk;
-}
-
/* exynos4: return uart clock frequency */
static unsigned long exynos4_get_uart_clk(int dev_index)
{
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5())
- return exynos5_get_pwm_clk();
+ return clock_get_periph_rate(PERIPH_ID_PWM0);
else {
if (proid_is_exynos4412())
return exynos4x12_get_pwm_clk();
#include <common.h>
#include <asm/io.h>
+#include <asm/system.h>
+
+enum l2_cache_params {
+ CACHE_TAG_RAM_SETUP = (1 << 9),
+ CACHE_DATA_RAM_SETUP = (1 << 5),
+ CACHE_TAG_RAM_LATENCY = (2 << 6),
+ CACHE_DATA_RAM_LATENCY = (2 << 0)
+};
void reset_cpu(ulong addr)
{
dcache_enable();
}
#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+/*
+ * Set L2 cache parameters
+ */
+static void exynos5_set_l2cache_params(void)
+{
+ unsigned int val = 0;
+
+ asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
+
+ val |= CACHE_TAG_RAM_SETUP |
+ CACHE_DATA_RAM_SETUP |
+ CACHE_TAG_RAM_LATENCY |
+ CACHE_DATA_RAM_LATENCY;
+
+ asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
+}
+
+/*
+ * Sets L2 cache related parameters before enabling data cache
+ */
+void v7_outer_cache_enable(void)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_l2cache_params();
+}
+#endif
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00015154
str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, =0x02888945
- orr r1, r1, #(1 << 16)
+ ldr r1, =0x02898945
str r1, [r0, #CLKCTL_CBCDR]
/* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x00808145
- orr r1, r1, #(2 << 10)
- orr r1, r1, #(0 << 16)
- orr r1, r1, #(1 << 19)
+ ldr r1, =0x00888945
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x00016154
return (type << 12) | (reg + 0x10);
}
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+ u32 cpurev = get_cpu_rev();
+ u32 type = ((cpurev >> 12) & 0xff);
+ if (type == MXC_CPU_MX6SOLO)
+ cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
+
+ return cpurev;
+}
+#endif
+
void init_aips(void)
{
struct aipstz_regs *aips1, *aips2;
/*
* Putting EMIF in HW_AUTO is seen to be causing issues with
- * EMIF clocks and the master DLL. Put EMIF in SW_WKUP
+ * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
* in OMAP5430 ES1.0 silicon
*/
if (omap_rev != OMAP5430_ES1_0) {
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
- clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
+ clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
return phy;
}
-static u32 get_emif_mem_size(struct emif_device_details *devices)
+static u32 get_emif_mem_size(u32 base)
{
u32 size_mbytes = 0, temp;
+ struct emif_device_details dev_details;
+ struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
+ u32 emif_nr = emif_num(base);
- if (!devices)
- return 0;
+ emif_reset_phy(base);
+ dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
+ &cs0_dev_details);
+ dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
+ &cs1_dev_details);
+ emif_reset_phy(base);
- if (devices->cs0_device_details) {
- temp = devices->cs0_device_details->density;
+ if (dev_details.cs0_device_details) {
+ temp = dev_details.cs0_device_details->density;
size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
}
- if (devices->cs1_device_details) {
- temp = devices->cs1_device_details->density;
+ if (dev_details.cs1_device_details) {
+ temp = dev_details.cs1_device_details->density;
size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
}
/* convert to bytes */
/* Return if no devices on this EMIF */
if (!dev_details.cs0_device_details &&
!dev_details.cs1_device_details) {
- emif_sizes[emif_nr - 1] = 0;
return;
}
- if (!in_sdram)
- emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
-
/*
* Get device timings:
* - Default timings specified by JESD209-2 if
mapped_size = 0;
section_cnt = 3;
sys_addr = CONFIG_SYS_SDRAM_BASE;
- emif1_size = emif_sizes[0];
- emif2_size = emif_sizes[1];
+ emif1_size = get_emif_mem_size(EMIF1_BASE);
+ emif2_size = get_emif_mem_size(EMIF2_BASE);
debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
if (!emif1_size && !emif2_size)
ldr r3, =boot_params
strb r2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r1
- /* boot mode is passed only for devices that can raw/fat mode */
- cmp r2, #BOOT_DEVICE_XIP
+ /*
+ * boot mode is only valid for device that can be raw or FAT booted.
+ * in other cases it may be fatal to look. While platforms differ
+ * in the values used for each MMC slot, they are contiguous.
+ */
+ cmp r2, #MMC_BOOT_DEVICES_START
blt 2f
- cmp r2, #BOOT_DEVICE_MMC2
+ cmp r2, #MMC_BOOT_DEVICES_END
bgt 2f
/* Store the boot mode (raw/FAT) in omap_bootmode */
ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr
.text :
{
__start = .;
- arch/arm/cpu/armv7/start.o (.text)
+ arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sram
*****************************************************************************/
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
- if (argc != 2)
+ if (argc < 2 || argc > 3)
goto usage;
- if (strncmp(argv[1], "hw", 2) == 0)
- omap_nand_switch_ecc(1);
- else if (strncmp(argv[1], "sw", 2) == 0)
- omap_nand_switch_ecc(0);
- else
+
+ if (strncmp(argv[1], "hw", 2) == 0) {
+ if (argc == 2) {
+ omap_nand_switch_ecc(1, 1);
+ } else {
+ if (strncmp(argv[2], "hamming", 7) == 0)
+ omap_nand_switch_ecc(1, 1);
+ else if (strncmp(argv[2], "bch8", 4) == 0)
+ omap_nand_switch_ecc(1, 8);
+ else
+ goto usage;
+ }
+ } else if (strncmp(argv[1], "sw", 2) == 0) {
+ omap_nand_switch_ecc(0, 0);
+ } else {
goto usage;
+ }
return 0;
}
U_BOOT_CMD(
- nandecc, 2, 1, do_switch_ecc,
+ nandecc, 3, 1, do_switch_ecc,
"switch OMAP3 NAND ECC calculation algorithm",
- "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
+ "hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and"
+ " 8-bit BCH\n"
+ " ecc calculation (second parameter may"
+ " be omitted).\n"
+ "nandecc sw - Switch to NAND software ecc algorithm."
);
#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
-u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE;
#endif
#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
struct pmic_data twl6030_4430es1 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
- .step = 12660, /* 10 mV represented in uV */
+ .step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
};
struct pmic_data twl6030 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
- .step = 12660, /* 10 mV represented in uV */
+ .step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
};
.core.value = 1200,
.core.addr = SMPS_REG_ADDR_VCORE1,
- .core.pmic = &tps62361,
+ .core.pmic = &twl6030,
.mm.value = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
- .mm.pmic = &tps62361,
+ .mm.pmic = &twl6030,
};
/*
#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
static u32 *const T_num = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_NUM;
static u32 *const T_den = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_DEN;
-static u32 *const emif_sizes = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_SIZE;
#endif
#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
return tin_parent_rate / 16;
}
-#define NS_IN_HZ (1000000000UL)
+#define NS_IN_SEC 1000000000UL
int pwm_config(int pwm_id, int duty_ns, int period_ns)
{
unsigned int offset;
unsigned long tin_rate;
unsigned long tin_ns;
- unsigned long period;
+ unsigned long frequency;
unsigned long tcon;
unsigned long tcnt;
unsigned long tcmp;
* fact that anything faster than 1GHz is easily representable
* by 32bits.
*/
- if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
+ if (period_ns > NS_IN_SEC || duty_ns > NS_IN_SEC || period_ns == 0)
return -ERANGE;
if (duty_ns > period_ns)
return -EINVAL;
- period = NS_IN_HZ / period_ns;
+ frequency = NS_IN_SEC / period_ns;
/* Check to see if we are changing the clock rate of the PWM */
- tin_rate = pwm_calc_tin(pwm_id, period);
+ tin_rate = pwm_calc_tin(pwm_id, frequency);
- tin_ns = NS_IN_HZ / tin_rate;
+ tin_ns = NS_IN_SEC / tin_rate;
tcnt = period_ns / tin_ns;
/* Note, counters count down */
tcmp = duty_ns / tin_ns;
tcmp = tcnt - tcmp;
- /*
- * the pwm hw only checks the compare register after a decrement,
- * so the pin never toggles if tcmp = tcnt
- */
- if (tcmp == tcnt)
- tcmp--;
-
- if (tcmp < 0)
- tcmp = 0;
-
/* Update the PWM register block. */
offset = pwm_id * 3;
if (pwm_id < 4) {
u32 val;
const struct s5p_timer *pwm =
(struct s5p_timer *)samsung_get_base_timer();
- unsigned long timer_rate_hz;
+ unsigned long ticks_per_period;
unsigned int offset, prescaler;
/*
val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id);
writel(val, &pwm->tcfg1);
- timer_rate_hz = get_pwm_clk() / ((prescaler + 1) *
- (div + 1));
+ if (pwm_id == 4) {
+ /*
+ * TODO(sjg): Use this as a countdown timer for now. We count
+ * down from the maximum value to 0, then reset.
+ */
+ ticks_per_period = -1UL;
+ } else {
+ const unsigned long pwm_hz = 1000;
+ unsigned long timer_rate_hz = get_pwm_clk() /
+ ((prescaler + 1) * (1 << div));
- timer_rate_hz = timer_rate_hz / CONFIG_SYS_HZ;
+ ticks_per_period = timer_rate_hz / pwm_hz;
+ }
/* set count value */
offset = pwm_id * 3;
- writel(timer_rate_hz, &pwm->tcntb0 + offset);
+
+ writel(ticks_per_period, &pwm->tcntb0 + offset);
val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id));
if (invert && (pwm_id < 4))
return (struct s5p_timer *)samsung_get_base_timer();
}
+/**
+ * Read the countdown timer.
+ *
+ * This operates at 1MHz and counts downwards. It will wrap about every
+ * hour (2^32 microseconds).
+ *
+ * @return current value of timer
+ */
+static unsigned long timer_get_us_down(void)
+{
+ struct s5p_timer *const timer = s5p_get_base_timer();
+
+ return readl(&timer->tcnto4);
+}
+
int timer_init(void)
{
/* PWM Timer 4 */
- pwm_init(4, MUX_DIV_2, 0);
- pwm_config(4, 0, 0);
+ pwm_init(4, MUX_DIV_4, 0);
+ pwm_config(4, 100000, 100000);
pwm_enable(4);
+ /* Use this as the current monotonic time in us */
+ gd->arch.timer_reset_value = 0;
+
+ /* Use this as the last timer value we saw */
+ gd->arch.lastinc = timer_get_us_down();
reset_timer_masked();
return 0;
*/
unsigned long get_timer(unsigned long base)
{
- return get_timer_masked() - base;
-}
+ ulong now = timer_get_us_down();
+
+ /*
+ * Increment the time by the amount elapsed since the last read.
+ * The timer may have wrapped around, but it makes no difference to
+ * our arithmetic here.
+ */
+ gd->arch.timer_reset_value += gd->arch.lastinc - now;
+ gd->arch.lastinc = now;
-/* delay x useconds */
-void __udelay(unsigned long usec)
-{
- struct s5p_timer *const timer = s5p_get_base_timer();
- unsigned long tmo, tmp, count_value;
-
- count_value = readl(&timer->tcntb4);
-
- if (usec >= 1000) {
- /*
- * if "big" number, spread normalization
- * to seconds
- * 1. start to normalize for usec to ticks per sec
- * 2. find number of "ticks" to wait to achieve target
- * 3. finish normalize.
- */
- tmo = usec / 1000;
- tmo *= (CONFIG_SYS_HZ * count_value);
- tmo /= 1000;
- } else {
- /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CONFIG_SYS_HZ * count_value;
- tmo /= (1000 * 1000);
- }
-
- /* get current timestamp */
- tmp = get_current_tick();
-
- /* if setting this fordward will roll time stamp */
- /* reset "advancing" timestamp to 0, set lastinc value */
- /* else, set advancing stamp wake up time */
- if ((tmo + tmp + 1) < tmp)
- reset_timer_masked();
- else
- tmo += tmp;
-
- /* loop till event */
- while (get_current_tick() < tmo)
- ; /* nop */
+ /* Divide by 1000 to convert from us to ms */
+ return gd->arch.timer_reset_value / 1000 - base;
}
-void reset_timer_masked(void)
+unsigned long timer_get_us(void)
{
- struct s5p_timer *const timer = s5p_get_base_timer();
+ static unsigned long base_time_us;
- /* reset time */
- gd->arch.lastinc = readl(&timer->tcnto4);
- gd->arch.tbl = 0;
+ struct s5p_timer *const timer =
+ (struct s5p_timer *)samsung_get_base_timer();
+ unsigned long now_downward_us = readl(&timer->tcnto4);
+
+ if (!base_time_us)
+ base_time_us = now_downward_us;
+
+ /* Note that this timer counts downward. */
+ return base_time_us - now_downward_us;
}
-unsigned long get_timer_masked(void)
+/* delay x useconds */
+void __udelay(unsigned long usec)
{
- struct s5p_timer *const timer = s5p_get_base_timer();
- unsigned long count_value = readl(&timer->tcntb4);
+ unsigned long count_value;
- return get_current_tick() / count_value;
+ count_value = timer_get_us_down();
+ while ((int)(count_value - timer_get_us_down()) < (int)usec)
+ ;
}
-unsigned long get_current_tick(void)
+void reset_timer_masked(void)
{
struct s5p_timer *const timer = s5p_get_base_timer();
- unsigned long now = readl(&timer->tcnto4);
- unsigned long count_value = readl(&timer->tcntb4);
-
- if (gd->arch.lastinc >= now)
- gd->arch.tbl += gd->arch.lastinc - now;
- else
- gd->arch.tbl += gd->arch.lastinc + count_value - now;
-
- gd->arch.lastinc = now;
- return gd->arch.tbl;
+ /* reset time */
+ gd->arch.lastinc = readl(&timer->tcnto4);
+ gd->arch.tbl = 0;
}
/*
. = ALIGN(4);
.text :
{
- arch/arm/cpu/armv7/start.o (.text)
+ arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sdram
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
-.global _image_copy_end_ofs
+.globl _image_copy_end_ofs
_image_copy_end_ofs:
- .word __image_copy_end - _start
+ .word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
#ifndef CONFIG_SPL_BUILD
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
ENTRY(relocate_code)
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
. = ALIGN(4);
+ __image_copy_end = .;
+
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
.globl _TEXT_BASE
_TEXT_BASE:
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
#ifndef CONFIG_SPL_BUILD
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
/* Disable the Dcache RAM lock for stack now */
#ifdef CONFIG_CPU_PXA25X
#endif
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
reg = <0x10060000 0x10000>;
};
+ fimd@14400000 {
+ compatible = "samsung,exynos-fimd";
+ reg = <0x14400000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ dp@145b0000 {
+ compatible = "samsung,exynos5-dp";
+ reg = <0x145b0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
};
COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
endif
COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
+COBJS-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
COBJS := $(sort $(COBJS-y))
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
$(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
-e $(CONFIG_SPL_TEXT_BASE) -d $< $@
+$(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
+ -I binary -O binary $< $(OBJTREE)/spl/u-boot-spl-pad.imx
+ cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.bin > $@
+ rm $(OBJTREE)/spl/u-boot-spl-pad.imx
+
+$(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
+ (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \
+ dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | \
+ cat - $< > $(OBJTREE)/spl/u-boot-nand-spl.imx
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
+ -I binary -O binary $(OBJTREE)/spl/u-boot-nand-spl.imx \
+ $(OBJTREE)/spl/u-boot-nand-spl-pad.imx
+ rm $(OBJTREE)/spl/u-boot-nand-spl.imx
+ cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.bin > $@
+ rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx
+
#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/io.h>
+
+static int do_hdmidet(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+ u8 reg = readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
+ return (reg&HDMI_PHY_HPD) ? 0 : 1;
+}
+
+U_BOOT_CMD(hdmidet, 1, 1, do_hdmidet,
+ "detect HDMI monitor",
+ ""
+);
DECLARE_GLOBAL_DATA_PTR;
-#define timestamp (gd->arch.tbl)
-#define lastinc (gd->arch.lastinc)
-
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
int timer_init(void)
{
int i;
- ulong val;
/* setup GP Timer 1 */
__raw_writel(GPTCR_SWR, &cur_gpt->control);
i = __raw_readl(&cur_gpt->control);
__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
- val = __raw_readl(&cur_gpt->counter);
- lastinc = val / (MXC_CLK32 / CONFIG_SYS_HZ);
- timestamp = 0;
+ gd->arch.tbl = __raw_readl(&cur_gpt->counter);
+ gd->arch.tbu = 0;
return 0;
}
{
ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */
- if (now >= lastinc) {
- /*
- * normal mode (non roll)
- * move stamp forward with absolut diff ticks
- */
- timestamp += (now - lastinc);
- } else {
- /* we have rollover of incrementer */
- timestamp += (0xFFFFFFFF - lastinc) + now;
- }
- lastinc = now;
- return timestamp;
+ /* increment tbu if tbl has rolled over */
+ if (now < gd->arch.tbl)
+ gd->arch.tbu++;
+ gd->arch.tbl = now;
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
}
ulong get_timer_masked(void)
#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
/* Micron MT41K256M16HA-125E */
-#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100006
-#define MT41K256M16HA125E_EMIF_TIM1 0x0888A39B
-#define MT41K256M16HA125E_EMIF_TIM2 0x26517FDA
-#define MT41K256M16HA125E_EMIF_TIM3 0x501F84EF
-#define MT41K256M16HA125E_EMIF_SDCFG 0x61C04BB2
-#define MT41K256M16HA125E_EMIF_SDREF 0x0000093B
+#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
+#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
+#define MT41K256M16HA125E_EMIF_TIM2 0x26437FDA
+#define MT41K256M16HA125E_EMIF_TIM3 0x501F83FF
+#define MT41K256M16HA125E_EMIF_SDCFG 0x61C052B2
+#define MT41K256M16HA125E_EMIF_SDREF 0xC30
#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
-#define MT41K256M16HA125E_RATIO 0x40
+#define MT41K256M16HA125E_RATIO 0x80
#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
-#define MT41K256M16HA125E_RD_DQS 0x3C
-#define MT41K256M16HA125E_WR_DQS 0x45
-#define MT41K256M16HA125E_PHY_WR_DATA 0x7F
+#define MT41K256M16HA125E_RD_DQS 0x3A
+#define MT41K256M16HA125E_WR_DQS 0x42
+#define MT41K256M16HA125E_PHY_WR_DATA 0x7E
#define MT41K256M16HA125E_PHY_FIFO_WE 0x9B
#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
#ifndef __ASM_ARCH_OMAP_GPMC_H
#define __ASM_ARCH_OMAP_GPMC_H
-#define GPMC_BUF_EMPTY 0
-#define GPMC_BUF_FULL 1
-
-#define ECCCLEAR (0x1 << 8)
-#define ECCRESULTREG1 (0x1 << 0)
-#define ECCSIZE512BYTE 0xFF
-#define ECCSIZE1 (ECCSIZE512BYTE << 22)
-#define ECCSIZE0 (ECCSIZE512BYTE << 12)
-#define ECCSIZE0SEL (0x000 << 0)
-
-/* Generic ECC Layouts */
-/* Large Page x8 NAND device Layout */
-#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 12,\
- .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
- 9, 10, 11, 12},\
- .oobfree = {\
- {.offset = 13,\
- .length = 51 } } \
-}
-#endif
-
-/* Large Page x16 NAND device Layout */
-#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 12,\
- .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
- 10, 11, 12, 13},\
- .oobfree = {\
- {.offset = 14,\
- .length = 50 } } \
-}
-#endif
-
-/* Small Page x8 NAND device Layout */
-#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 3,\
- .eccpos = {1, 2, 3},\
- .oobfree = {\
- {.offset = 4,\
- .length = 12 } } \
-}
-#endif
-
-/* Small Page x16 NAND device Layout */
-#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 3,\
- .eccpos = {2, 3, 4},\
- .oobfree = {\
- {.offset = 5,\
- .length = 11 } } \
-}
-#endif
-
+/* These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines are based on AM33xx ELM */
#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\
.eccbytes = 32,\
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
#define BOOT_DEVICE_USBETH 68
#define BOOT_DEVICE_CPGMAC 70
#define BOOT_DEVICE_MMC2_2 0xFF
+
+#ifdef CONFIG_AM33XX
+#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
+#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2
+#elif defined(CONFIG_TI814X)
+#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
+#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
+#endif
#endif
void gpmc_init(void);
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size);
-void omap_nand_switch_ecc(int);
+void omap_nand_switch_ecc(uint32_t, uint32_t);
#endif
#define BCM2835_TIMER_CS_M1 (1 << 1)
#define BCM2835_TIMER_CS_M0 (1 << 0)
+extern ulong get_timer_us(ulong base);
+
#endif
#define VPLL 4
#define BPLL 5
+enum pll_src_bit {
+ EXYNOS_SRC_MPLL = 6,
+ EXYNOS_SRC_EPLL,
+ EXYNOS_SRC_VPLL,
+};
+
unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
unsigned long get_i2c_clk(void);
int set_epll_clk(unsigned long rate);
int set_spi_clk(int periph_id, unsigned int rate);
+/**
+ * get the clk frequency of the required peripheral
+ *
+ * @param peripheral Peripheral id
+ *
+ * @return frequency of the peripheral clk
+ */
+unsigned long clock_get_periph_rate(int peripheral);
+
#endif
#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS4X12 */
#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS5 Common*/
#define EXYNOS5_I2C_SPACING 0x10000
#define EXYNOS5_SWRESET 0x10040400
#define EXYNOS5_SYSREG_BASE 0x10050000
#define EXYNOS5_WATCHDOG_BASE 0x101D0000
+#define EXYNOS5_ACE_SFR_BASE 0x10830000
#define EXYNOS5_DMC_PHY0_BASE 0x10C00000
#define EXYNOS5_DMC_PHY1_BASE 0x10C10000
#define EXYNOS5_GPIO_PART3_BASE 0x10D10000
SAMSUNG_BASE(adc, ADC_BASE)
SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
SAMSUNG_BASE(dp, DP_BASE)
SAMSUNG_BASE(sysreg, SYSREG_BASE)
SAMSUNG_BASE(fimd, FIMD_BASE)
struct exynos_dp_platform_data {
struct edp_device_info *edp_dev_info;
- void (*phy_enable)(unsigned int);
};
#ifdef CONFIG_EXYNOS_DP
PERIPH_ID_SPI3,
PERIPH_ID_SPI4,
PERIPH_ID_SDMMC4,
+ PERIPH_ID_PWM0,
+ PERIPH_ID_PWM1,
+ PERIPH_ID_PWM2,
+ PERIPH_ID_PWM3,
+ PERIPH_ID_PWM4,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
#define NO_MUX_I 0
#define NO_PAD_I 0
enum {
+ MX6_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0),
+ MX6_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0),
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0),
MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
# define H4_CS1_BASE 0x04000000 /* debug board */
# define H4_CS2_BASE 0x0A000000 /* wifi board */
#else
-# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */
-# define H4_CS1_BASE 0x08000000 /* debug board */
-# define H4_CS2_BASE 0x0A000000 /* wifi board */
+# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */
+# define H4_CS1_BASE 0x04000000 /* debug board */
+# define H4_CS2_BASE 0x0C000000 /* wifi board */
#endif
/* base address for indirect vectors (internal boot mode) */
u8 res[8]; /* blow up to 0x30 byte */
};
+struct bch_res_0_3 {
+ u32 bch_result_x[4];
+};
+
struct gpmc {
u8 res1[0x10];
u32 sysconfig; /* 0x10 */
u32 ecc7_result; /* 0x218 */
u32 ecc8_result; /* 0x21C */
u32 ecc9_result; /* 0x220 */
+ u8 res7[0x1C]; /* fill up to 0x240 */
+ struct bch_res_0_3 bch_result_0_3[7]; /* 0x240 */
};
/* Used for board specific gpmc initialization */
#ifndef __ASM_ARCH_OMAP_GPMC_H
#define __ASM_ARCH_OMAP_GPMC_H
-#define GPMC_BUF_EMPTY 0
-#define GPMC_BUF_FULL 1
-
-#define ECCCLEAR (0x1 << 8)
-#define ECCRESULTREG1 (0x1 << 0)
-#define ECCSIZE512BYTE 0xFF
-#define ECCSIZE1 (ECCSIZE512BYTE << 22)
-#define ECCSIZE0 (ECCSIZE512BYTE << 12)
-#define ECCSIZE0SEL (0x000 << 0)
-
-/* Generic ECC Layouts */
-/* Large Page x8 NAND device Layout */
-#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 12,\
- .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
- 9, 10, 11, 12},\
- .oobfree = {\
- {.offset = 13,\
- .length = 51 } } \
-}
-#endif
-
-/* Large Page x16 NAND device Layout */
-#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 12,\
- .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
- 10, 11, 12, 13},\
- .oobfree = {\
- {.offset = 14,\
- .length = 50 } } \
-}
-#endif
-
-/* Small Page x8 NAND device Layout */
-#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 3,\
- .eccpos = {1, 2, 3},\
- .oobfree = {\
- {.offset = 4,\
- .length = 12 } } \
-}
-#endif
-
-/* Small Page x16 NAND device Layout */
-#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
-#define GPMC_NAND_HW_ECC_LAYOUT {\
- .eccbytes = 3,\
- .eccpos = {2, 3, 4},\
+/*
+ * These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines using the BCH library.
+ * The OOB layout was first defined by linx kernel in commit
+ * 0e618ef0a6a33cf7ef96c2c824402088dd8ef48c, we have to reuse it here cause
+ * we want to be compatible.
+ */
+#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
+ .eccbytes = 56,\
+ .eccpos = {12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\
+ 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\
+ 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,\
+ 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63},\
.oobfree = {\
- {.offset = 5,\
- .length = 11 } } \
+ {.offset = 2,\
+ .length = 10 } } \
}
-#endif
/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
#define NET_LAN9221_GPMC_CONFIG1 0x00001000
#define BOOT_DEVICE_MMC1 6
#define BOOT_DEVICE_XIPWAIT 7
#define BOOT_DEVICE_MMC2_2 0xFF
+
+#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
+#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
#endif
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void make_cs1_contiguous(void);
-void omap_nand_switch_ecc(int);
+void omap_nand_switch_ecc(uint32_t, uint32_t);
void power_init_r(void);
void dieid_num_r(void);
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
/* SRAM scratch space entries */
#define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR
-#define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 0xFF
+#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
+#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2
#endif
* SRAM scratch space entries
*/
#define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR
-#define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 7
+#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
+#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2
#endif
+++ /dev/null
-/*
- * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ARCH_HARDWARE_H_
-#define _ARCH_HARDWARE_H_
-
-#include <asm/sizes.h>
-
-#ifndef __ASSEMBLY__
-#define UData(Data) ((unsigned long) (Data))
-
-#define __REG(x) (*(vu_long *)(x))
-#define __REGl(x) (*(vu_long *)(x))
-#define __REGw(x) (*(vu_short *)(x))
-#define __REGb(x) (*(vu_char *)(x))
-#define __REG2(x, y) (*(vu_long *)((x) + (y)))
-#else
-#define UData(Data) (Data)
-
-#define __REG(x) (x)
-#define __REGl(x) (x)
-#define __REGw(x) (x)
-#define __REGb(x) (x)
-#define __REG2(x, y) ((x) + (y))
-#endif
-
-#define Fld(Size, Shft) (((Size) << 16) + (Shft))
-
-#define FSize(Field) ((Field) >> 16)
-#define FShft(Field) ((Field) & 0x0000FFFF)
-#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
-#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
-#define F1stBit(Field) (UData (1) << FShft (Field))
-
-#define FClrBit(Data, Bit) (Data = (Data & ~(Bit)))
-#define FClrFld(Data, Field) (Data = (Data & ~FMsk(Field)))
-
-#define FInsrt(Value, Field) \
- (UData (Value) << FShft (Field))
-
-#define FExtr(Data, Field) \
- ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
-
-#endif /* _ARCH_HARDWARE_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com.
- * - only support for S3C6400
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME : s3c6400.h
- *
- * Based on S3C6400 User's manual Rev 0.0
- ************************************************/
-
-#ifndef __S3C6400_H__
-#define __S3C6400_H__
-
-#define S3C64XX_UART_CHANNELS 3
-#define S3C64XX_SPI_CHANNELS 2
-
-#include <asm/hardware.h>
-
-#define ELFIN_CLOCK_POWER_BASE 0x7e00f000
-
-/* Clock & Power Controller for mDirac3*/
-#define APLL_LOCK_OFFSET 0x00
-#define MPLL_LOCK_OFFSET 0x04
-#define EPLL_LOCK_OFFSET 0x08
-#define APLL_CON_OFFSET 0x0C
-#define MPLL_CON_OFFSET 0x10
-#define EPLL_CON0_OFFSET 0x14
-#define EPLL_CON1_OFFSET 0x18
-#define CLK_SRC_OFFSET 0x1C
-#define CLK_DIV0_OFFSET 0x20
-#define CLK_DIV1_OFFSET 0x24
-#define CLK_DIV2_OFFSET 0x28
-#define CLK_OUT_OFFSET 0x2C
-#define HCLK_GATE_OFFSET 0x30
-#define PCLK_GATE_OFFSET 0x34
-#define SCLK_GATE_OFFSET 0x38
-#define AHB_CON0_OFFSET 0x100
-#define AHB_CON1_OFFSET 0x104
-#define AHB_CON2_OFFSET 0x108
-#define SELECT_DMA_OFFSET 0x110
-#define SW_RST_OFFSET 0x114
-#define SYS_ID_OFFSET 0x118
-#define MEM_SYS_CFG_OFFSET 0x120
-#define QOS_OVERRIDE0_OFFSET 0x124
-#define QOS_OVERRIDE1_OFFSET 0x128
-#define MEM_CFG_STAT_OFFSET 0x12C
-#define PWR_CFG_OFFSET 0x804
-#define EINT_MASK_OFFSET 0x808
-#define NOR_CFG_OFFSET 0x810
-#define STOP_CFG_OFFSET 0x814
-#define SLEEP_CFG_OFFSET 0x818
-#define OSC_FREQ_OFFSET 0x820
-#define OSC_STABLE_OFFSET 0x824
-#define PWR_STABLE_OFFSET 0x828
-#define FPC_STABLE_OFFSET 0x82C
-#define MTC_STABLE_OFFSET 0x830
-#define OTHERS_OFFSET 0x900
-#define RST_STAT_OFFSET 0x904
-#define WAKEUP_STAT_OFFSET 0x908
-#define BLK_PWR_STAT_OFFSET 0x90C
-#define INF_REG0_OFFSET 0xA00
-#define INF_REG1_OFFSET 0xA04
-#define INF_REG2_OFFSET 0xA08
-#define INF_REG3_OFFSET 0xA0C
-#define INF_REG4_OFFSET 0xA10
-#define INF_REG5_OFFSET 0xA14
-#define INF_REG6_OFFSET 0xA18
-#define INF_REG7_OFFSET 0xA1C
-
-#define OSC_CNT_VAL_OFFSET 0x824
-#define PWR_CNT_VAL_OFFSET 0x828
-#define FPC_CNT_VAL_OFFSET 0x82C
-#define MTC_CNT_VAL_OFFSET 0x830
-
-#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
-#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
-#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
-#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
-#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
-#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
-#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
-#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
-#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
-#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
-#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
-#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
-#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
-#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
-#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
-#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
-#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
-#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
-#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- SELECT_DMA_OFFSET)
-#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
-#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
-#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- MEM_SYS_CFG_OFFSET)
-#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- QOS_OVERRIDE0_OFFSET)
-#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- QOS_OVERRIDE1_OFFSET)
-#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- MEM_CFG_STAT_OFFSET)
-#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
-#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
-#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
-#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
-#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
-#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
-#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- OSC_CNT_VAL_OFFSET)
-#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- PWR_CNT_VAL_OFFSET)
-#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- FPC_CNT_VAL_OFFSET)
-#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- MTC_CNT_VAL_OFFSET)
-#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
-#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
-#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- WAKEUP_STAT_OFFSET)
-#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- BLK_PWR_STAT_OFFSET)
-#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
-#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
-#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
-#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
-#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
-#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
-#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
-#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
-
-#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
-#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
-#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
-#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
-#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
-#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
-#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
-#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
-#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
-#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
-#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
-#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
-#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
-#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
-#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
-#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
-#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
-#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
-#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET)
-#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
-#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
-#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET)
-#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET)
-#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET)
-#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET)
-#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
-#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
-#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
-#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
-#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
-#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
-#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET)
-#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET)
-#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET)
-#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET)
-#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
-#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
-#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
-#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET)
-#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
-#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
-#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
-#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
-#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
-#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
-#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
-#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
-
-
-/*
- * GPIO
- */
-#define ELFIN_GPIO_BASE 0x7f008000
-
-#define GPACON_OFFSET 0x00
-#define GPADAT_OFFSET 0x04
-#define GPAPUD_OFFSET 0x08
-#define GPACONSLP_OFFSET 0x0C
-#define GPAPUDSLP_OFFSET 0x10
-#define GPBCON_OFFSET 0x20
-#define GPBDAT_OFFSET 0x24
-#define GPBPUD_OFFSET 0x28
-#define GPBCONSLP_OFFSET 0x2C
-#define GPBPUDSLP_OFFSET 0x30
-#define GPCCON_OFFSET 0x40
-#define GPCDAT_OFFSET 0x44
-#define GPCPUD_OFFSET 0x48
-#define GPCCONSLP_OFFSET 0x4C
-#define GPCPUDSLP_OFFSET 0x50
-#define GPDCON_OFFSET 0x60
-#define GPDDAT_OFFSET 0x64
-#define GPDPUD_OFFSET 0x68
-#define GPDCONSLP_OFFSET 0x6C
-#define GPDPUDSLP_OFFSET 0x70
-#define GPECON_OFFSET 0x80
-#define GPEDAT_OFFSET 0x84
-#define GPEPUD_OFFSET 0x88
-#define GPECONSLP_OFFSET 0x8C
-#define GPEPUDSLP_OFFSET 0x90
-#define GPFCON_OFFSET 0xA0
-#define GPFDAT_OFFSET 0xA4
-#define GPFPUD_OFFSET 0xA8
-#define GPFCONSLP_OFFSET 0xAC
-#define GPFPUDSLP_OFFSET 0xB0
-#define GPGCON_OFFSET 0xC0
-#define GPGDAT_OFFSET 0xC4
-#define GPGPUD_OFFSET 0xC8
-#define GPGCONSLP_OFFSET 0xCC
-#define GPGPUDSLP_OFFSET 0xD0
-#define GPHCON0_OFFSET 0xE0
-#define GPHCON1_OFFSET 0xE4
-#define GPHDAT_OFFSET 0xE8
-#define GPHPUD_OFFSET 0xEC
-#define GPHCONSLP_OFFSET 0xF0
-#define GPHPUDSLP_OFFSET 0xF4
-#define GPICON_OFFSET 0x100
-#define GPIDAT_OFFSET 0x104
-#define GPIPUD_OFFSET 0x108
-#define GPICONSLP_OFFSET 0x10C
-#define GPIPUDSLP_OFFSET 0x110
-#define GPJCON_OFFSET 0x120
-#define GPJDAT_OFFSET 0x124
-#define GPJPUD_OFFSET 0x128
-#define GPJCONSLP_OFFSET 0x12C
-#define GPJPUDSLP_OFFSET 0x130
-#define MEM0DRVCON_OFFSET 0x1D0
-#define MEM1DRVCON_OFFSET 0x1D4
-#define GPKCON0_OFFSET 0x800
-#define GPKCON1_OFFSET 0x804
-#define GPKDAT_OFFSET 0x808
-#define GPKPUD_OFFSET 0x80C
-#define GPLCON0_OFFSET 0x810
-#define GPLCON1_OFFSET 0x814
-#define GPLDAT_OFFSET 0x818
-#define GPLPUD_OFFSET 0x81C
-#define GPMCON_OFFSET 0x820
-#define GPMDAT_OFFSET 0x824
-#define GPMPUD_OFFSET 0x828
-#define GPNCON_OFFSET 0x830
-#define GPNDAT_OFFSET 0x834
-#define GPNPUD_OFFSET 0x838
-#define GPOCON_OFFSET 0x140
-#define GPODAT_OFFSET 0x144
-#define GPOPUD_OFFSET 0x148
-#define GPOCONSLP_OFFSET 0x14C
-#define GPOPUDSLP_OFFSET 0x150
-#define GPPCON_OFFSET 0x160
-#define GPPDAT_OFFSET 0x164
-#define GPPPUD_OFFSET 0x168
-#define GPPCONSLP_OFFSET 0x16C
-#define GPPPUDSLP_OFFSET 0x170
-#define GPQCON_OFFSET 0x180
-#define GPQDAT_OFFSET 0x184
-#define GPQPUD_OFFSET 0x188
-#define GPQCONSLP_OFFSET 0x18C
-#define GPQPUDSLP_OFFSET 0x190
-
-#define EINTPEND_OFFSET 0x924
-
-#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET)
-#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET)
-#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET)
-#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
-#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
-#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET)
-#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET)
-#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET)
-#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
-#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
-#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET)
-#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET)
-#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET)
-#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
-#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
-#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET)
-#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET)
-#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET)
-#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
-#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
-#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET)
-#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET)
-#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET)
-#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
-#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
-#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET)
-#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET)
-#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET)
-#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
-#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
-#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET)
-#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET)
-#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET)
-#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
-#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
-#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET)
-#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET)
-#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET)
-#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET)
-#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
-#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
-#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET)
-#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET)
-#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET)
-#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
-#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
-#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET)
-#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET)
-#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET)
-#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
-#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
-#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
-#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET)
-#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET)
-#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET)
-#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET)
-#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET)
-#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET)
-#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET)
-#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET)
-#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET)
-#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET)
-#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET)
-#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET)
-#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET)
-#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET)
-#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET)
-#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET)
-#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
-#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
-#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET)
-#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET)
-#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET)
-#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
-#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
-#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET)
-#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET)
-#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET)
-#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
-#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
-
-/*
- * Bus Matrix
- */
-#define ELFIN_MEM_SYS_CFG 0x7e00f120
-
-#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12)
-
-#define S3C64XX_MEM_SYS_CFG_NAND 0x0008
-#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT
-
-#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET)
-#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET)
-#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET)
-#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
-#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
-#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET)
-#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET)
-#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET)
-#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
-#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
-#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET)
-#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET)
-#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET)
-#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
-#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
-#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET)
-#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET)
-#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET)
-#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
-#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
-#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET)
-#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET)
-#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET)
-#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
-#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
-#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET)
-#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET)
-#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET)
-#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
-#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
-#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET)
-#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET)
-#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET)
-#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
-#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
-#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET)
-#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET)
-#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET)
-#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET)
-#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
-#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
-#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET)
-#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET)
-#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET)
-#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
-#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
-#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET)
-#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET)
-#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET)
-#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
-#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
-#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET)
-#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET)
-#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET)
-#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET)
-#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET)
-#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET)
-#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET)
-#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET)
-#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET)
-#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET)
-#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET)
-#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET)
-#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET)
-#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET)
-#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET)
-#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET)
-#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET)
-#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
-#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
-#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET)
-#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET)
-#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET)
-#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
-#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
-#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET)
-#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET)
-#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET)
-#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
-#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
-
-/*
- * Memory controller
- */
-#define ELFIN_SROM_BASE 0x70000000
-
-#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0)
-#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4)
-#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8)
-#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC)
-#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10)
-#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14)
-#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18)
-
-/*
- * SDRAM Controller
- */
-#define ELFIN_DMC0_BASE 0x7e000000
-#define ELFIN_DMC1_BASE 0x7e001000
-
-#define INDEX_DMC_MEMC_STATUS 0x00
-#define INDEX_DMC_MEMC_CMD 0x04
-#define INDEX_DMC_DIRECT_CMD 0x08
-#define INDEX_DMC_MEMORY_CFG 0x0C
-#define INDEX_DMC_REFRESH_PRD 0x10
-#define INDEX_DMC_CAS_LATENCY 0x14
-#define INDEX_DMC_T_DQSS 0x18
-#define INDEX_DMC_T_MRD 0x1C
-#define INDEX_DMC_T_RAS 0x20
-#define INDEX_DMC_T_RC 0x24
-#define INDEX_DMC_T_RCD 0x28
-#define INDEX_DMC_T_RFC 0x2C
-#define INDEX_DMC_T_RP 0x30
-#define INDEX_DMC_T_RRD 0x34
-#define INDEX_DMC_T_WR 0x38
-#define INDEX_DMC_T_WTR 0x3C
-#define INDEX_DMC_T_XP 0x40
-#define INDEX_DMC_T_XSR 0x44
-#define INDEX_DMC_T_ESR 0x48
-#define INDEX_DMC_MEMORY_CFG2 0x4C
-#define INDEX_DMC_CHIP_0_CFG 0x200
-#define INDEX_DMC_CHIP_1_CFG 0x204
-#define INDEX_DMC_CHIP_2_CFG 0x208
-#define INDEX_DMC_CHIP_3_CFG 0x20C
-#define INDEX_DMC_USER_STATUS 0x300
-#define INDEX_DMC_USER_CONFIG 0x304
-
-/*
- * Memory Chip direct command
- */
-#define DMC_NOP0 0x0c0000
-#define DMC_NOP1 0x1c0000
-#define DMC_PA0 0x000000 /* Precharge all */
-#define DMC_PA1 0x100000
-#define DMC_AR0 0x040000 /* Autorefresh */
-#define DMC_AR1 0x140000
-#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */
-#define DMC_SDR_MR1 0x180032
-#define DMC_DDR_MR0 0x080162
-#define DMC_DDR_MR1 0x180162
-#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */
-#define DMC_mDDR_MR1 0x180032
-#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */
-#define DMC_mSDR_EMR1 0x1a0000
-#define DMC_DDR_EMR0 0x090000
-#define DMC_DDR_EMR1 0x190000
-#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */
-#define DMC_mDDR_EMR1 0x1a0000
-
-/*
- * Definitions for memory configuration
- * Set memory configuration
- * active_chips = 1'b0 (1 chip)
- * qos_master_chip = 3'b000(ARID[3:0])
- * memory burst = 3'b010(burst 4)
- * stop_mem_clock = 1'b0(disable dynamical stop)
- * auto_power_down = 1'b0(disable auto power-down mode)
- * power_down_prd = 6'b00_0000(0 cycle for auto power-down)
- * ap_bit = 1'b0 (bit position of auto-precharge is 10)
- * row_bits = 3'b010(# row address 13)
- * column_bits = 3'b010(# column address 10 )
- *
- * Set user configuration
- * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
- *
- * Set chip select for chip [n]
- * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff
- * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24]
- */
-
-/*
- * Nand flash controller
- */
-#define ELFIN_NAND_BASE 0x70200000
-
-#define NFCONF_OFFSET 0x00
-#define NFCONT_OFFSET 0x04
-#define NFCMMD_OFFSET 0x08
-#define NFADDR_OFFSET 0x0c
-#define NFDATA_OFFSET 0x10
-#define NFMECCDATA0_OFFSET 0x14
-#define NFMECCDATA1_OFFSET 0x18
-#define NFSECCDATA0_OFFSET 0x1c
-#define NFSBLK_OFFSET 0x20
-#define NFEBLK_OFFSET 0x24
-#define NFSTAT_OFFSET 0x28
-#define NFESTAT0_OFFSET 0x2c
-#define NFESTAT1_OFFSET 0x30
-#define NFMECC0_OFFSET 0x34
-#define NFMECC1_OFFSET 0x38
-#define NFSECC_OFFSET 0x3c
-#define NFMLCBITPT_OFFSET 0x40
-
-#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET)
-#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET)
-#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET)
-#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET)
-#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
-#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
-#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
-#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET)
-#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET)
-#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET)
-#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET)
-#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET)
-#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET)
-#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET)
-#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET)
-#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
-
-#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET)
-#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET)
-#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET)
-#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET)
-#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
-#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
-#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
-#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET)
-#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET)
-#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET)
-#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET)
-#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET)
-#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET)
-#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET)
-#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET)
-#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
-
-#define NFCONF_ECC_4BIT (1<<24)
-
-#define NFCONT_ECC_ENC (1<<18)
-#define NFCONT_WP (1<<16)
-#define NFCONT_MECCLOCK (1<<7)
-#define NFCONT_SECCLOCK (1<<6)
-#define NFCONT_INITMECC (1<<5)
-#define NFCONT_INITSECC (1<<4)
-#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC)
-#define NFCONT_CS_ALT (1<<2)
-#define NFCONT_CS (1<<1)
-#define NFCONT_ENABLE (1<<0)
-
-#define NFSTAT_ECCENCDONE (1<<7)
-#define NFSTAT_ECCDECDONE (1<<6)
-#define NFSTAT_RnB (1<<0)
-
-#define NFESTAT0_ECCBUSY (1<<31)
-
-/*
- * Interrupt
- */
-#define ELFIN_VIC0_BASE_ADDR 0x71200000
-#define ELFIN_VIC1_BASE_ADDR 0x71300000
-#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */
-#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */
-#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */
-#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */
-#define oVECTADDR 0xF00 /* VIC ADDRESS */
-
-/*
- * Watchdog timer
- */
-#define ELFIN_WATCHDOG_BASE 0x7E004000
-
-#define WTCON_REG __REG(0x7E004004)
-#define WTDAT_REG __REG(0x7E004008)
-#define WTCNT_REG __REG(0x7E00400C)
-
-
-/*
- * UART
- */
-#define ELFIN_UART_BASE 0x7F005000
-
-#define ELFIN_UART0_OFFSET 0x0000
-#define ELFIN_UART1_OFFSET 0x0400
-#define ELFIN_UART2_OFFSET 0x0800
-
-#define ULCON_OFFSET 0x00
-#define UCON_OFFSET 0x04
-#define UFCON_OFFSET 0x08
-#define UMCON_OFFSET 0x0C
-#define UTRSTAT_OFFSET 0x10
-#define UERSTAT_OFFSET 0x14
-#define UFSTAT_OFFSET 0x18
-#define UMSTAT_OFFSET 0x1C
-#define UTXH_OFFSET 0x20
-#define URXH_OFFSET 0x24
-#define UBRDIV_OFFSET 0x28
-#define UDIVSLOT_OFFSET 0x2C
-#define UINTP_OFFSET 0x30
-#define UINTSP_OFFSET 0x34
-#define UINTM_OFFSET 0x38
-
-#define ULCON0_REG __REG(0x7F005000)
-#define UCON0_REG __REG(0x7F005004)
-#define UFCON0_REG __REG(0x7F005008)
-#define UMCON0_REG __REG(0x7F00500C)
-#define UTRSTAT0_REG __REG(0x7F005010)
-#define UERSTAT0_REG __REG(0x7F005014)
-#define UFSTAT0_REG __REG(0x7F005018)
-#define UMSTAT0_REG __REG(0x7F00501c)
-#define UTXH0_REG __REG(0x7F005020)
-#define URXH0_REG __REG(0x7F005024)
-#define UBRDIV0_REG __REG(0x7F005028)
-#define UDIVSLOT0_REG __REG(0x7F00502c)
-#define UINTP0_REG __REG(0x7F005030)
-#define UINTSP0_REG __REG(0x7F005034)
-#define UINTM0_REG __REG(0x7F005038)
-
-#define ULCON1_REG __REG(0x7F005400)
-#define UCON1_REG __REG(0x7F005404)
-#define UFCON1_REG __REG(0x7F005408)
-#define UMCON1_REG __REG(0x7F00540C)
-#define UTRSTAT1_REG __REG(0x7F005410)
-#define UERSTAT1_REG __REG(0x7F005414)
-#define UFSTAT1_REG __REG(0x7F005418)
-#define UMSTAT1_REG __REG(0x7F00541c)
-#define UTXH1_REG __REG(0x7F005420)
-#define URXH1_REG __REG(0x7F005424)
-#define UBRDIV1_REG __REG(0x7F005428)
-#define UDIVSLOT1_REG __REG(0x7F00542c)
-#define UINTP1_REG __REG(0x7F005430)
-#define UINTSP1_REG __REG(0x7F005434)
-#define UINTM1_REG __REG(0x7F005438)
-
-#define UTRSTAT_TX_EMPTY (1 << 2)
-#define UTRSTAT_RX_READY (1 << 0)
-#define UART_ERR_MASK 0xF
-
-/*
- * PWM timer
- */
-#define ELFIN_TIMER_BASE 0x7F006000
-
-#define TCFG0_REG __REG(0x7F006000)
-#define TCFG1_REG __REG(0x7F006004)
-#define TCON_REG __REG(0x7F006008)
-#define TCNTB0_REG __REG(0x7F00600c)
-#define TCMPB0_REG __REG(0x7F006010)
-#define TCNTO0_REG __REG(0x7F006014)
-#define TCNTB1_REG __REG(0x7F006018)
-#define TCMPB1_REG __REG(0x7F00601c)
-#define TCNTO1_REG __REG(0x7F006020)
-#define TCNTB2_REG __REG(0x7F006024)
-#define TCMPB2_REG __REG(0x7F006028)
-#define TCNTO2_REG __REG(0x7F00602c)
-#define TCNTB3_REG __REG(0x7F006030)
-#define TCMPB3_REG __REG(0x7F006034)
-#define TCNTO3_REG __REG(0x7F006038)
-#define TCNTB4_REG __REG(0x7F00603c)
-#define TCNTO4_REG __REG(0x7F006040)
-
-/* Fields */
-#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */
-#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */
-#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */
-#define fTCFG1_MUX4 Fld(4, 16)
-/* bits */
-#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE)
-#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1)
-#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0)
-#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */
-#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */
-#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */
-#define COUNT_4_ON (TCON_4_ONOFF * 1)
-#define COUNT_4_OFF (TCON_4_ONOFF * 0)
-#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */
-#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1)
-#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO)
-#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */
-#define TIMER3_IVT_ON (TCON_3_INVERT * 1)
-#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT))
-#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */
-#define TIMER3_MANUP (TCON_3_MAN*1)
-#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN))
-#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */
-#define TIMER3_ON (TCON_3_ONOFF * 1)
-#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF))
-
-#if defined(CONFIG_CLK_400_100_50)
-#define STARTUP_AMDIV 400
-#define STARTUP_MDIV 400
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#elif defined(CONFIG_CLK_400_133_66)
-#define STARTUP_AMDIV 400
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#elif defined(CONFIG_CLK_533_133_66)
-#define STARTUP_AMDIV 533
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#elif defined(CONFIG_CLK_667_133_66)
-#define STARTUP_AMDIV 667
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#endif
-
-#define STARTUP_PCLKDIV 3
-#define STARTUP_HCLKX2DIV 1
-#define STARTUP_HCLKDIV 1
-#define STARTUP_MPLLDIV 1
-#define STARTUP_APLLDIV 0
-
-#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \
- (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV)
-#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_MDIV)
-
-#if defined(CONFIG_SYNC_MODE)
-#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_MDIV)
-#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
- (STARTUP_HCLKDIV + 1))
-#else
-#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_AMDIV)
-#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
- (STARTUP_HCLKDIV + 1))
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */
-#define DMC1_MEM_CFG2 0xB45
-#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) */
-#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
-
-/* Memory Parameters */
-/* DDR Parameters */
-#define DDR_tREFRESH 7800 /* ns */
-#define DDR_tRAS 45 /* ns (min: 45ns)*/
-#define DDR_tRC 68 /* ns (min: 67.5ns)*/
-#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
-#define DDR_tRFC 80 /* ns (min: 80ns)*/
-#define DDR_tRP 23 /* ns (min: 22.5ns)*/
-#define DDR_tRRD 15 /* ns (min: 15ns)*/
-#define DDR_tWR 15 /* ns (min: 15ns)*/
-#define DDR_tXSR 120 /* ns (min: 120ns)*/
-#define DDR_CASL 3 /* CAS Latency 3 */
-
-/*
- * mDDR memory configuration
- */
-
-#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000)
-
-#define DMC_DDR_BA_EMRS 2
-#define DMC_DDR_MEM_CASLAT 3
-/* 6 Set Cas Latency to 3 */
-#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1)
-/* Min 0.75 ~ 1.25 */
-#define DMC_DDR_t_DQSS 1
-/* Min 2 tck */
-#define DMC_DDR_t_MRD 2
-/* 7, Min 45ns */
-#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1)
-/* 10, Min 67.5ns */
-#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1)
-/* 4,5(TRM), Min 22.5ns */
-#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1)
-#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3)
-/* 11,18(TRM) Min 80ns */
-#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1)
-#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5)
-/* 4, 5(TRM) Min 22.5ns */
-#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1)
-#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3)
-/* 3, Min 15ns */
-#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1)
-/* Min 15ns */
-#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1)
-#define DMC_DDR_t_WTR 2
-/* 1tck + tIS(1.5ns) */
-#define DMC_DDR_t_XP 2
-/* 17, Min 120ns */
-#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1)
-#define DMC_DDR_t_ESR DMC_DDR_t_XSR
-/* TRM 2656 */
-#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH))
-/* 2b01 : mDDR */
-#define DMC_DDR_USER_CONFIG 1
-
-#ifndef __ASSEMBLY__
-enum s3c64xx_uarts_nr {
- S3C64XX_UART0,
- S3C64XX_UART1,
- S3C64XX_UART2,
-};
-
-#include "s3c64x0.h"
-
-static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr)
-{
- return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400));
-}
-#endif
-
-#endif /*__S3C6400_H__*/
+++ /dev/null
-/*
- * (C) Copyright 2003
- * David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME : S3C64XX.h
- * Version : 31.3.2003
- *
- * common stuff for SAMSUNG S3C64XX SoC
- ************************************************/
-
-#ifndef __S3C64XX_H__
-#define __S3C64XX_H__
-
-#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400)
-#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration!
-#endif
-
-#include <asm/types.h>
-
-/* UART (see manual chapter 11) */
-typedef struct {
- volatile u32 ULCON;
- volatile u32 UCON;
- volatile u32 UFCON;
- volatile u32 UMCON;
- volatile u32 UTRSTAT;
- volatile u32 UERSTAT;
- volatile u32 UFSTAT;
- volatile u32 UMSTAT;
-#ifdef __BIG_ENDIAN
- volatile u8 res1[3];
- volatile u8 UTXH;
- volatile u8 res2[3];
- volatile u8 URXH;
-#else /* Little Endian */
- volatile u8 UTXH;
- volatile u8 res1[3];
- volatile u8 URXH;
- volatile u8 res2[3];
-#endif
- volatile u32 UBRDIV;
-#ifdef __BIG_ENDIAN
- volatile u8 res3[2];
- volatile u16 UDIVSLOT;
-#else
- volatile u16 UDIVSLOT;
- volatile u8 res3[2];
-#endif
-} s3c64xx_uart;
-
-/* PWM TIMER (see manual chapter 10) */
-typedef struct {
- volatile u32 TCNTB;
- volatile u32 TCMPB;
- volatile u32 TCNTO;
-} s3c64xx_timer;
-
-typedef struct {
- volatile u32 TCFG0;
- volatile u32 TCFG1;
- volatile u32 TCON;
- s3c64xx_timer ch[4];
- volatile u32 TCNTB4;
- volatile u32 TCNTO4;
-} s3c64xx_timers;
-
-#endif /*__S3C64XX_H__*/
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
extern u32 *const T_num;
extern u32 *const T_den;
-extern u32 *const emif_sizes;
#endif
void config_data_eye_leveling_samples(u32 emif_base);
#define MACH_TYPE_MIOA701 1257
#define MACH_TYPE_ARMADILLO5X0 1260
#define MACH_TYPE_CC9P9360JS 1264
-#define MACH_TYPE_SMDK6400 1270
#define MACH_TYPE_NOKIA_N800 1271
#define MACH_TYPE_EP80219 1281
#define MACH_TYPE_GORAMO_MLR 1292
# define machine_is_cc9p9360js() (0)
#endif
-#ifdef CONFIG_MACH_SMDK6400
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDK6400
-# endif
-# define machine_is_smdk6400() (machine_arch_type == MACH_TYPE_SMDK6400)
-#else
-# define machine_is_smdk6400() (0)
-#endif
-
#ifdef CONFIG_MACH_NOKIA_N800
# ifdef machine_arch_type
# undef machine_arch_type
--- /dev/null
+/*
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Rohit Choraria <rohitkc@ti.com>
+ *
+ * (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_OMAP_GPMC_H
+#define __ASM_OMAP_GPMC_H
+
+#include <asm/arch/omap_gpmc.h>
+
+#define GPMC_BUF_EMPTY 0
+#define GPMC_BUF_FULL 1
+
+#define ECCCLEAR (0x1 << 8)
+#define ECCRESULTREG1 (0x1 << 0)
+#define ECCSIZE512BYTE 0xFF
+#define ECCSIZE1 (ECCSIZE512BYTE << 22)
+#define ECCSIZE0 (ECCSIZE512BYTE << 12)
+#define ECCSIZE0SEL (0x000 << 0)
+
+/* Generic ECC Layouts */
+/* Large Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 12,\
+ .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
+ 9, 10, 11, 12},\
+ .oobfree = {\
+ {.offset = 13,\
+ .length = 51 } } \
+}
+#endif
+
+/* Large Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 12,\
+ .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
+ 10, 11, 12, 13},\
+ .oobfree = {\
+ {.offset = 14,\
+ .length = 50 } } \
+}
+#endif
+
+/* Small Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 3,\
+ .eccpos = {1, 2, 3},\
+ .oobfree = {\
+ {.offset = 4,\
+ .length = 12 } } \
+}
+#endif
+
+/* Small Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 3,\
+ .eccpos = {2, 3, 4},\
+ .oobfree = {\
+ {.offset = 5,\
+ .length = 11 } } \
+}
+#endif
+
+#endif /* __ASM_OMAP_GPMC_H */
#include <config.h>
#include <asm-offsets.h>
+#include <linux/linkage.h>
/*
* This file handles the target-independent stages of the U-Boot
* have some work left to do at this point regarding memory, so
* call c_runtime_cpu_setup.
*
- * 6. Branch to either nand_boot() or board_init_r().
+ * 6. Branch to board_init_r().
*/
-/*
- * declare nand_boot() or board_init_r() to jump to at end of crt0
- */
-
-#if defined(CONFIG_NAND_SPL)
-
-.globl nand_boot
-
-#elif ! defined(CONFIG_SPL_BUILD)
-
-.globl board_init_r
-
-#endif
-
-/*
- * start and end of BSS
- */
-
-.globl __bss_start
-.globl __bss_end
-
/*
* entry point of crt0 sequence
*/
-.global _main
-
-_main:
+ENTRY(_main)
/*
* Set up initial C runtime environment and call board_init_f(0).
*/
-#if defined(CONFIG_NAND_SPL)
- /* deprecated, use instead CONFIG_SPL_BUILD */
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
-#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr sp, =(CONFIG_SPL_STACK)
#else
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
/*
* Set up intermediate environment (new sp and gd) and call
- * relocate_code(addr_sp, gd, addr_moni). Trick here is that
- * we'll return 'here' but relocated.
+ * relocate_code(addr_moni). Trick here is that we'll return
+ * 'here' but relocated.
*/
ldr sp, [r8, #GD_START_ADDR_SP] /* r8 = gd->start_addr_sp */
adr lr, here
ldr r0, [r8, #GD_RELOC_OFF] /* lr = gd->start_addr_sp */
add lr, lr, r0
- ldr r0, [r8, #GD_START_ADDR_SP] /* r0 = gd->start_addr_sp */
- mov r1, r8 /* r1 = gd */
- ldr r2, [r8, #GD_RELOCADDR] /* r2 = gd->relocaddr */
+ ldr r0, [r8, #GD_RELOCADDR] /* r0 = gd->relocaddr */
b relocate_code
here:
bl coloured_LED_init
bl red_led_on
-#if defined(CONFIG_NAND_SPL)
-
- /* call _nand_boot() */
- ldr pc, =nand_boot
-
-#else
-
/* call board_init_r(gd_t *id, ulong dest_addr) */
mov r0, r8 /* gd_t */
ldr r1, [r8, #GD_RELOCADDR] /* dest_addr */
/* call board_init_r */
ldr pc, =board_init_r /* this is auto-relocated! */
-#endif
-
/* we should not return here. */
#endif
+
+ENDPROC(_main)
}
. = ALIGN (4);
+
+ __image_copy_end = .;
+
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
}
. = ALIGN (4);
+
+ __image_copy_end = .;
+
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
}
. = ALIGN (4);
+
+ __image_copy_end = .;
+
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
.text :
{
__start = .;
- arch/arm/cpu/arm926ejs/start.o (.text)
+ arch/arm/cpu/arm926ejs/start.o (.text*)
*(.text*)
} >.sram
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ usdhc_cfg[1].max_bus_width = 4;
+
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
}
#endif
-u32 get_board_rev(void)
-{
- return 0x63000;
-}
-
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
.text :
{
__start = .;
- arch/arm/cpu/arm926ejs/start.o (.text)
+ arch/arm/cpu/arm926ejs/start.o (.text*)
*(.text*)
} >.sram
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm926ejs/start.o (.text)
- arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text)
- drivers/mtd/nand/libnand.o (.text)
+ arch/arm/cpu/arm926ejs/start.o (.text*)
+ arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text*)
+ drivers/mtd/nand/libnand.o (.text*)
*(.text*)
}
. = ALIGN(4);
- .rodata : { *(.rodata) }
+ .rodata : { *(.rodata*) }
. = ALIGN(4);
.data : {
}
. = ALIGN(4);
+ __image_copy_end = .;
__rel_dyn_start = .;
__rel_dyn_end = .;
__dynsym_start = .;
}
. = ALIGN (4);
+
+ __image_copy_end = .;
+
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/arm/cpu/arm1136/start.o (.text)
- board/freescale/mx31ads/libmx31ads.o (.text)
- arch/arm/lib/libarm.o (.text)
- net/libnet.o (.text)
- drivers/mtd/libmtd.o (.text)
+ arch/arm/cpu/arm1136/start.o (.text*)
+ board/freescale/mx31ads/libmx31ads.o (.text*)
+ arch/arm/lib/libarm.o (.text*)
+ net/libnet.o (.text*)
+ drivers/mtd/libmtd.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o(.text)
+ common/env_embedded.o(.text*)
- *(.text)
+ *(.text*)
}
. = ALIGN(4);
- .rodata : { *(.rodata) }
+ .rodata : { *(.rodata*) }
. = ALIGN(4);
.data : {
- *(.data)
+ *(.data*)
}
. = ALIGN(4);
LIB = $(obj)lib$(BOARD).o
+ifdef CONFIG_SPL_BUILD
+SOBJS := lowlevel_init.o
+endif
COBJS := mx31pdk.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+++ /dev/null
-ifdef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = 0x87ec0000
-else
-CONFIG_SYS_TEXT_BASE = 0x87f00000
-endif
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong bootflag)
+{
+ relocate_code(CONFIG_SPL_TEXT_BASE);
+ asm volatile("ldr pc, =nand_boot");
+}
+#endif
+
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}
+#ifdef CONFIG_NAND_MXC
+static void setup_iomux_nand(void)
+{
+ u32 i, reg;
+ #define M4IF_GENP_WEIM_MM_MASK 0x00000001
+ #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
+
+ reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
+ reg &= ~M4IF_GENP_WEIM_MM_MASK;
+ __raw_writel(reg, M4IF_BASE_ADDR + 0xc);
+ for (i = 0x4; i < 0x94; i += 0x18) {
+ reg = __raw_readl(WEIM_BASE_ADDR + i);
+ reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
+ __raw_writel(reg, WEIM_BASE_ADDR + i);
+ }
+
+ mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
+ mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
+ mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA0, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA1, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA2, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA3, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA4, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA5, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA6, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA7, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+}
+#else
+static void setup_iomux_nand(void)
+{
+}
+#endif
+
static void setup_iomux_uart(void)
{
/* UART1 RXD */
int board_early_init_f(void)
{
+ setup_iomux_nand();
setup_iomux_uart();
return 0;
}
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
return 0;
}
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ return 0;
+}
+
int checkboard(void)
{
int rev = mx6sabre_rev();
MX6Q SABRELITE U-Boot > mmc dev 0
MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200
- MX6Q SABRELITE U-Boot > sf probe 1
+ MX6Q SABRELITE U-Boot > sf probe
MX6Q SABRELITE U-Boot > sf erase 0 0x40000
MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000
To build U-Boot for the SabreLite board:
make mx6qsabrelite_config
- make u-boot.imx
+ make
To copy the resulting u-boot.imx to the SD card:
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ usdhc_cfg[1].max_bus_width = 4;
+
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
}
#endif
-u32 get_board_rev(void)
-{
- return 0x63000 ;
-}
-
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
+
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
- return !gpio_get_value(USDHC2_CD_GPIO);
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
case USDHC3_BASE_ADDR:
- return !gpio_get_value(USDHC3_CD_GPIO);
- default:
- return 1; /* eMMC/uSDHC4 is always present */
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = 1; /* eMMC/uSDHC4 is always present */
+ break;
}
+
+ return ret;
}
int board_mmc_init(bd_t *bis)
{
int i;
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 SD2
+ * mmc1 SD3
+ * mmc2 eMMC
+ */
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
return 0;
}
-u32 get_board_rev(void)
-{
- return 0x63000;
-}
-
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ /* 8 bit bus width */
+ {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ return 0;
+}
+
int checkboard(void)
{
puts("Board: MX6Q-SabreSD\n");
#include <twl4030.h>
#include <netdev.h>
#include <asm/gpio.h>
-#include <asm/arch/omap_gpmc.h>
+#include <asm/omap_gpmc.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mmc_host_def.h>
LIB = $(obj)lib$(BOARD).o
-COBJS := tx25.o
+ifdef CONFIG_SPL_BUILD
SOBJS := lowlevel_init.o
+endif
+COBJS := tx25.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
+++ /dev/null
-ifdef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = 0x810c0000
-else
-CONFIG_SYS_TEXT_BASE = 0x81200000
-endif
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong bootflag)
+{
+ relocate_code(CONFIG_SPL_TEXT_BASE);
+ asm volatile("ldr pc, =nand_boot");
+}
+#endif
+
#ifdef CONFIG_FEC_MXC
#define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7)
#define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9)
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/omap_gpmc.h>
+#include <asm/omap_gpmc.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
#include "overo.h"
.sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
.sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
.zq_config = MT41J256M8HX15E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY,
+ .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
+ PHY_EN_DYN_PWRDN,
};
#endif
samsung,slope = <274761730>;
samsung,dc-value = <25>;
};
+
+ fimd@14400000 {
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <2560>;
+ samsung,vl-row = <1600>;
+ samsung,vl-width = <2560>;
+ samsung,vl-height = <1600>;
+
+ samsung,vl-clkp;
+ samsung,vl-dp;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <32>;
+ samsung,vl-hbpd = <80>;
+ samsung,vl-hfpd = <48>;
+ samsung,vl-vspw = <6>;
+ samsung,vl-vbpd = <37>;
+ samsung,vl-vfpd = <3>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <3>;
+ samsung,interface-mode = <1>;
+ samsung,dp-enabled = <1>;
+ samsung,dual-lcd-enabled = <0>;
+ };
+
+ dp@145b0000 {
+ samsung,lt-status = <0>;
+
+ samsung,master-mode = <0>;
+ samsung,bist-mode = <0>;
+ samsung,bist-pattern = <0>;
+ samsung,h-sync-polarity = <0>;
+ samsung,v-sync-polarity = <0>;
+ samsung,interlaced = <0>;
+ samsung,color-space = <0>;
+ samsung,dynamic-range = <0>;
+ samsung,ycbcr-coeff = <0>;
+ samsung,color-depth = <1>;
+ };
};
val = readl(&clk->mux_stat_core1);
} while ((val | MUX_MPLL_SEL_MASK) != val);
- clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK);
- clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK);
- clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK);
- clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK);
+ clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
+ clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
+ clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
+ clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
| MUX_GPLL_SEL_MASK;
do {
val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
arm_clk_ratio->apll_sdiv);
writel(val, &clk->apll_con0);
- while (readl(&clk->apll_con0) & APLL_CON0_LOCKED)
+ while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
;
/* Set MPLL */
writel(MPLL_CON1_VAL, &clk->mpll_con1);
val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
writel(val, &clk->mpll_con0);
- while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED)
+ while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
;
/* Set BPLL */
writel(BPLL_CON1_VAL, &clk->bpll_con1);
val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
writel(val, &clk->bpll_con0);
- while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED)
+ while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
;
/* Set CPLL */
writel(CPLL_CON1_VAL, &clk->cpll_con1);
val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
writel(val, &clk->cpll_con0);
- while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED)
+ while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
;
/* Set GPLL */
writel(GPLL_CON1_VAL, &clk->gpll_con1);
val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
writel(val, &clk->gpll_con0);
- while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED)
+ while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
;
/* Set EPLL */
writel(EPLL_CON1_VAL, &clk->epll_con1);
val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
writel(val, &clk->epll_con0);
- while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED)
+ while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
;
/* Set VPLL */
writel(VPLL_CON1_VAL, &clk->vpll_con1);
val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
writel(val, &clk->vpll_con0);
- while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED)
+ while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
;
writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
#define TOP2_VAL 0x0110000
/* CLK_SRC_PERIC0 */
-#define PWM_SEL 0
+#define PWM_SEL 6
#define UART3_SEL 6
#define UART2_SEL 6
#define UART1_SEL 6
.text :
{
__start = .;
- arch/arm/cpu/armv7/start.o (.text)
+ arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sram
. = ALIGN(4);
u32 smc_bw_conf, smc_bc_conf;
struct fdt_sromc config;
fdt_addr_t base_addr;
- int node;
#ifdef CONFIG_OF_CONTROL
+ int node;
+
node = decode_sromc(gd->fdt_blob, &config);
if (node < 0) {
debug("%s: Could not find sromc configuration\n", __func__);
#endif
#ifdef CONFIG_LCD
-void cfg_lcd_gpio(void)
+void exynos_cfg_lcd_gpio(void)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
}
+void exynos_set_dp_phy(unsigned int onoff)
+{
+ set_dp_phy_ctrl(onoff);
+}
+
+#ifndef CONFIG_OF_CONTROL
vidinfo_t panel_info = {
.vl_freq = 60,
.vl_col = 2560,
.vl_cmd_allow_len = 0xf,
.win_id = 3,
- .cfg_gpio = cfg_lcd_gpio,
- .backlight_on = NULL,
- .lcd_power_on = NULL,
- .reset_lcd = NULL,
.dual_lcd_enabled = 0,
.init_delay = 0,
};
static struct exynos_dp_platform_data dp_platform_data = {
- .phy_enable = set_dp_phy_ctrl,
.edp_dev_info = &edp_info,
};
+#endif
void init_panel_info(vidinfo_t *vid)
{
+#ifndef CONFIG_OF_CONTROL
vid->rgb_mode = MODE_RGB_P,
exynos_set_dp_platform_data(&dp_platform_data);
+#endif
}
#endif
+++ /dev/null
-#
-# Generated files
-#
-
-/config.tmp
+++ /dev/null
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS-y := smdk6400.o
-SOBJS := lowlevel_init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS-y))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(SOBJS) $(OBJS)
- $(call cmd_link_o_target, $(SOBJS) $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# SAMSUNG SMDK6400 board with mDirac3 (ARM1176) cpu
-#
-# see http://www.samsung.com/ for more information on SAMSUNG
-
-# On SMDK6400 we use the 64 MB SDRAM bank at
-#
-# 0x50000000 to 0x58000000
-#
-# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000
-#
-# we load ourselves to 0x57e00000 without MMU
-# with MMU, load address is changed to 0xc7e00000
-#
-# download area is 0x5000c000
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = $(RAM_TEXT)
-else
-CONFIG_SYS_TEXT_BASE = 0
-endif
+++ /dev/null
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the Samsung SMDK2410 by
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-
-#include <asm/arch/s3c6400.h>
-
-#ifdef CONFIG_SERIAL1
-#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
-#elif defined(CONFIG_SERIAL2)
-#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET)
-#else
-#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET)
-#endif
-
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
- .globl lowlevel_init
-lowlevel_init:
- mov r12, lr
-
- /* LED on only #8 */
- ldr r0, =ELFIN_GPIO_BASE
- ldr r1, =0x55540000
- str r1, [r0, #GPNCON_OFFSET]
-
- ldr r1, =0x55555555
- str r1, [r0, #GPNPUD_OFFSET]
-
- ldr r1, =0xf000
- str r1, [r0, #GPNDAT_OFFSET]
-
- /* Disable Watchdog */
- ldr r0, =0x7e000000 @0x7e004000
- orr r0, r0, #0x4000
- mov r1, #0
- str r1, [r0]
-
- /* External interrupt pending clear */
- ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/
- ldr r1, [r0]
- str r1, [r0]
-
- ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000
- ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000
-
- /* Disable all interrupts (VIC0 and VIC1) */
- mvn r3, #0x0
- str r3, [r0, #oINTMSK]
- str r3, [r1, #oINTMSK]
-
- /* Set all interrupts as IRQ */
- mov r3, #0x0
- str r3, [r0, #oINTMOD]
- str r3, [r1, #oINTMOD]
-
- /* Pending Interrupt Clear */
- mov r3, #0x0
- str r3, [r0, #oVECTADDR]
- str r3, [r1, #oVECTADDR]
-
- /* init system clock */
- bl system_clock_init
-
-#ifndef CONFIG_NAND_SPL
- /* for UART */
- bl uart_asm_init
-#endif
-
-#ifdef CONFIG_BOOT_NAND
- /* simple init for NAND */
- bl nand_asm_init
-#endif
-
- /* Memory subsystem address 0x7e00f120 */
- ldr r0, =ELFIN_MEM_SYS_CFG
-
- /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
- mov r1, #S3C64XX_MEM_SYS_CFG_NAND
- str r1, [r0]
-
- bl mem_ctrl_asm_init
-
-/* Wakeup support. Don't know if it's going to be used, untested. */
- ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
- ldr r1, [r0]
- bic r1, r1, #0xfffffff7
- cmp r1, #0x8
- beq wakeup_reset
-
-1:
- mov lr, r12
- mov pc, lr
-
-wakeup_reset:
-
- /* Clear wakeup status register */
- ldr r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
- ldr r1, [r0]
- str r1, [r0]
-
- /* LED test */
- ldr r0, =ELFIN_GPIO_BASE
- ldr r1, =0x3000
- str r1, [r0, #GPNDAT_OFFSET]
-
- /* Load return address and jump to kernel */
- ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
- /* r1 = physical address of s3c6400_cpu_resume function */
- ldr r1, [r0]
- /* Jump to kernel (sleep-s3c6400.S) */
- mov pc, r1
- nop
- nop
-/*
- * system_clock_init: Initialize core clock and bus clock.
- * void system_clock_init(void)
- */
-system_clock_init:
- ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */
-
-#ifdef CONFIG_SYNC_MODE
- ldr r1, [r0, #OTHERS_OFFSET]
- mov r2, #0x40
- orr r1, r1, r2
- str r1, [r0, #OTHERS_OFFSET]
-
- nop
- nop
- nop
- nop
- nop
-
- ldr r2, =0x80
- orr r1, r1, r2
- str r1, [r0, #OTHERS_OFFSET]
-
-check_syncack:
- ldr r1, [r0, #OTHERS_OFFSET]
- ldr r2, =0xf00
- and r1, r1, r2
- cmp r1, #0xf00
- bne check_syncack
-#else /* ASYNC Mode */
- nop
- nop
- nop
- nop
- nop
-
- /*
- * This was unconditional in original Samsung sources, but it doesn't
- * seem to make much sense on S3C6400.
- */
-#ifndef CONFIG_S3C6400
- ldr r1, [r0, #OTHERS_OFFSET]
- bic r1, r1, #0xC0
- orr r1, r1, #0x40
- str r1, [r0, #OTHERS_OFFSET]
-
-wait_for_async:
- ldr r1, [r0, #OTHERS_OFFSET]
- and r1, r1, #0xf00
- cmp r1, #0x0
- bne wait_for_async
-#endif
-
- ldr r1, [r0, #OTHERS_OFFSET]
- bic r1, r1, #0x40
- str r1, [r0, #OTHERS_OFFSET]
-#endif
-
- mov r1, #0xff00
- orr r1, r1, #0xff
- str r1, [r0, #APLL_LOCK_OFFSET]
- str r1, [r0, #MPLL_LOCK_OFFSET]
-
- /* Set Clock Divider */
- ldr r1, [r0, #CLK_DIV0_OFFSET]
- bic r1, r1, #0x30000
- bic r1, r1, #0xff00
- bic r1, r1, #0xff
- ldr r2, =CLK_DIV_VAL
- orr r1, r1, r2
- str r1, [r0, #CLK_DIV0_OFFSET]
-
- ldr r1, =APLL_VAL
- str r1, [r0, #APLL_CON_OFFSET]
- ldr r1, =MPLL_VAL
- str r1, [r0, #MPLL_CON_OFFSET]
-
- /* FOUT of EPLL is 96MHz */
- ldr r1, =0x200203
- str r1, [r0, #EPLL_CON0_OFFSET]
- ldr r1, =0x0
- str r1, [r0, #EPLL_CON1_OFFSET]
-
- /* APLL, MPLL, EPLL select to Fout */
- ldr r1, [r0, #CLK_SRC_OFFSET]
- orr r1, r1, #0x7
- str r1, [r0, #CLK_SRC_OFFSET]
-
- /* wait at least 200us to stablize all clock */
- mov r1, #0x10000
-1: subs r1, r1, #1
- bne 1b
-
- /* Synchronization for VIC port */
-#if defined(CONFIG_SYNC_MODE)
- ldr r1, [r0, #OTHERS_OFFSET]
- orr r1, r1, #0x20
- str r1, [r0, #OTHERS_OFFSET]
-#elif !defined(CONFIG_S3C6400)
- /* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */
- ldr r1, [r0, #OTHERS_OFFSET]
- bic r1, r1, #0x20
- str r1, [r0, #OTHERS_OFFSET]
-#endif
- mov pc, lr
-
-
-#ifndef CONFIG_NAND_SPL
-/*
- * uart_asm_init: Initialize UART's pins
- */
-uart_asm_init:
- /* set GPIO to enable UART */
- ldr r0, =ELFIN_GPIO_BASE
- ldr r1, =0x220022
- str r1, [r0, #GPACON_OFFSET]
- mov pc, lr
-#endif
-
-#ifdef CONFIG_BOOT_NAND
-/*
- * NAND Interface init for SMDK6400
- */
-nand_asm_init:
- ldr r0, =ELFIN_NAND_BASE
- ldr r1, [r0, #NFCONF_OFFSET]
- orr r1, r1, #0x70
- orr r1, r1, #0x7700
- str r1, [r0, #NFCONF_OFFSET]
-
- ldr r1, [r0, #NFCONT_OFFSET]
- orr r1, r1, #0x07
- str r1, [r0, #NFCONT_OFFSET]
-
- mov pc, lr
-#endif
-
-#ifdef CONFIG_ENABLE_MMU
-/*
- * MMU Table for SMDK6400
- */
-
- /* form a first-level section entry */
-.macro FL_SECTION_ENTRY base,ap,d,c,b
- .word (\base << 20) | (\ap << 10) | \
- (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1)
-.endm
-
-.section .mmudata, "a"
- .align 14
- /* the following alignment creates the mmu table at address 0x4000. */
- .globl mmu_table
-mmu_table:
- .set __base, 0
- /* 1:1 mapping for debugging */
- .rept 0xA00
- FL_SECTION_ENTRY __base, 3, 0, 0, 0
- .set __base, __base + 1
- .endr
-
- /* access is not allowed. */
- .rept 0xC00 - 0xA00
- .word 0x00000000
- .endr
-
- /* 128MB for SDRAM 0xC0000000 -> 0x50000000 */
- .set __base, 0x500
- .rept 0xC80 - 0xC00
- FL_SECTION_ENTRY __base, 3, 0, 1, 1
- .set __base, __base + 1
- .endr
-
- /* access is not allowed. */
- .rept 0x1000 - 0xc80
- .word 0x00000000
- .endr
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/s3c6400.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-#define CS8900_Tacs 0x0 /* 0clk address set-up */
-#define CS8900_Tcos 0x4 /* 4clk chip selection set-up */
-#define CS8900_Tacc 0xE /* 14clk access cycle */
-#define CS8900_Tcoh 0x1 /* 1clk chip selection hold */
-#define CS8900_Tah 0x4 /* 4clk address holding time */
-#define CS8900_Tacp 0x6 /* 6clk page mode access cycle */
-#define CS8900_PMC 0x0 /* normal(1data)page mode configuration */
-
-static inline void delay(unsigned long loops)
-{
- __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
- "bne 1b"
- : "=r" (loops) : "0" (loops));
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-static void cs8900_pre_init(void)
-{
- SROM_BW_REG &= ~(0xf << 4);
- SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4);
- SROM_BC1_REG = ((CS8900_Tacs << 28) + (CS8900_Tcos << 24) +
- (CS8900_Tacc << 16) + (CS8900_Tcoh << 12) +
- (CS8900_Tah << 8) + (CS8900_Tacp << 4) + CS8900_PMC);
-}
-
-int board_init(void)
-{
- cs8900_pre_init();
-
- /* NOR-flash in SROM0 */
-
- /* Enable WAIT */
- SROM_BW_REG |= 4 | 8 | 1;
-
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
-
- return 0;
-}
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- printf("Board: SMDK6400\n");
- return 0;
-}
-#endif
-
-#ifdef CONFIG_ENABLE_MMU
-ulong virt_to_phy_smdk6400(ulong addr)
-{
- if ((0xc0000000 <= addr) && (addr < 0xc8000000))
- return addr - 0xc0000000 + 0x50000000;
- else
- printf("do not support this address : %08lx\n", addr);
-
- return addr;
-}
-#endif
-
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info)
-{
- if (banknum == 0) { /* non-CFI boot flash */
- info->portwidth = FLASH_CFI_16BIT;
- info->chipwidth = FLASH_CFI_BY16;
- info->interface = FLASH_CFI_X16;
- return 1;
- } else
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_CS8900
- rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
- return rc;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-void board_init_f(unsigned long bootflag)
-{
- relocate_code(CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
- CONFIG_SYS_TEXT_BASE);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/arm1176/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
-
- . = align(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = align(4);
- .mmudata : { *(.mmudata) }
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
return 0;
}
-static void lcd_reset(void)
+void exynos_reset_lcd(void)
{
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
.vl_cmd_allow_len = 0xf,
.win_id = 3,
- .cfg_gpio = NULL,
- .backlight_on = NULL,
- .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */
- .reset_lcd = lcd_reset,
.dual_lcd_enabled = 0,
.init_delay = 0,
puts("LCD pmic initialisation error!\n");
}
-static void lcd_cfg_gpio(void)
+void exynos_cfg_lcd_gpio(void)
{
unsigned int i, f3_end = 4;
spi_init();
}
-static void reset_lcd(void)
+void exynos_reset_lcd(void)
{
s5p_gpio_set_value(&gpio2->y4, 5, 1);
udelay(10000);
udelay(100);
}
-static void lcd_power_on(void)
+void exynos_lcd_power_on(void)
{
struct pmic *p = pmic_get("MAX8998_PMIC");
.vl_cmd_allow_len = 0xf,
.win_id = 0,
- .cfg_gpio = lcd_cfg_gpio,
- .backlight_on = NULL,
- .lcd_power_on = lcd_power_on,
- .reset_lcd = reset_lcd,
.dual_lcd_enabled = 0,
.init_delay = 0,
.mipi_enabled = 0,
};
+void exynos_cfg_ldo(void)
+{
+ ld9040_cfg_ldo();
+}
+
+void exynos_enable_ldo(unsigned int onoff)
+{
+ ld9040_enable_ldo(onoff);
+}
+
void init_panel_info(vidinfo_t *vid)
{
vid->logo_on = 1;
vid->pclk_name = 1; /* MPLL */
vid->sclk_div = 1;
- vid->cfg_ldo = ld9040_cfg_ldo;
- vid->enable_ldo = ld9040_enable_ldo;
-
setenv("lcdinfo", "lcd=ld9040");
}
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
else if (board_is_bone_lt())
- config_ddr(303, MT41K256M16HA125E_IOCTRL_VALUE,
+ config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
&ddr3_beagleblack_data,
&ddr3_beagleblack_cmd_ctrl_data,
&ddr3_beagleblack_emif_reg_data, 0);
# (mem base + reserved)
# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80e80000
+#CONFIG_SYS_TEXT_BASE = 0x80e80000
# Used with full SRAM boot.
# This is either with a GP system or a signed boot image.
# Handy to get symbols to debug ROM version.
#CONFIG_SYS_TEXT_BASE = 0x0
-#CONFIG_SYS_TEXT_BASE = 0x08000000
+CONFIG_SYS_TEXT_BASE = 0x08000000
#CONFIG_SYS_TEXT_BASE = 0x04000000
__asm__ __volatile__("": : :"memory"); /* limit compiler scope */
- /* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx.
- * If we are running in flash prior to relocation and we use data
- * here which is not pc relative we need to get the address correct.
- * We need to find the current flash mapping to dress up the initial
- * pointer load. As long as this is const data we should be ok.
- */
- if((early) && running_in_flash()){
- sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base());
- /* NOR internal boot offset is 0x4000 from xloader signature */
- if(running_from_internal_boot())
- sdata = (sdrc_data_t *)((u32)sdata + 0x4000);
- }
-
if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) {
if(mtype == DDR_COMBO){
pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */
* Routine: dram_init
* Description: sets uboots idea of sdram size
**********************************************/
-int dram_init (void)
+int dram_init(void)
{
unsigned int size0=0,size1=0;
- u32 mtype, btype, rev;
+ u32 mtype, btype;
u8 chg_on = 0x5; /* enable charge of back up battery */
u8 vmode_on = 0x8C;
#define NOT_EARLY 0
btype = get_board_type();
mtype = get_mem_type();
- rev = get_cpu_rev();
display_board_info(btype);
if (btype == BOARD_H4_MENELAUS){
size0 = get_sdr_cs_size(SDRC_CS0_OSET);
size1 = get_sdr_cs_size(SDRC_CS1_OSET);
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size0;
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, size0 + size1);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ unsigned int size0, size1;
+ u32 rev;
+
+ rev = get_cpu_rev();
+ size0 = get_sdr_cs_size(SDRC_CS0_OSET);
+ size1 = get_sdr_cs_size(SDRC_CS1_OSET);
+
if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
else /* ES2 and above can remap at 32MB granularity */
gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
gd->bd->bi_dram[1].size = size1;
- return 0;
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = size0;
}
/**********************************************************
# TI OSK board with OMAP5912 (ARM925EJS) cpu
# see http://www.ti.com/ for more information on Texas Instruments
#
-# OSK has 1 bank of 256 MB SDRAM
+# OSK has 1 bank of 32 MB SDRAM
# Physical Address:
-# 1000'0000 to 2000'0000
+# 1000'0000 to 1200'0000
#
#
# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
# (mem base + reserved)
#
-# we load ourself to 1108'0000
+# When running from RAM use address 1108'0000, otherwise when
+# booting from NOR flash link to address 0000'0000.
#
-#
-
-CONFIG_SYS_TEXT_BASE = 0x11080000
+CONFIG_SYS_TEXT_BASE = 0x00000000
+#CONFIG_SYS_TEXT_BASE = 0x11080000
ldr r1, VAL_MPU_CNTL_TIMER
str r1, [r0]
+ /*
+ * Setup a temporary stack
+ */
+ ldr sp, SRAM_STACK
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+
+ /*
+ * Save the old lr(passed in ip) and the current lr to stack
+ */
+ push {ip, lr}
+
+ /*
+ * go setup pll, mux, memory
+ */
+ bl s_init
+ pop {ip, pc}
+
/* back to arch calling code */
mov pc, lr
VAL_ARM_IDLECT3:
.word 0x00000015
+SRAM_STACK:
+ .word CONFIG_SYS_INIT_SP_ADDR
+
/* command values */
.equ CMD_SDRAM_NOP, 0x00000000
.equ CMD_SDRAM_PRECHARGE, 0x00000001
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x10000100;
+ flash__init();
+ ether__init();
+
+ return 0;
+}
+
+void s_init(void)
+{
/* Configure MUX settings */
set_muxconf_regs ();
peripheral_power_enable ();
* ... rkw ...
*/
icache_enable ();
-
- flash__init ();
- ether__init ();
- return 0;
}
/******************************
Routine:
Description:
******************************/
-int dram_init (void)
+int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
return 0;
}
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
/******************************************************
Routine: set_muxconf_regs
Description: Setting up the configuration Mux registers
+++ /dev/null
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS := evm.o
-
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-clean:
- rm -f $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Texas Instruments Incorporated, <www.ti.com>
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <twl6035.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-
-#include "mux_data.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const struct omap_sysinfo sysinfo = {
- "Board: OMAP5430 EVM\n"
-};
-
-/**
- * @brief board_init
- *
- * @return 0
- */
-int board_init(void)
-{
- gpmc_init();
- gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
- gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return 0;
-}
-
-/**
- * @brief misc_init_r - Configure EVM board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * @return 0
- */
-int misc_init_r(void)
-{
-#ifdef CONFIG_TWL6035_POWER
- twl6035_init_settings();
-#endif
- return 0;
-}
-
-void set_muxconf_regs_essential(void)
-{
- do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
- sizeof(core_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
-
- do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
- sizeof(wkup_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
-}
-
-void set_muxconf_regs_non_essential(void)
-{
- do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
- sizeof(core_padconf_array_non_essential) /
- sizeof(struct pad_conf_entry));
-
- do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
- sizeof(wkup_padconf_array_non_essential) /
- sizeof(struct pad_conf_entry));
-}
-
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
-int board_mmc_init(bd_t *bis)
-{
- omap_mmc_init(0, 0, 0, -1, -1);
- omap_mmc_init(1, 0, 0, -1, -1);
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * Sricharan R <r.sricharan@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _EVM5430_MUX_DATA_H
-#define _EVM5430_MUX_DATA_H
-
-#include <asm/arch/mux_omap5.h>
-
-const struct pad_conf_entry core_padconf_array_essential[] = {
-
- {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */
- {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */
- {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */
- {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */
- {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */
- {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */
- {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */
- {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */
- {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */
- {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */
- {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */
- {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */
- {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0*/
- {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1*/
- {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2*/
- {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/
- {UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */
- {UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */
- {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */
- {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */
- {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */
- {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */
- {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/
- {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */
- {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */
- {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */
- {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */
-
-};
-
-const struct pad_conf_entry wkup_padconf_array_essential[] = {
-
- {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
- {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
- {SYS_32K, (IEN | M0)}, /* SYS_32K */
-
-};
-
-const struct pad_conf_entry core_padconf_array_non_essential[] = {
-
- {C2C_DATAIN0, (IEN | M0)}, /* C2C_DATAIN0 */
- {C2C_DATAIN1, (IEN | M0)}, /* C2C_DATAIN1 */
- {C2C_DATAIN2, (IEN | M0)}, /* C2C_DATAIN2 */
- {C2C_DATAIN3, (IEN | M0)}, /* C2C_DATAIN3 */
- {C2C_DATAIN4, (IEN | M0)}, /* C2C_DATAIN4 */
- {C2C_DATAIN5, (IEN | M0)}, /* C2C_DATAIN5 */
- {C2C_DATAIN6, (IEN | M0)}, /* C2C_DATAIN6 */
- {C2C_DATAIN7, (IEN | M0)}, /* C2C_DATAIN7 */
- {C2C_CLKIN1, (IEN | M0)}, /* C2C_CLKIN1 */
- {C2C_CLKIN0, (IEN | M0)}, /* C2C_CLKIN0 */
- {C2C_CLKOUT0, (M0)}, /* C2C_CLKOUT0 */
- {C2C_CLKOUT1, (M0)}, /* C2C_CLKOUT1 */
- {C2C_DATAOUT0, (M0)}, /* C2C_DATAOUT0 */
- {C2C_DATAOUT1, (M0)}, /* C2C_DATAOUT1 */
- {C2C_DATAOUT2, (M0)}, /* C2C_DATAOUT2 */
- {C2C_DATAOUT3, (M0)}, /* C2C_DATAOUT3 */
- {C2C_DATAOUT4, (M0)}, /* C2C_DATAOUT4 */
- {C2C_DATAOUT5, (M0)}, /* C2C_DATAOUT5 */
- {C2C_DATAOUT6, (M0)}, /* C2C_DATAOUT6 */
- {C2C_DATAOUT7, (M0)}, /* C2C_DATAOUT7 */
- {C2C_DATA8, (IEN | M0)}, /* C2C_DATA8 */
- {C2C_DATA9, (IEN | M0)}, /* C2C_DATA9 */
- {C2C_DATA10, (IEN | M0)}, /* C2C_DATA10 */
- {C2C_DATA11, (IEN | M0)}, /* C2C_DATA11 */
- {C2C_DATA12, (IEN | M0)}, /* C2C_DATA12 */
- {C2C_DATA13, (IEN | M0)}, /* C2C_DATA13 */
- {C2C_DATA14, (IEN | M0)}, /* C2C_DATA14 */
- {C2C_DATA15, (IEN | M0)}, /* C2C_DATA15 */
- {LLIB_WAKEREQOUT, (PTU | IEN | M6)}, /* GPIO2_32 */
- {LLIA_WAKEREQOUT, (M1)}, /* C2C_WAKEREQOUT */
- {HSI1_ACREADY, (PTD | M6)}, /* GPIO3_64 */
- {HSI1_CAREADY, (PTD | M6)}, /* GPIO3_65 */
- {HSI1_ACWAKE, (PTD | IEN | M6)}, /* GPIO3_66 */
- {HSI1_CAWAKE, (PTU | IEN | M6)}, /* GPIO3_67 */
- {HSI1_ACFLAG, (PTD | IEN | M6)}, /* GPIO3_68 */
- {HSI1_ACDATA, (PTD | M6)}, /* GPIO3_69 */
- {HSI1_CAFLAG, (M6)}, /* GPIO3_70 */
- {HSI1_CADATA, (M6)}, /* GPIO3_71 */
- {UART1_TX, (M0)}, /* UART1_TX */
- {UART1_CTS, (PTU | IEN | M0)}, /* UART1_CTS */
- {UART1_RX, (PTU | IEN | M0)}, /* UART1_RX */
- {UART1_RTS, (M0)}, /* UART1_RTS */
- {HSI2_CAREADY, (IEN | M0)}, /* HSI2_CAREADY */
- {HSI2_ACREADY, (OFF_EN | M0)}, /* HSI2_ACREADY */
- {HSI2_CAWAKE, (IEN | PTD | M0)}, /* HSI2_CAWAKE */
- {HSI2_ACWAKE, (M0)}, /* HSI2_ACWAKE */
- {HSI2_CAFLAG, (IEN | PTD | M0)}, /* HSI2_CAFLAG */
- {HSI2_CADATA, (IEN | PTD | M0)}, /* HSI2_CADATA */
- {HSI2_ACFLAG, (M0)}, /* HSI2_ACFLAG */
- {HSI2_ACDATA, (M0)}, /* HSI2_ACDATA */
- {UART2_RTS, (IEN | M1)}, /* MCSPI3_SOMI */
- {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */
- {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */
- {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */
- {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */
- {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */
- {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */
- {DSIPORTA_LANE0Y, (IEN | M0)}, /* DSIPORTA_LANE0Y */
- {DSIPORTA_LANE1X, (IEN | M0)}, /* DSIPORTA_LANE1X */
- {DSIPORTA_LANE1Y, (IEN | M0)}, /* DSIPORTA_LANE1Y */
- {DSIPORTA_LANE2X, (IEN | M0)}, /* DSIPORTA_LANE2X */
- {DSIPORTA_LANE2Y, (IEN | M0)}, /* DSIPORTA_LANE2Y */
- {DSIPORTA_LANE3X, (IEN | M0)}, /* DSIPORTA_LANE3X */
- {DSIPORTA_LANE3Y, (IEN | M0)}, /* DSIPORTA_LANE3Y */
- {DSIPORTA_LANE4X, (IEN | M0)}, /* DSIPORTA_LANE4X */
- {DSIPORTA_LANE4Y, (IEN | M0)}, /* DSIPORTA_LANE4Y */
- {TIMER9_PWM_EVT, (IEN | M0)}, /* TIMER9_PWM_EVT */
- {DSIPORTC_TE0, (IEN | M0)}, /* DSIPORTC_TE0 */
- {DSIPORTC_LANE0X, (IEN | M0)}, /* DSIPORTC_LANE0X */
- {DSIPORTC_LANE0Y, (IEN | M0)}, /* DSIPORTC_LANE0Y */
- {DSIPORTC_LANE1X, (IEN | M0)}, /* DSIPORTC_LANE1X */
- {DSIPORTC_LANE1Y, (IEN | M0)}, /* DSIPORTC_LANE1Y */
- {DSIPORTC_LANE2X, (IEN | M0)}, /* DSIPORTC_LANE2X */
- {DSIPORTC_LANE2Y, (IEN | M0)}, /* DSIPORTC_LANE2Y */
- {DSIPORTC_LANE3X, (IEN | M0)}, /* DSIPORTC_LANE3X */
- {DSIPORTC_LANE3Y, (IEN | M0)}, /* DSIPORTC_LANE3Y */
- {DSIPORTC_LANE4X, (IEN | M0)}, /* DSIPORTC_LANE4X */
- {DSIPORTC_LANE4Y, (IEN | M0)}, /* DSIPORTC_LANE4Y */
- {RFBI_HSYNC0, (M4)}, /* KBD_COL5 */
- {RFBI_TE_VSYNC0, (PTD | M6)}, /* GPIO6_161 */
- {RFBI_RE, (M4)}, /* KBD_COL4 */
- {RFBI_A0, (PTD | IEN | M6)}, /* GPIO6_165 */
- {RFBI_DATA8, (M4)}, /* KBD_COL3 */
- {RFBI_DATA9, (PTD | M6)}, /* GPIO6_175 */
- {RFBI_DATA10, (PTD | M6)}, /* GPIO6_176 */
- {RFBI_DATA11, (PTD | M6)}, /* GPIO6_177 */
- {RFBI_DATA12, (PTD | M6)}, /* GPIO6_178 */
- {RFBI_DATA13, (PTU | IEN | M6)}, /* GPIO6_179 */
- {RFBI_DATA14, (M4)}, /* KBD_COL7 */
- {RFBI_DATA15, (M4)}, /* KBD_COL6 */
- {GPIO6_182, (M6)}, /* GPIO6_182 */
- {GPIO6_183, (PTD | M6)}, /* GPIO6_183 */
- {GPIO6_184, (M4)}, /* KBD_COL2 */
- {GPIO6_185, (PTD | IEN | M6)}, /* GPIO6_185 */
- {GPIO6_186, (PTD | M6)}, /* GPIO6_186 */
- {GPIO6_187, (PTU | IEN | M4)}, /* KBD_ROW2 */
- {RFBI_DATA0, (PTD | M6)}, /* GPIO6_166 */
- {RFBI_DATA1, (PTD | M6)}, /* GPIO6_167 */
- {RFBI_DATA2, (PTD | M6)}, /* GPIO6_168 */
- {RFBI_DATA3, (PTD | IEN | M6)}, /* GPIO6_169 */
- {RFBI_DATA4, (IEN | M6)}, /* GPIO6_170 */
- {RFBI_DATA5, (IEN | M6)}, /* GPIO6_171 */
- {RFBI_DATA6, (PTD | M6)}, /* GPIO6_172 */
- {RFBI_DATA7, (PTD | M6)}, /* GPIO6_173 */
- {RFBI_CS0, (PTD | IEN | M6)}, /* GPIO6_163 */
- {RFBI_WE, (PTD | M6)}, /* GPIO6_162 */
- {MCSPI2_CS0, (M0)}, /* MCSPI2_CS0 */
- {MCSPI2_CLK, (IEN | M0)}, /* MCSPI2_CLK */
- {MCSPI2_SIMO, (IEN | M0)}, /* MCSPI2_SIMO*/
- {MCSPI2_SOMI, (PTU | IEN | M0)}, /* MCSPI2_SOMI*/
- {I2C4_SCL, (IEN | M0)}, /* I2C4_SCL */
- {I2C4_SDA, (IEN | M0)}, /* I2C4_SDA */
- {HDMI_CEC, (IEN | M0)}, /* HDMI_CEC */
- {HDMI_HPD, (PTD | IEN | M0)}, /* HDMI_HPD */
- {HDMI_DDC_SCL, (IEN | M0)}, /* HDMI_DDC_SCL */
- {HDMI_DDC_SDA, (IEN | M0)}, /* HDMI_DDC_SDA */
- {CSIPORTA_LANE0X, (IEN | M0)}, /* CSIPORTA_LANE0X */
- {CSIPORTA_LANE0Y, (IEN | M0)}, /* CSIPORTA_LANE0Y */
- {CSIPORTA_LANE1Y, (IEN | M0)}, /* CSIPORTA_LANE1Y */
- {CSIPORTA_LANE1X, (IEN | M0)}, /* CSIPORTA_LANE1X */
- {CSIPORTA_LANE2Y, (IEN | M0)}, /* CSIPORTA_LANE2Y */
- {CSIPORTA_LANE2X, (IEN | M0)}, /* CSIPORTA_LANE2X */
- {CSIPORTA_LANE3X, (IEN | M0)}, /* CSIPORTA_LANE3X */
- {CSIPORTA_LANE3Y, (IEN | M0)}, /* CSIPORTA_LANE3Y */
- {CSIPORTA_LANE4X, (IEN | M0)}, /* CSIPORTA_LANE4X */
- {CSIPORTA_LANE4Y, (IEN | M0)}, /* CSIPORTA_LANE4Y */
- {CSIPORTB_LANE0X, (IEN | M0)}, /* CSIPORTB_LANE0X */
- {CSIPORTB_LANE0Y, (IEN | M0)}, /* CSIPORTB_LANE0Y */
- {CSIPORTB_LANE1Y, (IEN | M0)}, /* CSIPORTB_LANE1Y */
- {CSIPORTB_LANE1X, (IEN | M0)}, /* CSIPORTB_LANE1X */
- {CSIPORTB_LANE2Y, (IEN | M0)}, /* CSIPORTB_LANE2Y */
- {CSIPORTB_LANE2X, (IEN | M0)}, /* CSIPORTB_LANE2X */
- {CSIPORTC_LANE0Y, (IEN | M0)}, /* CSIPORTC_LANE0Y */
- {CSIPORTC_LANE0X, (IEN | M0)}, /* CSIPORTC_LANE0X */
- {CSIPORTC_LANE1Y, (IEN | M0)}, /* CSIPORTC_LANE1Y */
- {CSIPORTC_LANE1X, (IEN | M0)}, /* CSIPORTC_LANE1X */
- {CAM_SHUTTER, (M0)}, /* CAM_SHUTTER */
- {CAM_STROBE, (M0)}, /* CAM_STROBE */
- {CAM_GLOBALRESET, (IEN | M0)}, /* CAM_GLOBALRESET */
- {TIMER11_PWM_EVT, (PTD | M6)}, /* GPIO8_227 */
- {TIMER5_PWM_EVT, (PTD | M6)}, /* GPIO8_228 */
- {TIMER6_PWM_EVT, (PTD | M6)}, /* GPIO8_229 */
- {TIMER8_PWM_EVT, (PTU | M6)}, /* GPIO8_230 */
- {I2C3_SCL, (IEN | M0)}, /* I2C3_SCL */
- {I2C3_SDA, (IEN | M0)}, /* I2C3_SDA */
- {GPIO8_233, (IEN | M2)}, /* TIMER8_PWM_EVT */
- {ABE_CLKS, (IEN | M0)}, /* ABE_CLKS */
- {ABEDMIC_DIN1, (IEN | M0)}, /* ABEDMIC_DIN1 */
- {ABEDMIC_DIN2, (IEN | M0)}, /* ABEDMIC_DIN2 */
- {ABEDMIC_DIN3, (IEN | M0)}, /* ABEDMIC_DIN3 */
- {ABEDMIC_CLK1, (M0)}, /* ABEDMIC_CLK1 */
- {ABEDMIC_CLK2, (IEN | M1)}, /* ABEMCBSP1_FSX */
- {ABEDMIC_CLK3, (M1)}, /* ABEMCBSP1_DX */
- {ABESLIMBUS1_CLOCK, (IEN | M1)}, /* ABEMCBSP1_CLKX */
- {ABESLIMBUS1_DATA, (IEN | M1)}, /* ABEMCBSP1_DR */
- {ABEMCBSP2_DR, (IEN | M0)}, /* ABEMCBSP2_DR */
- {ABEMCBSP2_DX, (M0)}, /* ABEMCBSP2_DX */
- {ABEMCBSP2_FSX, (IEN | M0)}, /* ABEMCBSP2_FSX */
- {ABEMCBSP2_CLKX, (IEN | M0)}, /* ABEMCBSP2_CLKX */
- {ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_UL_DATA */
- {ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_DL_DATA */
- {ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_FRAME */
- {ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_LB_CLK */
- {WLSDIO_CLK, (PTU | IEN | M0)}, /* WLSDIO_CLK */
- {WLSDIO_CMD, (PTU | IEN | M0)}, /* WLSDIO_CMD */
- {WLSDIO_DATA0, (PTU | IEN | M0)}, /* WLSDIO_DATA0*/
- {WLSDIO_DATA1, (PTU | IEN | M0)}, /* WLSDIO_DATA1*/
- {WLSDIO_DATA2, (PTU | IEN | M0)}, /* WLSDIO_DATA2*/
- {WLSDIO_DATA3, (PTU | IEN | M0)}, /* WLSDIO_DATA3*/
- {UART5_RX, (PTU | IEN | M0)}, /* UART5_RX */
- {UART5_TX, (M0)}, /* UART5_TX */
- {UART5_CTS, (PTU | IEN | M0)}, /* UART5_CTS */
- {UART5_RTS, (M0)}, /* UART5_RTS */
- {I2C2_SCL, (IEN | M0)}, /* I2C2_SCL */
- {I2C2_SDA, (IEN | M0)}, /* I2C2_SDA */
- {MCSPI1_CLK, (M6)}, /* GPIO5_140 */
- {MCSPI1_SOMI, (IEN | M6)}, /* GPIO5_141 */
- {MCSPI1_SIMO, (PTD | M6)}, /* GPIO5_142 */
- {MCSPI1_CS0, (PTD | M6)}, /* GPIO5_143 */
- {MCSPI1_CS1, (PTD | IEN | M6)}, /* GPIO5_144 */
- {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */
- {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */
- {PERSLIMBUS2_CLOCK, (PTD | M6)}, /* GPIO5_145 */
- {PERSLIMBUS2_DATA, (PTD | IEN | M6)}, /* GPIO5_146 */
- {UART6_TX, (PTU | IEN | M6)}, /* GPIO5_149 */
- {UART6_RX, (PTU | IEN | M6)}, /* GPIO5_150 */
- {UART6_CTS, (PTU | IEN | M6)}, /* GPIO5_151 */
- {UART6_RTS, (PTU | M0)}, /* UART6_RTS */
- {UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */
- {UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */
- {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */
- {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */
-
-};
-
-const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
-
-/*
- * This pad keeps C2C Module always enabled.
- * Putting this in safe mode do not cause the issue.
- * C2C driver could enable this mux setting if needed.
- */
- {LLIA_WAKEREQIN, (M7)}, /* SAFE MODE */
- {LLIB_WAKEREQIN, (M7)}, /* SAFE MODE */
- {DRM_EMU0, (PTU | IEN | M0)}, /* DRM_EMU0 */
- {DRM_EMU1, (PTU | IEN | M0)}, /* DRM_EMU1 */
- {JTAG_NTRST, (IEN | M0)}, /* JTAG_NTRST */
- {JTAG_TCK, (IEN | M0)}, /* JTAG_TCK */
- {JTAG_RTCK, (M0)}, /* JTAG_RTCK */
- {JTAG_TMSC, (IEN | M0)}, /* JTAG_TMSC */
- {JTAG_TDI, (IEN | M0)}, /* JTAG_TDI */
- {JTAG_TDO, (M0)}, /* JTAG_TDO */
- {FREF_CLK_IOREQ, (IEN | M0)}, /* FREF_CLK_IOREQ */
- {FREF_CLK0_OUT, (M0)}, /* FREF_CLK0_OUT */
- {FREF_CLK1_OUT, (M0)}, /* FREF_CLK1_OUT */
- {FREF_CLK2_OUT, (M0)}, /* FREF_CLK2_OUT */
- {FREF_CLK2_REQ, (PTU | IEN | M6)}, /* GPIO1_WK9 */
- {FREF_CLK1_REQ, (PTD | IEN | M6)}, /* GPIO1_WK8 */
- {SYS_NRESPWRON, (IEN | M0)}, /* SYS_NRESPWRON */
- {SYS_NRESWARM, (PTU | IEN | M0)}, /* SYS_NRESWARM */
- {SYS_PWR_REQ, (M0)}, /* SYS_PWR_REQ */
- {SYS_NIRQ1, (PTU | IEN | M0)}, /* SYS_NIRQ1 */
- {SYS_NIRQ2, (PTU | IEN | M0)}, /* SYS_NIRQ2 */
- {SYS_BOOT0, (IEN | M0)}, /* SYS_BOOT0 */
- {SYS_BOOT1, (IEN | M0)}, /* SYS_BOOT1 */
- {SYS_BOOT2, (IEN | M0)}, /* SYS_BOOT2 */
- {SYS_BOOT3, (IEN | M0)}, /* SYS_BOOT3 */
- {SYS_BOOT4, (IEN | M0)}, /* SYS_BOOT4 */
- {SYS_BOOT5, (IEN | M0)}, /* SYS_BOOT5 */
-
-};
-
-#endif /* _EVM4430_MUX_DATA_H */
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := evm.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl6035.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+
+#include "mux_data.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: OMAP5430 EVM\n"
+};
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+ gpmc_init();
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
+ gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure EVM board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_TWL6035_POWER
+ twl6035_init_settings();
+#endif
+ return 0;
+}
+
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+ sizeof(wkup_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+}
+
+void set_muxconf_regs_non_essential(void)
+{
+ do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+ sizeof(core_padconf_array_non_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+ sizeof(wkup_padconf_array_non_essential) /
+ sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _EVM5430_MUX_DATA_H
+#define _EVM5430_MUX_DATA_H
+
+#include <asm/arch/mux_omap5.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+ {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */
+ {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */
+ {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */
+ {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */
+ {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */
+ {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */
+ {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */
+ {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */
+ {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */
+ {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */
+ {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */
+ {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */
+ {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0*/
+ {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1*/
+ {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2*/
+ {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/
+ {UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */
+ {UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */
+ {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */
+ {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */
+ {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */
+ {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */
+ {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/
+ {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */
+ {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */
+ {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */
+ {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+ {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
+ {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
+ {SYS_32K, (IEN | M0)}, /* SYS_32K */
+
+};
+
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
+
+ {C2C_DATAIN0, (IEN | M0)}, /* C2C_DATAIN0 */
+ {C2C_DATAIN1, (IEN | M0)}, /* C2C_DATAIN1 */
+ {C2C_DATAIN2, (IEN | M0)}, /* C2C_DATAIN2 */
+ {C2C_DATAIN3, (IEN | M0)}, /* C2C_DATAIN3 */
+ {C2C_DATAIN4, (IEN | M0)}, /* C2C_DATAIN4 */
+ {C2C_DATAIN5, (IEN | M0)}, /* C2C_DATAIN5 */
+ {C2C_DATAIN6, (IEN | M0)}, /* C2C_DATAIN6 */
+ {C2C_DATAIN7, (IEN | M0)}, /* C2C_DATAIN7 */
+ {C2C_CLKIN1, (IEN | M0)}, /* C2C_CLKIN1 */
+ {C2C_CLKIN0, (IEN | M0)}, /* C2C_CLKIN0 */
+ {C2C_CLKOUT0, (M0)}, /* C2C_CLKOUT0 */
+ {C2C_CLKOUT1, (M0)}, /* C2C_CLKOUT1 */
+ {C2C_DATAOUT0, (M0)}, /* C2C_DATAOUT0 */
+ {C2C_DATAOUT1, (M0)}, /* C2C_DATAOUT1 */
+ {C2C_DATAOUT2, (M0)}, /* C2C_DATAOUT2 */
+ {C2C_DATAOUT3, (M0)}, /* C2C_DATAOUT3 */
+ {C2C_DATAOUT4, (M0)}, /* C2C_DATAOUT4 */
+ {C2C_DATAOUT5, (M0)}, /* C2C_DATAOUT5 */
+ {C2C_DATAOUT6, (M0)}, /* C2C_DATAOUT6 */
+ {C2C_DATAOUT7, (M0)}, /* C2C_DATAOUT7 */
+ {C2C_DATA8, (IEN | M0)}, /* C2C_DATA8 */
+ {C2C_DATA9, (IEN | M0)}, /* C2C_DATA9 */
+ {C2C_DATA10, (IEN | M0)}, /* C2C_DATA10 */
+ {C2C_DATA11, (IEN | M0)}, /* C2C_DATA11 */
+ {C2C_DATA12, (IEN | M0)}, /* C2C_DATA12 */
+ {C2C_DATA13, (IEN | M0)}, /* C2C_DATA13 */
+ {C2C_DATA14, (IEN | M0)}, /* C2C_DATA14 */
+ {C2C_DATA15, (IEN | M0)}, /* C2C_DATA15 */
+ {LLIB_WAKEREQOUT, (PTU | IEN | M6)}, /* GPIO2_32 */
+ {LLIA_WAKEREQOUT, (M1)}, /* C2C_WAKEREQOUT */
+ {HSI1_ACREADY, (PTD | M6)}, /* GPIO3_64 */
+ {HSI1_CAREADY, (PTD | M6)}, /* GPIO3_65 */
+ {HSI1_ACWAKE, (PTD | IEN | M6)}, /* GPIO3_66 */
+ {HSI1_CAWAKE, (PTU | IEN | M6)}, /* GPIO3_67 */
+ {HSI1_ACFLAG, (PTD | IEN | M6)}, /* GPIO3_68 */
+ {HSI1_ACDATA, (PTD | M6)}, /* GPIO3_69 */
+ {HSI1_CAFLAG, (M6)}, /* GPIO3_70 */
+ {HSI1_CADATA, (M6)}, /* GPIO3_71 */
+ {UART1_TX, (M0)}, /* UART1_TX */
+ {UART1_CTS, (PTU | IEN | M0)}, /* UART1_CTS */
+ {UART1_RX, (PTU | IEN | M0)}, /* UART1_RX */
+ {UART1_RTS, (M0)}, /* UART1_RTS */
+ {HSI2_CAREADY, (IEN | M0)}, /* HSI2_CAREADY */
+ {HSI2_ACREADY, (OFF_EN | M0)}, /* HSI2_ACREADY */
+ {HSI2_CAWAKE, (IEN | PTD | M0)}, /* HSI2_CAWAKE */
+ {HSI2_ACWAKE, (M0)}, /* HSI2_ACWAKE */
+ {HSI2_CAFLAG, (IEN | PTD | M0)}, /* HSI2_CAFLAG */
+ {HSI2_CADATA, (IEN | PTD | M0)}, /* HSI2_CADATA */
+ {HSI2_ACFLAG, (M0)}, /* HSI2_ACFLAG */
+ {HSI2_ACDATA, (M0)}, /* HSI2_ACDATA */
+ {UART2_RTS, (IEN | M1)}, /* MCSPI3_SOMI */
+ {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */
+ {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */
+ {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */
+ {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */
+ {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */
+ {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */
+ {DSIPORTA_LANE0Y, (IEN | M0)}, /* DSIPORTA_LANE0Y */
+ {DSIPORTA_LANE1X, (IEN | M0)}, /* DSIPORTA_LANE1X */
+ {DSIPORTA_LANE1Y, (IEN | M0)}, /* DSIPORTA_LANE1Y */
+ {DSIPORTA_LANE2X, (IEN | M0)}, /* DSIPORTA_LANE2X */
+ {DSIPORTA_LANE2Y, (IEN | M0)}, /* DSIPORTA_LANE2Y */
+ {DSIPORTA_LANE3X, (IEN | M0)}, /* DSIPORTA_LANE3X */
+ {DSIPORTA_LANE3Y, (IEN | M0)}, /* DSIPORTA_LANE3Y */
+ {DSIPORTA_LANE4X, (IEN | M0)}, /* DSIPORTA_LANE4X */
+ {DSIPORTA_LANE4Y, (IEN | M0)}, /* DSIPORTA_LANE4Y */
+ {TIMER9_PWM_EVT, (IEN | M0)}, /* TIMER9_PWM_EVT */
+ {DSIPORTC_TE0, (IEN | M0)}, /* DSIPORTC_TE0 */
+ {DSIPORTC_LANE0X, (IEN | M0)}, /* DSIPORTC_LANE0X */
+ {DSIPORTC_LANE0Y, (IEN | M0)}, /* DSIPORTC_LANE0Y */
+ {DSIPORTC_LANE1X, (IEN | M0)}, /* DSIPORTC_LANE1X */
+ {DSIPORTC_LANE1Y, (IEN | M0)}, /* DSIPORTC_LANE1Y */
+ {DSIPORTC_LANE2X, (IEN | M0)}, /* DSIPORTC_LANE2X */
+ {DSIPORTC_LANE2Y, (IEN | M0)}, /* DSIPORTC_LANE2Y */
+ {DSIPORTC_LANE3X, (IEN | M0)}, /* DSIPORTC_LANE3X */
+ {DSIPORTC_LANE3Y, (IEN | M0)}, /* DSIPORTC_LANE3Y */
+ {DSIPORTC_LANE4X, (IEN | M0)}, /* DSIPORTC_LANE4X */
+ {DSIPORTC_LANE4Y, (IEN | M0)}, /* DSIPORTC_LANE4Y */
+ {RFBI_HSYNC0, (M4)}, /* KBD_COL5 */
+ {RFBI_TE_VSYNC0, (PTD | M6)}, /* GPIO6_161 */
+ {RFBI_RE, (M4)}, /* KBD_COL4 */
+ {RFBI_A0, (PTD | IEN | M6)}, /* GPIO6_165 */
+ {RFBI_DATA8, (M4)}, /* KBD_COL3 */
+ {RFBI_DATA9, (PTD | M6)}, /* GPIO6_175 */
+ {RFBI_DATA10, (PTD | M6)}, /* GPIO6_176 */
+ {RFBI_DATA11, (PTD | M6)}, /* GPIO6_177 */
+ {RFBI_DATA12, (PTD | M6)}, /* GPIO6_178 */
+ {RFBI_DATA13, (PTU | IEN | M6)}, /* GPIO6_179 */
+ {RFBI_DATA14, (M4)}, /* KBD_COL7 */
+ {RFBI_DATA15, (M4)}, /* KBD_COL6 */
+ {GPIO6_182, (M6)}, /* GPIO6_182 */
+ {GPIO6_183, (PTD | M6)}, /* GPIO6_183 */
+ {GPIO6_184, (M4)}, /* KBD_COL2 */
+ {GPIO6_185, (PTD | IEN | M6)}, /* GPIO6_185 */
+ {GPIO6_186, (PTD | M6)}, /* GPIO6_186 */
+ {GPIO6_187, (PTU | IEN | M4)}, /* KBD_ROW2 */
+ {RFBI_DATA0, (PTD | M6)}, /* GPIO6_166 */
+ {RFBI_DATA1, (PTD | M6)}, /* GPIO6_167 */
+ {RFBI_DATA2, (PTD | M6)}, /* GPIO6_168 */
+ {RFBI_DATA3, (PTD | IEN | M6)}, /* GPIO6_169 */
+ {RFBI_DATA4, (IEN | M6)}, /* GPIO6_170 */
+ {RFBI_DATA5, (IEN | M6)}, /* GPIO6_171 */
+ {RFBI_DATA6, (PTD | M6)}, /* GPIO6_172 */
+ {RFBI_DATA7, (PTD | M6)}, /* GPIO6_173 */
+ {RFBI_CS0, (PTD | IEN | M6)}, /* GPIO6_163 */
+ {RFBI_WE, (PTD | M6)}, /* GPIO6_162 */
+ {MCSPI2_CS0, (M0)}, /* MCSPI2_CS0 */
+ {MCSPI2_CLK, (IEN | M0)}, /* MCSPI2_CLK */
+ {MCSPI2_SIMO, (IEN | M0)}, /* MCSPI2_SIMO*/
+ {MCSPI2_SOMI, (PTU | IEN | M0)}, /* MCSPI2_SOMI*/
+ {I2C4_SCL, (IEN | M0)}, /* I2C4_SCL */
+ {I2C4_SDA, (IEN | M0)}, /* I2C4_SDA */
+ {HDMI_CEC, (IEN | M0)}, /* HDMI_CEC */
+ {HDMI_HPD, (PTD | IEN | M0)}, /* HDMI_HPD */
+ {HDMI_DDC_SCL, (IEN | M0)}, /* HDMI_DDC_SCL */
+ {HDMI_DDC_SDA, (IEN | M0)}, /* HDMI_DDC_SDA */
+ {CSIPORTA_LANE0X, (IEN | M0)}, /* CSIPORTA_LANE0X */
+ {CSIPORTA_LANE0Y, (IEN | M0)}, /* CSIPORTA_LANE0Y */
+ {CSIPORTA_LANE1Y, (IEN | M0)}, /* CSIPORTA_LANE1Y */
+ {CSIPORTA_LANE1X, (IEN | M0)}, /* CSIPORTA_LANE1X */
+ {CSIPORTA_LANE2Y, (IEN | M0)}, /* CSIPORTA_LANE2Y */
+ {CSIPORTA_LANE2X, (IEN | M0)}, /* CSIPORTA_LANE2X */
+ {CSIPORTA_LANE3X, (IEN | M0)}, /* CSIPORTA_LANE3X */
+ {CSIPORTA_LANE3Y, (IEN | M0)}, /* CSIPORTA_LANE3Y */
+ {CSIPORTA_LANE4X, (IEN | M0)}, /* CSIPORTA_LANE4X */
+ {CSIPORTA_LANE4Y, (IEN | M0)}, /* CSIPORTA_LANE4Y */
+ {CSIPORTB_LANE0X, (IEN | M0)}, /* CSIPORTB_LANE0X */
+ {CSIPORTB_LANE0Y, (IEN | M0)}, /* CSIPORTB_LANE0Y */
+ {CSIPORTB_LANE1Y, (IEN | M0)}, /* CSIPORTB_LANE1Y */
+ {CSIPORTB_LANE1X, (IEN | M0)}, /* CSIPORTB_LANE1X */
+ {CSIPORTB_LANE2Y, (IEN | M0)}, /* CSIPORTB_LANE2Y */
+ {CSIPORTB_LANE2X, (IEN | M0)}, /* CSIPORTB_LANE2X */
+ {CSIPORTC_LANE0Y, (IEN | M0)}, /* CSIPORTC_LANE0Y */
+ {CSIPORTC_LANE0X, (IEN | M0)}, /* CSIPORTC_LANE0X */
+ {CSIPORTC_LANE1Y, (IEN | M0)}, /* CSIPORTC_LANE1Y */
+ {CSIPORTC_LANE1X, (IEN | M0)}, /* CSIPORTC_LANE1X */
+ {CAM_SHUTTER, (M0)}, /* CAM_SHUTTER */
+ {CAM_STROBE, (M0)}, /* CAM_STROBE */
+ {CAM_GLOBALRESET, (IEN | M0)}, /* CAM_GLOBALRESET */
+ {TIMER11_PWM_EVT, (PTD | M6)}, /* GPIO8_227 */
+ {TIMER5_PWM_EVT, (PTD | M6)}, /* GPIO8_228 */
+ {TIMER6_PWM_EVT, (PTD | M6)}, /* GPIO8_229 */
+ {TIMER8_PWM_EVT, (PTU | M6)}, /* GPIO8_230 */
+ {I2C3_SCL, (IEN | M0)}, /* I2C3_SCL */
+ {I2C3_SDA, (IEN | M0)}, /* I2C3_SDA */
+ {GPIO8_233, (IEN | M2)}, /* TIMER8_PWM_EVT */
+ {ABE_CLKS, (IEN | M0)}, /* ABE_CLKS */
+ {ABEDMIC_DIN1, (IEN | M0)}, /* ABEDMIC_DIN1 */
+ {ABEDMIC_DIN2, (IEN | M0)}, /* ABEDMIC_DIN2 */
+ {ABEDMIC_DIN3, (IEN | M0)}, /* ABEDMIC_DIN3 */
+ {ABEDMIC_CLK1, (M0)}, /* ABEDMIC_CLK1 */
+ {ABEDMIC_CLK2, (IEN | M1)}, /* ABEMCBSP1_FSX */
+ {ABEDMIC_CLK3, (M1)}, /* ABEMCBSP1_DX */
+ {ABESLIMBUS1_CLOCK, (IEN | M1)}, /* ABEMCBSP1_CLKX */
+ {ABESLIMBUS1_DATA, (IEN | M1)}, /* ABEMCBSP1_DR */
+ {ABEMCBSP2_DR, (IEN | M0)}, /* ABEMCBSP2_DR */
+ {ABEMCBSP2_DX, (M0)}, /* ABEMCBSP2_DX */
+ {ABEMCBSP2_FSX, (IEN | M0)}, /* ABEMCBSP2_FSX */
+ {ABEMCBSP2_CLKX, (IEN | M0)}, /* ABEMCBSP2_CLKX */
+ {ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_UL_DATA */
+ {ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_DL_DATA */
+ {ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_FRAME */
+ {ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_LB_CLK */
+ {WLSDIO_CLK, (PTU | IEN | M0)}, /* WLSDIO_CLK */
+ {WLSDIO_CMD, (PTU | IEN | M0)}, /* WLSDIO_CMD */
+ {WLSDIO_DATA0, (PTU | IEN | M0)}, /* WLSDIO_DATA0*/
+ {WLSDIO_DATA1, (PTU | IEN | M0)}, /* WLSDIO_DATA1*/
+ {WLSDIO_DATA2, (PTU | IEN | M0)}, /* WLSDIO_DATA2*/
+ {WLSDIO_DATA3, (PTU | IEN | M0)}, /* WLSDIO_DATA3*/
+ {UART5_RX, (PTU | IEN | M0)}, /* UART5_RX */
+ {UART5_TX, (M0)}, /* UART5_TX */
+ {UART5_CTS, (PTU | IEN | M0)}, /* UART5_CTS */
+ {UART5_RTS, (M0)}, /* UART5_RTS */
+ {I2C2_SCL, (IEN | M0)}, /* I2C2_SCL */
+ {I2C2_SDA, (IEN | M0)}, /* I2C2_SDA */
+ {MCSPI1_CLK, (M6)}, /* GPIO5_140 */
+ {MCSPI1_SOMI, (IEN | M6)}, /* GPIO5_141 */
+ {MCSPI1_SIMO, (PTD | M6)}, /* GPIO5_142 */
+ {MCSPI1_CS0, (PTD | M6)}, /* GPIO5_143 */
+ {MCSPI1_CS1, (PTD | IEN | M6)}, /* GPIO5_144 */
+ {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */
+ {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */
+ {PERSLIMBUS2_CLOCK, (PTD | M6)}, /* GPIO5_145 */
+ {PERSLIMBUS2_DATA, (PTD | IEN | M6)}, /* GPIO5_146 */
+ {UART6_TX, (PTU | IEN | M6)}, /* GPIO5_149 */
+ {UART6_RX, (PTU | IEN | M6)}, /* GPIO5_150 */
+ {UART6_CTS, (PTU | IEN | M6)}, /* GPIO5_151 */
+ {UART6_RTS, (PTU | M0)}, /* UART6_RTS */
+ {UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */
+ {UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */
+ {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */
+ {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
+
+/*
+ * This pad keeps C2C Module always enabled.
+ * Putting this in safe mode do not cause the issue.
+ * C2C driver could enable this mux setting if needed.
+ */
+ {LLIA_WAKEREQIN, (M7)}, /* SAFE MODE */
+ {LLIB_WAKEREQIN, (M7)}, /* SAFE MODE */
+ {DRM_EMU0, (PTU | IEN | M0)}, /* DRM_EMU0 */
+ {DRM_EMU1, (PTU | IEN | M0)}, /* DRM_EMU1 */
+ {JTAG_NTRST, (IEN | M0)}, /* JTAG_NTRST */
+ {JTAG_TCK, (IEN | M0)}, /* JTAG_TCK */
+ {JTAG_RTCK, (M0)}, /* JTAG_RTCK */
+ {JTAG_TMSC, (IEN | M0)}, /* JTAG_TMSC */
+ {JTAG_TDI, (IEN | M0)}, /* JTAG_TDI */
+ {JTAG_TDO, (M0)}, /* JTAG_TDO */
+ {FREF_CLK_IOREQ, (IEN | M0)}, /* FREF_CLK_IOREQ */
+ {FREF_CLK0_OUT, (M0)}, /* FREF_CLK0_OUT */
+ {FREF_CLK1_OUT, (M0)}, /* FREF_CLK1_OUT */
+ {FREF_CLK2_OUT, (M0)}, /* FREF_CLK2_OUT */
+ {FREF_CLK2_REQ, (PTU | IEN | M6)}, /* GPIO1_WK9 */
+ {FREF_CLK1_REQ, (PTD | IEN | M6)}, /* GPIO1_WK8 */
+ {SYS_NRESPWRON, (IEN | M0)}, /* SYS_NRESPWRON */
+ {SYS_NRESWARM, (PTU | IEN | M0)}, /* SYS_NRESWARM */
+ {SYS_PWR_REQ, (M0)}, /* SYS_PWR_REQ */
+ {SYS_NIRQ1, (PTU | IEN | M0)}, /* SYS_NIRQ1 */
+ {SYS_NIRQ2, (PTU | IEN | M0)}, /* SYS_NIRQ2 */
+ {SYS_BOOT0, (IEN | M0)}, /* SYS_BOOT0 */
+ {SYS_BOOT1, (IEN | M0)}, /* SYS_BOOT1 */
+ {SYS_BOOT2, (IEN | M0)}, /* SYS_BOOT2 */
+ {SYS_BOOT3, (IEN | M0)}, /* SYS_BOOT3 */
+ {SYS_BOOT4, (IEN | M0)}, /* SYS_BOOT4 */
+ {SYS_BOOT5, (IEN | M0)}, /* SYS_BOOT5 */
+
+};
+
+#endif /* _EVM4430_MUX_DATA_H */
. = ALIGN(4);
.data : {
- *(.data)
+ *(.data*)
}
. = ALIGN(4);
+ __image_copy_end = .;
+
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
- *(.bss)
+ *(.bss*)
. = ALIGN(4);
__bss_end = .;
}
--- /dev/null
+#
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := wandboard.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+U-Boot for Wandboard
+--------------------
+
+This file contains information for the port of U-Boot to the Wandboard.
+
+Wandboard is a development board that has two variants: one version based
+on mx6 dual lite and another one based on mx6 solo.
+
+For more details about Wandboard, please refer to:
+http://www.wandboard.org/
+
+Building U-boot for Wandboard
+-----------------------------
+
+To build U-Boot for the Wandboard Dual Lite version:
+
+$ make wanboard_dl_config
+$ make
+
+To build U-Boot for the Wandboard Solo version:
+
+$ make wanboard_solo_config
+$ make
+
+Flashing U-boot into the SD card
+--------------------------------
+
+- After the 'make' command completes, the generated 'u-boot.imx' binary must be
+flashed into the SD card;
+
+$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=512 seek=2; sync
+
+(Note - the SD card node may vary, so adjust this as needed).
+
+- Insert the SD card into the slot located in the bottom of the board (same side
+as the mx6 processor)
+
+- Connect the serial cable to the host PC
+
+- Power up the board and U-boot messages will appear in the serial console.
--- /dev/null
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <asm/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
+
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_DDR_MB * SZ_1M;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* AR8031 PHY Reset */
+ MX6_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ /* Reset AR8031 PHY */
+ gpio_direction_output(ETH_PHY_RESET, 0);
+ udelay(500);
+ gpio_set_value(ETH_PHY_RESET, 1);
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+static int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ setup_iomux_enet();
+
+ ret = cpu_eth_init(bis);
+ if (ret)
+ printf("FEC MXC: %s:failed\n", __func__);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Wandboard\n");
+
+ return 0;
+}
imx31_phycore_eet arm arm1136 imx31_phycore - mx31 imx31_phycore:IMX31_PHYCORE_EET
qong arm arm1136 - davedenx mx31
mx31ads arm arm1136 - freescale mx31
-mx31pdk arm arm1136 - freescale mx31 mx31pdk:NAND_U_BOOT
+mx31pdk arm arm1136 - freescale mx31
tt01 arm arm1136 - hale mx31
imx31_litekit arm arm1136 - logicpd mx31
flea3 arm arm1136 - CarMediaLab mx35
km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD
km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI
kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA
+kmsuv31 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_SUV31
mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN
kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN
portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2
apx4devkit arm arm926ejs apx4devkit bluegiga mxs apx4devkit
mx23evk arm arm926ejs mx23evk freescale mxs mx23evk
m28evk arm arm926ejs m28evk denx mxs m28evk
-mx28evk arm arm926ejs mx28evk freescale mxs mx28evk
+mx28evk arm arm926ejs mx28evk freescale mxs mx28evk:ENV_IS_IN_MMC
+mx28evk_nand arm arm926ejs mx28evk freescale mxs mx28evk:ENV_IS_IN_NAND
sc_sps_1 arm arm926ejs sc_sps_1 schulercontrol mxs
nhk8815 arm arm926ejs nhk8815 st nomadik
nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND
nitrogen6q2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048
nitrogen6s arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512
nitrogen6s1g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024
+wandboard_dl arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
+wandboard_solo arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512
cm_t35 arm armv7 cm_t35 - omap3
omap3_overo arm armv7 overo - omap3
omap3_pandora arm armv7 pandora - omap3
nokia_rx51 arm armv7 rx51 nokia omap3
omap4_panda arm armv7 panda ti omap4
omap4_sdp4430 arm armv7 sdp4430 ti omap4
-omap5_evm arm armv7 omap5_evm ti omap5
+omap5_uevm arm armv7 omap5_uevm ti omap5
dra7xx_evm arm armv7 dra7xx ti omap5
s5p_goni arm armv7 goni samsung s5pc1xx
smdkc100 arm armv7 smdkc100 samsung s5pc1xx
#include <common.h>
#include <command.h>
+#include <hw_sha.h>
#include <hash.h>
#include <sha1.h>
#include <sha256.h>
* algorithm names must be in lower case.
*/
static struct hash_algo hash_algo[] = {
+ /*
+ * CONFIG_SHA_HW_ACCEL is defined if hardware acceleration is
+ * available.
+ */
+#ifdef CONFIG_SHA_HW_ACCEL
+ {
+ "sha1",
+ SHA1_SUM_LEN,
+ hw_sha1,
+ CHUNKSZ_SHA1,
+ }, {
+ "sha256",
+ SHA256_SUM_LEN,
+ hw_sha256,
+ CHUNKSZ_SHA256,
+ },
+#endif
/*
* This is CONFIG_CMD_SHA1SUM instead of CONFIG_SHA1 since otherwise
* it bloats the code for boards which use SHA1 but not the 'hash'
#########################################################################
+# Set shell to bash if possible, otherwise fall back to sh
+SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
+ else if [ -x /bin/bash ]; then echo /bin/bash; \
+ else echo sh; fi; fi)
+
+export SHELL
+
ifeq ($(CURDIR),$(SRCTREE))
dir :=
else
-----------------------------------------------------------------------------
-For boards which boot from nand_spl, it is possible to save one copy
+For boards which boot from spl, it is possible to save one copy
if CONFIG_SYS_TEXT_BASE == relocation address! This prevents that uboot code
is copied again in relocate_code().
-example for the tx25 board:
+example for the tx25 board booting from NAND Flash:
a) cpu starts
b) it copies the first page in nand to internal ram
- (nand_spl_code)
+ (spl code)
c) end executes this code
d) this initialize CPU, RAM, ... and copy itself to RAM
(this bin must fit in one page, so board_init_f()
-----------------------------------------------------------------------------
-Relocation with NAND_SPL (example for the tx25):
+Relocation with SPL (example for the tx25 booting from NAND Flash):
- cpu copies the first page from NAND to 0xbb000000 (IMX_NFC_BASE)
and start with code execution on this address.
-- The First page contains u-boot code from u-boot:nand_spl/nand_boot_fsl_nfc.c
- which inits the dram, cpu registers, reloacte itself to CONFIG_SYS_TEXT_BASE and loads
+- The First page contains u-boot code from drivers/mtd/nand/mxc_nand_spl.c
+ which inits the dram, cpu registers, reloacte itself to CONFIG_SPL_TEXT_BASE and loads
the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution
@CONFIG_SYS_NAND_U_BOOT_START
- This u-boot does no RAM init, nor CPU register setup. Just look
where it has to copy and relocate itself to this address. If
relocate address = CONFIG_SYS_TEXT_BASE (not the same, as the
- CONFIG_SYS_TEXT_BASE from the nand_spl code), then there is no need
+ CONFIG_SPL_TEXT_BASE from the spl code), then there is no need
to copy, just go on with bss clear and jump to board_init_r.
-----------------------------------------------------------------------------
* VDD 5V: To the left (off)
* Hold Button: Down (off)
+
+Environment Storage
+-------------------
+
+There are two targets for mx28evk:
+
+"make mx28evk_config" - store enviroment variables into MMC
+
+or
+
+"make mx28evk_nand_config" - store enviroment variables into NAND flash
+
+Choose the target accordingly.
+
+Note: The mx28evk board does not come with a NAND flash populated from the
+factory. It comes with an empty slot (U23), which allows the insertion of a
+48-pin TSOP flash device.
+
Follow the instructions from doc/README.mx28_common to generate a bootable SD
card.
int omap3_dma_get_revision(uint32_t *minor, uint32_t *major)
Read silicon Revision of the DMA module
+NAND
+====
+
+There are some OMAP3 devices out there with NAND attached. Due to the fact that
+OMAP3 ROM code can only handle 1-bit hamming ECC for accessing first page
+(place where SPL lives) we require this setup for u-boot at least when reading
+the second progam within SPL. A lot of newer NAND chips however require more
+than 1-bit ECC for the pages, some can live with 1-bit for the first page. To
+handle this we can switch to another ECC algorithm after reading the payload
+within SPL.
+
+BCH8
+----
+
+To enable hardware assisted BCH8 (8-bit BCH [Bose, Chaudhuri, Hocquenghem]) on
+OMAP3 devices we can use the BCH library in lib/bch.c. To do so add CONFIG_BCH
+to enable the library and CONFIG_NAND_OMAP_BCH8 to to enable hardware assisted
+syndrom generation to your board config.
+The NAND OOB layout is the same as in linux kernel, if the linux kernel BCH8
+implementation for OMAP3 works for you so the u-boot version should also.
+When you require the SPL to read with BCH8 there are two more configs to
+change:
+
+ * CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in
+ GPMC_NAND_HW_BCH8_ECC_LAYOUT defined in
+ arch/arm/include/asm/arch-omap3/omap_gpmc.h)
+ * CONFIG_SYS_NAND_ECCSIZE must be 512
+ * CONFIG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
Acknowledgements
================
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+smdk6400 arm arm1176 - - Zhong Hongbo <bocui107@gmail.com>
ns9750dev arm arm926ejs - - Markus Pietrek <mpietrek@fsforth.de>
AMX860 powerpc mpc860 1b0757e 2012-10-28 Wolfgang Denk <wd@denx.de>
c2mon powerpc mpc855 1b0757e 2012-10-28 Wolfgang Denk <wd@denx.de>
--- /dev/null
+Exynos Display port controller
+==============================
+
+Required properties:
+SOC specific:
+ compatible: should be "samsung,exynos5-dp"
+ reg: Base address of DP IP
+
+Optional properties:
+ samsung,h-res: X resolution of the panel
+ samsung,h-sync-width: hsync value
+ samsung,h-back-porch: left margin
+ samsung,h-front-porch right margin
+ samsung,v-res: Y resolution of the panel
+ samsung,v-sync-width: vsync value
+ samsung,v-back-porch: upper margin
+ samsung,v-front-porch: lower margin
+ samsung,v-sync-rate: refresh rate
+
+ samsung,lt-status: Link training status
+ 0(DP_LT_NONE), 1(DP_LT_START), 2(DP_LT_CR), 3(DP_LT_ET),
+ 4(DP_LT_FINISHED), 5(DP_LT_FAIL)
+
+ samsung,master-mode: 1 if you want to run DP as master, else 0
+ samsung,bist-mode: 1 to enable video bist mode, else 0
+ samsung,bist-pattern: bist mode pattern type
+ 0(NO_PATTERN), 1(COLOR_RAMP), 2(BALCK_WHITE_V_LINES),
+ 3(COLOR_SQUARE), 4(INVALID_PATTERN), 5(COLORBAR_32),
+ 6(COLORBAR_64),7(WHITE_GRAY_BALCKBAR_32),
+ 8(WHITE_GRAY_BALCKBAR_64),9(MOBILE_WHITEBAR_32),
+ 10(MOBILE_WHITEBAR_64)
+ samsung,h-sync-polarity: Horizontal Sync polarity
+ CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ samsung,v-sync-polarity: Vertical Sync polarity
+ CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ samsung,interlaced: Progressive if 0, else Interlaced
+ samsung,color-space: input video data format
+ COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
+ samsung,dynamic-range: dynamic range for input video data
+ VESA = 0, CEA = 1
+ samsung,ycbcr-coeff: YCbCr co-efficients for input video
+ COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
+ samsung,color-depth: number of bits per colour component
+ COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
+
+Example:
+SOC specific part:
+ dp@145b0000 {
+ compatible = "samsung,exynos5-dp";
+ reg = <0x145b0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+Board(panel) specific part:
+ dp@145b0000 {
+ samsung,lt-status = <0>;
+
+ samsung,master-mode = <0>;
+ samsung,bist-mode = <0>;
+ samsung,bist-pattern = <0>;
+ samsung,h-sync-polarity = <0>;
+ samsung,v-sync-polarity = <0>;
+ samsung,interlaced = <0>;
+ samsung,color-space = <0>;
+ samsung,dynamic-range = <0>;
+ samsung,ycbcr-coeff = <0>;
+ samsung,color-depth = <1>;
+ };
--- /dev/null
+Exynos Display Controller
+=========================
+Required properties:
+SOC specific:
+ compatible: should be "samsung,exynos-fimd"
+ reg: Base address of FIMD IP.
+
+Board(panel specific):
+ samsung,vl-col: X resolution of the panel
+ samsung,vl-row: Y resolution of the panel
+ samsung,vl-freq: Refresh rate
+ samsung,vl-bpix: Bits per pixel
+ samsung,vl-hspw: Hsync value
+ samsung,vl-hfpd: Right margin
+ samsung,vl-hbpd: Left margin
+ samsung,vl-vspw: Vsync value
+ samsung,vl-vfpd: Lower margin
+ samsung,vl-vbpd: Upper margin
+
+Optional properties:
+Board(panel specific):
+ samsung,vl-width: width of display area in mm
+ samsung,vl-height: Height of display area in mm
+
+ samsung,vl-clkp: Clock polarity
+ CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ samsung,vl-oep: Output Enable polarity
+ CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ samsung,vl-hsp: Horizontal Sync polarity
+ CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ samsung,vl-vsp: Vertical Sync polarity
+ CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ samsung,vl-dp: Data polarity
+ CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+
+ samsung,vl-cmd-allow-len: Wait end of frame
+ samsung,winid: Window number on which data is to be displayed
+ samsung,init-delay: Delay before LCD initialization starts
+ samsung,power-on-delay: Delay after LCD is powered on
+ samsung,reset-delay: Delay after LCD is reset
+ samsung,interface-mode: 1(FIMD_RGB_INTERFACE), 2(FIMD_CPU_INTERFACE)
+ samsung,mipi-enabled: 1 if you want to use MIPI, else 0
+ samsung,dp-enabled: 1is you want to use DP, else 0
+ samsung,cs-setup: cs_setup value in FIMD_CPU_INTERFACE mode.
+ samsung,wr-setup: wr_setup value in FIMD_CPU_INTERFACE mode.
+ samsung,wr-act: wr_act value in FIMD_CPU_INTERFACE mode.
+ samsung,wr-hold: wr_hold value in FIMD_CPU_INTERFACE mode.
+ samsung,logo-on: 1 if you want to use custom logo.
+ 0 if you want LCD console.
+ samsung,logo-width: pixel width of logo image. Valid if logo_on = 1
+ samsung,logo-height: pixel height of logo image. Valid if logo_on = 1
+ samsung,logo-addr: Address of logo image. Valid if logo_on = 1
+ samsung,rgb-mode: 0(MODE_RGB_P), 1(MODE_BGR_P),
+ 2(MODE_RGB_S), 3(MODE_BGR_S)
+ samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
+ samsung,sclk-div: parent_clock/source_clock ratio
+ samsung,dual-lcd-enabled: 1 if you support two LCD, else 0
+
+Example:
+SOC specific part:
+ fimd@14400000 {
+ compatible = "samsung,exynos-fimd";
+ reg = <0x14400000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+Board specific part:
+ fimd@14400000 {
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <2560>;
+ samsung,vl-row = <1600>;
+ samsung,vl-width = <2560>;
+ samsung,vl-height = <1600>;
+
+ samsung,vl-clkp;
+ samsung,vl-dp;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <32>;
+ samsung,vl-hbpd = <80>;
+ samsung,vl-hfpd = <48>;
+ samsung,vl-vspw = <6>;
+ samsung,vl-vbpd = <37>;
+ samsung,vl-vfpd = <3>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <3>;
+ samsung,interface-mode = <1>;
+ samsung,dp-enabled = <1>;
+ samsung,dual-lcd-enabled = <0>;
+ };
------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 10) s3c64xx.c
+ 10) sandbox.c
-------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 11) sandbox.c
- -------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- 12) serial.c
+ 11) serial.c
------------
This is a complementary part of NS16550 UART driver, see above.
- 13) serial_clps7111.c
+ 12) serial_clps7111.c
---------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 14) serial_imx.c
+ 13) serial_imx.c
----------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible. This driver
might be removed in favor of serial_mxc.c .
- 15) serial_ixp.c
+ 14) serial_ixp.c
----------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 16) serial_ks8695.c
+ 15) serial_ks8695.c
-------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 17) serial_max3100.c
+ 16) serial_max3100.c
--------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 18) serial_mxc.c
+ 17) serial_mxc.c
----------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 19) serial_netarm.c
+ 18) serial_netarm.c
-------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 20) serial_pl01x.c
+ 19) serial_pl01x.c
------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible, though this
driver in fact contains two drivers in total.
- 21) serial_pxa.c
+ 20) serial_pxa.c
----------------
This driver is a bit complicated, but due to clean support for
CONFIG_SERIAL_MULTI, there are no expected obstructions throughout the
conversion process.
- 22) serial_s3c24x0.c
+ 21) serial_s3c24x0.c
--------------------
This driver, being quite ad-hoc might need some work to bring back to shape.
- 23) serial_s3c44b0.c
+ 22) serial_s3c44b0.c
--------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 24) serial_s5p.c
+ 23) serial_s5p.c
----------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 25) serial_sa1100.c
+ 24) serial_sa1100.c
-------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 26) serial_sh.c
+ 25) serial_sh.c
---------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 27) serial_xuartlite.c
+ 26) serial_xuartlite.c
----------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 28) usbtty.c
+ 27) usbtty.c
------------
This driver seems very complicated and entangled with USB framework. The
conversion might be complicated here.
- 29) arch/powerpc/cpu/mpc512x/serial.c
+ 28) arch/powerpc/cpu/mpc512x/serial.c
-------------------------------------
This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to
proper place.
---------------------------
+What: Remove CONFIG_SYS_ENABLE_PADS_ALL and CONFIG_SYS_CLOCKS_ENABLE_ALL
+When: Release v2013.07
+
+Why: When set these options enable "all" of the pads and clocks found
+ on OMAP4/5 platforms, so that the Linux Kernel does not have to.
+ It has been agreed that this goes against the U-Boot design
+ philosophy and since f3f98bb0 we have not enabled more than is
+ used in U-Boot. The kernel has been updating drivers to enable
+ rather than assume pads/clocks have been enabled already. Our
+ expectation is that by v2013.07 a suitable kernel shall exist that
+ does not need these options set for a reasonable I/O set to function.
+
+Who: Tom Rini <trini@ti.com> and Sricharan R <r.sricharan@ti.com>
+
+---------------------------
+
What: Users of the legacy miiphy_* code
When: undetermined
---------------------------
-What: boards with xxx_config targets in top level Makefile
-When: Release v2012.03
-
-Why: We have a boards.cfg file which the vast majority of boards have
- converted over to. Boards that still manually run mkconfig in the
- top level Makefile are either dead, or the maintainer doesn't care,
- or they are doing something weird/wrong that should be fixed in a
- different way, or they need to extend boards.cfg syntax (unlikely).
-
- In any case, if no one cares about these boards to figure out how
- to make boards.cfg work, then we'll just punt them.
-
-Who: Mike Frysinger <vapier@gentoo.org>
-
----------------------------
-
What: GPL cleanup
When: August 2009
Why: Over time, a couple of files have sneaked in into the U-Boot
--- /dev/null
+#
+# Copyright (c) 2013 Samsung Electronics Co., Ltd.
+# http://www.samsung.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)libcrypto.o
+
+COBJS-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+########################################################################
--- /dev/null
+/*
+ * Advanced Crypto Engine - SHA Firmware
+ * Copyright (c) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <sha256.h>
+#include <sha1.h>
+#include <asm/errno.h>
+#include "ace_sha.h"
+
+/* SHA1 value for the message of zero length */
+static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = {
+ 0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D,
+ 0x32, 0x55, 0xBF, 0xFF, 0x95, 0x60, 0x18, 0x90,
+ 0xAF, 0xD8, 0x07, 0x09};
+
+/* SHA256 value for the message of zero length */
+static const unsigned char sha256_digest_emptymsg[SHA256_SUM_LEN] = {
+ 0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14,
+ 0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24,
+ 0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C,
+ 0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55};
+
+int ace_sha_hash_digest(const unsigned char *pbuf, unsigned int buf_len,
+ unsigned char *pout, unsigned int hash_type)
+{
+ unsigned int i, reg, len;
+ unsigned int *pdigest;
+ struct exynos_ace_sfr *ace_sha_reg =
+ (struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
+
+ if (buf_len == 0) {
+ /* ACE H/W cannot compute hash value for empty string */
+ if (hash_type == ACE_SHA_TYPE_SHA1)
+ memcpy(pout, sha1_digest_emptymsg, SHA1_SUM_LEN);
+ else
+ memcpy(pout, sha256_digest_emptymsg, SHA256_SUM_LEN);
+ return 0;
+ }
+
+ /* Flush HRDMA */
+ writel(ACE_FC_HRDMACFLUSH_ON, &ace_sha_reg->fc_hrdmac);
+ writel(ACE_FC_HRDMACFLUSH_OFF, &ace_sha_reg->fc_hrdmac);
+
+ /* Set byte swap of data in */
+ writel(ACE_HASH_SWAPDI_ON | ACE_HASH_SWAPDO_ON | ACE_HASH_SWAPIV_ON,
+ &ace_sha_reg->hash_byteswap);
+
+ /* Select Hash input mux as external source */
+ reg = readl(&ace_sha_reg->fc_fifoctrl);
+ reg = (reg & ~ACE_FC_SELHASH_MASK) | ACE_FC_SELHASH_EXOUT;
+ writel(reg, &ace_sha_reg->fc_fifoctrl);
+
+ /* Set Hash as SHA1 or SHA256 and start Hash engine */
+ reg = (hash_type == ACE_SHA_TYPE_SHA1) ?
+ ACE_HASH_ENGSEL_SHA1HASH : ACE_HASH_ENGSEL_SHA256HASH;
+ reg |= ACE_HASH_STARTBIT_ON;
+ writel(reg, &ace_sha_reg->hash_control);
+
+ /* Enable FIFO mode */
+ writel(ACE_HASH_FIFO_ON, &ace_sha_reg->hash_fifo_mode);
+
+ /* Set message length */
+ writel(buf_len, &ace_sha_reg->hash_msgsize_low);
+ writel(0, &ace_sha_reg->hash_msgsize_high);
+
+ /* Set HRDMA */
+ writel((unsigned int)pbuf, &ace_sha_reg->fc_hrdmas);
+ writel(buf_len, &ace_sha_reg->fc_hrdmal);
+
+ while ((readl(&ace_sha_reg->hash_status) & ACE_HASH_MSGDONE_MASK) ==
+ ACE_HASH_MSGDONE_OFF) {
+ /*
+ * PRNG error bit goes HIGH if a PRNG request occurs without
+ * a complete seed setup. We are using this bit to check h/w
+ * fault because proper setup is not expected in that case.
+ */
+ if ((readl(&ace_sha_reg->hash_status)
+ & ACE_HASH_PRNGERROR_MASK) == ACE_HASH_PRNGERROR_ON)
+ return -EBUSY;
+ }
+
+ /* Clear MSG_DONE bit */
+ writel(ACE_HASH_MSGDONE_ON, &ace_sha_reg->hash_status);
+
+ /* Read hash result */
+ pdigest = (unsigned int *)pout;
+ len = (hash_type == ACE_SHA_TYPE_SHA1) ? SHA1_SUM_LEN : SHA256_SUM_LEN;
+
+ for (i = 0; i < len / 4; i++)
+ pdigest[i] = readl(&ace_sha_reg->hash_result[i]);
+
+ /* Clear HRDMA pending bit */
+ writel(ACE_FC_HRDMA, &ace_sha_reg->fc_intpend);
+
+ return 0;
+}
+
+void hw_sha256(const unsigned char *pbuf, unsigned int buf_len,
+ unsigned char *pout, unsigned int chunk_size)
+{
+ if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA256))
+ debug("ACE was not setup properly or it is faulty\n");
+}
+
+void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
+ unsigned char *pout, unsigned int chunk_size)
+{
+ if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1))
+ debug("ACE was not setup properly or it is faulty\n");
+}
--- /dev/null
+/*
+ * Header file for Advanced Crypto Engine - SFR definitions
+ *
+ * Copyright (c) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ACE_SHA_H
+#define __ACE_SHA_H
+
+struct exynos_ace_sfr {
+ unsigned int fc_intstat; /* base + 0 */
+ unsigned int fc_intenset;
+ unsigned int fc_intenclr;
+ unsigned int fc_intpend;
+ unsigned int fc_fifostat;
+ unsigned int fc_fifoctrl;
+ unsigned int fc_global;
+ unsigned int res1;
+ unsigned int fc_brdmas;
+ unsigned int fc_brdmal;
+ unsigned int fc_brdmac;
+ unsigned int res2;
+ unsigned int fc_btdmas;
+ unsigned int fc_btdmal;
+ unsigned int fc_btdmac;
+ unsigned int res3;
+ unsigned int fc_hrdmas;
+ unsigned int fc_hrdmal;
+ unsigned int fc_hrdmac;
+ unsigned int res4;
+ unsigned int fc_pkdmas;
+ unsigned int fc_pkdmal;
+ unsigned int fc_pkdmac;
+ unsigned int fc_pkdmao;
+ unsigned char res5[0x1a0];
+
+ unsigned int aes_control; /* base + 0x200 */
+ unsigned int aes_status;
+ unsigned char res6[0x8];
+ unsigned int aes_in[4];
+ unsigned int aes_out[4];
+ unsigned int aes_iv[4];
+ unsigned int aes_cnt[4];
+ unsigned char res7[0x30];
+ unsigned int aes_key[8];
+ unsigned char res8[0x60];
+
+ unsigned int tdes_control; /* base + 0x300 */
+ unsigned int tdes_status;
+ unsigned char res9[0x8];
+ unsigned int tdes_key[6];
+ unsigned int tdes_iv[2];
+ unsigned int tdes_in[2];
+ unsigned int tdes_out[2];
+ unsigned char res10[0xc0];
+
+ unsigned int hash_control; /* base + 0x400 */
+ unsigned int hash_control2;
+ unsigned int hash_fifo_mode;
+ unsigned int hash_byteswap;
+ unsigned int hash_status;
+ unsigned char res11[0xc];
+ unsigned int hash_msgsize_low;
+ unsigned int hash_msgsize_high;
+ unsigned int hash_prelen_low;
+ unsigned int hash_prelen_high;
+ unsigned int hash_in[16];
+ unsigned int hash_key_in[16];
+ unsigned int hash_iv[8];
+ unsigned char res12[0x30];
+ unsigned int hash_result[8];
+ unsigned char res13[0x20];
+ unsigned int hash_seed[8];
+ unsigned int hash_prng[8];
+ unsigned char res14[0x180];
+
+ unsigned int pka_sfr[5]; /* base + 0x700 */
+};
+
+/* ACE_FC_INT */
+#define ACE_FC_PKDMA (1 << 0)
+#define ACE_FC_HRDMA (1 << 1)
+#define ACE_FC_BTDMA (1 << 2)
+#define ACE_FC_BRDMA (1 << 3)
+#define ACE_FC_PRNG_ERROR (1 << 4)
+#define ACE_FC_MSG_DONE (1 << 5)
+#define ACE_FC_PRNG_DONE (1 << 6)
+#define ACE_FC_PARTIAL_DONE (1 << 7)
+
+/* ACE_FC_FIFOSTAT */
+#define ACE_FC_PKFIFO_EMPTY (1 << 0)
+#define ACE_FC_PKFIFO_FULL (1 << 1)
+#define ACE_FC_HRFIFO_EMPTY (1 << 2)
+#define ACE_FC_HRFIFO_FULL (1 << 3)
+#define ACE_FC_BTFIFO_EMPTY (1 << 4)
+#define ACE_FC_BTFIFO_FULL (1 << 5)
+#define ACE_FC_BRFIFO_EMPTY (1 << 6)
+#define ACE_FC_BRFIFO_FULL (1 << 7)
+
+/* ACE_FC_FIFOCTRL */
+#define ACE_FC_SELHASH_MASK (3 << 0)
+#define ACE_FC_SELHASH_EXOUT (0 << 0) /* independent source */
+#define ACE_FC_SELHASH_BCIN (1 << 0) /* blk cipher input */
+#define ACE_FC_SELHASH_BCOUT (2 << 0) /* blk cipher output */
+#define ACE_FC_SELBC_MASK (1 << 2)
+#define ACE_FC_SELBC_AES (0 << 2)
+#define ACE_FC_SELBC_DES (1 << 2)
+
+/* ACE_FC_GLOBAL */
+#define ACE_FC_SSS_RESET (1 << 0)
+#define ACE_FC_DMA_RESET (1 << 1)
+#define ACE_FC_AES_RESET (1 << 2)
+#define ACE_FC_DES_RESET (1 << 3)
+#define ACE_FC_HASH_RESET (1 << 4)
+#define ACE_FC_AXI_ENDIAN_MASK (3 << 6)
+#define ACE_FC_AXI_ENDIAN_LE (0 << 6)
+#define ACE_FC_AXI_ENDIAN_BIBE (1 << 6)
+#define ACE_FC_AXI_ENDIAN_WIBE (2 << 6)
+
+/* Feed control - BRDMA control */
+#define ACE_FC_BRDMACFLUSH_OFF (0 << 0)
+#define ACE_FC_BRDMACFLUSH_ON (1 << 0)
+#define ACE_FC_BRDMACSWAP_ON (1 << 1)
+#define ACE_FC_BRDMACARPROT_MASK (0x7 << 2)
+#define ACE_FC_BRDMACARPROT_OFS 2
+#define ACE_FC_BRDMACARCACHE_MASK (0xf << 5)
+#define ACE_FC_BRDMACARCACHE_OFS 5
+
+/* Feed control - BTDMA control */
+#define ACE_FC_BTDMACFLUSH_OFF (0 << 0)
+#define ACE_FC_BTDMACFLUSH_ON (1 << 0)
+#define ACE_FC_BTDMACSWAP_ON (1 << 1)
+#define ACE_FC_BTDMACAWPROT_MASK (0x7 << 2)
+#define ACE_FC_BTDMACAWPROT_OFS 2
+#define ACE_FC_BTDMACAWCACHE_MASK (0xf << 5)
+#define ACE_FC_BTDMACAWCACHE_OFS 5
+
+/* Feed control - HRDMA control */
+#define ACE_FC_HRDMACFLUSH_OFF (0 << 0)
+#define ACE_FC_HRDMACFLUSH_ON (1 << 0)
+#define ACE_FC_HRDMACSWAP_ON (1 << 1)
+#define ACE_FC_HRDMACARPROT_MASK (0x7 << 2)
+#define ACE_FC_HRDMACARPROT_OFS 2
+#define ACE_FC_HRDMACARCACHE_MASK (0xf << 5)
+#define ACE_FC_HRDMACARCACHE_OFS 5
+
+/* Feed control - PKDMA control */
+#define ACE_FC_PKDMACBYTESWAP_ON (1 << 3)
+#define ACE_FC_PKDMACDESEND_ON (1 << 2)
+#define ACE_FC_PKDMACTRANSMIT_ON (1 << 1)
+#define ACE_FC_PKDMACFLUSH_ON (1 << 0)
+
+/* Feed control - PKDMA offset */
+#define ACE_FC_SRAMOFFSET_MASK 0xfff
+
+/* AES control */
+#define ACE_AES_MODE_MASK (1 << 0)
+#define ACE_AES_MODE_ENC (0 << 0)
+#define ACE_AES_MODE_DEC (1 << 0)
+#define ACE_AES_OPERMODE_MASK (3 << 1)
+#define ACE_AES_OPERMODE_ECB (0 << 1)
+#define ACE_AES_OPERMODE_CBC (1 << 1)
+#define ACE_AES_OPERMODE_CTR (2 << 1)
+#define ACE_AES_FIFO_MASK (1 << 3)
+#define ACE_AES_FIFO_OFF (0 << 3) /* CPU mode */
+#define ACE_AES_FIFO_ON (1 << 3) /* FIFO mode */
+#define ACE_AES_KEYSIZE_MASK (3 << 4)
+#define ACE_AES_KEYSIZE_128 (0 << 4)
+#define ACE_AES_KEYSIZE_192 (1 << 4)
+#define ACE_AES_KEYSIZE_256 (2 << 4)
+#define ACE_AES_KEYCNGMODE_MASK (1 << 6)
+#define ACE_AES_KEYCNGMODE_OFF (0 << 6)
+#define ACE_AES_KEYCNGMODE_ON (1 << 6)
+#define ACE_AES_SWAP_MASK (0x1f << 7)
+#define ACE_AES_SWAPKEY_OFF (0 << 7)
+#define ACE_AES_SWAPKEY_ON (1 << 7)
+#define ACE_AES_SWAPCNT_OFF (0 << 8)
+#define ACE_AES_SWAPCNT_ON (1 << 8)
+#define ACE_AES_SWAPIV_OFF (0 << 9)
+#define ACE_AES_SWAPIV_ON (1 << 9)
+#define ACE_AES_SWAPDO_OFF (0 << 10)
+#define ACE_AES_SWAPDO_ON (1 << 10)
+#define ACE_AES_SWAPDI_OFF (0 << 11)
+#define ACE_AES_SWAPDI_ON (1 << 11)
+#define ACE_AES_COUNTERSIZE_MASK (3 << 12)
+#define ACE_AES_COUNTERSIZE_128 (0 << 12)
+#define ACE_AES_COUNTERSIZE_64 (1 << 12)
+#define ACE_AES_COUNTERSIZE_32 (2 << 12)
+#define ACE_AES_COUNTERSIZE_16 (3 << 12)
+
+/* AES status */
+#define ACE_AES_OUTRDY_MASK (1 << 0)
+#define ACE_AES_OUTRDY_OFF (0 << 0)
+#define ACE_AES_OUTRDY_ON (1 << 0)
+#define ACE_AES_INRDY_MASK (1 << 1)
+#define ACE_AES_INRDY_OFF (0 << 1)
+#define ACE_AES_INRDY_ON (1 << 1)
+#define ACE_AES_BUSY_MASK (1 << 2)
+#define ACE_AES_BUSY_OFF (0 << 2)
+#define ACE_AES_BUSY_ON (1 << 2)
+
+/* TDES control */
+#define ACE_TDES_MODE_MASK (1 << 0)
+#define ACE_TDES_MODE_ENC (0 << 0)
+#define ACE_TDES_MODE_DEC (1 << 0)
+#define ACE_TDES_OPERMODE_MASK (1 << 1)
+#define ACE_TDES_OPERMODE_ECB (0 << 1)
+#define ACE_TDES_OPERMODE_CBC (1 << 1)
+#define ACE_TDES_SEL_MASK (3 << 3)
+#define ACE_TDES_SEL_DES (0 << 3)
+#define ACE_TDES_SEL_TDESEDE (1 << 3) /* TDES EDE mode */
+#define ACE_TDES_SEL_TDESEEE (3 << 3) /* TDES EEE mode */
+#define ACE_TDES_FIFO_MASK (1 << 5)
+#define ACE_TDES_FIFO_OFF (0 << 5) /* CPU mode */
+#define ACE_TDES_FIFO_ON (1 << 5) /* FIFO mode */
+#define ACE_TDES_SWAP_MASK (0xf << 6)
+#define ACE_TDES_SWAPKEY_OFF (0 << 6)
+#define ACE_TDES_SWAPKEY_ON (1 << 6)
+#define ACE_TDES_SWAPIV_OFF (0 << 7)
+#define ACE_TDES_SWAPIV_ON (1 << 7)
+#define ACE_TDES_SWAPDO_OFF (0 << 8)
+#define ACE_TDES_SWAPDO_ON (1 << 8)
+#define ACE_TDES_SWAPDI_OFF (0 << 9)
+#define ACE_TDES_SWAPDI_ON (1 << 9)
+
+/* TDES status */
+#define ACE_TDES_OUTRDY_MASK (1 << 0)
+#define ACE_TDES_OUTRDY_OFF (0 << 0)
+#define ACE_TDES_OUTRDY_ON (1 << 0)
+#define ACE_TDES_INRDY_MASK (1 << 1)
+#define ACE_TDES_INRDY_OFF (0 << 1)
+#define ACE_TDES_INRDY_ON (1 << 1)
+#define ACE_TDES_BUSY_MASK (1 << 2)
+#define ACE_TDES_BUSY_OFF (0 << 2)
+#define ACE_TDES_BUSY_ON (1 << 2)
+
+/* Hash control */
+#define ACE_HASH_ENGSEL_MASK (0xf << 0)
+#define ACE_HASH_ENGSEL_SHA1HASH (0x0 << 0)
+#define ACE_HASH_ENGSEL_SHA1HMAC (0x1 << 0)
+#define ACE_HASH_ENGSEL_SHA1HMACIN (0x1 << 0)
+#define ACE_HASH_ENGSEL_SHA1HMACOUT (0x9 << 0)
+#define ACE_HASH_ENGSEL_MD5HASH (0x2 << 0)
+#define ACE_HASH_ENGSEL_MD5HMAC (0x3 << 0)
+#define ACE_HASH_ENGSEL_MD5HMACIN (0x3 << 0)
+#define ACE_HASH_ENGSEL_MD5HMACOUT (0xb << 0)
+#define ACE_HASH_ENGSEL_SHA256HASH (0x4 << 0)
+#define ACE_HASH_ENGSEL_SHA256HMAC (0x5 << 0)
+#define ACE_HASH_ENGSEL_PRNG (0x8 << 0)
+#define ACE_HASH_STARTBIT_ON (1 << 4)
+#define ACE_HASH_USERIV_EN (1 << 5)
+#define ACE_HASH_PAUSE_ON (1 << 0)
+
+/* Hash control - FIFO mode */
+#define ACE_HASH_FIFO_MASK (1 << 0)
+#define ACE_HASH_FIFO_OFF (0 << 0)
+#define ACE_HASH_FIFO_ON (1 << 0)
+
+/* Hash control - byte swap */
+#define ACE_HASH_SWAP_MASK (0xf << 0)
+#define ACE_HASH_SWAPKEY_OFF (0 << 0)
+#define ACE_HASH_SWAPKEY_ON (1 << 0)
+#define ACE_HASH_SWAPIV_OFF (0 << 1)
+#define ACE_HASH_SWAPIV_ON (1 << 1)
+#define ACE_HASH_SWAPDO_OFF (0 << 2)
+#define ACE_HASH_SWAPDO_ON (1 << 2)
+#define ACE_HASH_SWAPDI_OFF (0 << 3)
+#define ACE_HASH_SWAPDI_ON (1 << 3)
+
+/* Hash status */
+#define ACE_HASH_BUFRDY_MASK (1 << 0)
+#define ACE_HASH_BUFRDY_OFF (0 << 0)
+#define ACE_HASH_BUFRDY_ON (1 << 0)
+#define ACE_HASH_SEEDSETTING_MASK (1 << 1)
+#define ACE_HASH_SEEDSETTING_OFF (0 << 1)
+#define ACE_HASH_SEEDSETTING_ON (1 << 1)
+#define ACE_HASH_PRNGBUSY_MASK (1 << 2)
+#define ACE_HASH_PRNGBUSY_OFF (0 << 2)
+#define ACE_HASH_PRNGBUSY_ON (1 << 2)
+#define ACE_HASH_PARTIALDONE_MASK (1 << 4)
+#define ACE_HASH_PARTIALDONE_OFF (0 << 4)
+#define ACE_HASH_PARTIALDONE_ON (1 << 4)
+#define ACE_HASH_PRNGDONE_MASK (1 << 5)
+#define ACE_HASH_PRNGDONE_OFF (0 << 5)
+#define ACE_HASH_PRNGDONE_ON (1 << 5)
+#define ACE_HASH_MSGDONE_MASK (1 << 6)
+#define ACE_HASH_MSGDONE_OFF (0 << 6)
+#define ACE_HASH_MSGDONE_ON (1 << 6)
+#define ACE_HASH_PRNGERROR_MASK (1 << 7)
+#define ACE_HASH_PRNGERROR_OFF (0 << 7)
+#define ACE_HASH_PRNGERROR_ON (1 << 7)
+
+#define ACE_SHA_TYPE_SHA1 1
+#define ACE_SHA_TYPE_SHA256 2
+
+/**
+ * Computes hash value of input pbuf using ACE
+ *
+ * @param in_addr A pointer to the input buffer
+ * @param bufleni Byte length of input buffer
+ * @param out_addr A pointer to the output buffer. When complete
+ * 32 bytes are copied to pout[0]...pout[31]. Thus, a user
+ * should allocate at least 32 bytes at pOut in advance.
+ * @param hash_type SHA1 or SHA256
+ *
+ * @return 0 on Success, -1 on Failure (Timeout)
+ */
+int ace_sha_hash_digest(const uchar * in_addr, uint buflen,
+ uchar * out_addr, uint hash_type);
+#endif
#include <common.h>
#include <malloc.h>
#include <sdhci.h>
+#include <asm/arch/timer.h>
/* 400KHz is max freq for card ID etc. Use that as min */
#define MIN_FREQ 400000
* (Which is just as well - otherwise we'd have to nobble the DMA engine
* too)
*/
- while (get_timer(bcm_host->last_write) < bcm_host->twoticks_delay)
+ while (get_timer_us(bcm_host->last_write) < bcm_host->twoticks_delay)
;
writel(val, host->ioaddr + reg);
- bcm_host->last_write = get_timer(0);
+ bcm_host->last_write = get_timer_us(0);
}
static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg)
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
+ if (cfg->max_bus_width > 0) {
+ if (cfg->max_bus_width < 8)
+ mmc->host_caps &= ~MMC_MODE_8BIT;
+ if (cfg->max_bus_width < 4)
+ mmc->host_caps &= ~MMC_MODE_4BIT;
+ }
+
if (caps & ESDHC_HOSTCAPBLT_HSS)
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
-COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o
COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
else # minimal SPL drivers
COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
+COBJS-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
endif # drivers
endif # nand
int board_nand_init(struct nand_chip *nand)
{
nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
+#if defined(CONFIG_NAND_ECC_BCH)
+ nand->ecc.mode = NAND_ECC_SOFT_BCH;
+#else
nand->ecc.mode = NAND_ECC_SOFT;
+#endif
nand->cmd_ctrl = kw_nand_hwcontrol;
nand->chip_delay = 40;
nand->select_chip = kw_nand_select_chip;
#include <nand.h>
#include <linux/err.h>
#include <asm/io.h>
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
+ defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
#endif
-#include <fsl_nfc.h>
+#include "mxc_nand.h"
#define DRIVER_NAME "mxc_nand"
struct mtd_info mtd;
struct nand_chip *nand;
- struct fsl_nfc_regs __iomem *regs;
+ struct mxc_nand_regs __iomem *regs;
+#ifdef MXC_NFC_V3_2
+ struct mxc_nand_ip_regs __iomem *ip_regs;
+#endif
int spare_only;
int status_request;
int pagesize_2k;
.oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
};
#endif
-#elif defined(MXC_NFC_V2_1)
+#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
#ifndef CONFIG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout nand_hw_eccoob = {
.eccbytes = 9,
#endif
#endif
-#ifdef CONFIG_MX27
static int is_16bit_nand(void)
{
- struct system_control_regs *sc_regs =
- (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
-
- if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
- return 1;
- else
- return 0;
-}
-#elif defined(CONFIG_MX31)
-static int is_16bit_nand(void)
-{
- struct clock_control_regs *sc_regs =
- (struct clock_control_regs *)CCM_BASE;
-
- if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B)
- return 1;
- else
- return 0;
-}
-#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
-static int is_16bit_nand(void)
-{
- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-
- if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL)
- return 1;
- else
- return 0;
-}
+#if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
+ return 1;
#else
-#warning "8/16 bit NAND autodetection not supported"
-static int is_16bit_nand(void)
-{
return 0;
-}
#endif
+}
static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
{
/*
* This function polls the NANDFC to wait for the basic operation to
- * complete by checking the INT bit of config2 register.
+ * complete by checking the INT bit.
*/
static void wait_op_done(struct mxc_nand_host *host, int max_retries,
uint16_t param)
uint32_t tmp;
while (max_retries-- > 0) {
- if (readw(&host->regs->config2) & NFC_INT) {
- tmp = readw(&host->regs->config2);
- tmp &= ~NFC_INT;
- writew(tmp, &host->regs->config2);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+ tmp = readnfc(&host->regs->config2);
+ if (tmp & NFC_V1_V2_CONFIG2_INT) {
+ tmp &= ~NFC_V1_V2_CONFIG2_INT;
+ writenfc(tmp, &host->regs->config2);
+#elif defined(MXC_NFC_V3_2)
+ tmp = readnfc(&host->ip_regs->ipc);
+ if (tmp & NFC_V3_IPC_INT) {
+ tmp &= ~NFC_V3_IPC_INT;
+ writenfc(tmp, &host->ip_regs->ipc);
+#endif
break;
}
udelay(1);
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
- writew(cmd, &host->regs->flash_cmd);
- writew(NFC_CMD, &host->regs->config2);
+ writenfc(cmd, &host->regs->flash_cmd);
+ writenfc(NFC_CMD, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, cmd);
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
- writew(addr, &host->regs->flash_addr);
- writew(NFC_ADDR, &host->regs->config2);
+ writenfc(addr, &host->regs->flash_addr);
+ writenfc(NFC_ADDR, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, addr);
if (spare_only)
MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
- if (is_mxc_nfc_21()) {
+ if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
int i;
/*
* The controller copies the 64 bytes of spare data from
}
}
- writew(buf_id, &host->regs->buf_addr);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+ writenfc(buf_id, &host->regs->buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ uint32_t tmp = readnfc(&host->regs->config1);
+ tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
+ tmp |= NFC_V3_CONFIG1_RBA(buf_id);
+ writenfc(tmp, &host->regs->config1);
+#endif
/* Configure spare or page+spare access */
if (!host->pagesize_2k) {
- uint16_t config1 = readw(&host->regs->config1);
+ uint32_t config1 = readnfc(&host->regs->config1);
if (spare_only)
- config1 |= NFC_SP_EN;
+ config1 |= NFC_CONFIG1_SP_EN;
else
- config1 &= ~NFC_SP_EN;
- writew(config1, &host->regs->config1);
+ config1 &= ~NFC_CONFIG1_SP_EN;
+ writenfc(config1, &host->regs->config1);
}
- writew(NFC_INPUT, &host->regs->config2);
+ writenfc(NFC_INPUT, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, spare_only);
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
- writew(buf_id, &host->regs->buf_addr);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+ writenfc(buf_id, &host->regs->buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ uint32_t tmp = readnfc(&host->regs->config1);
+ tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
+ tmp |= NFC_V3_CONFIG1_RBA(buf_id);
+ writenfc(tmp, &host->regs->config1);
+#endif
/* Configure spare or page+spare access */
if (!host->pagesize_2k) {
- uint32_t config1 = readw(&host->regs->config1);
+ uint32_t config1 = readnfc(&host->regs->config1);
if (spare_only)
- config1 |= NFC_SP_EN;
+ config1 |= NFC_CONFIG1_SP_EN;
else
- config1 &= ~NFC_SP_EN;
- writew(config1, &host->regs->config1);
+ config1 &= ~NFC_CONFIG1_SP_EN;
+ writenfc(config1, &host->regs->config1);
}
- writew(NFC_OUTPUT, &host->regs->config2);
+ writenfc(NFC_OUTPUT, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, spare_only);
- if (is_mxc_nfc_21()) {
+ if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
int i;
/*
/* Request the NANDFC to perform a read of the NAND device ID. */
static void send_read_id(struct mxc_nand_host *host)
{
- uint16_t tmp;
+ uint32_t tmp;
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
/* NANDFC buffer 0 is used for device ID output */
- writew(0x0, &host->regs->buf_addr);
+ writenfc(0x0, &host->regs->buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ tmp = readnfc(&host->regs->config1);
+ tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
+ writenfc(tmp, &host->regs->config1);
+#endif
/* Read ID into main buffer */
- tmp = readw(&host->regs->config1);
- tmp &= ~NFC_SP_EN;
- writew(tmp, &host->regs->config1);
+ tmp = readnfc(&host->regs->config1);
+ tmp &= ~NFC_CONFIG1_SP_EN;
+ writenfc(tmp, &host->regs->config1);
- writew(NFC_ID, &host->regs->config2);
+ writenfc(NFC_ID, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, 0);
*/
static uint16_t get_dev_status(struct mxc_nand_host *host)
{
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
void __iomem *main_buf = host->regs->main_area[1];
uint32_t store;
- uint16_t ret, tmp;
+#endif
+ uint32_t ret, tmp;
/* Issue status request to NAND device */
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
/* store the main area1 first word, later do recovery */
store = readl(main_buf);
/* NANDFC buffer 1 is used for device status */
- writew(1, &host->regs->buf_addr);
+ writenfc(1, &host->regs->buf_addr);
+#endif
/* Read status into main buffer */
- tmp = readw(&host->regs->config1);
- tmp &= ~NFC_SP_EN;
- writew(tmp, &host->regs->config1);
+ tmp = readnfc(&host->regs->config1);
+ tmp &= ~NFC_CONFIG1_SP_EN;
+ writenfc(tmp, &host->regs->config1);
- writew(NFC_STATUS, &host->regs->config2);
+ writenfc(NFC_STATUS, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, 0);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
/*
* Status is placed in first word of main buffer
* get status, then recovery area 1 data
*/
ret = readw(main_buf);
writel(store, main_buf);
+#elif defined(MXC_NFC_V3_2)
+ ret = readnfc(&host->regs->config1) >> 16;
+#endif
return ret;
}
{
struct nand_chip *nand_chip = mtd->priv;
struct mxc_nand_host *host = nand_chip->priv;
- uint16_t tmp = readw(&host->regs->config1);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+ uint16_t tmp = readnfc(&host->regs->config1);
if (on)
- tmp |= NFC_ECC_EN;
+ tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
else
- tmp &= ~NFC_ECC_EN;
- writew(tmp, &host->regs->config1);
+ tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
+ writenfc(tmp, &host->regs->config1);
+#elif defined(MXC_NFC_V3_2)
+ uint32_t tmp = readnfc(&host->ip_regs->config2);
+
+ if (on)
+ tmp |= NFC_V3_CONFIG2_ECC_EN;
+ else
+ tmp &= ~NFC_V3_CONFIG2_ECC_EN;
+ writenfc(tmp, &host->ip_regs->config2);
+#endif
}
#ifdef CONFIG_MXC_NAND_HWECC
*/
}
-#ifdef MXC_NFC_V2_1
+#if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
struct nand_chip *chip,
int page, int sndcmd)
MTDDEBUG(MTD_DEBUG_LEVEL0,
"%s: Reading OOB area of page %u to oob %p\n",
- __FUNCTION__, host->page_addr, buf);
+ __func__, page, buf);
chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
for (i = 0; i < chip->ecc.steps; i++) {
int n;
_mxc_nand_enable_hwecc(mtd, 0);
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr);
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
host->col_addr = n * eccsize;
uint8_t *oob = chip->oob_poi;
MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
- host->page_addr, buf, oob);
+ page, buf, oob);
/* first read the data area and the available portion of OOB */
for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
/* Then switch ECC off and read the OOB area to get the ECC code */
_mxc_nand_enable_hwecc(mtd, 0);
- chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr);
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
eccsteps = chip->ecc.steps;
oob = chip->oob_poi + chip->ecc.prepad;
for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
* additional correction. 2-Bit errors cannot be corrected by
* HW ECC, so we need to return failure
*/
- uint16_t ecc_status = readw(&host->regs->ecc_status_result);
+ uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
MTDDEBUG(MTD_DEBUG_LEVEL0,
int board_nand_init(struct nand_chip *this)
{
struct mtd_info *mtd;
-#ifdef MXC_NFC_V2_1
- uint16_t tmp;
+#if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
+ uint32_t tmp;
#endif
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
this->read_buf = mxc_nand_read_buf;
this->verify_buf = mxc_nand_verify_buf;
- host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
+ host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
+#ifdef MXC_NFC_V3_2
+ host->ip_regs =
+ (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
+#endif
host->clk_act = 1;
#ifdef CONFIG_MXC_NAND_HWECC
this->ecc.calculate = mxc_nand_calculate_ecc;
this->ecc.hwctl = mxc_nand_enable_hwecc;
this->ecc.correct = mxc_nand_correct_data;
- if (is_mxc_nfc_21()) {
+ if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
this->ecc.mode = NAND_ECC_HW_SYNDROME;
this->ecc.read_page = mxc_nand_read_page_syndrome;
this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
this->ecc.layout = &nand_hw_eccoob;
#endif
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
#ifdef MXC_NFC_V2_1
- tmp = readw(&host->regs->config1);
- tmp |= NFC_ONE_CYCLE;
- tmp |= NFC_4_8N_ECC;
- writew(tmp, &host->regs->config1);
+ tmp = readnfc(&host->regs->config1);
+ tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
+ tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
+ writenfc(tmp, &host->regs->config1);
if (host->pagesize_2k)
- writew(64/2, &host->regs->spare_area_size);
+ writenfc(64/2, &host->regs->spare_area_size);
else
- writew(16/2, &host->regs->spare_area_size);
+ writenfc(16/2, &host->regs->spare_area_size);
#endif
/*
* preset operation
* Unlock the internal RAM Buffer
*/
- writew(0x2, &host->regs->config);
+ writenfc(0x2, &host->regs->config);
/* Blocks to be unlocked */
- writew(0x0, &host->regs->unlockstart_blkaddr);
+ writenfc(0x0, &host->regs->unlockstart_blkaddr);
/* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
* unlockend_blkaddr, but the magic 0x4000 does not always work
* when writing more than some 32 megabytes (on 2k page nands)
* This might be NAND chip specific and the i.MX31 datasheet is
* extremely vague about the semantics of this register.
*/
- writew(0xFFFF, &host->regs->unlockend_blkaddr);
+ writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
/* Unlock Block Command for given address range */
- writew(0x4, &host->regs->wrprot);
+ writenfc(0x4, &host->regs->wrprot);
+#elif defined(MXC_NFC_V3_2)
+ writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1);
+ writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc);
+
+ /* Unlock the internal RAM Buffer */
+ writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
+ &host->ip_regs->wrprot);
+
+ /* Blocks to be unlocked */
+ for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++)
+ writenfc(0x0 | 0xFFFF << 16,
+ &host->ip_regs->wrprot_unlock_blkaddr[tmp]);
+
+ writenfc(0, &host->ip_regs->ipc);
+
+ tmp = readnfc(&host->ip_regs->config2);
+ tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK |
+ NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK);
+ tmp |= NFC_V3_CONFIG2_ONE_CYCLE;
+
+ if (host->pagesize_2k) {
+ tmp |= NFC_V3_CONFIG2_SPAS(64/2);
+ tmp |= NFC_V3_CONFIG2_PS_2048;
+ } else {
+ tmp |= NFC_V3_CONFIG2_SPAS(16/2);
+ tmp |= NFC_V3_CONFIG2_PS_512;
+ }
+
+ writenfc(tmp, &host->ip_regs->config2);
+
+ tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
+ NFC_V3_CONFIG3_NO_SDMA |
+ NFC_V3_CONFIG3_RBB_MODE |
+ NFC_V3_CONFIG3_SBB(6) | /* Reset default */
+ NFC_V3_CONFIG3_ADD_OP(0);
+
+ if (!(this->options & NAND_BUSWIDTH_16))
+ tmp |= NFC_V3_CONFIG3_FW8;
+
+ writenfc(tmp, &host->ip_regs->config3);
+
+ writenfc(0, &host->ip_regs->delay_line);
+#endif
return 0;
}
--- /dev/null
+/*
+ * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MXC_NAND_H
+#define __MXC_NAND_H
+
+/*
+ * Register map and bit definitions for the Freescale NAND Flash Controller
+ * present in various i.MX devices.
+ *
+ * MX31 and MX27 have version 1, which has:
+ * 4 512-byte main buffers and
+ * 4 16-byte spare buffers
+ * to support up to 2K byte pagesize nand.
+ * Reading or writing a 2K page requires 4 FDI/FDO cycles.
+ *
+ * MX25 and MX35 have version 2.1, and MX51 and MX53 have version 3.2, which
+ * have:
+ * 8 512-byte main buffers and
+ * 8 64-byte spare buffers
+ * to support up to 4K byte pagesize nand.
+ * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
+ * Also some of registers are moved and/or changed meaning as seen below.
+ */
+#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
+#define MXC_NFC_V1
+#define is_mxc_nfc_1() 1
+#define is_mxc_nfc_21() 0
+#define is_mxc_nfc_32() 0
+#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
+#define MXC_NFC_V2_1
+#define is_mxc_nfc_1() 0
+#define is_mxc_nfc_21() 1
+#define is_mxc_nfc_32() 0
+#elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#define MXC_NFC_V3
+#define MXC_NFC_V3_2
+#define is_mxc_nfc_1() 0
+#define is_mxc_nfc_21() 0
+#define is_mxc_nfc_32() 1
+#else
+#error "MXC NFC implementation not supported"
+#endif
+#define is_mxc_nfc_3() is_mxc_nfc_32()
+
+#if defined(MXC_NFC_V1)
+#define NAND_MXC_NR_BUFS 4
+#define NAND_MXC_SPARE_BUF_SIZE 16
+#define NAND_MXC_REG_OFFSET 0xe00
+#define NAND_MXC_2K_MULTI_CYCLE
+#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
+#define NAND_MXC_NR_BUFS 8
+#define NAND_MXC_SPARE_BUF_SIZE 64
+#define NAND_MXC_REG_OFFSET 0x1e00
+#endif
+
+struct mxc_nand_regs {
+ u8 main_area[NAND_MXC_NR_BUFS][0x200];
+ u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
+ /*
+ * reserved size is offset of nfc registers
+ * minus total main and spare sizes
+ */
+ u8 reserved1[NAND_MXC_REG_OFFSET
+ - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
+#if defined(MXC_NFC_V1)
+ u16 buf_size;
+ u16 reserved2;
+ u16 buf_addr;
+ u16 flash_addr;
+ u16 flash_cmd;
+ u16 config;
+ u16 ecc_status_result;
+ u16 rsltmain_area;
+ u16 rsltspare_area;
+ u16 wrprot;
+ u16 unlockstart_blkaddr;
+ u16 unlockend_blkaddr;
+ u16 nf_wrprst;
+ u16 config1;
+ u16 config2;
+#elif defined(MXC_NFC_V2_1)
+ u16 reserved2[2];
+ u16 buf_addr;
+ u16 flash_addr;
+ u16 flash_cmd;
+ u16 config;
+ u32 ecc_status_result;
+ u16 spare_area_size;
+ u16 wrprot;
+ u16 reserved3[2];
+ u16 nf_wrprst;
+ u16 config1;
+ u16 config2;
+ u16 reserved4;
+ u16 unlockstart_blkaddr;
+ u16 unlockend_blkaddr;
+ u16 unlockstart_blkaddr1;
+ u16 unlockend_blkaddr1;
+ u16 unlockstart_blkaddr2;
+ u16 unlockend_blkaddr2;
+ u16 unlockstart_blkaddr3;
+ u16 unlockend_blkaddr3;
+#elif defined(MXC_NFC_V3_2)
+ u32 flash_cmd;
+ u32 flash_addr[12];
+ u32 config1;
+ u32 ecc_status_result;
+ u32 status_sum;
+ u32 launch;
+#endif
+};
+
+#ifdef MXC_NFC_V3_2
+struct mxc_nand_ip_regs {
+ u32 wrprot;
+ u32 wrprot_unlock_blkaddr[8];
+ u32 config2;
+ u32 config3;
+ u32 ipc;
+ u32 err_addr;
+ u32 delay_line;
+};
+#endif
+
+/* Set FCMD to 1, rest to 0 for Command operation */
+#define NFC_CMD 0x1
+
+/* Set FADD to 1, rest to 0 for Address operation */
+#define NFC_ADDR 0x2
+
+/* Set FDI to 1, rest to 0 for Input operation */
+#define NFC_INPUT 0x4
+
+/* Set FDO to 001, rest to 0 for Data Output operation */
+#define NFC_OUTPUT 0x8
+
+/* Set FDO to 010, rest to 0 for Read ID operation */
+#define NFC_ID 0x10
+
+/* Set FDO to 100, rest to 0 for Read Status operation */
+#define NFC_STATUS 0x20
+
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+#define NFC_CONFIG1_SP_EN (1 << 2)
+#define NFC_CONFIG1_RST (1 << 6)
+#define NFC_CONFIG1_CE (1 << 7)
+#elif defined(MXC_NFC_V3_2)
+#define NFC_CONFIG1_SP_EN (1 << 0)
+#define NFC_CONFIG1_CE (1 << 1)
+#define NFC_CONFIG1_RST (1 << 2)
+#endif
+#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
+#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
+#define NFC_V1_V2_CONFIG1_BIG (1 << 5)
+#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
+#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
+#define NFC_V2_CONFIG1_FP_INT (1 << 11)
+#define NFC_V3_CONFIG1_RBA_MASK (0x7 << 4)
+#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7) << 4)
+
+#define NFC_V1_V2_CONFIG2_INT (1 << 15)
+#define NFC_V3_CONFIG2_PS_MASK (0x3 << 0)
+#define NFC_V3_CONFIG2_PS_512 (0 << 0)
+#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
+#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
+#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
+#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
+#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
+#define NFC_V3_CONFIG2_NUM_ADDR_PH0 (1 << 5)
+#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
+#define NFC_V3_CONFIG2_PPB_MASK (0x3 << 7)
+#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
+#define NFC_V3_CONFIG2_EDC_MASK (0x7 << 9)
+#define NFC_V3_CONFIG2_EDC(x) (((x) & 0x7) << 9)
+#define NFC_V3_CONFIG2_NUM_ADDR_PH1(x) (((x) & 0x3) << 12)
+#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
+#define NFC_V3_CONFIG2_SPAS_MASK (0xff << 16)
+#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
+#define NFC_V3_CONFIG2_ST_CMD_MASK (0xff << 24)
+#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
+
+#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
+#define NFC_V3_CONFIG3_FW8 (1 << 3)
+#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
+#define NFC_V3_CONFIG3_NUM_OF_DEVS(x) (((x) & 0x7) << 12)
+#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
+#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
+
+#define NFC_V3_WRPROT_UNLOCK (1 << 2)
+#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
+
+#define NFC_V3_IPC_CREQ (1 << 0)
+#define NFC_V3_IPC_INT (1 << 31)
+
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+#define operation config2
+#define readnfc readw
+#define writenfc writew
+#elif defined(MXC_NFC_V3_2)
+#define operation launch
+#define readnfc readl
+#define writenfc writel
+#endif
+
+#endif /* __MXC_NAND_H */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * (C) Copyright 2008
+ * Maxim Artamonov, <scn1874 at yandex.ru>
+ *
+ * (C) Copyright 2006-2008
+ * Stefan Roese, DENX Software Engineering, sr at denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include "mxc_nand.h"
+
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR;
+#elif defined(MXC_NFC_V3_2)
+static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR_AXI;
+static struct mxc_nand_ip_regs *const nfc_ip = (void *)NFC_BASE_ADDR;
+#endif
+
+static void nfc_wait_ready(void)
+{
+ uint32_t tmp;
+
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+ while (!(readnfc(&nfc->config2) & NFC_V1_V2_CONFIG2_INT))
+ ;
+
+ /* Reset interrupt flag */
+ tmp = readnfc(&nfc->config2);
+ tmp &= ~NFC_V1_V2_CONFIG2_INT;
+ writenfc(tmp, &nfc->config2);
+#elif defined(MXC_NFC_V3_2)
+ while (!(readnfc(&nfc_ip->ipc) & NFC_V3_IPC_INT))
+ ;
+
+ /* Reset interrupt flag */
+ tmp = readnfc(&nfc_ip->ipc);
+ tmp &= ~NFC_V3_IPC_INT;
+ writenfc(tmp, &nfc_ip->ipc);
+#endif
+}
+
+static void nfc_nand_init(void)
+{
+#if defined(MXC_NFC_V3_2)
+ int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
+ int tmp;
+
+ tmp = (readnfc(&nfc_ip->config2) & ~(NFC_V3_CONFIG2_SPAS_MASK |
+ NFC_V3_CONFIG2_EDC_MASK | NFC_V3_CONFIG2_PS_MASK)) |
+ NFC_V3_CONFIG2_SPAS(CONFIG_SYS_NAND_OOBSIZE / 2) |
+ NFC_V3_CONFIG2_INT_MSK | NFC_V3_CONFIG2_ECC_EN |
+ NFC_V3_CONFIG2_ONE_CYCLE;
+ if (CONFIG_SYS_NAND_PAGE_SIZE == 4096)
+ tmp |= NFC_V3_CONFIG2_PS_4096;
+ else if (CONFIG_SYS_NAND_PAGE_SIZE == 2048)
+ tmp |= NFC_V3_CONFIG2_PS_2048;
+ else if (CONFIG_SYS_NAND_PAGE_SIZE == 512)
+ tmp |= NFC_V3_CONFIG2_PS_512;
+ /*
+ * if spare size is larger that 16 bytes per 512 byte hunk
+ * then use 8 symbol correction instead of 4
+ */
+ if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16)
+ tmp |= NFC_V3_CONFIG2_ECC_MODE_8;
+ else
+ tmp &= ~NFC_V3_CONFIG2_ECC_MODE_8;
+ writenfc(tmp, &nfc_ip->config2);
+
+ tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
+ NFC_V3_CONFIG3_NO_SDMA |
+ NFC_V3_CONFIG3_RBB_MODE |
+ NFC_V3_CONFIG3_SBB(6) | /* Reset default */
+ NFC_V3_CONFIG3_ADD_OP(0);
+#ifndef CONFIG_SYS_NAND_BUSWIDTH_16
+ tmp |= NFC_V3_CONFIG3_FW8;
+#endif
+ writenfc(tmp, &nfc_ip->config3);
+
+ writenfc(0, &nfc_ip->delay_line);
+#elif defined(MXC_NFC_V2_1)
+ int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
+ int config1;
+
+ writenfc(CONFIG_SYS_NAND_OOBSIZE / 2, &nfc->spare_area_size);
+
+ /* unlocking RAM Buff */
+ writenfc(0x2, &nfc->config);
+
+ /* hardware ECC checking and correct */
+ config1 = readnfc(&nfc->config1) | NFC_V1_V2_CONFIG1_ECC_EN |
+ NFC_V1_V2_CONFIG1_INT_MSK | NFC_V2_CONFIG1_ONE_CYCLE |
+ NFC_V2_CONFIG1_FP_INT;
+ /*
+ * if spare size is larger that 16 bytes per 512 byte hunk
+ * then use 8 symbol correction instead of 4
+ */
+ if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16)
+ config1 &= ~NFC_V2_CONFIG1_ECC_MODE_4;
+ else
+ config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
+ writenfc(config1, &nfc->config1);
+#elif defined(MXC_NFC_V1)
+ /* unlocking RAM Buff */
+ writenfc(0x2, &nfc->config);
+
+ /* hardware ECC checking and correct */
+ writenfc(NFC_V1_V2_CONFIG1_ECC_EN | NFC_V1_V2_CONFIG1_INT_MSK,
+ &nfc->config1);
+#endif
+}
+
+static void nfc_nand_command(unsigned short command)
+{
+ writenfc(command, &nfc->flash_cmd);
+ writenfc(NFC_CMD, &nfc->operation);
+ nfc_wait_ready();
+}
+
+static void nfc_nand_address(unsigned short address)
+{
+ writenfc(address, &nfc->flash_addr);
+ writenfc(NFC_ADDR, &nfc->operation);
+ nfc_wait_ready();
+}
+
+static void nfc_nand_page_address(unsigned int page_address)
+{
+ unsigned int page_count;
+
+ nfc_nand_address(0x00);
+
+ /* code only for large page flash */
+ if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
+ nfc_nand_address(0x00);
+
+ page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
+
+ if (page_address <= page_count) {
+ page_count--; /* transform 0x01000000 to 0x00ffffff */
+ do {
+ nfc_nand_address(page_address & 0xff);
+ page_address = page_address >> 8;
+ page_count = page_count >> 8;
+ } while (page_count);
+ }
+
+ nfc_nand_address(0x00);
+}
+
+static void nfc_nand_data_output(void)
+{
+#ifdef NAND_MXC_2K_MULTI_CYCLE
+ int i;
+#endif
+
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+ writenfc(0, &nfc->buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ int config1 = readnfc(&nfc->config1);
+ config1 &= ~NFC_V3_CONFIG1_RBA_MASK;
+ writenfc(config1, &nfc->config1);
+#endif
+ writenfc(NFC_OUTPUT, &nfc->operation);
+ nfc_wait_ready();
+#ifdef NAND_MXC_2K_MULTI_CYCLE
+ /*
+ * This NAND controller requires multiple input commands
+ * for pages larger than 512 bytes.
+ */
+ for (i = 1; i < CONFIG_SYS_NAND_PAGE_SIZE / 512; i++) {
+ writenfc(i, &nfc->buf_addr);
+ writenfc(NFC_OUTPUT, &nfc->operation);
+ nfc_wait_ready();
+ }
+#endif
+}
+
+static int nfc_nand_check_ecc(void)
+{
+#if defined(MXC_NFC_V1)
+ u16 ecc_status = readw(&nfc->ecc_status_result);
+ return (ecc_status & 0x3) == 2 || (ecc_status >> 2) == 2;
+#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
+ u32 ecc_status = readl(&nfc->ecc_status_result);
+ int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
+ int err_limit = CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16 ? 8 : 4;
+ int subpages = CONFIG_SYS_NAND_PAGE_SIZE / 512;
+
+ do {
+ if ((ecc_status & 0xf) > err_limit)
+ return 1;
+ ecc_status >>= 4;
+ } while (--subpages);
+
+ return 0;
+#endif
+}
+
+static void nfc_nand_read_page(unsigned int page_address)
+{
+ /* read in first 0 buffer */
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+ writenfc(0, &nfc->buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ int config1 = readnfc(&nfc->config1);
+ config1 &= ~NFC_V3_CONFIG1_RBA_MASK;
+ writenfc(config1, &nfc->config1);
+#endif
+ nfc_nand_command(NAND_CMD_READ0);
+ nfc_nand_page_address(page_address);
+
+ if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
+ nfc_nand_command(NAND_CMD_READSTART);
+
+ nfc_nand_data_output(); /* fill the main buffer 0 */
+}
+
+static int nfc_read_page(unsigned int page_address, unsigned char *buf)
+{
+ int i;
+ u32 *src;
+ u32 *dst;
+
+ nfc_nand_read_page(page_address);
+
+ if (nfc_nand_check_ecc())
+ return -1;
+
+ src = (u32 *)&nfc->main_area[0][0];
+ dst = (u32 *)buf;
+
+ /* main copy loop from NAND-buffer to SDRAM memory */
+ for (i = 0; i < CONFIG_SYS_NAND_PAGE_SIZE / 4; i++) {
+ writel(readl(src), dst);
+ src++;
+ dst++;
+ }
+
+ return 0;
+}
+
+static int is_badblock(int pagenumber)
+{
+ int page = pagenumber;
+ u32 badblock;
+ u32 *src;
+
+ /* Check the first two pages for bad block markers */
+ for (page = pagenumber; page < pagenumber + 2; page++) {
+ nfc_nand_read_page(page);
+
+ src = (u32 *)&nfc->spare_area[0][0];
+
+ /*
+ * IMPORTANT NOTE: The nand flash controller uses a non-
+ * standard layout for large page devices. This can
+ * affect the position of the bad block marker.
+ */
+ /* Get the bad block marker */
+ badblock = readl(&src[CONFIG_SYS_NAND_BAD_BLOCK_POS / 4]);
+ badblock >>= 8 * (CONFIG_SYS_NAND_BAD_BLOCK_POS % 4);
+ badblock &= 0xff;
+
+ /* bad block marker verify */
+ if (badblock != 0xff)
+ return 1; /* potential bad block */
+ }
+
+ return 0;
+}
+
+static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
+{
+ int i;
+ unsigned int page;
+ unsigned int maxpages = CONFIG_SYS_NAND_SIZE /
+ CONFIG_SYS_NAND_PAGE_SIZE;
+
+ nfc_nand_init();
+
+ /* Convert to page number */
+ page = from / CONFIG_SYS_NAND_PAGE_SIZE;
+ i = 0;
+
+ while (i < size / CONFIG_SYS_NAND_PAGE_SIZE) {
+ if (nfc_read_page(page, buf) < 0)
+ return -1;
+
+ page++;
+ i++;
+ buf = buf + CONFIG_SYS_NAND_PAGE_SIZE;
+
+ /*
+ * Check if we have crossed a block boundary, and if so
+ * check for bad block.
+ */
+ if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
+ /*
+ * Yes, new block. See if this block is good. If not,
+ * loop until we find a good block.
+ */
+ while (is_badblock(page)) {
+ page = page + CONFIG_SYS_NAND_PAGE_COUNT;
+ /* Check i we've reached the end of flash. */
+ if (page >= maxpages)
+ return -1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * The main entry for NAND booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from NAND into SDRAM and starts it from there.
+ */
+void nand_boot(void)
+{
+ __attribute__((noreturn)) void (*uboot)(void);
+
+ /*
+ * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
+ * be aligned to full pages
+ */
+ if (!nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
+ /* Copy from NAND successful, start U-boot */
+ uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ uboot();
+ } else {
+ /* Unrecoverable error when copying from NAND */
+ hang();
+ }
+}
+
+/*
+ * Called in case of an exception.
+ */
+void hang(void)
+{
+ /* Loop forever */
+ while (1) ;
+}
struct nand_chip *chip = mtd->priv;
-#ifdef CONFIG_SYS_NDFC_16BIT
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
return (uint8_t) readw(chip->IO_ADDR_R);
#else
return readb(chip->IO_ADDR_R);
nand->ecc.bytes = 3;
nand->select_chip = ndfc_select_chip;
-#ifdef CONFIG_SYS_NDFC_16BIT
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
nand->options |= NAND_BUSWIDTH_16;
#endif
#include <asm/errno.h>
#include <asm/arch/mem.h>
#include <asm/arch/cpu.h>
-#include <asm/arch/omap_gpmc.h>
+#include <asm/omap_gpmc.h>
#include <linux/mtd/nand_ecc.h>
+#include <linux/bch.h>
#include <linux/compiler.h>
#include <nand.h>
#ifdef CONFIG_AM33XX
static uint8_t cs;
static __maybe_unused struct nand_ecclayout hw_nand_oob =
GPMC_NAND_HW_ECC_LAYOUT;
+static __maybe_unused struct nand_ecclayout hw_bch8_nand_oob =
+ GPMC_NAND_HW_BCH8_ECC_LAYOUT;
/*
* omap_nand_hwcontrol - Set the address pointers corretly for the
}
/*
- * BCH8 support (needs ELM and thus AM33xx-only)
+ * Generic BCH interface
*/
-#ifdef CONFIG_AM33XX
struct nand_bch_priv {
uint8_t mode;
uint8_t type;
uint8_t nibbles;
+ struct bch_control *control;
};
/* bch types */
#define ECC_BCH8 1
#define ECC_BCH16 2
+/* GPMC ecc engine settings */
+#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
+#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
+
/* BCH nibbles for diff bch levels */
#define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1)
#define ECC_BCH4_NIBBLES 13
#define ECC_BCH8_NIBBLES 26
#define ECC_BCH16_NIBBLES 52
-static struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT;
-
-static struct nand_bch_priv bch_priv = {
+/*
+ * This can be a single instance cause all current users have only one NAND
+ * with nearly the same setup (BCH8, some with ELM and others with sw BCH
+ * library).
+ * When some users with other BCH strength will exists this have to change!
+ */
+static __maybe_unused struct nand_bch_priv bch_priv = {
.mode = NAND_ECC_HW_BCH,
.type = ECC_BCH8,
- .nibbles = ECC_BCH8_NIBBLES
+ .nibbles = ECC_BCH8_NIBBLES,
+ .control = NULL
};
+/*
+ * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
+ * GPMC controller
+ * @mtd: MTD device structure
+ * @mode: Read/Write mode
+ */
+__maybe_unused
+static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
+{
+ uint32_t val;
+ uint32_t dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
+#ifdef CONFIG_AM33XX
+ uint32_t unused_length = 0;
+#endif
+ uint32_t wr_mode = BCH_WRAPMODE_6;
+ struct nand_bch_priv *bch = chip->priv;
+
+ /* Clear the ecc result registers, select ecc reg as 1 */
+ writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
+
+#ifdef CONFIG_AM33XX
+ wr_mode = BCH_WRAPMODE_1;
+
+ switch (bch->nibbles) {
+ case ECC_BCH4_NIBBLES:
+ unused_length = 3;
+ break;
+ case ECC_BCH8_NIBBLES:
+ unused_length = 2;
+ break;
+ case ECC_BCH16_NIBBLES:
+ unused_length = 0;
+ break;
+ }
+
+ /*
+ * This is ecc_size_config for ELM mode.
+ * Here we are using different settings for read and write access and
+ * also depending on BCH strength.
+ */
+ switch (mode) {
+ case NAND_ECC_WRITE:
+ /* write access only setup eccsize1 config */
+ val = ((unused_length + bch->nibbles) << 22);
+ break;
+
+ case NAND_ECC_READ:
+ default:
+ /*
+ * by default eccsize0 selected for ecc1resultsize
+ * eccsize0 config.
+ */
+ val = (bch->nibbles << 12);
+ /* eccsize1 config */
+ val |= (unused_length << 22);
+ break;
+ }
+#else
+ /*
+ * This ecc_size_config setting is for BCH sw library.
+ *
+ * Note: we only support BCH8 currently with BCH sw library!
+ * Should be really easy to adobt to BCH4, however some omap3 have
+ * flaws with BCH4.
+ *
+ * Here we are using wrapping mode 6 both for reading and writing, with:
+ * size0 = 0 (no additional protected byte in spare area)
+ * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
+ */
+ val = (32 << 22) | (0 << 12);
+#endif
+ /* ecc size configuration */
+ writel(val, &gpmc_cfg->ecc_size_config);
+
+ /*
+ * Configure the ecc engine in gpmc
+ * We assume 512 Byte sector pages for access to NAND.
+ */
+ val = (1 << 16); /* enable BCH mode */
+ val |= (bch->type << 12); /* setup BCH type */
+ val |= (wr_mode << 8); /* setup wrapping mode */
+ val |= (dev_width << 7); /* setup device width (16 or 8 bit) */
+ val |= (cs << 1); /* setup chip select to work on */
+ debug("set ECC_CONFIG=0x%08x\n", val);
+ writel(val, &gpmc_cfg->ecc_config);
+}
+
+/*
+ * omap_enable_ecc_bch - This function enables the bch h/w ecc functionality
+ * @mtd: MTD device structure
+ * @mode: Read/Write mode
+ */
+__maybe_unused
+static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ omap_hwecc_init_bch(chip, mode);
+ /* enable ecc */
+ writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config);
+}
+
+/*
+ * omap_ecc_disable - Disable H/W ECC calculation
+ *
+ * @mtd: MTD device structure
+ */
+static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd)
+{
+ writel((readl(&gpmc_cfg->ecc_config) & ~0x1), &gpmc_cfg->ecc_config);
+}
+
+/*
+ * BCH8 support (needs ELM and thus AM33xx-only)
+ */
+#ifdef CONFIG_AM33XX
/*
* omap_read_bch8_result - Read BCH result for BCH8 level
*
}
}
-/*
- * omap_ecc_disable - Disable H/W ECC calculation
- *
- * @mtd: MTD device structure
- *
- */
-static void omap_ecc_disable(struct mtd_info *mtd)
-{
- writel((readl(&gpmc_cfg->ecc_config) & ~0x1),
- &gpmc_cfg->ecc_config);
-}
-
/*
* omap_rotate_ecc_bch - Rotate the syndrome bytes
*
return 0;
}
-/*
- * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
- * GPMC controller
- * @mtd: MTD device structure
- * @mode: Read/Write mode
- */
-static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
-{
- uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
- uint32_t unused_length = 0;
- struct nand_bch_priv *bch = chip->priv;
-
- switch (bch->nibbles) {
- case ECC_BCH4_NIBBLES:
- unused_length = 3;
- break;
- case ECC_BCH8_NIBBLES:
- unused_length = 2;
- break;
- case ECC_BCH16_NIBBLES:
- unused_length = 0;
- break;
- }
-
- /* Clear the ecc result registers, select ecc reg as 1 */
- writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
-
- switch (mode) {
- case NAND_ECC_WRITE:
- /* eccsize1 config */
- val = ((unused_length + bch->nibbles) << 22);
- break;
-
- case NAND_ECC_READ:
- default:
- /* by default eccsize0 selected for ecc1resultsize */
- /* eccsize0 config */
- val = (bch->nibbles << 12);
- /* eccsize1 config */
- val |= (unused_length << 22);
- break;
- }
- /* ecc size configuration */
- writel(val, &gpmc_cfg->ecc_size_config);
- /* by default 512bytes sector page is selected */
- /* set bch mode */
- val = (1 << 16);
- /* bch4 / bch8 / bch16 */
- val |= (bch->type << 12);
- /* set wrap mode to 1 */
- val |= (1 << 8);
- val |= (dev_width << 7);
- val |= (cs << 1);
- writel(val, &gpmc_cfg->ecc_config);
-}
-
-/*
- * omap_enable_ecc_bch- This function enables the bch h/w ecc functionality
- * @mtd: MTD device structure
- * @mode: Read/Write mode
- *
- */
-static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
-{
- struct nand_chip *chip = mtd->priv;
-
- omap_hwecc_init_bch(chip, mode);
- /* enable ecc */
- writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config);
-}
/**
* omap_read_page_bch - hardware ecc based page read function
}
#endif /* CONFIG_AM33XX */
-#ifndef CONFIG_SPL_BUILD
/*
- * omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
- * The default is to come up on s/w ecc
+ * OMAP3 BCH8 support (with BCH library)
+ */
+#ifdef CONFIG_NAND_OMAP_BCH8
+/*
+ * omap_calculate_ecc_bch - Read BCH ECC result
*
- * @hardware - 1 -switch to h/w ecc, 0 - s/w ecc
+ * @mtd: MTD device structure
+ * @dat: The pointer to data on which ecc is computed (unused here)
+ * @ecc: The ECC output buffer
+ */
+static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
+ uint8_t *ecc)
+{
+ int ret = 0;
+ size_t i;
+ unsigned long nsectors, val1, val2, val3, val4;
+
+ nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1;
+
+ for (i = 0; i < nsectors; i++) {
+ /* Read hw-computed remainder */
+ val1 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[0]);
+ val2 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[1]);
+ val3 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[2]);
+ val4 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[3]);
+
+ /*
+ * Add constant polynomial to remainder, in order to get an ecc
+ * sequence of 0xFFs for a buffer filled with 0xFFs.
+ */
+ *ecc++ = 0xef ^ (val4 & 0xFF);
+ *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
+ *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
+ *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
+ *ecc++ = 0xed ^ (val3 & 0xFF);
+ *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
+ *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
+ *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
+ *ecc++ = 0x97 ^ (val2 & 0xFF);
+ *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
+ *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
+ *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
+ *ecc++ = 0xb5 ^ (val1 & 0xFF);
+ }
+
+ /*
+ * Stop reading anymore ECC vals and clear old results
+ * enable will be called if more reads are required
+ */
+ omap_ecc_disable(mtd);
+
+ return ret;
+}
+
+/**
+ * omap_correct_data_bch - Decode received data and correct errors
+ * @mtd: MTD device structure
+ * @data: page data
+ * @read_ecc: ecc read from nand flash
+ * @calc_ecc: ecc read from HW ECC registers
+ */
+static int omap_correct_data_bch(struct mtd_info *mtd, u_char *data,
+ u_char *read_ecc, u_char *calc_ecc)
+{
+ int i, count;
+ /* cannot correct more than 8 errors */
+ unsigned int errloc[8];
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *chip_priv = chip->priv;
+ struct bch_control *bch = chip_priv->control;
+
+ count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc);
+ if (count > 0) {
+ /* correct errors */
+ for (i = 0; i < count; i++) {
+ /* correct data only, not ecc bytes */
+ if (errloc[i] < 8*512)
+ data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
+ printf("corrected bitflip %u\n", errloc[i]);
+#ifdef DEBUG
+ puts("read_ecc: ");
+ /*
+ * BCH8 have 13 bytes of ECC; BCH4 needs adoption
+ * here!
+ */
+ for (i = 0; i < 13; i++)
+ printf("%02x ", read_ecc[i]);
+ puts("\n");
+ puts("calc_ecc: ");
+ for (i = 0; i < 13; i++)
+ printf("%02x ", calc_ecc[i]);
+ puts("\n");
+#endif
+ }
+ } else if (count < 0) {
+ puts("ecc unrecoverable error\n");
+ }
+ return count;
+}
+
+/**
+ * omap_free_bch - Release BCH ecc resources
+ * @mtd: MTD device structure
+ */
+static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *chip_priv = chip->priv;
+ struct bch_control *bch = NULL;
+
+ if (chip_priv)
+ bch = chip_priv->control;
+
+ if (bch) {
+ free_bch(bch);
+ chip_priv->control = NULL;
+ }
+}
+#endif /* CONFIG_NAND_OMAP_BCH8 */
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * omap_nand_switch_ecc - switch the ECC operation between different engines
+ * (h/w and s/w) and different algorithms (hamming and BCHx)
*
+ * @hardware - true if one of the HW engines should be used
+ * @eccstrength - the number of bits that could be corrected
+ * (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
*/
-void omap_nand_switch_ecc(int32_t hardware)
+void omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
{
struct nand_chip *nand;
struct mtd_info *mtd;
nand->options |= NAND_OWN_BUFFERS;
/* Reset ecc interface */
+ nand->ecc.mode = NAND_ECC_NONE;
nand->ecc.read_page = NULL;
nand->ecc.write_page = NULL;
nand->ecc.read_oob = NULL;
nand->ecc.calculate = NULL;
/* Setup the ecc configurations again */
- if (hardware == 1) {
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.layout = &hw_nand_oob;
- nand->ecc.size = 512;
- nand->ecc.bytes = 3;
- nand->ecc.hwctl = omap_enable_hwecc;
- nand->ecc.correct = omap_correct_data;
- nand->ecc.calculate = omap_calculate_ecc;
- omap_hwecc_init(nand);
- printf("HW ECC selected\n");
+ if (hardware) {
+ if (eccstrength == 1) {
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.layout = &hw_nand_oob;
+ nand->ecc.size = 512;
+ nand->ecc.bytes = 3;
+ nand->ecc.hwctl = omap_enable_hwecc;
+ nand->ecc.correct = omap_correct_data;
+ nand->ecc.calculate = omap_calculate_ecc;
+ omap_hwecc_init(nand);
+ printf("1-bit hamming HW ECC selected\n");
+ }
+#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
+ else if (eccstrength == 8) {
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.layout = &hw_bch8_nand_oob;
+ nand->ecc.size = 512;
#ifdef CONFIG_AM33XX
- } else if (hardware == 2) {
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.layout = &hw_bch8_nand_oob;
- nand->ecc.size = 512;
- nand->ecc.bytes = 14;
- nand->ecc.read_page = omap_read_page_bch;
- nand->ecc.hwctl = omap_enable_ecc_bch;
- nand->ecc.correct = omap_correct_data_bch;
- nand->ecc.calculate = omap_calculate_ecc_bch;
- omap_hwecc_init_bch(nand, NAND_ECC_READ);
- printf("HW BCH8 selected\n");
+ nand->ecc.bytes = 14;
+ nand->ecc.read_page = omap_read_page_bch;
+#else
+ nand->ecc.bytes = 13;
+#endif
+ nand->ecc.hwctl = omap_enable_ecc_bch;
+ nand->ecc.correct = omap_correct_data_bch;
+ nand->ecc.calculate = omap_calculate_ecc_bch;
+ omap_hwecc_init_bch(nand, NAND_ECC_READ);
+ printf("8-bit BCH HW ECC selected\n");
+ }
#endif
} else {
nand->ecc.mode = NAND_ECC_SOFT;
nand->chip_delay = 100;
+#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
#ifdef CONFIG_AM33XX
+ /* AM33xx uses the ELM */
/* required in case of BCH */
elm_init();
-
+#else
+ /*
+ * Whereas other OMAP based SoC do not have the ELM, they use the BCH
+ * SW library.
+ */
+ bch_priv.control = init_bch(13, 8, 0x201b /* hw polynominal */);
+ if (!bch_priv.control) {
+ puts("Could not init_bch()\n");
+ return -ENODEV;
+ }
+#endif
/* BCH info that will be correct for SPL or overridden otherwise. */
nand->priv = &bch_priv;
#endif
/* Default ECC mode */
-#ifdef CONFIG_AM33XX
+#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.layout = &hw_bch8_nand_oob;
nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
nand->ecc.hwctl = omap_enable_ecc_bch;
nand->ecc.correct = omap_correct_data_bch;
nand->ecc.calculate = omap_calculate_ecc_bch;
+#ifdef CONFIG_AM33XX
nand->ecc.read_page = omap_read_page_bch;
+#endif
omap_hwecc_init_bch(nand, NAND_ECC_READ);
#else
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC)
+++ /dev/null
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * Implementation for U-Boot 1.1.6 by Samsung
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#include <nand.h>
-#include <linux/mtd/nand.h>
-
-#include <asm/arch/s3c6400.h>
-
-#include <asm/io.h>
-#include <asm/errno.h>
-
-#define MAX_CHIPS 2
-static int nand_cs[MAX_CHIPS] = {0, 1};
-
-#ifdef CONFIG_NAND_SPL
-#define printf(arg...) do {} while (0)
-#endif
-
-/* Nand flash definition values by jsgood */
-#ifdef S3C_NAND_DEBUG
-/*
- * Function to print out oob buffer for debugging
- * Written by jsgood
- */
-static void print_oob(const char *header, struct mtd_info *mtd)
-{
- int i;
- struct nand_chip *chip = mtd->priv;
-
- printf("%s:\t", header);
-
- for (i = 0; i < 64; i++)
- printf("%02x ", chip->oob_poi[i]);
-
- printf("\n");
-}
-#endif /* S3C_NAND_DEBUG */
-
-static void s3c_nand_select_chip(struct mtd_info *mtd, int chip)
-{
- int ctrl = readl(NFCONT);
-
- switch (chip) {
- case -1:
- ctrl |= 6;
- break;
- case 0:
- ctrl &= ~2;
- break;
- case 1:
- ctrl &= ~4;
- break;
- default:
- return;
- }
-
- writel(ctrl, NFCONT);
-}
-
-/*
- * Hardware specific access to control-lines function
- * Written by jsgood
- */
-static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if (ctrl & NAND_CLE)
- this->IO_ADDR_W = (void __iomem *)NFCMMD;
- else if (ctrl & NAND_ALE)
- this->IO_ADDR_W = (void __iomem *)NFADDR;
- else
- this->IO_ADDR_W = (void __iomem *)NFDATA;
- if (ctrl & NAND_NCE)
- s3c_nand_select_chip(mtd, *(int *)this->priv);
- else
- s3c_nand_select_chip(mtd, -1);
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-/*
- * Function for checking device ready pin
- * Written by jsgood
- */
-static int s3c_nand_device_ready(struct mtd_info *mtdinfo)
-{
- return !!(readl(NFSTAT) & NFSTAT_RnB);
-}
-
-#ifdef CONFIG_SYS_S3C_NAND_HWECC
-/*
- * This function is called before encoding ecc codes to ready ecc engine.
- * Written by jsgood
- */
-static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode)
-{
- u_long nfcont, nfconf;
-
- /*
- * The original driver used 4-bit ECC for "new" MLC chips, i.e., for
- * those with non-zero ID[3][3:2], which anyway only holds for ST
- * (Numonyx) chips
- */
- nfconf = readl(NFCONF) & ~NFCONF_ECC_4BIT;
-
- writel(nfconf, NFCONF);
-
- /* Initialize & unlock */
- nfcont = readl(NFCONT);
- nfcont |= NFCONT_INITECC;
- nfcont &= ~NFCONT_MECCLOCK;
-
- if (mode == NAND_ECC_WRITE)
- nfcont |= NFCONT_ECC_ENC;
- else if (mode == NAND_ECC_READ)
- nfcont &= ~NFCONT_ECC_ENC;
-
- writel(nfcont, NFCONT);
-}
-
-/*
- * This function is called immediately after encoding ecc codes.
- * This function returns encoded ecc codes.
- * Written by jsgood
- */
-static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
- u_char *ecc_code)
-{
- u_long nfcont, nfmecc0;
-
- /* Lock */
- nfcont = readl(NFCONT);
- nfcont |= NFCONT_MECCLOCK;
- writel(nfcont, NFCONT);
-
- nfmecc0 = readl(NFMECC0);
-
- ecc_code[0] = nfmecc0 & 0xff;
- ecc_code[1] = (nfmecc0 >> 8) & 0xff;
- ecc_code[2] = (nfmecc0 >> 16) & 0xff;
- ecc_code[3] = (nfmecc0 >> 24) & 0xff;
-
- return 0;
-}
-
-/*
- * This function determines whether read data is good or not.
- * If SLC, must write ecc codes to controller before reading status bit.
- * If MLC, status bit is already set, so only reading is needed.
- * If status bit is good, return 0.
- * If correctable errors occured, do that.
- * If uncorrectable errors occured, return -1.
- * Written by jsgood
- */
-static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat,
- u_char *read_ecc, u_char *calc_ecc)
-{
- int ret = -1;
- u_long nfestat0, nfmeccdata0, nfmeccdata1, err_byte_addr;
- u_char err_type, repaired;
-
- /* SLC: Write ecc to compare */
- nfmeccdata0 = (calc_ecc[1] << 16) | calc_ecc[0];
- nfmeccdata1 = (calc_ecc[3] << 16) | calc_ecc[2];
- writel(nfmeccdata0, NFMECCDATA0);
- writel(nfmeccdata1, NFMECCDATA1);
-
- /* Read ecc status */
- nfestat0 = readl(NFESTAT0);
- err_type = nfestat0 & 0x3;
-
- switch (err_type) {
- case 0: /* No error */
- ret = 0;
- break;
-
- case 1:
- /*
- * 1 bit error (Correctable)
- * (nfestat0 >> 7) & 0x7ff :error byte number
- * (nfestat0 >> 4) & 0x7 :error bit number
- */
- err_byte_addr = (nfestat0 >> 7) & 0x7ff;
- repaired = dat[err_byte_addr] ^ (1 << ((nfestat0 >> 4) & 0x7));
-
- printf("S3C NAND: 1 bit error detected at byte %ld. "
- "Correcting from 0x%02x to 0x%02x...OK\n",
- err_byte_addr, dat[err_byte_addr], repaired);
-
- dat[err_byte_addr] = repaired;
-
- ret = 1;
- break;
-
- case 2: /* Multiple error */
- case 3: /* ECC area error */
- printf("S3C NAND: ECC uncorrectable error detected. "
- "Not correctable.\n");
- ret = -1;
- break;
- }
-
- return ret;
-}
-#endif /* CONFIG_SYS_S3C_NAND_HWECC */
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - hwcontrol: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
- * only be provided if a hardware ECC is available
- * - eccmode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- * read regs (tR)
- * - options: various chip options. They can partly be set to inform
- * nand_scan about special functionality. See the defines for further
- * explanation
- * Members with a "?" were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *nand)
-{
- static int chip_n;
-
- if (chip_n >= MAX_CHIPS)
- return -ENODEV;
-
- NFCONT_REG = (NFCONT_REG & ~NFCONT_WP) | NFCONT_ENABLE | 0x6;
-
- nand->IO_ADDR_R = (void __iomem *)NFDATA;
- nand->IO_ADDR_W = (void __iomem *)NFDATA;
- nand->cmd_ctrl = s3c_nand_hwcontrol;
- nand->dev_ready = s3c_nand_device_ready;
- nand->select_chip = s3c_nand_select_chip;
- nand->options = 0;
-#ifdef CONFIG_NAND_SPL
- nand->read_byte = nand_read_byte;
- nand->write_buf = nand_write_buf;
- nand->read_buf = nand_read_buf;
-#endif
-
-#ifdef CONFIG_SYS_S3C_NAND_HWECC
- nand->ecc.hwctl = s3c_nand_enable_hwecc;
- nand->ecc.calculate = s3c_nand_calculate_ecc;
- nand->ecc.correct = s3c_nand_correct_data;
-
- /*
- * If you get more than 1 NAND-chip with different page-sizes on the
- * board one day, it will get more complicated...
- */
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
- nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
-#else
- nand->ecc.mode = NAND_ECC_SOFT;
-#endif /* ! CONFIG_SYS_S3C_NAND_HWECC */
-
- nand->priv = nand_cs + chip_n++;
-
- return 0;
-}
int blockpage, found = 0;
unsigned int i;
-#ifdef CONFIG_S3C64XX
- return 0;
-#endif
-
if (ONENAND_IS_2PLANE(this))
blockpage = onenand_get_2x_blockpage(mtd, addr);
else
/*
- * S3C64XX/S5PC100 OneNAND driver at U-Boot
+ * S5PC100 OneNAND driver at U-Boot
*
* Copyright (C) 2008-2009 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
#define ONENAND_MAIN_SPARE_ACCESS 0x16
#define ONENAND_PIPELINE_READ 0x4000
-#if defined(CONFIG_S3C64XX)
-#define MAP_00 (0x0 << 24)
-#define MAP_01 (0x1 << 24)
-#define MAP_10 (0x2 << 24)
-#define MAP_11 (0x3 << 24)
-#elif defined(CONFIG_S5P)
+#if defined(CONFIG_S5P)
#define MAP_00 (0x0 << 26)
#define MAP_01 (0x1 << 26)
#define MAP_10 (0x2 << 26)
* return the buffer address on the memory device
* It will be combined with CMD_MAP_XX
*/
-#if defined(CONFIG_S3C64XX)
-static unsigned int s3c_mem_addr(int fba, int fpa, int fsa)
-{
- return (fba << 12) | (fpa << 6) | (fsa << 4);
-}
-#elif defined(CONFIG_S5P)
+#if defined(CONFIG_S5P)
static unsigned int s3c_mem_addr(int fba, int fpa, int fsa)
{
return (fba << 13) | (fpa << 7) | (fsa << 5);
s3c_onenand_check_lock_status(mtd);
}
-#ifdef CONFIG_S3C64XX
-static void s3c_set_width_regs(struct onenand_chip *this)
-{
- int dev_id, density;
- int fba, fpa, fsa;
- int dbs_dfs;
-
- dev_id = DEVICE_ID0_REG;
-
- density = (dev_id >> ONENAND_DEVICE_DENSITY_SHIFT) & 0xf;
- dbs_dfs = !!(dev_id & ONENAND_DEVICE_IS_DDP);
-
- fba = density + 7;
- if (dbs_dfs)
- fba--; /* Decrease the fba */
- fpa = 6;
- if (density >= ONENAND_DEVICE_DENSITY_512Mb)
- fsa = 2;
- else
- fsa = 1;
-
- DPRINTK("FBA %lu, FPA %lu, FSA %lu, DDP %lu",
- FBA_WIDTH0_REG, FPA_WIDTH0_REG, FSA_WIDTH0_REG,
- DDP_DEVICE_REG);
-
- DPRINTK("mem_cfg0 0x%lx, sync mode %lu, "
- "dev_page_size %lu, BURST LEN %lu",
- MEM_CFG0_REG, SYNC_MODE_REG,
- DEV_PAGE_SIZE_REG, BURST_LEN0_REG);
-
- DEV_PAGE_SIZE_REG = 0x1;
-
- FBA_WIDTH0_REG = fba;
- FPA_WIDTH0_REG = fpa;
- FSA_WIDTH0_REG = fsa;
- DBS_DFS_WIDTH0_REG = dbs_dfs;
-}
-#endif
-
int s5pc110_chip_probe(struct mtd_info *mtd)
{
return 0;
onenand->mtd = mtd;
-#if defined(CONFIG_S3C64XX)
- onenand->base = (void *)0x70100000;
- onenand->ahb_addr = (void *)0x20000000;
-#elif defined(CONFIG_S5P)
+#if defined(CONFIG_S5P)
onenand->base = (void *)0xE7100000;
onenand->ahb_addr = (void *)0xB0000000;
#endif
COBJS-$(CONFIG_MCFUART) += mcfuart.o
COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
COBJS-$(CONFIG_SYS_NS16550) += ns16550.o
-COBJS-$(CONFIG_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_S5P) += serial_s5p.o
COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o
void NS16550_init(NS16550_t com_port, int baud_divisor)
{
-#if (!defined(CONFIG_SYS_NS16550_BROKEN_TEMT))
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX))
+ /*
+ * On some OMAP3 devices when UART3 is configured for boot mode before
+ * SPL starts only THRE bit is set. We have to empty the transmitter
+ * before initialization starts.
+ */
+ if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
+ == UART_LSR_THRE) {
+ serial_out(UART_LCR_DLAB, &com_port->lcr);
+ serial_out(baud_divisor & 0xff, &com_port->dll);
+ serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
+ serial_out(UART_LCRVAL, &com_port->lcr);
+ serial_out(0, &com_port->mdr1);
+ }
+#endif
+
while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
;
-#endif
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <linux/compiler.h>
-#include <serial.h>
-#include <asm/arch/s3c6400.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SERIAL1
-#define UART_NR S3C64XX_UART0
-
-#elif defined(CONFIG_SERIAL2)
-#define UART_NR S3C64XX_UART1
-
-#elif defined(CONFIG_SERIAL3)
-#define UART_NR S3C64XX_UART2
-
-#else
-#error "Bad: you didn't configure serial ..."
-#endif
-
-/*
- * The coefficient, used to calculate the baudrate on S3C6400 UARTs is
- * calculated as
- * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
- * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
- * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
- */
-static const int udivslot[] = {
- 0,
- 0x0080,
- 0x0808,
- 0x0888,
- 0x2222,
- 0x4924,
- 0x4a52,
- 0x54aa,
- 0x5555,
- 0xd555,
- 0xd5d5,
- 0xddd5,
- 0xdddd,
- 0xdfdd,
- 0xdfdf,
- 0xffdf,
-};
-
-static void s3c64xx_serial_setbrg(void)
-{
- s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
- u32 pclk = get_PCLK();
- u32 baudrate = gd->baudrate;
- int i;
-
- i = (pclk / baudrate) % 16;
-
- uart->UBRDIV = pclk / baudrate / 16 - 1;
- uart->UDIVSLOT = udivslot[i];
-
- for (i = 0; i < 100; i++)
- barrier();
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- */
-static int s3c64xx_serial_init(void)
-{
- s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
-
- /* reset and enable FIFOs, set triggers to the maximum */
- uart->UFCON = 0xff;
- uart->UMCON = 0;
- /* 8N1 */
- uart->ULCON = 3;
- /* No interrupts, no DMA, pure polling */
- uart->UCON = 5;
-
- serial_setbrg();
-
- return 0;
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int s3c64xx_serial_getc(void)
-{
- s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
-
- /* wait for character to arrive */
- while (!(uart->UTRSTAT & 0x1));
-
- return uart->URXH & 0xff;
-}
-
-#ifdef CONFIG_MODEM_SUPPORT
-static int be_quiet;
-void disable_putc(void)
-{
- be_quiet = 1;
-}
-
-void enable_putc(void)
-{
- be_quiet = 0;
-}
-#endif
-
-
-/*
- * Output a single byte to the serial port.
- */
-static void s3c64xx_serial_putc(const char c)
-{
- s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
-
-#ifdef CONFIG_MODEM_SUPPORT
- if (be_quiet)
- return;
-#endif
-
- /* wait for room in the tx FIFO */
- while (!(uart->UTRSTAT & 0x2));
-
- uart->UTXH = c;
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-static int s3c64xx_serial_tstc(void)
-{
- s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
-
- return uart->UTRSTAT & 0x1;
-}
-
-static struct serial_device s3c64xx_serial_drv = {
- .name = "s3c64xx_serial",
- .start = s3c64xx_serial_init,
- .stop = NULL,
- .setbrg = s3c64xx_serial_setbrg,
- .putc = s3c64xx_serial_putc,
- .puts = default_serial_puts,
- .getc = s3c64xx_serial_getc,
- .tstc = s3c64xx_serial_tstc,
-};
-
-void s3c64xx_serial_initialize(void)
-{
- serial_register(&s3c64xx_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &s3c64xx_serial_drv;
-}
serial_initfunc(lpc32xx_serial_initialize);
serial_initfunc(mcf_serial_initialize);
serial_initfunc(oc_serial_initialize);
-serial_initfunc(s3c64xx_serial_initialize);
serial_initfunc(sandbox_serial_initialize);
serial_initfunc(clps7111_serial_initialize);
serial_initfunc(imx_serial_initialize);
lpc32xx_serial_initialize();
mcf_serial_initialize();
oc_serial_initialize();
- s3c64xx_serial_initialize();
sandbox_serial_initialize();
clps7111_serial_initialize();
imx_serial_initialize();
* @param bus SPI bus structure to fill with information
* @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing
*/
+#ifdef CONFIG_OF_CONTROL
static int spi_get_config(const void *blob, int node, struct spi_bus *bus)
{
bus->node = node;
return 0;
}
+#endif
/* Sadly there is no error return from this function */
void spi_init(void)
return -1;
}
- reg_ctrl = reg_read(®s->ctrl);
-
/* Reset spi */
- reg_write(®s->ctrl, (reg_ctrl & ~MXC_CSPICTRL_EN));
- reg_write(®s->ctrl, (reg_ctrl | MXC_CSPICTRL_EN));
+ reg_write(®s->ctrl, 0);
+ reg_write(®s->ctrl, MXC_CSPICTRL_EN);
+
+ reg_ctrl = reg_read(®s->ctrl);
/*
* The following computation is taken directly from Freescale's code.
COBJS-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o
COBJS-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
-COBJS-$(CONFIG_USB_S3C64XX) += s3c64xx-hcd.o
COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o
COBJS-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o
#if defined(CONFIG_ARM920T) || \
defined(CONFIG_S3C24X0) || \
- defined(CONFIG_S3C6400) || \
defined(CONFIG_440EP) || \
defined(CONFIG_PCI_OHCI) || \
defined(CONFIG_MPC5200) || \
+++ /dev/null
-/*
- * URB OHCI HCD (Host Controller Driver) initialization for USB on the S3C64XX.
- *
- * Copyright (C) 2008,
- * Guennadi Liakhovetski, DENX Software Engineering <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <asm/arch/s3c6400.h>
-
-int usb_cpu_init(void)
-{
- OTHERS_REG |= 0x10000;
- return 0;
-}
-
-int usb_cpu_stop(void)
-{
- OTHERS_REG &= ~0x10000;
- return 0;
-}
-
-void usb_cpu_init_fail(void)
-{
- OTHERS_REG &= ~0x10000;
-}
/* put into basic highspeed mode and start session */
musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
+#ifdef CONFIG_USB_GADGET_DUALSPEED
| MUSB_POWER_HSENAB
+#endif
/* ENSUSPEND wedges tusb */
/* | MUSB_POWER_ENSUSPEND */
);
strcat(aInfo, ", dyn FIFOs");
musb->dyn_fifo = true;
}
+#ifndef CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
if (reg & MUSB_CONFIGDATA_MPRXE) {
strcat(aInfo, ", bulk combine");
musb->bulk_combine = true;
strcat(aInfo, ", bulk split");
musb->bulk_split = true;
}
+#else
+ musb->bulk_combine = false;
+ musb->bulk_split = false;
+#endif
if (reg & MUSB_CONFIGDATA_HBRXE) {
strcat(aInfo, ", HB-ISO Rx");
musb->hb_iso_rx = true;
{
int ret;
- if (!driver || driver->speed < USB_SPEED_HIGH || !driver->bind ||
+ if (!driver || driver->speed < USB_SPEED_FULL || !driver->bind ||
!driver->setup) {
printf("bad parameter.\n");
return -EINVAL;
#include <asm/arch/cpu.h>
#include <asm/arch/dp_info.h>
#include <asm/arch/dp.h>
+#include <fdtdec.h>
+#include <libfdt.h>
#include "exynos_dp_lowlevel.h"
+DECLARE_GLOBAL_DATA_PTR;
+
static struct exynos_dp_platform_data *dp_pd;
+void __exynos_set_dp_phy(unsigned int onoff)
+{
+}
+void exynos_set_dp_phy(unsigned int onoff)
+ __attribute__((weak, alias("__exynos_set_dp_phy")));
+
static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
{
disp_info->h_total = disp_info->h_res + disp_info->h_sync_width +
return ret;
}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info)
+{
+ unsigned int node = fdtdec_next_compatible(blob, 0,
+ COMPAT_SAMSUNG_EXYNOS5_DP);
+ if (node <= 0) {
+ debug("exynos_dp: Can't get device node for dp\n");
+ return -ENODEV;
+ }
+
+ edp_info->disp_info.h_res = fdtdec_get_int(blob, node,
+ "samsung,h-res", 0);
+ edp_info->disp_info.h_sync_width = fdtdec_get_int(blob, node,
+ "samsung,h-sync-width", 0);
+ edp_info->disp_info.h_back_porch = fdtdec_get_int(blob, node,
+ "samsung,h-back-porch", 0);
+ edp_info->disp_info.h_front_porch = fdtdec_get_int(blob, node,
+ "samsung,h-front-porch", 0);
+ edp_info->disp_info.v_res = fdtdec_get_int(blob, node,
+ "samsung,v-res", 0);
+ edp_info->disp_info.v_sync_width = fdtdec_get_int(blob, node,
+ "samsung,v-sync-width", 0);
+ edp_info->disp_info.v_back_porch = fdtdec_get_int(blob, node,
+ "samsung,v-back-porch", 0);
+ edp_info->disp_info.v_front_porch = fdtdec_get_int(blob, node,
+ "samsung,v-front-porch", 0);
+ edp_info->disp_info.v_sync_rate = fdtdec_get_int(blob, node,
+ "samsung,v-sync-rate", 0);
+
+ edp_info->lt_info.lt_status = fdtdec_get_int(blob, node,
+ "samsung,lt-status", 0);
+
+ edp_info->video_info.master_mode = fdtdec_get_int(blob, node,
+ "samsung,master-mode", 0);
+ edp_info->video_info.bist_mode = fdtdec_get_int(blob, node,
+ "samsung,bist-mode", 0);
+ edp_info->video_info.bist_pattern = fdtdec_get_int(blob, node,
+ "samsung,bist-pattern", 0);
+ edp_info->video_info.h_sync_polarity = fdtdec_get_int(blob, node,
+ "samsung,h-sync-polarity", 0);
+ edp_info->video_info.v_sync_polarity = fdtdec_get_int(blob, node,
+ "samsung,v-sync-polarity", 0);
+ edp_info->video_info.interlaced = fdtdec_get_int(blob, node,
+ "samsung,interlaced", 0);
+ edp_info->video_info.color_space = fdtdec_get_int(blob, node,
+ "samsung,color-space", 0);
+ edp_info->video_info.dynamic_range = fdtdec_get_int(blob, node,
+ "samsung,dynamic-range", 0);
+ edp_info->video_info.ycbcr_coeff = fdtdec_get_int(blob, node,
+ "samsung,ycbcr-coeff", 0);
+ edp_info->video_info.color_depth = fdtdec_get_int(blob, node,
+ "samsung,color-depth", 0);
+ return 0;
+}
+#endif
+
unsigned int exynos_init_dp(void)
{
unsigned int ret;
return -EFAULT;
}
+#ifdef CONFIG_OF_CONTROL
+ if (exynos_dp_parse_dt(gd->fdt_blob, edp_info))
+ debug("unable to parse DP DT node\n");
+#else
edp_info = dp_pd->edp_dev_info;
if (edp_info == NULL) {
debug("failed to get edp_info data.\n");
return -EFAULT;
}
+#endif
+
+ exynos_dp_set_base_addr();
exynos_dp_disp_info(&edp_info->disp_info);
- if (dp_pd->phy_enable)
- dp_pd->phy_enable(1);
+ exynos_set_dp_phy(1);
ret = exynos_dp_init_dp();
if (ret != EXYNOS_DP_SUCCESS) {
#include <asm/arch/cpu.h>
#include <asm/arch/dp_info.h>
#include <asm/arch/dp.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+struct exynos_dp *dp_regs;
+
+void exynos_dp_set_base_addr(void)
+{
+#ifdef CONFIG_OF_CONTROL
+ unsigned int node = fdtdec_next_compatible(gd->fdt_blob,
+ 0, COMPAT_SAMSUNG_EXYNOS5_DP);
+ if (node <= 0)
+ debug("exynos_dp: Can't get device node for dp\n");
+
+ dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob,
+ node, "reg");
+ if (dp_regs == NULL)
+ debug("Can't get the DP base address\n");
+#else
+ dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+#endif
+}
static void exynos_dp_enable_video_input(unsigned int enable)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->video_ctl1);
reg &= ~VIDEO_EN_MASK;
{
/*enable video bist*/
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->video_ctl4);
reg &= ~VIDEO_BIST_MASK;
void exynos_dp_enable_video_mute(unsigned int enable)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->video_ctl1);
reg &= ~(VIDEO_MUTE_MASK);
static void exynos_dp_init_analog_param(void)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/*
* Set termination
static void exynos_dp_init_interrupt(void)
{
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Set interrupt registers to initial states */
/*
void exynos_dp_reset(void)
{
unsigned int reg_func_1;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/*dp tx sw reset*/
writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
void exynos_dp_enable_sw_func(unsigned int enable)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->func_en1);
reg &= ~(SW_FUNC_EN_N);
unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->phy_pd);
switch (block) {
unsigned int exynos_dp_get_pll_lock_status(void)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->debug_ctl);
static void exynos_dp_set_pll_power(unsigned int enable)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->pll_ctl);
reg &= ~(DP_PLL_PD);
int ret = EXYNOS_DP_SUCCESS;
unsigned int retry_cnt = 10;
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/*Power On All Analog block */
exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
void exynos_dp_init_hpd(void)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Clear interrupts releated to Hot Plug Dectect */
reg = HOTPLUG_CHG | HPD_LOST | PLUG;
static inline void exynos_dp_reset_aux(void)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Disable AUX channel module */
reg = readl(&dp_regs->func_en2);
void exynos_dp_init_aux(void)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Clear inerrupts related to AUX channel */
reg = RPLY_RECEIV | AUX_ERR;
void exynos_dp_config_interrupt(void)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* 0: mask, 1: unmask */
reg = COMMON_INT_MASK_1;
unsigned int exynos_dp_get_plug_in_status(void)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->sys_ctl3);
if (reg & HPD_STATUS)
unsigned int reg;
unsigned int ret = 0;
unsigned int retry_cnt;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Enable AUX CH operation */
reg = readl(&dp_regs->aux_ch_ctl2);
unsigned char data)
{
unsigned int reg, ret;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Clear AUX CH data buffer */
reg = BUF_CLR;
{
unsigned int reg;
int retval;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Clear AUX CH data buffer */
reg = BUF_CLR;
unsigned int cur_data_idx;
unsigned int retry_cnt;
unsigned int ret = 0;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Clear AUX CH data buffer */
reg = BUF_CLR;
unsigned int cur_data_idx;
unsigned int retry_cnt;
unsigned int ret = 0;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Clear AUX CH data buffer */
reg = BUF_CLR;
{
unsigned int reg;
int retval;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Set EDID device address */
reg = device_addr;
unsigned int reg;
int i;
int retval;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
for (i = 0; i < 10; i++) {
/* Clear AUX CH data buffer */
unsigned int cur_data_idx;
unsigned int defer = 0;
int retval = 0;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
for (i = 0; i < count; i += 16) { /* use 16 burst */
for (j = 0; j < 100; j++) {
void exynos_dp_reset_macro(void)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->phy_test);
reg |= MACRO_RST;
void exynos_dp_set_link_bandwidth(unsigned char bwtype)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = (unsigned int)bwtype;
{
unsigned char ret;
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->link_bw_set);
ret = (unsigned char)reg;
void exynos_dp_set_lane_count(unsigned char count)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = (unsigned int)count;
unsigned int exynos_dp_get_lane_count(void)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->lane_count_set);
unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
{
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
unsigned int reg_list[DP_LANE_CNT_4] = {
(unsigned int)&dp_regs->ln0_link_training_ctl,
(unsigned int)&dp_regs->ln1_link_training_ctl,
void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
unsigned char lanecnt)
{
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
unsigned int reg_list[DP_LANE_CNT_4] = {
(unsigned int)&dp_regs->ln0_link_training_ctl,
(unsigned int)&dp_regs->ln1_link_training_ctl,
{
unsigned char i;
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
unsigned int reg_list[DP_LANE_CNT_4] = {
(unsigned int)&dp_regs->ln0_link_training_ctl,
(unsigned int)&dp_regs->ln1_link_training_ctl,
void exynos_dp_set_training_pattern(unsigned int pattern)
{
unsigned int reg = 0;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
switch (pattern) {
case PRBS7:
void exynos_dp_enable_enhanced_mode(unsigned char enable)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->sys_ctl4);
reg &= ~ENHANCED;
void exynos_dp_enable_scrambling(unsigned int enable)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->training_ptn_set);
reg &= ~(SCRAMBLING_DISABLE);
int exynos_dp_init_video(void)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */
reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Video Slave mode setting */
reg = readl(&dp_regs->func_en1);
void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Configure the input color depth, color space, dynamic range */
reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) |
unsigned int reg;
unsigned int bist_type = 0;
struct edp_video_info video_info = edp_info->video_info;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* For master mode, you don't need to set the video format */
if (video_info.master_mode == 0) {
unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Update Video stream clk detect status */
reg = readl(&dp_regs->sys_ctl1);
unsigned int n_value)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
if (type == REGISTER_M) {
reg = readl(&dp_regs->sys_ctl4);
void exynos_dp_set_video_timing_mode(unsigned int type)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->video_ctl10);
reg &= ~FORMAT_SEL;
void exynos_dp_enable_video_master(unsigned int enable)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->soc_general_ctl);
if (enable) {
void exynos_dp_start_video(void)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Enable Video input and disable Mute */
reg = readl(&dp_regs->video_ctl1);
unsigned int exynos_dp_is_video_stream_on(void)
{
unsigned int reg;
- struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Update STRM_VALID */
reg = readl(&dp_regs->sys_ctl3);
void exynos_dp_enable_video_master(unsigned int enable);
void exynos_dp_start_video(void);
unsigned int exynos_dp_is_video_stream_on(void);
+void exynos_dp_set_base_addr(void);
#endif /* _EXYNOS_DP_LOWLEVEL_H */
#include <config.h>
#include <common.h>
#include <lcd.h>
+#include <fdtdec.h>
+#include <libfdt.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <asm/arch/mipi_dsim.h>
#include <asm/arch/dp_info.h>
#include <asm/arch/system.h>
+#include <asm-generic/errno.h>
#include "exynos_fb.h"
static unsigned int panel_width, panel_height;
+/*
+ * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
+ * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve
+ * FB memory at a very early stage, i.e even before exynos_fimd_parse_dt()
+ * is called. So, we are forced to statically assign it.
+ */
+#ifdef CONFIG_OF_CONTROL
+vidinfo_t panel_info = {
+ .vl_col = LCD_XRES,
+ .vl_row = LCD_YRES,
+ .vl_bpix = LCD_COLOR16,
+};
+#endif
+
static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
{
unsigned long palette_size;
}
#endif
+void __exynos_cfg_lcd_gpio(void)
+{
+}
+void exynos_cfg_lcd_gpio(void)
+ __attribute__((weak, alias("__exynos_cfg_lcd_gpio")));
+
+void __exynos_backlight_on(unsigned int onoff)
+{
+}
+void exynos_backlight_on(unsigned int onoff)
+ __attribute__((weak, alias("__exynos_cfg_lcd_gpio")));
+
+void __exynos_reset_lcd(void)
+{
+}
+void exynos_reset_lcd(void)
+ __attribute__((weak, alias("__exynos_reset_lcd")));
+
+void __exynos_lcd_power_on(void)
+{
+}
+void exynos_lcd_power_on(void)
+ __attribute__((weak, alias("__exynos_lcd_power_on")));
+
+void __exynos_cfg_ldo(void)
+{
+}
+void exynos_cfg_ldo(void)
+ __attribute__((weak, alias("__exynos_cfg_ldo")));
+
+void __exynos_enable_ldo(unsigned int onoff)
+{
+}
+void exynos_enable_ldo(unsigned int onoff)
+ __attribute__((weak, alias("__exynos_enable_ldo")));
+
+void __exynos_backlight_reset(void)
+{
+}
+void exynos_backlight_reset(void)
+ __attribute__((weak, alias("__exynos_backlight_reset")));
+
static void lcd_panel_on(vidinfo_t *vid)
{
udelay(vid->init_delay);
- if (vid->backlight_reset)
- vid->backlight_reset();
+ exynos_backlight_reset();
- if (vid->cfg_gpio)
- vid->cfg_gpio();
+ exynos_cfg_lcd_gpio();
- if (vid->lcd_power_on)
- vid->lcd_power_on();
+ exynos_lcd_power_on();
udelay(vid->power_on_delay);
if (vid->dp_enabled)
exynos_init_dp();
- if (vid->reset_lcd) {
- vid->reset_lcd();
- udelay(vid->reset_delay);
- }
+ exynos_reset_lcd();
+
+ udelay(vid->reset_delay);
- if (vid->backlight_on)
- vid->backlight_on(1);
+ exynos_backlight_on(1);
- if (vid->cfg_ldo)
- vid->cfg_ldo();
+ exynos_cfg_ldo();
- if (vid->enable_ldo)
- vid->enable_ldo(1);
+ exynos_enable_ldo(1);
if (vid->mipi_enabled)
exynos_mipi_dsi_init();
}
+#ifdef CONFIG_OF_CONTROL
+int exynos_fimd_parse_dt(const void *blob)
+{
+ unsigned int node;
+ node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
+ if (node <= 0) {
+ debug("exynos_fb: Can't get device node for fimd\n");
+ return -ENODEV;
+ }
+
+ panel_info.vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0);
+ if (panel_info.vl_col == 0) {
+ debug("Can't get XRES\n");
+ return -ENXIO;
+ }
+
+ panel_info.vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0);
+ if (panel_info.vl_row == 0) {
+ debug("Can't get YRES\n");
+ return -ENXIO;
+ }
+
+ panel_info.vl_width = fdtdec_get_int(blob, node,
+ "samsung,vl-width", 0);
+
+ panel_info.vl_height = fdtdec_get_int(blob, node,
+ "samsung,vl-height", 0);
+
+ panel_info.vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0);
+ if (panel_info.vl_freq == 0) {
+ debug("Can't get refresh rate\n");
+ return -ENXIO;
+ }
+
+ if (fdtdec_get_bool(blob, node, "samsung,vl-clkp"))
+ panel_info.vl_clkp = CONFIG_SYS_LOW;
+
+ if (fdtdec_get_bool(blob, node, "samsung,vl-oep"))
+ panel_info.vl_oep = CONFIG_SYS_LOW;
+
+ if (fdtdec_get_bool(blob, node, "samsung,vl-hsp"))
+ panel_info.vl_hsp = CONFIG_SYS_LOW;
+
+ if (fdtdec_get_bool(blob, node, "samsung,vl-vsp"))
+ panel_info.vl_vsp = CONFIG_SYS_LOW;
+
+ if (fdtdec_get_bool(blob, node, "samsung,vl-dp"))
+ panel_info.vl_dp = CONFIG_SYS_LOW;
+
+ panel_info.vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0);
+ if (panel_info.vl_bpix == 0) {
+ debug("Can't get bits per pixel\n");
+ return -ENXIO;
+ }
+
+ panel_info.vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0);
+ if (panel_info.vl_hspw == 0) {
+ debug("Can't get hsync width\n");
+ return -ENXIO;
+ }
+
+ panel_info.vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0);
+ if (panel_info.vl_hfpd == 0) {
+ debug("Can't get right margin\n");
+ return -ENXIO;
+ }
+
+ panel_info.vl_hbpd = (u_char)fdtdec_get_int(blob, node,
+ "samsung,vl-hbpd", 0);
+ if (panel_info.vl_hbpd == 0) {
+ debug("Can't get left margin\n");
+ return -ENXIO;
+ }
+
+ panel_info.vl_vspw = (u_char)fdtdec_get_int(blob, node,
+ "samsung,vl-vspw", 0);
+ if (panel_info.vl_vspw == 0) {
+ debug("Can't get vsync width\n");
+ return -ENXIO;
+ }
+
+ panel_info.vl_vfpd = fdtdec_get_int(blob, node,
+ "samsung,vl-vfpd", 0);
+ if (panel_info.vl_vfpd == 0) {
+ debug("Can't get lower margin\n");
+ return -ENXIO;
+ }
+
+ panel_info.vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0);
+ if (panel_info.vl_vbpd == 0) {
+ debug("Can't get upper margin\n");
+ return -ENXIO;
+ }
+
+ panel_info.vl_cmd_allow_len = fdtdec_get_int(blob, node,
+ "samsung,vl-cmd-allow-len", 0);
+
+ panel_info.win_id = fdtdec_get_int(blob, node, "samsung,winid", 0);
+ panel_info.init_delay = fdtdec_get_int(blob, node,
+ "samsung,init-delay", 0);
+ panel_info.power_on_delay = fdtdec_get_int(blob, node,
+ "samsung,power-on-delay", 0);
+ panel_info.reset_delay = fdtdec_get_int(blob, node,
+ "samsung,reset-delay", 0);
+ panel_info.interface_mode = fdtdec_get_int(blob, node,
+ "samsung,interface-mode", 0);
+ panel_info.mipi_enabled = fdtdec_get_int(blob, node,
+ "samsung,mipi-enabled", 0);
+ panel_info.dp_enabled = fdtdec_get_int(blob, node,
+ "samsung,dp-enabled", 0);
+ panel_info.cs_setup = fdtdec_get_int(blob, node,
+ "samsung,cs-setup", 0);
+ panel_info.wr_setup = fdtdec_get_int(blob, node,
+ "samsung,wr-setup", 0);
+ panel_info.wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0);
+ panel_info.wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0);
+
+ panel_info.logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0);
+ if (panel_info.logo_on) {
+ panel_info.logo_width = fdtdec_get_int(blob, node,
+ "samsung,logo-width", 0);
+ panel_info.logo_height = fdtdec_get_int(blob, node,
+ "samsung,logo-height", 0);
+ panel_info.logo_addr = fdtdec_get_int(blob, node,
+ "samsung,logo-addr", 0);
+ }
+
+ panel_info.rgb_mode = fdtdec_get_int(blob, node,
+ "samsung,rgb-mode", 0);
+ panel_info.pclk_name = fdtdec_get_int(blob, node,
+ "samsung,pclk-name", 0);
+ panel_info.sclk_div = fdtdec_get_int(blob, node,
+ "samsung,sclk-div", 0);
+ panel_info.dual_lcd_enabled = fdtdec_get_int(blob, node,
+ "samsung,dual-lcd-enabled", 0);
+
+ return 0;
+}
+#endif
+
void lcd_ctrl_init(void *lcdbase)
{
set_system_display_ctrl();
set_lcd_clk();
+#ifdef CONFIG_OF_CONTROL
+ if (exynos_fimd_parse_dt(gd->fdt_blob))
+ debug("Can't get proper panel info\n");
+#endif
/* initialize parameters which is specific to panel. */
init_panel_info(&panel_info);
#include <asm/io.h>
#include <lcd.h>
#include <div64.h>
+#include <fdtdec.h>
+#include <libfdt.h>
#include <asm/arch/clk.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include "exynos_fb.h"
+DECLARE_GLOBAL_DATA_PTR;
+
static unsigned long *lcd_base_addr;
static vidinfo_t *pvid;
+static struct exynos_fb *fimd_ctrl;
void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
u_long palette_size)
static void exynos_fimd_set_dualrgb(unsigned int enabled)
{
- struct exynos_fb *fimd_ctrl =
- (struct exynos_fb *)samsung_get_base_fimd();
unsigned int cfg = 0;
if (enabled) {
static void exynos_fimd_set_dp_clkcon(unsigned int enabled)
{
-
- struct exynos_fb *fimd_ctrl =
- (struct exynos_fb *)samsung_get_base_fimd();
unsigned int cfg = 0;
if (enabled)
static void exynos_fimd_set_par(unsigned int win_id)
{
unsigned int cfg = 0;
- struct exynos_fb *fimd_ctrl =
- (struct exynos_fb *)samsung_get_base_fimd();
/* set window control */
cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
static void exynos_fimd_set_buffer_address(unsigned int win_id)
{
unsigned long start_addr, end_addr;
- struct exynos_fb *fimd_ctrl =
- (struct exynos_fb *)samsung_get_base_fimd();
start_addr = (unsigned long)lcd_base_addr;
end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
unsigned int cfg = 0, div = 0, remainder, remainder_div;
unsigned long pixel_clock;
unsigned long long src_clock;
- struct exynos_fb *fimd_ctrl =
- (struct exynos_fb *)samsung_get_base_fimd();
if (pvid->dual_lcd_enabled) {
pixel_clock = pvid->vl_freq *
void exynos_set_trigger(void)
{
unsigned int cfg = 0;
- struct exynos_fb *fimd_ctrl =
- (struct exynos_fb *)samsung_get_base_fimd();
cfg = readl(&fimd_ctrl->trigcon);
{
unsigned int cfg = 0;
int status;
- struct exynos_fb *fimd_ctrl =
- (struct exynos_fb *)samsung_get_base_fimd();
cfg = readl(&fimd_ctrl->trigcon);
static void exynos_fimd_lcd_on(void)
{
unsigned int cfg = 0;
- struct exynos_fb *fimd_ctrl =
- (struct exynos_fb *)samsung_get_base_fimd();
/* display on */
cfg = readl(&fimd_ctrl->vidcon0);
static void exynos_fimd_window_on(unsigned int win_id)
{
unsigned int cfg = 0;
- struct exynos_fb *fimd_ctrl =
- (struct exynos_fb *)samsung_get_base_fimd();
/* enable window */
cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
void exynos_fimd_lcd_off(void)
{
unsigned int cfg = 0;
- struct exynos_fb *fimd_ctrl =
- (struct exynos_fb *)samsung_get_base_fimd();
cfg = readl(&fimd_ctrl->vidcon0);
cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
void exynos_fimd_window_off(unsigned int win_id)
{
unsigned int cfg = 0;
- struct exynos_fb *fimd_ctrl =
- (struct exynos_fb *)samsung_get_base_fimd();
cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
EXYNOS_WINCON(win_id));
{
unsigned int cfg = 0, rgb_mode;
unsigned int offset;
- struct exynos_fb *fimd_ctrl =
- (struct exynos_fb *)samsung_get_base_fimd();
+#ifdef CONFIG_OF_CONTROL
+ unsigned int node;
+
+ node = fdtdec_next_compatible(gd->fdt_blob,
+ 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
+ if (node <= 0)
+ debug("exynos_fb: Can't get device node for fimd\n");
+
+ fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob,
+ node, "reg");
+ if (fimd_ctrl == NULL)
+ debug("Can't get the FIMD base address\n");
+#endif
+ fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
offset = exynos_fimd_get_base_offset();
void dcache_enable (void);
void dcache_disable(void);
void mmu_disable(void);
-void relocate_code (ulong, gd_t *, ulong) __attribute__ ((noreturn));
+#if defined(CONFIG_ARM)
+void relocate_code(ulong);
+#else
+void relocate_code(ulong, gd_t *, ulong) __attribute__ ((noreturn));
+#endif
ulong get_endaddr (void);
void trap_init (ulong);
#if defined (CONFIG_4xx) || \
#endif
#if defined(CONFIG_S3C24X0) || \
defined(CONFIG_LH7A40X) || \
- defined(CONFIG_S3C6400) || \
defined(CONFIG_EP93XX)
ulong get_FCLK (void);
ulong get_HCLK (void);
#ifndef __CONFIG_FALLBACKS_H
#define __CONFIG_FALLBACKS_H
+#ifdef CONFIG_SPL
+#ifdef CONFIG_SPL_PAD_TO
+#ifdef CONFIG_SPL_MAX_SIZE
+#if CONFIG_SPL_PAD_TO && CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE
+#error CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE
+#endif
+#endif
+#else
+#ifdef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
+#else
+#define CONFIG_SPL_PAD_TO 0
+#endif
+#endif
+#endif
+
#ifndef CONFIG_SYS_BAUDRATE_TABLE
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#endif
#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
#define CONFIG_SPL_MAX_SIZE (4 * 1024)
-#define CONFIG_SPL_PAD_TO 0xfff04000
+#define CONFIG_SPL_PAD_TO 0x4000
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_MUSB_GADGET
#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_MUSB_HOST
#ifndef __CONFIG_DRA7XX_EVM_H
#define __CONFIG_DRA7XX_EVM_H
+#define CONFIG_ENV_IS_NOWHERE /* For now. */
+
#include <configs/omap5_common.h>
#define CONFIG_DRA7XX /* in a TI DRA7XX core */
/* Keep L2 Cache Disabled */
#define CONFIG_SYS_DCACHE_OFF
+/* Enable ACE acceleration for SHA1 and SHA256 */
+#define CONFIG_EXYNOS_ACE_SHA
+#define CONFIG_SHA_HW_ACCEL
+
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_TEXT_BASE 0x43E00000
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_NET
+#define CONFIG_CMD_HASH
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define LCD_BPP LCD_COLOR16
#endif
+/* Enable Time Command */
+#define CONFIG_CMD_TIME
+
#endif /* __CONFIG_H */
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-/* define to avoid U-Boot to hang while waiting for TEMT */
-#define CONFIG_SYS_NS16550_BROKEN_TEMT
-
/* select serial console configuration */
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD
+#define CONFIG_NAND_ECC_BCH
+#define CONFIG_BCH
+
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
#define CONFIG_CMD_DIAG
/* we do the whole PCIe FPGA config stuff here */
-#define BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
#endif /* _CONFIG_KM_ARM_H */
#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
#define CONFIG_KM_PIGGY4_88E6061
+/* KM_SUV31 */
+#elif defined(CONFIG_KM_SUV31)
+#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
+#define CONFIG_IDENT_STRING "\nKeymile SUV31"
+#define CONFIG_HOSTNAME kmsuv31
+#define CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_FPGA_CONFIG
+
#else
#error ("Board unsupported")
#endif
/*
* SoC configurations
*/
-#define CONFIG_MX23 /* i.MX23 SoC */
-#define CONFIG_MXS_GPIO /* GPIO control */
-#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+#define CONFIG_MX23 /* i.MX23 SoC */
+#define CONFIG_MXS_GPIO /* GPIO control */
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
-#define CONFIG_MACH_TYPE 4105
+#define CONFIG_MACH_TYPE 4105
#include <asm/arch/regs-base.h>
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_MISC_INIT
/*
* SPL
*/
-#define CONFIG_SPL
-#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
-#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL
+#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
/*
* U-Boot Commands
*/
#include <config_cmd_default.h>
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DOS_PARTITION
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_GPIO
-#define CONFIG_CMD_LED
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_USB
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_LED
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_USB
/*
* Memory configurations
*/
-#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x40000000 /* Base address */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
-#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
-#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
-#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x40000000 /* Base address */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
+#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
+#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Point initial SP in SRAM so SPL can use it too. */
#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
* binary. In case there was more of this mess, 0x100 bytes are skipped.
*/
-#define CONFIG_SYS_TEXT_BASE 0x40000100
+#define CONFIG_SYS_TEXT_BASE 0x40000100
/*
* U-Boot general configurations
*/
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "=> "
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
-#define CONFIG_SYS_PBSIZE \
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Print buffer size */
-#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
-#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
-#define CONFIG_AUTO_COMPLETE /* Command auto complete */
-#define CONFIG_CMDLINE_EDITING /* Command history etc */
-#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
/*
* Serial Driver
*/
-#define CONFIG_PL011_SERIAL
-#define CONFIG_PL011_CLOCK 24000000
-#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
-#define CONFIG_CONS_INDEX 0
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 24000000
+#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
/*
* Status LED
*/
-#define CONFIG_STATUS_LED
-#define CONFIG_GPIO_LED
-#define CONFIG_BOARD_SPECIFIC_LED
-#define STATUS_LED_BOOT 0
-#define STATUS_LED_BIT MX23_PAD_SSP1_DETECT__GPIO_2_1
-#define STATUS_LED_STATE STATUS_LED_ON
-#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+#define CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define STATUS_LED_BOOT 0
+#define STATUS_LED_BIT MX23_PAD_SSP1_DETECT__GPIO_2_1
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
/*
* MMC Driver
*/
-#ifdef CONFIG_CMD_MMC
+#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_GENERIC_MMC
#define CONFIG_APBH_DMA
/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MXS
-#define CONFIG_EHCI_MXS_PORT0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MXS
+#define CONFIG_EHCI_MXS_PORT0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
#endif
/* Ethernet */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
+#ifdef CONFIG_CMD_NET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
#endif
/*
* Boot Linux
*/
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_LOADADDR 0x42000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_LOADADDR 0x42000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_OF_LIBFDT
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OVERWRITE
-#ifdef CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET (256 * 1024)
-#define CONFIG_ENV_SIZE (16 * 1024)
-#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OVERWRITE
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_ENV_SIZE (16 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
/*
"else " \
"bootm; " \
"fi;\0" \
- "netargs=setenv bootargs console=${console_mainline},${baudrate} " \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
#define CONFIG_SYS_I2C_BASE IMX_I2C_BASE
#define CONFIG_SYS_I2C_SPEED 100000
+/* RTC */
+#define CONFIG_RTC_IMXDI
+#define CONFIG_CMD_DATE
+
/* Ethernet Configs */
#define CONFIG_CMD_PING
#ifndef __MX28EVK_CONFIG_H__
#define __MX28EVK_CONFIG_H__
-/*
- * SoC configurations
- */
+/* SoC configurations */
#define CONFIG_MX28 /* i.MX28 SoC */
#define CONFIG_MXS_GPIO /* GPIO control */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_MISC_INIT
-/*
- * SPL
- */
+/* SPL */
#define CONFIG_SPL
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
-/*
- * U-Boot Commands
- */
+/* U-Boot Commands */
#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_SPI
#define CONFIG_CMD_USB
#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NAND
-/*
- * Memory configurations
- */
+/* Memory configurations */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */
#define CONFIG_SYS_TEXT_BASE 0x40000100
#define CONFIG_ENV_OVERWRITE
-/*
- * U-Boot general configurations
- */
+/* U-Boot general configurations */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "MX28EVK U-Boot > "
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
#define CONFIG_CMDLINE_EDITING /* Command history etc */
#define CONFIG_SYS_HUSH_PARSER
-/*
- * Serial Driver
- */
+/* Serial Driver */
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-/*
- * DMA
- */
+/* DMA */
#define CONFIG_APBH_DMA
-/*
- * MMC Driver
- */
-#define CONFIG_ENV_IS_IN_MMC
+/* MMC Driver */
#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (256 * 1024)
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_MXS_MMC
#endif
-/*
- * NAND Driver
- */
+/* NAND Driver */
+#define CONFIG_ENV_SIZE (16 * 1024)
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_MXS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x60000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+/* Environment is in NAND */
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_RANGE (512 * 1024)
+#ifndef CONFIG_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x300000
#endif
+#define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
-/*
- * Ethernet on SOC (FEC)
- */
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=gpmi-nand"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=gpmi-nand:" \
+ "3m(bootloader)ro," \
+ "512k(environment)," \
+ "512k(redundant-environment)," \
+ "4m(kernel)," \
+ "128k(fdt)," \
+ "8m(ramdisk)," \
+ "-(filesystem)"
+#endif
+
+/* Ethernet on SOC (FEC) */
#ifdef CONFIG_CMD_NET
#define CONFIG_NET_MULTI
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_MX28_FEC_MAC_IN_OCOTP
#endif
-/*
- * RTC
- */
+/* RTC */
#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_MXS
#endif
-/*
- * USB
- */
+/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MXS
#define CONFIG_SYS_I2C_SPEED 400000
#endif
-/*
- * SPI
- */
+/* SPI */
#ifdef CONFIG_CMD_SPI
#define CONFIG_HARD_SPI
#define CONFIG_MXS_SPI
#endif
#endif
-/*
- * Boot Linux
- */
+/* Boot Linux */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTDELAY 1
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_OF_LIBFDT
-/*
- * Extra Environments
- */
+/* Extra Environments */
#define CONFIG_EXTRA_ENV_SETTINGS \
"update_nand_full_filename=u-boot.nand\0" \
"update_nand_firmware_filename=u-boot.sb\0" \
#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SPL
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_MAX_SIZE 2048
+#define CONFIG_SPL_NAND_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE 0x87dc0000
+#define CONFIG_SYS_TEXT_BASE 0x87e00000
+
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_IMX_WATCHDOG
#define CONFIG_MXC_GPIO
#define CONFIG_HARD_SPI
"bootcmd=run bootcmd_net\0" \
"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
"tftpboot 0x81000000 uImage-mx31; bootm\0" \
- "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \
+ "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
"nand erase 0x0 0x40000; " \
"nand write 0x81000000 0x0 0x40000\0"
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_GBL_DATA_OFFSET)
+ CONFIG_SYS_INIT_RAM_SIZE)
/*-----------------------------------------------------------------------
* FLASH and environment organization
/* NAND configuration for the NAND_SPL */
/* Start copying real U-boot from the second page */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
/* Load U-Boot to this address */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MXC_GPIO
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
+#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_CMD_NAND
+
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
/* Command definition */
#include <config_cmd_default.h>
+#define CONFIG_CMD_BMODE
#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
"fi;\0"
#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev};" \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"fi; " \
"else run netboot; fi"
-#define CONFIG_ARP_TIMEOUT 200UL
-
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
+#define CONFIG_OF_LIBFDT
/*
* Size of malloc() pool
#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
#define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Physical Memory Map
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */
#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_128K)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_256K)
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
*/
#define CONFIG_BOOTDELAY 3
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
#define CONFIG_ENV_OVERWRITE
"loadaddr=0x82000000\0" \
"console=ttyO2,115200n8\0" \
"fdt_high=0xffffffff\0" \
+ "fdtaddr=0x80f80000\0" \
+ "bootpart=0:2\0" \
+ "bootdir=/boot\0" \
+ "bootfile=zImage\0" \
"usbtty=cdc_acm\0" \
"vram=16M\0" \
"mmcdev=0\0" \
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
"env import -t ${loadaddr} ${filesize}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
"mmcboot=echo Booting from mmc${mmcdev} ...; " \
"run mmcargs; " \
- "bootm ${loadaddr}\0" \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+ "findfdt="\
+ "if test $board_name = sdp4430; then " \
+ "setenv fdtfile omap4-sdp.dtb; fi; " \
+ "if test $board_name = panda; then " \
+ "setenv fdtfile omap4-panda-es.dtb; fi\0" \
+ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
"if run loadbootscript; then " \
"run uenvcmd;" \
"fi;" \
"fi;" \
- "if run loaduimage; then " \
+ "if run loadimage; then " \
+ "run loadfdt;" \
"run mmcboot; " \
"fi; " \
"fi"
*/
#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_ENV_IS_IN_FLASH 1
/* addr of environment */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_OFFSET 0x40000 /* environment starts here */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR PHYS_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE (250 * 1024)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE)
#endif /* __CONFIG_H */
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
+
/* I2C */
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_DRIVER_OMAP34XX_I2C
#define CONFIG_I2C_MULTI_BUS
-
/* MMC */
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
-/* MMC ENV related defines */
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
-#define CONFIG_ENV_OFFSET 0xE0000
-#define CONFIG_CMD_SAVEENV
-
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/* Flash */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
-#define CONFIG_CMD_SAVEENV
/* Disabled commands */
#undef CONFIG_CMD_NET
*/
#define CONFIG_BOOTDELAY 3
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
#define CONFIG_ENV_OVERWRITE
+#ifndef PARTS_DEFAULT
+#define PARTS_DEFAULT
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"console=ttyO2,115200n8\0" \
+ "fdt_high=0xffffffff\0" \
+ "fdtaddr=0x80f80000\0" \
+ "bootpart=0:2\0" \
+ "bootdir=/boot\0" \
+ "bootfile=zImage\0" \
"usbtty=cdc_acm\0" \
"vram=16M\0" \
+ "partitions=" PARTS_DEFAULT "\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
"source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+ "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
+ "env import -t ${loadaddr} ${filesize}\0" \
+ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
"mmcboot=echo Booting from mmc${mmcdev} ...; " \
"run mmcargs; " \
- "bootm ${loadaddr}\0" \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+ "findfdt="\
+ "if test $board_name = omap5_uevm; then " \
+ "setenv fdtfile omap5-uevm.dtb; fi;\0 " \
+ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "fi; " \
+ "if run loadbootenv; then " \
+ "run importbootenv; " \
+ "fi;" \
+ "if test -n ${uenvcmd}; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "fi;" \
+ "if run loadimage; then " \
+ "run loadfdt; " \
+ "run mmcboot; " \
"fi; " \
"fi"
+++ /dev/null
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated.
- * Sricharan R <r.sricharan@ti.com>
- *
- * Configuration settings for the TI EVM5430 board.
- * See omap5_common.h for omap5 common settings.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_OMAP5_EVM_H
-#define __CONFIG_OMAP5_EVM_H
-
-#include <configs/omap5_common.h>
-
-/* TWL6035 */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_TWL6035_POWER
-#endif
-
-#define CONFIG_SYS_PROMPT "OMAP5430 EVM # "
-
-#endif /* __CONFIG_OMAP5_EVM_H */
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated.
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * Configuration settings for the TI EVM5430 board.
+ * See omap5_common.h for omap5 common settings.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_OMAP5_EVM_H
+#define __CONFIG_OMAP5_EVM_H
+
+/* Define the default GPT table for eMMC */
+#define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
+
+#include <configs/omap5_common.h>
+
+/* TWL6035 */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_TWL6035_POWER
+#endif
+
+/* MMC ENV related defines */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
+#define CONFIG_ENV_OFFSET 0xE0000
+#define CONFIG_CMD_SAVEENV
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+#define CONFIG_SYS_PROMPT "OMAP5430 EVM # "
+
+#endif /* __CONFIG_OMAP5_EVM_H */
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xfffff000
-#define CONFIG_SPL_MAX_SIZE (4 * 1024)
+#define CONFIG_SPL_MAX_SIZE 4096
#ifdef CONFIG_SYS_INIT_L2_ADDR
/* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */
#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708
/* Timer */
-#define CONFIG_SYS_HZ 1000000
+#define CONFIG_SYS_HZ 1000
/* Memory layout */
#define CONFIG_NR_DRAM_BANKS 1
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Gary Jennejohn <garyj@denx.de>
- * David Mueller <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_S3C6400 1 /* in a SAMSUNG S3C6400 SoC */
-#define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */
-#define CONFIG_SMDK6400 1 /* on a SAMSUNG SMDK6400 Board */
-
-#define CONFIG_PERIPORT_REMAP
-#define CONFIG_PERIPORT_BASE 0x70000000
-#define CONFIG_PERIPORT_SIZE 0x13
-
-#define CONFIG_SYS_IRAM_BASE 0x0c000000 /* Internal SRAM base address */
-#define CONFIG_SYS_IRAM_SIZE 0x2000 /* 8 KB of internal SRAM memory */
-#define CONFIG_SYS_IRAM_END (CONFIG_SYS_IRAM_BASE + CONFIG_SYS_IRAM_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IRAM_END - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_SDRAM_BASE 0x50000000
-
-/* input clock of PLL: SMDK6400 has 12MHz input clock */
-#define CONFIG_SYS_CLK_FREQ 12000000
-
-#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
-#define CONFIG_ENABLE_MMU
-#endif
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-
-/*
- * Architecture magic and machine type
- */
-#define CONFIG_MACH_TYPE 1270
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_CS8900 /* we have a CS8900 on-board */
-#define CONFIG_CS8900_BASE 0x18800300
-#define CONFIG_CS8900_BUS16 /* follow the Linux driver */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK6400 */
-
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#define CONFIG_CMDLINE_EDITING
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 115200
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_NAND
-#if defined(CONFIG_BOOT_ONENAND)
-#define CONFIG_CMD_ONENAND
-#endif
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "SMDK6400 # " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load address */
-
-#define CONFIG_SYS_HZ 1000
-
-/**********************************
- Support Clock Settings
- **********************************
- Setting SYNC ASYNC
- ----------------------------------
- 667_133_66 X O
- 533_133_66 O O
- 400_133_66 X O
- 400_100_50 O O
- **********************************/
-
-/*#define CONFIG_CLK_667_133_66*/
-#define CONFIG_CLK_533_133_66
-/*
-#define CONFIG_CLK_400_100_50
-#define CONFIG_CLK_400_133_66
-#define CONFIG_SYNC_MODE
-*/
-
-/* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB in Bank #1 */
-
-#define CONFIG_SYS_FLASH_BASE 0x10000000
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-/* AM29LV160B has 35 sectors, AM29LV800B - 19 */
-#define CONFIG_SYS_MAX_FLASH_SECT 40
-
-#define CONFIG_AMD_LV800
-#define CONFIG_SYS_FLASH_CFI 1 /* Use CFI parameters (needed?) */
-/* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant */
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_LEGACY_512Kx16
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/*
- * SMDK6400 board specific data
- */
-
-#define CONFIG_IDENT_STRING " for SMDK6400"
-
-/* base address for uboot */
-#define CONFIG_SYS_PHY_UBOOT_BASE (CONFIG_SYS_SDRAM_BASE + 0x07e00000)
-/* total memory available to uboot */
-#define CONFIG_SYS_UBOOT_SIZE (1024 * 1024)
-
-/* Put environment copies after the end of U-Boot owned RAM */
-#define CONFIG_NAND_ENV_DST (CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE)
-
-#ifdef CONFIG_ENABLE_MMU
-#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000
-#define CONFIG_BOOTCOMMAND "nand read 0xc0018000 0x60000 0x1c0000;" \
- "bootm 0xc0018000"
-#else
-#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
-#define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \
- "bootm 0x50018000"
-#endif
-
-/* NAND U-Boot load and start address */
-#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_MAPPED_RAM_BASE + 0x07e00000)
-
-#define CONFIG_ENV_OFFSET 0x0040000
-
-/* NAND configuration */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x70200010
-#define CONFIG_SYS_S3C_NAND_HWECC
-
-#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-#define CONFIG_SYS_NAND_WP 1
-#define CONFIG_SYS_NAND_YAFFS_WRITE 1 /* support yaffs write */
-#define CONFIG_SYS_NAND_BBT_2NDPAGE 1 /* bad-block markers in 1st and 2nd pages */
-
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_PHY_UBOOT_BASE /* NUB load-addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* NUB start-addr */
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */
-
-/* NAND chip page size */
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-/* NAND chip block size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-/* NAND chip page per block count */
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-/* Location of the bad-block label */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-/* Extra address cycle for > 128MiB */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-
-/* Size of the block protected by one OOB (Spare Area in Samsung terminology) */
-#define CONFIG_SYS_NAND_ECCSIZE CONFIG_SYS_NAND_PAGE_SIZE
-/* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */
-#define CONFIG_SYS_NAND_ECCBYTES 4
-/* Size of a single OOB region */
-#define CONFIG_SYS_NAND_OOBSIZE 64
-/* ECC byte positions */
-#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
- 48, 49, 50, 51, 52, 53, 54, 55, \
- 56, 57, 58, 59, 60, 61, 62, 63}
-
-/* Boot configuration (define only one of next 3) */
-#define CONFIG_BOOT_NAND
-/* None of these are currently implemented. Left from the original Samsung
- * version for reference
-#define CONFIG_BOOT_NOR
-#define CONFIG_BOOT_MOVINAND
-#define CONFIG_BOOT_ONENAND
-*/
-
-#define CONFIG_NAND
-#define CONFIG_NAND_S3C64XX
-/* Unimplemented or unsupported. See comment above.
-#define CONFIG_ONENAND
-#define CONFIG_MOVINAND
-*/
-
-/* Settings as above boot configuration */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_BOOTARGS "console=ttySAC,115200"
-
-#if !defined(CONFIG_ENABLE_MMU)
-#define CONFIG_CMD_USB 1
-#define CONFIG_USB_S3C64XX
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x74300000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "s3c6400"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
-
-#define CONFIG_USB_STORAGE 1
-#endif
-#define CONFIG_DOS_PARTITION 1
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_ENABLE_MMU)
-# error "usb_ohci.c is currently broken with MMU enabled."
-#endif
-
-#endif /* __CONFIG_H */
"splfile=falcon.bin\0" \
"spl_export=" \
"setexpr spl_imgsize ${splsize} + 8 ;" \
+ "setenv spl_imgsize 0x${spl_imgsize};" \
"setexpr spl_imgaddr ${spladdr} - 8 ;" \
"setexpr spl_addr_tmp ${spladdr} - 4 ;" \
"mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
+#define CONFIG_NAND_OMAP_BCH8
+#define CONFIG_BCH
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
-#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
+#define CONFIG_SPL_MAX_SIZE (55 * 1024) /* 7 KB for stack */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
- 10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCPOS {12, 13, 14, 15, 16, 17, 18, 19, 20,\
+ 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\
+ 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,\
+ 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,\
+ 60, 61, 62, 63}
#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_SYS_NAND_ECCBYTES 13
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <asm/arch/imx-regs.h>
/*
* KARO TX25 board - SoC Configuration
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
-/* NAND BOOT is the only boot method */
-#define CONFIG_NAND_U_BOOT
+#define CONFIG_SPL
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_MAX_SIZE 2048
+#define CONFIG_SPL_NAND_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE 0x810c0000
+#define CONFIG_SYS_TEXT_BASE 0x81200000
#ifndef MACH_TYPE_TX25
#define MACH_TYPE_TX25 2177
#define CONFIG_MACH_TYPE MACH_TYPE_TX25
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
/* Start copying real U-boot from the second page */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x81200000)
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_SPARE_SIZE 64
+#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024)
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (IMX_RAM_BASE + IMX_RAM_SIZE)
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Wandboard.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+#include <asm/sizes.h>
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MACH_TYPE_WANDBOARD 4412
+#define CONFIG_MACH_TYPE MACH_TYPE_WANDBOARD
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 5
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+#define CONFIG_LOADADDR 0x12000000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+/* MMC Configuration */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Ethernet Configuration */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+#if defined(CONFIG_MX6DL)
+#define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb"
+#elif defined(CONFIG_MX6S)
+#define CONFIG_DEFAULT_FDT_FILE "imx6s-wandboard.dtb"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "uimage=uImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x11000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev=0\0" \
+ "mmcpart=2\0" \
+ "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${uimage}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif /* __CONFIG_H * */
COMPAT_SAMSUNG_EXYNOS_EHCI, /* Exynos EHCI controller */
COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */
COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */
+ COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */
+ COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */
COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */
COMPAT_MAXIM_98095_CODEC, /* MAX98095 Codec */
struct fsl_esdhc_cfg {
u32 esdhc_base;
u32 sdhc_clk;
+ u8 max_bus_width;
};
/* Select the correct accessors depending on endianess */
+++ /dev/null
-/*
- * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __FSL_NFC_H
-#define __FSL_NFC_H
-
-/*
- * Register map and bit definitions for the Freescale NAND Flash Controller
- * present in various i.MX devices.
- *
- * MX31 and MX27 have version 1, which has:
- * 4 512-byte main buffers and
- * 4 16-byte spare buffers
- * to support up to 2K byte pagesize nand.
- * Reading or writing a 2K page requires 4 FDI/FDO cycles.
- *
- * MX25 and MX35 have version 2.1, which has:
- * 8 512-byte main buffers and
- * 8 64-byte spare buffers
- * to support up to 4K byte pagesize nand.
- * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
- * Also some of registers are moved and/or changed meaning as seen below.
- */
-#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
-#define MXC_NFC_V1
-#define is_mxc_nfc_1() 1
-#define is_mxc_nfc_21() 0
-#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
-#define MXC_NFC_V2_1
-#define is_mxc_nfc_1() 0
-#define is_mxc_nfc_21() 1
-#else
-#error "MXC NFC implementation not supported"
-#endif
-
-#if defined(MXC_NFC_V1)
-#define NAND_MXC_NR_BUFS 4
-#define NAND_MXC_SPARE_BUF_SIZE 16
-#define NAND_MXC_REG_OFFSET 0xe00
-#define NAND_MXC_2K_MULTI_CYCLE
-#elif defined(MXC_NFC_V2_1)
-#define NAND_MXC_NR_BUFS 8
-#define NAND_MXC_SPARE_BUF_SIZE 64
-#define NAND_MXC_REG_OFFSET 0x1e00
-#endif
-
-struct fsl_nfc_regs {
- u8 main_area[NAND_MXC_NR_BUFS][0x200];
- u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
- /*
- * reserved size is offset of nfc registers
- * minus total main and spare sizes
- */
- u8 reserved1[NAND_MXC_REG_OFFSET
- - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
-#if defined(MXC_NFC_V1)
- u16 buf_size;
- u16 reserved2;
- u16 buf_addr;
- u16 flash_addr;
- u16 flash_cmd;
- u16 config;
- u16 ecc_status_result;
- u16 rsltmain_area;
- u16 rsltspare_area;
- u16 wrprot;
- u16 unlockstart_blkaddr;
- u16 unlockend_blkaddr;
- u16 nf_wrprst;
- u16 config1;
- u16 config2;
-#elif defined(MXC_NFC_V2_1)
- u16 reserved2[2];
- u16 buf_addr;
- u16 flash_addr;
- u16 flash_cmd;
- u16 config;
- u32 ecc_status_result;
- u16 spare_area_size;
- u16 wrprot;
- u16 reserved3[2];
- u16 nf_wrprst;
- u16 config1;
- u16 config2;
- u16 reserved4;
- u16 unlockstart_blkaddr;
- u16 unlockend_blkaddr;
- u16 unlockstart_blkaddr1;
- u16 unlockend_blkaddr1;
- u16 unlockstart_blkaddr2;
- u16 unlockend_blkaddr2;
- u16 unlockstart_blkaddr3;
- u16 unlockend_blkaddr3;
-#endif
-};
-
-/*
- * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command
- * operation
- */
-#define NFC_CMD 0x1
-
-/*
- * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address
- * operation
- */
-#define NFC_ADDR 0x2
-
-/*
- * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input
- * operation
- */
-#define NFC_INPUT 0x4
-
-/*
- * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data
- * Output operation
- */
-#define NFC_OUTPUT 0x8
-
-/*
- * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID
- * operation
- */
-#define NFC_ID 0x10
-
-/*
- * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read
- * Status operation
- */
-#define NFC_STATUS 0x20
-
-/*
- * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status
- * operation
- */
-#define NFC_INT 0x8000
-
-#ifdef MXC_NFC_V2_1
-#define NFC_4_8N_ECC (1 << 0)
-#endif
-#define NFC_SP_EN (1 << 2)
-#define NFC_ECC_EN (1 << 3)
-#define NFC_INT_MSK (1 << 4)
-#define NFC_BIG (1 << 5)
-#define NFC_RST (1 << 6)
-#define NFC_CE (1 << 7)
-#define NFC_ONE_CYCLE (1 << 8)
-#define NFC_FP_INT (1 << 11)
-
-#endif /* __FSL_NFC_H */
--- /dev/null
+/*
+ * Header file for SHA hardware acceleration
+ *
+ * Copyright (c) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#ifndef __HW_SHA_H
+#define __HW_SHA_H
+
+
+/**
+ * Computes hash value of input pbuf using h/w acceleration
+ *
+ * @param in_addr A pointer to the input buffer
+ * @param bufleni Byte length of input buffer
+ * @param out_addr A pointer to the output buffer. When complete
+ * 32 bytes are copied to pout[0]...pout[31]. Thus, a user
+ * should allocate at least 32 bytes at pOut in advance.
+ * @param chunk_size chunk size for sha256
+ */
+void hw_sha256(const uchar * in_addr, uint buflen,
+ uchar * out_addr, uint chunk_size);
+
+/**
+ * Computes hash value of input pbuf using h/w acceleration
+ *
+ * @param in_addr A pointer to the input buffer
+ * @param bufleni Byte length of input buffer
+ * @param out_addr A pointer to the output buffer. When complete
+ * 32 bytes are copied to pout[0]...pout[31]. Thus, a user
+ * should allocate at least 32 bytes at pOut in advance.
+ * @param chunk_size chunk_size for sha1
+ */
+void hw_sha1(const uchar * in_addr, uint buflen,
+ uchar * out_addr, uint chunk_size);
+#endif
u_char vl_vbpd; /* Wait end of frame */
u_char vl_cmd_allow_len; /* Wait end of frame */
- void (*cfg_gpio)(void);
- void (*backlight_on)(unsigned int onoff);
- void (*reset_lcd)(void);
- void (*lcd_power_on)(void);
- void (*cfg_ldo)(void);
- void (*enable_ldo)(unsigned int onoff);
- void (*mipi_power)(void);
- void (*backlight_reset)(void);
-
unsigned int win_id;
unsigned int init_delay;
unsigned int power_on_delay;
extern int flexonenand_set_boundary(struct mtd_info *mtd, int die,
int boundary, int lock);
-/* S3C64xx */
-extern void s3c64xx_onenand_init(struct mtd_info *);
-extern void s3c64xx_set_width_regs(struct onenand_chip *);
-
/* SPL */
void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst);
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_ADDR_MAP) += addr_map.o
-COBJS-$(CONFIG_BCH) += bch.o
COBJS-$(CONFIG_AES) += aes.o
COBJS-$(CONFIG_BZIP2) += bzlib.o
COBJS-$(CONFIG_BZIP2) += bzlib_crctable.o
COBJS-$(CONFIG_SPL_NET_SUPPORT) += hashtable.o
COBJS-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o
endif
+COBJS-$(CONFIG_BCH) += bch.o
COBJS-y += crc32.o
COBJS-y += ctype.o
COBJS-y += div64.o
COMPAT(SAMSUNG_EXYNOS_EHCI, "samsung,exynos-ehci"),
COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),
COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"),
+ COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"),
+ COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"),
set ${line}
# add default board name if needed
[ $# = 3 ] && set ${line} ${1}
-elif [ "${MAKEFLAGS+set}${MAKELEVEL+set}" = "setset" ] ; then
- # only warn when using a config target in the Makefile
- cat <<-EOF
-
- warning: Please migrate to boards.cfg. Failure to do so will
- mean removal of your board in the next release.
-
- EOF
- sleep 5
fi
while [ $# -gt 0 ] ; do
+++ /dev/null
-CONFIG_NAND_SPL = y
-PAD_TO := 2048
-
-include $(TOPDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-
-SOBJS = start.o crt0.o lowlevel_init.o
-COBJS = nand_boot_fsl_nfc.o
-
-SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
-SRCS += $(SRCTREE)/arch/arm/cpu/arm1136/start.S
-SRCS += $(SRCTREE)/arch/arm/lib/crt0.S
-SRCS += $(SRCTREE)/board/freescale/mx31pdk/lowlevel_init.S
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-#########################################################################
-
-$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm1136/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/arch/arm/lib/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/board/freescale/mx31pdk/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/nand_spl/%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- start.o (.text)
- lowlevel_init.o (.text)
- nand_boot_fsl_nfc.o (.text)
- *(.text)
- . = 2K;
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- . = ALIGN(4);
- .u_boot_list : {
- *(SORT(.u_boot_list*));
- }
-
- . = ALIGN(4);
-
- __image_copy_end = .;
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end = .;
- }
-
- /DISCARD/ : { *(.bss*) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynsym*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.hash*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
+++ /dev/null
-#
-# (C) Copyright 2009 DENX Software Engineering
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundatio; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-CONFIG_NAND_SPL = y
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-
-SOBJS = start.o crt0.o lowlevel_init.o
-COBJS = nand_boot_fsl_nfc.o
-
-SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
-SRCS += $(SRCTREE)/arch/arm/cpu/arm926ejs/start.S
-SRCS += $(SRCTREE)/arch/arm/lib/crt0.S
-SRCS += $(SRCTREE)/board/karo/tx25/lowlevel_init.S
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-#########################################################################
-
-$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm926ejs/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/arch/arm/lib/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/board/karo/tx25/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/nand_spl/%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-PAD_TO := 2048
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- start.o (.text)
- lowlevel_init.o (.text)
- nand_boot_fsl_nfc.o (.text)
- *(.text)
- . = 2K;
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- . = ALIGN(4);
- .u_boot_list : {
- *(SORT(.u_boot_list*));
- }
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end = .;
- }
-
- /DISCARD/ : { *(.bss*) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynsym*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.hash*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
+++ /dev/null
-#
-# (C) Copyright 2006-2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-CONFIG_NAND_SPL = y
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL) -gc-sections
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL -ffunction-sections
-
-SOBJS = start.o cpu_init.o lowlevel_init.o
-COBJS = nand_boot.o nand_ecc.o s3c64xx.o smdk6400_nand_spl.o nand_base.o
-
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)start.S:
- @rm -f $@
- @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/start.S $@
-
-# from SoC directory
-$(obj)cpu_init.S:
- @rm -f $@
- @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S $@
-
-# from board directory
-$(obj)lowlevel_init.S:
- @rm -f $@
- @ln -s $(TOPDIR)/board/samsung/smdk6400/lowlevel_init.S $@
-
-# from nand_spl directory
-$(obj)nand_boot.c:
- @rm -f $@
- @ln -s $(TOPDIR)/nand_spl/nand_boot.c $@
-
-# from drivers/mtd/nand directory
-$(obj)nand_ecc.c:
- @rm -f $@
- @ln -s $(TOPDIR)/drivers/mtd/nand/nand_ecc.c $@
-
-$(obj)s3c64xx.c:
- @rm -f $@
- @ln -s $(TOPDIR)/drivers/mtd/nand/s3c64xx.c $@
-
-$(obj)smdk6400_nand_spl.c:
- @rm -f $@
- @ln -s $(TOPDIR)/board/samsung/smdk6400/smdk6400_nand_spl.c $@
-
-$(obj)nand_base.c:
- @rm -f $@
- @ln -s $(TOPDIR)/drivers/mtd/nand/nand_base.c $@
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2006
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-#
-# Samsung S3C64xx Reference Platform (smdk6400) board
-
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On S3C64xx platforms the SPL is located in SRAM at 0.
-#
-# CONFIG_SYS_TEXT_BASE = 0
-
-include $(TOPDIR)/board/$(BOARDDIR)/config.mk
-
-# PAD_TO used to generate a 4kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 4096
-PAD_TO := $(shell expr $$[$(CONFIG_SYS_TEXT_BASE) + 4096])
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- start.o (.text)
- cpu_init.o (.text)
- nand_boot.o (.text)
-
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
-
- . = ALIGN(4);
- .u_boot_list : {
- *(SORT(.u_boot_list*));
- }
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end = .;
- }
-}
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Magnus Lilja <lilja.magnus@gmail.com>
- *
- * (C) Copyright 2008
- * Maxim Artamonov, <scn1874 at yandex.ru>
- *
- * (C) Copyright 2006-2008
- * Stefan Roese, DENX Software Engineering, sr at denx.de.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/io.h>
-#include <fsl_nfc.h>
-
-static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR;
-
-static void nfc_wait_ready(void)
-{
- uint32_t tmp;
-
- while (!(readw(&nfc->config2) & NFC_INT))
- ;
-
- /* Reset interrupt flag */
- tmp = readw(&nfc->config2);
- tmp &= ~NFC_INT;
- writew(tmp, &nfc->config2);
-}
-
-static void nfc_nand_init(void)
-{
-#if defined(MXC_NFC_V2_1)
- int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
- int config1;
-
- writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size);
-
- /* unlocking RAM Buff */
- writew(0x2, &nfc->config);
-
- /* hardware ECC checking and correct */
- config1 = readw(&nfc->config1) | NFC_ECC_EN | NFC_INT_MSK |
- NFC_ONE_CYCLE | NFC_FP_INT;
- /*
- * if spare size is larger that 16 bytes per 512 byte hunk
- * then use 8 symbol correction instead of 4
- */
- if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16)
- config1 &= ~NFC_4_8N_ECC;
- else
- config1 |= NFC_4_8N_ECC;
- writew(config1, &nfc->config1);
-#elif defined(MXC_NFC_V1)
- /* unlocking RAM Buff */
- writew(0x2, &nfc->config);
-
- /* hardware ECC checking and correct */
- writew(NFC_ECC_EN | NFC_INT_MSK, &nfc->config1);
-#endif
-}
-
-static void nfc_nand_command(unsigned short command)
-{
- writew(command, &nfc->flash_cmd);
- writew(NFC_CMD, &nfc->config2);
- nfc_wait_ready();
-}
-
-static void nfc_nand_address(unsigned short address)
-{
- writew(address, &nfc->flash_addr);
- writew(NFC_ADDR, &nfc->config2);
- nfc_wait_ready();
-}
-
-static void nfc_nand_page_address(unsigned int page_address)
-{
- unsigned int page_count;
-
- nfc_nand_address(0x00);
-
- /* code only for large page flash */
- if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
- nfc_nand_address(0x00);
-
- page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
-
- if (page_address <= page_count) {
- page_count--; /* transform 0x01000000 to 0x00ffffff */
- do {
- nfc_nand_address(page_address & 0xff);
- page_address = page_address >> 8;
- page_count = page_count >> 8;
- } while (page_count);
- }
-
- nfc_nand_address(0x00);
-}
-
-static void nfc_nand_data_output(void)
-{
-#ifdef NAND_MXC_2K_MULTI_CYCLE
- int i;
-#endif
-
- writew(0, &nfc->buf_addr);
- writew(NFC_OUTPUT, &nfc->config2);
- nfc_wait_ready();
-#ifdef NAND_MXC_2K_MULTI_CYCLE
- /*
- * This NAND controller requires multiple input commands
- * for pages larger than 512 bytes.
- */
- for (i = 1; i < CONFIG_SYS_NAND_PAGE_SIZE / 512; i++) {
- writew(i, &nfc->buf_addr);
- writew(NFC_OUTPUT, &nfc->config2);
- nfc_wait_ready();
- }
-#endif
-}
-
-static int nfc_nand_check_ecc(void)
-{
-#if defined(MXC_NFC_V1)
- u16 ecc_status = readw(&nfc->ecc_status_result);
- return (ecc_status & 0x3) == 2 || (ecc_status >> 2) == 2;
-#elif defined(MXC_NFC_V2_1)
- u32 ecc_status = readl(&nfc->ecc_status_result);
- int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
- int err_limit = CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16 ? 8 : 4;
- int subpages = CONFIG_SYS_NAND_PAGE_SIZE / 512;
-
- do {
- if ((ecc_status & 0xf) > err_limit)
- return 1;
- ecc_status >>= 4;
- } while (--subpages);
-
- return 0;
-#endif
-}
-
-static void nfc_nand_read_page(unsigned int page_address)
-{
- writew(0, &nfc->buf_addr); /* read in first 0 buffer */
- nfc_nand_command(NAND_CMD_READ0);
- nfc_nand_page_address(page_address);
-
- if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
- nfc_nand_command(NAND_CMD_READSTART);
-
- nfc_nand_data_output(); /* fill the main buffer 0 */
-}
-
-static int nfc_read_page(unsigned int page_address, unsigned char *buf)
-{
- int i;
- u32 *src;
- u32 *dst;
-
- nfc_nand_read_page(page_address);
-
- if (nfc_nand_check_ecc())
- return -1;
-
- src = (u32 *)&nfc->main_area[0][0];
- dst = (u32 *)buf;
-
- /* main copy loop from NAND-buffer to SDRAM memory */
- for (i = 0; i < CONFIG_SYS_NAND_PAGE_SIZE / 4; i++) {
- writel(readl(src), dst);
- src++;
- dst++;
- }
-
- return 0;
-}
-
-static int is_badblock(int pagenumber)
-{
- int page = pagenumber;
- u32 badblock;
- u32 *src;
-
- /* Check the first two pages for bad block markers */
- for (page = pagenumber; page < pagenumber + 2; page++) {
- nfc_nand_read_page(page);
-
- src = (u32 *)&nfc->spare_area[0][0];
-
- /*
- * IMPORTANT NOTE: The nand flash controller uses a non-
- * standard layout for large page devices. This can
- * affect the position of the bad block marker.
- */
- /* Get the bad block marker */
- badblock = readl(&src[CONFIG_SYS_NAND_BAD_BLOCK_POS / 4]);
- badblock >>= 8 * (CONFIG_SYS_NAND_BAD_BLOCK_POS % 4);
- badblock &= 0xff;
-
- /* bad block marker verify */
- if (badblock != 0xff)
- return 1; /* potential bad block */
- }
-
- return 0;
-}
-
-static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
-{
- int i;
- unsigned int page;
- unsigned int maxpages = CONFIG_SYS_NAND_SIZE /
- CONFIG_SYS_NAND_PAGE_SIZE;
-
- nfc_nand_init();
-
- /* Convert to page number */
- page = from / CONFIG_SYS_NAND_PAGE_SIZE;
- i = 0;
-
- while (i < size / CONFIG_SYS_NAND_PAGE_SIZE) {
- if (nfc_read_page(page, buf) < 0)
- return -1;
-
- page++;
- i++;
- buf = buf + CONFIG_SYS_NAND_PAGE_SIZE;
-
- /*
- * Check if we have crossed a block boundary, and if so
- * check for bad block.
- */
- if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
- /*
- * Yes, new block. See if this block is good. If not,
- * loop until we find a good block.
- */
- while (is_badblock(page)) {
- page = page + CONFIG_SYS_NAND_PAGE_COUNT;
- /* Check i we've reached the end of flash. */
- if (page >= maxpages)
- return -1;
- }
- }
- }
-
- return 0;
-}
-
-#if defined(CONFIG_ARM)
-void board_init_f (ulong bootflag)
-{
- relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
- CONFIG_SYS_TEXT_BASE);
-}
-#endif
-
-/*
- * The main entry for NAND booting. It's necessary that SDRAM is already
- * configured and available since this code loads the main U-Boot image
- * from NAND into SDRAM and starts it from there.
- */
-void nand_boot(void)
-{
- __attribute__((noreturn)) void (*uboot)(void);
-
- /*
- * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
- * be aligned to full pages
- */
- if (!nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
- /* Copy from NAND successful, start U-boot */
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
- uboot();
- } else {
- /* Unrecoverable error when copying from NAND */
- hang();
- }
-}
-
-/*
- * Called in case of an exception.
- */
-void hang(void)
-{
- /* Loop forever */
- while (1) ;
-}
s/="\([0-9][0-9]*\)"/=\1/;
# ... and from hex numbers
s/="\(0[Xx][0-9a-fA-F][0-9a-fA-F]*\)"/=\1/;
+ # ... and from configs defined from other configs
+ s/="\(CONFIG_[A-Za-z0-9_][A-Za-z0-9_]*\)"/=$(\1)/;
# Change '1' and empty values to "y" (not perfect, but
# supports conditional compilation in the makefiles
s/=$/=y/;
projects / u-boot / commitdiff
