<projectStorage><?xml version="1.0" encoding="UTF-8"?> \r
<TargetConfig> \r
<Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1766ENG" property_count="5" version="1"/> \r
-<infoList vendor="NXP"><info chip="LPC1766ENG" match_id="0x00033f33" name="LPC1766ENG"><chip><name>LPC1766ENG</name> \r
+<infoList vendor="NXP"> \r
+<info chip="LPC1766ENG" match_id="0x00033f33" name="LPC1766ENG"> \r
+<chip> \r
+<name>LPC1766ENG</name> \r
<family>LPC17xx</family> \r
<vendor>NXP (formerly Philips)</vendor> \r
<reset board="None" core="Real" sys="Real"/> \r
<peripheralInstance derived_from="MPU" determined="infoFile" id="MPU" location="0xE000ED90"/> \r
<peripheralInstance derived_from="LPC1x_WDT" determined="infoFile" id="WDT" location="0x40000000"/> \r
</chip> \r
-<processor><name gcc_name="cortex-m3">Cortex-M3</name> \r
+<processor> \r
+<name gcc_name="cortex-m3">Cortex-M3</name> \r
<family>Cortex-M</family> \r
</processor> \r
<link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/> \r
#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
\r
\r
+/* MAC address configuration. */\r
+#define configMAC_ADDR0 0x00\r
+#define configMAC_ADDR1 0x12\r
+#define configMAC_ADDR2 0x13\r
+#define configMAC_ADDR3 0x10\r
+#define configMAC_ADDR4 0x15\r
+#define configMAC_ADDR5 0x11\r
+\r
+/* IP address configuration. */\r
+#define configIP_ADDR0 192\r
+#define configIP_ADDR1 168\r
+#define configIP_ADDR2 0\r
+#define configIP_ADDR3 200 \r
+\r
+/* Netmask configuration. */\r
+#define configNET_MASK0 255\r
+#define configNET_MASK1 255\r
+#define configNET_MASK2 255\r
+#define configNET_MASK3 0\r
+\r
/* Use the system definition, if there is one */\r
#ifdef __NVIC_PRIO_BITS\r
#define configPRIO_BITS __NVIC_PRIO_BITS\r
# The demo app source files.\r
Demo_OBJS= $(OUTPUT_DIR)/main.o \\r
$(OUTPUT_DIR)/BlockQ.o \\r
- $(OUTPUT_DIR)/death.o \\r
$(OUTPUT_DIR)/integer.o \\r
$(OUTPUT_DIR)/PollQ.o \\r
$(OUTPUT_DIR)/semtest.o \\r
\r
/* Demo app includes. */\r
#include "BlockQ.h"\r
-#include "death.h"\r
#include "integer.h"\r
#include "blocktim.h"\r
#include "flash.h"\r
xLCDQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( xLCDMessage ) );\r
\r
/* Start the tasks defined within this file/specific to this demo. */\r
- xTaskCreate( vLCDTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
+ xTaskCreate( vLCDTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE * 2, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
\r
- /* The suicide tasks must be created last as they need to know how many\r
- tasks were running prior to their creation in order to ascertain whether\r
- or not the correct/expected number of tasks are running at any given time. */\r
- vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
-\r
/* Start the scheduler. */\r
vTaskStartScheduler();\r
\r
void vLCDTask( void *pvParameters )\r
{\r
xLCDMessage xMessage;\r
+char cIPAddr[ 17 ]; /* To fit max IP address length of xxx.xxx.xxx.xxx\0 */\r
\r
( void ) pvParameters;\r
\r
LCD_cls(); \r
LCD_gotoxy( 1, 1 );\r
LCD_puts( "www.FreeRTOS.org" );\r
+ LCD_gotoxy( 1, 2 );\r
+ sprintf( cIPAddr, "%d.%d.%d.%d", configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 );\r
+ LCD_puts( cIPAddr );\r
\r
for( ;; )\r
{\r
void write_PHY (int PhyReg, int Value)\r
{\r
unsigned int tout;\r
+ const unsigned int uiMaxTime = 10;\r
\r
MAC_MADR = DP83848C_DEF_ADR | PhyReg;\r
MAC_MWTD = Value;\r
\r
/* Wait utill operation completed */\r
tout = 0;\r
- for (tout = 0; tout < MII_WR_TOUT; tout++) {\r
+ for (tout = 0; tout < uiMaxTime; tout++) {\r
if ((MAC_MIND & MIND_BUSY) == 0) {\r
break;\r
}\r
+ vTaskDelay( 2 );\r
}\r
}\r
\r
unsigned short read_PHY (unsigned char PhyReg) \r
{\r
unsigned int tout;\r
+ const unsigned int uiMaxTime = 10;\r
\r
MAC_MADR = DP83848C_DEF_ADR | PhyReg;\r
MAC_MCMD = MCMD_READ;\r
\r
/* Wait until operation completed */\r
tout = 0;\r
- for (tout = 0; tout < MII_RD_TOUT; tout++) {\r
+ for (tout = 0; tout < uiMaxTime; tout++) {\r
if ((MAC_MIND & MIND_BUSY) == 0) {\r
break;\r
}\r
+ vTaskDelay( 2 );\r
}\r
MAC_MCMD = 0;\r
return (MAC_MRDD);\r
PINSEL3 = (PINSEL3 & ~0x0000000F) | 0x00000005;\r
\r
/* Power Up the EMAC controller. */\r
- PCONP |= 0x40000000;\r
- vTaskDelay( 1 );\r
+ PCONP |= PCONP_PCENET;\r
+ vTaskDelay( 2 );\r
\r
/* Reset all EMAC internal modules. */\r
MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;\r
- MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES;\r
+ MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;\r
\r
/* A short delay after reset. */\r
- vTaskDelay( 1 );\r
+ vTaskDelay( 2 );\r
\r
/* Initialize MAC control registers. */\r
MAC_MAC1 = MAC1_PASS_ALL;\r
\r
/* Reset Reduced MII Logic. */\r
MAC_SUPP = SUPP_RES_RMII;\r
+ vTaskDelay( 2 );\r
MAC_SUPP = 0;\r
\r
- /* Put the DP83848C in reset mode */\r
+ /* Put the PHY in reset mode */\r
write_PHY (PHY_REG_BMCR, 0x8000);\r
write_PHY (PHY_REG_BMCR, 0x8000);\r
\r
}\r
}\r
\r
+ /* Set the Ethernet MAC Address registers */\r
+ MAC_SA0 = (emacETHADDR0 << 8) | emacETHADDR1;\r
+ MAC_SA1 = (emacETHADDR2 << 8) | emacETHADDR3;\r
+ MAC_SA2 = (emacETHADDR4 << 8) | emacETHADDR5;\r
+\r
+ /* Initialize Tx and Rx DMA Descriptors */\r
+ rx_descr_init ();\r
+ tx_descr_init ();\r
+\r
+ /* Receive Broadcast and Perfect Match Packets */\r
+ MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;\r
+\r
+ /* Create the semaphore used ot wake the uIP task. */\r
+ vSemaphoreCreateBinary( xEMACSemaphore ); \r
+ \r
/* Check if this is a DP83848C PHY. */\r
id1 = read_PHY (PHY_REG_IDR1);\r
id2 = read_PHY (PHY_REG_IDR2);\r
MAC_SUPP = SUPP_SPEED;\r
}\r
\r
- /* Set the Ethernet MAC Address registers */\r
- MAC_SA0 = (emacETHADDR0 << 8) | emacETHADDR1;\r
- MAC_SA1 = (emacETHADDR2 << 8) | emacETHADDR3;\r
- MAC_SA2 = (emacETHADDR4 << 8) | emacETHADDR5;\r
-\r
- /* Initialize Tx and Rx DMA Descriptors */\r
- rx_descr_init ();\r
- tx_descr_init ();\r
-\r
- /* Receive Broadcast and Perfect Match Packets */\r
- MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;\r
-\r
- /* Create the semaphore used ot wake the uIP task. */\r
- vSemaphoreCreateBinary( xEMACSemaphore );\r
-\r
/* Reset all interrupts */\r
MAC_INTCLEAR = 0xFFFF;\r
\r
#include "core_cm3.h"\r
/*-----------------------------------------------------------*/\r
\r
-/* MAC address configuration. */\r
-#define uipMAC_ADDR0 0x00\r
-#define uipMAC_ADDR1 0x12\r
-#define uipMAC_ADDR2 0x13\r
-#define uipMAC_ADDR3 0x10\r
-#define uipMAC_ADDR4 0x15\r
-#define uipMAC_ADDR5 0x11\r
-\r
-/* IP address configuration. */\r
-#define uipIP_ADDR0 192\r
-#define uipIP_ADDR1 168\r
-#define uipIP_ADDR2 0\r
-#define uipIP_ADDR3 200 \r
-\r
/* How long to wait before attempting to connect the MAC again. */\r
#define uipINIT_WAIT 100\r
\r
timer_set( &periodic_timer, configTICK_RATE_HZ / 2 );\r
timer_set( &arp_timer, configTICK_RATE_HZ * 10 );\r
uip_init();\r
- uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 );\r
+ uip_ipaddr( xIPAddr, configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 );\r
uip_sethostaddr( xIPAddr );\r
+ uip_ipaddr( xIPAddr, configNET_MASK0, configNET_MASK1, configNET_MASK2, configNET_MASK3 );\r
+ uip_setnetmask( xIPAddr ); \r
httpd_init();\r
\r
/* Initialise the MAC. */\r
struct uip_eth_addr xAddr;\r
\r
/* Configure the MAC address in the uIP stack. */\r
- xAddr.addr[ 0 ] = uipMAC_ADDR0;\r
- xAddr.addr[ 1 ] = uipMAC_ADDR1;\r
- xAddr.addr[ 2 ] = uipMAC_ADDR2;\r
- xAddr.addr[ 3 ] = uipMAC_ADDR3;\r
- xAddr.addr[ 4 ] = uipMAC_ADDR4;\r
- xAddr.addr[ 5 ] = uipMAC_ADDR5;\r
+ xAddr.addr[ 0 ] = configMAC_ADDR0;\r
+ xAddr.addr[ 1 ] = configMAC_ADDR1;\r
+ xAddr.addr[ 2 ] = configMAC_ADDR2;\r
+ xAddr.addr[ 3 ] = configMAC_ADDR3;\r
+ xAddr.addr[ 4 ] = configMAC_ADDR4;\r
+ xAddr.addr[ 5 ] = configMAC_ADDR5;\r
uip_setethaddr( xAddr );\r
}\r
/*-----------------------------------------------------------*/\r
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