Added 6502 illegal instructions

git-svn-id: svn://svn.cc65.org/cc65/trunk@3022 b7a2c559-68d2-44c3-8de9-860c34a00d81

diff --git a/doc/ca65.sgml b/doc/ca65.sgml
index f39841406a0277fdeb347c35996b496f4a8418c6..13195bfc465b3e075dacca92b72360fa0b740b59 100644 (file)
--- a/doc/ca65.sgml
+++ b/doc/ca65.sgml
@@ -309,6 +309,8 @@ The assembler accepts
 <itemize>
 <item>all valid 6502 mnemonics when in 6502 mode (the default or after the
       <tt><ref id=".P02" name=".P02"></tt> command was given).
+<item>all valid 6502 mnemonics plus a set of illegal instructions when in
+      <ref id="6502X-mode" name="6502X mode">.
 <item>all valid 65SC02 mnemonics when in 65SC02 mode (after the
       <tt><ref id=".PSC02" name=".PSC02"></tt> command was given).
 <item>all valid 65C02 mnemonics when in 65C02 mode (after the
@@ -338,17 +340,36 @@ mnemonics:
        TSA is an alias for TSC
 </verb></tscreen>
 
-Evaluation of banked expressions in 65816 mode differs slightly from the
-official syntax:
 
-Instead of accepting a 24 bit address (something that is difficult for
-the assembler to determine and would have required one more special
-.import command), the bank and the absolute address in that bank are
-separated by a dot:
 
-<tscreen><verb>
-       jsl     3.$1234         ; Call subroutine at $1234 in bank 3
-</verb></tscreen>
+<sect1>6502X mode<label id="6502X-mode"><p>
+
+6502X mode is an extension to the normal 6502 mode. In this mode, several
+mnemomics for illegal instructions of the NMOS 6502 CPUs are accepted. Since
+these instructions are illegal, there are no official mnemonics for them. The
+unofficial ones are taken from <htmlurl
+url="http://oxyron.net/graham/opcodes02.html"
+name="http://oxyron.net/graham/opcodes02.html">. Please note that only the
+ones marked as "stable" are supported. The following table uses information
+from the mentioned web page, for more information, see there.
+
+<itemize>
+<item><tt>ALR: A:=(A and #{imm})*2;</tt>
+<item><tt>ANC: A:=A and #{imm};</tt> Generates opcode &dollar;0B.
+<item><tt>ARR: A:=(A and #{imm})/2;</tt>
+<item><tt>AXS: X:=A and X-#{imm};</tt>
+<item><tt>DCP: {adr}:={adr}-1; A-{adr};</tt>
+<item><tt>ISC: {adr}:={adr}+1; A:=A-{adr};</tt>
+<item><tt>LAS: A,X,S:={adr} and S;</tt>
+<item><tt>LAX: A,X:={adr};</tt>
+<item><tt>RLA: {adr}:={adr}rol; A:=A and {adr};</tt>
+<item><tt>RRA: {adr}:={adr}ror; A:=A adc {adr};</tt>
+<item><tt>SAX: {adr}:=A and X;</tt>
+<item><tt>SLO: {adr}:={adr}*2; A:=A or {adr};</tt>
+<item><tt>SRE: {adr}:={adr}/2; A:=A xor {adr};</tt>
+</itemize>
+
+
 
 <sect1>Number format<p>
 
@@ -2955,9 +2976,10 @@ Here's a list of all control commands and a description, what they do:
   Switch the CPU instruction set. The command is followed by a string that
   specifies the CPU. Possible values are those that can also be supplied to
   the <tt><ref id="option--cpu" name="--cpu"></tt> command line option,
-  namely: 6502, 65SC02, 65C02, 65816 and sunplus. Please note that support
-  for the sunplus CPU is not available in the freeware version, because the
-  instruction set of the sunplus CPU is "proprietary and confidential".
+  namely: 6502, 6502X, 65SC02, 65C02, 65816 and sunplus. Please note that 
+  support for the sunplus CPU is not available in the freeware version,
+  because the instruction set of the sunplus CPU is "proprietary and
+  confidential".
 
   See: <tt><ref id=".CPU" name=".CPU"></tt>,
        <tt><ref id=".IFP02" name=".IFP02"></tt>,

diff --git a/src/ca65/instr.c b/src/ca65/instr.c
index 0ed9a0f7be1ee4fbc38cf7560d9f7c72a57c615d..33f364c1a8d5f9df7becf1414b390863a083092c 100644 (file)
--- a/src/ca65/instr.c
+++ b/src/ca65/instr.c
@@ -147,7 +147,7 @@ static const struct {
 };
 
 /* Instruction table for the 6502 with illegal instructions */
-#define INS_COUNT_6502X                57
+#define INS_COUNT_6502X                70
 static const struct {
     unsigned Count;
     InsDesc  Ins[INS_COUNT_6502X];
@@ -155,8 +155,12 @@ static const struct {
     INS_COUNT_6502X,
     {
                { "ADC",  0x080A26C, 0x60, 0, PutAll },
+        { "ALR",  0x0800000, 0x4B, 0, PutAll },         /* X */
+        { "ANC",  0x0800000, 0x0B, 0, PutAll },         /* X */
                { "AND",  0x080A26C, 0x20, 0, PutAll },
+        { "ARR",  0x0800000, 0x6B, 0, PutAll },         /* X */
                { "ASL",  0x000006e, 0x02, 1, PutAll },
+        { "AXS",  0x0800000, 0xCB, 0, PutAll },         /* X */
                { "BCC",  0x0020000, 0x90, 0, PutPCRel8 },
                { "BCS",  0x0020000, 0xb0, 0, PutPCRel8 },
                { "BEQ",  0x0020000, 0xf0, 0, PutPCRel8 },
@@ -174,6 +178,7 @@ static const struct {
                { "CMP",  0x080A26C, 0xc0, 0, PutAll },
                { "CPX",  0x080000C, 0xe0, 1, PutAll },
                { "CPY",  0x080000C, 0xc0, 1, PutAll },
+        { "DCP",  0x000A26C, 0xC3, 0, PutAll },         /* X */
                { "DEC",  0x000006C, 0x00, 3, PutAll },
                { "DEX",  0x0000001, 0xca, 0, PutAll },
                { "DEY",  0x0000001, 0x88, 0, PutAll },
@@ -181,9 +186,12 @@ static const struct {
                { "INC",  0x000006c, 0x00, 4, PutAll },
                { "INX",  0x0000001, 0xe8, 0, PutAll },
                { "INY",  0x0000001, 0xc8, 0, PutAll },
+        { "ISC",  0x000A26C, 0xE3, 0, PutAll },         /* X */
         { "JAM",  0x0000001, 0x02, 0, PutAll },         /* X */
                { "JMP",  0x0000808, 0x4c, 6, PutJMP },
                { "JSR",  0x0000008, 0x20, 7, PutAll },
+        { "LAS",  0x0000200, 0xBB, 0, PutAll },         /* X */
+        { "LAX",  0x000A30C, 0xA3, 1, PutAll },         /* X */
                { "LDA",  0x080A26C, 0xa0, 0, PutAll },
                { "LDX",  0x080030C, 0xa2, 1, PutAll },
                { "LDY",  0x080006C, 0xa0, 1, PutAll },
@@ -194,14 +202,19 @@ static const struct {
                { "PHP",  0x0000001, 0x08, 0, PutAll },
                { "PLA",  0x0000001, 0x68, 0, PutAll },
                { "PLP",  0x0000001, 0x28, 0, PutAll },
+        { "RLA",  0x000A26C, 0x23, 0, PutAll },         /* X */
                { "ROL",  0x000006F, 0x22, 1, PutAll },
                { "ROR",  0x000006F, 0x62, 1, PutAll },
+        { "RRA",  0x000A26C, 0x63, 0, PutAll },         /* X */
                { "RTI",  0x0000001, 0x40, 0, PutAll },
                { "RTS",  0x0000001, 0x60, 0, PutAll },
+        { "SAX",  0x000810C, 0x83, 1, PutAll },         /* X */
                { "SBC",  0x080A26C, 0xe0, 0, PutAll },
                { "SEC",  0x0000001, 0x38, 0, PutAll },
                { "SED",  0x0000001, 0xf8, 0, PutAll },
                { "SEI",  0x0000001, 0x78, 0, PutAll },
+        { "SLO",  0x000A26C, 0x03, 0, PutAll },         /* X */
+        { "SRE",  0x000A26C, 0x43, 0, PutAll },         /* X */
                { "STA",  0x000A26C, 0x80, 0, PutAll },
                { "STX",  0x000010c, 0x82, 1, PutAll },
                { "STY",  0x000002c, 0x80, 1, PutAll },
@@ -406,7 +419,7 @@ static const struct {
     unsigned Count;
     InsDesc  Ins[INS_COUNT_65816];
 } InsTab65816 = {
-    INS_COUNT_65816,
+    INS_COUNT_65816,             
     {
                { "ADC",  0x0b8f6fc, 0x60, 0, PutAll },
                { "AND",  0x0b8f6fc, 0x20, 0, PutAll },
@@ -544,7 +557,7 @@ unsigned char EATab [9][AMI_COUNT] = {
     },
     {   /* Table 1 */
        0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
-       0x14, 0x1C, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00,
+       0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                0x00
     },
@@ -552,7 +565,7 @@ unsigned char EATab [9][AMI_COUNT] = {
        0x00, 0x00, 0x24, 0x2C, 0x0F, 0x34, 0x3C, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00,
-               0x00                        
+               0x00
     },
     {   /* Table 3 */
        0x3A, 0x3A, 0xC6, 0xCE, 0x00, 0xD6, 0xDE, 0x00,