Add barrier instructions to the GCC CM3 ports.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1857 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
index afc0cfa12f7a51a5a0ff8c5453868d0bb5a26ddb..4c2b223dca5b9a94510afb15812d36ea09e58eca 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
@@ -56,19 +56,19 @@
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 \r
@@ -210,10 +210,15 @@ void vPortEndScheduler( void )
 }\r
 /*-----------------------------------------------------------*/\r
 \r
-void vPortYieldFromISR( void )\r
+void vPortYield( void )\r
 {\r
        /* Set a PendSV to request a context switch. */\r
        *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+\r
+       /* Barriers are normally not required but do ensure the code is completely\r
+       within the specified behaviour for the architecture. */\r
+       __asm volatile( "dsb" );\r
+       __asm volatile( "isb" );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -221,6 +226,8 @@ void vPortEnterCritical( void )
 {\r
     portDISABLE_INTERRUPTS();\r
     uxCriticalNesting++;\r
+       __asm volatile( "dsb" );\r
+       __asm volatile( "isb" );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
index 18b9b8b8c357f93c0710075f8559c8ef751cd54b..65457bc6da6610209f384b6c6071c8c5b1f502d4 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
@@ -116,9 +116,11 @@ extern "C" {
 \r
 \r
 /* Scheduler utilities. */\r
-extern void vPortYieldFromISR( void );\r
-#define portYIELD()                                                                    vPortYieldFromISR()\r
-#define portEND_SWITCHING_ISR( xSwitchRequired )       if( xSwitchRequired ) vPortYieldFromISR()\r
+extern void vPortYield( void );\r
+#define portNVIC_INT_CTRL_REG          ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT         ( 1UL << 28UL )\r
+#define portYIELD()                                    vPortYield()\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
 /*-----------------------------------------------------------*/\r
 \r
 \r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
index f4090d74a198073c6c52ca129049948fb9ca436c..ad82773396561d84a943a0190d5ca81c72e25704 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
@@ -255,7 +255,7 @@ void vPortEndScheduler( void )
 }\r
 /*-----------------------------------------------------------*/\r
 \r
-void vPortYieldFromISR( void )\r
+void vPortYield( void )\r
 {\r
        /* Set a PendSV to request a context switch. */\r
        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
index d436e732ac18bda3c1e1a82f1b04b956fc053e20..552b3396c6251eb7d6079e9ceeeb56b4f03cf46a 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
@@ -116,9 +116,11 @@ extern "C" {
 \r
 \r
 /* Scheduler utilities. */\r
-extern void vPortYieldFromISR( void );\r
-#define portYIELD()                                    vPortYieldFromISR()\r
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()\r
+extern void vPortYield( void );\r
+#define portNVIC_INT_CTRL_REG          ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT         ( 1UL << 28UL )\r
+#define portYIELD()                                    vPortYield()\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
 /*-----------------------------------------------------------*/\r
 \r
 /* Critical section management. */\r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
index 913b03fcae204dae8ac4e05856c1fb5054401800..9b564e9a57ef27b68acb9787adbda7e3e601b718 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
@@ -56,19 +56,19 @@
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 \r
@@ -290,6 +290,13 @@ unsigned char ucSVCNumber;
                                                                                        break;\r
 \r
                case portSVC_YIELD                              :       *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
+                                                                                       /* Barriers are normally not required\r
+                                                                                       but do ensure the code is completely\r
+                                                                                       within the specified behaviour for the\r
+                                                                                       architecture. */\r
+                                                                                       __asm volatile( "dsb" );\r
+                                                                                       __asm volatile( "isb" );\r
+\r
                                                                                        break;\r
 \r
                case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
index 213b712778dd98b76f8072310aad8b9538395af5..0b06b64cf70c7c92952691e7ca0b64664b4f27a7 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
@@ -56,19 +56,19 @@
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 \r
@@ -92,14 +92,12 @@
 #define portNVIC_SYSTICK_CTRL_REG                      ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
 #define portNVIC_SYSTICK_LOAD_REG                      ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
 #define portNVIC_SYSTICK_CURRENT_VALUE_REG     ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
-#define portNVIC_INT_CTRL_REG                          ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
 #define portNVIC_SYSPRI2_REG                           ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
 /* ...then bits in the registers. */\r
 #define portNVIC_SYSTICK_CLK_BIT                       ( 1UL << 2UL )\r
 #define portNVIC_SYSTICK_INT_BIT                       ( 1UL << 1UL )\r
 #define portNVIC_SYSTICK_ENABLE_BIT                    ( 1UL << 0UL )\r
 #define portNVIC_SYSTICK_COUNT_FLAG_BIT                ( 1UL << 16UL )\r
-#define portNVIC_PENDSVSET_BIT                         ( 1UL << 28UL )\r
 #define portNVIC_PENDSVCLEAR_BIT                       ( 1UL << 27UL )\r
 #define portNVIC_PEND_SYSTICK_CLEAR_BIT                ( 1UL << 25UL )\r
 \r
@@ -279,10 +277,15 @@ void vPortEndScheduler( void )
 }\r
 /*-----------------------------------------------------------*/\r
 \r
-void vPortYieldFromISR( void )\r
+void vPortYield( void )\r
 {\r
        /* Set a PendSV to request a context switch. */\r
        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+\r
+       /* Barriers are normally not required but do ensure the code is completely\r
+       within the specified behaviour for the architecture. */\r
+       __asm volatile( "dsb" );\r
+       __asm volatile( "isb" );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -290,6 +293,8 @@ void vPortEnterCritical( void )
 {\r
        portDISABLE_INTERRUPTS();\r
        uxCriticalNesting++;\r
+       __asm volatile( "dsb" );\r
+       __asm volatile( "isb" );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -473,6 +478,8 @@ void xPortSysTickHandler( void )
                        if( xModifiableIdleTime > 0 )\r
                        {\r
                                __asm volatile( "wfi" );\r
+                               __asm volatile( "dsb" );\r
+                               __asm volatile( "isb" );\r
                        }\r
                        configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 \r

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
index e99354d6f041ba016967241218e44cdcc8a700e1..e4dafe1de40d548db6aacc2a74149327a4a17275 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
@@ -56,19 +56,19 @@
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 \r
@@ -81,7 +81,7 @@ extern "C" {
 #endif\r
 \r
 /*-----------------------------------------------------------\r
- * Port specific definitions.  \r
+ * Port specific definitions.\r
  *\r
  * The settings in this file configure FreeRTOS correctly for the\r
  * given hardware and compiler.\r
@@ -106,19 +106,21 @@ extern "C" {
        typedef unsigned portLONG portTickType;\r
        #define portMAX_DELAY ( portTickType ) 0xffffffff\r
 #endif\r
-/*-----------------------------------------------------------*/        \r
+/*-----------------------------------------------------------*/\r
 \r
 /* Architecture specifics. */\r
 #define portSTACK_GROWTH                       ( -1 )\r
-#define portTICK_RATE_MS                       ( ( portTickType ) 1000 / configTICK_RATE_HZ )          \r
+#define portTICK_RATE_MS                       ( ( portTickType ) 1000 / configTICK_RATE_HZ )\r
 #define portBYTE_ALIGNMENT                     8\r
-/*-----------------------------------------------------------*/        \r
+/*-----------------------------------------------------------*/\r
 \r
 \r
 /* Scheduler utilities. */\r
-extern void vPortYieldFromISR( void );\r
-#define portYIELD()                                    vPortYieldFromISR()\r
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()\r
+extern void vPortYield( void );\r
+#define portNVIC_INT_CTRL_REG          ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT         ( 1UL << 28UL )\r
+#define portYIELD()                                    vPortYield()\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
 /*-----------------------------------------------------------*/\r
 \r
 /* Critical section management. */\r
@@ -133,7 +135,7 @@ extern void vPortClearInterruptMask( unsigned long ulNewMaskValue );
 #define portENTER_CRITICAL()                                   vPortEnterCritical()\r
 #define portEXIT_CRITICAL()                                            vPortExitCritical()\r
 \r
-/* There are an uneven number of items on the initial stack, so \r
+/* There are an uneven number of items on the initial stack, so\r
 portALIGNMENT_ASSERT_pxCurrentTCB() will trigger false positive asserts. */\r
 #define portALIGNMENT_ASSERT_pxCurrentTCB ( void )\r
 \r