-/******************************************************************************\r
- * @file: LPC17xx.h\r
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for \r
- * NXP LPC17xx Device Series \r
- * @version: V1.1\r
- * @date: 14th May 2009\r
- *----------------------------------------------------------------------------\r
- *\r
- * Copyright (C) 2008 ARM Limited. All rights reserved.\r
- *\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M3 \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-\r
-#ifndef __LPC17xx_H__\r
-#define __LPC17xx_H__\r
-\r
-/*\r
- * ==========================================================================\r
- * ---------- Interrupt Number Definition -----------------------------------\r
- * ==========================================================================\r
- */\r
+#ifndef __LPC17xx_H\r
+#define __LPC17xx_H\r
+\r
+#include "CortexM3.h"\r
+\r
+\r
+/* System Control Block (SCB) includes:\r
+ Flash Accelerator Module, Clocking and Power Control, External Interrupts,\r
+ Reset, System Control and Status\r
+*/\r
+#define SCB_BASE_ADDR 0x400FC000\r
+\r
+/* Flash Accelerator Module */\r
+#define FLASHCTRL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000))\r
+#define FLASHTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004))\r
+\r
+/* Phase Locked Loop (Main PLL0) */\r
+#define PLL0CON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080))\r
+#define PLL0CFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084))\r
+#define PLL0STAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088))\r
+#define PLL0FEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C))\r
+\r
+/* Phase Locked Loop (USB PLL1) */\r
+#define PLL1CON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A0))\r
+#define PLL1CFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A4))\r
+#define PLL1STAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A8))\r
+#define PLL1FEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0AC))\r
+\r
+/* Power Control */\r
+#define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0))\r
+#define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4))\r
+\r
+/* Clock Selection and Dividers */\r
+#define CCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104))\r
+#define USBCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108))\r
+#define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C))\r
+#define IRCTRIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A4))\r
+#define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8))\r
+#define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC))\r
+ \r
+/* External Interrupts */\r
+#define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140))\r
+#define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148))\r
+#define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C))\r
+\r
+/* Reset */\r
+#define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))\r
+\r
+/* System Controls and Status */\r
+#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) \r
+\r
+\r
+/* Pin Connect Block */\r
+#define PINCON_BASE_ADDR 0x4002C000\r
+#define PINSEL0 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x00))\r
+#define PINSEL1 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x04))\r
+#define PINSEL2 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x08))\r
+#define PINSEL3 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x0C))\r
+#define PINSEL4 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x10))\r
+#define PINSEL5 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x14))\r
+#define PINSEL6 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x18))\r
+#define PINSEL7 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x1C))\r
+#define PINSEL8 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x20))\r
+#define PINSEL9 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x24))\r
+#define PINSEL10 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x28))\r
+\r
+#define PINMODE0 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x40))\r
+#define PINMODE1 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x44))\r
+#define PINMODE2 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x48))\r
+#define PINMODE3 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x4C))\r
+#define PINMODE4 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x50))\r
+#define PINMODE5 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x54))\r
+#define PINMODE6 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x58))\r
+#define PINMODE7 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x5C))\r
+#define PINMODE8 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x60))\r
+#define PINMODE9 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x64))\r
+#define PINMODE_OD0 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x68))\r
+#define PINMODE_OD1 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x6C))\r
+#define PINMODE_OD2 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x70))\r
+#define PINMODE_OD3 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x74))\r
+#define PINMODE_OD4 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x78))\r
+\r
+\r
+/* General Purpose Input/Output (GPIO) - Fast GPIO */\r
+// #define GPIO_BASE_ADDR 0x50014000 /* For the first silicon v0.00 */\r
+#define GPIO_BASE_ADDR 0x2009C000 /* For silicon v0.01 or newer */\r
+#define FIO0DIR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00)) \r
+#define FIO0MASK (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))\r
+#define FIO0PIN (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))\r
+#define FIO0SET (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))\r
+#define FIO0CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))\r
+\r
+#define FIO1DIR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x20)) \r
+#define FIO1MASK (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x30))\r
+#define FIO1PIN (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x34))\r
+#define FIO1SET (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x38))\r
+#define FIO1CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x3C))\r
+\r
+#define FIO2DIR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x40)) \r
+#define FIO2MASK (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x50))\r
+#define FIO2PIN (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x54))\r
+#define FIO2SET (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x58))\r
+#define FIO2CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x5C))\r
+\r
+#define FIO3DIR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x60)) \r
+#define FIO3MASK (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x70))\r
+#define FIO3PIN (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x74))\r
+#define FIO3SET (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x78))\r
+#define FIO3CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x7C))\r
+\r
+#define FIO4DIR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80)) \r
+#define FIO4MASK (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90))\r
+#define FIO4PIN (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94))\r
+#define FIO4SET (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x98))\r
+#define FIO4CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x9C))\r
+\r
+/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */\r
+#define FIO0DIR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x00)) \r
+#define FIO1DIR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x20)) \r
+#define FIO2DIR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x40)) \r
+#define FIO3DIR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x60)) \r
+#define FIO4DIR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x80)) \r
+\r
+#define FIO0DIR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x01)) \r
+#define FIO1DIR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x21)) \r
+#define FIO2DIR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x41)) \r
+#define FIO3DIR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x61)) \r
+#define FIO4DIR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x81)) \r
+\r
+#define FIO0DIR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x02)) \r
+#define FIO1DIR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x22)) \r
+#define FIO2DIR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x42)) \r
+#define FIO3DIR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x62)) \r
+#define FIO4DIR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x82)) \r
+\r
+#define FIO0DIR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x03)) \r
+#define FIO1DIR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x23)) \r
+#define FIO2DIR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x43)) \r
+#define FIO3DIR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x63)) \r
+#define FIO4DIR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x83)) \r
+\r
+#define FIO0DIRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x00)) \r
+#define FIO1DIRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x20)) \r
+#define FIO2DIRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x40)) \r
+#define FIO3DIRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x60)) \r
+#define FIO4DIRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x80)) \r
+\r
+#define FIO0DIRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x02)) \r
+#define FIO1DIRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x22)) \r
+#define FIO2DIRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x42)) \r
+#define FIO3DIRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x62)) \r
+#define FIO4DIRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x82)) \r
+\r
+#define FIO0MASK0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x10)) \r
+#define FIO1MASK0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x30)) \r
+#define FIO2MASK0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x40)) \r
+#define FIO3MASK0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x50)) \r
+#define FIO4MASK0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x90)) \r
+\r
+#define FIO0MASK1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x11)) \r
+#define FIO1MASK1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x31)) \r
+#define FIO2MASK1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x41)) \r
+#define FIO3MASK1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x51)) \r
+#define FIO4MASK1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x91)) \r
+\r
+#define FIO0MASK2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x12)) \r
+#define FIO1MASK2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x32)) \r
+#define FIO2MASK2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x42)) \r
+#define FIO3MASK2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x52)) \r
+#define FIO4MASK2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x92)) \r
+\r
+#define FIO0MASK3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x13)) \r
+#define FIO1MASK3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x33)) \r
+#define FIO2MASK3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x43)) \r
+#define FIO3MASK3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x53)) \r
+#define FIO4MASK3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x93)) \r
+\r
+#define FIO0MASKL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x10)) \r
+#define FIO1MASKL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x30)) \r
+#define FIO2MASKL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x40)) \r
+#define FIO3MASKL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x50)) \r
+#define FIO4MASKL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x90)) \r
+\r
+#define FIO0MASKU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x12)) \r
+#define FIO1MASKU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x32)) \r
+#define FIO2MASKU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x42)) \r
+#define FIO3MASKU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x52)) \r
+#define FIO4MASKU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x92)) \r
+\r
+#define FIO0PIN0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x14)) \r
+#define FIO1PIN0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x34)) \r
+#define FIO2PIN0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x44)) \r
+#define FIO3PIN0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x54)) \r
+#define FIO4PIN0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x94)) \r
+\r
+#define FIO0PIN1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x15)) \r
+#define FIO1PIN1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x35)) \r
+#define FIO2PIN1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x45)) \r
+#define FIO3PIN1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x55)) \r
+#define FIO4PIN1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x95)) \r
+\r
+#define FIO0PIN2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x16)) \r
+#define FIO1PIN2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x36)) \r
+#define FIO2PIN2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x46)) \r
+#define FIO3PIN2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x56)) \r
+#define FIO4PIN2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x96)) \r
+\r
+#define FIO0PIN3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x17)) \r
+#define FIO1PIN3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x37)) \r
+#define FIO2PIN3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x47)) \r
+#define FIO3PIN3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x57)) \r
+#define FIO4PIN3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x97)) \r
+\r
+#define FIO0PINL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x14)) \r
+#define FIO1PINL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x34)) \r
+#define FIO2PINL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x44)) \r
+#define FIO3PINL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x54)) \r
+#define FIO4PINL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x94)) \r
+\r
+#define FIO0PINU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x16)) \r
+#define FIO1PINU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x36)) \r
+#define FIO2PINU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x46)) \r
+#define FIO3PINU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x56)) \r
+#define FIO4PINU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x96)) \r
+\r
+#define FIO0SET0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x18)) \r
+#define FIO1SET0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x38)) \r
+#define FIO2SET0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x48)) \r
+#define FIO3SET0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x58)) \r
+#define FIO4SET0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x98)) \r
+\r
+#define FIO0SET1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x19)) \r
+#define FIO1SET1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x39)) \r
+#define FIO2SET1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x49)) \r
+#define FIO3SET1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x59)) \r
+#define FIO4SET1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x99)) \r
+\r
+#define FIO0SET2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1A)) \r
+#define FIO1SET2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3A)) \r
+#define FIO2SET2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4A)) \r
+#define FIO3SET2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5A)) \r
+#define FIO4SET2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9A)) \r
+\r
+#define FIO0SET3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1B)) \r
+#define FIO1SET3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3B)) \r
+#define FIO2SET3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4B)) \r
+#define FIO3SET3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5B)) \r
+#define FIO4SET3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9B)) \r
+\r
+#define FIO0SETL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x18)) \r
+#define FIO1SETL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x38)) \r
+#define FIO2SETL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x48)) \r
+#define FIO3SETL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x58)) \r
+#define FIO4SETL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x98)) \r
+\r
+#define FIO0SETU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x1A)) \r
+#define FIO1SETU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x3A)) \r
+#define FIO2SETU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x4A)) \r
+#define FIO3SETU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x5A)) \r
+#define FIO4SETU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x9A)) \r
+\r
+#define FIO0CLR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1C)) \r
+#define FIO1CLR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3C)) \r
+#define FIO2CLR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4C)) \r
+#define FIO3CLR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5C)) \r
+#define FIO4CLR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9C)) \r
+\r
+#define FIO0CLR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1D)) \r
+#define FIO1CLR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3D)) \r
+#define FIO2CLR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4D)) \r
+#define FIO3CLR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5D)) \r
+#define FIO4CLR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9D)) \r
+\r
+#define FIO0CLR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1E)) \r
+#define FIO1CLR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3E)) \r
+#define FIO2CLR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4E)) \r
+#define FIO3CLR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5E)) \r
+#define FIO4CLR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9E)) \r
+\r
+#define FIO0CLR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1F)) \r
+#define FIO1CLR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3F)) \r
+#define FIO2CLR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4F)) \r
+#define FIO3CLR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5F)) \r
+#define FIO4CLR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9F)) \r
+\r
+#define FIO0CLRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x1C)) \r
+#define FIO1CLRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x3C)) \r
+#define FIO2CLRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x4C)) \r
+#define FIO3CLRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x5C)) \r
+#define FIO4CLRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x9C)) \r
+\r
+#define FIO0CLRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x1E)) \r
+#define FIO1CLRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x3E)) \r
+#define FIO2CLRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x4E)) \r
+#define FIO3CLRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x5E)) \r
+#define FIO4CLRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x9E)) \r
+\r
+/* GPIO Interrupt Registers */\r
+#define GPIO_INT_BASE_ADDR 0x40028000\r
+#define IO0IntEnR (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x90)) \r
+#define IO0IntEnF (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x94))\r
+#define IO0IntStatR (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x84))\r
+#define IO0IntStatF (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x88))\r
+#define IO0IntClr (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x8C))\r
+\r
+#define IO2IntEnR (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0xB0)) \r
+#define IO2IntEnF (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0xB4))\r
+#define IO2IntStatR (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0xA4))\r
+#define IO2IntStatF (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0xA8))\r
+#define IO2IntClr (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0xAC))\r
+\r
+#define IOIntStatus (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x80))\r
+\r
+\r
+/* Timer 0 */\r
+#define TMR0_BASE_ADDR 0x40004000\r
+#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))\r
+#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))\r
+#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))\r
+#define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))\r
+#define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))\r
+#define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))\r
+#define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))\r
+#define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C))\r
+#define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20))\r
+#define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24))\r
+#define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28))\r
+#define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C))\r
+#define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30))\r
+#define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34))\r
+#define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38))\r
+#define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C))\r
+#define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))\r
+\r
+/* Timer 1 */\r
+#define TMR1_BASE_ADDR 0x40008000\r
+#define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))\r
+#define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))\r
+#define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))\r
+#define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C))\r
+#define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10))\r
+#define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14))\r
+#define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18))\r
+#define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C))\r
+#define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20))\r
+#define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24))\r
+#define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28))\r
+#define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C))\r
+#define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30))\r
+#define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34))\r
+#define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38))\r
+#define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C))\r
+#define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))\r
+\r
+/* Timer 2 */\r
+#define TMR2_BASE_ADDR 0x40090000\r
+#define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00))\r
+#define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04))\r
+#define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08))\r
+#define T2PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C))\r
+#define T2PC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10))\r
+#define T2MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14))\r
+#define T2MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18))\r
+#define T2MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C))\r
+#define T2MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20))\r
+#define T2MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24))\r
+#define T2CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28))\r
+#define T2CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C))\r
+#define T2CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30))\r
+#define T2CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34))\r
+#define T2CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38))\r
+#define T2EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C))\r
+#define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70))\r
+\r
+/* Timer 3 */\r
+#define TMR3_BASE_ADDR 0x40094000\r
+#define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00))\r
+#define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04))\r
+#define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08))\r
+#define T3PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C))\r
+#define T3PC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10))\r
+#define T3MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14))\r
+#define T3MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18))\r
+#define T3MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C))\r
+#define T3MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20))\r
+#define T3MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24))\r
+#define T3CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28))\r
+#define T3CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C))\r
+#define T3CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30))\r
+#define T3CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34))\r
+#define T3CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38))\r
+#define T3EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C))\r
+#define T3CTCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70))\r
+\r
+\r
+/* Pulse Width Modulator (PWM) */\r
+#define PWM1_BASE_ADDR 0x40018000\r
+#define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00))\r
+#define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04))\r
+#define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08))\r
+#define PWM1PR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C))\r
+#define PWM1PC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10))\r
+#define PWM1MCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14))\r
+#define PWM1MR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18))\r
+#define PWM1MR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C))\r
+#define PWM1MR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20))\r
+#define PWM1MR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24))\r
+#define PWM1CCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28))\r
+#define PWM1CR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C))\r
+#define PWM1CR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30))\r
+#define PWM1CR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34))\r
+#define PWM1CR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38))\r
+#define PWM1MR4 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40))\r
+#define PWM1MR5 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44))\r
+#define PWM1MR6 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48))\r
+#define PWM1PCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C))\r
+#define PWM1LER (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50))\r
+#define PWM1CTCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70))\r
+\r
+\r
+/* Universal Asynchronous Receiver Transmitter 0 (UART0) */\r
+#define UART0_BASE_ADDR 0x4000C000\r
+#define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))\r
+#define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))\r
+#define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))\r
+#define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))\r
+#define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))\r
+#define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))\r
+#define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))\r
+#define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C))\r
+#define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14))\r
+#define U0SCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C))\r
+#define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20))\r
+#define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28))\r
+#define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30))\r
+#define U0RS485CTRL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x4C))\r
+#define U0ADRMATCH (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x50))\r
+\r
+/* Universal Asynchronous Receiver Transmitter 1 (UART1) */\r
+#define UART1_BASE_ADDR 0x40010000\r
+#define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))\r
+#define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))\r
+#define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))\r
+#define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))\r
+#define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))\r
+#define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))\r
+#define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))\r
+#define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C))\r
+#define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10))\r
+#define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14))\r
+#define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18))\r
+#define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C))\r
+#define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20))\r
+#define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28))\r
+#define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30))\r
+#define U1RS485CTRL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x4C))\r
+#define U1ADRMATCH (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x50))\r
+#define U1RS485DLY (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x54))\r
+\r
+/* Universal Asynchronous Receiver Transmitter 2 (UART2) */\r
+#define UART2_BASE_ADDR 0x40098000\r
+#define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))\r
+#define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))\r
+#define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))\r
+#define U2DLM (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))\r
+#define U2IER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))\r
+#define U2IIR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))\r
+#define U2FCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))\r
+#define U2LCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C))\r
+#define U2LSR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14))\r
+#define U2SCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C))\r
+#define U2ACR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20))\r
+#define U2FDR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28))\r
+#define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30))\r
+#define U2RS485CTRL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x4C))\r
+#define U2ADRMATCH (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x50))\r
+\r
+/* Universal Asynchronous Receiver Transmitter 3 (UART3) */\r
+#define UART3_BASE_ADDR 0x4009C000\r
+#define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))\r
+#define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))\r
+#define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))\r
+#define U3DLM (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))\r
+#define U3IER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))\r
+#define U3IIR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))\r
+#define U3FCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))\r
+#define U3LCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C))\r
+#define U3LSR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14))\r
+#define U3SCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C))\r
+#define U3ACR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20))\r
+#define U3ICR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24))\r
+#define U3FDR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28))\r
+#define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30))\r
+#define U3RS485CTRL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x4C))\r
+#define U3ADRMATCH (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x50))\r
+\r
+\r
+/* SPI0 (Serial Peripheral Interface 0) */\r
+#define SPI0_BASE_ADDR 0x40020000\r
+#define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00))\r
+#define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04))\r
+#define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08))\r
+#define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C))\r
+#define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C))\r
+\r
+/* SSP0 Controller */\r
+#define SSP0_BASE_ADDR 0x40088000\r
+#define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00))\r
+#define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04))\r
+#define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08))\r
+#define SSP0SR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C))\r
+#define SSP0CPSR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10))\r
+#define SSP0IMSC (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14))\r
+#define SSP0RIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18))\r
+#define SSP0MIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C))\r
+#define SSP0ICR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20))\r
+#define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24))\r
+\r
+/* SSP1 Controller */\r
+#define SSP1_BASE_ADDR 0x40030000\r
+#define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00))\r
+#define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04))\r
+#define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08))\r
+#define SSP1SR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C))\r
+#define SSP1CPSR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10))\r
+#define SSP1IMSC (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14))\r
+#define SSP1RIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18))\r
+#define SSP1MIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C))\r
+#define SSP1ICR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20))\r
+#define SSP1DMACR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24))\r
+\r
+\r
+/* I2C Interface 0 */\r
+#define I2C0_BASE_ADDR 0x4001C000\r
+#define I2C0CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))\r
+#define I2C0STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))\r
+#define I2C0DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))\r
+#define I2C0ADR0 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C))\r
+#define I2C0SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10))\r
+#define I2C0SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14))\r
+#define I2C0CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18))\r
+#define I2C0MMCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x1C))\r
+#define I2C0ADR1 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x20))\r
+#define I2C0ADR2 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x24))\r
+#define I2C0ADR3 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x28))\r
+#define I2C0DATBUFFER (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x2C))\r
+#define I2C0MASK0 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x30))\r
+#define I2C0MASK1 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x34))\r
+#define I2C0MASK2 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x38))\r
+#define I2C0MASK3 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x3C))\r
+\r
+/* I2C Interface 1 */\r
+#define I2C1_BASE_ADDR 0x4005C000\r
+#define I2C1CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))\r
+#define I2C1STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))\r
+#define I2C1DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))\r
+#define I2C1ADR0 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C))\r
+#define I2C1SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10))\r
+#define I2C1SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14))\r
+#define I2C1CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18))\r
+#define I2C1MMCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x1C))\r
+#define I2C1ADR1 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x20))\r
+#define I2C1ADR2 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x24))\r
+#define I2C1ADR3 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x28))\r
+#define I2C1DATBUFFER (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x2C))\r
+#define I2C1MASK0 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x30))\r
+#define I2C1MASK1 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x34))\r
+#define I2C1MASK2 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x38))\r
+#define I2C1MASK3 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x3C))\r
+\r
+/* I2C Interface 2 */\r
+#define I2C2_BASE_ADDR 0x400A0000\r
+#define I2C2CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00))\r
+#define I2C2STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04))\r
+#define I2C2DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08))\r
+#define I2C2ADR0 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C))\r
+#define I2C2SCLH (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10))\r
+#define I2C2SCLL (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14))\r
+#define I2C2CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18))\r
+#define I2C2MMCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x1C))\r
+#define I2C2ADR1 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x20))\r
+#define I2C2ADR2 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x24))\r
+#define I2C2ADR3 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x28))\r
+#define I2C2DATBUFFER (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x2C))\r
+#define I2C2MASK0 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x30))\r
+#define I2C2MASK1 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x34))\r
+#define I2C2MASK2 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x38))\r
+#define I2C2MASK3 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x3C))\r
+\r
+\r
+/* I2S Interface Controller (I2S) */\r
+#define I2S_BASE_ADDR 0x400A8000\r
+#define I2SDAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00))\r
+#define I2SDAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04))\r
+#define I2STXFIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08))\r
+#define I2SRXFIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C))\r
+#define I2SSTATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10))\r
+#define I2SDMA1 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14))\r
+#define I2SDMA2 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18))\r
+#define I2SIRQ (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C))\r
+#define I2STXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20))\r
+#define I2SRXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24))\r
+#define I2STXBITRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x28))\r
+#define I2SRXBITRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x2C))\r
+#define I2STXMODE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x30))\r
+#define I2SRXMODE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x34))\r
+\r
+\r
+/* Repetitive Interrupt Timer (RIT) */\r
+#define RIT_BASE_ADDR 0x400B4000\r
+#define RICOMPVAL (*(volatile unsigned long *)(RIT_BASE_ADDR + 0x00))\r
+#define RIMASK (*(volatile unsigned long *)(RIT_BASE_ADDR + 0x04))\r
+#define RICTRL (*(volatile unsigned long *)(RIT_BASE_ADDR + 0x08))\r
+#define RICOUNTER (*(volatile unsigned long *)(RIT_BASE_ADDR + 0x0C))\r
+\r
+\r
+/* Real Time Clock (RTC) */\r
+#define RTC_BASE_ADDR 0x40024000\r
+#define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))\r
+#define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))\r
+#define RTC_CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C))\r
+#define RTC_AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10))\r
+#define RTC_CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14))\r
+#define RTC_CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18))\r
+#define RTC_CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C))\r
+#define RTC_SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20))\r
+#define RTC_MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24))\r
+#define RTC_HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28))\r
+#define RTC_DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C))\r
+#define RTC_DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30))\r
+#define RTC_DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34))\r
+#define RTC_MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38))\r
+#define RTC_YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C))\r
+#define RTC_CALIBRATION (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40))\r
+#define RTC_GPREG0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x44))\r
+#define RTC_GPREG1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x48))\r
+#define RTC_GPREG2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x4C))\r
+#define RTC_GPREG3 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x50))\r
+#define RTC_GPREG4 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x54))\r
+#define RTC_WAKEUPDIS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x58))\r
+#define RTC_PWRCTRL (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x5c))\r
+#define RTC_ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60))\r
+#define RTC_ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64))\r
+#define RTC_ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68))\r
+#define RTC_ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C))\r
+#define RTC_ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70))\r
+#define RTC_ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74))\r
+#define RTC_ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78))\r
+#define RTC_ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C))\r
+\r
+\r
+/* Watchdog Timer (WDT) */\r
+#define WDT_BASE_ADDR 0x40000000\r
+#define WDMOD (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x00))\r
+#define WDTC (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x04))\r
+#define WDFEED (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x08))\r
+#define WDTV (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x0C))\r
+#define WDCLKSEL (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x10))\r
+\r
+\r
+/* A/D Converter 0 (ADC0) */\r
+#define AD0_BASE_ADDR 0x40034000\r
+#define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))\r
+#define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))\r
+#define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C))\r
+#define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10))\r
+#define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14))\r
+#define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18))\r
+#define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C))\r
+#define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20))\r
+#define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24))\r
+#define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28))\r
+#define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C))\r
+#define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30))\r
+#define ADTRIM (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x34))\r
+\r
+\r
+/* D/A Converter (DAC) */\r
+#define DAC_BASE_ADDR 0x4008C000\r
+#define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00))\r
+#define DACCTRL (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x04))\r
+#define DACCNTVAL (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x08))\r
+\r
+\r
+/* Motor Control PWM */\r
+#define MCPWM_BASE_ADDR 0x400B8000\r
+#define MCCON (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x00))\r
+#define MCCON_SET (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x04))\r
+#define MCCON_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x08))\r
+#define MCCAPCON (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x0C))\r
+#define MCCAPCON_SET (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x10))\r
+#define MCCAPCON_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x14))\r
+#define MCTIM0 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x18))\r
+#define MCTIM1 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x1C))\r
+#define MCTIM2 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x20))\r
+#define MCPER0 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x24))\r
+#define MCPER1 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x28))\r
+#define MCPER2 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x2C))\r
+#define MCPW0 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x30))\r
+#define MCPW1 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x34))\r
+#define MCPW2 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x38))\r
+#define MCDEADTIME (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x3C))\r
+#define MCCCP (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x40))\r
+#define MCCR0 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x44))\r
+#define MCCR1 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x48))\r
+#define MCCR2 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x4C))\r
+#define MCINTEN (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x50))\r
+#define MCINTEN_SET (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x54))\r
+#define MCINTEN_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x58))\r
+#define MCCNTCON (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x5C))\r
+#define MCCNTCON_SET (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x60))\r
+#define MCCNTCON_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x64))\r
+#define MCINTFLAG (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x68))\r
+#define MCINTFLAG_SET (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x6C))\r
+#define MCINTFLAG_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x70))\r
+#define MCCAP_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x74))\r
+\r
+\r
+/* Quadrature Encoder Interface (QEI) */\r
+#define QEI_BASE_ADDR 0x400BC000\r
+\r
+/* QEI Control Registers */\r
+#define QEICON (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x000))\r
+#define QEISTAT (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x004))\r
+#define QEICONF (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x008))\r
+\r
+/* QEI Position, Index, and Timer Registers */\r
+#define QEIPOS (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x00C))\r
+#define QEIMAXPSOS (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x010))\r
+#define CMPOS0 (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x014))\r
+#define CMPOS1 (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x018))\r
+#define CMPOS2 (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x01C))\r
+#define INXCNT (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x020))\r
+#define INXCMP (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x024))\r
+#define QEILOAD (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x028))\r
+#define QEITIME (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x02C))\r
+#define QEIVEL (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x030))\r
+#define QEICAP (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x034))\r
+#define VELCOMP (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x038))\r
+#define FILTER (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x03C))\r
+\r
+/* QEI Interrupt registers */\r
+#define QEIIES (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFDC))\r
+#define QEIIEC (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFD8))\r
+#define QEIINTSTAT (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFE0))\r
+#define QEIIE (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFE4))\r
+#define QEICLR (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFE8))\r
+#define QEISET (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFEC))\r
+\r
+\r
+/* CAN Controllers and Acceptance Filter */\r
+\r
+/* CAN Acceptance Filter */\r
+#define CAN_AF_BASE_ADDR 0x4003C000\r
+#define AFMR (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x00)) \r
+#define SFF_sa (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x04)) \r
+#define SFF_GRP_sa (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x08))\r
+#define EFF_sa (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x0C))\r
+#define EFF_GRP_sa (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x10)) \r
+#define ENDofTable (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x14))\r
+#define LUTerrAd (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x18)) \r
+#define LUTerr (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x1C))\r
+#define FCANIE (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x20))\r
+#define FCANIC0 (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x24))\r
+#define FCANIC1 (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x28))\r
+\r
+/* CAN Centralized Registers */\r
+#define CAN_BASE_ADDR 0x40040000 \r
+#define CANTxSR (*(volatile unsigned long *)(CAN_BASE_ADDR + 0x00)) \r
+#define CANRxSR (*(volatile unsigned long *)(CAN_BASE_ADDR + 0x04)) \r
+#define CANMSR (*(volatile unsigned long *)(CAN_BASE_ADDR + 0x08))\r
+\r
+/* CAN1 Controller */\r
+#define CAN1_BASE_ADDR 0x40044000\r
+#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) \r
+#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) \r
+#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) \r
+#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) \r
+#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10))\r
+#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) \r
+#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) \r
+#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) \r
+#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) \r
+#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24))\r
+#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) \r
+#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) \r
+#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) \r
+#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) \r
+#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38))\r
+#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) \r
+#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) \r
+#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) \r
+#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) \r
+#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C))\r
+#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) \r
+#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) \r
+#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) \r
+#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C))\r
+\r
+/* CAN2 Controller */\r
+#define CAN2_BASE_ADDR 0x40048000\r
+#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) \r
+#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) \r
+#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) \r
+#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) \r
+#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10))\r
+#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) \r
+#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) \r
+#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) \r
+#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) \r
+#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24))\r
+#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) \r
+#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) \r
+#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) \r
+#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) \r
+#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38))\r
+#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) \r
+#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) \r
+#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) \r
+#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) \r
+#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C))\r
+#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) \r
+#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) \r
+#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) \r
+#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C))\r
+\r
+\r
+/* General Purpose DMA Controller (GPDMA) */\r
+#define DMA_BASE_ADDR 0x50004000\r
+#define DMACIntStat (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000))\r
+#define DMACIntTCStat (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004))\r
+#define DMACIntTCClear (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008))\r
+#define DMACIntErrStat (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C))\r
+#define DMACIntErrClr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010))\r
+#define DMACRawIntTCStat (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014))\r
+#define DMACRawIntErrStat (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018))\r
+#define DMACEnbldChns (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C))\r
+#define DMACSoftBReq (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020))\r
+#define DMACSoftSReq (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024))\r
+#define DMACSoftLBReq (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028))\r
+#define DMACSoftLSReq (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C))\r
+#define DMACConfig (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030))\r
+#define DMACSync (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034))\r
+\r
+/* DMA Channel 0 Registers */\r
+#define DMACC0SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100))\r
+#define DMACC0DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104))\r
+#define DMACC0LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108))\r
+#define DMACC0Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C))\r
+#define DMACC0Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110))\r
+\r
+/* DMA Channel 1 Registers */\r
+#define DMACC1SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120))\r
+#define DMACC1DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124))\r
+#define DMACC1LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128))\r
+#define DMACC1Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C))\r
+#define DMACC1Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130))\r
+\r
+/* DMA Channel 2 Registers */\r
+#define DMACC2SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x140))\r
+#define DMACC2DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x144))\r
+#define DMACC2LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x148))\r
+#define DMACC2Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x14C))\r
+#define DMACC2Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x150))\r
+\r
+/* DMA Channel 3 Registers */\r
+#define DMACC3SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x160))\r
+#define DMACC3DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x164))\r
+#define DMACC3LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x168))\r
+#define DMACC3Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x16C))\r
+#define DMACC3Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x170))\r
+\r
+/* DMA Channel 4 Registers */\r
+#define DMACC4SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x180))\r
+#define DMACC4DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x184))\r
+#define DMACC4LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x188))\r
+#define DMACC4Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x18C))\r
+#define DMACC4Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x190))\r
+\r
+/* DMA Channel 5 Registers */\r
+#define DMACC5SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1A0))\r
+#define DMACC5DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1A4))\r
+#define DMACC5LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1A8))\r
+#define DMACC5Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1AC))\r
+#define DMACC5Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1B0))\r
+\r
+/* DMA Channel 6 Registers */\r
+#define DMACC6SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1C0))\r
+#define DMACC6DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1C4))\r
+#define DMACC6LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1C8))\r
+#define DMACC6Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1CC))\r
+#define DMACC6Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1D0))\r
+\r
+/* DMA Channel 7 Registers */\r
+#define DMACC7SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1E0))\r
+#define DMACC7DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1E4))\r
+#define DMACC7LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1E8))\r
+#define DMACC7Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1EC))\r
+#define DMACC7Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1F0))\r
+\r
+\r
+/* USB Controller */\r
+#define USB_BASE_ADDR 0x5000C000\r
+\r
+#define USBIntSt (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1C0))\r
+\r
+\r
+/* USB Device Controller */\r
+\r
+/* USB Device Clock Control Registers */\r
+#define USBClkCtrl (*(volatile unsigned long *)(USB_BASE_ADDR + 0xFF4))\r
+#define USBClkSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0xFF8))\r
+\r
+/* USB Device Interrupt Registers */\r
+#define USBDevIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x200))\r
+#define USBDevIntEn (*(volatile unsigned long *)(USB_BASE_ADDR + 0x204))\r
+#define USBDevIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x208))\r
+#define USBDevIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20C))\r
+#define USBDevIntPri (*(volatile unsigned long *)(USB_BASE_ADDR + 0x22C))\r
+\r
+/* USB Device Endpoint Interrupt Registers */\r
+#define USBEpIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x230))\r
+#define USBEpIntEn (*(volatile unsigned long *)(USB_BASE_ADDR + 0x234))\r
+#define USBEpIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x238))\r
+#define USBEpIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x23C))\r
+#define USBEpIntPri (*(volatile unsigned long *)(USB_BASE_ADDR + 0x240))\r
+\r
+/* USB Device Endpoint Realization Registers */\r
+#define USBReEp (*(volatile unsigned long *)(USB_BASE_ADDR + 0x244))\r
+#define USBEpInd (*(volatile unsigned long *)(USB_BASE_ADDR + 0x248))\r
+#define USBMaxPSize (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24C))\r
+\r
+/* USB Device SIE Command Reagisters */\r
+#define USBCmdCode (*(volatile unsigned long *)(USB_BASE_ADDR + 0x210))\r
+#define USBCmdData (*(volatile unsigned long *)(USB_BASE_ADDR + 0x214))\r
+\r
+/* USB Device Data Transfer Registers */\r
+#define USBRxData (*(volatile unsigned long *)(USB_BASE_ADDR + 0x218))\r
+#define USBTxData (*(volatile unsigned long *)(USB_BASE_ADDR + 0x21C))\r
+#define USBRxPLen (*(volatile unsigned long *)(USB_BASE_ADDR + 0x220))\r
+#define USBTxPLen (*(volatile unsigned long *)(USB_BASE_ADDR + 0x224))\r
+#define USBCtrl (*(volatile unsigned long *)(USB_BASE_ADDR + 0x228))\r
+\r
+/* USB Device DMA Registers */\r
+#define USBDMARSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x250))\r
+#define USBDMARClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x254))\r
+#define USBDMARSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x258))\r
+#define USBUDCAH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x280))\r
+#define USBEpDMASt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x284))\r
+#define USBEpDMAEn (*(volatile unsigned long *)(USB_BASE_ADDR + 0x288))\r
+#define USBEpDMADis (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28C))\r
+#define USBDMAIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x290))\r
+#define USBDMAIntEn (*(volatile unsigned long *)(USB_BASE_ADDR + 0x294))\r
+#define USBEoTIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2A0))\r
+#define USBEoTIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2A4))\r
+#define USBEoTIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2A8))\r
+#define USBNDDRIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2AC))\r
+#define USBNDDRIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2B0))\r
+#define USBNDDRIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2B4))\r
+#define USBSysErrIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2B8))\r
+#define USBSysErrIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2BC))\r
+#define USBSysErrIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C0))\r
+\r
+\r
+/* USB Host Controller */\r
+#define HcRevision (*(volatile unsigned long *)(USB_BASE_ADDR + 0x000))\r
+#define HcControl (*(volatile unsigned long *)(USB_BASE_ADDR + 0x004))\r
+#define HcCommandStatus (*(volatile unsigned long *)(USB_BASE_ADDR + 0x008))\r
+#define HcInterruptStatus (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00C))\r
+#define HcInterruptEnable (*(volatile unsigned long *)(USB_BASE_ADDR + 0x010))\r
+#define HcInterruptDisable (*(volatile unsigned long *)(USB_BASE_ADDR + 0x014))\r
+#define HcHCCA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x018))\r
+#define HcPeriodCurrentED (*(volatile unsigned long *)(USB_BASE_ADDR + 0x01C))\r
+#define HcControlHeadED (*(volatile unsigned long *)(USB_BASE_ADDR + 0x020))\r
+#define HcControlCurrentED (*(volatile unsigned long *)(USB_BASE_ADDR + 0x024))\r
+#define HcBulkHeadED (*(volatile unsigned long *)(USB_BASE_ADDR + 0x028))\r
+#define HcBulkCurrentED (*(volatile unsigned long *)(USB_BASE_ADDR + 0x02C))\r
+#define HcDoneHead (*(volatile unsigned long *)(USB_BASE_ADDR + 0x030))\r
+#define HcFmInterval (*(volatile unsigned long *)(USB_BASE_ADDR + 0x034))\r
+#define HcFmRemaining (*(volatile unsigned long *)(USB_BASE_ADDR + 0x038))\r
+#define HcFmNumber (*(volatile unsigned long *)(USB_BASE_ADDR + 0x03C))\r
+#define HcPeriodStart (*(volatile unsigned long *)(USB_BASE_ADDR + 0x040))\r
+#define HcLSThreshold (*(volatile unsigned long *)(USB_BASE_ADDR + 0x044))\r
+#define HcRhDescriptorA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x048))\r
+#define HcRhDescriptorB (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04C))\r
+#define HcRhStatus (*(volatile unsigned long *)(USB_BASE_ADDR + 0x050))\r
+#define HcRhPortStatus1 (*(volatile unsigned long *)(USB_BASE_ADDR + 0x054))\r
+#define HcRhPortStatus2 (*(volatile unsigned long *)(USB_BASE_ADDR + 0x058))\r
+\r
+\r
+/* USB OTG Controller */\r
+\r
+/* USB OTG Registers */\r
+#define OTGIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x100))\r
+#define OTGIntEn (*(volatile unsigned long *)(USB_BASE_ADDR + 0x104))\r
+#define OTGIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x108))\r
+#define OTGIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10C))\r
+#define OTGIntCtrl (*(volatile unsigned long *)(USB_BASE_ADDR + 0x110))\r
+#define OTGTmr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x114))\r
+\r
+/* USB OTG I2C Registers */\r
+#define I2C_RX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x300))\r
+#define I2C_TX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x300))\r
+#define I2C_STS (*(volatile unsigned long *)(USB_BASE_ADDR + 0x304))\r
+#define I2C_CTL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x308))\r
+#define I2C_CLKHI (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30C))\r
+#define I2C_CLKLO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x310))\r
+\r
+/* USB OTG Clock Control Registers */\r
+#define OTGClkCtrl (*(volatile unsigned long *)(USB_BASE_ADDR + 0xFF4))\r
+#define OTGClkSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0xFF8))\r
+\r
+\r
+/* Ethernet MAC */\r
+#define MAC_BASE_ADDR 0x50000000\r
+\r
+/* MAC Registers */\r
+#define ETH_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000))\r
+#define ETH_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004))\r
+#define ETH_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008))\r
+#define ETH_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C))\r
+#define ETH_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010))\r
+#define ETH_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014))\r
+#define ETH_PHYSUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018))\r
+#define ETH_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C))\r
+#define ETH_MIICFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020))\r
+#define ETH_MIICMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024))\r
+#define ETH_MIIADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028))\r
+#define ETH_MIIWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C))\r
+#define ETH_MIIRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030))\r
+#define ETH_MIIIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034))\r
+#define ETH_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040))\r
+#define ETH_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044))\r
+#define ETH_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048))\r
+\r
+/* MAC Control Registers */\r
+#define ETH_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100))\r
+#define ETH_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104))\r
+#define ETH_RXDESC (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108))\r
+#define ETH_RXSTAT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C))\r
+#define ETH_RXDESCRNO (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110))\r
+#define ETH_RXPRODIX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114))\r
+#define ETH_RXCONSIX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118))\r
+#define ETH_TXDESC (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C))\r
+#define ETH_TXSTAT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120))\r
+#define ETH_TXDESCRNO (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124))\r
+#define ETH_TXPRODIX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128))\r
+#define ETH_TXCONSIX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C))\r
+#define ETH_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158))\r
+#define ETH_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C))\r
+#define ETH_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160))\r
+#define ETH_FLOWCNTCOUNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170))\r
+#define ETH_FLOWCNTSTAT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174))\r
+\r
+/* MAX Rx Filter Registers */\r
+#define ETH_RXFILTERCTL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200))\r
+#define ETH_RXFILTERWOLSTAT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204))\r
+#define ETH_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208))\r
+#define ETH_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210))\r
+#define ETH_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214))\r
+\r
+/* MAC Module Control Registers */\r
+#define ETH_INSTSTAT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0))\r
+#define ETH_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4))\r
+#define ETH_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8))\r
+#define ETH_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC))\r
+#define ETH_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4))\r
+\r
+#define MAC_Module_ID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC))\r
+\r
+/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */\r
+#define MAC_BASE_ADDR 0x50000000\r
+#define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */\r
+#define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */\r
+#define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */\r
+#define MAC_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */\r
+#define MAC_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */\r
+#define MAC_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */\r
+#define MAC_SUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */\r
+#define MAC_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */\r
+#define MAC_MCFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */\r
+#define MAC_MCMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */\r
+#define MAC_MADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */\r
+#define MAC_MWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */\r
+#define MAC_MRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */\r
+#define MAC_MIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */\r
+\r
+#define MAC_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */\r
+#define MAC_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */\r
+#define MAC_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */\r
+\r
+#define MAC_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */\r
+#define MAC_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */\r
+#define MAC_RXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */\r
+#define MAC_RXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */\r
+#define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */\r
+#define MAC_RXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */\r
+#define MAC_RXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */\r
+#define MAC_TXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */\r
+#define MAC_TXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */\r
+#define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */\r
+#define MAC_TXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */\r
+#define MAC_TXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */\r
+\r
+#define MAC_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */\r
+#define MAC_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */\r
+#define MAC_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */\r
+\r
+#define MAC_FLOWCONTROLCNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */\r
+#define MAC_FLOWCONTROLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */\r
+\r
+#define MAC_RXFILTERCTRL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */\r
+#define MAC_RXFILTERWOLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */\r
+#define MAC_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */\r
+\r
+#define MAC_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */\r
+#define MAC_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */\r
+\r
+#define MAC_INTSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */\r
+#define MAC_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */\r
+#define MAC_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */\r
+#define MAC_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */\r
+\r
+#define MAC_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */\r
+#define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */\r
+\r
+#define PCONP_PCTIM0 0x00000002\r
+#define PCONP_PCTIM1 0x00000004\r
+#define PCONP_PCUART0 0x00000008\r
+#define PCONP_PCUART1 0x00000010\r
+#define PCONP_PCPWM1 0x00000040\r
+#define PCONP_PCI2C0 0x00000080\r
+#define PCONP_PCSPI 0x00000100\r
+#define PCONP_PCRTC 0x00000200\r
+#define PCONP_PCSSP1 0x00000400\r
+#define PCONP_PCAD 0x00001000\r
+#define PCONP_PCCAN1 0x00002000\r
+#define PCONP_PCCAN2 0x00004000\r
+#define PCONP_PCGPIO 0x00008000\r
+#define PCONP_PCRIT 0x00010000\r
+#define PCONP_PCMCPWM 0x00020000\r
+#define PCONP_PCQEI 0x00040000\r
+#define PCONP_PCI2C1 0x00080000\r
+#define PCONP_PCSSP0 0x00200000\r
+#define PCONP_PCTIM2 0x00400000\r
+#define PCONP_PCTIM3 0x00800000\r
+#define PCONP_PCUART2 0x01000000\r
+#define PCONP_PCUART3 0x02000000\r
+#define PCONP_PCI2C2 0x04000000\r
+#define PCONP_PCI2S 0x08000000\r
+#define PCONP_PCGPDMA 0x20000000\r
+#define PCONP_PCENET 0x40000000\r
+#define PCONP_PCUSB 0x80000000\r
+\r
+#define PLLCON_PLLE 0x00000001\r
+#define PLLCON_PLLC 0x00000002\r
+#define PLLCON_MASK 0x00000003\r
+\r
+#define PLLCFG_MUL1 0x00000000\r
+#define PLLCFG_MUL2 0x00000001\r
+#define PLLCFG_MUL3 0x00000002\r
+#define PLLCFG_MUL4 0x00000003\r
+#define PLLCFG_MUL5 0x00000004\r
+#define PLLCFG_MUL6 0x00000005\r
+#define PLLCFG_MUL7 0x00000006\r
+#define PLLCFG_MUL8 0x00000007\r
+#define PLLCFG_MUL9 0x00000008\r
+#define PLLCFG_MUL10 0x00000009\r
+#define PLLCFG_MUL11 0x0000000A\r
+#define PLLCFG_MUL12 0x0000000B\r
+#define PLLCFG_MUL13 0x0000000C\r
+#define PLLCFG_MUL14 0x0000000D\r
+#define PLLCFG_MUL15 0x0000000E\r
+#define PLLCFG_MUL16 0x0000000F\r
+#define PLLCFG_MUL17 0x00000010\r
+#define PLLCFG_MUL18 0x00000011\r
+#define PLLCFG_MUL19 0x00000012\r
+#define PLLCFG_MUL20 0x00000013\r
+#define PLLCFG_MUL21 0x00000014\r
+#define PLLCFG_MUL22 0x00000015\r
+#define PLLCFG_MUL23 0x00000016\r
+#define PLLCFG_MUL24 0x00000017\r
+#define PLLCFG_MUL25 0x00000018\r
+#define PLLCFG_MUL26 0x00000019\r
+#define PLLCFG_MUL27 0x0000001A\r
+#define PLLCFG_MUL28 0x0000001B\r
+#define PLLCFG_MUL29 0x0000001C\r
+#define PLLCFG_MUL30 0x0000001D\r
+#define PLLCFG_MUL31 0x0000001E\r
+#define PLLCFG_MUL32 0x0000001F\r
+#define PLLCFG_MUL33 0x00000020\r
+#define PLLCFG_MUL34 0x00000021\r
+#define PLLCFG_MUL35 0x00000022\r
+#define PLLCFG_MUL36 0x00000023\r
+\r
+#define PLLCFG_DIV1 0x00000000\r
+#define PLLCFG_DIV2 0x00010000\r
+#define PLLCFG_DIV3 0x00020000\r
+#define PLLCFG_DIV4 0x00030000\r
+#define PLLCFG_DIV5 0x00040000\r
+#define PLLCFG_DIV6 0x00050000\r
+#define PLLCFG_DIV7 0x00060000\r
+#define PLLCFG_DIV8 0x00070000\r
+#define PLLCFG_DIV9 0x00080000\r
+#define PLLCFG_DIV10 0x00090000\r
+#define PLLCFG_MASK 0x00FF7FFF\r
+\r
+#define PLLSTAT_MSEL_MASK 0x00007FFF\r
+#define PLLSTAT_NSEL_MASK 0x00FF0000\r
+\r
+#define PLLSTAT_PLLE (1 << 24)\r
+#define PLLSTAT_PLLC (1 << 25)\r
+#define PLLSTAT_PLOCK (1 << 26)\r
+\r
+#define PLLFEED_FEED1 0x000000AA\r
+#define PLLFEED_FEED2 0x00000055\r
+\r
+#define NVIC_IRQ_WDT 0u // IRQ0, exception number 16\r
+#define NVIC_IRQ_TIMER0 1u // IRQ1, exception number 17\r
+#define NVIC_IRQ_TIMER1 2u // IRQ2, exception number 18\r
+#define NVIC_IRQ_TIMER2 3u // IRQ3, exception number 19\r
+#define NVIC_IRQ_TIMER3 4u // IRQ4, exception number 20\r
+#define NVIC_IRQ_UART0 5u // IRQ5, exception number 21\r
+#define NVIC_IRQ_UART1 6u // IRQ6, exception number 22\r
+#define NVIC_IRQ_UART2 7u // IRQ7, exception number 23\r
+#define NVIC_IRQ_UART3 8u // IRQ8, exception number 24\r
+#define NVIC_IRQ_PWM1 9u // IRQ9, exception number 25\r
+#define NVIC_IRQ_I2C0 10u // IRQ10, exception number 26\r
+#define NVIC_IRQ_I2C1 11u // IRQ11, exception number 27\r
+#define NVIC_IRQ_I2C2 12u // IRQ12, exception number 28\r
+#define NVIC_IRQ_SPI 13u // IRQ13, exception number 29\r
+#define NVIC_IRQ_SSP0 14u // IRQ14, exception number 30\r
+#define NVIC_IRQ_SSP1 15u // IRQ15, exception number 31\r
+#define NVIC_IRQ_PLL0 16u // IRQ16, exception number 32\r
+#define NVIC_IRQ_RTC 17u // IRQ17, exception number 33\r
+#define NVIC_IRQ_EINT0 18u // IRQ18, exception number 34\r
+#define NVIC_IRQ_EINT1 19u // IRQ19, exception number 35\r
+#define NVIC_IRQ_EINT2 20u // IRQ20, exception number 36\r
+#define NVIC_IRQ_EINT3 21u // IRQ21, exception number 37\r
+#define NVIC_IRQ_ADC 22u // IRQ22, exception number 38\r
+#define NVIC_IRQ_BOD 23u // IRQ23, exception number 39\r
+#define NVIC_IRQ_USB 24u // IRQ24, exception number 40\r
+#define NVIC_IRQ_CAN 25u // IRQ25, exception number 41\r
+#define NVIC_IRQ_GPDMA 26u // IRQ26, exception number 42\r
+#define NVIC_IRQ_I2S 27u // IRQ27, exception number 43\r
+#define NVIC_IRQ_ETHERNET 28u // IRQ28, exception number 44\r
+#define NVIC_IRQ_RIT 29u // IRQ29, exception number 45\r
+#define NVIC_IRQ_MCPWM 30u // IRQ30, exception number 46\r
+#define NVIC_IRQ_QE 31u // IRQ31, exception number 47\r
+#define NVIC_IRQ_PLL1 32u // IRQ32, exception number 48\r
+#define NVIC_IRQ_USB_ACT 33u // IRQ33, exception number 49\r
+#define NVIC_IRQ_CAN_ACT 34u // IRQ34, exception number 50\r
\r
typedef enum IRQn\r
{\r
PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */\r
} IRQn_Type;\r
\r
-\r
-/*\r
- * ==========================================================================\r
- * ----------- Processor and Core Peripheral Section ------------------------\r
- * ==========================================================================\r
- */\r
-\r
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */\r
-#define __MPU_PRESENT 1 /*!< MPU present or not */\r
-#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */\r
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
-\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_LPC17xx.h" /* System Header */\r
-\r
-\r
-\r
-/**\r
- * Initialize the system clock\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * @brief Setup the microcontroller system.\r
- * Initialize the System and update the SystemFrequency variable.\r
- */\r
-extern void SystemInit (void);\r
-\r
-\r
-/******************************************************************************/\r
-/* Device Specific Peripheral registers structures */\r
-/******************************************************************************/\r
-\r
-//#pragma anon_unions\r
-\r
-/*------------- System Control (SC) ------------------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t FLASHCFG; /* Flash Accelerator Module */\r
- uint32_t RESERVED0[31];\r
- __IO uint32_t PLL0CON; /* Clocking and Power Control */\r
- __IO uint32_t PLL0CFG;\r
- __I uint32_t PLL0STAT;\r
- __O uint32_t PLL0FEED;\r
- uint32_t RESERVED1[4];\r
- __IO uint32_t PLL1CON;\r
- __IO uint32_t PLL1CFG;\r
- __I uint32_t PLL1STAT;\r
- __O uint32_t PLL1FEED;\r
- uint32_t RESERVED2[4];\r
- __IO uint32_t PCON;\r
- __IO uint32_t PCONP;\r
- uint32_t RESERVED3[15];\r
- __IO uint32_t CCLKCFG;\r
- __IO uint32_t USBCLKCFG;\r
- __IO uint32_t CLKSRCSEL;\r
- uint32_t RESERVED4[12];\r
- __IO uint32_t EXTINT; /* External Interrupts */\r
- uint32_t RESERVED5;\r
- __IO uint32_t EXTMODE;\r
- __IO uint32_t EXTPOLAR;\r
- uint32_t RESERVED6[12];\r
- __IO uint32_t RSID; /* Reset */\r
- uint32_t RESERVED7[7];\r
- __IO uint32_t SCS; /* Syscon Miscellaneous Registers */\r
- __IO uint32_t IRCTRIM; /* Clock Dividers */\r
- __IO uint32_t PCLKSEL0;\r
- __IO uint32_t PCLKSEL1;\r
- uint32_t RESERVED8[4];\r
- __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */\r
- uint32_t RESERVED9;\r
- __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */\r
- } SC_TypeDef;\r
-\r
-/*------------- Pin Connect Block (PINCON) -----------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t PINSEL0;\r
- __IO uint32_t PINSEL1;\r
- __IO uint32_t PINSEL2;\r
- __IO uint32_t PINSEL3;\r
- __IO uint32_t PINSEL4;\r
- __IO uint32_t PINSEL5;\r
- __IO uint32_t PINSEL6;\r
- __IO uint32_t PINSEL7;\r
- __IO uint32_t PINSEL8;\r
- __IO uint32_t PINSEL9;\r
- __IO uint32_t PINSEL10;\r
- uint32_t RESERVED0[5];\r
- __IO uint32_t PINMODE0;\r
- __IO uint32_t PINMODE1;\r
- __IO uint32_t PINMODE2;\r
- __IO uint32_t PINMODE3;\r
- __IO uint32_t PINMODE4;\r
- __IO uint32_t PINMODE5;\r
- __IO uint32_t PINMODE6;\r
- __IO uint32_t PINMODE7;\r
- __IO uint32_t PINMODE8;\r
- __IO uint32_t PINMODE9;\r
- __IO uint32_t PINMODE_OD0;\r
- __IO uint32_t PINMODE_OD1;\r
- __IO uint32_t PINMODE_OD2;\r
- __IO uint32_t PINMODE_OD3;\r
- __IO uint32_t PINMODE_OD4;\r
-} PINCON_TypeDef;\r
-\r
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t FIODIR;\r
- uint32_t RESERVED0[3];\r
- __IO uint32_t FIOMASK;\r
- __IO uint32_t FIOPIN;\r
- __IO uint32_t FIOSET;\r
- __O uint32_t FIOCLR;\r
-} GPIO_TypeDef;\r
-\r
-typedef struct\r
-{\r
- __I uint32_t IntStatus;\r
- __I uint32_t IO0IntStatR;\r
- __I uint32_t IO0IntStatF;\r
- __O uint32_t IO0IntClr;\r
- __IO uint32_t IO0IntEnR;\r
- __IO uint32_t IO0IntEnF;\r
- uint32_t RESERVED0[3];\r
- __I uint32_t IO2IntStatR;\r
- __I uint32_t IO2IntStatF;\r
- __O uint32_t IO2IntClr;\r
- __IO uint32_t IO2IntEnR;\r
- __IO uint32_t IO2IntEnF;\r
-} GPIOINT_TypeDef;\r
-\r
-/*------------- Timer (TIM) --------------------------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t IR;\r
- __IO uint32_t TCR;\r
- __IO uint32_t TC;\r
- __IO uint32_t PR;\r
- __IO uint32_t PC;\r
- __IO uint32_t MCR;\r
- __IO uint32_t MR0;\r
- __IO uint32_t MR1;\r
- __IO uint32_t MR2;\r
- __IO uint32_t MR3;\r
- __IO uint32_t CCR;\r
- __I uint32_t CR0;\r
- __I uint32_t CR1;\r
- uint32_t RESERVED0[2];\r
- __IO uint32_t EMR;\r
- uint32_t RESERVED1[24];\r
- __IO uint32_t CTCR;\r
-} TIM_TypeDef;\r
-\r
-/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t IR;\r
- __IO uint32_t TCR;\r
- __IO uint32_t TC;\r
- __IO uint32_t PR;\r
- __IO uint32_t PC;\r
- __IO uint32_t MCR;\r
- __IO uint32_t MR0;\r
- __IO uint32_t MR1;\r
- __IO uint32_t MR2;\r
- __IO uint32_t MR3;\r
- __IO uint32_t CCR;\r
- __I uint32_t CR0;\r
- __I uint32_t CR1;\r
- __I uint32_t CR2;\r
- __I uint32_t CR3;\r
- __IO uint32_t MR4;\r
- __IO uint32_t MR5;\r
- __IO uint32_t MR6;\r
- __IO uint32_t PCR;\r
- __IO uint32_t LER;\r
- uint32_t RESERVED0[7];\r
- __IO uint32_t CTCR;\r
-} PWM_TypeDef;\r
-\r
-/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/\r
-typedef struct\r
-{\r
- union {\r
- __I uint8_t RBR;\r
- __O uint8_t THR;\r
- __IO uint8_t DLL;\r
- uint32_t RESERVED0;\r
- };\r
- union {\r
- __IO uint8_t DLM;\r
- __IO uint32_t IER;\r
- };\r
- union {\r
- __I uint32_t IIR;\r
- __O uint8_t FCR;\r
- };\r
- __IO uint8_t LCR;\r
- uint8_t RESERVED1[7];\r
- __IO uint8_t LSR;\r
- uint8_t RESERVED2[7];\r
- __IO uint8_t SCR;\r
- uint8_t RESERVED3[3];\r
- __IO uint32_t ACR;\r
- __IO uint8_t ICR;\r
- uint8_t RESERVED4[3];\r
- __IO uint8_t FDR;\r
- uint8_t RESERVED5[7];\r
- __IO uint8_t TER;\r
- uint8_t RESERVED6[27];\r
- __IO uint8_t RS485CTRL;\r
- uint8_t RESERVED7[3];\r
- __IO uint8_t ADRMATCH;\r
-} UART_TypeDef;\r
-\r
-typedef struct\r
-{\r
- union {\r
- __I uint8_t RBR;\r
- __O uint8_t THR;\r
- __IO uint8_t DLL;\r
- uint32_t RESERVED0;\r
- };\r
- union {\r
- __IO uint8_t DLM;\r
- __IO uint32_t IER;\r
- };\r
- union {\r
- __I uint32_t IIR;\r
- __O uint8_t FCR;\r
- };\r
- __IO uint8_t LCR;\r
- uint8_t RESERVED1[3];\r
- __IO uint8_t MCR;\r
- uint8_t RESERVED2[3];\r
- __IO uint8_t LSR;\r
- uint8_t RESERVED3[3];\r
- __IO uint8_t MSR;\r
- uint8_t RESERVED4[3];\r
- __IO uint8_t SCR;\r
- uint8_t RESERVED5[3];\r
- __IO uint32_t ACR;\r
- uint32_t RESERVED6;\r
- __IO uint32_t FDR;\r
- uint32_t RESERVED7;\r
- __IO uint8_t TER;\r
- uint8_t RESERVED8[27];\r
- __IO uint8_t RS485CTRL;\r
- uint8_t RESERVED9[3];\r
- __IO uint8_t ADRMATCH;\r
- uint8_t RESERVED10[3];\r
- __IO uint8_t RS485DLY;\r
-} UART1_TypeDef;\r
-\r
-/*------------- Serial Peripheral Interface (SPI) ----------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t SPCR;\r
- __I uint32_t SPSR;\r
- __IO uint32_t SPDR;\r
- __IO uint32_t SPCCR;\r
- uint32_t RESERVED0[3];\r
- __IO uint32_t SPINT;\r
-} SPI_TypeDef;\r
-\r
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t CR0;\r
- __IO uint32_t CR1;\r
- __IO uint32_t DR;\r
- __I uint32_t SR;\r
- __IO uint32_t CPSR;\r
- __IO uint32_t IMSC;\r
- __IO uint32_t RIS;\r
- __IO uint32_t MIS;\r
- __IO uint32_t ICR;\r
- __IO uint32_t DMACR;\r
-} SSP_TypeDef;\r
-\r
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t I2CONSET;\r
- __I uint32_t I2STAT;\r
- __IO uint32_t I2DAT;\r
- __IO uint32_t I2ADR0;\r
- __IO uint32_t I2SCLH;\r
- __IO uint32_t I2SCLL;\r
- __O uint32_t I2CONCLR;\r
- __IO uint32_t MMCTRL;\r
- __IO uint32_t I2ADR1;\r
- __IO uint32_t I2ADR2;\r
- __IO uint32_t I2ADR3;\r
- __I uint32_t I2DATA_BUFFER;\r
- __IO uint32_t I2MASK0;\r
- __IO uint32_t I2MASK1;\r
- __IO uint32_t I2MASK2;\r
- __IO uint32_t I2MASK3;\r
-} I2C_TypeDef;\r
-\r
-/*------------- Inter IC Sound (I2S) -----------------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t I2SDAO;\r
- __I uint32_t I2SDAI;\r
- __O uint32_t I2STXFIFO;\r
- __I uint32_t I2SRXFIFO;\r
- __I uint32_t I2SSTATE;\r
- __IO uint32_t I2SDMA1;\r
- __IO uint32_t I2SDMA2;\r
- __IO uint32_t I2SIRQ;\r
- __IO uint32_t I2STXRATE;\r
- __IO uint32_t I2SRXRATE;\r
- __IO uint32_t I2STXBITRATE;\r
- __IO uint32_t I2SRXBITRATE;\r
- __IO uint32_t I2STXMODE;\r
- __IO uint32_t I2SRXMODE;\r
-} I2S_TypeDef;\r
-\r
-/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t RICOMPVAL;\r
- __IO uint32_t RIMASK;\r
- __IO uint8_t RICTRL;\r
- uint8_t RESERVED0[3];\r
- __IO uint32_t RICOUNTER;\r
-} RIT_TypeDef;\r
-\r
-/*------------- Real-Time Clock (RTC) ----------------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint8_t ILR;\r
- uint8_t RESERVED0[3];\r
- __IO uint8_t CCR;\r
- uint8_t RESERVED1[3];\r
- __IO uint8_t CIIR;\r
- uint8_t RESERVED2[3];\r
- __IO uint8_t AMR;\r
- uint8_t RESERVED3[3];\r
- __I uint32_t CTIME0;\r
- __I uint32_t CTIME1;\r
- __I uint32_t CTIME2;\r
- __IO uint8_t SEC;\r
- uint8_t RESERVED4[3];\r
- __IO uint8_t MIN;\r
- uint8_t RESERVED5[3];\r
- __IO uint8_t HOUR;\r
- uint8_t RESERVED6[3];\r
- __IO uint8_t DOM;\r
- uint8_t RESERVED7[3];\r
- __IO uint8_t DOW;\r
- uint8_t RESERVED8[3];\r
- __IO uint16_t DOY;\r
- uint16_t RESERVED9;\r
- __IO uint8_t MONTH;\r
- uint8_t RESERVED10[3];\r
- __IO uint16_t YEAR;\r
- uint16_t RESERVED11;\r
- __IO uint32_t CALIBRATION;\r
- __IO uint32_t GPREG0;\r
- __IO uint32_t GPREG1;\r
- __IO uint32_t GPREG2;\r
- __IO uint32_t GPREG3;\r
- __IO uint32_t GPREG4;\r
- __IO uint8_t WAKEUPDIS;\r
- uint8_t RESERVED12[3];\r
- __IO uint8_t PWRCTRL;\r
- uint8_t RESERVED13[3];\r
- __IO uint8_t ALSEC;\r
- uint8_t RESERVED14[3];\r
- __IO uint8_t ALMIN;\r
- uint8_t RESERVED15[3];\r
- __IO uint8_t ALHOUR;\r
- uint8_t RESERVED16[3];\r
- __IO uint8_t ALDOM;\r
- uint8_t RESERVED17[3];\r
- __IO uint8_t ALDOW;\r
- uint8_t RESERVED18[3];\r
- __IO uint16_t ALDOY;\r
- uint16_t RESERVED19;\r
- __IO uint8_t ALMON;\r
- uint8_t RESERVED20[3];\r
- __IO uint16_t ALYEAR;\r
- uint16_t RESERVED21;\r
-} RTC_TypeDef;\r
-\r
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint8_t WDMOD;\r
- uint8_t RESERVED0[3];\r
- __IO uint32_t WDTC;\r
- __O uint8_t WDFEED;\r
- uint8_t RESERVED1[3];\r
- __I uint32_t WDTV;\r
- __IO uint32_t WDCLKSEL;\r
-} WDT_TypeDef;\r
-\r
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t ADCR;\r
- __IO uint32_t ADGDR;\r
- uint32_t RESERVED0;\r
- __IO uint32_t ADINTEN;\r
- __I uint32_t ADDR0;\r
- __I uint32_t ADDR1;\r
- __I uint32_t ADDR2;\r
- __I uint32_t ADDR3;\r
- __I uint32_t ADDR4;\r
- __I uint32_t ADDR5;\r
- __I uint32_t ADDR6;\r
- __I uint32_t ADDR7;\r
- __I uint32_t ADSTAT;\r
- __IO uint32_t ADTRM;\r
-} ADC_TypeDef;\r
-\r
-/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t DACR;\r
- __IO uint32_t DACCTRL;\r
- __IO uint16_t DACCNTVAL;\r
-} DAC_TypeDef;\r
-\r
-/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/\r
-typedef struct\r
-{\r
- __I uint32_t MCCON;\r
- __O uint32_t MCCON_SET;\r
- __O uint32_t MCCON_CLR;\r
- __I uint32_t MCCAPCON;\r
- __O uint32_t MCCAPCON_SET;\r
- __O uint32_t MCCAPCON_CLR;\r
- __IO uint32_t MCTIM0;\r
- __IO uint32_t MCTIM1;\r
- __IO uint32_t MCTIM2;\r
- __IO uint32_t MCPER0;\r
- __IO uint32_t MCPER1;\r
- __IO uint32_t MCPER2;\r
- __IO uint32_t MCPW0;\r
- __IO uint32_t MCPW1;\r
- __IO uint32_t MCPW2;\r
- __IO uint32_t MCDEADTIME;\r
- __IO uint32_t MCCCP;\r
- __IO uint32_t MCCR0;\r
- __IO uint32_t MCCR1;\r
- __IO uint32_t MCCR2;\r
- __I uint32_t MCINTEN;\r
- __O uint32_t MCINTEN_SET;\r
- __O uint32_t MCINTEN_CLR;\r
- __I uint32_t MCCNTCON;\r
- __O uint32_t MCCNTCON_SET;\r
- __O uint32_t MCCNTCON_CLR;\r
- __I uint32_t MCINTFLAG;\r
- __O uint32_t MCINTFLAG_SET;\r
- __O uint32_t MCINTFLAG_CLR;\r
- __O uint32_t MCCAP_CLR;\r
-} MCPWM_TypeDef;\r
-\r
-/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/\r
-typedef struct\r
-{\r
- __O uint32_t QEICON;\r
- __I uint32_t QEISTAT;\r
- __IO uint32_t QEICONF;\r
- __I uint32_t QEIPOS;\r
- __IO uint32_t QEIMAXPOS;\r
- __IO uint32_t CMPOS0;\r
- __IO uint32_t CMPOS1;\r
- __IO uint32_t CMPOS2;\r
- __I uint32_t INXCNT;\r
- __IO uint32_t INXCMP;\r
- __IO uint32_t QEILOAD;\r
- __I uint32_t QEITIME;\r
- __I uint32_t QEIVEL;\r
- __I uint32_t QEICAP;\r
- __IO uint32_t VELCOMP;\r
- __IO uint32_t FILTER;\r
- uint32_t RESERVED0[998];\r
- __O uint32_t QEIIEC;\r
- __O uint32_t QEIIES;\r
- __I uint32_t QEIINTSTAT;\r
- __I uint32_t QEIIE;\r
- __O uint32_t QEICLR;\r
- __O uint32_t QEISET;\r
-} QEI_TypeDef;\r
-\r
-/*------------- Controller Area Network (CAN) --------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t mask[512]; /* ID Masks */\r
-} CANAF_RAM_TypeDef;\r
-\r
-typedef struct /* Acceptance Filter Registers */\r
-{\r
- __IO uint32_t AFMR;\r
- __IO uint32_t SFF_sa;\r
- __IO uint32_t SFF_GRP_sa;\r
- __IO uint32_t EFF_sa;\r
- __IO uint32_t EFF_GRP_sa;\r
- __IO uint32_t ENDofTable;\r
- __I uint32_t LUTerrAd;\r
- __I uint32_t LUTerr;\r
-} CANAF_TypeDef;\r
-\r
-typedef struct /* Central Registers */\r
-{\r
- __I uint32_t CANTxSR;\r
- __I uint32_t CANRxSR;\r
- __I uint32_t CANMSR;\r
-} CANCR_TypeDef;\r
-\r
-typedef struct /* Controller Registers */\r
-{\r
- __IO uint32_t MOD;\r
- __O uint32_t CMR;\r
- __IO uint32_t GSR;\r
- __I uint32_t ICR;\r
- __IO uint32_t IER;\r
- __IO uint32_t BTR;\r
- __IO uint32_t EWL;\r
- __I uint32_t SR;\r
- __IO uint32_t RFS;\r
- __IO uint32_t RID;\r
- __IO uint32_t RDA;\r
- __IO uint32_t RDB;\r
- __IO uint32_t TFI1;\r
- __IO uint32_t TID1;\r
- __IO uint32_t TDA1;\r
- __IO uint32_t TDB1;\r
- __IO uint32_t TFI2;\r
- __IO uint32_t TID2;\r
- __IO uint32_t TDA2;\r
- __IO uint32_t TDB2;\r
- __IO uint32_t TFI3;\r
- __IO uint32_t TID3;\r
- __IO uint32_t TDA3;\r
- __IO uint32_t TDB3;\r
-} CAN_TypeDef;\r
-\r
-/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/\r
-typedef struct /* Common Registers */\r
-{\r
- __I uint32_t DMACIntStat;\r
- __I uint32_t DMACIntTCStat;\r
- __O uint32_t DMACIntTCClear;\r
- __I uint32_t DMACIntErrStat;\r
- __O uint32_t DMACIntErrClr;\r
- __I uint32_t DMACRawIntTCStat;\r
- __I uint32_t DMACRawIntErrStat;\r
- __I uint32_t DMACEnbldChns;\r
- __IO uint32_t DMACSoftBReq;\r
- __IO uint32_t DMACSoftSReq;\r
- __IO uint32_t DMACSoftLBReq;\r
- __IO uint32_t DMACSoftLSReq;\r
- __IO uint32_t DMACConfig;\r
- __IO uint32_t DMACSync;\r
-} GPDMA_TypeDef;\r
-\r
-typedef struct /* Channel Registers */\r
-{\r
- __IO uint32_t DMACCSrcAddr;\r
- __IO uint32_t DMACCDestAddr;\r
- __IO uint32_t DMACCLLI;\r
- __IO uint32_t DMACCControl;\r
- __IO uint32_t DMACCConfig;\r
-} GPDMACH_TypeDef;\r
-\r
-/*------------- Universal Serial Bus (USB) -----------------------------------*/\r
-typedef struct\r
-{\r
- __I uint32_t HcRevision; /* USB Host Registers */\r
- __IO uint32_t HcControl;\r
- __IO uint32_t HcCommandStatus;\r
- __IO uint32_t HcInterruptStatus;\r
- __IO uint32_t HcInterruptEnable;\r
- __IO uint32_t HcInterruptDisable;\r
- __IO uint32_t HcHCCA;\r
- __I uint32_t HcPeriodCurrentED;\r
- __IO uint32_t HcControlHeadED;\r
- __IO uint32_t HcControlCurrentED;\r
- __IO uint32_t HcBulkHeadED;\r
- __IO uint32_t HcBulkCurrentED;\r
- __I uint32_t HcDoneHead;\r
- __IO uint32_t HcFmInterval;\r
- __I uint32_t HcFmRemaining;\r
- __I uint32_t HcFmNumber;\r
- __IO uint32_t HcPeriodicStart;\r
- __IO uint32_t HcLSTreshold;\r
- __IO uint32_t HcRhDescriptorA;\r
- __IO uint32_t HcRhDescriptorB;\r
- __IO uint32_t HcRhStatus;\r
- __IO uint32_t HcRhPortStatus1;\r
- __IO uint32_t HcRhPortStatus2;\r
- uint32_t RESERVED0[40];\r
- __I uint32_t Module_ID;\r
-\r
- __I uint32_t OTGIntSt; /* USB On-The-Go Registers */\r
- __IO uint32_t OTGIntEn;\r
- __O uint32_t OTGIntSet;\r
- __O uint32_t OTGIntClr;\r
- __IO uint32_t OTGStCtrl;\r
- __IO uint32_t OTGTmr;\r
- uint32_t RESERVED1[58];\r
-\r
- __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */\r
- __IO uint32_t USBDevIntEn;\r
- __O uint32_t USBDevIntClr;\r
- __O uint32_t USBDevIntSet;\r
-\r
- __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */\r
- __I uint32_t USBCmdData;\r
-\r
- __I uint32_t USBRxData; /* USB Device Transfer Registers */\r
- __O uint32_t USBTxData;\r
- __I uint32_t USBRxPLen;\r
- __O uint32_t USBTxPLen;\r
- __IO uint32_t USBCtrl;\r
- __O uint32_t USBDevIntPri;\r
-\r
- __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */\r
- __IO uint32_t USBEpIntEn;\r
- __O uint32_t USBEpIntClr;\r
- __O uint32_t USBEpIntSet;\r
- __O uint32_t USBEpIntPri;\r
-\r
- __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/\r
- __O uint32_t USBEpInd;\r
- __IO uint32_t USBMaxPSize;\r
-\r
- __I uint32_t USBDMARSt; /* USB Device DMA Registers */\r
- __O uint32_t USBDMARClr;\r
- __O uint32_t USBDMARSet;\r
- uint32_t RESERVED2[9];\r
- __IO uint32_t USBUDCAH;\r
- __I uint32_t USBEpDMASt;\r
- __O uint32_t USBEpDMAEn;\r
- __O uint32_t USBEpDMADis;\r
- __I uint32_t USBDMAIntSt;\r
- __IO uint32_t USBDMAIntEn;\r
- uint32_t RESERVED3[2];\r
- __I uint32_t USBEoTIntSt;\r
- __O uint32_t USBEoTIntClr;\r
- __O uint32_t USBEoTIntSet;\r
- __I uint32_t USBNDDRIntSt;\r
- __O uint32_t USBNDDRIntClr;\r
- __O uint32_t USBNDDRIntSet;\r
- __I uint32_t USBSysErrIntSt;\r
- __O uint32_t USBSysErrIntClr;\r
- __O uint32_t USBSysErrIntSet;\r
- uint32_t RESERVED4[15];\r
-\r
- __I uint32_t I2C_RX; /* USB OTG I2C Registers */\r
- __O uint32_t I2C_WO;\r
- __I uint32_t I2C_STS;\r
- __IO uint32_t I2C_CTL;\r
- __IO uint32_t I2C_CLKHI;\r
- __O uint32_t I2C_CLKLO;\r
- uint32_t RESERVED5[823];\r
-\r
- union {\r
- __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */\r
- __IO uint32_t OTGClkCtrl;\r
- };\r
- union {\r
- __I uint32_t USBClkSt;\r
- __I uint32_t OTGClkSt;\r
- };\r
-} USB_TypeDef;\r
-\r
-/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t MAC1; /* MAC Registers */\r
- __IO uint32_t MAC2;\r
- __IO uint32_t IPGT;\r
- __IO uint32_t IPGR;\r
- __IO uint32_t CLRT;\r
- __IO uint32_t MAXF;\r
- __IO uint32_t SUPP;\r
- __IO uint32_t TEST;\r
- __IO uint32_t MCFG;\r
- __IO uint32_t MCMD;\r
- __IO uint32_t MADR;\r
- __O uint32_t MWTD;\r
- __I uint32_t MRDD;\r
- __I uint32_t MIND;\r
- uint32_t RESERVED0[2];\r
- __IO uint32_t SA0;\r
- __IO uint32_t SA1;\r
- __IO uint32_t SA2;\r
- uint32_t RESERVED1[45];\r
- __IO uint32_t Command; /* Control Registers */\r
- __I uint32_t Status;\r
- __IO uint32_t RxDescriptor;\r
- __IO uint32_t RxStatus;\r
- __IO uint32_t RxDescriptorNumber;\r
- __I uint32_t RxProduceIndex;\r
- __IO uint32_t RxConsumeIndex;\r
- __IO uint32_t TxDescriptor;\r
- __IO uint32_t TxStatus;\r
- __IO uint32_t TxDescriptorNumber;\r
- __IO uint32_t TxProduceIndex;\r
- __I uint32_t TxConsumeIndex;\r
- uint32_t RESERVED2[10];\r
- __I uint32_t TSV0;\r
- __I uint32_t TSV1;\r
- __I uint32_t RSV;\r
- uint32_t RESERVED3[3];\r
- __IO uint32_t FlowControlCounter;\r
- __I uint32_t FlowControlStatus;\r
- uint32_t RESERVED4[34];\r
- __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */\r
- __IO uint32_t RxFilterWoLStatus;\r
- __IO uint32_t RxFilterWoLClear;\r
- uint32_t RESERVED5;\r
- __IO uint32_t HashFilterL;\r
- __IO uint32_t HashFilterH;\r
- uint32_t RESERVED6[882];\r
- __I uint32_t IntStatus; /* Module Control Registers */\r
- __IO uint32_t IntEnable;\r
- __O uint32_t IntClear;\r
- __O uint32_t IntSet;\r
- uint32_t RESERVED7;\r
- __IO uint32_t PowerDown;\r
- uint32_t RESERVED8;\r
- __IO uint32_t Module_ID;\r
-} EMAC_TypeDef;\r
-\r
-//#pragma no_anon_unions\r
-\r
-\r
-/******************************************************************************/\r
-/* Peripheral memory map */\r
-/******************************************************************************/\r
-/* Base addresses */\r
-#define FLASH_BASE (0x00000000UL)\r
-#define RAM_BASE (0x10000000UL)\r
-#define GPIO_BASE (0x2009C000UL)\r
-#define APB0_BASE (0x40000000UL)\r
-#define APB1_BASE (0x40080000UL)\r
-#define AHB_BASE (0x50000000UL)\r
-#define CM3_BASE (0xE0000000UL)\r
-\r
-/* APB0 peripherals */\r
-#define WDT_BASE (APB0_BASE + 0x00000)\r
-#define TIM0_BASE (APB0_BASE + 0x04000)\r
-#define TIM1_BASE (APB0_BASE + 0x08000)\r
-#define UART0_BASE (APB0_BASE + 0x0C000)\r
-#define UART1_BASE (APB0_BASE + 0x10000)\r
-#define PWM1_BASE (APB0_BASE + 0x18000)\r
-#define I2C0_BASE (APB0_BASE + 0x1C000)\r
-#define SPI_BASE (APB0_BASE + 0x20000)\r
-#define RTC_BASE (APB0_BASE + 0x24000)\r
-#define GPIOINT_BASE (APB0_BASE + 0x28080)\r
-#define PINCON_BASE (APB0_BASE + 0x2C000)\r
-#define SSP1_BASE (APB0_BASE + 0x30000)\r
-#define ADC_BASE (APB0_BASE + 0x34000)\r
-#define CANAF_RAM_BASE (APB0_BASE + 0x38000)\r
-#define CANAF_BASE (APB0_BASE + 0x3C000)\r
-#define CANCR_BASE (APB0_BASE + 0x40000)\r
-#define CAN1_BASE (APB0_BASE + 0x44000)\r
-#define CAN2_BASE (APB0_BASE + 0x48000)\r
-#define I2C1_BASE (APB0_BASE + 0x5C000)\r
-\r
-/* APB1 peripherals */\r
-#define SSP0_BASE (APB1_BASE + 0x08000)\r
-#define DAC_BASE (APB1_BASE + 0x0C000)\r
-#define TIM2_BASE (APB1_BASE + 0x10000)\r
-#define TIM3_BASE (APB1_BASE + 0x14000)\r
-#define UART2_BASE (APB1_BASE + 0x18000)\r
-#define UART3_BASE (APB1_BASE + 0x1C000)\r
-#define I2C2_BASE (APB1_BASE + 0x20000)\r
-#define I2S_BASE (APB1_BASE + 0x28000)\r
-#define RIT_BASE (APB1_BASE + 0x30000)\r
-#define MCPWM_BASE (APB1_BASE + 0x38000)\r
-#define QEI_BASE (APB1_BASE + 0x3C000)\r
-#define SC_BASE (APB1_BASE + 0x7C000)\r
-\r
-/* AHB peripherals */\r
-#define EMAC_BASE (AHB_BASE + 0x00000)\r
-#define GPDMA_BASE (AHB_BASE + 0x04000)\r
-#define GPDMACH0_BASE (AHB_BASE + 0x04100)\r
-#define GPDMACH1_BASE (AHB_BASE + 0x04120)\r
-#define GPDMACH2_BASE (AHB_BASE + 0x04140)\r
-#define GPDMACH3_BASE (AHB_BASE + 0x04160)\r
-#define GPDMACH4_BASE (AHB_BASE + 0x04180)\r
-#define GPDMACH5_BASE (AHB_BASE + 0x041A0)\r
-#define GPDMACH6_BASE (AHB_BASE + 0x041C0)\r
-#define GPDMACH7_BASE (AHB_BASE + 0x041E0)\r
-#define USB_BASE (AHB_BASE + 0x0C000)\r
-\r
-/* GPIOs */\r
-#define GPIO0_BASE (GPIO_BASE + 0x00000)\r
-#define GPIO1_BASE (GPIO_BASE + 0x00020)\r
-#define GPIO2_BASE (GPIO_BASE + 0x00040)\r
-#define GPIO3_BASE (GPIO_BASE + 0x00060)\r
-#define GPIO4_BASE (GPIO_BASE + 0x00080)\r
-\r
-\r
-/******************************************************************************/\r
-/* Peripheral declaration */\r
-/******************************************************************************/\r
-#define SC (( SC_TypeDef *) SC_BASE)\r
-#define GPIO0 (( GPIO_TypeDef *) GPIO0_BASE)\r
-#define GPIO1 (( GPIO_TypeDef *) GPIO1_BASE)\r
-#define GPIO2 (( GPIO_TypeDef *) GPIO2_BASE)\r
-#define GPIO3 (( GPIO_TypeDef *) GPIO3_BASE)\r
-#define GPIO4 (( GPIO_TypeDef *) GPIO4_BASE)\r
-#define WDT (( WDT_TypeDef *) WDT_BASE)\r
-#define TIM0 (( TIM_TypeDef *) TIM0_BASE)\r
-#define TIM1 (( TIM_TypeDef *) TIM1_BASE)\r
-#define TIM2 (( TIM_TypeDef *) TIM2_BASE)\r
-#define TIM3 (( TIM_TypeDef *) TIM3_BASE)\r
-#define RIT (( RIT_TypeDef *) RIT_BASE)\r
-#define UART0 (( UART_TypeDef *) UART0_BASE)\r
-#define UART1 (( UART1_TypeDef *) UART1_BASE)\r
-#define UART2 (( UART_TypeDef *) UART2_BASE)\r
-#define UART3 (( UART_TypeDef *) UART3_BASE)\r
-#define PWM1 (( PWM_TypeDef *) PWM1_BASE)\r
-#define I2C0 (( I2C_TypeDef *) I2C0_BASE)\r
-#define I2C1 (( I2C_TypeDef *) I2C1_BASE)\r
-#define I2C2 (( I2C_TypeDef *) I2C2_BASE)\r
-#define I2S (( I2S_TypeDef *) I2S_BASE)\r
-#define SPI (( SPI_TypeDef *) SPI_BASE)\r
-#define RTC (( RTC_TypeDef *) RTC_BASE)\r
-#define GPIOINT (( GPIOINT_TypeDef *) GPIOINT_BASE)\r
-#define PINCON (( PINCON_TypeDef *) PINCON_BASE)\r
-#define SSP0 (( SSP_TypeDef *) SSP0_BASE)\r
-#define SSP1 (( SSP_TypeDef *) SSP1_BASE)\r
-#define ADC (( ADC_TypeDef *) ADC_BASE)\r
-#define DAC (( DAC_TypeDef *) DAC_BASE)\r
-#define CANAF_RAM ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE)\r
-#define CANAF (( CANAF_TypeDef *) CANAF_BASE)\r
-#define CANCR (( CANCR_TypeDef *) CANCR_BASE)\r
-#define CAN1 (( CAN_TypeDef *) CAN1_BASE)\r
-#define CAN2 (( CAN_TypeDef *) CAN2_BASE)\r
-#define MCPWM (( MCPWM_TypeDef *) MCPWM_BASE)\r
-#define QEI (( QEI_TypeDef *) QEI_BASE)\r
-#define EMAC (( EMAC_TypeDef *) EMAC_BASE)\r
-#define GPDMA (( GPDMA_TypeDef *) GPDMA_BASE)\r
-#define GPDMACH0 (( GPDMACH_TypeDef *) GPDMACH0_BASE)\r
-#define GPDMACH1 (( GPDMACH_TypeDef *) GPDMACH1_BASE)\r
-#define GPDMACH2 (( GPDMACH_TypeDef *) GPDMACH2_BASE)\r
-#define GPDMACH3 (( GPDMACH_TypeDef *) GPDMACH3_BASE)\r
-#define GPDMACH4 (( GPDMACH_TypeDef *) GPDMACH4_BASE)\r
-#define GPDMACH5 (( GPDMACH_TypeDef *) GPDMACH5_BASE)\r
-#define GPDMACH6 (( GPDMACH_TypeDef *) GPDMACH6_BASE)\r
-#define GPDMACH7 (( GPDMACH_TypeDef *) GPDMACH7_BASE)\r
-#define USB (( USB_TypeDef *) USB_BASE)\r
-\r
-#endif // __LPC17xx_H__\r
+#endif // __LPC17xx_H\r
projects / freertos / commitdiff