* the target.
*/
- arm11->target->state = TARGET_HALTED;
- arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
+ arm11->arm.target->state = TARGET_HALTED;
+ arm11->arm.target->debug_reason =
+ arm11_get_DSCR_debug_reason(*dscr);
}
else
{
- arm11->target->state = TARGET_RUNNING;
- arm11->target->debug_reason = DBG_REASON_NOTHALTED;
+ arm11->arm.target->state = TARGET_RUNNING;
+ arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
}
arm11_sc7_clear_vbw(arm11);
armv4_5_init_arch_info(target, &arm11->arm);
- arm11->target = target;
-
arm11->jtag_info.tap = target->tap;
arm11->jtag_info.scann_size = 5;
arm11->jtag_info.scann_instr = ARM11_SCAN_N;
/** \todo TODO: reserve one brp slot if we allow breakpoints during step */
arm11->free_brps = arm11->brp;
- arm11->free_wrps = arm11->wrp;
LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
device_id, implementor, didr);
/** Load a register that is marked !valid in the register cache */
static int arm11_get_reg(struct reg *reg)
{
- struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
+ struct arm11_reg_state *r = reg->arch_info;
+ struct target *target = r->target;
if (target->state != TARGET_HALTED)
{
/** Change a value in the register cache */
static int arm11_set_reg(struct reg *reg, uint8_t *buf)
{
- struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target;
+ struct arm11_reg_state *r = reg->arch_info;
+ struct target *target = r->target;
struct arm11_common *arm11 = target_to_arm11(target);
// const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
struct arm11_common
{
struct arm arm;
- struct target * target; /**< Reference back to the owner */
/** Debug module state. */
struct arm_dpm dpm;
- /** \name Processor type detection */
- /*@{*/
-
size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
-
- /*@}*/
+ size_t free_brps; /**< Number of breakpoints allocated */
uint32_t last_dscr; /**< Last retrieved DSCR value;
Use only for debug message generation */
/*@}*/
- size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
- size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
// GA
struct reg_cache *core_cache;
*/
void arm11_setup_field(struct arm11_common * arm11, int num_bits, void * out_data, void * in_data, struct scan_field * field)
{
- field->tap = arm11->target->tap;
+ field->tap = arm11->arm.target->tap;
field->num_bits = num_bits;
field->out_value = out_data;
field->in_value = in_data;
*/
void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state)
{
- struct jtag_tap *tap;
- tap = arm11->target->tap;
+ struct jtag_tap *tap = arm11->arm.target->tap;
if (buf_get_u32(tap->cur_instr, 0, 5) == instr)
{