#define configUSE_IDLE_HOOK 0\r
#define configUSE_TICK_HOOK 0\r
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 96000000 )\r
-#define configCPU_PERIPH_HZ ( ( unsigned portLONG ) 96000000 )\r
+#define configCPU_PERIPH_HZ ( ( unsigned portLONG ) 48000000 )\r
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 180 )\r
/* FMI Waite States */\r
FMI_Config( FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE, FMI_LVD_ENABLE, FMI_FREQ_HIGH ); \r
\r
- /* Configure the FPLL = 96MHz */\r
+ /* Configure the FPLL = 96MHz, and APB to 48MHz. */\r
+ SCU_PCLKDivisorConfig( SCU_PCLK_Div2 );\r
SCU_PLLFactorsConfig( 192, 25, 2 ); \r
SCU_PLLCmd( ENABLE );\r
SCU_MCLKSourceConfig( SCU_MCLK_PLL );\r