actually accumulator addressing. These went through and caused the
optimizer to behave strangely.
git-svn-id: svn://svn.cc65.org/cc65/trunk@3164
b7a2c559-68d2-44c3-8de9-
860c34a00d81
switch (*L) {
case '\0':
- /* Implicit */
- AM = AM65_IMP;
+ /* Implicit or accu */
+ if (OPC->Info & OF_NOIMP) {
+ AM = AM65_ACC;
+ } else {
+ AM = AM65_IMP;
+ }
break;
case '#':
0, /* size */
REG_A, /* use */
REG_A, /* chg */
- OF_SETF /* flags */
+ OF_SETF /* flags */
},
{ OP65_AND, /* opcode */
"and", /* mnemonic */
0, /* size */
REG_A, /* use */
REG_A, /* chg */
- OF_SETF /* flags */
+ OF_SETF /* flags */
},
{ OP65_ASL, /* opcode */
"asl", /* mnemonic */
0, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
- OF_SETF /* flags */
+ OF_SETF | OF_NOIMP /* flags */
},
{ OP65_BCC, /* opcode */
"bcc", /* mnemonic */
2, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
- OF_CBRA /* flags */
+ OF_CBRA /* flags */
},
{ OP65_CLC, /* opcode */
"clc", /* mnemonic */
0, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
- OF_SETF /* flags */
+ OF_SETF | OF_NOIMP /* flags */
},
{ OP65_DEX, /* opcode */
"dex", /* mnemonic */
0, /* size */
REG_A, /* use */
REG_A, /* chg */
- OF_SETF /* flags */
+ OF_SETF /* flags */
},
{ OP65_INA, /* opcode */
"ina", /* mnemonic */
0, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
- OF_SETF /* flags */
+ OF_SETF | OF_NOIMP /* flags */
},
{ OP65_INX, /* opcode */
"inx", /* mnemonic */
5, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
- OF_CBRA | OF_LBRA /* flags */
+ OF_CBRA | OF_LBRA /* flags */
},
{ OP65_JVS, /* opcode */
"jvs", /* mnemonic */
0, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
- OF_SETF /* flags */
+ OF_SETF | OF_NOIMP /* flags */
},
{ OP65_NOP, /* opcode */
"nop", /* mnemonic */
1, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
- OF_NONE /* flags */
+ OF_NONE /* flags */
},
{ OP65_PLX, /* opcode */
"plx", /* mnemonic */
0, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
- OF_SETF /* flags */
+ OF_SETF | OF_NOIMP /* flags */
},
{ OP65_ROR, /* opcode */
"ror", /* mnemonic */
0, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
- OF_SETF /* flags */
+ OF_SETF | OF_NOIMP /* flags */
},
/* Mark RTI as "uses all registers but doesn't change them", so the
* optimizer won't remove preceeding loads.
1, /* size */
REG_AXY, /* use */
REG_NONE, /* chg */
- OF_RET /* flags */
+ OF_RET /* flags */
},
{ OP65_RTS, /* opcode */
"rts", /* mnemonic */
1, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
- OF_RET /* flags */
+ OF_RET /* flags */
},
{ OP65_SBC, /* opcode */
"sbc", /* mnemonic */
0, /* size */
REG_A, /* use */
REG_A, /* chg */
- OF_SETF /* flags */
+ OF_SETF /* flags */
},
{ OP65_SEC, /* opcode */
"sec", /* mnemonic */
1, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
- OF_NONE /* flags */
+ OF_NONE /* flags */
},
{ OP65_SED, /* opcode */
"sed", /* mnemonic */
1, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
- OF_NONE /* flags */
+ OF_NONE /* flags */
},
{ OP65_SEI, /* opcode */
"sei", /* mnemonic */
1, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
- OF_NONE /* flags */
+ OF_NONE /* flags */
},
{ OP65_STA, /* opcode */
"sta", /* mnemonic */
0, /* size */
REG_A, /* use */
REG_NONE, /* chg */
- OF_STORE /* flags */
+ OF_STORE /* flags */
},
{ OP65_STX, /* opcode */
"stx", /* mnemonic */
0, /* size */
REG_X, /* use */
REG_NONE, /* chg */
- OF_STORE /* flags */
+ OF_STORE /* flags */
},
{ OP65_STY, /* opcode */
"sty", /* mnemonic */
0, /* size */
REG_Y, /* use */
REG_NONE, /* chg */
- OF_STORE /* flags */
+ OF_STORE /* flags */
},
{ OP65_STZ, /* opcode */
"stz", /* mnemonic */
0, /* size */
REG_NONE, /* use */
REG_NONE, /* chg */
- OF_STORE /* flags */
+ OF_STORE /* flags */
},
{ OP65_TAX, /* opcode */
"tax", /* mnemonic */
0, /* size */
REG_A, /* use */
REG_NONE, /* chg */
- OF_SETF /* flags */
+ OF_SETF /* flags */
},
{ OP65_TSX, /* opcode */
"tsx", /* mnemonic */
1, /* size */
REG_X, /* use */
REG_NONE, /* chg */
- OF_XFR /* flags */
+ OF_XFR /* flags */
},
{ OP65_TYA, /* opcode */
"tya", /* mnemonic */
#define OF_REG_INCDEC 0x0400U /* A register increment or decrement */
#define OF_SETF 0x0800U /* Insn will set all load flags (not carry) */
#define OF_CMP 0x1000U /* A compare A/X/Y instruction */
+#define OF_NOIMP 0x2000U /* Implicit addressing mode is actually A */
/* Combined infos */
#define OF_BRA (OF_UBRA | OF_CBRA) /* Operation is a jump/branch */