]> git.sur5r.net Git - openocd/commitdiff
Michael Bruck:
authoroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Thu, 6 Mar 2008 12:01:52 +0000 (12:01 +0000)
committeroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Thu, 6 Mar 2008 12:01:52 +0000 (12:01 +0000)
- force simulate_reset_on_next_halt when target state is initially detected
- print out method of debug entry
- fix VCR activation (didn't work before)

git-svn-id: svn://svn.berlios.de/openocd/trunk@452 b42882b7-edfa-0310-969c-e2dbd0fdcd60

src/target/arm11.c
src/target/arm11_dbgtap.c

index 45066031a3e6ee9a9feb14c6c9e0792574c91d62..9c3d1f28d6062d1b1e3031807ccc590a21d1600a 100644 (file)
@@ -331,8 +331,14 @@ void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
 
        /* add further reset initialization here */
 
+       arm11->simulate_reset_on_next_halt = true;
+
        if (*dscr & ARM11_DSCR_CORE_HALTED)
        {
+           /** \todo TODO: this needs further scrutiny because
+             * arm11_on_enter_debug_state() never gets properly called
+             */
+
            arm11->target->state        = TARGET_HALTED;
            arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
        }
index bb4695e03f7f917e3622362508cec0cd3d6ee694..8eeba797a96c9d0640a8e1d895158a739641caf7 100644 (file)
@@ -274,14 +274,32 @@ enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
 {
     switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
     {
-    case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT:                        return DBG_REASON_DBGRQ;
-    case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT:          return DBG_REASON_BREAKPOINT;
-    case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT:          return DBG_REASON_WATCHPOINT;
-    case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION:    return DBG_REASON_BREAKPOINT;
-    case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ:              return DBG_REASON_DBGRQ;
-    case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH:                return DBG_REASON_BREAKPOINT;
+    case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT:
+       INFO("Debug entry: JTAG HALT");
+       return DBG_REASON_DBGRQ;
+
+    case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT:
+       INFO("Debug entry: breakpoint");
+       return DBG_REASON_BREAKPOINT;
+
+    case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT:
+       INFO("Debug entry: watchpoint");
+       return DBG_REASON_WATCHPOINT;
+
+    case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION:
+       INFO("Debug entry: BKPT instruction");
+       return DBG_REASON_BREAKPOINT;
+
+    case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ:
+       INFO("Debug entry: EDBGRQ signal");
+       return DBG_REASON_DBGRQ;
+
+    case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH:
+       INFO("Debug entry: VCR vector catch");
+       return DBG_REASON_BREAKPOINT;
 
     default:
+       INFO("Debug entry: unknown");
        return DBG_REASON_DBGRQ;
     }
 };
@@ -752,7 +770,7 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value)
 {
     arm11_sc7_action_t         set_vcr;
 
-    set_vcr.write              = 0;
+    set_vcr.write              = true;
     set_vcr.address            = ARM11_SC7_VCR;
     set_vcr.value              = value;