-#ifndef __LPC17xx_H\r
-#define __LPC17xx_H\r
-\r
-/* System Control Block (SCB) includes:\r
- Flash Accelerator Module, Clocking and Power Control, External Interrupts,\r
- Reset, System Control and Status\r
-*/\r
-#define SCB_BASE_ADDR 0x400FC000\r
-\r
-#define PCONP_PCTIM0 0x00000002\r
-#define PCONP_PCTIM1 0x00000004\r
-#define PCONP_PCUART0 0x00000008\r
-#define PCONP_PCUART1 0x00000010\r
-#define PCONP_PCPWM1 0x00000040\r
-#define PCONP_PCI2C0 0x00000080\r
-#define PCONP_PCSPI 0x00000100\r
-#define PCONP_PCRTC 0x00000200\r
-#define PCONP_PCSSP1 0x00000400\r
-#define PCONP_PCAD 0x00001000\r
-#define PCONP_PCCAN1 0x00002000\r
-#define PCONP_PCCAN2 0x00004000\r
-#define PCONP_PCGPIO 0x00008000\r
-#define PCONP_PCRIT 0x00010000\r
-#define PCONP_PCMCPWM 0x00020000\r
-#define PCONP_PCQEI 0x00040000\r
-#define PCONP_PCI2C1 0x00080000\r
-#define PCONP_PCSSP0 0x00200000\r
-#define PCONP_PCTIM2 0x00400000\r
-#define PCONP_PCTIM3 0x00800000\r
-#define PCONP_PCUART2 0x01000000\r
-#define PCONP_PCUART3 0x02000000\r
-#define PCONP_PCI2C2 0x04000000\r
-#define PCONP_PCI2S 0x08000000\r
-#define PCONP_PCGPDMA 0x20000000\r
-#define PCONP_PCENET 0x40000000\r
-#define PCONP_PCUSB 0x80000000\r
-\r
-#define PLLCON_PLLE 0x00000001\r
-#define PLLCON_PLLC 0x00000002\r
-#define PLLCON_MASK 0x00000003\r
-\r
-#define PLLCFG_MUL1 0x00000000\r
-#define PLLCFG_MUL2 0x00000001\r
-#define PLLCFG_MUL3 0x00000002\r
-#define PLLCFG_MUL4 0x00000003\r
-#define PLLCFG_MUL5 0x00000004\r
-#define PLLCFG_MUL6 0x00000005\r
-#define PLLCFG_MUL7 0x00000006\r
-#define PLLCFG_MUL8 0x00000007\r
-#define PLLCFG_MUL9 0x00000008\r
-#define PLLCFG_MUL10 0x00000009\r
-#define PLLCFG_MUL11 0x0000000A\r
-#define PLLCFG_MUL12 0x0000000B\r
-#define PLLCFG_MUL13 0x0000000C\r
-#define PLLCFG_MUL14 0x0000000D\r
-#define PLLCFG_MUL15 0x0000000E\r
-#define PLLCFG_MUL16 0x0000000F\r
-#define PLLCFG_MUL17 0x00000010\r
-#define PLLCFG_MUL18 0x00000011\r
-#define PLLCFG_MUL19 0x00000012\r
-#define PLLCFG_MUL20 0x00000013\r
-#define PLLCFG_MUL21 0x00000014\r
-#define PLLCFG_MUL22 0x00000015\r
-#define PLLCFG_MUL23 0x00000016\r
-#define PLLCFG_MUL24 0x00000017\r
-#define PLLCFG_MUL25 0x00000018\r
-#define PLLCFG_MUL26 0x00000019\r
-#define PLLCFG_MUL27 0x0000001A\r
-#define PLLCFG_MUL28 0x0000001B\r
-#define PLLCFG_MUL29 0x0000001C\r
-#define PLLCFG_MUL30 0x0000001D\r
-#define PLLCFG_MUL31 0x0000001E\r
-#define PLLCFG_MUL32 0x0000001F\r
-#define PLLCFG_MUL33 0x00000020\r
-#define PLLCFG_MUL34 0x00000021\r
-#define PLLCFG_MUL35 0x00000022\r
-#define PLLCFG_MUL36 0x00000023\r
-\r
-#define PLLCFG_DIV1 0x00000000\r
-#define PLLCFG_DIV2 0x00010000\r
-#define PLLCFG_DIV3 0x00020000\r
-#define PLLCFG_DIV4 0x00030000\r
-#define PLLCFG_DIV5 0x00040000\r
-#define PLLCFG_DIV6 0x00050000\r
-#define PLLCFG_DIV7 0x00060000\r
-#define PLLCFG_DIV8 0x00070000\r
-#define PLLCFG_DIV9 0x00080000\r
-#define PLLCFG_DIV10 0x00090000\r
-#define PLLCFG_MASK 0x00FF7FFF\r
-\r
-#define PLLSTAT_MSEL_MASK 0x00007FFF\r
-#define PLLSTAT_NSEL_MASK 0x00FF0000\r
-\r
-#define PLLSTAT_PLLE (1 << 24)\r
-#define PLLSTAT_PLLC (1 << 25)\r
-#define PLLSTAT_PLOCK (1 << 26)\r
-\r
-#define PLLFEED_FEED1 0x000000AA\r
-#define PLLFEED_FEED2 0x00000055\r
-\r
-#define NVIC_IRQ_WDT 0u // IRQ0, exception number 16\r
-#define NVIC_IRQ_TIMER0 1u // IRQ1, exception number 17\r
-#define NVIC_IRQ_TIMER1 2u // IRQ2, exception number 18\r
-#define NVIC_IRQ_TIMER2 3u // IRQ3, exception number 19\r
-#define NVIC_IRQ_TIMER3 4u // IRQ4, exception number 20\r
-#define NVIC_IRQ_UART0 5u // IRQ5, exception number 21\r
-#define NVIC_IRQ_UART1 6u // IRQ6, exception number 22\r
-#define NVIC_IRQ_UART2 7u // IRQ7, exception number 23\r
-#define NVIC_IRQ_UART3 8u // IRQ8, exception number 24\r
-#define NVIC_IRQ_PWM1 9u // IRQ9, exception number 25\r
-#define NVIC_IRQ_I2C0 10u // IRQ10, exception number 26\r
-#define NVIC_IRQ_I2C1 11u // IRQ11, exception number 27\r
-#define NVIC_IRQ_I2C2 12u // IRQ12, exception number 28\r
-#define NVIC_IRQ_SPI 13u // IRQ13, exception number 29\r
-#define NVIC_IRQ_SSP0 14u // IRQ14, exception number 30\r
-#define NVIC_IRQ_SSP1 15u // IRQ15, exception number 31\r
-#define NVIC_IRQ_PLL0 16u // IRQ16, exception number 32\r
-#define NVIC_IRQ_RTC 17u // IRQ17, exception number 33\r
-#define NVIC_IRQ_EINT0 18u // IRQ18, exception number 34\r
-#define NVIC_IRQ_EINT1 19u // IRQ19, exception number 35\r
-#define NVIC_IRQ_EINT2 20u // IRQ20, exception number 36\r
-#define NVIC_IRQ_EINT3 21u // IRQ21, exception number 37\r
-#define NVIC_IRQ_ADC 22u // IRQ22, exception number 38\r
-#define NVIC_IRQ_BOD 23u // IRQ23, exception number 39\r
-#define NVIC_IRQ_USB 24u // IRQ24, exception number 40\r
-#define NVIC_IRQ_CAN 25u // IRQ25, exception number 41\r
-#define NVIC_IRQ_GPDMA 26u // IRQ26, exception number 42\r
-#define NVIC_IRQ_I2S 27u // IRQ27, exception number 43\r
-#define NVIC_IRQ_ETHERNET 28u // IRQ28, exception number 44\r
-#define NVIC_IRQ_RIT 29u // IRQ29, exception number 45\r
-#define NVIC_IRQ_MCPWM 30u // IRQ30, exception number 46\r
-#define NVIC_IRQ_QE 31u // IRQ31, exception number 47\r
-#define NVIC_IRQ_PLL1 32u // IRQ32, exception number 48\r
-#define NVIC_IRQ_USB_ACT 33u // IRQ33, exception number 49\r
-#define NVIC_IRQ_CAN_ACT 34u // IRQ34, exception number 50\r
-\r
-\r
-#endif // __LPC17xx_H\r
-\r
-\r
-#ifndef CMSIS_17xx_H\r
-#define CMSIS_17xx_H\r
-\r
-/******************************************************************************\r
- * @file: LPC17xx.h\r
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for\r
+/**************************************************************************//**\r
+ * @file LPC17xx.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for \r
* NXP LPC17xx Device Series\r
- * @version: V1.1\r
- * @date: 14th May 2009\r
- *----------------------------------------------------------------------------\r
+ * @version: V1.09\r
+ * @date: 17. March 2010\r
+\r
*\r
- * Copyright (C) 2008 ARM Limited. All rights reserved.\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
*\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M3\r
- * processor based microcontrollers. This file can be freely distributed\r
- * within development tools that are supporting such ARM based processors.\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
*\r
+ * @par\r
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */\r
QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */\r
PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */\r
+ USBActivity_IRQn = 33, /* USB Activity interrupt */\r
+ CANActivity_IRQn = 34, /* CAN Activity interrupt */\r
} IRQn_Type;\r
\r
\r
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
\r
\r
-//#include "..\core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "core_cm3.h"\r
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
#include "system_LPC17xx.h" /* System Header */\r
\r
\r
-\r
-/**\r
- * Initialize the system clock\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * @brief Setup the microcontroller system.\r
- * Initialize the System and update the SystemFrequency variable.\r
- */\r
-extern void SystemInit (void);\r
-\r
-\r
/******************************************************************************/\r
/* Device Specific Peripheral registers structures */\r
/******************************************************************************/\r
\r
+#if defined ( __CC_ARM )\r
+#pragma anon_unions\r
+#endif\r
+\r
/*------------- System Control (SC) ------------------------------------------*/\r
typedef struct\r
{\r
__IO uint32_t CCLKCFG;\r
__IO uint32_t USBCLKCFG;\r
__IO uint32_t CLKSRCSEL;\r
- uint32_t RESERVED4[12];\r
+ __IO uint32_t CANSLEEPCLR;\r
+ __IO uint32_t CANWAKEFLAGS;\r
+ uint32_t RESERVED4[10];\r
__IO uint32_t EXTINT; /* External Interrupts */\r
uint32_t RESERVED5;\r
__IO uint32_t EXTMODE;\r
__IO uint32_t PCLKSEL1;\r
uint32_t RESERVED8[4];\r
__IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */\r
- uint32_t RESERVED9;\r
+ __IO uint32_t DMAREQSEL;\r
__IO uint32_t CLKOUTCFG; /* Clock Output Configuration */\r
- } SC_TypeDef;\r
+ } LPC_SC_TypeDef;\r
\r
/*------------- Pin Connect Block (PINCON) -----------------------------------*/\r
typedef struct\r
__IO uint32_t PINMODE_OD2;\r
__IO uint32_t PINMODE_OD3;\r
__IO uint32_t PINMODE_OD4;\r
-} PINCON_TypeDef;\r
+ __IO uint32_t I2CPADCFG;\r
+} LPC_PINCON_TypeDef;\r
\r
/*------------- General Purpose Input/Output (GPIO) --------------------------*/\r
typedef struct\r
{\r
- __IO uint32_t FIODIR;\r
- uint32_t RESERVED0[3];\r
- __IO uint32_t FIOMASK;\r
- __IO uint32_t FIOPIN;\r
- __IO uint32_t FIOSET;\r
- __O uint32_t FIOCLR;\r
-} GPIO_TypeDef;\r
+ union {\r
+ __IO uint32_t FIODIR;\r
+ struct {\r
+ __IO uint16_t FIODIRL;\r
+ __IO uint16_t FIODIRH;\r
+ };\r
+ struct {\r
+ __IO uint8_t FIODIR0;\r
+ __IO uint8_t FIODIR1;\r
+ __IO uint8_t FIODIR2;\r
+ __IO uint8_t FIODIR3;\r
+ };\r
+ };\r
+ uint32_t RESERVED0[3];\r
+ union {\r
+ __IO uint32_t FIOMASK;\r
+ struct {\r
+ __IO uint16_t FIOMASKL;\r
+ __IO uint16_t FIOMASKH;\r
+ };\r
+ struct {\r
+ __IO uint8_t FIOMASK0;\r
+ __IO uint8_t FIOMASK1;\r
+ __IO uint8_t FIOMASK2;\r
+ __IO uint8_t FIOMASK3;\r
+ };\r
+ };\r
+ union {\r
+ __IO uint32_t FIOPIN;\r
+ struct {\r
+ __IO uint16_t FIOPINL;\r
+ __IO uint16_t FIOPINH;\r
+ };\r
+ struct {\r
+ __IO uint8_t FIOPIN0;\r
+ __IO uint8_t FIOPIN1;\r
+ __IO uint8_t FIOPIN2;\r
+ __IO uint8_t FIOPIN3;\r
+ };\r
+ };\r
+ union {\r
+ __IO uint32_t FIOSET;\r
+ struct {\r
+ __IO uint16_t FIOSETL;\r
+ __IO uint16_t FIOSETH;\r
+ };\r
+ struct {\r
+ __IO uint8_t FIOSET0;\r
+ __IO uint8_t FIOSET1;\r
+ __IO uint8_t FIOSET2;\r
+ __IO uint8_t FIOSET3;\r
+ };\r
+ };\r
+ union {\r
+ __O uint32_t FIOCLR;\r
+ struct {\r
+ __O uint16_t FIOCLRL;\r
+ __O uint16_t FIOCLRH;\r
+ };\r
+ struct {\r
+ __O uint8_t FIOCLR0;\r
+ __O uint8_t FIOCLR1;\r
+ __O uint8_t FIOCLR2;\r
+ __O uint8_t FIOCLR3;\r
+ };\r
+ };\r
+} LPC_GPIO_TypeDef;\r
\r
typedef struct\r
{\r
__O uint32_t IO2IntClr;\r
__IO uint32_t IO2IntEnR;\r
__IO uint32_t IO2IntEnF;\r
-} GPIOINT_TypeDef;\r
+} LPC_GPIOINT_TypeDef;\r
\r
/*------------- Timer (TIM) --------------------------------------------------*/\r
typedef struct\r
__I uint32_t CR1;\r
uint32_t RESERVED0[2];\r
__IO uint32_t EMR;\r
- uint32_t RESERVED1[24];\r
+ uint32_t RESERVED1[12];\r
__IO uint32_t CTCR;\r
-} TIM_TypeDef;\r
+} LPC_TIM_TypeDef;\r
\r
/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/\r
typedef struct\r
__I uint32_t CR1;\r
__I uint32_t CR2;\r
__I uint32_t CR3;\r
+ uint32_t RESERVED0;\r
__IO uint32_t MR4;\r
__IO uint32_t MR5;\r
__IO uint32_t MR6;\r
__IO uint32_t PCR;\r
__IO uint32_t LER;\r
- uint32_t RESERVED0[7];\r
+ uint32_t RESERVED1[7];\r
__IO uint32_t CTCR;\r
-} PWM_TypeDef;\r
+} LPC_PWM_TypeDef;\r
\r
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/\r
typedef struct\r
};\r
__IO uint8_t LCR;\r
uint8_t RESERVED1[7];\r
- __IO uint8_t LSR;\r
+ __I uint8_t LSR;\r
uint8_t RESERVED2[7];\r
__IO uint8_t SCR;\r
uint8_t RESERVED3[3];\r
__IO uint8_t FDR;\r
uint8_t RESERVED5[7];\r
__IO uint8_t TER;\r
- uint8_t RESERVED6[27];\r
- __IO uint8_t RS485CTRL;\r
- uint8_t RESERVED7[3];\r
- __IO uint8_t ADRMATCH;\r
-} UART_TypeDef;\r
+ uint8_t RESERVED6[39];\r
+ __IO uint32_t FIFOLVL;\r
+} LPC_UART_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ union {\r
+ __I uint8_t RBR;\r
+ __O uint8_t THR;\r
+ __IO uint8_t DLL;\r
+ uint32_t RESERVED0;\r
+ };\r
+ union {\r
+ __IO uint8_t DLM;\r
+ __IO uint32_t IER;\r
+ };\r
+ union {\r
+ __I uint32_t IIR;\r
+ __O uint8_t FCR;\r
+ };\r
+ __IO uint8_t LCR;\r
+ uint8_t RESERVED1[7];\r
+ __I uint8_t LSR;\r
+ uint8_t RESERVED2[7];\r
+ __IO uint8_t SCR;\r
+ uint8_t RESERVED3[3];\r
+ __IO uint32_t ACR;\r
+ __IO uint8_t ICR;\r
+ uint8_t RESERVED4[3];\r
+ __IO uint8_t FDR;\r
+ uint8_t RESERVED5[7];\r
+ __IO uint8_t TER;\r
+ uint8_t RESERVED6[39];\r
+ __IO uint32_t FIFOLVL;\r
+} LPC_UART0_TypeDef;\r
\r
typedef struct\r
{\r
uint8_t RESERVED1[3];\r
__IO uint8_t MCR;\r
uint8_t RESERVED2[3];\r
- __IO uint8_t LSR;\r
+ __I uint8_t LSR;\r
uint8_t RESERVED3[3];\r
- __IO uint8_t MSR;\r
+ __I uint8_t MSR;\r
uint8_t RESERVED4[3];\r
__IO uint8_t SCR;\r
uint8_t RESERVED5[3];\r
__IO uint8_t ADRMATCH;\r
uint8_t RESERVED10[3];\r
__IO uint8_t RS485DLY;\r
-} UART1_TypeDef;\r
+ uint8_t RESERVED11[3];\r
+ __IO uint32_t FIFOLVL;\r
+} LPC_UART1_TypeDef;\r
\r
/*------------- Serial Peripheral Interface (SPI) ----------------------------*/\r
typedef struct\r
__IO uint32_t SPCCR;\r
uint32_t RESERVED0[3];\r
__IO uint32_t SPINT;\r
-} SPI_TypeDef;\r
+} LPC_SPI_TypeDef;\r
\r
/*------------- Synchronous Serial Communication (SSP) -----------------------*/\r
typedef struct\r
__IO uint32_t MIS;\r
__IO uint32_t ICR;\r
__IO uint32_t DMACR;\r
-} SSP_TypeDef;\r
+} LPC_SSP_TypeDef;\r
\r
/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/\r
typedef struct\r
__IO uint32_t I2MASK1;\r
__IO uint32_t I2MASK2;\r
__IO uint32_t I2MASK3;\r
-} I2C_TypeDef;\r
+} LPC_I2C_TypeDef;\r
\r
/*------------- Inter IC Sound (I2S) -----------------------------------------*/\r
typedef struct\r
{\r
__IO uint32_t I2SDAO;\r
- __IO uint32_t I2SDAI;\r
+ __IO uint32_t I2SDAI;\r
__O uint32_t I2STXFIFO;\r
__I uint32_t I2SRXFIFO;\r
__I uint32_t I2SSTATE;\r
__IO uint32_t I2SRXBITRATE;\r
__IO uint32_t I2STXMODE;\r
__IO uint32_t I2SRXMODE;\r
-} I2S_TypeDef;\r
+} LPC_I2S_TypeDef;\r
\r
/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/\r
typedef struct\r
__IO uint8_t RICTRL;\r
uint8_t RESERVED0[3];\r
__IO uint32_t RICOUNTER;\r
-} RIT_TypeDef;\r
+} LPC_RIT_TypeDef;\r
\r
/*------------- Real-Time Clock (RTC) ----------------------------------------*/\r
typedef struct\r
{\r
__IO uint8_t ILR;\r
- uint8_t RESERVED0[3];\r
+ uint8_t RESERVED0[7];\r
__IO uint8_t CCR;\r
uint8_t RESERVED1[3];\r
__IO uint8_t CIIR;\r
__IO uint32_t GPREG2;\r
__IO uint32_t GPREG3;\r
__IO uint32_t GPREG4;\r
- __IO uint8_t WAKEUPDIS;\r
+ __IO uint8_t RTC_AUXEN;\r
uint8_t RESERVED12[3];\r
- __IO uint8_t PWRCTRL;\r
+ __IO uint8_t RTC_AUX;\r
uint8_t RESERVED13[3];\r
__IO uint8_t ALSEC;\r
uint8_t RESERVED14[3];\r
uint8_t RESERVED20[3];\r
__IO uint16_t ALYEAR;\r
uint16_t RESERVED21;\r
-} RTC_TypeDef;\r
+} LPC_RTC_TypeDef;\r
\r
/*------------- Watchdog Timer (WDT) -----------------------------------------*/\r
typedef struct\r
uint8_t RESERVED1[3];\r
__I uint32_t WDTV;\r
__IO uint32_t WDCLKSEL;\r
-} WDT_TypeDef;\r
+} LPC_WDT_TypeDef;\r
\r
/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/\r
typedef struct\r
__I uint32_t ADDR7;\r
__I uint32_t ADSTAT;\r
__IO uint32_t ADTRM;\r
-} ADC_TypeDef;\r
+} LPC_ADC_TypeDef;\r
\r
/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/\r
typedef struct\r
__IO uint32_t DACR;\r
__IO uint32_t DACCTRL;\r
__IO uint16_t DACCNTVAL;\r
-} DAC_TypeDef;\r
+} LPC_DAC_TypeDef;\r
\r
/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/\r
typedef struct\r
__O uint32_t MCINTFLAG_SET;\r
__O uint32_t MCINTFLAG_CLR;\r
__O uint32_t MCCAP_CLR;\r
-} MCPWM_TypeDef;\r
+} LPC_MCPWM_TypeDef;\r
\r
/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/\r
typedef struct\r
__I uint32_t QEIIE;\r
__O uint32_t QEICLR;\r
__O uint32_t QEISET;\r
-} QEI_TypeDef;\r
+} LPC_QEI_TypeDef;\r
\r
/*------------- Controller Area Network (CAN) --------------------------------*/\r
typedef struct\r
{\r
__IO uint32_t mask[512]; /* ID Masks */\r
-} CANAF_RAM_TypeDef;\r
+} LPC_CANAF_RAM_TypeDef;\r
\r
typedef struct /* Acceptance Filter Registers */\r
{\r
__IO uint32_t ENDofTable;\r
__I uint32_t LUTerrAd;\r
__I uint32_t LUTerr;\r
-} CANAF_TypeDef;\r
+ __IO uint32_t FCANIE;\r
+ __IO uint32_t FCANIC0;\r
+ __IO uint32_t FCANIC1;\r
+} LPC_CANAF_TypeDef;\r
\r
typedef struct /* Central Registers */\r
{\r
__I uint32_t CANTxSR;\r
__I uint32_t CANRxSR;\r
__I uint32_t CANMSR;\r
-} CANCR_TypeDef;\r
+} LPC_CANCR_TypeDef;\r
\r
typedef struct /* Controller Registers */\r
{\r
__IO uint32_t TID3;\r
__IO uint32_t TDA3;\r
__IO uint32_t TDB3;\r
-} CAN_TypeDef;\r
+} LPC_CAN_TypeDef;\r
\r
/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/\r
typedef struct /* Common Registers */\r
__IO uint32_t DMACSoftLSReq;\r
__IO uint32_t DMACConfig;\r
__IO uint32_t DMACSync;\r
-} GPDMA_TypeDef;\r
+} LPC_GPDMA_TypeDef;\r
\r
typedef struct /* Channel Registers */\r
{\r
__IO uint32_t DMACCLLI;\r
__IO uint32_t DMACCControl;\r
__IO uint32_t DMACCConfig;\r
-} GPDMACH_TypeDef;\r
+} LPC_GPDMACH_TypeDef;\r
\r
/*------------- Universal Serial Bus (USB) -----------------------------------*/\r
typedef struct\r
__O uint32_t USBSysErrIntSet;\r
uint32_t RESERVED4[15];\r
\r
+ union {\r
__I uint32_t I2C_RX; /* USB OTG I2C Registers */\r
- __O uint32_t I2C_WO;\r
+ __O uint32_t I2C_TX;\r
+ };\r
__I uint32_t I2C_STS;\r
__IO uint32_t I2C_CTL;\r
__IO uint32_t I2C_CLKHI;\r
__O uint32_t I2C_CLKLO;\r
- uint32_t RESERVED5[823];\r
+ uint32_t RESERVED5[824];\r
\r
union {\r
__IO uint32_t USBClkCtrl; /* USB Clock Control Registers */\r
__IO uint32_t OTGClkCtrl;\r
- } ;\r
+ };\r
union {\r
__I uint32_t USBClkSt;\r
__I uint32_t OTGClkSt;\r
};\r
-} USB_TypeDef;\r
+} LPC_USB_TypeDef;\r
\r
/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/\r
typedef struct\r
__IO uint32_t PowerDown;\r
uint32_t RESERVED8;\r
__IO uint32_t Module_ID;\r
-} EMAC_TypeDef;\r
+} LPC_EMAC_TypeDef;\r
+\r
+#if defined ( __CC_ARM )\r
+#pragma no_anon_unions\r
+#endif\r
+\r
\r
/******************************************************************************/\r
/* Peripheral memory map */\r
/******************************************************************************/\r
/* Base addresses */\r
-#define FLASH_BASE (0x00000000UL)\r
-#define RAM_BASE (0x10000000UL)\r
-#define GPIO_BASE (0x2009C000UL)\r
-#define APB0_BASE (0x40000000UL)\r
-#define APB1_BASE (0x40080000UL)\r
-#define AHB_BASE (0x50000000UL)\r
-#define CM3_BASE (0xE0000000UL)\r
+#define LPC_FLASH_BASE (0x00000000UL)\r
+#define LPC_RAM_BASE (0x10000000UL)\r
+#define LPC_GPIO_BASE (0x2009C000UL)\r
+#define LPC_APB0_BASE (0x40000000UL)\r
+#define LPC_APB1_BASE (0x40080000UL)\r
+#define LPC_AHB_BASE (0x50000000UL)\r
+#define LPC_CM3_BASE (0xE0000000UL)\r
\r
/* APB0 peripherals */\r
-#define WDT_BASE (APB0_BASE + 0x00000)\r
-#define TIM0_BASE (APB0_BASE + 0x04000)\r
-#define TIM1_BASE (APB0_BASE + 0x08000)\r
-#define UART0_BASE (APB0_BASE + 0x0C000)\r
-#define UART1_BASE (APB0_BASE + 0x10000)\r
-#define PWM1_BASE (APB0_BASE + 0x18000)\r
-#define I2C0_BASE (APB0_BASE + 0x1C000)\r
-#define SPI_BASE (APB0_BASE + 0x20000)\r
-#define RTC_BASE (APB0_BASE + 0x24000)\r
-#define GPIOINT_BASE (APB0_BASE + 0x28080)\r
-#define PINCON_BASE (APB0_BASE + 0x2C000)\r
-#define SSP1_BASE (APB0_BASE + 0x30000)\r
-#define ADC_BASE (APB0_BASE + 0x34000)\r
-#define CANAF_RAM_BASE (APB0_BASE + 0x38000)\r
-#define CANAF_BASE (APB0_BASE + 0x3C000)\r
-#define CANCR_BASE (APB0_BASE + 0x40000)\r
-#define CAN1_BASE (APB0_BASE + 0x44000)\r
-#define CAN2_BASE (APB0_BASE + 0x48000)\r
-#define I2C1_BASE (APB0_BASE + 0x5C000)\r
+#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)\r
+#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)\r
+#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)\r
+#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)\r
+#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)\r
+#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)\r
+#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)\r
+#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)\r
+#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)\r
+#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)\r
+#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)\r
+#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)\r
+#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)\r
+#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)\r
+#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)\r
+#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)\r
+#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)\r
+#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)\r
+#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)\r
\r
/* APB1 peripherals */\r
-#define SSP0_BASE (APB1_BASE + 0x08000)\r
-#define DAC_BASE (APB1_BASE + 0x0C000)\r
-#define TIM2_BASE (APB1_BASE + 0x10000)\r
-#define TIM3_BASE (APB1_BASE + 0x14000)\r
-#define UART2_BASE (APB1_BASE + 0x18000)\r
-#define UART3_BASE (APB1_BASE + 0x1C000)\r
-#define I2C2_BASE (APB1_BASE + 0x20000)\r
-#define I2S_BASE (APB1_BASE + 0x28000)\r
-#define RIT_BASE (APB1_BASE + 0x30000)\r
-#define MCPWM_BASE (APB1_BASE + 0x38000)\r
-#define QEI_BASE (APB1_BASE + 0x3C000)\r
-#define SC_BASE (APB1_BASE + 0x7C000)\r
+#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)\r
+#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)\r
+#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)\r
+#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)\r
+#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)\r
+#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)\r
+#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)\r
+#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)\r
+#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)\r
+#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)\r
+#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)\r
+#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)\r
\r
/* AHB peripherals */\r
-#define EMAC_BASE (AHB_BASE + 0x00000)\r
-#define GPDMA_BASE (AHB_BASE + 0x04000)\r
-#define GPDMACH0_BASE (AHB_BASE + 0x04100)\r
-#define GPDMACH1_BASE (AHB_BASE + 0x04120)\r
-#define GPDMACH2_BASE (AHB_BASE + 0x04140)\r
-#define GPDMACH3_BASE (AHB_BASE + 0x04160)\r
-#define GPDMACH4_BASE (AHB_BASE + 0x04180)\r
-#define GPDMACH5_BASE (AHB_BASE + 0x041A0)\r
-#define GPDMACH6_BASE (AHB_BASE + 0x041C0)\r
-#define GPDMACH7_BASE (AHB_BASE + 0x041E0)\r
-#define USB_BASE (AHB_BASE + 0x0C000)\r
+#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)\r
+#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)\r
+#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)\r
+#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)\r
+#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)\r
+#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)\r
+#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)\r
+#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)\r
+#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)\r
+#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)\r
+#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)\r
\r
/* GPIOs */\r
-#define GPIO0_BASE (GPIO_BASE + 0x00000)\r
-#define GPIO1_BASE (GPIO_BASE + 0x00020)\r
-#define GPIO2_BASE (GPIO_BASE + 0x00040)\r
-#define GPIO3_BASE (GPIO_BASE + 0x00060)\r
-#define GPIO4_BASE (GPIO_BASE + 0x00080)\r
+#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)\r
+#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)\r
+#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)\r
+#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)\r
+#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)\r
\r
\r
/******************************************************************************/\r
/* Peripheral declaration */\r
/******************************************************************************/\r
-#define SC (( SC_TypeDef *) SC_BASE)\r
-#define GPIO0 (( GPIO_TypeDef *) GPIO0_BASE)\r
-#define GPIO1 (( GPIO_TypeDef *) GPIO1_BASE)\r
-#define GPIO2 (( GPIO_TypeDef *) GPIO2_BASE)\r
-#define GPIO3 (( GPIO_TypeDef *) GPIO3_BASE)\r
-#define GPIO4 (( GPIO_TypeDef *) GPIO4_BASE)\r
-#define WDT (( WDT_TypeDef *) WDT_BASE)\r
-#define TIM0 (( TIM_TypeDef *) TIM0_BASE)\r
-#define TIM1 (( TIM_TypeDef *) TIM1_BASE)\r
-#define TIM2 (( TIM_TypeDef *) TIM2_BASE)\r
-#define TIM3 (( TIM_TypeDef *) TIM3_BASE)\r
-#define RIT (( RIT_TypeDef *) RIT_BASE)\r
-#define UART0 (( UART_TypeDef *) UART0_BASE)\r
-#define UART1 (( UART1_TypeDef *) UART1_BASE)\r
-#define UART2 (( UART_TypeDef *) UART2_BASE)\r
-#define UART3 (( UART_TypeDef *) UART3_BASE)\r
-#define PWM1 (( PWM_TypeDef *) PWM1_BASE)\r
-#define I2C0 (( I2C_TypeDef *) I2C0_BASE)\r
-#define I2C1 (( I2C_TypeDef *) I2C1_BASE)\r
-#define I2C2 (( I2C_TypeDef *) I2C2_BASE)\r
-#define I2S (( I2S_TypeDef *) I2S_BASE)\r
-#define SPI (( SPI_TypeDef *) SPI_BASE)\r
-#define RTC (( RTC_TypeDef *) RTC_BASE)\r
-#define GPIOINT (( GPIOINT_TypeDef *) GPIOINT_BASE)\r
-#define PINCON (( PINCON_TypeDef *) PINCON_BASE)\r
-#define SSP0 (( SSP_TypeDef *) SSP0_BASE)\r
-#define SSP1 (( SSP_TypeDef *) SSP1_BASE)\r
-#define ADC (( ADC_TypeDef *) ADC_BASE)\r
-#define DAC (( DAC_TypeDef *) DAC_BASE)\r
-#define CANAF_RAM ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE)\r
-#define CANAF (( CANAF_TypeDef *) CANAF_BASE)\r
-#define CANCR (( CANCR_TypeDef *) CANCR_BASE)\r
-#define CAN1 (( CAN_TypeDef *) CAN1_BASE)\r
-#define CAN2 (( CAN_TypeDef *) CAN2_BASE)\r
-#define MCPWM (( MCPWM_TypeDef *) MCPWM_BASE)\r
-#define QEI (( QEI_TypeDef *) QEI_BASE)\r
-#define EMAC (( EMAC_TypeDef *) EMAC_BASE)\r
-#define GPDMA (( GPDMA_TypeDef *) GPDMA_BASE)\r
-#define GPDMACH0 (( GPDMACH_TypeDef *) GPDMACH0_BASE)\r
-#define GPDMACH1 (( GPDMACH_TypeDef *) GPDMACH1_BASE)\r
-#define GPDMACH2 (( GPDMACH_TypeDef *) GPDMACH2_BASE)\r
-#define GPDMACH3 (( GPDMACH_TypeDef *) GPDMACH3_BASE)\r
-#define GPDMACH4 (( GPDMACH_TypeDef *) GPDMACH4_BASE)\r
-#define GPDMACH5 (( GPDMACH_TypeDef *) GPDMACH5_BASE)\r
-#define GPDMACH6 (( GPDMACH_TypeDef *) GPDMACH6_BASE)\r
-#define GPDMACH7 (( GPDMACH_TypeDef *) GPDMACH7_BASE)\r
-#define USB (( USB_TypeDef *) USB_BASE)\r
+#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )\r
+#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )\r
+#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )\r
+#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )\r
+#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )\r
+#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )\r
+#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )\r
+#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )\r
+#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )\r
+#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )\r
+#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )\r
+#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )\r
+#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )\r
+#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )\r
+#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )\r
+#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )\r
+#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )\r
+#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )\r
+#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )\r
+#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )\r
+#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )\r
+#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )\r
+#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )\r
+#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )\r
+#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )\r
+#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )\r
+#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )\r
+#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )\r
+#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )\r
+#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)\r
+#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )\r
+#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )\r
+#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )\r
+#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )\r
+#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )\r
+#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )\r
+#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )\r
+#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )\r
+#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )\r
+#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )\r
+#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )\r
+#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )\r
+#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )\r
+#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )\r
+#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )\r
+#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )\r
+#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )\r
\r
#endif // __LPC17xx_H__\r
-\r
-\r
-#endif\r
-/******************************************************************************\r
- * @file: core_cm3.h\r
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version: V1.20\r
- * @date: 22. May 2009\r
- *----------------------------------------------------------------------------\r
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V1.30\r
+ * @date 30. October 2009\r
*\r
+ * @note\r
* Copyright (C) 2009 ARM Limited. All rights reserved.\r
*\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx \r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
* processor based microcontrollers. This file can be freely distributed \r
* within development tools that are supporting such ARM based processors. \r
*\r
+ * @par\r
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
#ifndef __CM3_CORE_H__\r
#define __CM3_CORE_H__\r
\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x03) /*!< Cortex core */\r
-\r
-/**\r
- * Lint configuration \n\r
- * ----------------------- \n\r
- *\r
- * The following Lint messages will be suppressed and not shown: \n\r
- * \n\r
- * --- Error 10: --- \n\r
- * register uint32_t __regBasePri __asm("basepri"); \n\r
- * Error 10: Expecting ';' \n\r
- * \n\r
- * --- Error 530: --- \n\r
- * return(__regBasePri); \n\r
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n\r
- * \n\r
- * --- Error 550: --- \n\r
- * __regBasePri = (basePri & 0x1ff); \n\r
- * } \n\r
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n\r
- * \n\r
- * --- Error 754: --- \n\r
- * uint32_t RESERVED0[24]; \n\r
- * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n\r
- * \n\r
- * --- Error 750: --- \n\r
- * #define __CM3_CORE_H__ \n\r
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n\r
- * \n\r
- * --- Error 528: --- \n\r
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n\r
- * \n\r
- * --- Error 751: --- \n\r
- * } InterruptType_Type; \n\r
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n\r
- * \n\r
- * \n\r
- * Note: To re-enable a Message, insert a space before 'lint' * \n\r
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
+ *\r
+ * List of Lint messages which will be suppressed and not shown:\r
+ * - Error 10: \n\r
+ * register uint32_t __regBasePri __asm("basepri"); \n\r
+ * Error 10: Expecting ';'\r
+ * .\r
+ * - Error 530: \n\r
+ * return(__regBasePri); \n\r
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized\r
+ * . \r
+ * - Error 550: \n\r
+ * __regBasePri = (basePri & 0x1ff); \n\r
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed\r
+ * .\r
+ * - Error 754: \n\r
+ * uint32_t RESERVED0[24]; \n\r
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 750: \n\r
+ * #define __CM3_CORE_H__ \n\r
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 528: \n\r
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 751: \n\r
+ * } InterruptType_Type; \n\r
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced\r
+ * .\r
+ * Note: To re-enable a Message, insert a space before 'lint' *\r
*\r
*/\r
\r
/*lint -e751 */\r
\r
\r
+/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
+ This file defines all structures and symbols for CMSIS core:\r
+ - CMSIS version number\r
+ - Cortex-M core registers and bitfields\r
+ - Cortex-M core peripheral base address\r
+ @{\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex core */\r
+\r
#include <stdint.h> /* Include standard types */\r
\r
#if defined (__ICCARM__)\r
*/\r
\r
#ifdef __cplusplus\r
-#define __I volatile /*!< defines 'read only' permissions */\r
+ #define __I volatile /*!< defines 'read only' permissions */\r
#else\r
-#define __I volatile const /*!< defines 'read only' permissions */\r
+ #define __I volatile const /*!< defines 'read only' permissions */\r
#endif\r
#define __O volatile /*!< defines 'write only' permissions */\r
#define __IO volatile /*!< defines 'read / write' permissions */\r
/*******************************************************************************\r
* Register Abstraction\r
******************************************************************************/\r
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
+ @{\r
+*/\r
\r
\r
-/* System Reset */\r
-#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */\r
-#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */\r
-#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */\r
-#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */\r
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
+ memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24]; \r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24]; \r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24]; \r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24]; \r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56]; \r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644]; \r
+ __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */\r
+} NVIC_Type; \r
+/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
+ memory mapped structure for System Control Block (SCB)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */\r
+} SCB_Type; \r
\r
-/* Core Debug */\r
-#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */\r
-#define ITM_TCR_ITMENA 1 /*!< ITM enable */\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
\r
-/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */\r
-typedef struct\r
-{\r
- __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24];\r
- __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24];\r
- __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24];\r
- __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24];\r
- __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */\r
- uint32_t RESERVED4[56];\r
- __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */\r
- uint32_t RESERVED5[644];\r
- __O uint32_t STIR; /*!< Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-\r
-/* memory mapping struct for System Control Block */\r
-typedef struct\r
-{\r
- __I uint32_t CPUID; /*!< CPU ID Base Register */\r
- __IO uint32_t ICSR; /*!< Interrupt Control State Register */\r
- __IO uint32_t VTOR; /*!< Vector Table Offset Register */\r
- __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */\r
- __IO uint32_t SCR; /*!< System Control Register */\r
- __IO uint32_t CCR; /*!< Configuration Control Register */\r
- __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IO uint32_t SHCSR; /*!< System Handler Control and State Register */\r
- __IO uint32_t CFSR; /*!< Configurable Fault Status Register */\r
- __IO uint32_t HFSR; /*!< Hard Fault Status Register */\r
- __IO uint32_t DFSR; /*!< Debug Fault Status Register */\r
- __IO uint32_t MMFAR; /*!< Mem Manage Address Register */\r
- __IO uint32_t BFAR; /*!< Bus Fault Address Register */\r
- __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */\r
- __I uint32_t PFR[2]; /*!< Processor Feature Register */\r
- __I uint32_t DFR; /*!< Debug Feature Register */\r
- __I uint32_t ADR; /*!< Auxiliary Feature Register */\r
- __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */\r
- __I uint32_t ISAR[5]; /*!< ISA Feature Register */\r
-} SCB_Type;\r
-\r
-\r
-/* memory mapping struct for SysTick */\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+ \r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SCB */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
+ memory mapped structure for SysTick\r
+ @{\r
+ */\r
typedef struct\r
{\r
- __IO uint32_t CTRL; /*!< SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< SysTick Calibration Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */\r
} SysTick_Type;\r
\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
\r
-/* memory mapping structur for ITM */\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
+ memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
typedef struct\r
{\r
__O union \r
{\r
- __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */\r
- __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */\r
- __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */\r
- } PORT [32]; /*!< ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864];\r
- __IO uint32_t TER; /*!< ITM Trace Enable Register */\r
- uint32_t RESERVED1[15];\r
- __IO uint32_t TPR; /*!< ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15];\r
- __IO uint32_t TCR; /*!< ITM Trace Control Register */\r
- uint32_t RESERVED3[29];\r
- __IO uint32_t IWR; /*!< ITM Integration Write Register */\r
- __IO uint32_t IRR; /*!< ITM Integration Read Register */\r
- __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43];\r
- __IO uint32_t LAR; /*!< ITM Lock Access Register */\r
- __IO uint32_t LSR; /*!< ITM Lock Status Register */\r
- uint32_t RESERVED5[6];\r
- __I uint32_t PID4; /*!< ITM Product ID Registers */\r
- __I uint32_t PID5;\r
- __I uint32_t PID6;\r
- __I uint32_t PID7;\r
- __I uint32_t PID0;\r
- __I uint32_t PID1;\r
- __I uint32_t PID2;\r
- __I uint32_t PID3;\r
- __I uint32_t CID0;\r
- __I uint32_t CID1;\r
- __I uint32_t CID2;\r
- __I uint32_t CID3;\r
-} ITM_Type;\r
-\r
-\r
-/* memory mapped struct for Interrupt Type */\r
+ __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864]; \r
+ __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15]; \r
+ __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15]; \r
+ __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */\r
+ uint32_t RESERVED3[29]; \r
+ __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */\r
+ __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43]; \r
+ __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */\r
+ __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */\r
+ uint32_t RESERVED5[6]; \r
+ __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */\r
+} ITM_Type; \r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_ITM */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
+ memory mapped structure for Interrupt Type\r
+ @{\r
+ */\r
typedef struct\r
{\r
uint32_t RESERVED0;\r
- __I uint32_t ICTR; /*!< Interrupt Control Type Register */\r
+ __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */\r
#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
- __IO uint32_t ACTLR; /*!< Auxiliary Control Register */\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */\r
#else\r
uint32_t RESERVED1;\r
#endif\r
} InterruptType_Type;\r
\r
+/* Interrupt Controller Type Register Definitions */\r
+#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */\r
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */\r
+#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */\r
+\r
+#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
+\r
+#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */\r
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
+\r
\r
-/* Memory Protection Unit */\r
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
+ memory mapped structure for Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
typedef struct\r
{\r
- __I uint32_t TYPE; /*!< MPU Type Register */\r
- __IO uint32_t CTRL; /*!< MPU Control Register */\r
- __IO uint32_t RNR; /*!< MPU Region RNRber Register */\r
- __IO uint32_t RBAR; /*!< MPU Region Base Address Register */\r
- __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */\r
- __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */\r
- __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */\r
- __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
+ __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type; \r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */\r
+#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */\r
+#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */\r
+#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */\r
+#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */\r
+#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */\r
+#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_MPU */\r
#endif\r
\r
\r
-/* Core Debug Register */\r
+/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
+ memory mapped structure for Core Debug Register\r
+ @{\r
+ */\r
typedef struct\r
{\r
- __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */\r
- __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */\r
- __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */\r
- __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */\r
} CoreDebug_Type;\r
\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
+\r
\r
/* Memory mapping of Cortex-M3 Hardware */\r
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
-\r
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
+\r
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
\r
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
#endif\r
\r
+/*@}*/ /* end of group CMSIS_CM3_core_register */\r
\r
\r
/*******************************************************************************\r
* Hardware Abstraction Layer\r
******************************************************************************/\r
\r
-\r
#if defined ( __CC_ARM )\r
#define __ASM __asm /*!< asm keyword for ARM Compiler */\r
#define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
\r
#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
\r
#elif defined ( __GNUC__ )\r
#define __INLINE inline /*!< inline keyword for GNU Compiler */\r
\r
#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
\r
#endif\r
\r
/**\r
* @brief Return the Process Stack Pointer\r
*\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
+ * @return ProcessStackPointer\r
*\r
* Return the actual process stack pointer\r
*/\r
/**\r
* @brief Set the Process Stack Pointer\r
*\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
+ * @param topOfProcStack Process Stack Pointer\r
*\r
* Assign the value ProcessStackPointer to the MSP \r
* (process stack pointer) Cortex processor register\r
/**\r
* @brief Return the Main Stack Pointer\r
*\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
+ * @return Main Stack Pointer\r
*\r
* Return the current value of the MSP (main stack pointer)\r
* Cortex processor register\r
/**\r
* @brief Set the Main Stack Pointer\r
*\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
+ * @param topOfMainStack Main Stack Pointer\r
*\r
* Assign the value mainStackPointer to the MSP \r
* (main stack pointer) Cortex processor register\r
/**\r
* @brief Reverse byte order in unsigned short value\r
*\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
+ * @param value value to reverse\r
+ * @return reversed value\r
*\r
* Reverse byte order in unsigned short value\r
*/\r
extern uint32_t __REV16(uint16_t value);\r
\r
-/*\r
+/**\r
* @brief Reverse byte order in signed short value with sign extension to integer\r
*\r
- * @param int16_t value to reverse\r
- * @return int32_t reversed value\r
+ * @param value value to reverse\r
+ * @return reversed value\r
*\r
* Reverse byte order in signed short value with sign extension to integer\r
*/\r
/**\r
* @brief Remove the exclusive lock created by ldrex\r
*\r
- * @param none\r
- * @return none\r
- *\r
* Removes the exclusive lock which is created by ldrex.\r
*/\r
extern void __CLREX(void);\r
/**\r
* @brief Return the Base Priority value\r
*\r
- * @param none\r
- * @return uint32_t BasePriority\r
+ * @return BasePriority\r
*\r
* Return the content of the base priority register\r
*/\r
/**\r
* @brief Set the Base Priority value\r
*\r
- * @param uint32_t BasePriority\r
- * @return none\r
+ * @param basePri BasePriority\r
*\r
* Set the base priority register\r
*/\r
/**\r
* @brief Return the Priority Mask value\r
*\r
- * @param none\r
- * @return uint32_t PriMask\r
+ * @return PriMask\r
*\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
+ * Return state of the priority mask bit from the priority mask register\r
*/\r
extern uint32_t __get_PRIMASK(void);\r
\r
/**\r
* @brief Set the Priority Mask value\r
*\r
- * @param uint32_t PriMask\r
- * @return none\r
+ * @param priMask PriMask\r
*\r
* Set the priority mask bit in the priority mask register\r
*/\r
/**\r
* @brief Return the Fault Mask value\r
*\r
- * @param none\r
- * @return uint32_t FaultMask\r
+ * @return FaultMask\r
*\r
* Return the content of the fault mask register\r
*/\r
/**\r
* @brief Set the Fault Mask value\r
*\r
- * @param uint32_t faultMask value\r
- * @return none\r
+ * @param faultMask faultMask value\r
*\r
* Set the fault mask register\r
*/\r
/**\r
* @brief Return the Control Register value\r
* \r
- * @param none\r
- * @return uint32_t Control value\r
+ * @return Control value\r
*\r
* Return the content of the control register\r
*/\r
/**\r
* @brief Set the Control Register value\r
*\r
- * @param uint32_t Control value\r
- * @return none\r
+ * @param control Control value\r
*\r
* Set the control register\r
*/\r
\r
#else /* (__ARMCC_VERSION >= 400000) */\r
\r
-\r
/**\r
* @brief Remove the exclusive lock created by ldrex\r
*\r
- * @param none\r
- * @return none\r
- *\r
* Removes the exclusive lock which is created by ldrex.\r
*/\r
#define __CLREX __clrex\r
/**\r
* @brief Return the Base Priority value\r
*\r
- * @param none\r
- * @return uint32_t BasePriority\r
+ * @return BasePriority\r
*\r
* Return the content of the base priority register\r
*/\r
/**\r
* @brief Set the Base Priority value\r
*\r
- * @param uint32_t BasePriority\r
- * @return none\r
+ * @param basePri BasePriority\r
*\r
* Set the base priority register\r
*/\r
static __INLINE void __set_BASEPRI(uint32_t basePri)\r
{\r
register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0x1ff);\r
+ __regBasePri = (basePri & 0xff);\r
}\r
\r
/**\r
* @brief Return the Priority Mask value\r
*\r
- * @param none\r
- * @return uint32_t PriMask\r
+ * @return PriMask\r
*\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
+ * Return state of the priority mask bit from the priority mask register\r
*/\r
static __INLINE uint32_t __get_PRIMASK(void)\r
{\r
/**\r
* @brief Set the Priority Mask value\r
*\r
- * @param uint32_t PriMask\r
- * @return none\r
+ * @param priMask PriMask\r
*\r
* Set the priority mask bit in the priority mask register\r
*/\r
/**\r
* @brief Return the Fault Mask value\r
*\r
- * @param none\r
- * @return uint32_t FaultMask\r
+ * @return FaultMask\r
*\r
* Return the content of the fault mask register\r
*/\r
/**\r
* @brief Set the Fault Mask value\r
*\r
- * @param uint32_t faultMask value\r
- * @return none\r
+ * @param faultMask faultMask value\r
*\r
* Set the fault mask register\r
*/\r
/**\r
* @brief Return the Control Register value\r
* \r
- * @param none\r
- * @return uint32_t Control value\r
+ * @return Control value\r
*\r
* Return the content of the control register\r
*/\r
/**\r
* @brief Set the Control Register value\r
*\r
- * @param uint32_t Control value\r
- * @return none\r
+ * @param control Control value\r
*\r
* Set the control register\r
*/\r
static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
\r
-#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ \r
+#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ \r
static __INLINE void __WFI() { __ASM ("wfi"); }\r
static __INLINE void __WFE() { __ASM ("wfe"); }\r
static __INLINE void __SEV() { __ASM ("sev"); }\r
/**\r
* @brief Return the Process Stack Pointer\r
*\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
+ * @return ProcessStackPointer\r
*\r
* Return the actual process stack pointer\r
*/\r
/**\r
* @brief Set the Process Stack Pointer\r
*\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
+ * @param topOfProcStack Process Stack Pointer\r
*\r
* Assign the value ProcessStackPointer to the MSP \r
* (process stack pointer) Cortex processor register\r
/**\r
* @brief Return the Main Stack Pointer\r
*\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
+ * @return Main Stack Pointer\r
*\r
* Return the current value of the MSP (main stack pointer)\r
* Cortex processor register\r
/**\r
* @brief Set the Main Stack Pointer\r
*\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
+ * @param topOfMainStack Main Stack Pointer\r
*\r
* Assign the value mainStackPointer to the MSP \r
* (main stack pointer) Cortex processor register\r
/**\r
* @brief Reverse byte order in unsigned short value\r
*\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
+ * @param value value to reverse\r
+ * @return reversed value\r
*\r
* Reverse byte order in unsigned short value\r
*/\r
/**\r
* @brief Reverse bit order of value\r
*\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
+ * @param value value to reverse\r
+ * @return reversed value\r
*\r
* Reverse bit order of value\r
*/\r
extern uint32_t __RBIT(uint32_t value);\r
\r
/**\r
- * @brief LDR Exclusive\r
+ * @brief LDR Exclusive (8 bit)\r
*\r
- * @param uint8_t* address\r
- * @return uint8_t value of (*address)\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
*\r
- * Exclusive LDR command\r
+ * Exclusive LDR command for 8 bit values)\r
*/\r
extern uint8_t __LDREXB(uint8_t *addr);\r
\r
/**\r
- * @brief LDR Exclusive\r
+ * @brief LDR Exclusive (16 bit)\r
*\r
- * @param uint16_t* address\r
- * @return uint16_t value of (*address)\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
*\r
- * Exclusive LDR command\r
+ * Exclusive LDR command for 16 bit values\r
*/\r
extern uint16_t __LDREXH(uint16_t *addr);\r
\r
/**\r
- * @brief LDR Exclusive\r
+ * @brief LDR Exclusive (32 bit)\r
*\r
- * @param uint32_t* address\r
- * @return uint32_t value of (*address)\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
*\r
- * Exclusive LDR command\r
+ * Exclusive LDR command for 32 bit values\r
*/\r
extern uint32_t __LDREXW(uint32_t *addr);\r
\r
/**\r
- * @brief STR Exclusive\r
+ * @brief STR Exclusive (8 bit)\r
*\r
- * @param uint8_t *address\r
- * @param uint8_t value to store\r
- * @return uint32_t successful / failed\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
*\r
- * Exclusive STR command\r
+ * Exclusive STR command for 8 bit values\r
*/\r
extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
\r
/**\r
- * @brief STR Exclusive\r
+ * @brief STR Exclusive (16 bit)\r
*\r
- * @param uint16_t *address\r
- * @param uint16_t value to store\r
- * @return uint32_t successful / failed\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
*\r
- * Exclusive STR command\r
+ * Exclusive STR command for 16 bit values\r
*/\r
extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
\r
/**\r
- * @brief STR Exclusive\r
+ * @brief STR Exclusive (32 bit)\r
*\r
- * @param uint32_t *address\r
- * @param uint32_t value to store\r
- * @return uint32_t successful / failed\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
*\r
- * Exclusive STR command\r
+ * Exclusive STR command for 32 bit values\r
*/\r
extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
\r
/**\r
* @brief Return the Process Stack Pointer\r
*\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
+ * @return ProcessStackPointer\r
*\r
* Return the actual process stack pointer\r
*/\r
/**\r
* @brief Set the Process Stack Pointer\r
*\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
+ * @param topOfProcStack Process Stack Pointer\r
*\r
* Assign the value ProcessStackPointer to the MSP \r
* (process stack pointer) Cortex processor register\r
/**\r
* @brief Return the Main Stack Pointer\r
*\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
+ * @return Main Stack Pointer\r
*\r
* Return the current value of the MSP (main stack pointer)\r
* Cortex processor register\r
/**\r
* @brief Set the Main Stack Pointer\r
*\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
+ * @param topOfMainStack Main Stack Pointer\r
*\r
* Assign the value mainStackPointer to the MSP \r
* (main stack pointer) Cortex processor register\r
/**\r
* @brief Return the Base Priority value\r
*\r
- * @param none\r
- * @return uint32_t BasePriority\r
+ * @return BasePriority\r
*\r
* Return the content of the base priority register\r
*/\r
/**\r
* @brief Set the Base Priority value\r
*\r
- * @param uint32_t BasePriority\r
- * @return none\r
+ * @param basePri BasePriority\r
*\r
* Set the base priority register\r
*/\r
/**\r
* @brief Return the Priority Mask value\r
*\r
- * @param none\r
- * @return uint32_t PriMask\r
+ * @return PriMask\r
*\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
+ * Return state of the priority mask bit from the priority mask register\r
*/\r
extern uint32_t __get_PRIMASK(void);\r
\r
/**\r
* @brief Set the Priority Mask value\r
*\r
- * @param uint32_t PriMask\r
- * @return none\r
+ * @param priMask PriMask\r
*\r
* Set the priority mask bit in the priority mask register\r
*/\r
/**\r
* @brief Return the Fault Mask value\r
*\r
- * @param none\r
- * @return uint32_t FaultMask\r
+ * @return FaultMask\r
*\r
* Return the content of the fault mask register\r
*/\r
/**\r
* @brief Set the Fault Mask value\r
*\r
- * @param uint32_t faultMask value\r
- * @return none\r
+ * @param faultMask faultMask value\r
*\r
* Set the fault mask register\r
*/\r
/**\r
* @brief Return the Control Register value\r
* \r
-* @param none\r
-* @return uint32_t Control value\r
+* @return Control value\r
*\r
* Return the content of the control register\r
*/\r
/**\r
* @brief Set the Control Register value\r
*\r
- * @param uint32_t Control value\r
- * @return none\r
+ * @param control Control value\r
*\r
* Set the control register\r
*/\r
/**\r
* @brief Reverse byte order in integer value\r
*\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
+ * @param value value to reverse\r
+ * @return reversed value\r
*\r
* Reverse byte order in integer value\r
*/\r
/**\r
* @brief Reverse byte order in unsigned short value\r
*\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
+ * @param value value to reverse\r
+ * @return reversed value\r
*\r
* Reverse byte order in unsigned short value\r
*/\r
extern uint32_t __REV16(uint16_t value);\r
\r
-/*\r
- * Reverse byte order in signed short value with sign extension to integer\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
*\r
- * @param int16_t value to reverse\r
- * @return int32_t reversed value\r
+ * @param value value to reverse\r
+ * @return reversed value\r
*\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
+ * Reverse byte order in signed short value with sign extension to integer\r
*/\r
extern int32_t __REVSH(int16_t value);\r
\r
/**\r
* @brief Reverse bit order of value\r
*\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
+ * @param value value to reverse\r
+ * @return reversed value\r
*\r
* Reverse bit order of value\r
*/\r
extern uint32_t __RBIT(uint32_t value);\r
\r
/**\r
- * @brief LDR Exclusive\r
+ * @brief LDR Exclusive (8 bit)\r
*\r
- * @param uint8_t* address\r
- * @return uint8_t value of (*address)\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
*\r
- * Exclusive LDR command\r
+ * Exclusive LDR command for 8 bit value\r
*/\r
extern uint8_t __LDREXB(uint8_t *addr);\r
\r
/**\r
- * @brief LDR Exclusive\r
+ * @brief LDR Exclusive (16 bit)\r
*\r
- * @param uint16_t* address\r
- * @return uint16_t value of (*address)\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
*\r
- * Exclusive LDR command\r
+ * Exclusive LDR command for 16 bit values\r
*/\r
extern uint16_t __LDREXH(uint16_t *addr);\r
\r
/**\r
- * @brief LDR Exclusive\r
+ * @brief LDR Exclusive (32 bit)\r
*\r
- * @param uint32_t* address\r
- * @return uint32_t value of (*address)\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
*\r
- * Exclusive LDR command\r
+ * Exclusive LDR command for 32 bit values\r
*/\r
extern uint32_t __LDREXW(uint32_t *addr);\r
\r
/**\r
- * @brief STR Exclusive\r
+ * @brief STR Exclusive (8 bit)\r
*\r
- * @param uint8_t *address\r
- * @param uint8_t value to store\r
- * @return uint32_t successful / failed\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
*\r
- * Exclusive STR command\r
+ * Exclusive STR command for 8 bit values\r
*/\r
extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
\r
/**\r
- * @brief STR Exclusive\r
+ * @brief STR Exclusive (16 bit)\r
*\r
- * @param uint16_t *address\r
- * @param uint16_t value to store\r
- * @return uint32_t successful / failed\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
*\r
- * Exclusive STR command\r
+ * Exclusive STR command for 16 bit values\r
*/\r
extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
\r
/**\r
- * @brief STR Exclusive\r
+ * @brief STR Exclusive (32 bit)\r
*\r
- * @param uint32_t *address\r
- * @param uint32_t value to store\r
- * @return uint32_t successful / failed\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
*\r
- * Exclusive STR command\r
+ * Exclusive STR command for 32 bit values\r
*/\r
extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
\r
#endif\r
\r
\r
+/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface\r
+ Core Function Interface containing:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Reset Functions\r
+*/\r
+/*@{*/\r
\r
/* ########################## NVIC functions #################################### */\r
\r
-\r
/**\r
* @brief Set the Priority Grouping in NVIC Interrupt Controller\r
*\r
- * @param uint32_t priority_grouping is priority grouping field\r
- * @return none \r
+ * @param PriorityGroup is priority grouping field\r
*\r
* Set the priority grouping field using the required unlock sequence.\r
* The parameter priority_grouping is assigned to the field \r
uint32_t reg_value;\r
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */\r
- reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ (0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
}\r
\r
/**\r
* @brief Get the Priority Grouping from NVIC Interrupt Controller\r
*\r
- * @param none\r
- * @return uint32_t priority grouping field \r
+ * @return priority grouping field \r
*\r
* Get the priority grouping from NVIC Interrupt Controller.\r
* priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
*/\r
static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
{\r
- return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
}\r
\r
/**\r
* @brief Enable Interrupt in NVIC Interrupt Controller\r
*\r
- * @param IRQn_Type IRQn specifies the interrupt number\r
- * @return none \r
+ * @param IRQn The positive number of the external interrupt to enable\r
*\r
* Enable a device specific interupt in the NVIC interrupt controller.\r
* The interrupt number cannot be a negative value.\r
/**\r
* @brief Disable the interrupt line for external interrupt specified\r
* \r
- * @param IRQn_Type IRQn is the positive number of the external interrupt\r
- * @return none\r
+ * @param IRQn The positive number of the external interrupt to disable\r
* \r
* Disable a device specific interupt in the NVIC interrupt controller.\r
* The interrupt number cannot be a negative value.\r
/**\r
* @brief Read the interrupt pending bit for a device specific interrupt source\r
* \r
- * @param IRQn_Type IRQn is the number of the device specifc interrupt\r
- * @return uint32_t 1 if pending interrupt else 0\r
+ * @param IRQn The number of the device specifc interrupt\r
+ * @return 1 = interrupt pending, 0 = interrupt not pending\r
*\r
* Read the pending register in NVIC and return 1 if its status is pending, \r
* otherwise it returns 0\r
/**\r
* @brief Set the pending bit for an external interrupt\r
* \r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return none\r
+ * @param IRQn The number of the interrupt for set pending\r
*\r
* Set the pending bit for the specified interrupt.\r
* The interrupt number cannot be a negative value.\r
/**\r
* @brief Clear the pending bit for an external interrupt\r
*\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return none\r
+ * @param IRQn The number of the interrupt for clear pending\r
*\r
* Clear the pending bit for the specified interrupt. \r
* The interrupt number cannot be a negative value.\r
/**\r
* @brief Read the active bit for an external interrupt\r
*\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return uint32_t 1 if active else 0\r
+ * @param IRQn The number of the interrupt for read active bit\r
+ * @return 1 = interrupt active, 0 = interrupt not active\r
*\r
* Read the active register in NVIC and returns 1 if its status is active, \r
* otherwise it returns 0.\r
/**\r
* @brief Set the priority for an interrupt\r
*\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @param priority is the priority for the interrupt\r
- * @return none\r
+ * @param IRQn The number of the interrupt for set priority\r
+ * @param priority The priority to set\r
*\r
* Set the priority for the specified interrupt. The interrupt \r
* number can be positive to specify an external (device specific) \r
- * interrupt, or negative to specify an internal (core) interrupt. \n\r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
*\r
* Note: The priority cannot be set for every core interrupt.\r
*/\r
if(IRQn < 0) {\r
SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
}\r
\r
/**\r
* @brief Read the priority for an interrupt\r
*\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return uint32_t priority is the priority for the interrupt\r
+ * @param IRQn The number of the interrupt for get priority\r
+ * @return The priority for the interrupt\r
*\r
* Read the priority for the specified interrupt. The interrupt \r
* number can be positive to specify an external (device specific) \r
/**\r
* @brief Encode the priority for an interrupt\r
*\r
- * @param uint32_t PriorityGroup is the used priority group\r
- * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0)\r
- * @param uint32_t SubPriority is the sub priority value (starting from 0)\r
- * @return uint32_t the priority for the interrupt\r
+ * @param PriorityGroup The used priority group\r
+ * @param PreemptPriority The preemptive priority value (starting from 0)\r
+ * @param SubPriority The sub priority value (starting from 0)\r
+ * @return The encoded priority for the interrupt\r
*\r
* Encode the priority for an interrupt with the given priority group,\r
* preemptive priority value and sub priority value.\r
*/\r
static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
uint32_t SubPriorityBits;\r
\r
/**\r
* @brief Decode the priority of an interrupt\r
*\r
- * @param uint32_t Priority the priority for the interrupt\r
- * @param uint32_t PrioGroup is the used priority group\r
- * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)\r
- * @param uint32_t* pSubPrio is the sub priority value (starting from 0)\r
- * @return none\r
+ * @param Priority The priority for the interrupt\r
+ * @param PriorityGroup The used priority group\r
+ * @param pPreemptPriority The preemptive priority value (starting from 0)\r
+ * @param pSubPriority The sub priority value (starting from 0)\r
*\r
* Decode an interrupt priority value with the given priority group to \r
* preemptive priority value and sub priority value.\r
*/\r
static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
uint32_t SubPriorityBits;\r
\r
\r
#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
\r
-/* SysTick constants */\r
-#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */\r
-#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */\r
-#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */\r
-#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */\r
-\r
/**\r
* @brief Initialize and start the SysTick counter and its interrupt.\r
*\r
- * @param uint32_t ticks is the number of ticks between two interrupts\r
- * @return none\r
+ * @param ticks number of ticks between two interrupts\r
+ * @return 1 = failed, 0 = successful\r
*\r
* Initialise the system tick timer and its interrupt and start the\r
* system tick timer / counter in free running mode to generate \r
*/\r
static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
{ \r
- if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */\r
-\r
- SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
- SysTick->VAL = (0x00); /* Load the SysTick Counter Value */\r
- SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ \r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | \r
+ SysTick_CTRL_TICKINT_Msk | \r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
}\r
\r
#endif\r
\r
\r
\r
-\r
/* ################################## Reset function ############################################ */\r
\r
/**\r
* @brief Initiate a system reset request.\r
*\r
- * @param none\r
- * @return none\r
- *\r
- * Initialize a system reset request to reset the MCU\r
+ * Initiate a system reset request to reset the MCU\r
*/\r
static __INLINE void NVIC_SystemReset(void)\r
{\r
- SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */ \r
- while(1); /* wait until reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | \r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */ \r
+ while(1); /* wait until reset */\r
}\r
\r
+/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
\r
-/* ################################## Debug Output function ############################################ */\r
+/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface\r
+ Core Debug Interface containing:\r
+ - Core Debug Receive / Transmit Functions\r
+ - Core Debug Defines\r
+ - Core Debug Variables\r
+*/\r
+/*@{*/\r
+\r
+extern volatile int ITM_RxBuffer; /*!< variable to receive characters */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
\r
\r
/**\r
* @brief Outputs a character via the ITM channel 0\r
*\r
- * @param uint32_t character to output\r
- * @return uint32_t input character\r
+ * @param ch character to output\r
+ * @return character to output\r
*\r
* The function outputs a character via the ITM channel 0. \r
* The function returns when no debugger is connected that has booked the output. \r
*/\r
static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
{\r
- if (ch == '\n') ITM_SendChar('\r');\r
- \r
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&\r
- (ITM->TCR & ITM_TCR_ITMENA) &&\r
- (ITM->TER & (1UL << 0)) ) \r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */\r
{\r
while (ITM->PORT[0].u32 == 0);\r
ITM->PORT[0].u8 = (uint8_t) ch;\r
return (ch);\r
}\r
\r
+\r
+/**\r
+ * @brief Inputs a character via variable ITM_RxBuffer\r
+ *\r
+ * @return received character, -1 = no character received\r
+ *\r
+ * The function inputs a character via variable ITM_RxBuffer. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE int ITM_ReceiveChar (void) {\r
+ int ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+ \r
+ return (ch); \r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if a character via variable ITM_RxBuffer is available\r
+ *\r
+ * @return 1 = character available, 0 = no character available\r
+ *\r
+ * The function checks variable ITM_RxBuffer whether a character is available or not. \r
+ * The function returns '1' if a character is available and '0' if no character is available. \r
+ */\r
+static __INLINE int ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */\r
+\r
+\r
#ifdef __cplusplus\r
}\r
#endif\r
\r
+/*@}*/ /* end of group CMSIS_CM3_core_definitions */\r
+\r
#endif /* __CM3_CORE_H__ */\r
\r
/*lint -restore */\r
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