--- /dev/null
+/*****************************************************************************\r
+ *\r
+ * Project : lwIP Web\r
+ * Subproject : \r
+ * Name : LPC23xx.h\r
+ * Function : register definitions\r
+ * Designer : K. Sterckx\r
+ * Creation date : 22/01/2007\r
+ * Compiler : GNU ARM\r
+ * Processor : LPC23xx\r
+ * Last update :\r
+ * Last updated by :\r
+ * History :\r
+ *\r
+ *****************************************************************************\r
+ *\r
+ * Hardware specific macro's and defines\r
+ *\r
+ ****************************************************************************/\r
+\r
+#ifndef __LPC23xx_H\r
+#define __LPC23xx_H\r
+\r
+/* Vectored Interrupt Controller (VIC) */\r
+#define VIC_BASE_ADDR 0xFFFFF000\r
+#define VICIRQStatus (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x000))\r
+#define VICFIQStatus (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x004))\r
+#define VICRawIntr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x008))\r
+#define VICIntSelect (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x00C))\r
+#define VICIntEnable (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x010))\r
+#define VICIntEnClr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x014))\r
+#define VICSoftInt (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x018))\r
+#define VICSoftIntClr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x01C))\r
+#define VICProtection (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x020))\r
+#define VICSWPrioMask (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x024))\r
+\r
+#define VICVectAddr0 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x100))\r
+#define VICVectAddr1 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x104))\r
+#define VICVectAddr2 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x108))\r
+#define VICVectAddr3 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x10C))\r
+#define VICVectAddr4 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x110))\r
+#define VICVectAddr5 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x114))\r
+#define VICVectAddr6 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x118))\r
+#define VICVectAddr7 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x11C))\r
+#define VICVectAddr8 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x120))\r
+#define VICVectAddr9 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x124))\r
+#define VICVectAddr10 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x128))\r
+#define VICVectAddr11 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x12C))\r
+#define VICVectAddr12 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x130))\r
+#define VICVectAddr13 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x134))\r
+#define VICVectAddr14 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x138))\r
+#define VICVectAddr15 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x13C))\r
+#define VICVectAddr16 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x140))\r
+#define VICVectAddr17 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x144))\r
+#define VICVectAddr18 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x148))\r
+#define VICVectAddr19 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x14C))\r
+#define VICVectAddr20 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x150))\r
+#define VICVectAddr21 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x154))\r
+#define VICVectAddr22 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x158))\r
+#define VICVectAddr23 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x15C))\r
+#define VICVectAddr24 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x160))\r
+#define VICVectAddr25 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x164))\r
+#define VICVectAddr26 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x168))\r
+#define VICVectAddr27 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x16C))\r
+#define VICVectAddr28 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x170))\r
+#define VICVectAddr29 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x174))\r
+#define VICVectAddr30 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x178))\r
+#define VICVectAddr31 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x17C))\r
+\r
+/* The name convention below is from previous LPC2000 family MCUs, in LPC230x,\r
+these registers are known as "VICVectPriority(x)". */\r
+#define VICVectCntl0 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x200))\r
+#define VICVectCntl1 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x204))\r
+#define VICVectCntl2 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x208))\r
+#define VICVectCntl3 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x20C))\r
+#define VICVectCntl4 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x210))\r
+#define VICVectCntl5 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x214))\r
+#define VICVectCntl6 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x218))\r
+#define VICVectCntl7 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x21C))\r
+#define VICVectCntl8 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x220))\r
+#define VICVectCntl9 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x224))\r
+#define VICVectCntl10 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x228))\r
+#define VICVectCntl11 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x22C))\r
+#define VICVectCntl12 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x230))\r
+#define VICVectCntl13 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x234))\r
+#define VICVectCntl14 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x238))\r
+#define VICVectCntl15 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x23C))\r
+#define VICVectCntl16 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x240))\r
+#define VICVectCntl17 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x244))\r
+#define VICVectCntl18 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x248))\r
+#define VICVectCntl19 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x24C))\r
+#define VICVectCntl20 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x250))\r
+#define VICVectCntl21 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x254))\r
+#define VICVectCntl22 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x258))\r
+#define VICVectCntl23 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x25C))\r
+#define VICVectCntl24 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x260))\r
+#define VICVectCntl25 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x264))\r
+#define VICVectCntl26 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x268))\r
+#define VICVectCntl27 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x26C))\r
+#define VICVectCntl28 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x270))\r
+#define VICVectCntl29 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x274))\r
+#define VICVectCntl30 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x278))\r
+#define VICVectCntl31 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x27C))\r
+\r
+#define VICVectAddr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0xF00))\r
+\r
+\r
+/* Pin Connect Block */\r
+#define PINSEL_BASE_ADDR 0xE002C000\r
+#define PINSEL0 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x00))\r
+#define PINSEL1 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x04))\r
+#define PINSEL2 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x08))\r
+#define PINSEL3 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x0C))\r
+#define PINSEL4 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x10))\r
+#define PINSEL5 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x14))\r
+#define PINSEL6 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x18))\r
+#define PINSEL7 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x1C))\r
+#define PINSEL8 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x20))\r
+#define PINSEL9 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x24))\r
+#define PINSEL10 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x28))\r
+\r
+#define PINMODE0 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x40))\r
+#define PINMODE1 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x44))\r
+#define PINMODE2 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x48))\r
+#define PINMODE3 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x4C))\r
+#define PINMODE4 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x50))\r
+#define PINMODE5 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x54))\r
+#define PINMODE6 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x58))\r
+#define PINMODE7 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x5C))\r
+#define PINMODE8 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x60))\r
+#define PINMODE9 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x64))\r
+\r
+/* General Purpose Input/Output (GPIO) */\r
+#define GPIO_BASE_ADDR 0xE0028000\r
+#define IOPIN0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x00))\r
+#define IOSET0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x04))\r
+#define IODIR0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x08))\r
+#define IOCLR0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x0C))\r
+#define IOPIN1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x10))\r
+#define IOSET1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x14))\r
+#define IODIR1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x18))\r
+#define IOCLR1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x1C))\r
+\r
+/* GPIO Interrupt Registers */\r
+#define IO0_INT_EN_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x90)) \r
+#define IO0_INT_EN_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x94))\r
+#define IO0_INT_STAT_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x84))\r
+#define IO0_INT_STAT_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x88))\r
+#define IO0_INT_CLR (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x8C))\r
+\r
+#define IO2_INT_EN_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xB0)) \r
+#define IO2_INT_EN_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xB4))\r
+#define IO2_INT_STAT_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xA4))\r
+#define IO2_INT_STAT_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xA8))\r
+#define IO2_INT_CLR (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xAC))\r
+\r
+#define IO_INT_STAT (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x80))\r
+\r
+#define PARTCFG_BASE_ADDR 0x3FFF8000\r
+#define PARTCFG (*(volatile unsigned int *)(PARTCFG_BASE_ADDR + 0x00)) \r
+\r
+/* Fast I/O setup */\r
+#define FIO_BASE_ADDR 0x3FFFC000\r
+#define FIO0DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x00)) \r
+#define FIO0MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x10))\r
+#define FIO0PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x14))\r
+#define FIO0SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x18))\r
+#define FIO0CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x1C))\r
+\r
+#define FIO1DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x20)) \r
+#define FIO1MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x30))\r
+#define FIO1PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x34))\r
+#define FIO1SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x38))\r
+#define FIO1CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x3C))\r
+\r
+#define FIO2DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x40)) \r
+#define FIO2MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x50))\r
+#define FIO2PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x54))\r
+#define FIO2SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x58))\r
+#define FIO2CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x5C))\r
+\r
+#define FIO3DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x60)) \r
+#define FIO3MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x70))\r
+#define FIO3PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x74))\r
+#define FIO3SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x78))\r
+#define FIO3CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x7C))\r
+\r
+#define FIO4DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x80)) \r
+#define FIO4MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x90))\r
+#define FIO4PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x94))\r
+#define FIO4SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x98))\r
+#define FIO4CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x9C))\r
+\r
+/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */\r
+#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) \r
+#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) \r
+#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) \r
+#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) \r
+#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) \r
+\r
+#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) \r
+#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) \r
+#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) \r
+#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) \r
+#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) \r
+\r
+#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) \r
+#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) \r
+#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) \r
+#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) \r
+#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) \r
+\r
+#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x04)) \r
+#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x24)) \r
+#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x44)) \r
+#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x64)) \r
+#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x84)) \r
+\r
+#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) \r
+#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) \r
+#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) \r
+#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) \r
+#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) \r
+\r
+#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) \r
+#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) \r
+#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) \r
+#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) \r
+#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) \r
+\r
+#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) \r
+#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) \r
+#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) \r
+#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) \r
+#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) \r
+\r
+#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) \r
+#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) \r
+#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) \r
+#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) \r
+#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) \r
+\r
+#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) \r
+#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) \r
+#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) \r
+#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) \r
+#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) \r
+\r
+#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) \r
+#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) \r
+#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) \r
+#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) \r
+#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) \r
+\r
+#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) \r
+#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) \r
+#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) \r
+#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) \r
+#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) \r
+\r
+#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) \r
+#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) \r
+#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) \r
+#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) \r
+#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) \r
+\r
+#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) \r
+#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) \r
+#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) \r
+#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) \r
+#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) \r
+\r
+#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) \r
+#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x25)) \r
+#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) \r
+#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) \r
+#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) \r
+\r
+#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) \r
+#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) \r
+#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) \r
+#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) \r
+#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) \r
+\r
+#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) \r
+#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) \r
+#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) \r
+#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) \r
+#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) \r
+\r
+#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) \r
+#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) \r
+#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) \r
+#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) \r
+#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) \r
+\r
+#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) \r
+#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) \r
+#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) \r
+#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) \r
+#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) \r
+\r
+#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) \r
+#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) \r
+#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) \r
+#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) \r
+#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) \r
+\r
+#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) \r
+#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) \r
+#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) \r
+#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) \r
+#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) \r
+\r
+#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) \r
+#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) \r
+#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) \r
+#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) \r
+#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) \r
+\r
+#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) \r
+#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) \r
+#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) \r
+#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) \r
+#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) \r
+\r
+#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) \r
+#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) \r
+#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) \r
+#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) \r
+#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) \r
+\r
+#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) \r
+#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) \r
+#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) \r
+#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) \r
+#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) \r
+\r
+#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) \r
+#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) \r
+#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) \r
+#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) \r
+#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) \r
+\r
+#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) \r
+#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) \r
+#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) \r
+#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) \r
+#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) \r
+\r
+#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) \r
+#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) \r
+#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) \r
+#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) \r
+#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) \r
+\r
+#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) \r
+#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) \r
+#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) \r
+#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) \r
+#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) \r
+\r
+#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) \r
+#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) \r
+#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) \r
+#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) \r
+#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) \r
+\r
+#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) \r
+#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) \r
+#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) \r
+#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) \r
+#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) \r
+\r
+\r
+/* System Control Block(SCB) modules include Memory Accelerator Module,\r
+Phase Locked Loop, VPB divider, Power Control, External Interrupt, \r
+Reset, and Code Security/Debugging */\r
+#define SCB_BASE_ADDR 0xE01FC000\r
+\r
+/* Memory Accelerator Module (MAM) */\r
+#define MAMCR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x000))\r
+#define MAMTIM (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x004))\r
+#define MEMMAP (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x040))\r
+\r
+/* Phase Locked Loop (PLL) */\r
+#define PLLCON (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x080))\r
+#define PLLCFG (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x084))\r
+#define PLLSTAT (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x088))\r
+#define PLLFEED (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x08C))\r
+\r
+/* Power Control */\r
+#define PCON (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x0C0))\r
+#define PCONP (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x0C4))\r
+\r
+/* Clock Divider */\r
+#define APBDIV (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x100))\r
+#define CCLKCFG (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x104))\r
+#define USBCLKCFG (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x108))\r
+#define CLKSRCSEL (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x10C))\r
+#define PCLKSEL0 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x1A8))\r
+#define PCLKSEL1 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x1AC))\r
+ \r
+/* External Interrupts */\r
+#define EXTINT (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x140))\r
+#define INTWAKE (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x144))\r
+#define EXTMODE (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x148))\r
+#define EXTPOLAR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x14C))\r
+\r
+/* Reset, reset source identification */\r
+#define RSIR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x180))\r
+\r
+/* RSID, code security protection */\r
+#define CSPR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x184))\r
+\r
+/* AHB configuration */\r
+#define AHBCFG1 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x188))\r
+#define AHBCFG2 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x18C))\r
+\r
+/* System Controls and Status */\r
+#define SCS (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x1A0))\r
+\r
+/*MPMC(EMC) registers*/\r
+#define STATIC_MEM0_BASE 0x80000000\r
+#define STATIC_MEM1_BASE 0x81000000\r
+#define STATIC_MEM2_BASE 0x82000000\r
+#define STATIC_MEM3_BASE 0x83000000\r
+\r
+#define DYNAMIC_MEM0_BASE 0xA0000000\r
+#define DYNAMIC_MEM1_BASE 0xB0000000\r
+#define DYNAMIC_MEM2_BASE 0xC0000000\r
+#define DYNAMIC_MEM3_BASE 0xD0000000\r
+\r
+/* External Memory Controller (EMC) */\r
+#define EMC_BASE_ADDR 0xFFE08000\r
+#define EMC_CTRL (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x000))\r
+#define EMC_STAT (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x004))\r
+#define EMC_CONFIG (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x008))\r
+\r
+/* Dynamic RAM access registers */\r
+#define EMC_DYN_CTRL (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x020))\r
+#define EMC_DYN_RFSH (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x024))\r
+#define EMC_DYN_RD_CFG (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x028))\r
+#define EMC_DYN_RP (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x030))\r
+#define EMC_DYN_RAS (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x034))\r
+#define EMC_DYN_SREX (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x038))\r
+#define EMC_DYN_APR (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x03C))\r
+#define EMC_DYN_DAL (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x040))\r
+#define EMC_DYN_WR (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x044))\r
+#define EMC_DYN_RC (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x048))\r
+#define EMC_DYN_RFC (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x04C))\r
+#define EMC_DYN_XSR (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x050))\r
+#define EMC_DYN_RRD (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x054))\r
+#define EMC_DYN_MRD (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x058))\r
+\r
+#define EMC_DYN_CFG0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x100))\r
+#define EMC_DYN_RASCAS0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x104))\r
+#define EMC_DYN_CFG1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x140))\r
+#define EMC_DYN_RASCAS1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x144))\r
+#define EMC_DYN_CFG2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x160))\r
+#define EMC_DYN_RASCAS2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x164))\r
+#define EMC_DYN_CFG3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x180))\r
+#define EMC_DYN_RASCAS3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x184))\r
+\r
+/* static RAM access registers */\r
+#define EMC_STA_CFG0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x200))\r
+#define EMC_STA_WAITWEN0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x204))\r
+#define EMC_STA_WAITOEN0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x208))\r
+#define EMC_STA_WAITRD0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x20C))\r
+#define EMC_STA_WAITPAGE0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x210))\r
+#define EMC_STA_WAITWR0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x214))\r
+#define EMC_STA_WAITTURN0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x218))\r
+\r
+#define EMC_STA_CFG1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x220))\r
+#define EMC_STA_WAITWEN1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x224))\r
+#define EMC_STA_WAITOEN1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x228))\r
+#define EMC_STA_WAITRD1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x22C))\r
+#define EMC_STA_WAITPAGE1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x230))\r
+#define EMC_STA_WAITWR1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x234))\r
+#define EMC_STA_WAITTURN1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x238))\r
+\r
+#define EMC_STA_CFG2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x240))\r
+#define EMC_STA_WAITWEN2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x244))\r
+#define EMC_STA_WAITOEN2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x248))\r
+#define EMC_STA_WAITRD2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x24C))\r
+#define EMC_STA_WAITPAGE2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x250))\r
+#define EMC_STA_WAITWR2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x254))\r
+#define EMC_STA_WAITTURN2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x258))\r
+\r
+#define EMC_STA_CFG3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x260))\r
+#define EMC_STA_WAITWEN3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x264))\r
+#define EMC_STA_WAITOEN3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x268))\r
+#define EMC_STA_WAITRD3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x26C))\r
+#define EMC_STA_WAITPAGE3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x270))\r
+#define EMC_STA_WAITWR3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x274))\r
+#define EMC_STA_WAITTURN3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x278))\r
+\r
+#define EMC_STA_EXT_WAIT (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x880))\r
+\r
+ \r
+/* Timer 0 */\r
+#define TMR0_BASE_ADDR 0xE0004000\r
+#define T0IR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x00))\r
+#define T0TCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x04))\r
+#define T0TC (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x08))\r
+#define T0PR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x0C))\r
+#define T0PC (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x10))\r
+#define T0MCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x14))\r
+#define T0MR0 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x18))\r
+#define T0MR1 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x1C))\r
+#define T0MR2 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x20))\r
+#define T0MR3 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x24))\r
+#define T0CCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x28))\r
+#define T0CR0 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x2C))\r
+#define T0CR1 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x30))\r
+#define T0CR2 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x34))\r
+#define T0CR3 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x38))\r
+#define T0EMR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x3C))\r
+#define T0CTCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x70))\r
+\r
+/* Timer 1 */\r
+#define TMR1_BASE_ADDR 0xE0008000\r
+#define T1IR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x00))\r
+#define T1TCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x04))\r
+#define T1TC (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x08))\r
+#define T1PR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x0C))\r
+#define T1PC (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x10))\r
+#define T1MCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x14))\r
+#define T1MR0 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x18))\r
+#define T1MR1 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x1C))\r
+#define T1MR2 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x20))\r
+#define T1MR3 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x24))\r
+#define T1CCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x28))\r
+#define T1CR0 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x2C))\r
+#define T1CR1 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x30))\r
+#define T1CR2 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x34))\r
+#define T1CR3 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x38))\r
+#define T1EMR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x3C))\r
+#define T1CTCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x70))\r
+\r
+/* Timer 2 */\r
+#define TMR2_BASE_ADDR 0xE0070000\r
+#define T2IR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x00))\r
+#define T2TCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x04))\r
+#define T2TC (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x08))\r
+#define T2PR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x0C))\r
+#define T2PC (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x10))\r
+#define T2MCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x14))\r
+#define T2MR0 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x18))\r
+#define T2MR1 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x1C))\r
+#define T2MR2 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x20))\r
+#define T2MR3 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x24))\r
+#define T2CCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x28))\r
+#define T2CR0 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x2C))\r
+#define T2CR1 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x30))\r
+#define T2CR2 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x34))\r
+#define T2CR3 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x38))\r
+#define T2EMR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x3C))\r
+#define T2CTCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x70))\r
+\r
+/* Timer 3 */\r
+#define TMR3_BASE_ADDR 0xE0074000\r
+#define T3IR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x00))\r
+#define T3TCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x04))\r
+#define T3TC (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x08))\r
+#define T3PR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x0C))\r
+#define T3PC (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x10))\r
+#define T3MCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x14))\r
+#define T3MR0 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x18))\r
+#define T3MR1 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x1C))\r
+#define T3MR2 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x20))\r
+#define T3MR3 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x24))\r
+#define T3CCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x28))\r
+#define T3CR0 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x2C))\r
+#define T3CR1 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x30))\r
+#define T3CR2 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x34))\r
+#define T3CR3 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x38))\r
+#define T3EMR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x3C))\r
+#define T3CTCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x70))\r
+\r
+\r
+/* Pulse Width Modulator (PWM) */\r
+#define PWM0_BASE_ADDR 0xE0014000\r
+#define PWM0IR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x00))\r
+#define PWM0TCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x04))\r
+#define PWM0TC (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x08))\r
+#define PWM0PR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x0C))\r
+#define PWM0PC (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x10))\r
+#define PWM0MCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x14))\r
+#define PWM0MR0 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x18))\r
+#define PWM0MR1 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x1C))\r
+#define PWM0MR2 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x20))\r
+#define PWM0MR3 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x24))\r
+#define PWM0CCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x28))\r
+#define PWM0CR0 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x2C))\r
+#define PWM0CR1 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x30))\r
+#define PWM0CR2 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x34))\r
+#define PWM0CR3 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x38))\r
+#define PWM0EMR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x3C))\r
+#define PWM0MR4 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x40))\r
+#define PWM0MR5 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x44))\r
+#define PWM0MR6 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x48))\r
+#define PWM0PCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x4C))\r
+#define PWM0LER (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x50))\r
+#define PWM0CTCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x70))\r
+\r
+#define PWM1_BASE_ADDR 0xE0018000\r
+#define PWM1IR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x00))\r
+#define PWM1TCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x04))\r
+#define PWM1TC (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x08))\r
+#define PWM1PR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x0C))\r
+#define PWM1PC (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x10))\r
+#define PWM1MCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x14))\r
+#define PWM1MR0 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x18))\r
+#define PWM1MR1 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x1C))\r
+#define PWM1MR2 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x20))\r
+#define PWM1MR3 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x24))\r
+#define PWM1CCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x28))\r
+#define PWM1CR0 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x2C))\r
+#define PWM1CR1 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x30))\r
+#define PWM1CR2 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x34))\r
+#define PWM1CR3 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x38))\r
+#define PWM1EMR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x3C))\r
+#define PWM1MR4 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x40))\r
+#define PWM1MR5 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x44))\r
+#define PWM1MR6 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x48))\r
+#define PWM1PCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x4C))\r
+#define PWM1LER (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x50))\r
+#define PWM1CTCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x70))\r
+\r
+\r
+/* Universal Asynchronous Receiver Transmitter 0 (UART0) */\r
+#define UART0_BASE_ADDR 0xE000C000\r
+#define U0RBR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x00))\r
+#define U0THR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x00))\r
+#define U0DLL (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x00))\r
+#define U0DLM (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x04))\r
+#define U0IER (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x04))\r
+#define U0IIR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x08))\r
+#define U0FCR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x08))\r
+#define U0LCR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x0C))\r
+#define U0LSR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x14))\r
+#define U0SCR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x1C))\r
+#define U0ACR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x20))\r
+#define U0ICR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x24))\r
+#define U0FDR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x28))\r
+#define U0TER (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x30))\r
+\r
+/* Universal Asynchronous Receiver Transmitter 1 (UART1) */\r
+#define UART1_BASE_ADDR 0xE0010000\r
+#define U1RBR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x00))\r
+#define U1THR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x00))\r
+#define U1DLL (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x00))\r
+#define U1DLM (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x04))\r
+#define U1IER (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x04))\r
+#define U1IIR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x08))\r
+#define U1FCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x08))\r
+#define U1LCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x0C))\r
+#define U1MCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x10))\r
+#define U1LSR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x14))\r
+#define U1MSR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x18))\r
+#define U1SCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x1C))\r
+#define U1ACR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x20))\r
+#define U1FDR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x28))\r
+#define U1TER (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x30))\r
+\r
+/* Universal Asynchronous Receiver Transmitter 2 (UART2) */\r
+#define UART2_BASE_ADDR 0xE0078000\r
+#define U2RBR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x00))\r
+#define U2THR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x00))\r
+#define U2DLL (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x00))\r
+#define U2DLM (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x04))\r
+#define U2IER (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x04))\r
+#define U2IIR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x08))\r
+#define U2FCR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x08))\r
+#define U2LCR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x0C))\r
+#define U2LSR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x14))\r
+#define U2SCR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x1C))\r
+#define U2ACR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x20))\r
+#define U2ICR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x24))\r
+#define U2FDR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x28))\r
+#define U2TER (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x30))\r
+\r
+/* Universal Asynchronous Receiver Transmitter 3 (UART3) */\r
+#define UART3_BASE_ADDR 0xE007C000\r
+#define U3RBR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x00))\r
+#define U3THR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x00))\r
+#define U3DLL (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x00))\r
+#define U3DLM (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x04))\r
+#define U3IER (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x04))\r
+#define U3IIR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x08))\r
+#define U3FCR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x08))\r
+#define U3LCR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x0C))\r
+#define U3LSR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x14))\r
+#define U3SCR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x1C))\r
+#define U3ACR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x20))\r
+#define U3ICR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x24))\r
+#define U3FDR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x28))\r
+#define U3TER (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x30))\r
+\r
+/* I2C Interface 0 */\r
+#define I2C0_BASE_ADDR 0xE001C000\r
+#define I20CONSET (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x00))\r
+#define I20STAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x04))\r
+#define I20DAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x08))\r
+#define I20ADR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x0C))\r
+#define I20SCLH (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x10))\r
+#define I20SCLL (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x14))\r
+#define I20CONCLR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x18))\r
+//Slightly different naming\r
+#define I2C0CONSET (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x00))\r
+#define I2C0STAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x04))\r
+#define I2C0DAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x08))\r
+#define I2C0ADR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x0C))\r
+#define I2C0SCLH (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x10))\r
+#define I2C0SCLL (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x14))\r
+#define I2C0CONCLR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x18))\r
+\r
+\r
+/* I2C Interface 1 */\r
+#define I2C1_BASE_ADDR 0xE005C000\r
+#define I21CONSET (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x00))\r
+#define I21STAT (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x04))\r
+#define I21DAT (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x08))\r
+#define I21ADR (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x0C))\r
+#define I21SCLH (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x10))\r
+#define I21SCLL (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x14))\r
+#define I21CONCLR (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x18))\r
+\r
+/* I2C Interface 2 */\r
+#define I2C2_BASE_ADDR 0xE0080000\r
+#define I22CONSET (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x00))\r
+#define I22STAT (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x04))\r
+#define I22DAT (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x08))\r
+#define I22ADR (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x0C))\r
+#define I22SCLH (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x10))\r
+#define I22SCLL (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x14))\r
+#define I22CONCLR (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x18))\r
+\r
+/* SPI0 (Serial Peripheral Interface 0) */\r
+#define SPI0_BASE_ADDR 0xE0020000\r
+#define S0SPCR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x00))\r
+#define S0SPSR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x04))\r
+#define S0SPDR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x08))\r
+#define S0SPCCR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x0C))\r
+#define S0SPINT (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x1C))\r
+\r
+/* SSP0 Controller */\r
+#define SSP0_BASE_ADDR 0xE0068000\r
+#define SSP0CR0 (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x00))\r
+#define SSP0CR1 (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x04))\r
+#define SSP0DR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x08))\r
+#define SSP0SR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x0C))\r
+#define SSP0CPSR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x10))\r
+#define SSP0IMSC (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x14))\r
+#define SSP0RIS (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x18))\r
+#define SSP0MIS (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x1C))\r
+#define SSP0ICR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x20))\r
+#define SSP0DMACR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x24))\r
+\r
+/* SSP1 Controller */\r
+#define SSP1_BASE_ADDR 0xE0030000\r
+#define SSP1CR0 (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x00))\r
+#define SSP1CR1 (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x04))\r
+#define SSP1DR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x08))\r
+#define SSP1SR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x0C))\r
+#define SSP1CPSR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x10))\r
+#define SSP1IMSC (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x14))\r
+#define SSP1RIS (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x18))\r
+#define SSP1MIS (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x1C))\r
+#define SSP1ICR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x20))\r
+#define SSP1DMACR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x24))\r
+\r
+\r
+/* Real Time Clock */\r
+#define RTC_BASE_ADDR 0xE0024000\r
+#define RTC_ILR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x00))\r
+#define RTC_CTC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x04))\r
+#define RTC_CCR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x08))\r
+#define RTC_CIIR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x0C))\r
+#define RTC_AMR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x10))\r
+#define RTC_CTIME0 (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x14))\r
+#define RTC_CTIME1 (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x18))\r
+#define RTC_CTIME2 (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x1C))\r
+#define RTC_SEC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x20))\r
+#define RTC_MIN (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x24))\r
+#define RTC_HOUR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x28))\r
+#define RTC_DOM (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x2C))\r
+#define RTC_DOW (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x30))\r
+#define RTC_DOY (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x34))\r
+#define RTC_MONTH (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x38))\r
+#define RTC_YEAR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x3C))\r
+#define RTC_CISS (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x40))\r
+#define RTC_ALSEC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x60))\r
+#define RTC_ALMIN (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x64))\r
+#define RTC_ALHOUR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x68))\r
+#define RTC_ALDOM (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x6C))\r
+#define RTC_ALDOW (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x70))\r
+#define RTC_ALDOY (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x74))\r
+#define RTC_ALMON (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x78))\r
+#define RTC_ALYEAR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x7C))\r
+#define RTC_PREINT (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x80))\r
+#define RTC_PREFRAC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x84))\r
+\r
+\r
+/* A/D Converter 0 (AD0) */\r
+#define AD0_BASE_ADDR 0xE0034000\r
+#define AD0CR (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x00))\r
+#define AD0GDR (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x04))\r
+#define AD0INTEN (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x0C))\r
+#define AD0DR0 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x10))\r
+#define AD0DR1 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x14))\r
+#define AD0DR2 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x18))\r
+#define AD0DR3 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x1C))\r
+#define AD0DR4 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x20))\r
+#define AD0DR5 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x24))\r
+#define AD0DR6 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x28))\r
+#define AD0DR7 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x2C))\r
+#define AD0STAT (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x30))\r
+\r
+\r
+/* D/A Converter */\r
+#define DAC_BASE_ADDR 0xE006C000\r
+#define DACR (*(volatile unsigned int *)(DAC_BASE_ADDR + 0x00))\r
+\r
+\r
+/* Watchdog */\r
+#define WDG_BASE_ADDR 0xE0000000\r
+#define WDMOD (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x00))\r
+#define WDTC (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x04))\r
+#define WDFEED (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x08))\r
+#define WDTV (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x0C))\r
+#define WDCLKSEL (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x10))\r
+\r
+/* CAN CONTROLLERS AND ACCEPTANCE FILTER */\r
+#define CAN_ACCEPT_BASE_ADDR 0xE003C000\r
+#define CAN_AFMR (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x00)) \r
+#define CAN_SFF_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x04)) \r
+#define CAN_SFF_GRP_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x08))\r
+#define CAN_EFF_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x0C))\r
+#define CAN_EFF_GRP_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x10)) \r
+#define CAN_EOT (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x14))\r
+#define CAN_LUT_ERR_ADR (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x18)) \r
+#define CAN_LUT_ERR (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x1C))\r
+\r
+#define CAN_CENTRAL_BASE_ADDR 0xE0040000 \r
+#define CAN_TX_SR (*(volatile unsigned int *)(CAN_CENTRAL_BASE_ADDR + 0x00)) \r
+#define CAN_RX_SR (*(volatile unsigned int *)(CAN_CENTRAL_BASE_ADDR + 0x04)) \r
+#define CAN_MSR (*(volatile unsigned int *)(CAN_CENTRAL_BASE_ADDR + 0x08))\r
+\r
+#define CAN1_BASE_ADDR 0xE0044000\r
+#define CAN1MOD (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x00)) \r
+#define CAN1CMR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x04)) \r
+#define CAN1GSR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x08)) \r
+#define CAN1ICR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x0C)) \r
+#define CAN1IER (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x10))\r
+#define CAN1BTR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x14)) \r
+#define CAN1EWL (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x18)) \r
+#define CAN1SR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x1C)) \r
+#define CAN1RFS (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x20)) \r
+#define CAN1RID (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x24))\r
+#define CAN1RDA (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x28)) \r
+#define CAN1RDB (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x2C))\r
+ \r
+#define CAN1TFI1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x30)) \r
+#define CAN1TID1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x34)) \r
+#define CAN1TDA1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x38))\r
+#define CAN1TDB1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x3C)) \r
+#define CAN1TFI2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x40)) \r
+#define CAN1TID2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x44)) \r
+#define CAN1TDA2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x48)) \r
+#define CAN1TDB2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x4C))\r
+#define CAN1TFI3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x50)) \r
+#define CAN1TID3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x54)) \r
+#define CAN1TDA3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x58)) \r
+#define CAN1TDB3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x5C))\r
+\r
+#define CAN2_BASE_ADDR 0xE0048000\r
+#define CAN2MOD (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x00)) \r
+#define CAN2CMR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x04)) \r
+#define CAN2GSR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x08)) \r
+#define CAN2ICR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x0C)) \r
+#define CAN2IER (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x10))\r
+#define CAN2BTR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x14)) \r
+#define CAN2EWL (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x18)) \r
+#define CAN2SR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x1C)) \r
+#define CAN2RFS (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x20)) \r
+#define CAN2RID (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x24))\r
+#define CAN2RDA (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x28)) \r
+#define CAN2RDB (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x2C))\r
+ \r
+#define CAN2TFI1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x30)) \r
+#define CAN2TID1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x34)) \r
+#define CAN2TDA1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x38))\r
+#define CAN2TDB1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x3C)) \r
+#define CAN2TFI2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x40)) \r
+#define CAN2TID2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x44)) \r
+#define CAN2TDA2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x48)) \r
+#define CAN2TDB2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x4C))\r
+#define CAN2TFI3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x50)) \r
+#define CAN2TID3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x54)) \r
+#define CAN2TDA3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x58)) \r
+#define CAN2TDB3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x5C))\r
+\r
+\r
+/* MultiMedia Card Interface(MCI) Controller */\r
+#define MCI_BASE_ADDR 0xE008C000\r
+#define MCI_POWER (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x00))\r
+#define MCI_CLOCK (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x04))\r
+#define MCI_ARGUMENT (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x08))\r
+#define MCI_COMMAND (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x0C))\r
+#define MCI_RESP_CMD (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x10))\r
+#define MCI_RESP0 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x14))\r
+#define MCI_RESP1 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x18))\r
+#define MCI_RESP2 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x1C))\r
+#define MCI_RESP3 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x20))\r
+#define MCI_DATA_TMR (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x24))\r
+#define MCI_DATA_LEN (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x28))\r
+#define MCI_DATA_CTRL (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x2C))\r
+#define MCI_DATA_CNT (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x30))\r
+#define MCI_STATUS (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x34))\r
+#define MCI_CLEAR (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x38))\r
+#define MCI_MASK0 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x3C))\r
+#define MCI_MASK1 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x40))\r
+#define MCI_FIFO_CNT (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x48))\r
+#define MCI_FIFO (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x80))\r
+\r
+\r
+/* I2S Interface Controller (I2S) */\r
+#define I2S_BASE_ADDR 0xE0088000\r
+#define I2S_DAO (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x00))\r
+#define I2S_DAI (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x04))\r
+#define I2S_TX_FIFO (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x08))\r
+#define I2S_RX_FIFO (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x0C))\r
+#define I2S_STATE (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x10))\r
+#define I2S_DMA1 (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x14))\r
+#define I2S_DMA2 (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x18))\r
+#define I2S_IRQ (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x1C))\r
+#define I2S_TXRATE (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x20))\r
+#define I2S_RXRATE (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x24))\r
+\r
+\r
+/* General-purpose DMA Controller */\r
+#define DMA_BASE_ADDR 0xFFE04000\r
+#define GPDMA_INT_STAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x000))\r
+#define GPDMA_INT_TCSTAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x004))\r
+#define GPDMA_INT_TCCLR (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x008))\r
+#define GPDMA_INT_ERR_STAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x00C))\r
+#define GPDMA_INT_ERR_CLR (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x010))\r
+#define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x014))\r
+#define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x018))\r
+#define GPDMA_ENABLED_CHNS (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x01C))\r
+#define GPDMA_SOFT_BREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x020))\r
+#define GPDMA_SOFT_SREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x024))\r
+#define GPDMA_SOFT_LBREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x028))\r
+#define GPDMA_SOFT_LSREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x02C))\r
+#define GPDMA_CONFIG (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x030))\r
+#define GPDMA_SYNC (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x034))\r
+\r
+/* DMA channel 0 registers */\r
+#define GPDMA_CH0_SRC (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x100))\r
+#define GPDMA_CH0_DEST (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x104))\r
+#define GPDMA_CH0_LLI (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x108))\r
+#define GPDMA_CH0_CTRL (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x10C))\r
+#define GPDMA_CH0_CFG (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x110))\r
+\r
+/* DMA channel 1 registers */\r
+#define GPDMA_CH1_SRC (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x120))\r
+#define GPDMA_CH1_DEST (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x124))\r
+#define GPDMA_CH1_LLI (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x128))\r
+#define GPDMA_CH1_CTRL (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x12C))\r
+#define GPDMA_CH1_CFG (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x130))\r
+\r
+\r
+/* USB Controller */\r
+#define USB_INT_BASE_ADDR 0xE01FC1C0\r
+#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */\r
+\r
+#define USB_INT_STAT (*(volatile unsigned int *)(USB_INT_BASE_ADDR + 0x00))\r
+\r
+/* USB Device Interrupt Registers */\r
+#define DEV_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x00))\r
+#define DEV_INT_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x04))\r
+#define DEV_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0x08))\r
+#define DEV_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0x0C))\r
+#define DEV_INT_PRIO (*(volatile unsigned int *)(USB_BASE_ADDR + 0x2C))\r
+\r
+/* USB Device Endpoint Interrupt Registers */\r
+#define EP_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x30))\r
+#define EP_INT_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x34))\r
+#define EP_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0x38))\r
+#define EP_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0x3C))\r
+#define EP_INT_PRIO (*(volatile unsigned int *)(USB_BASE_ADDR + 0x40))\r
+\r
+/* USB Device Endpoint Realization Registers */\r
+#define REALIZE_EP (*(volatile unsigned int *)(USB_BASE_ADDR + 0x44))\r
+#define EP_INDEX (*(volatile unsigned int *)(USB_BASE_ADDR + 0x48))\r
+#define MAXPACKET_SIZE (*(volatile unsigned int *)(USB_BASE_ADDR + 0x4C))\r
+\r
+/* USB Device Command Reagisters */\r
+#define CMD_CODE (*(volatile unsigned int *)(USB_BASE_ADDR + 0x10))\r
+#define CMD_DATA (*(volatile unsigned int *)(USB_BASE_ADDR + 0x14))\r
+\r
+/* USB Device Data Transfer Registers */\r
+#define RX_DATA (*(volatile unsigned int *)(USB_BASE_ADDR + 0x18))\r
+#define TX_DATA (*(volatile unsigned int *)(USB_BASE_ADDR + 0x1C))\r
+#define RX_PLENGTH (*(volatile unsigned int *)(USB_BASE_ADDR + 0x20))\r
+#define TX_PLENGTH (*(volatile unsigned int *)(USB_BASE_ADDR + 0x24))\r
+#define USB_CTRL (*(volatile unsigned int *)(USB_BASE_ADDR + 0x28))\r
+\r
+/* USB Device DMA Registers */\r
+#define DMA_REQ_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x50))\r
+#define DMA_REQ_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0x54))\r
+#define DMA_REQ_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0x58))\r
+#define UDCA_HEAD (*(volatile unsigned int *)(USB_BASE_ADDR + 0x80))\r
+#define EP_DMA_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x84))\r
+#define EP_DMA_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x88))\r
+#define EP_DMA_DIS (*(volatile unsigned int *)(USB_BASE_ADDR + 0x8C))\r
+#define DMA_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x90))\r
+#define DMA_INT_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x94))\r
+#define EOT_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0xA0))\r
+#define EOT_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0xA4))\r
+#define EOT_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0xA8))\r
+#define NDD_REQ_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0xAC))\r
+#define NDD_REQ_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0xB0))\r
+#define NDD_REQ_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0xB4))\r
+#define SYS_ERR_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0xB8))\r
+#define SYS_ERR_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0xBC))\r
+#define SYS_ERR_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0xC0))\r
+\r
+\r
+/* USB Host Controller */\r
+#define USBHC_BASE_ADDR 0xFFE0C000\r
+#define HC_REVISION (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x00))\r
+#define HC_CONTROL (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x04))\r
+#define HC_CMD_STAT (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x08))\r
+#define HC_INT_STAT (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x0C))\r
+#define HC_INT_EN (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x10))\r
+#define HC_INT_DIS (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x14))\r
+#define HC_HCCA (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x18))\r
+#define HC_PERIOD_CUR_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x1C))\r
+#define HC_CTRL_HEAD_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x20))\r
+#define HC_CTRL_CUR_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x24))\r
+#define HC_BULK_HEAD_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x28))\r
+#define HC_BULK_CUR_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x2C))\r
+#define HC_DONE_HEAD (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x30))\r
+#define HC_FM_INTERVAL (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x34))\r
+#define HC_FM_REMAINING (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x38))\r
+#define HC_FM_NUMBER (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x3C))\r
+#define HC_PERIOD_START (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x40))\r
+#define HC_LS_THRHLD (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x44))\r
+#define HC_RH_DESCA (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x48))\r
+#define HC_RH_DESCB (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x4C))\r
+#define HC_RH_STAT (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x50))\r
+#define HC_RH_PORT_STAT1 (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x54))\r
+#define HC_RH_PORT_STAT2 (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x58))\r
+\r
+/* USB OTG Controller */\r
+#define USBOTG_BASE_ADDR 0xFFE0C100\r
+#define OTG_INT_STAT (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x00))\r
+#define OTG_INT_EN (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x04))\r
+#define OTG_INT_SET (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x08))\r
+#define OTG_INT_CLR (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x0C))\r
+#define OTG_STAT_CTRL (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x10))\r
+#define OTG_TIMER (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x14))\r
+\r
+#define USBOTG_I2C_BASE_ADDR 0xFFE0C300\r
+#define OTG_I2C_RX (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x00))\r
+#define OTG_I2C_TX (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x00))\r
+#define OTG_I2C_STS (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x04))\r
+#define OTG_I2C_CTL (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x08))\r
+#define OTG_I2C_CLKHI (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x0C))\r
+#define OTG_I2C_CLKLO (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x10))\r
+\r
+#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0\r
+#define OTG_CLK_CTRL (*(volatile unsigned int *)(USBOTG_CLK_BASE_ADDR + 0x04))\r
+#define OTG_CLK_STAT (*(volatile unsigned int *)(USBOTG_CLK_BASE_ADDR + 0x08))\r
+\r
+\r
+/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */\r
+#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */\r
+#define MAC_MAC1 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */\r
+#define MAC_MAC2 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */\r
+#define MAC_IPGT (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */\r
+#define MAC_IPGR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */\r
+#define MAC_CLRT (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */\r
+#define MAC_MAXF (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */\r
+#define MAC_SUPP (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */\r
+#define MAC_TEST (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */\r
+#define MAC_MCFG (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */\r
+#define MAC_MCMD (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */\r
+#define MAC_MADR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */\r
+#define MAC_MWTD (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */\r
+#define MAC_MRDD (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */\r
+#define MAC_MIND (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */\r
+\r
+#define MAC_SA0 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */\r
+#define MAC_SA1 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */\r
+#define MAC_SA2 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */\r
+\r
+#define MAC_COMMAND (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x100)) /* Command reg */\r
+#define MAC_STATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */\r
+#define MAC_RXDESCRIPTOR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */\r
+#define MAC_RXSTATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */\r
+#define MAC_RXDESCRIPTORNUM (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */\r
+#define MAC_RXPRODUCEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */\r
+#define MAC_RXCONSUMEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */\r
+#define MAC_TXDESCRIPTOR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */\r
+#define MAC_TXSTATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */\r
+#define MAC_TXDESCRIPTORNUM (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */\r
+#define MAC_TXPRODUCEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */\r
+#define MAC_TXCONSUMEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */\r
+\r
+#define MAC_TSV0 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */\r
+#define MAC_TSV1 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */\r
+#define MAC_RSV (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */\r
+\r
+#define MAC_FLOWCONTROLCNT (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */\r
+#define MAC_FLOWCONTROLSTS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */\r
+\r
+#define MAC_RXFILTERCTRL (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */\r
+#define MAC_RXFILTERWOLSTS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */\r
+#define MAC_RXFILTERWOLCLR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */\r
+\r
+#define MAC_HASHFILTERL (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */\r
+#define MAC_HASHFILTERH (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */\r
+\r
+#define MAC_INTSTATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */\r
+#define MAC_INTENABLE (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */\r
+#define MAC_INTCLEAR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */\r
+#define MAC_INTSET (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */\r
+\r
+#define MAC_POWERDOWN (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */\r
+#define MAC_MODULEID (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */\r
+\r
+\r
+#endif /* __LPC23xx_H */\r
+\r
projects / freertos / commitdiff