NRF5_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
NRF5_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
+ /* nRF52832 Devices */
+ NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512),
+
/* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
with built-in jlink seem to use engineering samples not listed
in the nRF51 Series Compatibility Matrix V1.0. */
set _CHIPNAME nrf52
}
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x4000
+}
+
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-adapter_khz 10000
+adapter_khz 1000
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
if { ![using_hla] } {
cortex_m reset_config sysresetreq
}
+
+flash bank $_CHIPNAME.flash nrf5 0x00000000 0 1 1 $_TARGETNAME
+flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 1 1 $_TARGETNAME