cfg: Beaglebone/AM335x refactor

Split out functions specific to the AM335x SOC into the target directory and simplified the board config
file.  This should allow one to quickly create new configs for boards based on the TI processor family.

Change-Id: I0c3db97950dfa832f1f1918fc10c180f068bba74
Signed-off-by: Neil Jensen <neil30al@gmail.com>
Reviewed-on: http://openocd.zylin.com/489
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

diff --git a/tcl/board/ti_beaglebone.cfg b/tcl/board/ti_beaglebone.cfg
index dffb07f83534dbd5ce0015e850010ea8b832c4cc..be4da201bc5af0fe98f6cde4da80224988d37b93 100644 (file)
--- a/tcl/board/ti_beaglebone.cfg
+++ b/tcl/board/ti_beaglebone.cfg
@@ -1,3 +1,7 @@
+# AM335x Beaglebone
+#  http://beagleboard.org/bone
+
+# The JTAG interface is built directly on the board.
 interface ft2232
 #ft2232_device_desc "BeagleBone A"
 ft2232_layout xds100v2
@@ -5,80 +9,8 @@ ft2232_vid_pid 0x0403 0xa6d0
 
 adapter_khz 16000
 
-reset_config trst_and_srst
-
-
-
-
-if { [info exists CHIPNAME] } {
-   set _CHIPNAME $CHIPNAME
-} else {
-   set _CHIPNAME am335x
-}
-
-proc icepick_d_tapenable {jrc port} {
-       # select router
-       irscan $jrc 7 -endstate IRPAUSE
-       drscan $jrc 8 0x89 -endstate DRPAUSE
-
-       # set ip control
-       irscan $jrc 2 -endstate IRPAUSE
-       drscan $jrc 32 [expr 0xa0002108 + ($port << 24)] -endstate DRPAUSE
+source [find target/am335x.cfg]
 
-       # for icepick_D
-       irscan $jrc 2 -endstate IRPAUSE
-       drscan $jrc 32 0xe0002008 -endstate DRPAUSE
-
-       irscan $jrc 0x3F -endstate RUN/IDLE
-       runtest 10
-}
-
-#
-# M3 DAP
-#
-if { [info exists M3_DAP_TAPID] } {
-       set _M3_DAP_TAPID $M3_DAP_TAPID
-} else {
-       set _M3_DAP_TAPID 0x4b6b902f
-}
-jtag newtap $_CHIPNAME m3_dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m3_dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11"
-
-#
-# Main DAP
-#
-if { [info exists DAP_TAPID ] } {
-   set _DAP_TAPID $DAP_TAPID
-} else {
-   set _DAP_TAPID 0x4b6b902f
-}
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12"
-
-#
-# ICEpick-D (JTAG route controller)
-#
-if { [info exists JRC_TAPID ] } {
-   set _JRC_TAPID $JRC_TAPID
-} else {
-   set _JRC_TAPID 0x0b94402f
-}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
-jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
-# some TCK tycles are required to activate the DEBUG power domain
-jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
-
-#
-# Cortex A8 target
-#
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
-
-# SRAM: 64K at 0x4030.0000; use the first 16K
-$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
+reset_config trst_and_srst
 
-$_TARGETNAME configure -event gdb-attach {
-   cortex_a8 dbginit
-   halt
-}
 

diff --git a/tcl/target/am335x.cfg b/tcl/target/am335x.cfg
new file mode 100644 (file)
index 0000000..99693dc
--- /dev/null
+++ b/tcl/target/am335x.cfg
@@ -0,0 +1,76 @@
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME am335x
+}
+
+# This chip contains an IcePick-D JTAG router.  The IcePick-C configuration is almost
+# compatible, but it doesn't work.  For now, we will just embed the IcePick-D
+# routines here.
+proc icepick_d_tapenable {jrc port} {
+       # select router
+       irscan $jrc 7 -endstate IRPAUSE
+       drscan $jrc 8 0x89 -endstate DRPAUSE
+
+       # set ip control
+       irscan $jrc 2 -endstate IRPAUSE
+       drscan $jrc 32 [expr 0xa0002108 + ($port << 24)] -endstate DRPAUSE
+
+       # for icepick_D
+       irscan $jrc 2 -endstate IRPAUSE
+       drscan $jrc 32 0xe0002008 -endstate DRPAUSE
+
+       irscan $jrc 0x3F -endstate RUN/IDLE
+       runtest 10
+}
+
+#
+# M3 DAP
+#
+if { [info exists M3_DAP_TAPID] } {
+       set _M3_DAP_TAPID $M3_DAP_TAPID
+} else {
+       set _M3_DAP_TAPID 0x4b6b902f
+}
+jtag newtap $_CHIPNAME m3_dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
+jtag configure $_CHIPNAME.m3_dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11"
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID ] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x4b6b902f
+}
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12"
+
+#
+# ICEpick-D (JTAG route controller)
+#
+if { [info exists JRC_TAPID ] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b94402f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+
+#
+# Cortex A8 target
+#
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
+
+# SRAM: 64K at 0x4030.0000; use the first 16K
+$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
+
+$_TARGETNAME configure -event gdb-attach {
+   cortex_a8 dbginit
+   halt
+}
+