add at91sam9261-ek support

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>

diff --git a/tcl/board/at91sam9261-ek.cfg b/tcl/board/at91sam9261-ek.cfg
new file mode 100644 (file)
index 0000000..3963e93
--- /dev/null
+++ b/tcl/board/at91sam9261-ek.cfg
@@ -0,0 +1,63 @@
+################################################################################
+# Atmel AT91SAM9261-EK eval board
+################################################################################
+
+source [find mem_helper.tcl]
+source [find target/at91sam9261.cfg]
+uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9261.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9261_matrix.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9261.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+scan_chain
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91sam9261ek_reset_init }
+$_TARGETNAME configure -event reset-start { at91sam9_reset_start }
+
+proc at91sam9261ek_reset_init { } {
+
+       ;# for ppla at 199 Mhz
+       set config(master_pll_div)      15
+       set config(master_pll_mul)      162
+
+       ;# for ppla at 239 Mhz
+       ;# set master_pll_div   1
+       ;# set master_pll_mul   13
+
+       set val [expr $::AT91_WDT_WDV]                  ;# Counter Value
+       set val [expr ($val | $::AT91_WDT_WDDIS)]       ;# Watchdog Disable
+       set val [expr ($val | $::AT91_WDT_WDD)]         ;# Delta Value
+       set val [expr ($val | $::AT91_WDT_WDDBGHLT)]    ;# Debug Halt
+       set val [expr ($val | $::AT91_WDT_WDIDLEHLT)]   ;# Idle Halt
+
+       set config(wdt_mr_val) $val
+
+       ;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
+       set config(matrix_ebicsa_addr)  $::AT91_MATRIX_EBICSA
+       set config(matrix_ebicsa_val) [expr ($::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC)]
+
+       ;# SDRAMC_CR - Configuration register
+       set val [expr $::AT91_SDRAMC_NC_9]
+       set val [expr ($val | $::AT91_SDRAMC_NR_13)]
+       set val [expr ($val | $::AT91_SDRAMC_NB_4)]
+       set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
+       set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
+       set val [expr ($val | (2 <<  8))]               ;# Write Recovery Delay
+       set val [expr ($val | (7 << 12))]               ;# Row Cycle Delay
+       set val [expr ($val | (3 << 16))]               ;# Row Precharge Delay
+       set val [expr ($val | (2 << 20))]               ;# Row to Column Delay
+       set val [expr ($val | (5 << 24))]               ;# Active to Precharge Delay
+       set val [expr ($val | (8 << 28))]               ;# Exit Self Refresh to Active Delay
+
+       set config(sdram_cr_val) $val
+
+       set config(sdram_tr_val) 0x13c
+
+       set config(sdram_base) $::AT91_CHIPSELECT_1
+       at91sam9_reset_init $config
+}