]> git.sur5r.net Git - freertos/commitdiff
Update port layers to make better use of the xTaskIncrementTick() return value.
authorrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sat, 8 Jun 2013 18:36:25 +0000 (18:36 +0000)
committerrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sat, 8 Jun 2013 18:36:25 +0000 (18:36 +0000)
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1928 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portISR.c
FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portISR.c
FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79
FreeRTOS/Source/portable/IAR/MSP430/portext.s43
FreeRTOS/Source/portable/IAR/MSP430X/portext.s43
FreeRTOS/Source/portable/IAR/RL78/portasm.s87
FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/port.c
FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portASM.s
FreeRTOS/Source/portable/Rowley/MSP430F449/portext.asm

index 02dbf8eee9e51c5d998fa5de8f1e951fcd907775..c46286a281ba2c5097090713d0bd06345188c946 100644 (file)
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 \r
 \r
 /*\r
        Changes from V2.5.2\r
-               \r
+\r
        + The critical section management functions have been changed.  These no\r
          longer modify the stack and are safe to use at all optimisation levels.\r
          The functions are now also the same for both ARM and THUMB modes.\r
 \r
        Changes from V2.6.0\r
 \r
-       + Removed the 'static' from the definition of vNonPreemptiveTick() to \r
+       + Removed the 'static' from the definition of vNonPreemptiveTick() to\r
          allow the demo to link when using the cooperative scheduler.\r
 \r
        Changes from V3.2.4\r
@@ -114,7 +114,7 @@ volatile unsigned long ulCriticalNesting = 9999UL;
 /* ISR to handle manual context switches (from a call to taskYIELD()). */\r
 void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));\r
 \r
-/* \r
+/*\r
  * The scheduler can only be started from ARM mode, hence the inclusion of this\r
  * function here.\r
  */\r
@@ -132,15 +132,15 @@ void vPortISRStartFirstTask( void )
 /*\r
  * Called by portYIELD() or taskYIELD() to manually force a context switch.\r
  *\r
- * When a context switch is performed from the task level the saved task \r
+ * When a context switch is performed from the task level the saved task\r
  * context is made to look as if it occurred from within the tick ISR.  This\r
  * way the same restore context function can be used when restoring the context\r
  * saved from the ISR or that saved from a call to vPortYieldProcessor.\r
  */\r
 void vPortYieldProcessor( void )\r
 {\r
-       /* Within an IRQ ISR the link register has an offset from the true return \r
-       address, but an SWI ISR does not.  Add the offset manually so the same \r
+       /* Within an IRQ ISR the link register has an offset from the true return\r
+       address, but an SWI ISR does not.  Add the offset manually so the same\r
        ISR return code can be used in both cases. */\r
        __asm volatile ( "ADD           LR, LR, #4" );\r
 \r
@@ -151,31 +151,34 @@ void vPortYieldProcessor( void )
        __asm volatile ( "bl vTaskSwitchContext" );\r
 \r
        /* Restore the context of the new task. */\r
-       portRESTORE_CONTEXT();  \r
+       portRESTORE_CONTEXT();\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
-/* \r
+/*\r
  * The ISR used for the scheduler tick.\r
  */\r
 void vTickISR( void ) __attribute__((naked));\r
 void vTickISR( void )\r
 {\r
        /* Save the context of the interrupted task. */\r
-       portSAVE_CONTEXT();     \r
+       portSAVE_CONTEXT();\r
 \r
-       /* Increment the RTOS tick count, then look for the highest priority \r
+       /* Increment the RTOS tick count, then look for the highest priority\r
        task that is ready to run. */\r
-       __asm volatile( "bl xTaskIncrementTick" );\r
-\r
-       #if configUSE_PREEMPTION == 1\r
-               __asm volatile( "bl vTaskSwitchContext" );\r
-       #endif\r
+       __asm volatile\r
+       (\r
+               "       bl xTaskIncrementTick   \t\n" \\r
+               "       cmp r0, #0                              \t\n" \\r
+               "       beq SkipContextSwitch   \t\n" \\r
+               "       bl vTaskSwitchContext   \t\n" \\r
+               "SkipContextSwitch:                     \t\n"\r
+       );\r
 \r
        /* Ready for the next interrupt. */\r
        T0_IR = portTIMER_MATCH_ISR_BIT;\r
        VICVectAddr = portCLEAR_VIC_INTERRUPT;\r
-       \r
+\r
        /* Restore the context of the new task. */\r
        portRESTORE_CONTEXT();\r
 }\r
@@ -194,7 +197,7 @@ void vTickISR( void )
 \r
        void vPortDisableInterruptsFromThumb( void )\r
        {\r
-               __asm volatile ( \r
+               __asm volatile (\r
                        "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */\r
                        "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */\r
                        "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                                            */\r
@@ -202,14 +205,14 @@ void vTickISR( void )
                        "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */\r
                        "BX             R14" );                                 /* Return back to thumb.                                        */\r
        }\r
-                       \r
+\r
        void vPortEnableInterruptsFromThumb( void )\r
        {\r
-               __asm volatile ( \r
-                       "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */      \r
-                       "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */      \r
-                       "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                                                     */      \r
-                       "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */      \r
+               __asm volatile (\r
+                       "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */\r
+                       "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */\r
+                       "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                                                     */\r
+                       "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */\r
                        "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */\r
                        "BX             R14" );                                 /* Return back to thumb.                                        */\r
        }\r
@@ -223,14 +226,14 @@ in a variable, which is then saved as part of the stack context. */
 void vPortEnterCritical( void )\r
 {\r
        /* Disable interrupts as per portDISABLE_INTERRUPTS();                                                  */\r
-       __asm volatile ( \r
+       __asm volatile (\r
                "STMDB  SP!, {R0}                       \n\t"   /* Push R0.                                                             */\r
                "MRS    R0, CPSR                        \n\t"   /* Get CPSR.                                                    */\r
                "ORR    R0, R0, #0xC0           \n\t"   /* Disable IRQ, FIQ.                                    */\r
                "MSR    CPSR, R0                        \n\t"   /* Write back modified value.                   */\r
                "LDMIA  SP!, {R0}" );                           /* Pop R0.                                                              */\r
 \r
-       /* Now interrupts are disabled ulCriticalNesting can be accessed \r
+       /* Now interrupts are disabled ulCriticalNesting can be accessed\r
        directly.  Increment ulCriticalNesting to keep a count of how many times\r
        portENTER_CRITICAL() has been called. */\r
        ulCriticalNesting++;\r
@@ -248,11 +251,11 @@ void vPortExitCritical( void )
                if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
                {\r
                        /* Enable interrupts as per portEXIT_CRITICAL().                                        */\r
-                       __asm volatile ( \r
-                               "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \r
-                               "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \r
-                               "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */      \r
-                               "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */      \r
+                       __asm volatile (\r
+                               "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */\r
+                               "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */\r
+                               "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */\r
+                               "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */\r
                                "LDMIA  SP!, {R0}" );                   /* Pop R0.                                              */\r
                }\r
        }\r
index e39026f1ca63bf8d3f11a83248f9809ddc4bdd6d..004010d9a0c8016261f689a1700c2a986d097c0b 100644 (file)
@@ -167,8 +167,14 @@ void vPortYieldProcessor( void )
 \r
                /* Increment the RTOS tick count, then look for the highest priority \r
                task that is ready to run. */\r
-               __asm volatile( "bl xTaskIncrementTick" );\r
-               __asm volatile( "bl vTaskSwitchContext" );\r
+               __asm volatile\r
+               (\r
+                       "       bl xTaskIncrementTick   \t\n" \\r
+                       "       cmp r0, #0                              \t\n" \\r
+                       "       beq SkipContextSwitch   \t\n" \\r
+                       "       bl vTaskSwitchContext   \t\n" \\r
+                       "SkipContextSwitch:                     \t\n"\r
+               );\r
 \r
                /* Ready for the next interrupt. */\r
                T0IR = 2;\r
index 8752bec8ade2c657e3b0121e3a2f1a329d16cfb1..7536f39ee66c4779a046edc5a5ff0a5e2b2f5045 100644 (file)
@@ -74,10 +74,10 @@ vPortStartFirstTask:
 ; Manual context switch function.  This is the SWI hander.\r
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
 vPortYieldProcessor:\r
-       ADD             LR, LR, #4                      ; Add 4 to the LR to make the LR appear exactly \r
-                                                               ; as if the context was saved during and IRQ \r
+       ADD             LR, LR, #4                      ; Add 4 to the LR to make the LR appear exactly\r
+                                                               ; as if the context was saved during and IRQ\r
                                                                ; handler.\r
-                                                               \r
+\r
        portSAVE_CONTEXT                        ; Save the context of the current task...\r
        LDR R0, =vTaskSwitchContext     ; before selecting the next task to execute.\r
        mov     lr, pc\r
@@ -94,10 +94,13 @@ vPortPreemptiveTick:
        LDR R0, =xTaskIncrementTick ; Increment the tick count - this may wake a task.\r
        mov lr, pc\r
        BX R0\r
+\r
+       CMP R0, #0\r
+       BEQ SkipContextSwitch\r
        LDR R0, =vTaskSwitchContext ; Select the next task to execute.\r
        mov lr, pc\r
        BX R0\r
-\r
+SkipContextSwitch\r
        LDR     R14, =AT91C_BASE_PITC   ; Clear the PIT interrupt\r
        LDR     R0, [R14, #PITC_PIVR ]\r
 \r
index 5ed4f17239ed9b32b2a5c422998ae5afcf8b124c..14a5be2b8845acd802ba6d15b83f90c826190e7d 100644 (file)
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 #include "FreeRTOSConfig.h"\r
@@ -81,7 +81,7 @@
        EXPORT vTickISR\r
        EXPORT vPortYield\r
        EXPORT xPortStartScheduler\r
-       \r
+\r
        RSEG CODE\r
 \r
 /*\r
  */\r
 vTickISR:\r
        portSAVE_CONTEXT\r
-                               \r
+\r
        call    #xTaskIncrementTick\r
+       cmp.w   #0x0, R12\r
+    jeq                SkipContextSwitch\r
+       call    #vTaskSwitchContext\r
+SkipContextSwitch:\r
 \r
-       #if configUSE_PREEMPTION == 1\r
-               call    #vTaskSwitchContext\r
-       #endif\r
-               \r
        portRESTORE_CONTEXT\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -111,16 +111,16 @@ vTickISR:
 vPortYield:\r
 \r
        /* Mimic an interrupt by pushing the SR. */\r
-       push    SR                      \r
+       push    SR\r
 \r
        /* Now the SR is stacked we can disable interrupts. */\r
-       dint                    \r
-                               \r
+       dint\r
+\r
        /* Save the context of the current task. */\r
-       portSAVE_CONTEXT                        \r
+       portSAVE_CONTEXT\r
 \r
        /* Switch to the highest priority task that is ready to run. */\r
-       call    #vTaskSwitchContext             \r
+       call    #vTaskSwitchContext\r
 \r
        /* Restore the context of the new task. */\r
        portRESTORE_CONTEXT\r
@@ -140,14 +140,14 @@ xPortStartScheduler:
        /* Restore the context of the first task that is going to run. */\r
        portRESTORE_CONTEXT\r
 /*-----------------------------------------------------------*/\r
-               \r
+\r
 \r
        /* Install vTickISR as the timer A0 interrupt. */\r
        ASEG\r
        ORG 0xFFE0 + TIMERA0_VECTOR\r
-       \r
+\r
        _vTickISR_: DC16 vTickISR\r
-       \r
+\r
 \r
        END\r
-               \r
+\r
index fdd71049880d863133396846c78f007425b4920d..a49f8e5a27ca50dcf6d9e413304f2648afcd9a65 100644 (file)
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 #include "msp430.h"\r
@@ -95,7 +95,7 @@ portSAVE_CONTEXT macro
        mov_x   sp, 0( r12 )\r
        endm\r
 /*-----------------------------------------------------------*/\r
-               \r
+\r
 portRESTORE_CONTEXT macro\r
 \r
        mov_x   &pxCurrentTCB, r12\r
@@ -131,11 +131,10 @@ vPortTickISR:
        portSAVE_CONTEXT\r
 \r
        calla   #xTaskIncrementTick\r
-\r
-       #if configUSE_PREEMPTION == 1\r
-               calla   #vTaskSwitchContext\r
-       #endif\r
-\r
+       cmp.w   #0x0, R12\r
+    jeq     SkipContextSwitch\r
+    calla   #vTaskSwitchContext\r
+SkipContextSwitch:\r
        portRESTORE_CONTEXT\r
 /*-----------------------------------------------------------*/\r
 \r
index 6da1fb179cae63948cb551413200984e41f5b9d6..d1c02cb9c75e3e078e7baebbfe3d2085b0352c9b 100644 (file)
@@ -86,12 +86,12 @@ vPortStartFirstTask:
         RSEG CODE:CODE\r
 vPortTickISR:\r
 \r
-       portSAVE_CONTEXT                        ; Save the context of the current task.\r
-       call      xTaskIncrementTick    ; Call the timer tick function.\r
-#if configUSE_PREEMPTION == 1\r
-       call      vTaskSwitchContext    ; Call the scheduler to select the next task.\r
-#endif\r
-       portRESTORE_CONTEXT                     ; Restore the context of the next task to run.\r
+       portSAVE_CONTEXT                       ; Save the context of the current task.\r
+       call    xTaskIncrementTick     ; Call the timer tick function.\r
+       cmpw    ax, #0x00\r
+       skz\r
+       call    vTaskSwitchContext     ; Call the scheduler to select the next task.\r
+       portRESTORE_CONTEXT                    ; Restore the context of the next task to run.\r
        reti\r
 \r
 \r
index afaf561896c42ff9f5465956bc455189f9c45a1b..d326508c1c8e154619b6bb956a6a1b7259a39a22 100644 (file)
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 \r
@@ -97,6 +97,12 @@ FreeRTOS.org V4.3.0. */
        #define configKERNEL_INTERRUPT_PRIORITY 1\r
 #endif\r
 \r
+/* Use _T1Interrupt as the interrupt handler name if the application writer has\r
+not provided their own. */\r
+#ifndef configTICK_INTERRUPT_HANDLER\r
+       #define configTICK_INTERRUPT_HANDLER _T1Interrupt\r
+#endif /* configTICK_INTERRUPT_HANDLER */\r
+\r
 /* The program counter is only 23 bits. */\r
 #define portUNUSED_PR_BITS     0x7f\r
 \r
@@ -107,7 +113,7 @@ unsigned portBASE_TYPE uxCriticalNesting = 0xef;
        #error If configKERNEL_INTERRUPT_PRIORITY is not 1 then the #32 in the following macros needs changing to equal the portINTERRUPT_BITS value, which is ( configKERNEL_INTERRUPT_PRIORITY << 5 )\r
 #endif\r
 \r
-#ifdef MPLAB_PIC24_PORT\r
+#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )\r
 \r
     #ifdef __HAS_EDS__\r
                #define portRESTORE_CONTEXT()                                                                                                                                                                           \\r
@@ -151,7 +157,7 @@ unsigned portBASE_TYPE uxCriticalNesting = 0xef;
                #endif /* __HAS_EDS__ */\r
 #endif /* MPLAB_PIC24_PORT */\r
 \r
-#ifdef MPLAB_DSPIC_PORT\r
+#if defined( __dsPIC30F__ ) || defined ( __dsPIC33E__ ) || defined( __dsPIC33F__ )\r
 \r
        #define portRESTORE_CONTEXT()                                                                                                                                                                           \\r
                asm volatile(   "MOV    _pxCurrentTCB, W0               \n"     /* Restore the stack pointer for the task. */                           \\r
@@ -185,10 +191,14 @@ unsigned portBASE_TYPE uxCriticalNesting = 0xef;
 \r
 #endif /* MPLAB_DSPIC_PORT */\r
 \r
+#ifndef portRESTORE_CONTEXT\r
+       #error Unrecognised device selected\r
+#endif\r
+\r
 /*\r
  * Setup the timer used to generate the tick interrupt.\r
  */\r
-static void prvSetupTimerInterrupt( void );\r
+void vApplicationSetupTickTimerInterrupt( void );\r
 \r
 /*\r
  * See header file for description.\r
@@ -196,7 +206,7 @@ static void prvSetupTimerInterrupt( void );
 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 {\r
 unsigned short usCode;\r
-portBASE_TYPE i;\r
+unsigned portBASE_TYPE i;\r
 \r
 const portSTACK_TYPE xInitialStack[] =\r
 {\r
@@ -284,7 +294,7 @@ const portSTACK_TYPE xInitialStack[] =
 portBASE_TYPE xPortStartScheduler( void )\r
 {\r
        /* Setup a timer for the tick ISR. */\r
-       prvSetupTimerInterrupt();\r
+       vApplicationSetupTickTimerInterrupt();\r
 \r
        /* Restore the context of the first task to run. */\r
        portRESTORE_CONTEXT();\r
@@ -308,7 +318,7 @@ void vPortEndScheduler( void )
 /*\r
  * Setup a timer for a regular tick.\r
  */\r
-static void prvSetupTimerInterrupt( void )\r
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )\r
 {\r
 const unsigned long ulCompareMatch = ( ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;\r
 \r
@@ -353,7 +363,7 @@ void vPortExitCritical( void )
 }\r
 /*-----------------------------------------------------------*/\r
 \r
-void __attribute__((__interrupt__, auto_psv)) _T1Interrupt( void )\r
+void __attribute__((__interrupt__, auto_psv)) configTICK_INTERRUPT_HANDLER( void )\r
 {\r
        /* Clear the timer interrupt. */\r
        IFS0bits.T1IF = 0;\r
index 95995e36026b75ef4625a180c7e75d3459815ea9..dd832a0c04087d1e2cf1c7659dbf7f8d7f758013 100644 (file)
@@ -130,11 +130,13 @@ vPreemptiveTick
        LDR R0, =xTaskIncrementTick                     ; Increment the tick count.  \r
        MOV LR, PC                                                      ; This may make a delayed task ready\r
        BX R0                                                           ; to run.\r
-       \r
+\r
+       CMP R0, #0\r
+       BEQ SkipContextSwitch\r
        LDR R0, =vTaskSwitchContext                     ; Find the highest priority task that \r
        MOV LR, PC                                                      ; is ready to run.\r
        BX R0\r
-       \r
+SkipContextSwitch\r
        MOV R0, #T0MATCHBIT                                     ; Clear the timer event\r
        LDR R1, =T0IR\r
        STR R0, [R1] \r
index 85c9421ac5ebfce6e734990865e3cd9778163dbc..2a16fd976a6384a8949483b4e7d3c8fbe0705a8b 100644 (file)
@@ -90,11 +90,10 @@ _vTickISR:
                portSAVE_CONTEXT\r
                                \r
                call    #_xTaskIncrementTick\r
-\r
-               #if configUSE_PREEMPTION == 1\r
-                       call    #_vTaskSwitchContext\r
-               #endif\r
-               \r
+               cmp.w   #0x00, r15\r
+                jeq     _SkipContextSwitch\r
+               call    #_vTaskSwitchContext\r
+_SkipContextSwitch:            \r
                portRESTORE_CONTEXT\r
 /*-----------------------------------------------------------*/\r
 \r