-\r
-set RCC_CR [expr $RCC_BASE + 0x00]\r
-set RCC_CFGR [expr $RCC_BASE + 0x04]\r
-set RCC_CIR [expr $RCC_BASE + 0x08]\r
-set RCC_APB2RSTR [expr $RCC_BASE + 0x0c]\r
-set RCC_APB1RSTR [expr $RCC_BASE + 0x10]\r
-set RCC_AHBENR [expr $RCC_BASE + 0x14]\r
-set RCC_APB2ENR [expr $RCC_BASE + 0x18]\r
-set RCC_APB1ENR [expr $RCC_BASE + 0x1c]\r
-set RCC_BDCR [expr $RCC_BASE + 0x20]\r
-set RCC_CSR [expr $RCC_BASE + 0x24]\r
-\r
-\r
-proc show_RCC_CR { } {\r
- if [ catch { set val [show_mmr32_reg RCC_CR] } msg ] {\r
- error $msg\r
- }\r
-\r
- show_mmr_bitfield 0 0 $val HSI { OFF ON } \r
- show_mmr_bitfield 1 1 $val HSIRDY { NOTRDY RDY }\r
- show_mmr_bitfield 7 3 $val HSITRIM { _NUMBER_ }\r
- show_mmr_bitfield 15 8 $val HSICAL { _NUMBER_ }\r
- show_mmr_bitfield 16 16 $val HSEON { OFF ON }\r
- show_mmr_bitfield 17 17 $val HSERDY { NOTRDY RDY }\r
- show_mmr_bitfield 18 18 $val HSEBYP { NOTBYPASSED BYPASSED }\r
- show_mmr_bitfield 19 19 $val CSSON { OFF ON }\r
- show_mmr_bitfield 24 24 $val PLLON { OFF ON }\r
- show_mmr_bitfield 25 25 $val PLLRDY { NOTRDY RDY }\r
-} \r
- \r
-proc show_RCC_CFGR { } {\r
- if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] {\r
- error $msg\r
- }\r
-\r
-\r
- show_mmr_bitfield 1 0 $val SW { HSI HSE PLL ILLEGAL }\r
- show_mmr_bitfield 3 2 $val SWS { HSI HSE PLL ILLEGAL }\r
- show_mmr_bitfield 7 4 $val HPRE { sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_2 sysclk_div_4 sysclk_div_8 sysclk_div_16 sysclk_div_64 sysclk_div_128 sysclk_div_256 sysclk_div_512 }\r
- show_mmr_bitfield 10 8 $val PPRE1 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }\r
- show_mmr_bitfield 13 11 $val PPRE2 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }\r
- show_mmr_bitfield 15 14 $val ADCPRE { pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div2 pclk2_div4 pclk2_div8 pclk2_div16 }\r
- show_mmr_bitfield 16 16 $val PLLSRC { HSI_div_2 HSE }\r
- show_mmr_bitfield 17 17 $val PLLXTPRE { hse_div1 hse_div2 }\r
- show_mmr_bitfield 21 18 $val PLLMUL { x2 x3 x4 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16 }\r
- show_mmr_bitfield 22 22 $val USBPRE { div1 div1_5 }\r
- show_mmr_bitfield 26 24 $val MCO { none none none none SysClk HSI HSE PLL_div2 }\r
-}\r
-\r
- \r
-proc show_RCC_CIR { } {\r
- if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] {\r
- error $msg\r
- }\r
- \r
-}\r
-\r
-proc show_RCC_APB2RSTR { } {\r
- if [ catch { set val [ show_mmr32_reg RCC_APB2RSTR] } msg ] {\r
- error $msg\r
- }\r
- for { set x 0 } { $x < 32 } { incr x } {\r
- set bits($x) xxx\r
- }\r
- set bits(15) adc3\r
- set bits(14) usart1\r
- set bits(13) tim8\r
- set bits(12) spi1\r
- set bits(11) tim1\r
- set bits(10) adc2\r
- set bits(9) adc1\r
- set bits(8) iopg\r
- set bits(7) iopf\r
- set bits(6) iope\r
- set bits(5) iopd\r
- set bits(4) iopc\r
- set bits(3) iopb\r
- set bits(2) iopa\r
- set bits(1) xxx\r
- set bits(0) afio\r
- show_mmr32_bits bits $val\r
-}\r
-\r
-proc show_RCC_APB1RSTR { } {\r
- if [ catch { set val [ show_mmr32_reg RCC_APB1RSTR] } msg ] {\r
- error $msg\r
- }\r
- set bits(31) xxx\r
- set bits(30) xxx\r
- set bits(29) dac\r
- set bits(28) pwr\r
- set bits(27) bkp\r
- set bits(26) xxx\r
- set bits(25) can\r
- set bits(24) xxx\r
- set bits(23) usb\r
- set bits(22) i2c2\r
- set bits(21) i2c1\r
- set bits(20) uart5\r
- set bits(19) uart4\r
- set bits(18) uart3\r
- set bits(17) uart2\r
- set bits(16) xxx\r
- set bits(15) spi3\r
- set bits(14) spi2\r
- set bits(13) xxx\r
- set bits(12) xxx\r
- set bits(11) wwdg\r
- set bits(10) xxx \r
- set bits(9) xxx\r
- set bits(8) xxx\r
- set bits(7) xxx\r
- set bits(6) xxx\r
- set bits(5) tim7\r
- set bits(4) tim6\r
- set bits(3) tim5\r
- set bits(2) tim4\r
- set bits(1) tim3\r
- set bits(0) tim2\r
- show_mmr32_bits bits $val\r
- \r
-}\r
-\r
-proc show_RCC_AHBENR { } {\r
- if [ catch { set val [ show_mmr32_reg RCC_AHBENR ] } msg ] {\r
- error $msg\r
- }\r
- set bits(31) xxx\r
- set bits(30) xxx\r
- set bits(29) xxx\r
- set bits(28) xxx\r
- set bits(27) xxx\r
- set bits(26) xxx\r
- set bits(25) xxx\r
- set bits(24) xxx\r
- set bits(23) xxx\r
- set bits(22) xxx\r
- set bits(21) xxx\r
- set bits(20) xxx\r
- set bits(19) xxx\r
- set bits(18) xxx\r
- set bits(17) xxx\r
- set bits(16) xxx\r
- set bits(15) xxx \r
- set bits(14) xxx\r
- set bits(13) xxx\r
- set bits(12) xxx\r
- set bits(11) xxx\r
- set bits(10) sdio\r
- set bits(9) xxx\r
- set bits(8) fsmc\r
- set bits(7) xxx\r
- set bits(6) crce\r
- set bits(5) xxx\r
- set bits(4) flitf\r
- set bits(3) xxx\r
- set bits(2) sram\r
- set bits(1) dma2\r
- set bits(0) dma1\r
- show_mmr32_bits bits $val\r
-}\r
-\r
-proc show_RCC_APB2ENR { } {\r
- if [ catch { set val [ show_mmr32_reg RCC_APB2ENR ] } msg ] {\r
- error $msg\r
- }\r
- set bits(31) xxx\r
- set bits(30) xxx\r
- set bits(29) xxx\r
- set bits(28) xxx\r
- set bits(27) xxx\r
- set bits(26) xxx\r
- set bits(25) xxx\r
- set bits(24) xxx\r
- set bits(23) xxx\r
- set bits(22) xxx\r
- set bits(21) xxx\r
- set bits(20) xxx\r
- set bits(19) xxx\r
- set bits(18) xxx\r
- set bits(17) xxx\r
- set bits(16) xxx\r
- set bits(15) adc3 \r
- set bits(14) usart1\r
- set bits(13) tim8\r
- set bits(12) spi1\r
- set bits(11) tim1\r
- set bits(10) adc2\r
- set bits(9) adc1\r
- set bits(8) iopg\r
- set bits(7) iopf\r
- set bits(6) iope\r
- set bits(5) iopd\r
- set bits(4) iopc\r
- set bits(3) iopb\r
- set bits(2) iopa\r
- set bits(1) xxx\r
- set bits(0) afio\r
- show_mmr32_bits bits $val\r
-\r
-}\r
-\r
-proc show_RCC_APB1ENR { } {\r
- if [ catch { set val [ show_mmr32_reg RCC_APB1ENR ] } msg ] {\r
- error $msg\r
- }\r
- set bits(31) xxx\r
- set bits(30) xxx\r
- set bits(29) dac\r
- set bits(28) pwr\r
- set bits(27) bkp\r
- set bits(26) xxx\r
- set bits(25) can\r
- set bits(24) xxx\r
- set bits(23) usb\r
- set bits(22) i2c2\r
- set bits(21) i2c1\r
- set bits(20) usart5\r
- set bits(19) usart4\r
- set bits(18) usart3\r
- set bits(17) usart2\r
- set bits(16) xxx\r
- set bits(15) spi3\r
- set bits(14) spi2\r
- set bits(13) xxx\r
- set bits(12) xxx\r
- set bits(11) wwdg\r
- set bits(10) xxx\r
- set bits(9) xxx\r
- set bits(8) xxx\r
- set bits(7) xxx\r
- set bits(6) xxx\r
- set bits(5) tim7\r
- set bits(4) tim6\r
- set bits(3) tim5\r
- set bits(2) tim4\r
- set bits(1) tim3\r
- set bits(0) tim2\r
- show_mmr32_bits bits $val\r
-}\r
-\r
-proc show_RCC_BDCR { } {\r
- if [ catch { set val [ show_mmr32_reg RCC_BDCR ] } msg ] {\r
- error $msg\r
- }\r
- for { set x 0 } { $x < 32 } { incr x } {\r
- set bits($x) xxx\r
- }\r
- set bits(0) lseon\r
- set bits(1) lserdy\r
- set bits(2) lsebyp\r
- set bits(8) rtcsel0\r
- set bits(9) rtcsel1\r
- set bits(15) rtcen\r
- set bits(16) bdrst\r
- show_mmr32_bits bits $val\r
-}\r
-\r
-proc show_RCC_CSR { } {\r
- if [ catch { set val [ show_mmr32_reg RCC_CSR ] } msg ] {\r
- error $msg\r
- }\r
- for { set x 0 } { $x < 32 } { incr x } {\r
- set bits($x) xxx\r
- }\r
- set bits(0) lsion\r
- set bits(1) lsirdy\r
- set bits(24) rmvf\r
- set bits(26) pin\r
- set bits(27) por\r
- set bits(28) sft\r
- set bits(29) iwdg\r
- set bits(30) wwdg\r
- set bits(31) lpwr\r
- show_mmr32_bits bits $val\r
-}\r
-\r
-proc show_RCC { } {\r
-\r
- show_RCC_CR\r
- show_RCC_CFGR\r
- show_RCC_CIR\r
- show_RCC_APB2RSTR\r
- show_RCC_APB1RSTR\r
- show_RCC_AHBENR\r
- show_RCC_APB2ENR\r
- show_RCC_APB1ENR\r
- show_RCC_BDCR\r
- show_RCC_CSR\r
-}\r
+
+set RCC_CR [expr $RCC_BASE + 0x00]
+set RCC_CFGR [expr $RCC_BASE + 0x04]
+set RCC_CIR [expr $RCC_BASE + 0x08]
+set RCC_APB2RSTR [expr $RCC_BASE + 0x0c]
+set RCC_APB1RSTR [expr $RCC_BASE + 0x10]
+set RCC_AHBENR [expr $RCC_BASE + 0x14]
+set RCC_APB2ENR [expr $RCC_BASE + 0x18]
+set RCC_APB1ENR [expr $RCC_BASE + 0x1c]
+set RCC_BDCR [expr $RCC_BASE + 0x20]
+set RCC_CSR [expr $RCC_BASE + 0x24]
+
+
+proc show_RCC_CR { } {
+ if [ catch { set val [show_mmr32_reg RCC_CR] } msg ] {
+ error $msg
+ }
+
+ show_mmr_bitfield 0 0 $val HSI { OFF ON }
+ show_mmr_bitfield 1 1 $val HSIRDY { NOTRDY RDY }
+ show_mmr_bitfield 7 3 $val HSITRIM { _NUMBER_ }
+ show_mmr_bitfield 15 8 $val HSICAL { _NUMBER_ }
+ show_mmr_bitfield 16 16 $val HSEON { OFF ON }
+ show_mmr_bitfield 17 17 $val HSERDY { NOTRDY RDY }
+ show_mmr_bitfield 18 18 $val HSEBYP { NOTBYPASSED BYPASSED }
+ show_mmr_bitfield 19 19 $val CSSON { OFF ON }
+ show_mmr_bitfield 24 24 $val PLLON { OFF ON }
+ show_mmr_bitfield 25 25 $val PLLRDY { NOTRDY RDY }
+}
+
+proc show_RCC_CFGR { } {
+ if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] {
+ error $msg
+ }
+
+
+ show_mmr_bitfield 1 0 $val SW { HSI HSE PLL ILLEGAL }
+ show_mmr_bitfield 3 2 $val SWS { HSI HSE PLL ILLEGAL }
+ show_mmr_bitfield 7 4 $val HPRE { sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_2 sysclk_div_4 sysclk_div_8 sysclk_div_16 sysclk_div_64 sysclk_div_128 sysclk_div_256 sysclk_div_512 }
+ show_mmr_bitfield 10 8 $val PPRE1 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }
+ show_mmr_bitfield 13 11 $val PPRE2 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }
+ show_mmr_bitfield 15 14 $val ADCPRE { pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div2 pclk2_div4 pclk2_div8 pclk2_div16 }
+ show_mmr_bitfield 16 16 $val PLLSRC { HSI_div_2 HSE }
+ show_mmr_bitfield 17 17 $val PLLXTPRE { hse_div1 hse_div2 }
+ show_mmr_bitfield 21 18 $val PLLMUL { x2 x3 x4 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16 }
+ show_mmr_bitfield 22 22 $val USBPRE { div1 div1_5 }
+ show_mmr_bitfield 26 24 $val MCO { none none none none SysClk HSI HSE PLL_div2 }
+}
+
+
+proc show_RCC_CIR { } {
+ if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] {
+ error $msg
+ }
+
+}
+
+proc show_RCC_APB2RSTR { } {
+ if [ catch { set val [ show_mmr32_reg RCC_APB2RSTR] } msg ] {
+ error $msg
+ }
+ for { set x 0 } { $x < 32 } { incr x } {
+ set bits($x) xxx
+ }
+ set bits(15) adc3
+ set bits(14) usart1
+ set bits(13) tim8
+ set bits(12) spi1
+ set bits(11) tim1
+ set bits(10) adc2
+ set bits(9) adc1
+ set bits(8) iopg
+ set bits(7) iopf
+ set bits(6) iope
+ set bits(5) iopd
+ set bits(4) iopc
+ set bits(3) iopb
+ set bits(2) iopa
+ set bits(1) xxx
+ set bits(0) afio
+ show_mmr32_bits bits $val
+}
+
+proc show_RCC_APB1RSTR { } {
+ if [ catch { set val [ show_mmr32_reg RCC_APB1RSTR] } msg ] {
+ error $msg
+ }
+ set bits(31) xxx
+ set bits(30) xxx
+ set bits(29) dac
+ set bits(28) pwr
+ set bits(27) bkp
+ set bits(26) xxx
+ set bits(25) can
+ set bits(24) xxx
+ set bits(23) usb
+ set bits(22) i2c2
+ set bits(21) i2c1
+ set bits(20) uart5
+ set bits(19) uart4
+ set bits(18) uart3
+ set bits(17) uart2
+ set bits(16) xxx
+ set bits(15) spi3
+ set bits(14) spi2
+ set bits(13) xxx
+ set bits(12) xxx
+ set bits(11) wwdg
+ set bits(10) xxx
+ set bits(9) xxx
+ set bits(8) xxx
+ set bits(7) xxx
+ set bits(6) xxx
+ set bits(5) tim7
+ set bits(4) tim6
+ set bits(3) tim5
+ set bits(2) tim4
+ set bits(1) tim3
+ set bits(0) tim2
+ show_mmr32_bits bits $val
+
+}
+
+proc show_RCC_AHBENR { } {
+ if [ catch { set val [ show_mmr32_reg RCC_AHBENR ] } msg ] {
+ error $msg
+ }
+ set bits(31) xxx
+ set bits(30) xxx
+ set bits(29) xxx
+ set bits(28) xxx
+ set bits(27) xxx
+ set bits(26) xxx
+ set bits(25) xxx
+ set bits(24) xxx
+ set bits(23) xxx
+ set bits(22) xxx
+ set bits(21) xxx
+ set bits(20) xxx
+ set bits(19) xxx
+ set bits(18) xxx
+ set bits(17) xxx
+ set bits(16) xxx
+ set bits(15) xxx
+ set bits(14) xxx
+ set bits(13) xxx
+ set bits(12) xxx
+ set bits(11) xxx
+ set bits(10) sdio
+ set bits(9) xxx
+ set bits(8) fsmc
+ set bits(7) xxx
+ set bits(6) crce
+ set bits(5) xxx
+ set bits(4) flitf
+ set bits(3) xxx
+ set bits(2) sram
+ set bits(1) dma2
+ set bits(0) dma1
+ show_mmr32_bits bits $val
+}
+
+proc show_RCC_APB2ENR { } {
+ if [ catch { set val [ show_mmr32_reg RCC_APB2ENR ] } msg ] {
+ error $msg
+ }
+ set bits(31) xxx
+ set bits(30) xxx
+ set bits(29) xxx
+ set bits(28) xxx
+ set bits(27) xxx
+ set bits(26) xxx
+ set bits(25) xxx
+ set bits(24) xxx
+ set bits(23) xxx
+ set bits(22) xxx
+ set bits(21) xxx
+ set bits(20) xxx
+ set bits(19) xxx
+ set bits(18) xxx
+ set bits(17) xxx
+ set bits(16) xxx
+ set bits(15) adc3
+ set bits(14) usart1
+ set bits(13) tim8
+ set bits(12) spi1
+ set bits(11) tim1
+ set bits(10) adc2
+ set bits(9) adc1
+ set bits(8) iopg
+ set bits(7) iopf
+ set bits(6) iope
+ set bits(5) iopd
+ set bits(4) iopc
+ set bits(3) iopb
+ set bits(2) iopa
+ set bits(1) xxx
+ set bits(0) afio
+ show_mmr32_bits bits $val
+
+}
+
+proc show_RCC_APB1ENR { } {
+ if [ catch { set val [ show_mmr32_reg RCC_APB1ENR ] } msg ] {
+ error $msg
+ }
+ set bits(31) xxx
+ set bits(30) xxx
+ set bits(29) dac
+ set bits(28) pwr
+ set bits(27) bkp
+ set bits(26) xxx
+ set bits(25) can
+ set bits(24) xxx
+ set bits(23) usb
+ set bits(22) i2c2
+ set bits(21) i2c1
+ set bits(20) usart5
+ set bits(19) usart4
+ set bits(18) usart3
+ set bits(17) usart2
+ set bits(16) xxx
+ set bits(15) spi3
+ set bits(14) spi2
+ set bits(13) xxx
+ set bits(12) xxx
+ set bits(11) wwdg
+ set bits(10) xxx
+ set bits(9) xxx
+ set bits(8) xxx
+ set bits(7) xxx
+ set bits(6) xxx
+ set bits(5) tim7
+ set bits(4) tim6
+ set bits(3) tim5
+ set bits(2) tim4
+ set bits(1) tim3
+ set bits(0) tim2
+ show_mmr32_bits bits $val
+}
+
+proc show_RCC_BDCR { } {
+ if [ catch { set val [ show_mmr32_reg RCC_BDCR ] } msg ] {
+ error $msg
+ }
+ for { set x 0 } { $x < 32 } { incr x } {
+ set bits($x) xxx
+ }
+ set bits(0) lseon
+ set bits(1) lserdy
+ set bits(2) lsebyp
+ set bits(8) rtcsel0
+ set bits(9) rtcsel1
+ set bits(15) rtcen
+ set bits(16) bdrst
+ show_mmr32_bits bits $val
+}
+
+proc show_RCC_CSR { } {
+ if [ catch { set val [ show_mmr32_reg RCC_CSR ] } msg ] {
+ error $msg
+ }
+ for { set x 0 } { $x < 32 } { incr x } {
+ set bits($x) xxx
+ }
+ set bits(0) lsion
+ set bits(1) lsirdy
+ set bits(24) rmvf
+ set bits(26) pin
+ set bits(27) por
+ set bits(28) sft
+ set bits(29) iwdg
+ set bits(30) wwdg
+ set bits(31) lpwr
+ show_mmr32_bits bits $val
+}
+
+proc show_RCC { } {
+
+ show_RCC_CR
+ show_RCC_CFGR
+ show_RCC_CIR
+ show_RCC_APB2RSTR
+ show_RCC_APB1RSTR
+ show_RCC_AHBENR
+ show_RCC_APB2ENR
+ show_RCC_APB1ENR
+ show_RCC_BDCR
+ show_RCC_CSR
+}
-# /* Peripheral and SRAM base address in the alias region */\r
-set PERIPH_BB_BASE 0x42000000\r
-set SRAM_BB_BASE 0x22000000\r
-\r
-# /*Peripheral and SRAM base address in the bit-band region */\r
-set SRAM_BASE 0x20000000\r
-set PERIPH_BASE 0x40000000\r
-\r
-# /*FSMC registers base address */\r
-set FSMC_R_BASE 0xA0000000\r
-\r
-# /*Peripheral memory map */\r
-set APB1PERIPH_BASE [set PERIPH_BASE]\r
-set APB2PERIPH_BASE [expr $PERIPH_BASE + 0x10000]\r
-set AHBPERIPH_BASE [expr $PERIPH_BASE + 0x20000]\r
-\r
-set TIM2_BASE [expr $APB1PERIPH_BASE + 0x0000]\r
-set TIM3_BASE [expr $APB1PERIPH_BASE + 0x0400]\r
-set TIM4_BASE [expr $APB1PERIPH_BASE + 0x0800]\r
-set TIM5_BASE [expr $APB1PERIPH_BASE + 0x0C00]\r
-set TIM6_BASE [expr $APB1PERIPH_BASE + 0x1000]\r
-set TIM7_BASE [expr $APB1PERIPH_BASE + 0x1400]\r
-set RTC_BASE [expr $APB1PERIPH_BASE + 0x2800]\r
-set WWDG_BASE [expr $APB1PERIPH_BASE + 0x2C00]\r
-set IWDG_BASE [expr $APB1PERIPH_BASE + 0x3000]\r
-set SPI2_BASE [expr $APB1PERIPH_BASE + 0x3800]\r
-set SPI3_BASE [expr $APB1PERIPH_BASE + 0x3C00]\r
-set USART2_BASE [expr $APB1PERIPH_BASE + 0x4400]\r
-set USART3_BASE [expr $APB1PERIPH_BASE + 0x4800]\r
-set UART4_BASE [expr $APB1PERIPH_BASE + 0x4C00]\r
-set UART5_BASE [expr $APB1PERIPH_BASE + 0x5000]\r
-set I2C1_BASE [expr $APB1PERIPH_BASE + 0x5400]\r
-set I2C2_BASE [expr $APB1PERIPH_BASE + 0x5800]\r
-set CAN_BASE [expr $APB1PERIPH_BASE + 0x6400]\r
-set BKP_BASE [expr $APB1PERIPH_BASE + 0x6C00]\r
-set PWR_BASE [expr $APB1PERIPH_BASE + 0x7000]\r
-set DAC_BASE [expr $APB1PERIPH_BASE + 0x7400]\r
-\r
-set AFIO_BASE [expr $APB2PERIPH_BASE + 0x0000]\r
-set EXTI_BASE [expr $APB2PERIPH_BASE + 0x0400]\r
-set GPIOA_BASE [expr $APB2PERIPH_BASE + 0x0800]\r
-set GPIOB_BASE [expr $APB2PERIPH_BASE + 0x0C00]\r
-set GPIOC_BASE [expr $APB2PERIPH_BASE + 0x1000]\r
-set GPIOD_BASE [expr $APB2PERIPH_BASE + 0x1400]\r
-set GPIOE_BASE [expr $APB2PERIPH_BASE + 0x1800]\r
-set GPIOF_BASE [expr $APB2PERIPH_BASE + 0x1C00]\r
-set GPIOG_BASE [expr $APB2PERIPH_BASE + 0x2000]\r
-set ADC1_BASE [expr $APB2PERIPH_BASE + 0x2400]\r
-set ADC2_BASE [expr $APB2PERIPH_BASE + 0x2800]\r
-set TIM1_BASE [expr $APB2PERIPH_BASE + 0x2C00]\r
-set SPI1_BASE [expr $APB2PERIPH_BASE + 0x3000]\r
-set TIM8_BASE [expr $APB2PERIPH_BASE + 0x3400]\r
-set USART1_BASE [expr $APB2PERIPH_BASE + 0x3800]\r
-set ADC3_BASE [expr $APB2PERIPH_BASE + 0x3C00]\r
-\r
-set SDIO_BASE [expr $PERIPH_BASE + 0x18000]\r
-\r
-set DMA1_BASE [expr $AHBPERIPH_BASE + 0x0000]\r
-set DMA1_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0008]\r
-set DMA1_Channel2_BASE [expr $AHBPERIPH_BASE + 0x001C]\r
-set DMA1_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0030]\r
-set DMA1_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0044]\r
-set DMA1_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0058]\r
-set DMA1_Channel6_BASE [expr $AHBPERIPH_BASE + 0x006C]\r
-set DMA1_Channel7_BASE [expr $AHBPERIPH_BASE + 0x0080]\r
-set DMA2_BASE [expr $AHBPERIPH_BASE + 0x0400]\r
-set DMA2_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0408]\r
-set DMA2_Channel2_BASE [expr $AHBPERIPH_BASE + 0x041C]\r
-set DMA2_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0430]\r
-set DMA2_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0444]\r
-set DMA2_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0458]\r
-set RCC_BASE [expr $AHBPERIPH_BASE + 0x1000]\r
-set CRC_BASE [expr $AHBPERIPH_BASE + 0x3000]\r
-\r
-# /*Flash registers base address */\r
-set FLASH_R_BASE [expr $AHBPERIPH_BASE + 0x2000]\r
-# /*Flash Option Bytes base address */\r
-set OB_BASE 0x1FFFF800\r
-\r
-# /*FSMC Bankx registers base address */\r
-set FSMC_Bank1_R_BASE [expr $FSMC_R_BASE + 0x0000]\r
-set FSMC_Bank1E_R_BASE [expr $FSMC_R_BASE + 0x0104]\r
-set FSMC_Bank2_R_BASE [expr $FSMC_R_BASE + 0x0060]\r
-set FSMC_Bank3_R_BASE [expr $FSMC_R_BASE + 0x0080]\r
-set FSMC_Bank4_R_BASE [expr $FSMC_R_BASE + 0x00A0]\r
-\r
-# /*Debug MCU registers base address */\r
-set DBGMCU_BASE 0xE0042000\r
-\r
-# /*System Control Space memory map */\r
-set SCS_BASE 0xE000E000\r
-\r
-set SysTick_BASE [expr $SCS_BASE + 0x0010]\r
-set NVIC_BASE [expr $SCS_BASE + 0x0100]\r
-set SCB_BASE [expr $SCS_BASE + 0x0D00]\r
+# /* Peripheral and SRAM base address in the alias region */
+set PERIPH_BB_BASE 0x42000000
+set SRAM_BB_BASE 0x22000000
+
+# /*Peripheral and SRAM base address in the bit-band region */
+set SRAM_BASE 0x20000000
+set PERIPH_BASE 0x40000000
+
+# /*FSMC registers base address */
+set FSMC_R_BASE 0xA0000000
+
+# /*Peripheral memory map */
+set APB1PERIPH_BASE [set PERIPH_BASE]
+set APB2PERIPH_BASE [expr $PERIPH_BASE + 0x10000]
+set AHBPERIPH_BASE [expr $PERIPH_BASE + 0x20000]
+
+set TIM2_BASE [expr $APB1PERIPH_BASE + 0x0000]
+set TIM3_BASE [expr $APB1PERIPH_BASE + 0x0400]
+set TIM4_BASE [expr $APB1PERIPH_BASE + 0x0800]
+set TIM5_BASE [expr $APB1PERIPH_BASE + 0x0C00]
+set TIM6_BASE [expr $APB1PERIPH_BASE + 0x1000]
+set TIM7_BASE [expr $APB1PERIPH_BASE + 0x1400]
+set RTC_BASE [expr $APB1PERIPH_BASE + 0x2800]
+set WWDG_BASE [expr $APB1PERIPH_BASE + 0x2C00]
+set IWDG_BASE [expr $APB1PERIPH_BASE + 0x3000]
+set SPI2_BASE [expr $APB1PERIPH_BASE + 0x3800]
+set SPI3_BASE [expr $APB1PERIPH_BASE + 0x3C00]
+set USART2_BASE [expr $APB1PERIPH_BASE + 0x4400]
+set USART3_BASE [expr $APB1PERIPH_BASE + 0x4800]
+set UART4_BASE [expr $APB1PERIPH_BASE + 0x4C00]
+set UART5_BASE [expr $APB1PERIPH_BASE + 0x5000]
+set I2C1_BASE [expr $APB1PERIPH_BASE + 0x5400]
+set I2C2_BASE [expr $APB1PERIPH_BASE + 0x5800]
+set CAN_BASE [expr $APB1PERIPH_BASE + 0x6400]
+set BKP_BASE [expr $APB1PERIPH_BASE + 0x6C00]
+set PWR_BASE [expr $APB1PERIPH_BASE + 0x7000]
+set DAC_BASE [expr $APB1PERIPH_BASE + 0x7400]
+
+set AFIO_BASE [expr $APB2PERIPH_BASE + 0x0000]
+set EXTI_BASE [expr $APB2PERIPH_BASE + 0x0400]
+set GPIOA_BASE [expr $APB2PERIPH_BASE + 0x0800]
+set GPIOB_BASE [expr $APB2PERIPH_BASE + 0x0C00]
+set GPIOC_BASE [expr $APB2PERIPH_BASE + 0x1000]
+set GPIOD_BASE [expr $APB2PERIPH_BASE + 0x1400]
+set GPIOE_BASE [expr $APB2PERIPH_BASE + 0x1800]
+set GPIOF_BASE [expr $APB2PERIPH_BASE + 0x1C00]
+set GPIOG_BASE [expr $APB2PERIPH_BASE + 0x2000]
+set ADC1_BASE [expr $APB2PERIPH_BASE + 0x2400]
+set ADC2_BASE [expr $APB2PERIPH_BASE + 0x2800]
+set TIM1_BASE [expr $APB2PERIPH_BASE + 0x2C00]
+set SPI1_BASE [expr $APB2PERIPH_BASE + 0x3000]
+set TIM8_BASE [expr $APB2PERIPH_BASE + 0x3400]
+set USART1_BASE [expr $APB2PERIPH_BASE + 0x3800]
+set ADC3_BASE [expr $APB2PERIPH_BASE + 0x3C00]
+
+set SDIO_BASE [expr $PERIPH_BASE + 0x18000]
+
+set DMA1_BASE [expr $AHBPERIPH_BASE + 0x0000]
+set DMA1_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0008]
+set DMA1_Channel2_BASE [expr $AHBPERIPH_BASE + 0x001C]
+set DMA1_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0030]
+set DMA1_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0044]
+set DMA1_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0058]
+set DMA1_Channel6_BASE [expr $AHBPERIPH_BASE + 0x006C]
+set DMA1_Channel7_BASE [expr $AHBPERIPH_BASE + 0x0080]
+set DMA2_BASE [expr $AHBPERIPH_BASE + 0x0400]
+set DMA2_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0408]
+set DMA2_Channel2_BASE [expr $AHBPERIPH_BASE + 0x041C]
+set DMA2_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0430]
+set DMA2_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0444]
+set DMA2_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0458]
+set RCC_BASE [expr $AHBPERIPH_BASE + 0x1000]
+set CRC_BASE [expr $AHBPERIPH_BASE + 0x3000]
+
+# /*Flash registers base address */
+set FLASH_R_BASE [expr $AHBPERIPH_BASE + 0x2000]
+# /*Flash Option Bytes base address */
+set OB_BASE 0x1FFFF800
+
+# /*FSMC Bankx registers base address */
+set FSMC_Bank1_R_BASE [expr $FSMC_R_BASE + 0x0000]
+set FSMC_Bank1E_R_BASE [expr $FSMC_R_BASE + 0x0104]
+set FSMC_Bank2_R_BASE [expr $FSMC_R_BASE + 0x0060]
+set FSMC_Bank3_R_BASE [expr $FSMC_R_BASE + 0x0080]
+set FSMC_Bank4_R_BASE [expr $FSMC_R_BASE + 0x00A0]
+
+# /*Debug MCU registers base address */
+set DBGMCU_BASE 0xE0042000
+
+# /*System Control Space memory map */
+set SCS_BASE 0xE000E000
+
+set SysTick_BASE [expr $SCS_BASE + 0x0010]
+set NVIC_BASE [expr $SCS_BASE + 0x0100]
+set SCB_BASE [expr $SCS_BASE + 0x0D00]
projects / openocd / commitdiff