Combine different part variants into a single port.c file.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@646 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Source/portable/IAR/V850ES/port.c b/Source/portable/IAR/V850ES/port.c
index df9fbbb27d591b3d27e589e7b5266de3fcb0da22..feba836eda3ee8fdd8fd25aac5c21469db6af0ca 100644 (file)
--- a/Source/portable/IAR/V850ES/port.c
+++ b/Source/portable/IAR/V850ES/port.c
@@ -37,13 +37,13 @@
        Please ensure to read the configuration and relevant port sections of the\r
        online documentation.\r
 \r
-       http://www.FreeRTOS.org - Documentation, latest information, license and \r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
        contact details.\r
 \r
-       http://www.SafeRTOS.com - A version that is certified for use in safety \r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
        critical systems.\r
 \r
-       http://www.OpenRTOS.com - Commercial support, development, porting, \r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
        licensing and training services.\r
 */\r
 \r
@@ -184,11 +184,18 @@ static void prvSetupTimerInterrupt( void )
        TM0EQMK0  = 1;  /* INTTM0EQ0 interrupt disable */\r
        TM0EQIF0  = 0;  /* clear INTTM0EQ0 interrupt flag */\r
 \r
-       /* Set INTTM0EQ0 level 5 priority */\r
+       #ifdef __IAR_V850ES_Fx3__\r
+       {\r
+               TM0CMP0   = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1);    /* divided by 2 because peripherals only run at CPU_CLOCK/2 */\r
+       }\r
+       #else\r
+       {\r
+               TM0CMP0   = (configCPU_CLOCK_HZ / configTICK_RATE_HZ);  \r
+       }\r
+       #endif\r
+\r
        TM0EQIC0 &= 0xF8;\r
        TM0CTL0   = 0x00;\r
-       TM0CMP0   = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1);    /* divided by 2 because peripherals only run at CPU_CLOCK/2 */\r
-\r
        TM0EQIF0 =  0;  /* clear INTTM0EQ0 interrupt flag */\r
        TM0EQMK0 =  0;  /* INTTM0EQ0 interrupt enable */\r
        TM0CE =     1;  /* TMM0 operation enable */\r