\r
A special exception to the GPL can be applied should you wish to distribute\r
a combined work that includes FreeRTOS.org, without being obliged to provide\r
- the source code for any proprietary components. See the licensing section \r
+ the source code for any proprietary components. See the licensing section\r
of http://www.FreeRTOS.org for full details of how and when the exception\r
can be applied.\r
\r
Please ensure to read the configuration and relevant port sections of the\r
online documentation.\r
\r
- http://www.FreeRTOS.org - Documentation, latest information, license and \r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
contact details.\r
\r
- http://www.SafeRTOS.com - A version that is certified for use in safety \r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
critical systems.\r
\r
- http://www.OpenRTOS.com - Commercial support, development, porting, \r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
licensing and training services.\r
*/\r
\r
#include "FreeRTOS.h"\r
#include "task.h"\r
\r
-/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is \r
-defined. The value should also ensure backward compatibility. \r
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
+defined. The value should also ensure backward compatibility.\r
FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
#ifndef configKERNEL_INTERRUPT_PRIORITY\r
#define configKERNEL_INTERRUPT_PRIORITY 255\r
\r
/* Each task maintains its own interrupt status in the critical nesting\r
variable. */\r
-unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
+static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
\r
-/* \r
+/*\r
* Setup the timer to generate the tick interrupts.\r
*/\r
static void prvSetupTimerInterrupt( void );\r
\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
- * See header file for description. \r
+/*\r
+ * See header file for description.\r
*/\r
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
{\r
*pxTopOfStack = 0; /* LR */\r
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
- pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
- *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */\r
+ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
\r
return pxTopOfStack;\r
}\r
" ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */\r
" ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
- " ldmia r0!, {r1, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
- " ldr r2, uxCriticalNestingConst2 \n" /* Restore the critical nesting count used by the task. */\r
- " str r1, [r2] \n"\r
+ " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
" msr psp, r0 \n" /* Restore the task stack pointer. */\r
" mov r0, #0 \n"\r
- " msr basepri, r0 \n" \r
+ " msr basepri, r0 \n"\r
" orr r14, #0xd \n"\r
" bx r14 \n"\r
" \n"\r
" .align 2 \n"\r
"pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
- "uxCriticalNestingConst2: .word uxCriticalNesting \n"\r
);\r
}\r
/*-----------------------------------------------------------*/\r
/* ulValue is used from the asm code, but the compiler does not know\r
this so remove the warning. */\r
( void ) ulValue;\r
- \r
- asm volatile( \r
- " msr msp, r0 \n" /* Set the msp back to the start of the stack. */\r
- " svc 0 \n" /* System call to start first task. */\r
+\r
+ asm volatile(\r
+ " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n"\r
+ " ldr r0, [r0] \n"\r
+ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */\r
+ " svc 0 \n" /* System call to start first task. */\r
);\r
}\r
/*-----------------------------------------------------------*/\r
\r
-/* \r
- * See header file for description. \r
+/*\r
+ * See header file for description.\r
*/\r
portBASE_TYPE xPortStartScheduler( void )\r
{\r
/* Start the timer that generates the tick ISR. Interrupts are disabled\r
here already. */\r
prvSetupTimerInterrupt();\r
- \r
+\r
+ /* Initialise the critical nesting count ready for the first task. */\r
+ uxCriticalNesting = 0;\r
+\r
/* Start the first task. */\r
vPortStartFirstTask( *((unsigned portLONG *) 0 ) );\r
\r
{\r
/* Set a PendSV to request a context switch. */\r
*(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;\r
-\r
- /* This function is also called in response to a Yield(), so we want\r
- the yield to occur immediately. */\r
- portENABLE_INTERRUPTS();\r
}\r
/*-----------------------------------------------------------*/\r
\r
/* This is a naked function. */\r
\r
__asm volatile\r
- ( \r
- " mrs r0, psp \n" \r
- " \n"\r
- " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */\r
- " ldr r2, [r3] \n" \r
- " \n" \r
- " ldr r1, uxCriticalNestingConst \n" /* Save the remaining registers and the critical nesting count onto the task stack. */\r
- " ldr r1, [r1] \n"\r
- " stmdb r0!, {r1,r4-r11} \n"\r
- " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */\r
- " \n"\r
- " stmdb sp!, {r3, r14} \n" \r
- " bl vTaskSwitchContext \n"\r
- " ldmia sp!, {r3, r14} \n"\r
- " \n" /* Restore the context, including the critical nesting count. */\r
- " ldr r1, [r3] \n" \r
- " ldr r2, uxCriticalNestingConst \n"\r
- " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
- " ldmia r0!, {r1, r4-r11} \n" /* Pop the registers and the critical nesting count. */\r
- " str r1, [r2] \n" /* Save the new critical nesting value into ulCriticalNesting. */ \r
- " msr psp, r0 \n" \r
- " orr r14, #0xd \n"\r
- " \n" /* Exit with interrupts in the state required by the task. */ \r
- " cbnz r1, sv_disable_interrupts \n" /* If the nesting count is greater than 0 we need to exit with interrupts masked. */\r
- " bx r14 \n"\r
- " \n"\r
- "sv_disable_interrupts: \n" \r
- " ldr r1, =ulKernelPriority \n"\r
- " ldr r1, [r1] \n"\r
- " msr basepri, r1 \n"\r
- " bx r14 \n"\r
- " \n"\r
- " .align 2 \n"\r
- "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
- "uxCriticalNestingConst: .word uxCriticalNesting \n"\r
+ (\r
+ " mrs r0, psp \n"\r
+ " \n"\r
+ " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */\r
+ " ldr r2, [r3] \n"\r
+ " \n"\r
+ " stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */\r
+ " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */\r
+ " \n"\r
+ " stmdb sp!, {r3, r14} \n"\r
+ " mov r0, %0 \n"\r
+ " msr basepri, r0 \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " mov r0, #0 \n"\r
+ " msr basepri, r0 \n" \r
+ " ldmia sp!, {r3, r14} \n"\r
+ " \n" /* Restore the context, including the critical nesting count. */\r
+ " ldr r1, [r3] \n"\r
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
+ " ldmia r0!, {r4-r11} \n" /* Pop the registers. */\r
+ " msr psp, r0 \n"\r
+ " bx r14 \n"\r
+ " \n"\r
+ " .align 2 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
);\r
}\r
/*-----------------------------------------------------------*/\r
{\r
/* If using preemption, also force a context switch. */\r
#if configUSE_PREEMPTION == 1\r
- *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; \r
+ *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;\r
#endif\r
\r
- vTaskIncrementTick();\r
+ portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ vTaskIncrementTick();\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR();\r
}\r
/*-----------------------------------------------------------*/\r
\r
projects / freertos / commitdiff