David Brownell <david-b@pacbell.net> DaVinci DM355 SoC support

git-svn-id: svn://svn.berlios.de/openocd/trunk@1633 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/src/target/target/ti_dm355.cfg b/src/target/target/ti_dm355.cfg
new file mode 100644 (file)
index 0000000..95e4cbc
--- /dev/null
+++ b/src/target/target/ti_dm355.cfg
@@ -0,0 +1,63 @@
+#\r
+# Texas Instruments DaVinci family:  TMS320DM355\r
+#\r
+if { [info exists CHIPNAME] } {\r
+   set  _CHIPNAME $CHIPNAME\r
+} else {\r
+   set  _CHIPNAME dm355\r
+}\r
+if { [info exists ENDIAN] } {\r
+   set  _ENDIAN $ENDIAN\r
+} else {\r
+   set  _ENDIAN little\r
+}\r
+\r
+#\r
+# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB\r
+# are enabled without making ICEpick route ARM and ETB into the JTAG chain.\r
+#\r
+# Also note:  when running without RTCK before the PLLs are set up, you\r
+# may need to slow the JTAG clock down quite a lot (under 2 MHz).\r
+#\r
+\r
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer\r
+if { [info exists ETB_TAPID ] } {\r
+   set _ETB_TAPID $ETB_TAPID\r
+} else {\r
+   set _ETB_TAPID 0x2b900f0f\r
+}\r
+jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID\r
+\r
+# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.\r
+if { [info exists CPU_TAPID ] } {\r
+   set _CPU_TAPID $CPU_TAPID\r
+} else {\r
+   set _CPU_TAPID 0x07926001\r
+}\r
+jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU_TAPID\r
+\r
+# Primary TAP: ICEpick (JTAG route controller) and boundary scan\r
+if { [info exists JRC_TAPID ] } {\r
+   set _JRC_TAPID $JRC_TAPID\r
+} else {\r
+   set _JRC_TAPID 0x0b73b02f\r
+}\r
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID\r
+\r
+# GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)\r
+# and the ETB memory (4K) are other options, while trace is unused.\r
+set _TARGETNAME $_CHIPNAME.arm\r
+\r
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME\r
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00014000 -work-area-size 0x4000 -work-area-backup 0\r
+\r
+arm7_9 dbgrq enable\r
+arm7_9 fast_memory_access enable\r
+arm7_9 dcc_downloads enable\r
+\r
+# trace setup\r
+# FIXME we ought to be able to say "... config $_TARGETNAME ..."\r
+# (not "config 0") facilitating additional targets (e.g. other chips)\r
+etm config 0 16 normal full etb\r
+etb config 0 $_CHIPNAME.etb\r
+\r