48, /* thread_state_offset; */
136, /* thread_next_offset */
&rtos_standard_Cortex_M3_stacking, /* stacking_info */
- }
+ },
+ {
+ "cortex_r4", /* target_name */
+ 4, /* pointer_width; */
+ 8, /* thread_stack_offset; */
+ 40, /* thread_name_offset; */
+ 48, /* thread_state_offset; */
+ 136, /* thread_next_offset */
+ &rtos_standard_Cortex_R4_stacking, /* stacking_info */
+ },
};
#define THREADX_NUM_PARAMS ((int)(sizeof(ThreadX_params_list)/sizeof(struct ThreadX_params)))
{ 0x3c, 32 }, /* xPSR */
};
+
+static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets[] = {
+ { 0x08, 32 }, /* r0 (a1) */
+ { 0x0c, 32 }, /* r1 (a2) */
+ { 0x10, 32 }, /* r2 (a3) */
+ { 0x14, 32 }, /* r3 (a4) */
+ { 0x18, 32 }, /* r4 (v1) */
+ { 0x1c, 32 }, /* r5 (v2) */
+ { 0x20, 32 }, /* r6 (v3) */
+ { 0x24, 32 }, /* r7 (v4) */
+ { 0x28, 32 }, /* r8 (a1) */
+ { 0x2c, 32 }, /* r9 (sb) */
+ { 0x30, 32 }, /* r10 (sl) */
+ { 0x34, 32 }, /* r11 (fp) */
+ { 0x38, 32 }, /* r12 (ip) */
+ { -2, 32 }, /* sp */
+ { 0x3c, 32 }, /* lr */
+ { 0x40, 32 }, /* pc */
+ { -1, 96 }, /* FPA1 */
+ { -1, 96 }, /* FPA2 */
+ { -1, 96 }, /* FPA3 */
+ { -1, 96 }, /* FPA4 */
+ { -1, 96 }, /* FPA5 */
+ { -1, 96 }, /* FPA6 */
+ { -1, 96 }, /* FPA7 */
+ { -1, 96 }, /* FPA8 */
+ { -1, 32 }, /* FPS */
+ { 0x04, 32 }, /* CSPR */
+};
+
const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = {
0x40, /* stack_registers_size */
-1, /* stack_growth_direction */
8, /* stack_alignment */
rtos_standard_Cortex_M3_stack_offsets /* register_offsets */
};
+
+
+const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking = {
+ 0x48, /* stack_registers_size */
+ -1, /* stack_growth_direction */
+ 26, /* num_output_registers */
+ 8, /* stack_alignment */
+ rtos_standard_Cortex_R4_stack_offsets /* register_offsets */
+};