Reluctantly convert to use the CMSIS header files.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@807 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/emac.c b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/emac.c
index 660d707d3fc03f1236c5ddd0836aefb1105a3820..7e92422e07283c9ce324264fcf5d1a7f97f0f4fd 100644 (file)
--- a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/emac.c
+++ b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/emac.c
@@ -57,7 +57,6 @@
 #include "semphr.h"\r
 \r
 /* Hardware specific includes. */\r
-#include "LPC17xx_defs.h"\r
 #include "EthDev_LPC17xx.h"\r
 \r
 /* Time to wait between each inspection of the link status. */\r
@@ -150,7 +149,6 @@ static unsigned short usSendLen = 0;
 long lEMACInit( void )\r
 {\r
 long lReturn = pdPASS;\r
-volatile unsigned long regv, tout;\r
 unsigned long ulID1, ulID2;\r
 \r
        /* Reset peripherals, configure port pins and registers. */\r
@@ -162,15 +160,15 @@ unsigned long ulID1, ulID2;
        if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFF0UL ) ) == DP83848C_ID )\r
        {\r
                /* Set the Ethernet MAC Address registers */\r
-               MAC_SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;\r
-               MAC_SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;\r
-               MAC_SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;\r
+               EMAC->SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;\r
+               EMAC->SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;\r
+               EMAC->SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;\r
 \r
                /* Initialize Tx and Rx DMA Descriptors */\r
                prvInitDescriptors();\r
 \r
                /* Receive broadcast and perfect match packets */\r
-               MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;\r
+               EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;\r
 \r
                /* Setup the PHY. */\r
                prvConfigurePHY();\r
@@ -192,11 +190,11 @@ unsigned long ulID1, ulID2;
                uip_buf = prvGetNextBuffer();\r
 \r
                /* Reset all interrupts */\r
-               MAC_INTCLEAR = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );\r
+               EMAC->IntClear = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );\r
 \r
                /* Enable receive and transmit mode of MAC Ethernet core */\r
-               MAC_COMMAND |= ( CR_RX_EN | CR_TX_EN );\r
-               MAC_MAC1 |= MAC1_REC_EN;\r
+               EMAC->Command |= ( CR_RX_EN | CR_TX_EN );\r
+               EMAC->MAC1 |= MAC1_REC_EN;\r
        }\r
 \r
        return lReturn;\r
@@ -260,12 +258,12 @@ long x, lNextBuffer = 0;
        }\r
 \r
        /* Set EMAC Receive Descriptor Registers. */\r
-       MAC_RXDESCRIPTOR = RX_DESC_BASE;\r
-       MAC_RXSTATUS = RX_STAT_BASE;\r
-       MAC_RXDESCRIPTORNUM = NUM_RX_FRAG - 1;\r
+       EMAC->RxDescriptor = RX_DESC_BASE;\r
+       EMAC->RxStatus = RX_STAT_BASE;\r
+       EMAC->RxDescriptorNumber = NUM_RX_FRAG - 1;\r
 \r
        /* Rx Descriptors Point to 0 */\r
-       MAC_RXCONSUMEINDEX = 0;\r
+       EMAC->RxConsumeIndex = 0;\r
 \r
        /* A buffer is not allocated to the Tx descriptors until they are actually\r
        used. */\r
@@ -277,12 +275,12 @@ long x, lNextBuffer = 0;
        }\r
 \r
        /* Set EMAC Transmit Descriptor Registers. */\r
-       MAC_TXDESCRIPTOR = TX_DESC_BASE;\r
-       MAC_TXSTATUS = TX_STAT_BASE;\r
-       MAC_TXDESCRIPTORNUM = NUM_TX_FRAG - 1;\r
+       EMAC->TxDescriptor = TX_DESC_BASE;\r
+       EMAC->TxStatus = TX_STAT_BASE;\r
+       EMAC->TxDescriptorNumber = NUM_TX_FRAG - 1;\r
 \r
        /* Tx Descriptors Point to 0 */\r
-       MAC_TXPRODUCEINDEX = 0;\r
+       EMAC->TxProduceIndex = 0;\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -292,34 +290,34 @@ unsigned short us;
 long x, lDummy;\r
 \r
        /* Enable P1 Ethernet Pins. */\r
-       PINSEL2 = emacPINSEL2_VALUE;\r
-       PINSEL3 = ( PINSEL3 & ~0x0000000F ) | 0x00000005;\r
+       PINCON->PINSEL2 = emacPINSEL2_VALUE;\r
+       PINCON->PINSEL3 = ( PINCON->PINSEL3 & ~0x0000000F ) | 0x00000005;\r
 \r
        /* Power Up the EMAC controller. */\r
-       PCONP |= PCONP_PCENET;\r
+       SC->PCONP |= PCONP_PCENET;\r
        vTaskDelay( emacSHORT_DELAY );\r
 \r
        /* Reset all EMAC internal modules. */\r
-       MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;\r
-       MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;\r
+       EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;\r
+       EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;\r
 \r
        /* A short delay after reset. */\r
        vTaskDelay( emacSHORT_DELAY );\r
 \r
        /* Initialize MAC control registers. */\r
-       MAC_MAC1 = MAC1_PASS_ALL;\r
-       MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;\r
-       MAC_MAXF = ETH_MAX_FLEN;\r
-       MAC_CLRT = CLRT_DEF;\r
-       MAC_IPGR = IPGR_DEF;\r
+       EMAC->MAC1 = MAC1_PASS_ALL;\r
+       EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;\r
+       EMAC->MAXF = ETH_MAX_FLEN;\r
+       EMAC->CLRT = CLRT_DEF;\r
+       EMAC->IPGR = IPGR_DEF;\r
 \r
        /* Enable Reduced MII interface. */\r
-       MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM;\r
+       EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;\r
 \r
        /* Reset Reduced MII Logic. */\r
-       MAC_SUPP = SUPP_RES_RMII;\r
+       EMAC->SUPP = SUPP_RES_RMII;\r
        vTaskDelay( emacSHORT_DELAY );\r
-       MAC_SUPP = 0;\r
+       EMAC->SUPP = 0;\r
 \r
        /* Put the PHY in reset mode */\r
        prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );\r
@@ -389,26 +387,26 @@ unsigned short usLinkStatus;
                if( usLinkStatus & emacFULL_DUPLEX_ENABLED )\r
                {\r
                        /* Full duplex is enabled. */\r
-                       MAC_MAC2 |= MAC2_FULL_DUP;\r
-                       MAC_COMMAND |= CR_FULL_DUP;\r
-                       MAC_IPGT = IPGT_FULL_DUP;\r
+                       EMAC->MAC2 |= MAC2_FULL_DUP;\r
+                       EMAC->Command |= CR_FULL_DUP;\r
+                       EMAC->IPGT = IPGT_FULL_DUP;\r
                }\r
                else\r
                {\r
                        /* Half duplex mode. */\r
-                       MAC_IPGT = IPGT_HALF_DUP;\r
+                       EMAC->IPGT = IPGT_HALF_DUP;\r
                }\r
 \r
                /* Configure 100MBit/10MBit mode. */\r
                if( usLinkStatus & emac10BASE_T_MODE )\r
                {\r
                        /* 10MBit mode. */\r
-                       MAC_SUPP = 0;\r
+                       EMAC->SUPP = 0;\r
                }\r
                else\r
                {\r
                        /* 100MBit mode. */\r
-                       MAC_SUPP = SUPP_SPEED;\r
+                       EMAC->SUPP = SUPP_SPEED;\r
                }\r
        }\r
 \r
@@ -437,21 +435,21 @@ unsigned long ulGetEMACRxData( void )
 unsigned long ulLen = 0;\r
 long lIndex;\r
 \r
-       if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX )\r
+       if( EMAC->RxProduceIndex != EMAC->RxConsumeIndex )\r
        {\r
                /* Mark the current buffer as free as uip_buf is going to be set to\r
                the buffer that contains the received data. */\r
                prvReturnBuffer( uip_buf );\r
 \r
-               ulLen = ( RX_STAT_INFO( MAC_RXCONSUMEINDEX ) & RINFO_SIZE ) - 3;\r
-               uip_buf = ( unsigned char * ) RX_DESC_PACKET( MAC_RXCONSUMEINDEX );\r
+               ulLen = ( RX_STAT_INFO( EMAC->RxConsumeIndex ) & RINFO_SIZE ) - 3;\r
+               uip_buf = ( unsigned char * ) RX_DESC_PACKET( EMAC->RxConsumeIndex );\r
 \r
                /* Allocate a new buffer to the descriptor. */\r
-        RX_DESC_PACKET( MAC_RXCONSUMEINDEX ) = ( unsigned long ) prvGetNextBuffer();\r
+        RX_DESC_PACKET( EMAC->RxConsumeIndex ) = ( unsigned long ) prvGetNextBuffer();\r
 \r
                /* Move the consume index onto the next position, ensuring it wraps to\r
                the beginning at the appropriate place. */\r
-               lIndex = MAC_RXCONSUMEINDEX;\r
+               lIndex = EMAC->RxConsumeIndex;\r
 \r
                lIndex++;\r
                if( lIndex >= NUM_RX_FRAG )\r
@@ -459,7 +457,7 @@ long lIndex;
                        lIndex = 0;\r
                }\r
 \r
-               MAC_RXCONSUMEINDEX = lIndex;\r
+               EMAC->RxConsumeIndex = lIndex;\r
        }\r
 \r
        return ulLen;\r
@@ -494,7 +492,7 @@ unsigned long ulAttempts = 0UL;
        usSendLen = usTxDataLen;\r
        TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) uip_buf;\r
        TX_DESC_CTRL( emacTX_DESC_INDEX ) = ( usTxDataLen | TCTRL_LAST | TCTRL_INT );\r
-       MAC_TXPRODUCEINDEX = ( emacTX_DESC_INDEX + 1 );\r
+       EMAC->TxProduceIndex = ( emacTX_DESC_INDEX + 1 );\r
 \r
        /* uip_buf is being sent by the Tx descriptor.  Allocate a new buffer. */\r
        uip_buf = prvGetNextBuffer();\r
@@ -506,13 +504,13 @@ static long prvWritePHY( long lPhyReg, long lValue )
 const long lMaxTime = 10;\r
 long x;\r
 \r
-       MAC_MADR = DP83848C_DEF_ADR | lPhyReg;\r
-       MAC_MWTD = lValue;\r
+       EMAC->MADR = DP83848C_DEF_ADR | lPhyReg;\r
+       EMAC->MWTD = lValue;\r
 \r
        x = 0;\r
        for( x = 0; x < lMaxTime; x++ )\r
        {\r
-               if( ( MAC_MIND & MIND_BUSY ) == 0 )\r
+               if( ( EMAC->MIND & MIND_BUSY ) == 0 )\r
                {\r
                        /* Operation has finished. */\r
                        break;\r
@@ -537,13 +535,13 @@ static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus )
 long x;\r
 const long lMaxTime = 10;\r
 \r
-       MAC_MADR = DP83848C_DEF_ADR | ucPhyReg;\r
-       MAC_MCMD = MCMD_READ;\r
+       EMAC->MADR = DP83848C_DEF_ADR | ucPhyReg;\r
+       EMAC->MCMD = MCMD_READ;\r
 \r
        for( x = 0; x < lMaxTime; x++ )\r
        {\r
                /* Operation has finished. */\r
-               if( ( MAC_MIND & MIND_BUSY ) == 0 )\r
+               if( ( EMAC->MIND & MIND_BUSY ) == 0 )\r
                {\r
                        break;\r
                }\r
@@ -551,31 +549,31 @@ const long lMaxTime = 10;
                vTaskDelay( emacSHORT_DELAY );\r
        }\r
 \r
-       MAC_MCMD = 0;\r
+       EMAC->MCMD = 0;\r
 \r
        if( x >= lMaxTime )\r
        {\r
                *plStatus = pdFAIL;\r
        }\r
 \r
-       return( MAC_MRDD );\r
+       return( EMAC->MRDD );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
 void vEMAC_ISR( void )\r
 {\r
 unsigned long ulStatus;\r
-portBASE_TYPE  xHigherPriorityTaskWoken = pdFALSE;\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
 \r
-       ulStatus = MAC_INTSTATUS;\r
+       ulStatus = EMAC->IntStatus;\r
 \r
        /* Clear the interrupt. */\r
-       MAC_INTCLEAR = ulStatus;\r
+       EMAC->IntClear = ulStatus;\r
 \r
        if( ulStatus & INT_RX_DONE )\r
        {\r
                /* Ensure the uIP task is not blocked as data has arrived. */\r
-               xSemaphoreGiveFromISR( xEMACSemaphore, &xHigherPriorityTaskWoken );\r
+               xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );\r
        }\r
 \r
        if( ulStatus & INT_TX_DONE )\r
@@ -586,7 +584,7 @@ portBASE_TYPE       xHigherPriorityTaskWoken = pdFALSE;
                        only two descriptors the index is set back to 0. */\r
                        TX_DESC_PACKET( ( emacTX_DESC_INDEX + 1 ) ) = TX_DESC_PACKET( emacTX_DESC_INDEX );\r
                        TX_DESC_CTRL( ( emacTX_DESC_INDEX + 1 ) ) = ( usSendLen | TCTRL_LAST | TCTRL_INT );\r
-                       MAC_TXPRODUCEINDEX = ( emacTX_DESC_INDEX );\r
+                       EMAC->TxProduceIndex = ( emacTX_DESC_INDEX );\r
 \r
                        /* This is the second Tx so set usSendLen to 0 to indicate that the\r
                        Tx descriptors will be free again. */\r
@@ -600,5 +598,5 @@ portBASE_TYPE       xHigherPriorityTaskWoken = pdFALSE;
                }\r
        }\r
 \r
-       portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+       portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );\r
 }\r

diff --git a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c
index f8efc3708f0d8f948923edb6f09e3ea1853b7149..75ba96d592c2affa27d429707e5779e1aa4c2b71 100644 (file)
--- a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c
+++ b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c
@@ -144,7 +144,7 @@ extern void ( vEMAC_ISR_Wrapper )( void );
 \r
        portENTER_CRITICAL();\r
        {\r
-               ETH_INTENABLE = ( INT_RX_DONE | INT_TX_DONE );\r
+               EMAC->IntEnable = ( INT_RX_DONE | INT_TX_DONE );\r
                /* set the interrupt priority */\r
                NVIC_SetPriority( ENET_IRQn, configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
                /* enable the interrupt */\r