Added timeout(instead of infinite loop) to soft_reset_halt

git-svn-id: svn://svn.berlios.de/openocd/trunk@533 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 6b2e2151e3c4026c00199169a847033eb60916e1..118fff45ea125fc9c7f182519268bdf7261412d4 100644 (file)
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -365,14 +365,28 @@ int arm720t_soft_reset_halt(struct target_s *target)
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
        arm720t_common_t *arm720t = arm7tdmi->arch_info;
+       int i;
        reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
        
        target->type->halt(target);
        
-       while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+       for (i=0; i<10; i++)
        {
-               embeddedice_read_reg(dbg_stat);
-               jtag_execute_queue();
+               if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+               {
+                       embeddedice_read_reg(dbg_stat);
+                       jtag_execute_queue();
+               } else
+               {
+                       break;
+               }
+               /* do not eat all CPU, time out after 1 se*/
+               usleep(100*1000);
+       }
+       if (i==10)
+       {
+               LOG_ERROR("Failed to halt CPU after 1 sec");
+               return ERROR_TARGET_TIMEOUT;
        }
        
        target->state = TARGET_HALTED;

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 3d178161481b5096dc6c252331649815e76a861a..2468202fbc03de1893b2035388e717e90751d1d1 100644 (file)
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -622,13 +622,27 @@ int arm920t_soft_reset_halt(struct target_s *target)
        arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
        arm920t_common_t *arm920t = arm9tdmi->arch_info;
        reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       int i;
        
        target->type->halt(target);
        
-       while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+       for (i=0; i<10; i++)
        {
-               embeddedice_read_reg(dbg_stat);
-               jtag_execute_queue();
+               if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+               {
+                       embeddedice_read_reg(dbg_stat);
+                       jtag_execute_queue();
+               } else
+               {
+                       break;
+               }
+               /* do not eat all CPU, time out after 1 se*/
+               usleep(100*1000);
+       }
+       if (i==10)
+       {
+               LOG_ERROR("Failed to halt CPU after 1 sec");
+               return ERROR_TARGET_TIMEOUT;
        }
        
        target->state = TARGET_HALTED;

diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index caf5b7ba75d7e1ddc56938fc392afce5530d7272..4636023094d74bb9ccf825322bc0339e52c8bdc5 100644 (file)
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -578,13 +578,27 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
        arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
        arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
        reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+       int i;
        
        target->type->halt(target);
        
-       while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+       for (i=0; i<10; i++)
        {
-               embeddedice_read_reg(dbg_stat);
-               jtag_execute_queue();
+               if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+               {
+                       embeddedice_read_reg(dbg_stat);
+                       jtag_execute_queue();
+               }  else
+               {
+                       break;
+               }
+               /* do not eat all CPU, time out after 1 se*/
+               usleep(100*1000);
+       }
+       if (i==10)
+       {
+               LOG_ERROR("Failed to halt CPU after 1 sec");
+               return ERROR_TARGET_TIMEOUT;
        }
        
        target->state = TARGET_HALTED;