select DM
select DM_THERMAL
+config TARGET_MX6SXSABREAUTO
+ bool "mx6sxsabreauto"
+ select DM
+ select DM_THERMAL
+
config TARGET_MX6UL_9X9_EVK
bool "mx6ul_9x9_evk"
select MX6UL
source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
source "board/freescale/mx6sxsabresd/Kconfig"
+source "board/freescale/mx6sxsabreauto/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
}
temp = freq * max_pred * max_postd;
- if (temp > max) {
- puts("Please decrease freq, too large!\n");
- return;
- }
if (temp < min) {
/*
* Register: PLL_VIDEO
u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
if (is_cpu_type(MXC_CPU_MX6SX)) {
- if ((base_addr == LCDIF1_BASE_ADDR) ||
- (base_addr == LCDIF2_BASE_ADDR)) {
+ if ((base_addr != LCDIF1_BASE_ADDR) &&
+ (base_addr != LCDIF2_BASE_ADDR)) {
puts("Wrong LCD interface!\n");
return -EINVAL;
}
#include <asm/io.h>
#include <asm/types.h>
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+
+static int wait_for_bit(void *reg, const uint32_t mask, bool set)
+{
+ unsigned int timeout = 1000;
+ u32 val;
+
+ while (--timeout) {
+ val = readl(reg);
+ if (!set)
+ val = ~val;
+
+ if ((val & mask) == mask)
+ return 0;
+
+ udelay(1);
+ }
+
+ printf("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
+ __func__, reg, mask, set);
+ hang(); /* DRAM couldn't be calibrated, game over :-( */
+}
+
+static void reset_read_data_fifos(void)
+{
+ struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+
+ /* Reset data FIFOs twice. */
+ setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
+ wait_for_bit(&mmdc0->mpdgctrl0, 1 << 31, 0);
+
+ setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
+ wait_for_bit(&mmdc0->mpdgctrl0, 1 << 31, 0);
+}
+
+static void precharge_all(const bool cs0_enable, const bool cs1_enable)
+{
+ struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+
+ /*
+ * Issue the Precharge-All command to the DDR device for both
+ * chip selects. Note, CON_REQ bit should also remain set. If
+ * only using one chip select, then precharge only the desired
+ * chip select.
+ */
+ if (cs0_enable) { /* CS0 */
+ writel(0x04008050, &mmdc0->mdscr);
+ wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
+ }
+
+ if (cs1_enable) { /* CS1 */
+ writel(0x04008058, &mmdc0->mdscr);
+ wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
+ }
+}
+
+static void force_delay_measurement(int bus_size)
+{
+ struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+ struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+
+ writel(0x800, &mmdc0->mpmur0);
+ if (bus_size == 0x2)
+ writel(0x800, &mmdc1->mpmur0);
+}
+
+static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
+{
+ u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl;
+
+ /*
+ * DQS gating absolute offset should be modified from reflecting
+ * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80)
+ */
+
+ val_ctrl = readl(reg_ctrl);
+ val_ctrl &= 0xf0000000;
+
+ dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0;
+ dg_dl_abs_offset = dg_tmp_val & 0x7f;
+ dg_hc_del = (dg_tmp_val & 0x780) << 1;
+
+ val_ctrl |= dg_dl_abs_offset + dg_hc_del;
+
+ dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0;
+ dg_dl_abs_offset = dg_tmp_val & 0x7f;
+ dg_hc_del = (dg_tmp_val & 0x780) << 1;
+
+ val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16;
+
+ writel(val_ctrl, reg_ctrl);
+}
+
+int mmdc_do_write_level_calibration(void)
+{
+ struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+ struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+ u32 esdmisc_val, zq_val;
+ u32 errors = 0;
+ u32 ldectrl[4];
+ u32 ddr_mr1 = 0x4;
+
+ /*
+ * Stash old values in case calibration fails,
+ * we need to restore them
+ */
+ ldectrl[0] = readl(&mmdc0->mpwldectrl0);
+ ldectrl[1] = readl(&mmdc0->mpwldectrl1);
+ ldectrl[2] = readl(&mmdc1->mpwldectrl0);
+ ldectrl[3] = readl(&mmdc1->mpwldectrl1);
+
+ /* disable DDR logic power down timer */
+ clrbits_le32(&mmdc0->mdpdc, 0xff00);
+
+ /* disable Adopt power down timer */
+ setbits_le32(&mmdc0->mapsr, 0x1);
+
+ debug("Starting write leveling calibration.\n");
+
+ /*
+ * 2. disable auto refresh and ZQ calibration
+ * before proceeding with Write Leveling calibration
+ */
+ esdmisc_val = readl(&mmdc0->mdref);
+ writel(0x0000C000, &mmdc0->mdref);
+ zq_val = readl(&mmdc0->mpzqhwctrl);
+ writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
+
+ /* 3. increase walat and ralat to maximum */
+ setbits_le32(&mmdc0->mdmisc,
+ (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
+ setbits_le32(&mmdc1->mdmisc,
+ (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
+ /*
+ * 4 & 5. Configure the external DDR device to enter write-leveling
+ * mode through Load Mode Register command.
+ * Register setting:
+ * Bits[31:16] MR1 value (0x0080 write leveling enable)
+ * Bit[9] set WL_EN to enable MMDC DQS output
+ * Bits[6:4] set CMD bits for Load Mode Register programming
+ * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
+ */
+ writel(0x00808231, &mmdc0->mdscr);
+
+ /* 6. Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */
+ writel(0x00000001, &mmdc0->mpwlgcr);
+
+ /*
+ * 7. Upon completion of this process the MMDC de-asserts
+ * the MPWLGCR[HW_WL_EN]
+ */
+ wait_for_bit(&mmdc0->mpwlgcr, 1 << 0, 0);
+
+ /*
+ * 8. check for any errors: check both PHYs for x64 configuration,
+ * if x32, check only PHY0
+ */
+ if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
+ errors |= 1;
+ if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
+ errors |= 2;
+
+ debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
+
+ /* check to see if cal failed */
+ if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
+ (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
+ (readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
+ (readl(&mmdc1->mpwldectrl1) == 0x001F001F)) {
+ debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
+ writel(ldectrl[0], &mmdc0->mpwldectrl0);
+ writel(ldectrl[1], &mmdc0->mpwldectrl1);
+ writel(ldectrl[2], &mmdc1->mpwldectrl0);
+ writel(ldectrl[3], &mmdc1->mpwldectrl1);
+ errors |= 4;
+ }
+
+ /*
+ * User should issue MRS command to exit write leveling mode
+ * through Load Mode Register command
+ * Register setting:
+ * Bits[31:16] MR1 value "ddr_mr1" value from initialization
+ * Bit[9] clear WL_EN to disable MMDC DQS output
+ * Bits[6:4] set CMD bits for Load Mode Register programming
+ * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
+ */
+ writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);
+
+ /* re-enable auto refresh and zq cal */
+ writel(esdmisc_val, &mmdc0->mdref);
+ writel(zq_val, &mmdc0->mpzqhwctrl);
+
+ debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
+ readl(&mmdc0->mpwldectrl0));
+ debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
+ readl(&mmdc0->mpwldectrl1));
+ debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
+ readl(&mmdc1->mpwldectrl0));
+ debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
+ readl(&mmdc1->mpwldectrl1));
+
+ /* We must force a readback of these values, to get them to stick */
+ readl(&mmdc0->mpwldectrl0);
+ readl(&mmdc0->mpwldectrl1);
+ readl(&mmdc1->mpwldectrl0);
+ readl(&mmdc1->mpwldectrl1);
+
+ /* enable DDR logic power down timer: */
+ setbits_le32(&mmdc0->mdpdc, 0x00005500);
+
+ /* Enable Adopt power down timer: */
+ clrbits_le32(&mmdc0->mapsr, 0x1);
+
+ /* Clear CON_REQ */
+ writel(0, &mmdc0->mdscr);
+
+ return errors;
+}
+
+int mmdc_do_dqs_calibration(void)
+{
+ struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+ struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+ struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux =
+ (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
+ bool cs0_enable;
+ bool cs1_enable;
+ bool cs0_enable_initial;
+ bool cs1_enable_initial;
+ u32 esdmisc_val;
+ u32 bus_size;
+ u32 temp_ref;
+ u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
+ u32 errors = 0;
+ u32 initdelay = 0x40404040;
+
+ /* check to see which chip selects are enabled */
+ cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000;
+ cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000;
+
+ /* disable DDR logic power down timer: */
+ clrbits_le32(&mmdc0->mdpdc, 0xff00);
+
+ /* disable Adopt power down timer: */
+ setbits_le32(&mmdc0->mapsr, 0x1);
+
+ /* set DQS pull ups */
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000);
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000);
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000);
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000);
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000);
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000);
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000);
+ setbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000);
+
+ /* Save old RALAT and WALAT values */
+ esdmisc_val = readl(&mmdc0->mdmisc);
+
+ setbits_le32(&mmdc0->mdmisc,
+ (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
+
+ /* Disable auto refresh before proceeding with calibration */
+ temp_ref = readl(&mmdc0->mdref);
+ writel(0x0000c000, &mmdc0->mdref);
+
+ /*
+ * Per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2,
+ * this also sets the CON_REQ bit.
+ */
+ if (cs0_enable_initial)
+ writel(0x00008020, &mmdc0->mdscr);
+ if (cs1_enable_initial)
+ writel(0x00008028, &mmdc0->mdscr);
+
+ /* poll to make sure the con_ack bit was asserted */
+ wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
+
+ /*
+ * Check MDMISC register CALIB_PER_CS to see which CS calibration
+ * is targeted to (under normal cases, it should be cleared
+ * as this is the default value, indicating calibration is directed
+ * to CS0).
+ * Disable the other chip select not being target for calibration
+ * to avoid any potential issues. This will get re-enabled at end
+ * of calibration.
+ */
+ if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0)
+ clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
+ else
+ clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
+
+ /*
+ * Check to see which chip selects are now enabled for
+ * the remainder of the calibration.
+ */
+ cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
+ cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
+
+ /* Check to see what the data bus size is */
+ bus_size = (readl(&mmdc0->mdctl) & 0x30000) >> 16;
+ debug("Data bus size: %d (%d bits)\n", bus_size, 1 << (bus_size + 4));
+
+ precharge_all(cs0_enable, cs1_enable);
+
+ /* Write the pre-defined value into MPPDCMPR1 */
+ writel(pddword, &mmdc0->mppdcmpr1);
+
+ /*
+ * Issue a write access to the external DDR device by setting
+ * the bit SW_DUMMY_WR (bit 0) in the MPSWDAR0 and then poll
+ * this bit until it clears to indicate completion of the write access.
+ */
+ setbits_le32(&mmdc0->mpswdar0, 1);
+ wait_for_bit(&mmdc0->mpswdar0, 1 << 0, 0);
+
+ /* Set the RD_DL_ABS# bits to their default values
+ * (will be calibrated later in the read delay-line calibration).
+ * Both PHYs for x64 configuration, if x32, do only PHY0.
+ */
+ writel(initdelay, &mmdc0->mprddlctl);
+ if (bus_size == 0x2)
+ writel(initdelay, &mmdc1->mprddlctl);
+
+ /* Force a measurment, for previous delay setup to take effect. */
+ force_delay_measurement(bus_size);
+
+ /*
+ * ***************************
+ * Read DQS Gating calibration
+ * ***************************
+ */
+ debug("Starting Read DQS Gating calibration.\n");
+
+ /*
+ * Reset the read data FIFOs (two resets); only need to issue reset
+ * to PHY0 since in x64 mode, the reset will also go to PHY1.
+ */
+ reset_read_data_fifos();
+
+ /*
+ * Start the automatic read DQS gating calibration process by
+ * asserting MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC]
+ * and then poll MPDGCTRL0[HW_DG_EN]] until this bit clears
+ * to indicate completion.
+ * Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate
+ * no errors were seen during calibration.
+ */
+
+ /*
+ * Set bit 30: chooses option to wait 32 cycles instead of
+ * 16 before comparing read data.
+ */
+ setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
+
+ /* Set bit 28 to start automatic read DQS gating calibration */
+ setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
+
+ /* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
+ wait_for_bit(&mmdc0->mpdgctrl0, 1 << 28, 0);
+
+ /*
+ * Check to see if any errors were encountered during calibration
+ * (check MPDGCTRL0[HW_DG_ERR]).
+ * Check both PHYs for x64 configuration, if x32, check only PHY0.
+ */
+ if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
+ errors |= 1;
+
+ if ((bus_size == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
+ errors |= 2;
+
+ /*
+ * DQS gating absolute offset should be modified from
+ * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
+ * reflecting (HW_DG_UPx - 0x80)
+ */
+ modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1,
+ &mmdc0->mpdgctrl0);
+ modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
+ &mmdc0->mpdgctrl1);
+ if (bus_size == 0x2) {
+ modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
+ &mmdc1->mpdgctrl0);
+ modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
+ &mmdc1->mpdgctrl1);
+ }
+ debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors);
+
+ /*
+ * **********************
+ * Read Delay calibration
+ * **********************
+ */
+ debug("Starting Read Delay calibration.\n");
+
+ reset_read_data_fifos();
+
+ /*
+ * 4. Issue the Precharge-All command to the DDR device for both
+ * chip selects. If only using one chip select, then precharge
+ * only the desired chip select.
+ */
+ precharge_all(cs0_enable, cs1_enable);
+
+ /*
+ * 9. Read delay-line calibration
+ * Start the automatic read calibration process by asserting
+ * MPRDDLHWCTL[HW_RD_DL_EN].
+ */
+ writel(0x00000030, &mmdc0->mprddlhwctl);
+
+ /*
+ * 10. poll for completion
+ * MMDC indicates that the write data calibration had finished by
+ * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
+ * no error bits were set.
+ */
+ wait_for_bit(&mmdc0->mprddlhwctl, 1 << 4, 0);
+
+ /* check both PHYs for x64 configuration, if x32, check only PHY0 */
+ if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
+ errors |= 4;
+
+ if ((bus_size == 0x2) && (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
+ errors |= 8;
+
+ debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
+
+ /*
+ * ***********************
+ * Write Delay Calibration
+ * ***********************
+ */
+ debug("Starting Write Delay calibration.\n");
+
+ reset_read_data_fifos();
+
+ /*
+ * 4. Issue the Precharge-All command to the DDR device for both
+ * chip selects. If only using one chip select, then precharge
+ * only the desired chip select.
+ */
+ precharge_all(cs0_enable, cs1_enable);
+
+ /*
+ * 8. Set the WR_DL_ABS# bits to their default values.
+ * Both PHYs for x64 configuration, if x32, do only PHY0.
+ */
+ writel(initdelay, &mmdc0->mpwrdlctl);
+ if (bus_size == 0x2)
+ writel(initdelay, &mmdc1->mpwrdlctl);
+
+ /*
+ * XXX This isn't in the manual. Force a measurement,
+ * for previous delay setup to effect.
+ */
+ force_delay_measurement(bus_size);
+
+ /*
+ * 9. 10. Start the automatic write calibration process
+ * by asserting MPWRDLHWCTL0[HW_WR_DL_EN].
+ */
+ writel(0x00000030, &mmdc0->mpwrdlhwctl);
+
+ /*
+ * Poll for completion.
+ * MMDC indicates that the write data calibration had finished
+ * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
+ * Also, ensure that no error bits were set.
+ */
+ wait_for_bit(&mmdc0->mpwrdlhwctl, 1 << 4, 0);
+
+ /* Check both PHYs for x64 configuration, if x32, check only PHY0 */
+ if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
+ errors |= 16;
+
+ if ((bus_size == 0x2) && (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
+ errors |= 32;
+
+ debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
+
+ reset_read_data_fifos();
+
+ /* Enable DDR logic power down timer */
+ setbits_le32(&mmdc0->mdpdc, 0x00005500);
+
+ /* Enable Adopt power down timer */
+ clrbits_le32(&mmdc0->mapsr, 0x1);
+
+ /* Restore MDMISC value (RALAT, WALAT) to MMDCP1 */
+ writel(esdmisc_val, &mmdc0->mdmisc);
+
+ /* Clear DQS pull ups */
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000);
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000);
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000);
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000);
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000);
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000);
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000);
+ clrbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000);
+
+ /* Re-enable SDE (chip selects) if they were set initially */
+ if (cs1_enable_initial)
+ /* Set SDE_1 */
+ setbits_le32(&mmdc0->mdctl, 1 << 30);
+
+ if (cs0_enable_initial)
+ /* Set SDE_0 */
+ setbits_le32(&mmdc0->mdctl, 1 << 31);
+
+ /* Re-enable to auto refresh */
+ writel(temp_ref, &mmdc0->mdref);
+
+ /* Clear the MDSCR (including the con_req bit) */
+ writel(0x0, &mmdc0->mdscr); /* CS0 */
+
+ /* Poll to make sure the con_ack bit is clear */
+ wait_for_bit(&mmdc0->mdscr, 1 << 14, 0);
+
+ /*
+ * Print out the registers that were updated as a result
+ * of the calibration process.
+ */
+ debug("MMDC registers updated from calibration\n");
+ debug("Read DQS gating calibration:\n");
+ debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0));
+ debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1));
+ debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));
+ debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));
+ debug("Read calibration:\n");
+ debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl));
+ debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));
+ debug("Write calibration:\n");
+ debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl));
+ debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));
+
+ /*
+ * Registers below are for debugging purposes. These print out
+ * the upper and lower boundaries captured during
+ * read DQS gating calibration.
+ */
+ debug("Status registers bounds for read DQS gating:\n");
+ debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));
+ debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
+ debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
+ debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
+ debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
+ debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
+ debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
+ debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
+
+ debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
+
+ return errors;
+}
+#endif
+
#if defined(CONFIG_MX6SX)
/* Configure MX6SX mmdc iomux */
void mx6sx_dram_iocfg(unsigned width,
return 0;
}
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return CONFIG_SYS_MMC_ENV_DEV;
+}
+
+int mmc_get_env_dev(void)
+{
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ u32 soc_sbmr = readl(&src_regs->sbmr1);
+ u32 bootsel;
+ int devno;
+
+ /*
+ * Refer to
+ * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
+ * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
+ * i.MX6SL/SX/UL has same layout.
+ */
+ bootsel = (soc_sbmr & 0x000000FF) >> 6;
+
+ /* If not boot from sd/mmc, use default value */
+ if (bootsel != 1)
+ return CONFIG_SYS_MMC_ENV_DEV;
+
+ /* BOOT_CFG2[3] and BOOT_CFG2[4] */
+ devno = (soc_sbmr & 0x00001800) >> 11;
+
+ return board_mmc_get_env_dev(devno);
+}
+#endif
+
int board_postclk_init(void)
{
set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
struct fuse_bank4_regs *fuse =
(struct fuse_bank4_regs *)bank->fuse_regs;
- u32 value = readl(&fuse->mac_addr_high);
- mac[0] = (value >> 8);
- mac[1] = value ;
-
- value = readl(&fuse->mac_addr_low);
- mac[2] = value >> 24 ;
- mac[3] = value >> 16 ;
- mac[4] = value >> 8 ;
- mac[5] = value ;
+ if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) &&
+ dev_id == 1) {
+ u32 value = readl(&fuse->mac_addr2);
+ mac[0] = value >> 24 ;
+ mac[1] = value >> 16 ;
+ mac[2] = value >> 8 ;
+ mac[3] = value ;
+
+ value = readl(&fuse->mac_addr1);
+ mac[4] = value >> 24 ;
+ mac[5] = value >> 16 ;
+
+ } else {
+ u32 value = readl(&fuse->mac_addr1);
+ mac[0] = (value >> 8);
+ mac[1] = value ;
+
+ value = readl(&fuse->mac_addr0);
+ mac[2] = value >> 24 ;
+ mac[3] = value >> 16 ;
+ mac[4] = value >> 8 ;
+ mac[5] = value ;
+ }
}
#endif
return boot_dev;
}
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return CONFIG_SYS_MMC_ENV_DEV;
+}
+
+int mmc_get_env_dev(void)
+{
+ struct bootrom_sw_info **p =
+ (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
+ int devno = (*p)->boot_dev_instance;
+ u8 boot_type = (*p)->boot_dev_type;
+
+ /* If not boot from sd/mmc, use default value */
+ if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
+ return CONFIG_SYS_MMC_ENV_DEV;
+
+ return board_mmc_get_env_dev(devno);
+}
+#endif
+
void s_init(void)
{
#if !defined CONFIG_SPL_BUILD
sun9i-a80-cubieboard4.dtb
dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
- vf610-colibri.dtb
+ vf610-colibri.dtb \
+ vf610-twr.dtb \
+ pcm052.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
k2l-evm.dtb \
--- /dev/null
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "vf.dtsi"
+
+/ {
+ model = "Phytec phyCORE-Vybrid";
+ compatible = "phytec,pcm052", "fsl,vf610";
+
+ choosen {
+ stdout-path = &uart1;
+ };
+
+};
+
+&uart1 {
+ status = "okay";
+};
* Copyright 2014 Toradex AG
*
* SPDX-License-Identifier: GPL-2.0+ or X11
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
*/
#include "vf.dtsi"
+/ {
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
&dspi1 {
status = "okay";
bus-num = <1>;
spi-max-frequency = <50000000>;
};
};
+
+&uart0 {
+ status = "okay";
+};
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+ or X11
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
*/
/include/ "skeleton.dtsi"
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
spi0 = &dspi0;
spi1 = &dspi1;
};
#size-cells = <1>;
ranges;
+ uart0: serial@40027000 {
+ compatible = "fsl,vf610-lpuart";
+ reg = <0x40027000 0x1000>;
+ status = "disabled";
+ };
+
+ uart1: serial@40028000 {
+ compatible = "fsl,vf610-lpuart";
+ reg = <0x40028000 0x1000>;
+ status = "disabled";
+ };
+
+ uart2: serial@40029000 {
+ compatible = "fsl,vf610-lpuart";
+ reg = <0x40029000 0x1000>;
+ status = "disabled";
+ };
+
+ uart3: serial@4002a000 {
+ compatible = "fsl,vf610-lpuart";
+ reg = <0x4002a000 0x1000>;
+ status = "disabled";
+ };
+
dspi0: dspi0@4002c000 {
#address-cells = <1>;
#size-cells = <0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
+
+ uart4: serial@400a9000 {
+ compatible = "fsl,vf610-lpuart";
+ reg = <0x400a9000 0x1000>;
+ status = "disabled";
+ };
+
+ uart5: serial@400aa000 {
+ compatible = "fsl,vf610-lpuart";
+ reg = <0x400aa000 0x1000>;
+ status = "disabled";
+ };
+
};
};
};
* Copyright 2014 Toradex AG
*
* SPDX-License-Identifier: GPL-2.0+ or X11
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
*/
/dts-v1/;
* Copyright 2014 Toradex AG
*
* SPDX-License-Identifier: GPL-2.0+ or X11
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
*/
/dts-v1/;
--- /dev/null
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "vf.dtsi"
+
+/ {
+ model = "VF610 Tower Board";
+ compatible = "fsl,vf610-twr", "fsl,vf610";
+
+ choosen {
+ stdout-path = &uart1;
+ };
+
+};
+
+&uart1 {
+ status = "okay";
+};
u32 rsvd7[3];
};
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
struct fuse_bank4_regs {
u32 sjc_resp_low;
u32 rsvd0[3];
u32 sjc_resp_high;
u32 rsvd1[3];
- u32 mac_addr_low;
+ u32 mac_addr0;
u32 rsvd2[3];
- u32 mac_addr_high;
+ u32 mac_addr1;
u32 rsvd3[3];
- u32 mac_addr2;
+ u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
u32 rsvd4[7];
u32 gp1;
u32 rsvd5[3];
u32 gp2;
u32 rsvd6[3];
};
-#else
-struct fuse_bank4_regs {
- u32 sjc_resp_low;
- u32 rsvd0[3];
- u32 sjc_resp_high;
- u32 rsvd1[3];
- u32 mac_addr_low;
- u32 rsvd2[3];
- u32 mac_addr_high;
- u32 rsvd3[0xb];
- u32 gp1;
- u32 rsvd4[3];
- u32 gp2;
- u32 rsvd5[3];
-};
-#endif
struct aipstz_regs {
u32 mprot0;
const struct mx6sl_iomux_ddr_regs *,
const struct mx6sl_iomux_grp_regs *);
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+int mmdc_do_write_level_calibration(void);
+int mmdc_do_dqs_calibration(void);
+#endif
+
/* configure mx6 mmdc registers */
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
const struct mx6_mmdc_calibration *,
{USDHC4_BASE_ADDR},
};
+int board_mmc_get_env_dev(int devno)
+{
+ return devno - 2;
+}
+
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
+int board_mmc_get_env_dev(int devno)
+{
+ return devno - 1;
+}
+
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
/* 8 bit bus width */
- {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
{NULL, 0},
};
#endif
/* Reset LAN8720 PHY */
gpio_direction_output(ETH_PHY_RESET , 0);
- udelay(1000);
+ udelay(25000);
gpio_set_value(ETH_PHY_RESET, 1);
}
{USDHC3_BASE_ADDR, 0, 4},
};
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
--- /dev/null
+if TARGET_MX6SXSABREAUTO
+
+config SYS_BOARD
+ default "mx6sxsabreauto"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "mx6sxsabreauto"
+
+endif
--- /dev/null
+MX6SXSABREAUTO BOARD
+M: Fabio Estevam <fabio.estevam@nxp.com>
+S: Maintained
+F: board/freescale/mx6sxsabreauto/
+F: include/configs/mx6sxsabreauto.h
+F: configs/mx6sxsabreauto_defconfig
--- /dev/null
+# (C) Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6sxsabreauto.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x000c0000
+DATA 4 0x020e05fc 0x00000000
+
+/* Clock */
+DATA 4 0x020e032c 0x00000030
+
+/* Address */
+DATA 4 0x020e0300 0x00000030
+DATA 4 0x020e02fc 0x00000030
+DATA 4 0x020e05f4 0x00000030
+
+/* Control */
+DATA 4 0x020e0340 0x00000030
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000030
+DATA 4 0x020e0314 0x00000030
+DATA 4 0x020e0614 0x00000030
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00000030
+DATA 4 0x020e0334 0x00000030
+DATA 4 0x020e0338 0x00000030
+DATA 4 0x020e033c 0x00000030
+
+/* Data */
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000030
+DATA 4 0x020e0610 0x00000030
+DATA 4 0x020e061c 0x00000030
+DATA 4 0x020e0620 0x00000030
+DATA 4 0x020e02ec 0x00000030
+DATA 4 0x020e02f0 0x00000030
+DATA 4 0x020e02f4 0x00000030
+DATA 4 0x020e02f8 0x00000030
+
+/* Calibrations - ZQ */
+DATA 4 0x021b0800 0xa1390003
+
+/* Write leveling */
+DATA 4 0x021b080c 0x002C003D
+DATA 4 0x021b0810 0x00110046
+
+/* DQS Read Gate */
+DATA 4 0x021b083c 0x4160016C
+DATA 4 0x021b0840 0x013C016C
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x46424446
+DATA 4 0x021b0850 0x3A3C3C3A
+
+DATA 4 0x021b08c0 0x2492244A
+
+/* read data bit delay */
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+/* Complete calibration by forced measurement */
+DATA 4 0x021b08b8 0x00000800
+
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x676b52f3
+DATA 4 0x021b0010 0xb66d8b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00011740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000007f
+DATA 4 0x021b0000 0x85190000
+
+/* Initialize MT41K256M16HA-125 - MR2 */
+DATA 4 0x021b001c 0x04008032
+/* MR3 */
+DATA 4 0x021b001c 0x00008033
+/* MR1 */
+DATA 4 0x021b001c 0x00068031
+/* MR0 */
+DATA 4 0x021b001c 0x05208030
+/* DDR device ZQ calibration */
+DATA 4 0x021b001c 0x04008040
+
+/* Final DDR setup, before operation start */
+DATA 4 0x021b0020 0x00000800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b0004 0x0002556d
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
--- /dev/null
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * Author: Ye Li <ye.li@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/io.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-fsl.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
+
+#define I2C_PMIC 1
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+ PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+/*Define for building port exp gpio, pin starts from 0*/
+#define PORTEXP_IO_NR(chip, pin) \
+ ((chip << 5) + pin)
+
+/*Get the chip addr from a ioexp gpio*/
+#define PORTEXP_IO_TO_CHIP(gpio_nr) \
+ (gpio_nr >> 5)
+
+/*Get the pin number from a ioexp gpio*/
+#define PORTEXP_IO_TO_PIN(gpio_nr) \
+ (gpio_nr & 0x1f)
+
+#define CPU_PER_RST_B PORTEXP_IO_NR(0x30, 4)
+#define STEER_ENET PORTEXP_IO_NR(0x32, 2)
+
+static int port_exp_direction_output(unsigned gpio, int value)
+{
+ int ret;
+
+ i2c_set_bus_num(2);
+ ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (value << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* CD pin */
+ MX6_PAD_USB_H_DATA__GPIO7_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* RST_B, used for power reset cycle */
+ MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* CD pin */
+ MX6_PAD_USB_H_STROBE__GPIO7_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec2_pads[] = {
+ MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
+
+ return enable_fec_anatop_clock(1, ENET_125MHZ);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
+ setup_fec();
+
+ ret = fecmxc_initialize_multi(bis, 1,
+ CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+ if (ret)
+ printf("FEC%d MXC: %s:failed\n", 1, __func__);
+
+ return ret;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /*
+ * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
+ * Phy control debug reg 0
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ /* rgmii tx clock delay enable */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C2 for PMIC */
+struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
+ .gp = IMX_GPIO_NR(1, 2),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
+ .gp = IMX_GPIO_NR(1, 3),
+ },
+};
+
+/* I2C3 for IO Expander */
+struct i2c_pads_info i2c_pad_info3 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL4__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_KEY_COL4__GPIO2_IO_14 | PC,
+ .gp = IMX_GPIO_NR(2, 14),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW4__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_KEY_ROW4__GPIO2_IO_19 | PC,
+ .gp = IMX_GPIO_NR(2, 19),
+ },
+};
+
+int power_init_board(void)
+{
+ struct pmic *p;
+
+ p = pfuze_common_init(I2C_PMIC);
+ if (!p)
+ return -ENODEV;
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ /* OGT1 */
+ MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG2 */
+ MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ /* Set Power polarity */
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 10)
+#define USDHC3_RST_GPIO IMX_GPIO_NR(2, 11)
+#define USDHC4_CD_GPIO IMX_GPIO_NR(7, 11)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = !gpio_get_value(USDHC4_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC3
+ * mmc1 USDHC4
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+
+ /* This starts a power cycle for UHS-I. Need to set steer to B0 to A*/
+ gpio_direction_output(USDHC3_RST_GPIO, 0);
+ udelay(1000); /* need 1ms at least */
+ gpio_direction_output(USDHC3_RST_GPIO, 1);
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ gpio_direction_input(USDHC4_CD_GPIO);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1 \
+ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+ MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+
+int board_qspi_init(void)
+{
+ /* Set the iomux */
+ imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+ ARRAY_SIZE(quadspi_pads));
+
+ /* Set the clock */
+ enable_qspi_clk(0);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+iomux_v3_cfg_t gpmi_pads[] = {
+ MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
+ MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+ setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_MXC
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+#endif
+
+ /* Reset CPU_PER_RST_B signal for enet phy and PCIE */
+ port_exp_direction_output(CPU_PER_RST_B, 0);
+ udelay(500);
+ port_exp_direction_output(CPU_PER_RST_B, 1);
+
+ /* Set steering signal to L for selecting B0 */
+ port_exp_direction_output(STEER_ENET, 0);
+
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+ board_qspi_init();
+#endif
+
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ {"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
+ {"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+ {"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6SX SABRE AUTO\n");
+
+ return 0;
+}
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE)
+#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
+int board_mmc_get_env_dev(int devno)
+{
+ return devno - 1;
+}
+
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
}
#endif
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+ MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* Use GPIO for Brightness adjustment, duty cycle = period */
+ MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static int setup_lcd(void)
+{
+ enable_lcdif_clock(LCDIF1_BASE_ADDR);
+
+ imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+ /* Reset the LCD */
+ gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
+ udelay(500);
+ gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
+
+ /* Set Brightness to high */
+ gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
+
+ return 0;
+}
+#endif
+
int board_init(void)
{
/* Address of boot parameters */
board_qspi_init();
#endif
+#ifdef CONFIG_VIDEO_MXS
+ setup_lcd();
+#endif
+
return 0;
}
{USDHC3_BASE_ADDR},
};
-static int mmc_get_env_devno(void)
+int board_mmc_get_env_dev(int devno)
{
- struct bootrom_sw_info **p =
- (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
+ if (devno == 2)
+ devno--;
- u8 boot_type = (*p)->boot_dev_type;
- u8 dev_no = (*p)->boot_dev_instance;
-
- /* If not boot from sd/mmc, use default value */
- if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
- return CONFIG_SYS_MMC_ENV_DEV;
-
- if (dev_no == 2)
- dev_no--;
-
- return dev_no;
+ return devno;
}
static int mmc_map_to_kernel_blk(int dev_no)
{
char cmd[32];
char mmcblk[32];
- u32 dev_no = mmc_get_env_devno();
+ u32 dev_no = mmc_get_env_dev();
if (!check_mmc_autodetect())
return;
.dram_ras = 0x00000038,
.dram_reset = 0x00000038,
/* SDCKE[0:1]: 100k pull-up */
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
+ .dram_sdcke0 = 0x00000038,
+ .dram_sdcke1 = 0x00000038,
/* SDBA2: pull-up disabled */
.dram_sdba2 = 0x00000000,
/* SDODT[0:1]: 100k pull-up, 40 ohm */
/* Single chip select */
.ncs = 1,
.cs1_mirror = 0,
- .rtt_wr = 1, /* RTT_Wr = RZQ/4 */
- .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
- .walat = 3, /* Write additional latency */
- .ralat = 7, /* Read additional latency */
+ .rtt_wr = 0, /* RTT_Wr = RZQ/4 */
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 0, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rowaddr = 16,
.coladdr = 10,
.pagesz = 2,
- .trcd = 1300,
- .trcmin = 4900,
- .trasmin = 3590,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
};
static void ccgr_init(void)
mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600);
+ /* Perform DDR DRAM calibration */
+ udelay(100);
+ mmdc_do_write_level_calibration();
+ mmdc_do_dqs_calibration();
+
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
if (!ret)
gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
- udelay(1000);
+ udelay(25000);
gpio_set_value(ENET_PHY_RESET_GPIO, 1);
}
CONFIG_ARM=y
CONFIG_TARGET_COLIBRI_VF=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
CONFIG_SYS_PROMPT="Colibri VFxx # "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_SPI=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_VYBRID_GPIO=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
CONFIG_FSL_LPUART=y
+CONFIG_FSL_DSPI=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_COLIBRI_VF=y
-CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
-CONFIG_SYS_PROMPT="Colibri VFxx # "
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DM=y
-CONFIG_NAND_VF610_NFC=y
-CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
-CONFIG_FSL_LPUART=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6SXSABREAUTO=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg,MX6SX"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_ARM=y
CONFIG_TARGET_PCM052=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="pcm052"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND"
+CONFIG_CMD_GPIO=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_VYBRID_GPIO=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_FSL_LPUART=y
CONFIG_ARM=y
CONFIG_TARGET_VF610TWR=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC"
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_VYBRID_GPIO=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_VF610TWR=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND"
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_VYBRID_GPIO=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPI_FLASH=y
-----------------------------------
1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the
- 16 msbs in word 3.
+ 16 msbs in word 3[15:0].
+ For i.MX6SX and i.MX6UL, they have two MAC addresses. The second MAC address
+ is stored in fuse bank 4, with the 16 lsb in word 3[31:16] and the 32 msbs in
+ word 4.
Example:
return 0;
}
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct vybrid_gpio_platdata vybrid_gpio[] = {
- {0, GPIO0_BASE_ADDR, "GPIO0 "},
- {1, GPIO1_BASE_ADDR, "GPIO1 "},
- {2, GPIO2_BASE_ADDR, "GPIO2 "},
- {3, GPIO3_BASE_ADDR, "GPIO3 "},
- {4, GPIO4_BASE_ADDR, "GPIO4 "},
-};
-
-U_BOOT_DEVICES(vybrid_gpio) = {
- { "gpio_vybrid", &vybrid_gpio[0] },
- { "gpio_vybrid", &vybrid_gpio[1] },
- { "gpio_vybrid", &vybrid_gpio[2] },
- { "gpio_vybrid", &vybrid_gpio[3] },
- { "gpio_vybrid", &vybrid_gpio[4] },
-};
-#endif
-
static const struct udevice_id vybrid_gpio_ids[] = {
{ .compatible = "fsl,vf610-gpio" },
{ }
DECLARE_GLOBAL_DATA_PTR;
-struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
-
struct lpuart_serial_platdata {
struct lpuart_fsl *reg;
};
return 0;
}
-#ifndef CONFIG_DM_SERIAL
-static void lpuart_serial_setbrg(void)
-{
- _lpuart_serial_setbrg(base, gd->baudrate);
-}
-
-static int lpuart_serial_getc(void)
-{
- return _lpuart_serial_getc(base);
-}
-
-static void lpuart_serial_putc(const char c)
-{
- _lpuart_serial_putc(base, c);
-}
-
-static int lpuart_serial_tstc(void)
-{
- return _lpuart_serial_tstc(base);
-}
-
-static int lpuart_serial_init(void)
-{
- return _lpuart_serial_init(base);
-}
-
-static struct serial_device lpuart_serial_drv = {
- .name = "lpuart_serial",
- .start = lpuart_serial_init,
- .stop = NULL,
- .setbrg = lpuart_serial_setbrg,
- .putc = lpuart_serial_putc,
- .puts = default_serial_puts,
- .getc = lpuart_serial_getc,
- .tstc = lpuart_serial_tstc,
-};
-#else /* CONFIG_DM_SERIAL */
static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
{
struct lpuart_serial_platdata *plat = dev->platdata;
return _lpuart_serial_init(reg);
}
-#endif /* CONFIG_DM_SERIAL */
#else
+
static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate)
{
u32 clk = CONFIG_SYS_CLK_FREQ;
return 0;
}
-#ifndef CONFIG_DM_SERIAL
-static void lpuart32_serial_setbrg(void)
-{
- _lpuart32_serial_setbrg(base, gd->baudrate);
-}
-
-static int lpuart32_serial_getc(void)
-{
- return _lpuart32_serial_getc(base);
-}
-
-static void lpuart32_serial_putc(const char c)
-{
- _lpuart32_serial_putc(base, c);
-}
-
-static int lpuart32_serial_tstc(void)
-{
- return _lpuart32_serial_tstc(base);
-}
-
-static int lpuart32_serial_init(void)
-{
- return _lpuart32_serial_init(base);
-}
-
-static struct serial_device lpuart32_serial_drv = {
- .name = "lpuart32_serial",
- .start = lpuart32_serial_init,
- .stop = NULL,
- .setbrg = lpuart32_serial_setbrg,
- .putc = lpuart32_serial_putc,
- .puts = default_serial_puts,
- .getc = lpuart32_serial_getc,
- .tstc = lpuart32_serial_tstc,
-};
-#else /* CONFIG_DM_SERIAL */
static int lpuart32_serial_setbrg(struct udevice *dev, int baudrate)
{
struct lpuart_serial_platdata *plat = dev->platdata;
return _lpuart32_serial_init(reg);
}
-#endif /* CONFIG_DM_SERIAL */
-#endif
-
-#ifndef CONFIG_DM_SERIAL
-void lpuart_serial_initialize(void)
-{
-#ifdef CONFIG_LPUART_32B_REG
- serial_register(&lpuart32_serial_drv);
-#else
- serial_register(&lpuart_serial_drv);
-#endif
-}
+#endif /* CONFIG_LPUART_32B_REG */
-__weak struct serial_device *default_serial_console(void)
-{
-#ifdef CONFIG_LPUART_32B_REG
- return &lpuart32_serial_drv;
-#else
- return &lpuart_serial_drv;
-#endif
-}
-#else /* CONFIG_DM_SERIAL */
static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
{
struct lpuart_serial_platdata *plat = dev->platdata;
.flags = DM_FLAG_PRE_RELOC,
};
#endif /* CONFIG_LPUART_32B_REG */
-#endif /* CONFIG_DM_SERIAL */
#define CONFIG_BOARD_EARLY_INIT_F
-#define LPUART_BASE UART0_BASE
-
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_VERSION_VARIABLE
-#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_CMD_ASKENV
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
-/* GPIO support */
-#define CONFIG_DM_GPIO
-#define CONFIG_VYBRID_GPIO
-
/* Dynamic MTD partition support */
#define CONFIG_CMD_MTDPARTS /* Enable 'mtdparts' command line support */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_CMD_USB_MASS_STORAGE
-/* Enable SPI support */
-#ifdef CONFIG_OF_CONTROL
-#define CONFIG_DM_SPI
-#define CONFIG_CMD_SPI
-#endif
-
#endif /* __CONFIG_H */
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RMII
-#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SX Sabreauto board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=imx6sx-sabreauto.dtb\0" \
+ "fdt_addr=0x88000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
+
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE SZ_2G
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
+/* NAND flash command */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+
+/* Network */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+
+#define IMX_FEC_BASE ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x0
+
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_CMD_TIME
+
+#define CONFIG_FSL_QSPI
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SYS_FSL_QSPI_AHB
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 40000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define FSL_QSPI_FLASH_SIZE SZ_32M
+#define FSL_QSPI_FLASH_NUM 2
+#endif
+
+#define CONFIG_ENV_OFFSET (8 * SZ_64K)
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/
+#endif
+
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
+
+#endif /* __CONFIG_H */
"fdt_addr=0x88000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
+ "videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \
"mmcdev=2\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
#define FSL_QSPI_FLASH_NUM 2
#endif
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR
+#endif
+#endif
+
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_BOARD_EARLY_INIT_F
-#define LPUART_BASE UART1_BASE
-
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_UART_PORT (1)
#define CONFIG_BAUDRATE 115200
#undef CONFIG_CMD_IMLS
#define CONFIG_BOARD_EARLY_INIT_F
-#define LPUART_BASE UART1_BASE
-
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_UART_PORT (1)
#define CONFIG_BAUDRATE 115200
/* NAND support */
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine dtb to use; fi; \0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxe_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"ramdisk_addr_r=0x13000000\0" \
"ramdiskaddr=0x13000000\0" \
"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
cb = (struct mx28_sd_config_block *)buf;
- cb->signature = htole32(0x00112233);
- cb->primary_boot_tag = htole32(0x1);
- cb->secondary_boot_tag = htole32(0x1);
- cb->num_copies = htole32(1);
- cb->drv_info[0].chip_num = htole32(0x0);
- cb->drv_info[0].drive_type = htole32(0x0);
- cb->drv_info[0].tag = htole32(0x1);
- cb->drv_info[0].first_sector_number = htole32(sd_sector + 4);
- cb->drv_info[0].sector_count = htole32((size - 4) / 512);
+ cb->signature = cpu_to_le32(0x00112233);
+ cb->primary_boot_tag = cpu_to_le32(0x1);
+ cb->secondary_boot_tag = cpu_to_le32(0x1);
+ cb->num_copies = cpu_to_le32(1);
+ cb->drv_info[0].chip_num = cpu_to_le32(0x0);
+ cb->drv_info[0].drive_type = cpu_to_le32(0x0);
+ cb->drv_info[0].tag = cpu_to_le32(0x1);
+ cb->drv_info[0].first_sector_number = cpu_to_le32(sd_sector + 4);
+ cb->drv_info[0].sector_count = cpu_to_le32((size - 4) / 512);
wr_size = write(outfd, buf, size);
if (wr_size != size) {
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