]> git.sur5r.net Git - openocd/commitdiff
targets: fix target_type name for Cortex-A targets
authorPaul Fertser <fercerpav@gmail.com>
Thu, 23 May 2013 11:20:45 +0000 (15:20 +0400)
committerSpencer Oliver <spen@spen-soft.co.uk>
Tue, 28 May 2013 08:48:45 +0000 (08:48 +0000)
Commit d9ba56c295f057e716519a798bf9cdb4898c24f4 did a bunch of
renaming of cortex_a8 to cortex_a, including the names in config
files. However that introduced a regression as the name in target_type
struct remained unchanged.

This adds the last missing bit: actual renaming of the target name as
understood by OpenOCD.

Also change the (hopefully) last instance of using it in the supplied
config files, namely from imx6.cfg.

Change-Id: Ib9289fc6d946630133ec6e36c20015ccb50acf61
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1420
Tested-by: jenkins
Reviewed-by: Chris Johns <chrisj@rtems.org>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
src/target/cortex_a.c
tcl/target/imx6.cfg

index 2b5510f57f939d601471f4973b70bc1f27ce7b3c..7788ada6fef2c5efd88190b62ba5c24f10202639 100644 (file)
@@ -2756,7 +2756,8 @@ static const struct command_registration cortex_a8_command_handlers[] = {
 };
 
 struct target_type cortexa8_target = {
-       .name = "cortex_a8",
+       .name = "cortex_a",
+       .deprecated_name = "cortex_a8",
 
        .poll = cortex_a8_poll,
        .arch_state = armv7a_arch_state,
index 707bab84cc85be57215e9edb533bb5b3b281a22d..292b1148e49fc8f64c4c8af0d65736ca2d9ee4cb 100644 (file)
@@ -37,7 +37,7 @@ jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
 # core 2  -  0x82154000
 # core 3  -  0x82156000
 set _TARGETNAME $_CHIPNAME.cpu.0
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
         -coreid 0 -dbgbase 0x82150000
 
 # some TCK cycles are required to activate the DEBUG power domain
@@ -45,7 +45,7 @@ jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
 
 proc imx6_dbginit {target} {
         # General Cortex A8/A9 debug initialisation
-        cortex_a8 dbginit
+        cortex_a dbginit
 }
 
 # Slow speed to be sure it will work