First version of the MicroBlaze demo with the full Ethernet IP. The Ethernet driver...

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1569 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/data/freertos.mss b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/data/freertos.mss
new file mode 100644 (file)
index 0000000..330c308
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/data/freertos.mss
@@ -0,0 +1,12 @@
+
+PARAMETER VERSION = 2.2.0
+
+BEGIN OS
+ PARAMETER OS_NAME = freertos
+ PARAMETER STDIN =  *
+ PARAMETER STDOUT = *
+ PARAMETER SYSTMR_SPEC = true
+ PARAMETER SYSTMR_DEV = *
+ PARAMETER SYSINTC_SPEC = *
+END
+

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/data/freertos_v2_1_0.mld b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/data/freertos_v2_1_0.mld
new file mode 100644 (file)
index 0000000..123cd4a
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/data/freertos_v2_1_0.mld
@@ -0,0 +1,101 @@
+##############################################################################
+#
+# (c) Copyright 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information of Xilinx, Inc.
+# and is protected under U.S. and international copyright and other
+# intellectual property laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any rights to the
+# materials distributed herewith. Except as otherwise provided in a valid
+# license issued to you by Xilinx, and to the maximum extent permitted by
+# applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+# FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+# IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+# MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+# and (2) Xilinx shall not be liable (whether in contract or tort, including
+# negligence, or under any other theory of liability) for any loss or damage
+# of any kind or nature related to, arising under or in connection with these
+# materials, including for any direct, or any indirect, special, incidental,
+# or consequential loss or damage (including loss of data, profits, goodwill,
+# or any type of loss or damage suffered as a result of any action brought by
+# a third party) even if such damage or loss was reasonably foreseeable or
+# Xilinx had been advised of the possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-safe, or for use in
+# any application requiring fail-safe performance, such as life-support or
+# safety devices or systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any other applications
+# that could lead to death, personal injury, or severe property or
+# environmental damage (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and liability of any use of
+# Xilinx products in Critical Applications, subject only to applicable laws
+# and regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+# AT ALL TIMES.
+#
+# This file is part of Xilkernel.
+#
+# $Id: xilkernel_v2_1_0.mld,v 1.1.2.4 2010/12/10 07:27:08 svemula Exp $
+###############################################################################
+
+OPTION psf_version = 2.1.0 ; 
+BEGIN OS freertos
+               
+  OPTION DRC = kernel_drc ; 
+  OPTION SUPPORTED_PERIPHERALS = (microblaze);
+  OPTION COPYFILES = all;      
+  OPTION DEPENDS = (standalone_v3_01_a);
+  OPTION APP_LINKER_FLAGS = "-Wl,--start-group,-lxil,-lfreertos,-lgcc,-lc,--end-group";
+
+  OPTION DESC = "FreeRTOS is a popular lightweight kernel."
+
+  # STDIN/STDOUT
+  PARAM name = stdin, type = peripheral_instance, requires_interface = stdin, default=none, desc = "Specify the instance name of the standard input peripheral";
+  PARAM name = stdout, type = peripheral_instance, requires_interface = stdout, default=none, desc = "Specify the instance name of the standard output peripheral";
+
+  # System timer specification
+  PARAM name = systmr_interval, type = int, default = 10, desc = "Specify the time interval for each kernel tick (in milliseconds). This controls the CPU budget for each process. If the timer is fit_timer, then this parameter is automatically determined";        
+
+  # System interrupt controller specification
+  # PARAM name = sysintc_spec, type = peripheral_instance, range = (opb_intc, xps_intc, dcr_intc, axi_intc), default = none, desc = "Specify the instance name of the interrupt controller device driving system interrupts";
+
+  BEGIN CATEGORY kernel_behavior
+    PARAM name = kernel_behavior, type = bool, default = true, desc = "Parameters relating to the kernel behavior", permit = user;
+    PARAM name = use_preemption, type = bool, default = true, desc = "Set to true to use the preemptive scheduler, or false to use the cooperative scheduler.";
+    PARAM name = idle_yield, type = bool, default = true, desc = "Set to true if the Idle task should yield if another idle priority task is able to run, or false if the idle task should always use its entire time slice unless it is preempted.";
+    PARAM name = max_priorities, type = int, default = 4, desc = "The number of task priorities that will be available.  Priorities can be assigned from zero to (max_priorities - 1)";
+    PARAM name = minimal_stack_size, type = int, default = 120, desc = "The size of the stack allocated to the Idle task. Also used by standard demo and test tasks found in the main FreeRTOS download.";
+    PARAM name = total_heap_size, type = int, default = 65536, desc = "Only used if heap_1.c or heap_2.c is included in the project.  Sets the amount of RAM reserved for use by the kernel - used when tasks, queues and semaphores are created.";
+    PARAM name = max_task_name_len, type = int, default = 8, desc = "The maximum number of characters that can be in the name of a task.";
+  END CATEGORY
+  
+  BEGIN CATEGORY kernel_features
+       PARAM name = kernel_features, type = bool, default = true, desc = "Include or exclude kernel features", permit = user;
+       PARAM name = use_mutexes, type = bool, default = true, desc = "Set to true to include mutex functionality, or false to exclude mutex functionality.";
+       PARAM name = use_recursive_mutexes, type = bool, default = true, desc = "Set to true to include recursive mutex functionality, or false to exclude recursive mutex functionality.";
+       PARAM name = use_counting_semaphores, type = bool, default = true, desc = "Set to true to include counting semaphore functionality, or false to exclude recursive mutex functionality.";
+       PARAM name = queue_registry_size, type = int, default = 10, desc = "The maximum number of queues that can be registered at any one time. Registered queues can be viewed in the kernel aware debugger plug-in.";
+       PARAM name = use_trace_facility, type = bool, default = true, desc = "Set to true to include the legacy trace functionality, and a few other features.  traceMACROS are the preferred method of tracing now.";
+  END CATEGORY
+  
+  BEGIN CATEGORY hook_functions
+       PARAM name = hook_functions, type = bool, default = true, desc = "Include or exclude application defined hook (callback) functions.  Callback functions must be defined by the application that is using FreeRTOS", permit = user;
+    PARAM name = use_idle_hook, type = bool, default = false, desc = "Set to true for the kernel to call vApplicationIdleHook() on each iteration of the idle task.  The application must provide an implementation of vApplicationIdleHook().";
+    PARAM name = use_tick_hook, type = bool, default = false, desc = "Set to true for the kernel to call vApplicationTickHook() during each tick interrupt.  The application must provide an implementation of vApplicationTickHook().";
+       PARAM name = use_malloc_failed_hook, type = bool, default = true, desc = "Only used if heap_1.c, heap_2.c or heap_3.c is included in the project.  Set to true for the kernel to call vApplicationMallocFailedHookHook() if there is insufficient FreeRTOS heap available for a task, queue or semaphore to be created.  The application must provide an implementation of vApplicationMallocFailedHook().";
+       PARAM name = check_for_stack_overflow, type = int, default = 2, desc = "Set to 1 to include basic run time task stack checking.  Set to 2 to include more comprehensive run time task stack checking.";
+  END CATEGORY
+
+  BEGIN CATEGORY software_timers
+       PARAM name = software_timers, type = bool, default = true, desc = "Options relating to the software timers functionality", permit = user;
+       PARAM name = use_timers, type = bool, default = true, desc = "Set to true to include software timer functionality, or false to exclude software timer functionality";
+       PARAM name = timer_task_priority, type = string, default = "(configMAX_PRIORITIES - 1)", desc = "The priority at which the software timer service/daemon task will execute.";
+       PARAM name = timer_command_queue_length, type = int, default = 10, desc = "The number of commands the timer command queue can hold at any one time.";
+       PARAM name = timer_task_stack_depth, type = string, default = "(configMINIMAL_STACK_SIZE), desc = "The size of the stack allocated to the timer service/daemon task.";
+  END CATEGORY
+ 
+END OS 

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/data/freertos_v2_1_0.tcl b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/data/freertos_v2_1_0.tcl
new file mode 100644 (file)
index 0000000..c7067eb
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/data/freertos_v2_1_0.tcl
@@ -0,0 +1,806 @@
+##############################################################################
+#
+# (c) Copyright 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information of Xilinx, Inc.
+# and is protected under U.S. and international copyright and other
+# intellectual property laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any rights to the
+# materials distributed herewith. Except as otherwise provided in a valid
+# license issued to you by Xilinx, and to the maximum extent permitted by
+# applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+# FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+# IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+# MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+# and (2) Xilinx shall not be liable (whether in contract or tort, including
+# negligence, or under any other theory of liability) for any loss or damage
+# of any kind or nature related to, arising under or in connection with these
+# materials, including for any direct, or any indirect, special, incidental,
+# or consequential loss or damage (including loss of data, profits, goodwill,
+# or any type of loss or damage suffered as a result of any action brought by
+# a third party) even if such damage or loss was reasonably foreseeable or
+# Xilinx had been advised of the possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-safe, or for use in
+# any application requiring fail-safe performance, such as life-support or
+# safety devices or systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any other applications
+# that could lead to death, personal injury, or severe property or
+# environmental damage (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and liability of any use of
+# Xilinx products in Critical Applications, subject only to applicable laws
+# and regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+# AT ALL TIMES.
+#
+# This file is part of FreeRTOS.
+#
+# $Id: freertos_v2_1_0.tcl,v 1.1.2.8 2010/12/10 07:27:08 svemula Exp $
+###############################################################################
+
+# standalone bsp version. set this to the latest "ACTIVE" version.
+set standalone_version standalone_v3_01_a
+
+proc kernel_drc {os_handle} {
+    set sw_proc_handle [xget_libgen_proc_handle]
+    set hw_proc_handle [xget_handle $sw_proc_handle "IPINST"]
+    set proctype [xget_value $hw_proc_handle "OPTION" "IPNAME"]
+    set compiler [xget_value $sw_proc_handle "PARAMETER" "COMPILER"]
+
+    # check for valid compiler
+    if { [string first "mb-gcc" $compiler] == 0 && [string first "mb-g++" $compiler] == 0} {
+        error "Wrong compiler requested. FreeRTOS can be compiled only with the GNU compiler for MicroBlaze." "" "mdt_error"
+    }
+
+    # check for valid stdio parameters
+    set stdin [xget_value $os_handle "PARAMETER" "STDIN"]
+    set stdout [xget_value $os_handle "PARAMETER" "STDOUT"]
+    if { $stdin == "none" || $stdout == "none" } {
+        error "The STDIN/STDOUT parameters are not set. FreeRTOS requires stdin/stdout to be set." "" "mdt_error"
+    }
+
+    # check if the design has a intc
+    set intr_port [xget_value $hw_proc_handle "PORT" "Interrupt"]
+    if { [llength $intr_port] == 0 } {
+        error "CPU has no connection to Interrupt controller." "" "mdt_error"
+    }
+
+    # support only AXI/PLB
+    set interconnect [xget_value $hw_proc_handle "PARAMETER" "C_INTERCONNECT"]
+    if { $interconnect == 1 } {
+        set bus_name [xget_hw_busif_value $hw_proc_handle "DPLB"]
+    } elseif { $interconnect == 2 } {
+        set bus_name [xget_hw_busif_value $hw_proc_handle "M_AXI_DP"]
+    } else {
+        error "FreeRTOS supports Microblaze with only a AXI or PLB interconnect" "" "mdt_error"
+    }
+
+    # obtain handles to all the peripherals in the design
+    set mhs_handle [xget_hw_parent_handle $hw_proc_handle]
+    set slave_ifs [xget_hw_connected_busifs_handle $mhs_handle $bus_name "slave"]
+    set timer_count 0
+    set timer_has_intr 0
+
+    # check for a valid timer
+    foreach if $slave_ifs {
+        set ip_handle [xget_hw_parent_handle $if]
+
+        if {$ip_handle != $hw_proc_handle} {
+            set type [xget_hw_value $ip_handle]
+            if { $type == "xps_timer" || $type == "axi_timer" } {
+                incr timer_count
+                
+                # check if the timer interrupts are enabled
+                set intr_port [xget_value $ip_handle "PORT" "Interrupt"]
+                if { [llength $intr_port] != 0 } {
+                    set timer_has_intr 1
+                }
+            }
+        }
+    }
+
+    if { $timer_count == 0 } {
+        error "FreeRTOS for Microblaze requires an axi_timer or xps_timer. The HW platform doesn't have a valid timer." "" "mdt_error"
+    }
+
+    if { $timer_has_intr == 0 } {
+        error "FreeRTOS for Microblaze requires interrupts enabled for a timer." "" "mdt_error"
+    }
+
+    set systmr_interval_ms [xget_value $os_handle "PARAMETER" "systmr_interval"]
+    if { $systmr_interval_ms <= 0 } {
+        error "Invalid value for parameter systmr_interval specified. Please specify a positive value." "" "mdt_error"
+    }
+
+    ### ToDo: Add DRC specific to FreeRTOS
+}
+
+proc generate {os_handle} {
+
+    variable standalone_version
+
+    set sw_proc_handle [xget_libgen_proc_handle]
+    set hw_proc_handle [xget_handle $sw_proc_handle "IPINST"]
+    set proctype [xget_value $hw_proc_handle "OPTION" "IPNAME"]
+    set procver [xget_value $hw_proc_handle "PARAMETER" "HW_VER"]
+    
+    set need_config_file "false"
+
+    # proctype should be "microblaze"
+    set mbsrcdir  "../${standalone_version}/src/microblaze"
+    set commondir   "../${standalone_version}/src/common"
+    set datadir   "../${standalone_version}/data"
+
+    foreach entry [glob -nocomplain [file join $commondir *]] {
+        file copy -force $entry [file join ".." "${standalone_version}" "src"]
+    }
+    
+    # proctype should be "microblaze"
+    switch -regexp $proctype {
+        "microblaze" { 
+
+            foreach entry [glob -nocomplain [file join $mbsrcdir *]] {
+                if { [string first "microblaze_interrupt_handler" $entry] == -1 } { ;# Do not copy over the Standalone BSP exception handler
+                    file copy -force $entry [file join ".." "${standalone_version}" "src"]
+                }
+            }
+            set need_config_file "true"
+        }
+        "default" {puts "unknown processor type $proctype\n"}
+    }
+
+    # Write the config.make file
+    set makeconfig [open "../standalone_v3_01_a/src/config.make" w]  
+    xprint_generated_header_tcl $makeconfig "Configuration parameters for Standalone Makefile"
+
+    if { $proctype == "microblaze" } {
+        if { [mb_has_exceptions $hw_proc_handle] } {
+            puts $makeconfig "LIBSOURCES = *.s *.c *.S"
+        } else {
+            puts $makeconfig "LIBSOURCES = *.s *.c"
+        }
+    }
+
+    puts $makeconfig "LIBS = standalone_libs"
+    close $makeconfig
+
+    # Remove microblaze directories...
+    file delete -force $mbsrcdir
+
+    # copy required files to the main src directory
+    file copy -force [file join src Source tasks.c] src
+    file copy -force [file join src Source queue.c] src
+    file copy -force [file join src Source list.c] src
+    file copy -force [file join src Source timers.c] src
+    file copy -force [file join src Source portable MemMang heap_3.c] src
+    file copy -force [file join src Source portable GCC MicroBlazeV8 port.c] src
+    file copy -force [file join src Source portable GCC MicroBlazeV8 port_exceptions.c] src
+    file copy -force [file join src Source portable GCC MicroBlazeV8 portasm.S] src
+    file copy -force [file join src Source portable GCC MicroBlazeV8 portmacro.h] src
+    set headers [glob -join ./src/Source/include *.\[h\]]
+    foreach header $headers {
+        file copy -force $header src
+    }
+
+    file delete -force [file join src Source]
+    file delete -force [file join src Source]
+
+    # Handle stdin and stdout
+    xhandle_stdin $os_handle
+    xhandle_stdout $os_handle
+
+    # Create config file for microblaze interrupt handling
+    if {[string compare -nocase $need_config_file "true"] == 0} {
+        xhandle_mb_interrupts
+    }
+
+    # Create config files for Microblaze exception handling
+    if { $proctype == "microblaze" && [mb_has_exceptions $hw_proc_handle] } {
+        xcreate_mb_exc_config_file 
+    }
+
+    # Create bspconfig file
+    set bspcfg_fn [file join ".." "${standalone_version}" "src"  "bspconfig.h"] 
+    file delete $bspcfg_fn
+    set bspcfg_fh [open $bspcfg_fn w]
+    xprint_generated_header $bspcfg_fh "Configurations for Standalone BSP"
+
+    if { $proctype == "microblaze" && [mb_has_pvr $hw_proc_handle] } {
+        
+        set pvr [xget_value $hw_proc_handle "PARAMETER" "C_PVR"]
+        
+        switch $pvr {
+            "0" {
+                puts $bspcfg_fh "#define MICROBLAZE_PVR_NONE"
+            }
+            "1" {
+                puts $bspcfg_fh "#define MICROBLAZE_PVR_BASIC"
+            }
+            "2" {
+                puts $bspcfg_fh "#define MICROBLAZE_PVR_FULL"
+            }
+            "default" {
+                puts $bspcfg_fh "#define MICROBLAZE_PVR_NONE"
+            }
+        }    
+    }
+
+    close $bspcfg_fh
+
+# ToDO: FreeRTOS does not handle the following, refer xilkernel TCL script
+# - MPU settings
+
+    set config_file [xopen_new_include_file "./src/FreeRTOSConfig.h" "FreeRTOS Configuration parameters"]
+    puts $config_file "\#include \"xparameters.h\" \n"
+
+    set val [xget_value $os_handle "PARAMETER" "use_preemption"]
+    if {$val == "false"} {
+        xput_define $config_file "configUSE_PREEMPTION" "0"
+    } else {
+        xput_define $config_file "configUSE_PREEMPTION" "1"
+    }
+
+    set val [xget_value $os_handle "PARAMETER" "use_mutexes"]
+    if {$val == "false"} {
+        xput_define $config_file "configUSE_MUTEXES" "0"
+    } else {
+        xput_define $config_file "configUSE_MUTEXES" "1"
+    }
+    
+    set val [xget_value $os_handle "PARAMETER" "use_recursive_mutexes"]
+    if {$val == "false"} {
+        xput_define $config_file "configUSE_RECURSIVE_MUTEXES" "0"
+    } else {
+        xput_define $config_file "configUSE_RECURSIVE_MUTEXES" "1"
+    }
+
+    set val [xget_value $os_handle "PARAMETER" "use_counting_semaphores"]
+    if {$val == "false"} {
+        xput_define $config_file "configUSE_COUNTING_SEMAPHORES" "0"
+    } else {
+        xput_define $config_file "configUSE_COUNTING_SEMAPHORES" "1"
+    }
+
+    set val [xget_value $os_handle "PARAMETER" "use_timers"]
+    if {$val == "false"} {
+        xput_define $config_file "configUSE_TIMERS" "0"
+    } else {
+        xput_define $config_file "configUSE_TIMERS" "1"
+    }
+
+    set val [xget_value $os_handle "PARAMETER" "use_idle_hook"]
+    if {$val == "false"} {
+        xput_define $config_file "configUSE_IDLE_HOOK"    "0"
+    } else {
+        xput_define $config_file "configUSE_IDLE_HOOK"    "1"
+    }
+
+    set val [xget_value $os_handle "PARAMETER" "use_tick_hook"]
+    if {$val == "false"} {
+        xput_define $config_file "configUSE_TICK_HOOK"    "0"
+    } else {
+        xput_define $config_file "configUSE_TICK_HOOK"    "1"
+    }
+
+    set val [xget_value $os_handle "PARAMETER" "use_malloc_failed_hook"]
+    if {$val == "false"} {
+        xput_define $config_file "configUSE_MALLOC_FAILED_HOOK"    "0"
+    } else {
+        xput_define $config_file "configUSE_MALLOC_FAILED_HOOK"    "1"
+    }
+
+    set val [xget_value $os_handle "PARAMETER" "use_trace_facility"]
+    if {$val == "false"} {
+        xput_define $config_file "configUSE_TRACE_FACILITY" "0"
+    } else {
+        xput_define $config_file "configUSE_TRACE_FACILITY" "1"
+    }
+
+    xput_define $config_file "configUSE_16_BIT_TICKS"   "0"
+    xput_define $config_file "configUSE_APPLICATION_TASK_TAG"   "0"
+    xput_define $config_file "configUSE_CO_ROUTINES"    "0"
+
+    # System timer tick rate (Microblaze only. kernel DRC ensures this)
+    set systmr_interval [xget_value $os_handle "PARAMETER" "systmr_interval"]
+    xput_define $config_file "configTICK_RATE_HZ"     $systmr_interval
+
+    set max_priorities [xget_value $os_handle "PARAMETER" "max_priorities"]
+    xput_define $config_file "configMAX_PRIORITIES"   $max_priorities
+    xput_define $config_file "configMAX_CO_ROUTINE_PRIORITIES" "2"
+    
+    set min_stack [xget_value $os_handle "PARAMETER" "minimal_stack_size"]
+    set min_stack [expr [expr $min_stack + 3] & 0xFFFFFFFC]
+    xput_define $config_file "configMINIMAL_STACK_SIZE" $min_stack
+
+    set total_heap_size [xget_value $os_handle "PARAMETER" "total_heap_size"]
+    set total_heap_size [expr [expr $total_heap_size + 3] & 0xFFFFFFFC]
+    xput_define $config_file "configTOTAL_HEAP_SIZE"  $total_heap_size
+
+    set max_task_name_len [xget_value $os_handle "PARAMETER" "max_task_name_len"]
+    xput_define $config_file "configMAX_TASK_NAME_LEN"  $max_task_name_len
+    
+    set val [xget_value $os_handle "PARAMETER" "idle_yield"]
+    if {$val == "false"} {
+        xput_define $config_file "configIDLE_SHOULD_YIELD"  "0"
+    } else {
+        xput_define $config_file "configIDLE_SHOULD_YIELD"  "1"
+    }
+
+    set val [xget_value $os_handle "PARAMETER" "check_for_stack_overflow"]
+    if {$val == "false"} {
+        xput_define $config_file "configCHECK_FOR_STACK_OVERFLOW"  "0"
+    } else {
+        xput_define $config_file "configCHECK_FOR_STACK_OVERFLOW"  "2"
+    }
+    
+    set val [xget_value $os_handle "PARAMETER" "queue_registry_size"]
+    if {$val == "false"} {
+        xput_define $config_file "configQUEUE_REGISTRY_SIZE"  "0"
+    } else {
+        xput_define $config_file "configQUEUE_REGISTRY_SIZE"  "10"
+    }
+
+    xput_define $config_file "configGENERATE_RUN_TIME_STATS"    "0"
+
+    set val [xget_value $os_handle "PARAMETER" "timer_task_priority"]
+    if {$val == "false"} {
+        xput_define $config_file "configTIMER_TASK_PRIORITY"  "0"
+    } else {
+        xput_define $config_file "configTIMER_TASK_PRIORITY"  "10"
+    }
+
+    set val [xget_value $os_handle "PARAMETER" "timer_command_queue_length"]
+    if {$val == "false"} {
+        xput_define $config_file "configTIMER_QUEUE_LENGTH"  "0"
+    } else {
+        xput_define $config_file "configTIMER_QUEUE_LENGTH"  "10"
+    }
+
+    set val [xget_value $os_handle "PARAMETER" "timer_task_stack_depth"]
+    if {$val == "false"} {
+        xput_define $config_file "configTIMER_TASK_STACK_DEPTH"  "0"
+    } else {
+        xput_define $config_file "configTIMER_TASK_STACK_DEPTH"  $min_stack
+    }
+
+    if { [mb_has_exceptions $hw_proc_handle] } {    
+        xput_define $config_file "configINSTALL_EXCEPTION_HANDLERS"  "1"
+    } else {
+        xput_define $config_file "configINSTALL_EXCEPTION_HANDLERS"  "0"
+    }
+
+    xput_define $config_file "configINTERRUPT_CONTROLLER_TO_USE"  "XPAR_INTC_SINGLE_DEVICE_ID"
+
+    xput_define $config_file "INCLUDE_vTaskCleanUpResources" "0"
+    xput_define $config_file "INCLUDE_vTaskDelay"        "1"
+    xput_define $config_file "INCLUDE_vTaskDelayUntil"   "1"
+    xput_define $config_file "INCLUDE_vTaskDelete"       "1"
+    xput_define $config_file "INCLUDE_xTaskGetCurrentTaskHandle"   "1"
+    xput_define $config_file "INCLUDE_xTaskGetIdleTaskHandle"      "1"
+    xput_define $config_file "INCLUDE_xTaskGetSchedulerState"  "1"
+    xput_define $config_file "INCLUDE_xTimerGetTimerTaskHandle"    "1"
+    xput_define $config_file "INCLUDE_uxTaskGetStackHighWaterMark"  "1"
+    xput_define $config_file "INCLUDE_uxTaskPriorityGet" "1"
+    xput_define $config_file "INCLUDE_vTaskPrioritySet"  "1"
+    xput_define $config_file "INCLUDE_xTaskResumeFromISR"  "1"
+    xput_define $config_file "INCLUDE_vTaskSuspend"      "1"
+    xput_define $config_file "INCLUDE_pcTaskNameGet"      "1"
+    xput_define $config_file "INCLUDE_xTaskIdleTaskHandleGet"      "1"
+    xput_define $config_file "INCLUDE_xTimerDaemonTaskHandleGet"      "1"
+
+    # complete the header protectors
+    puts $config_file "\#endif"
+    close $config_file
+}
+
+proc xopen_new_include_file { filename description } {
+    set inc_file [open $filename w]
+    xprint_generated_header $inc_file $description
+    set newfname [string map {. _} [lindex [split $filename {\/}] end]]
+    puts $inc_file "\#ifndef _[string toupper $newfname]"
+    puts $inc_file "\#define _[string toupper $newfname]\n\n"
+    return $inc_file
+}
+
+proc xadd_define { config_file os_handle parameter } {
+    set param_value [xget_value $os_handle "PARAMETER" $parameter]
+    puts $config_file "#define [string toupper $parameter] $param_value\n"
+
+    # puts "creating #define [string toupper $parameter] $param_value\n"
+}
+
+proc xput_define { config_file parameter param_value } {
+    puts $config_file "#define $parameter $param_value\n"
+
+    # puts "creating #define [string toupper $parameter] $param_value\n"
+}
+
+# args field of the array
+proc xadd_extern_fname {initfile oshandle arrayname arg} { 
+
+    set arrhandle [xget_handle $oshandle "ARRAY" $arrayname]
+    set elements [xget_handle $arrhandle "ELEMENTS" "*"]
+    set count 0
+    set max_count [llength $elements]
+
+    foreach ele $elements {
+        incr count
+        set arg_value [xget_value $ele "PARAMETER" $arg]
+        puts $initfile "extern void $arg_value\(\)\;"
+    }
+    puts $initfile ""
+}
+
+# args is variable no - fields of the array
+proc xadd_struct {initfile oshandle structtype structname arrayname args} { 
+
+    set arrhandle [xget_handle $oshandle "ARRAY" $arrayname]
+    set elements [xget_handle $arrhandle "ELEMENTS" "*"]
+    set count 0
+    set max_count [llength $elements]
+    puts $initfile "struct $structtype $structname\[$max_count\] = \{"
+
+    foreach ele $elements {
+       incr count
+       puts -nonewline $initfile "\t\{"
+       foreach field $args {
+           set field_value [xget_value $ele "PARAMETER" $field]
+           # puts "$arrayname ( $count )->$field is $field_value"
+           puts -nonewline $initfile "$field_value"
+           if { $field != [lindex $args end] } {
+               puts -nonewline $initfile ","
+           }
+       }
+       if {$count < $max_count} {
+           puts $initfile "\},"
+       } else {
+           puts $initfile "\}"
+       }
+    }
+    puts $initfile "\}\;"
+}
+
+# return the sum of all the arg field values in arrayname
+proc get_field_sum {oshandle arrayname arg} { 
+
+    set arrhandle [xget_handle $oshandle "ARRAY" $arrayname]
+    set elements [xget_handle $arrhandle "ELEMENTS" "*"]
+    set count 0
+    set max_count [llength $elements]
+  
+    foreach ele $elements {
+       set field_value [xget_value $ele "PARAMETER" $arg]
+       set count [expr $field_value+$count]
+    }
+    return $count
+}
+
+# return the sum of the product of field values in arrayname
+proc get_field_product_sum {oshandle arrayname field1 field2} { 
+
+    set arrhandle [xget_handle $oshandle "ARRAY" $arrayname]
+    set elements [xget_handle $arrhandle "ELEMENTS" "*"]
+    set count 0
+    set max_count [llength $elements]
+
+    foreach ele $elements {
+        set field1_value [xget_value $ele "PARAMETER" $field1]
+        set field2_value [xget_value $ele "PARAMETER" $field2]
+        set incr_value [expr $field1_value*$field2_value]
+        set count [expr $count+$incr_value]
+    }
+    return $count
+}
+
+proc xhandle_mb_interrupts {} {
+
+    set default_interrupt_handler "XNullHandler"
+    set default_arg "XNULL"
+
+    set source_interrupt_handler $default_interrupt_handler
+    set source_handler_arg $default_arg
+    
+    # Handle the interrupt pin
+    set sw_proc_handle [xget_libgen_proc_handle] 
+    set periph [xget_handle $sw_proc_handle "IPINST"]
+    set source_ports [xget_interrupt_sources $periph]
+    if {[llength $source_ports] > 1} {
+        error "Too many interrupting ports on the MicroBlaze.  Should only find 1" "" "libgen_error"
+        return
+    }
+    
+    if {[llength $source_ports] == 1} {
+       set source_port [lindex $source_ports 0]
+       if {[llength $source_port] != 0} {
+           set source_port_name [xget_value $source_port "VALUE"]      
+           set source_periph [xget_handle $source_port "PARENT"]
+           set source_name [xget_value $source_periph "NAME"]
+           set source_driver [xget_sw_driver_handle_for_ipinst $sw_proc_handle $source_name]
+
+           if {[string compare -nocase $source_driver ""] != 0} {
+               set int_array [xget_handle $source_driver "ARRAY" "interrupt_handler"]
+               if {[llength $int_array] != 0} {
+                   set int_array_elems [xget_handle $int_array "ELEMENTS" "*"]
+                   if {[llength $int_array_elems] != 0} {
+                       foreach int_array_elem $int_array_elems {
+                           set int_port [xget_value $int_array_elem "PARAMETER" "int_port"]
+                           if {[llength $int_port] != 0} {
+                               if {[string compare -nocase $int_port $source_port_name] == 0 } {
+                                   set source_interrupt_handler [xget_value $int_array_elem "PARAMETER" "int_handler"]
+                                   set source_handler_arg [xget_value $int_array_elem "PARAMETER" "int_handler_arg"]
+                                   if {[string compare -nocase $source_handler_arg DEVICE_ID] == 0 } {
+                                       set source_handler_arg [xget_name $source_periph "DEVICE_ID"]
+                                   } else {
+                                       if {[string compare -nocase "global" [xget_port_type $source_port]] == 0} {
+                                           set source_handler_arg $default_arg
+                                       } else {
+                                           set source_handler_arg [xget_name $source_periph "C_BASEADDR"]
+                                       }
+                                   }
+                                   break
+                               }
+                           }
+                       }
+                   }
+               }
+           }
+       }
+    }
+    
+    # Generate microblaze_interrupts_g.c file...
+    xcreate_mb_intr_config_file $source_interrupt_handler $source_handler_arg
+    
+}
+
+
+proc xcreate_mb_intr_config_file {handler arg} {
+    
+    set mb_table "MB_InterruptVectorTable"
+
+    set filename [file join "../standalone_v3_01_a/src" "microblaze_interrupts_g.c"] 
+    file delete $filename
+    set config_file [open $filename w]
+
+    xprint_generated_header $config_file "Interrupt Handler Table for MicroBlaze Processor"
+    
+    puts $config_file "#include \"microblaze_interrupts_i.h\""
+    puts $config_file "#include \"xparameters.h\""
+    puts $config_file "\n"
+    puts $config_file [format "extern void %s (void *);" $handler]
+    puts $config_file "\n/*"
+    puts $config_file "* The interrupt handler table for microblaze processor"
+    puts $config_file "*/\n"
+    puts $config_file [format "%sEntry %s\[\] =" $mb_table $mb_table]
+    puts $config_file "\{"
+    puts -nonewline $config_file [format "\{\t%s" $handler]
+    puts -nonewline $config_file [format ",\n\t(void*) %s\}" $arg]
+    puts -nonewline $config_file "\n\};"
+    puts $config_file "\n"
+    close $config_file
+}
+
+
+# -------------------------------------------
+# Tcl procedure xcreate_mb_exc_config file
+# -------------------------------------------
+proc xcreate_mb_exc_config_file { } {
+    
+    set hfilename [file join "src" "microblaze_exceptions_g.h"] 
+    file delete $hfilename
+    set hconfig_file [open $hfilename w]
+
+    xprint_generated_header $hconfig_file "Exception Handling Header for MicroBlaze Processor"
+    
+    puts $hconfig_file "\n"
+
+    set sw_proc_handle [xget_libgen_proc_handle]
+    set hw_proc_handle [xget_handle $sw_proc_handle "IPINST"]
+    set procver [xget_value $hw_proc_handle "PARAMETER" "HW_VER"]
+
+    if { ![mb_has_exceptions $hw_proc_handle]} { ;# NO exceptions are enabled
+        close $hconfig_file              ;# Do not generate any info in either the header or the C file
+        return
+    }
+    
+    puts $hconfig_file "\#define MICROBLAZE_EXCEPTIONS_ENABLED 1"
+    if { [mb_can_handle_exceptions_in_delay_slots $procver] } {
+        puts $hconfig_file "#define MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS"
+    }
+
+    close $hconfig_file
+}
+
+# --------------------------------------
+# Tcl procedure post_generate
+# This proc removes from libxil.a the basic 
+# and standalone BSP versions of 
+# _interrupt_handler and _hw_exception_handler
+# routines
+# --------------------------------------
+proc post_generate {os_handle} {
+    set sw_proc_handle [xget_libgen_proc_handle]
+    set hw_proc_handle [xget_handle $sw_proc_handle "IPINST"]
+    set proctype [xget_value $hw_proc_handle "OPTION" "IPNAME"]
+    set procname [xget_value $hw_proc_handle "NAME"]
+
+    set procdrv [xget_sw_driver_handle_for_ipinst $sw_proc_handle $procname]
+    set archiver [xget_value $procdrv "PARAMETER" "archiver"]
+
+    if {[string compare -nocase $proctype "microblaze"] == 0 } {
+        # Remove _interrupt_handler.o from libxil.a for FreeRTOS
+               set libxil_a [file join .. .. lib libxil.a]
+        exec $archiver -d $libxil_a   _interrupt_handler.o
+
+        # We have linkage problems due to how these platforms are defined. Can't do this right now.  
+        # # Remove _exception_handler.o from libxil.a for FreeRTOS
+        # exec bash -c "$archiver -d ../../lib/libxil.a _exception_handler.o"
+        
+        # Remove _hw_exception_handler.o from libxil.a for microblaze cores with exception support
+        if {[mb_has_exceptions $hw_proc_handle]} {
+            exec $archiver -d ../../lib/libxil.a _hw_exception_handler.o
+        }
+    }
+}
+
+# --------------------------------------
+# Tcl procedure execs_generate
+# This proc removes from libxil.a all 
+# the stuff that we are overriding
+# with xilkernel
+# We currently override,
+#  MicroBlaze
+#   - Dummy _interrupt_hander and _hw_exception_handler 
+#     (in post_generate)
+#  PPC
+#   - xvectors.o; sleep.o (IF config_time is true)
+#  Common to all processors
+#    - errno.o
+# --------------------------------------
+proc execs_generate {os_handle} {
+    set sw_proc_handle [xget_libgen_proc_handle]
+    set hw_proc_handle [xget_handle $sw_proc_handle "IPINST"]
+    set proctype [xget_value $hw_proc_handle "OPTION" "IPNAME"]
+    set procname [xget_value $hw_proc_handle "NAME"]
+
+    set procdrv [xget_sw_driver_handle_for_ipinst $sw_proc_handle $procname]
+    # Remove _interrupt_handler.o from libxil.a for mb-gcc
+    set archiver [xget_value $procdrv "PARAMETER" "archiver"]
+
+    set libxil_a [file join .. .. lib libxil.a]
+#    exec $archiver -d $libxil_a  errno.o
+
+    # We have linkage problems due to how these platforms are defined. Can't do this right now.  
+    # exec "$archiver -d $libxil_a microblaze_interrupt_handler.o"
+}
+
+# --------------------------------------
+# Return true if this MB has 
+# exception handling support
+# --------------------------------------
+proc mb_has_exceptions { hw_proc_handle } {
+   
+    # Check if the following parameters exist on this MicroBlaze's MPD
+    set ee [xget_value $hw_proc_handle "PARAMETER" "C_UNALIGNED_EXCEPTIONS"]
+    if { $ee != "" } {
+        return true
+    }
+
+    set ee [xget_value $hw_proc_handle "PARAMETER" "C_ILL_OPCODE_EXCEPTION"]
+    if { $ee != "" } {
+        return true
+    }
+
+    set ee [xget_value $hw_proc_handle "PARAMETER" "C_IOPB_BUS_EXCEPTION"]
+    if { $ee != "" } {
+        return true
+    }
+
+    set ee [xget_value $hw_proc_handle "PARAMETER" "C_DOPB_BUS_EXCEPTION"]
+    if { $ee != "" } {
+        return true
+    }
+
+    set ee [xget_value $hw_proc_handle "PARAMETER" "C_DIV_BY_ZERO_EXCEPTION"]
+    if { $ee != "" } {
+        return true
+    } 
+
+    set ee [xget_value $hw_proc_handle "PARAMETER" "C_DIV_ZERO_EXCEPTION"]
+    if { $ee != "" } {
+        return true
+    } 
+
+    set ee [xget_value $hw_proc_handle "PARAMETER" "C_FPU_EXCEPTION"]
+    if { $ee != "" } {
+        return true
+    } 
+
+    set ee [xget_value $hw_proc_handle "PARAMETER" "C_USE_MMU"]
+    if { $ee != "" && $ee != 0 } {
+        return true
+    } 
+
+    return false
+}
+
+# --------------------------------------
+# Return true if this MB has 
+# FPU exception handling support
+# --------------------------------------
+proc mb_has_fpu_exceptions { hw_proc_handle } {
+    
+    # Check if the following parameters exist on this MicroBlaze's MPD
+    set ee [xget_value $hw_proc_handle "PARAMETER" "C_FPU_EXCEPTION"]
+    if { $ee != "" } {
+        return true
+    }
+
+    return false
+}
+
+# --------------------------------------
+# Return true if this MB has PVR support
+# --------------------------------------
+proc mb_has_pvr { hw_proc_handle } {
+    
+    # Check if the following parameters exist on this MicroBlaze's MPD
+    set pvr [xget_value $hw_proc_handle "PARAMETER" "C_PVR"]
+    if { $pvr != "" } {
+        return true
+    } 
+
+    return false
+}
+
+# --------------------------------------
+# Return true if MB ver 'procver' has 
+# support for handling exceptions in 
+# delay slots
+# --------------------------------------
+proc mb_can_handle_exceptions_in_delay_slots { procver } {
+    
+    if { [string compare -nocase $procver "5.00.a"] >= 0 } {
+        return true
+    } else {
+        return false
+    }
+}
+
+# --------------------------------------------------------------------------
+# Gets all the handles that are memory controller cores.
+# --------------------------------------------------------------------------
+proc xget_memory_controller_handles { mhs } {
+   set ret_list ""
+
+   # Gets all MhsInsts in the system
+   set mhsinsts [xget_hw_ipinst_handle $mhs "*"]
+
+   # Loop thru each MhsInst and determine if have "ADDR_TYPE = MEMORY" in
+   # the parameters.
+   foreach mhsinst $mhsinsts {
+      # Gets all parameters of the component
+      set params [xget_hw_parameter_handle $mhsinst "*"]
+
+      # Loop thru each param and find tag "ADDR_TYPE = MEMORY"
+      foreach param $params {
+         if {$param == 0} {
+            continue
+         } elseif {$param == ""} {
+            continue
+         }
+         set addrTypeValue [ xget_hw_subproperty_value $param "ADDR_TYPE" ]
+
+         # Found tag! Add MhsInst to list and break to go to next MhsInst
+         if {[string compare -nocase $addrTypeValue "MEMORY"] == 0} {
+            lappend ret_list $mhsinst
+            break
+         }
+      }
+   }
+
+   return $ret_list
+}

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/CreatingTheDirectoryStructure.txt b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/CreatingTheDirectoryStructure.txt
new file mode 100644 (file)
index 0000000..df40ad2
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/CreatingTheDirectoryStructure.txt
@@ -0,0 +1,4 @@
+The necessary files are copied to this BSP directory structure by executing \r
+the CreateProjectDirectoryStructure.bat batch file located in the \r
+FreeRTOS\\Demo\MicroBlaze_Spartan-6_EthernetLite\SDKProjects\RTOSDemoSource\r
+folder.
\ No newline at end of file

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/License/license.txt b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/License/license.txt
new file mode 100644 (file)
index 0000000..e296691
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/License/license.txt
@@ -0,0 +1,435 @@
+The FreeRTOS.org source code is licensed by the modified GNU General Public \r
+License (GPL) text provided below.  The FreeRTOS download also includes \r
+demo application source code, some of which is provided by third parties \r
+AND IS LICENSED SEPARATELY FROM FREERTOS.ORG.  \r
+\r
+For the avoidance of any doubt refer to the comment included at the top\r
+of each source and header file for license and copyright information.\r
+\r
+This is a list of files for which Real Time Engineers Ltd are not the \r
+copyright owner and are NOT COVERED BY THE GPL.\r
+\r
+\r
+1) Various header files provided by silicon manufacturers and tool vendors\r
+   that define processor specific memory addresses and utility macros.\r
+   Permission has been granted by the various copyright holders for these\r
+   files to be included in the FreeRTOS download.  Users must ensure license\r
+   conditions are adhered to for any use other than compilation of the \r
+   FreeRTOS demo applications.\r
+\r
+2) The uIP TCP/IP stack the copyright of which is held by Adam Dunkels.\r
+   Users must ensure the open source license conditions stated at the top \r
+   of each uIP source file is understood and adhered to.\r
+\r
+3) The lwIP TCP/IP stack the copyright of which is held by the Swedish \r
+   Institute of Computer Science.  Users must ensure the open source license \r
+   conditions stated at the top  of each lwIP source file is understood and \r
+   adhered to.\r
+\r
+4) Various peripheral driver source files and binaries provided by silicon\r
+   manufacturers and tool vendors.  Permission has been granted by the\r
+   various copyright holders for these files to be included in the FreeRTOS\r
+   download.  Users must ensure license conditions are adhered to for any\r
+   use other than compilation of the FreeRTOS demo applications.\r
+\r
+5) The files contained within FreeRTOS\Demo\WizNET_DEMO_TERN_186\tern_code,\r
+   which are slightly modified versions of code provided by and copyright to\r
+   Tern Inc.\r
+\r
+Errors and omissions should be reported to Richard Barry, contact details for\r
+whom can be obtained from http://www.FreeRTOS.org.\r
+\r
+\r
+\r
+\r
+\r
+The GPL license text follows.\r
+\r
+A special exception to the GPL is included to allow you to distribute a \r
+combined work that includes FreeRTOS without being obliged to provide\r
+the source code for any proprietary components.  See the licensing section\r
+of http://www.FreeRTOS.org for full details.  The exception text is also\r
+included at the bottom of this file.\r
+\r
+--------------------------------------------------------------------\r
+\r
+\r
+\r
+                   GNU GENERAL PUBLIC LICENSE\r
+                      Version 2, June 1991\r
+\r
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.\r
+                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+ Everyone is permitted to copy and distribute verbatim copies\r
+ of this license document, but changing it is not allowed.\r
+\r
+                           Preamble\r
+\r
+  The licenses for most software are designed to take away your\r
+freedom to share and change it.  By contrast, the GNU General Public\r
+License is intended to guarantee your freedom to share and change free\r
+software--to make sure the software is free for all its users.  This\r
+General Public License applies to most of the Free Software\r
+Foundation's software and to any other program whose authors commit to\r
+using it.  (Some other Free Software Foundation software is covered by\r
+the GNU Library General Public License instead.)  You can apply it to\r
+your programs, too.\r
+\r
+  When we speak of free software, we are referring to freedom, not\r
+price.  Our General Public Licenses are designed to make sure that you\r
+have the freedom to distribute copies of free software (and charge for\r
+this service if you wish), that you receive source code or can get it\r
+if you want it, that you can change the software or use pieces of it\r
+in new free programs; and that you know you can do these things.\r
+\r
+  To protect your rights, we need to make restrictions that forbid\r
+anyone to deny you these rights or to ask you to surrender the rights.\r
+These restrictions translate to certain responsibilities for you if you\r
+distribute copies of the software, or if you modify it.\r
+\r
+  For example, if you distribute copies of such a program, whether\r
+gratis or for a fee, you must give the recipients all the rights that\r
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+\r
+  The precise terms and conditions for copying, distribution and\r
+modification follow.\r
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+                   GNU GENERAL PUBLIC LICENSE\r
+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\r
+\r
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+a notice placed by the copyright holder saying it may be distributed\r
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+Activities other than copying, distribution and modification are not\r
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+  1. You may copy and distribute verbatim copies of the Program's\r
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+\r
+You may charge a fee for the physical act of transferring a copy, and\r
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+  2. You may modify your copy or copies of the Program or any portion\r
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+\r
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+\f\r
+These requirements apply to the modified work as a whole.  If\r
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+\r
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+In addition, mere aggregation of another work not based on the Program\r
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+  3. You may copy and distribute the Program (or a work based on it,\r
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+\r
+    a) Accompany it with the complete corresponding machine-readable\r
+    source code, which must be distributed under the terms of Sections\r
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+\r
+    b) Accompany it with a written offer, valid for at least three\r
+    years, to give any third party, for a charge no more than your\r
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+\r
+    c) Accompany it with the information you received as to the offer\r
+    to distribute corresponding source code.  (This alternative is\r
+    allowed only for noncommercial distribution and only if you\r
+    received the program in object code or executable form with such\r
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+\r
+The source code for a work means the preferred form of the work for\r
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+access to copy the source code from the same place counts as\r
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+compelled to copy the source along with the object code.\r
+\f\r
+  4. You may not copy, modify, sublicense, or distribute the Program\r
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+otherwise to copy, modify, sublicense or distribute the Program is\r
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+\r
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+distribute the Program or its derivative works.  These actions are\r
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+modifying or distributing the Program (or any work based on the\r
+Program), you indicate your acceptance of this License to do so, and\r
+all its terms and conditions for copying, distributing or modifying\r
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+\r
+  6. Each time you redistribute the Program (or any work based on the\r
+Program), the recipient automatically receives a license from the\r
+original licensor to copy, distribute or modify the Program subject to\r
+these terms and conditions.  You may not impose any further\r
+restrictions on the recipients' exercise of the rights granted herein.\r
+You are not responsible for enforcing compliance by third parties to\r
+this License.\r
+\r
+  7. If, as a consequence of a court judgment or allegation of patent\r
+infringement or for any other reason (not limited to patent issues),\r
+conditions are imposed on you (whether by court order, agreement or\r
+otherwise) that contradict the conditions of this License, they do not\r
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+may not distribute the Program at all.  For example, if a patent\r
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+all those who receive copies directly or indirectly through you, then\r
+the only way you could satisfy both it and this License would be to\r
+refrain entirely from distribution of the Program.\r
+\r
+If any portion of this section is held invalid or unenforceable under\r
+any particular circumstance, the balance of the section is intended to\r
+apply and the section as a whole is intended to apply in other\r
+circumstances.\r
+\r
+It is not the purpose of this section to induce you to infringe any\r
+patents or other property right claims or to contest validity of any\r
+such claims; this section has the sole purpose of protecting the\r
+integrity of the free software distribution system, which is\r
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+to distribute software through any other system and a licensee cannot\r
+impose that choice.\r
+\r
+This section is intended to make thoroughly clear what is believed to\r
+be a consequence of the rest of this License.\r
+\f\r
+  8. If the distribution and/or use of the Program is restricted in\r
+certain countries either by patents or by copyrighted interfaces, the\r
+original copyright holder who places the Program under this License\r
+may add an explicit geographical distribution limitation excluding\r
+those countries, so that distribution is permitted only in or among\r
+countries not thus excluded.  In such case, this License incorporates\r
+the limitation as if written in the body of this License.\r
+\r
+  9. The Free Software Foundation may publish revised and/or new versions\r
+of the General Public License from time to time.  Such new versions will\r
+be similar in spirit to the present version, but may differ in detail to\r
+address new problems or concerns.\r
+\r
+Each version is given a distinguishing version number.  If the Program\r
+specifies a version number of this License which applies to it and "any\r
+later version", you have the option of following the terms and conditions\r
+either of that version or of any later version published by the Free\r
+Software Foundation.  If the Program does not specify a version number of\r
+this License, you may choose any version ever published by the Free Software\r
+Foundation.\r
+\r
+  10. If you wish to incorporate parts of the Program into other free\r
+programs whose distribution conditions are different, write to the author\r
+to ask for permission.  For software which is copyrighted by the Free\r
+Software Foundation, write to the Free Software Foundation; we sometimes\r
+make exceptions for this.  Our decision will be guided by the two goals\r
+of preserving the free status of all derivatives of our free software and\r
+of promoting the sharing and reuse of software generally.\r
+\r
+                           NO WARRANTY\r
+\r
+  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY\r
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN\r
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES\r
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED\r
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS\r
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE\r
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,\r
+REPAIR OR CORRECTION.\r
+\r
+  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\r
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR\r
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,\r
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING\r
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED\r
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY\r
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER\r
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE\r
+POSSIBILITY OF SUCH DAMAGES.\r
+\r
+                    END OF TERMS AND CONDITIONS\r
+\f\r
+           How to Apply These Terms to Your New Programs\r
+\r
+  If you develop a new program, and you want it to be of the greatest\r
+possible use to the public, the best way to achieve this is to make it\r
+free software which everyone can redistribute and change under these terms.\r
+\r
+  To do so, attach the following notices to the program.  It is safest\r
+to attach them to the start of each source file to most effectively\r
+convey the exclusion of warranty; and each file should have at least\r
+the "copyright" line and a pointer to where the full notice is found.\r
+\r
+    <one line to give the program's name and a brief idea of what it does.>\r
+    Copyright (C) <year>  <name of author>\r
+\r
+    This program is free software; you can redistribute it and/or modify\r
+    it under the terms of the GNU General Public License** as published by\r
+    the Free Software Foundation; either version 2 of the License, or\r
+    (at your option) any later version.\r
+\r
+    This program is distributed in the hope that it will be useful,\r
+    but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+    GNU General Public License for more details.\r
+\r
+    You should have received a copy of the GNU General Public License\r
+    along with this program; if not, write to the Free Software\r
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+\r
+Also add information on how to contact you by electronic and paper mail.\r
+\r
+If the program is interactive, make it output a short notice like this\r
+when it starts in an interactive mode:\r
+\r
+    Gnomovision version 69, Copyright (C) year name of author\r
+    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\r
+    This is free software, and you are welcome to redistribute it\r
+    under certain conditions; type `show c' for details.\r
+\r
+The hypothetical commands `show w' and `show c' should show the appropriate\r
+parts of the General Public License.  Of course, the commands you use may\r
+be called something other than `show w' and `show c'; they could even be\r
+mouse-clicks or menu items--whatever suits your program.\r
+\r
+You should also get your employer (if you work as a programmer) or your\r
+school, if any, to sign a "copyright disclaimer" for the program, if\r
+necessary.  Here is a sample; alter the names:\r
+\r
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program\r
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.\r
+\r
+  <signature of Ty Coon>, 1 April 1989\r
+  Ty Coon, President of Vice\r
+\r
+This General Public License does not permit incorporating your program into\r
+proprietary programs.  If your program is a subroutine library, you may\r
+consider it more useful to permit linking proprietary applications with the\r
+library.  If this is what you want to do, use the GNU Library General\r
+Public License instead of this License.\r
+\r
+----------------------------------------------------------------------------\r
+\r
+The FreeRTOS GPL Exception Text:\r
+\r
+Any FreeRTOS source code, whether modified or in it's original release form, \r
+or whether in whole or in part, can only be distributed by you under the terms \r
+of the GNU General Public License plus this exception. An independent module is \r
+a module which is not derived from or based on FreeRTOS.\r
+\r
+Clause 1:\r
+\r
+Linking FreeRTOS statically or dynamically with other modules is making a \r
+combined work based on FreeRTOS. Thus, the terms and conditions of the GNU \r
+General Public License cover the whole combination.\r
+\r
+As a special exception, the copyright holder of FreeRTOS gives you permission \r
+to link FreeRTOS with independent modules that communicate with FreeRTOS \r
+solely through the FreeRTOS API interface, regardless of the license terms of \r
+these independent modules, and to copy and distribute the resulting combined \r
+work under terms of your choice, provided that\r
+\r
+  + Every copy of the combined work is accompanied by a written statement that \r
+  details to the recipient the version of FreeRTOS used and an offer by yourself \r
+  to provide the FreeRTOS source code (including any modifications you may have \r
+  made) should the recipient request it.\r
+\r
+  + The combined work is not itself an RTOS, scheduler, kernel or related product.\r
+\r
+  + The independent modules add significant and primary functionality to FreeRTOS \r
+  and do not merely extend the existing functionality already present in FreeRTOS.\r
+\r
+Clause 2:\r
+\r
+FreeRTOS may not be used for any competitive or comparative purpose, including the \r
+publication of any form of run time or compile time metric, without the express \r
+permission of Real Time Engineers Ltd. (this is the norm within the industry and \r
+is intended to ensure information accuracy).\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/Makefile b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/Makefile
new file mode 100644 (file)
index 0000000..57884bf
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/Makefile
@@ -0,0 +1,77 @@
+############################################################################## 
+#
+# Copyright (c) 2010 Xilinx, Inc.  All rights reserved.
+#
+# Xilinx, Inc.
+# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A 
+# COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+# ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR 
+# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE 
+# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  
+# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO 
+# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO 
+# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 
+# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY 
+# AND FITNESS FOR A PARTICULAR PURPOSE.
+# 
+# Top level Makefile
+#
+# $Id: $
+#
+##############################################################################
+
+#
+# Processor architecture
+# microblaze
+#
+ARCH = microblaze
+
+SYSTEMDIR = ../../..
+
+TOPDIR = .
+
+ARCH_PREFIX = mb
+
+#
+# gnu tools for Makefile
+#
+CC = $(ARCH_PREFIX)-gcc
+AR = $(ARCH_PREFIX)-ar
+CP = cp
+
+#
+# Compiler, linker and other options.
+#
+CFLAGS = ${COMPILER_FLAGS} ${EXTRA_COMPILER_FLAGS} 
+
+#
+# System project directories.
+#
+LIBDIR = $(SYSTEMDIR)/lib
+INCLUDEDIR = $(SYSTEMDIR)/include
+
+# Kernel library. 
+LIBFREERTOS = ${LIBDIR}/libfreertos.a
+
+INCLUDEFILES = ${TOPDIR}/*.h
+
+INCLUDES = -I$(INCLUDEDIR) \
+       -I${TOPDIR}
+
+KERNEL_AR_OBJS = *.c *.S
+
+OUTS = *.o
+
+libs:  $(KERNEL_AR_OBJS)
+       @echo "Compiling FreeRTOS"
+       @$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $^
+       @$(ARCHIVER) -r ${LIBFREERTOS} ${OUTS}
+       make clean
+
+.PHONY: include
+include:
+       ${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+       rm -rf ${OUTS}

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/Source/portable/readme.txt b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/Source/portable/readme.txt
new file mode 100644 (file)
index 0000000..a20d687
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/Source/portable/readme.txt
@@ -0,0 +1,19 @@
+Each real time kernel port consists of three files that contain the core kernel\r
+components and are common to every port, and one or more files that are \r
+specific to a particular microcontroller and/or compiler.\r
+\r
+\r
++ The FreeRTOS/Source/Portable/MemMang directory contains the three sample \r
+memory allocators as described on the http://www.FreeRTOS.org WEB site.\r
+\r
++ The other directories each contain files specific to a particular \r
+microcontroller or compiler.\r
+\r
+\r
+\r
+For example, if you are interested in the GCC port for the ATMega323 \r
+microcontroller then the port specific files are contained in\r
+FreeRTOS/Source/Portable/GCC/ATMega323 directory.  If this is the only\r
+port you are interested in then all the other directories can be\r
+ignored.\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/Source/readme.txt b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/Source/readme.txt
new file mode 100644 (file)
index 0000000..81518ec
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/Source/readme.txt
@@ -0,0 +1,17 @@
+Each real time kernel port consists of three files that contain the core kernel\r
+components and are common to every port, and one or more files that are \r
+specific to a particular microcontroller and or compiler.\r
+\r
++ The FreeRTOS/Source directory contains the three files that are common to \r
+every port - list.c, queue.c and tasks.c.  The kernel is contained within these \r
+three files.  croutine.c implements the optional co-routine functionality - which\r
+is normally only used on very memory limited systems.\r
+\r
++ The FreeRTOS/Source/Portable directory contains the files that are specific to \r
+a particular microcontroller and or compiler.\r
+\r
++ The FreeRTOS/Source/include directory contains the real time kernel header \r
+files.\r
+\r
+See the readme file in the FreeRTOS/Source/Portable directory for more \r
+information.
\ No newline at end of file

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/readme.txt b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/readme.txt
new file mode 100644 (file)
index 0000000..49eecd6
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/bsp/freertos_v2_00_a/src/readme.txt
@@ -0,0 +1,19 @@
+The download includes the kernel source code, and a demo application for EVERY\r
+RTOS port.  See http://www.freertos.org/a00017.html for full details of the \r
+directory structure and information on locating the files you require.\r
+\r
+The easiest way to use FreeRTOS is start start with one of the demo application \r
+projects.  Once this is running the project can be modified to include your own\r
+source files.  This way the correct files and compiler options will be \r
+automatically included in your application.\r
+\r
++ The Source directory contains the real time kernel source files for every \r
+port.  The kernel itself is only 3 files.\r
+\r
++ The Demo directory contains the demo application source files for every \r
+port.\r
+\r
++ The TraceCon directory contains the trace visualisation exe file.\r
+\r
+See the readme files in the respective directories for further information.\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/sw_apps/FreeRTOS_Hello_World/data/FreeRTOS_Hello_World.mss b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/sw_apps/FreeRTOS_Hello_World/data/FreeRTOS_Hello_World.mss
new file mode 100644 (file)
index 0000000..230dee3
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/sw_apps/FreeRTOS_Hello_World/data/FreeRTOS_Hello_World.mss
@@ -0,0 +1,9 @@
+
+ PARAMETER VERSION = 2.2.0
+
+
+BEGIN OS
+ PARAMETER OS_NAME = freertos
+ PARAMETER STDIN =  *
+ PARAMETER STDOUT = *
+END

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/sw_apps/FreeRTOS_Hello_World/data/FreeRTOS_Hello_World.tcl b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/sw_apps/FreeRTOS_Hello_World/data/FreeRTOS_Hello_World.tcl
new file mode 100644 (file)
index 0000000..7845d73
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/sw_apps/FreeRTOS_Hello_World/data/FreeRTOS_Hello_World.tcl
@@ -0,0 +1,127 @@
+proc swapp_get_name {} {
+    return "FreeRTOS Hello World";
+}
+
+proc swapp_get_description {} {
+    return "Let's say 'Hello World' in FreeRTOS.";
+}
+
+proc get_os {} {
+    set oslist [xget_sw_modules "type" "os"];
+    set os [lindex $oslist 0];
+
+    if { $os == "" } {
+        error "No Operating System specified in the Board Support Package.";
+    }
+
+    return $os;
+}
+
+proc get_stdout {} {
+    set os [get_os];
+    set stdout [xget_sw_module_parameter $os "STDOUT"];
+    return $stdout;
+}
+
+proc check_stdout_hw {} {
+    set uartlites [xget_ips "type" "uartlite"];
+    set uart16550s [xget_ips "type" "uart16550"];
+    if { ([llength $uartlites] == 0) && ([llength $uart16550s] == 0) } {
+        # Check for MDM-Uart peripheral. The MDM would be listed as a peripheral
+        # only if it has a UART interface. So no further check is required
+        set mdmlist [xget_ips "type" "mdm"]
+        if { [llength $mdmlist] == 0 } {
+           error "This application requires a Uart IP in the hardware."
+        }
+    }
+}
+
+proc check_stdout_sw {} {
+    set stdout [get_stdout];
+    if { $stdout == "none" } {
+        error "The STDOUT parameter is not set on the OS. Hello World requires stdout to be set."
+    }
+}
+
+proc get_mem_size { memlist } {
+    return [lindex $memlist 4];
+}
+
+proc require_memory {memsize} {
+    set imemlist [xget_memory_ranges "access_type" "I"];
+    set idmemlist [xget_memory_ranges "access_type" "ID"];
+    set dmemlist [xget_memory_ranges "access_type" "D"];
+
+    set memlist [concat $imemlist $idmemlist $dmemlist];
+
+    while { [llength $memlist] > 3 } {
+        set mem [lrange $memlist 0 4];
+        set memlist [lreplace $memlist 0 4];
+
+        if { [get_mem_size $mem] >= $memsize } {
+            return 1;
+        }
+    }
+
+    error "This application requires atleast $memsize bytes of memory.";
+}
+
+proc swapp_is_supported_hw {} {
+    # check for uart peripheral
+    check_stdout_hw;
+
+    # require about 1M of memory
+    require_memory "1000000";
+
+    return 1;
+}
+
+proc swapp_is_supported_sw {} {
+    # check for stdout being set
+    check_stdout_sw;
+
+    return 1;
+}
+
+proc generate_stdout_config { fid } {
+    set stdout [get_stdout];
+
+    # if stdout is uartlite, we don't have to generate anything
+    set stdout_type [xget_ip_attribute "type" $stdout];
+
+    if { [regexp -nocase "uartlite" $stdout_type] || [string match -nocase "mdm" $stdout_type] } {
+        return;
+    } elseif { [regexp -nocase "uart16550" $stdout_type] } {
+       # mention that we have a 16550
+        puts $fid "#define STDOUT_IS_16550";
+
+        # and note down its base address
+       set prefix "XPAR_";
+       set postfix "_BASEADDR";
+       set stdout_baseaddr_macro $prefix$stdout$postfix;
+       set stdout_baseaddr_macro [string toupper $stdout_baseaddr_macro];
+       puts $fid "#define STDOUT_BASEADDR $stdout_baseaddr_macro";
+    }
+}
+
+# depending on the type of os (standalone|xilkernel), choose
+# the correct source files
+proc swapp_generate {} {
+
+    # cleanup this file for writing
+    set fid [open "platform_config.h" "w+"];
+    puts $fid "#ifndef __PLATFORM_CONFIG_H_";
+    puts $fid "#define __PLATFORM_CONFIG_H_\n";
+
+    # if we have a uart16550 as stdout, then generate some config for that
+    generate_stdout_config $fid;
+
+    puts $fid "#endif";
+    close $fid;
+}
+
+proc swapp_get_linker_constraints {} {
+
+    # we need a 4k heap
+    return "stack 40k heap 40k";
+}

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/sw_apps/FreeRTOS_Hello_World/src/FreeRTOS-main.c b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/sw_apps/FreeRTOS_Hello_World/src/FreeRTOS-main.c
new file mode 100644 (file)
index 0000000..2ce33b7
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/KernelAwareBSPRepository/sw_apps/FreeRTOS_Hello_World/src/FreeRTOS-main.c
@@ -0,0 +1,398 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+       ***************************************************************************\r
+       See http://www.FreeRTOS.org for full information on FreeRTOS, including\r
+       an API reference, pdf API reference manuals, and FreeRTOS tutorial books.\r
+\r
+       See http://www.freertos.org/Free-RTOS-for-Xilinx-MicroBlaze-on-Spartan-6-FPGA.html\r
+       for comprehensive standalone FreeRTOS for MicroBlaze demos.\r
+       ***************************************************************************\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/*\r
+ * FreeRTOS-main.c (this file) defines a very simple demo that creates two tasks,\r
+ * one queue, and one timer.\r
+ *\r
+ * The main() Function:\r
+ * main() creates one software timer, one queue, and two tasks.  It then starts\r
+ * the scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file.  prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main().  Once the value is sent, the task loops back\r
+ * around to block for another 200 milliseconds.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file.  prvQueueReceiveTask() sits in a loop that causes it to\r
+ * repeatedly attempt to read data from the queue that was created within\r
+ * main().  When data is received, the task checks the value of the data, and\r
+ * if the value equals the expected 100, increments the ulRecieved variable.\r
+ * The 'block time' parameter passed to the queue receive function specifies\r
+ * that the task should be held in the Blocked state indefinitely to wait for\r
+ * data to be available on the queue.  The queue receive task will only leave\r
+ * the Blocked state when the queue send task writes to the queue.  As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive task\r
+ * leaves the Blocked state every 200 milliseconds, and therefore toggles the LED\r
+ * every 200 milliseconds.\r
+ *\r
+ * The Software Timer:\r
+ * The software timer is configured to be an "auto reset" timer.  Its callback\r
+ * function simply increments the ulCallback variable each time it executes.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "timers.h"\r
+\r
+/* BSP includes. */\r
+#include "xtmrctr.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY                ( tskIDLE_PRIORITY + 2 )\r
+#define        mainQUEUE_SEND_TASK_PRIORITY            ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue, specified in milliseconds, and\r
+converted to ticks using the portTICK_RATE_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS                    ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold.  This is 1 as the receive task\r
+will remove items as they are added because it has the higher priority, meaning\r
+the send task should always find the queue empty. */\r
+#define mainQUEUE_LENGTH                                       ( 1 )\r
+\r
+/* A block time of 0 simply means, "don't block". */\r
+#define mainDONT_BLOCK                                         ( portTickType ) 0\r
+\r
+/* The following constants describe the timer instance used in this application.\r
+They are defined here such that a user can easily change all the needed parameters\r
+in one place. */\r
+#define TIMER_DEVICE_ID                                                XPAR_TMRCTR_0_DEVICE_ID\r
+#define TIMER_FREQ_HZ                                          XPAR_TMRCTR_0_CLOCK_FREQ_HZ\r
+#define TIMER_INTR_ID                                          XPAR_INTC_0_TMRCTR_0_VEC_ID\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * The LED timer callback function.  This does nothing but increment the\r
+ * ulCallback variable each time it executes.\r
+ */\r
+static void vSoftwareTimerCallback( xTimerHandle xTimer );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by the queue send and queue receive tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/* The LED software timer.  This uses vSoftwareTimerCallback() as its callback\r
+function. */\r
+static xTimerHandle xExampleSoftwareTimer = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Structures that hold the state of the various peripherals used by this demo.\r
+These are used by the Xilinx peripheral driver API functions. */\r
+static XTmrCtr xTimer0Instance;\r
+\r
+/* The variable that is incremented each time the receive task receives the\r
+value 100. */\r
+static unsigned long ulReceived = 0UL;\r
+\r
+/* The variable that is incremented each time the software time callback function\r
+executes. */\r
+static unsigned long ulCallback = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+       /***************************************************************************\r
+       See http://www.FreeRTOS.org for full information on FreeRTOS, including\r
+       an API reference, pdf API reference manuals, and FreeRTOS tutorial books.\r
+\r
+       See http://www.freertos.org/Free-RTOS-for-Xilinx-MicroBlaze-on-Spartan-6-FPGA.html\r
+       for comprehensive standalone FreeRTOS for MicroBlaze demos.\r
+       ***************************************************************************/\r
+\r
+       /* Create the queue used by the queue send and queue receive tasks as\r
+       described in the comments at the top of this file. */\r
+       xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+       /* Sanity check that the queue was created. */\r
+       configASSERT( xQueue );\r
+\r
+       /* Start the two tasks as described in the comments at the top of this\r
+       file. */\r
+       xTaskCreate( prvQueueReceiveTask, ( signed char * ) "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL );\r
+       xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+       /* Create the software timer */\r
+       xExampleSoftwareTimer = xTimerCreate(   ( const signed char * ) "SoftwareTimer", /* A text name, purely to help debugging. */\r
+                                                                                       ( 5000 / portTICK_RATE_MS ),            /* The timer period, in this case 5000ms (5s). */\r
+                                                                                       pdTRUE,                                                         /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+                                                                                       ( void * ) 0,                                           /* The ID is not used, so can be set to anything. */\r
+                                                                                       vSoftwareTimerCallback                          /* The callback function that switches the LED off. */\r
+                                                                               );\r
+\r
+       /* Start the software timer. */\r
+       xTimerStart( xExampleSoftwareTimer, mainDONT_BLOCK );\r
+\r
+       /* Start the tasks and timer running. */\r
+       vTaskStartScheduler();\r
+\r
+       /* If all is well, the scheduler will now be running, and the following line\r
+       will never be reached.  If the following line does execute, then there was\r
+       insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
+       to be created.  See the memory management section on the FreeRTOS web site\r
+       for more details. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The callback is executed when the software timer expires. */\r
+static void vSoftwareTimerCallback( xTimerHandle xTimer )\r
+{\r
+       /* Just increment the ulCallbac variable. */\r
+       ulCallback++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+       /* Initialise xNextWakeTime - this only needs to be done once. */\r
+       xNextWakeTime = xTaskGetTickCount();\r
+\r
+       for( ;; )\r
+       {\r
+               /* Place this task in the blocked state until it is time to run again.\r
+               The block time is specified in ticks, the constant used converts ticks\r
+               to ms.  While in the Blocked state this task will not consume any CPU\r
+               time. */\r
+               vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+               /* Send to the queue - causing the queue receive task to unblock and\r
+               toggle an LED.  0 is used as the block time so the sending operation\r
+               will not block - it shouldn't need to block as the queue should always\r
+               be empty at this point in the code. */\r
+               xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+       for( ;; )\r
+       {\r
+               /* Wait until something arrives in the queue - this task will block\r
+               indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+               FreeRTOSConfig.h. */\r
+               xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+               /*  To get here something must have been received from the queue, but\r
+               is it the expected value?  If it is, increment the ulReceived variable. */\r
+               if( ulReceivedValue == 100UL )\r
+               {\r
+                       ulReceived++;\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+       /* vApplicationMallocFailedHook() will only be called if\r
+       configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h.  It is a hook\r
+       function that will get called if a call to pvPortMalloc() fails.\r
+       pvPortMalloc() is called internally by the kernel whenever a task, queue or\r
+       semaphore is created.  It is also called by various parts of the demo\r
+       application.  If heap_1.c or heap_2.c are used, then the size of the heap\r
+       available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+       FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+       to query the size of free heap space that remains (although it does not\r
+       provide information on how the remaining heap might be fragmented). */\r
+       taskDISABLE_INTERRUPTS();\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
+{\r
+       ( void ) pcTaskName;\r
+       ( void ) pxTask;\r
+\r
+       /* vApplicationStackOverflowHook() will only be called if\r
+       configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2.  The handle and name\r
+       of the offending task will be passed into the hook function via its\r
+       parameters.  However, when a stack has overflowed, it is possible that the\r
+       parameters will have been corrupted, in which case the pxCurrentTCB variable\r
+       can be inspected directly. */\r
+       taskDISABLE_INTERRUPTS();\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+       /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+       to 1 in FreeRTOSConfig.h.  It will be called on each iteration of the idle\r
+       task.  It is essential that code added to this hook function never attempts\r
+       to block in any way (for example, call xQueueReceive() with a block time\r
+       specified, or call vTaskDelay()).  If the application makes use of the\r
+       vTaskDelete() API function (as this demo application does) then it is also\r
+       important that vApplicationIdleHook() is permitted to return to its calling\r
+       function, because it is the responsibility of the idle task to clean up\r
+       memory allocated by the kernel to any task that has since been deleted. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+       /* vApplicationTickHook() will only be called if configUSE_TICK_HOOK is set\r
+       to 1 in FreeRTOSConfig.h.  It executes from an interrupt context so must\r
+       not use any FreeRTOS API functions that do not end in ...FromISR().\r
+\r
+       This simple blinky demo does not use the tick hook, but a tick hook is\r
+       required to be defined as the blinky and full demos share a\r
+       FreeRTOSConfig.h header file. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is an application defined callback function used to install the tick\r
+interrupt handler.  It is provided as an application callback because the kernel\r
+will run on lots of different MicroBlaze and FPGA configurations - there could\r
+be multiple timer instances in the hardware platform and the users can chose to\r
+use any one of them. This example uses Timer 0. If that is available in  your\r
+hardware platform then this example callback implementation should not require\r
+modification. The definitions for the timer instance used are at the top of this\r
+file so that users can change them at one place based on the timer instance they\r
+use. The name of the interrupt handler that should be installed is vPortTickISR(),\r
+which the function below declares as an extern. */\r
+void vApplicationSetupTimerInterrupt( void )\r
+{\r
+portBASE_TYPE xStatus;\r
+const unsigned char ucTimerCounterNumber = ( unsigned char ) 0U;\r
+const unsigned long ulCounterValue = ( ( TIMER_FREQ_HZ / configTICK_RATE_HZ ) - 1UL );\r
+extern void vPortTickISR( void *pvUnused );\r
+\r
+       /* Initialise the timer/counter. */\r
+       xStatus = XTmrCtr_Initialize( &xTimer0Instance, TIMER_DEVICE_ID );\r
+\r
+       if( xStatus == XST_SUCCESS )\r
+       {\r
+               /* Install the tick interrupt handler as the timer ISR.\r
+               *NOTE* The xPortInstallInterruptHandler() API function must be used for\r
+               this purpose. */\r
+               xStatus = xPortInstallInterruptHandler( TIMER_INTR_ID, vPortTickISR, NULL );\r
+       }\r
+\r
+       if( xStatus == pdPASS )\r
+       {\r
+               /* Enable the timer interrupt in the interrupt controller.\r
+               *NOTE* The vPortEnableInterrupt() API function must be used for this\r
+               purpose. */\r
+               vPortEnableInterrupt( TIMER_INTR_ID );\r
+\r
+               /* Configure the timer interrupt handler. */\r
+               XTmrCtr_SetHandler( &xTimer0Instance, ( void * ) vPortTickISR, NULL );\r
+\r
+               /* Set the correct period for the timer. */\r
+               XTmrCtr_SetResetValue( &xTimer0Instance, ucTimerCounterNumber, ulCounterValue );\r
+\r
+               /* Enable the interrupts.  Auto-reload mode is used to generate a\r
+               periodic tick.  Note that interrupts are disabled when this function is\r
+               called, so interrupts will not start to be processed until the first\r
+               task has started to run. */\r
+               XTmrCtr_SetOptions( &xTimer0Instance, ucTimerCounterNumber, ( XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION | XTC_DOWN_COUNT_OPTION ) );\r
+\r
+               /* Start the timer. */\r
+               XTmrCtr_Start( &xTimer0Instance, ucTimerCounterNumber );\r
+       }\r
+\r
+       /* Sanity check that the function executed as expected. */\r
+       configASSERT( ( xStatus == pdPASS ) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is an application defined callback function used to clear whichever\r
+interrupt was installed by the the vApplicationSetupTimerInterrupt() callback\r
+function - in this case the interrupt generated by the AXI timer.  It is\r
+provided as an application callback because the kernel will run on lots of\r
+different MicroBlaze and FPGA configurations - not all of which will have the\r
+same timer peripherals defined or available.  This example uses the AXI Timer 0.\r
+If that is available on your hardware platform then this example callback\r
+implementation should not require modification provided the example definition\r
+of vApplicationSetupTimerInterrupt() is also not modified. */\r
+void vApplicationClearTimerInterrupt( void )\r
+{\r
+unsigned long ulCSR;\r
+\r
+       /* Clear the timer interrupt */\r
+       ulCSR = XTmrCtr_GetControlStatusReg( XPAR_TMRCTR_0_BASEADDR, 0 );\r
+       XTmrCtr_SetControlStatusReg( XPAR_TMRCTR_0_BASEADDR, 0, ulCSR );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/HardwareWithEthernetFull/.project b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/HardwareWithEthernetFull/.project
new file mode 100644 (file)
index 0000000..c526d75
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/HardwareWithEthernetFull/.project
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+       <name>HardwareWithEthernetFull</name>\r
+       <comment></comment>\r
+       <projects>\r
+       </projects>\r
+       <buildSpec>\r
+       </buildSpec>\r
+       <natures>\r
+               <nature>com.xilinx.sdk.hw.HwProject</nature>\r
+       </natures>\r
+</projectDescription>\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/HardwareWithEthernetFull/system.bit b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/HardwareWithEthernetFull/system.bit
new file mode 100644 (file)
index 0000000..4fa2c85
Binary files /dev/null and b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/HardwareWithEthernetFull/system.bit differ

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/HardwareWithEthernetFull/system.xml b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/HardwareWithEthernetFull/system.xml
new file mode 100644 (file)
index 0000000..3c2d81d
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/HardwareWithEthernetFull/system.xml
@@ -0,0 +1,6936 @@
+
+<EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Sat Aug 27 15:05:40 2011">
+
+  <SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45t" PACKAGE="fgg484" PART="xc6slx45tfgg484-3" SOURCE="C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.xmp" SPEEDGRADE="-3"/>
+
+  <EXTERNALPORTS>
+    <PORT DIR="I" MHS_INDEX="0" NAME="RESET" RSTPOLARITY="1" SIGIS="RST" SIGNAME="RESET"/>
+    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK"/>
+    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="2" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK"/>
+    <PORT DIR="O" MHS_INDEX="3" NAME="RS232_Uart_1_sout" SIGNAME="RS232_Uart_1_sout"/>
+    <PORT DIR="I" MHS_INDEX="4" NAME="RS232_Uart_1_sin" SIGNAME="RS232_Uart_1_sin"/>
+    <PORT DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="5" MSB="3" NAME="LEDs_4Bits_TRI_O" RIGHT="0" SIGNAME="LEDs_4Bits_TRI_O"/>
+    <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="6" MSB="3" NAME="Push_Buttons_4Bits_TRI_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I"/>
+    <PORT DIR="O" MHS_INDEX="7" NAME="mcbx_dram_clk" SIGIS="CLK" SIGNAME="mcbx_dram_clk"/>
+    <PORT DIR="O" MHS_INDEX="8" NAME="mcbx_dram_clk_n" SIGIS="CLK" SIGNAME="mcbx_dram_clk_n"/>
+    <PORT DIR="O" MHS_INDEX="9" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
+    <PORT DIR="O" MHS_INDEX="10" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
+    <PORT DIR="O" MHS_INDEX="11" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
+    <PORT DIR="O" MHS_INDEX="12" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
+    <PORT DIR="O" MHS_INDEX="13" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
+    <PORT DIR="O" MHS_INDEX="14" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
+    <PORT DIR="O" MHS_INDEX="15" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
+    <PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="16" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba"/>
+    <PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="17" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr"/>
+    <PORT DIR="O" MHS_INDEX="18" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
+    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="15" LSB="0" MHS_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq"/>
+    <PORT DIR="IO" MHS_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
+    <PORT DIR="IO" MHS_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
+    <PORT DIR="IO" MHS_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
+    <PORT DIR="IO" MHS_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
+    <PORT DIR="IO" MHS_INDEX="24" NAME="rzq" SIGNAME="rzq"/>
+    <PORT DIR="IO" MHS_INDEX="25" NAME="zio" SIGNAME="zio"/>
+    <PORT DIR="IO" MHS_INDEX="26" NAME="ETHERNET_MDIO" SIGNAME="ETHERNET_MDIO"/>
+    <PORT DIR="O" MHS_INDEX="27" NAME="ETHERNET_MDC" SIGNAME="ETHERNET_MDC"/>
+    <PORT DIR="O" MHS_INDEX="28" NAME="ETHERNET_TX_ER" SIGNAME="ETHERNET_TX_ER"/>
+    <PORT DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MHS_INDEX="29" MSB="7" NAME="ETHERNET_TXD" RIGHT="0" SIGNAME="ETHERNET_TXD"/>
+    <PORT DIR="O" MHS_INDEX="30" NAME="ETHERNET_TX_EN" SIGNAME="ETHERNET_TX_EN"/>
+    <PORT DIR="I" MHS_INDEX="31" NAME="ETHERNET_MII_TX_CLK" SIGNAME="ETHERNET_MII_TX_CLK"/>
+    <PORT DIR="O" MHS_INDEX="32" NAME="ETHERNET_TX_CLK" SIGNAME="ETHERNET_TX_CLK"/>
+    <PORT DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MHS_INDEX="33" MSB="7" NAME="ETHERNET_RXD" RIGHT="0" SIGNAME="ETHERNET_RXD"/>
+    <PORT DIR="I" MHS_INDEX="34" NAME="ETHERNET_RX_ER" SIGNAME="ETHERNET_RX_ER"/>
+    <PORT DIR="I" MHS_INDEX="35" NAME="ETHERNET_RX_CLK" SIGNAME="ETHERNET_RX_CLK"/>
+    <PORT DIR="I" MHS_INDEX="36" NAME="ETHERNET_RX_DV" SIGNAME="ETHERNET_RX_DV"/>
+    <PORT DIR="O" MHS_INDEX="37" NAME="ETHERNET_PHY_RST_N" SIGNAME="ETHERNET_PHY_RST_N"/>
+  </EXTERNALPORTS>
+
+  <MODULES>
+    <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4_0" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="0" MODCLASS="BUS" MODTYPE="axi_interconnect">
+      <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Base Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="5">
+          <DESCRIPTION>Number of Slave Slots </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Number of Master Slots </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="3">
+          <DESCRIPTION>AXI ID Widgth </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Widgth </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
+          <DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
+          <DESCRIPTION>Master AXI Data Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>AXI Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Master AXI Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000080000000">
+          <DESCRIPTION>Master AXI Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000807fffff">
+          <DESCRIPTION>Master AXI High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000003000000020000000100000000">
+          <DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e10005f5e10005f5e10005f5e100">
+          <DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100">
+          <DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111110101">
+          <DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111101111">
+          <DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Propagate USER Signals</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="5">
+          <DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="5">
+          <DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>WUSER Signal Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>RUSER Signal Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>BUSER Signal Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001f">
+          <DESCRIPTION>AXI Connectivity</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111100000">
+          <DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110">
+          <DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000400000001000000010000000100000020">
+          <DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004000000010000000200000002">
+          <DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004">
+          <DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004">
+          <DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Secure</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000">
+          <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000">
+          <DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000010000000100000001">
+          <DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000010000000100000001">
+          <DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000010000000100000001">
+          <DESCRIPTION>Slave AXI W Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000010000000100000001">
+          <DESCRIPTION>Slave AXI R Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000010000000100000001">
+          <DESCRIPTION>Slave AXI B Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Master AXI AW Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Master AXI AR Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Master AXI W Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Master AXI R Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Master AXI B Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Interconnect Architecture</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Generate Interrupts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
+          <DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
+          <DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Simulation debug</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="interconnect_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="2" MSB="4" NAME="S_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARESETN" DIR="O" MPD_INDEX="3" NAME="M_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT DEF_SIGNAME="clk_100_0000MHzPLL0&amp;clk_100_0000MHzPLL0&amp;clk_100_0000MHzPLL0&amp;clk_100_0000MHzPLL0&amp;clk_100_0000MHzPLL0" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="5" MSB="4" NAME="S_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0&amp;clk_100_0000MHzPLL0&amp;clk_100_0000MHzPLL0&amp;clk_100_0000MHzPLL0&amp;clk_100_0000MHzPLL0" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
+          <SIGNALS>
+            <SIGNAL NAME="clk_100_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_100_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_100_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_100_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_100_0000MHzPLL0"/>
+          </SIGNALS>
+        </PORT>
+        <PORT DEF_SIGNAME="axi4_0_S_AWID" DIR="I" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="6" MSB="14" NAME="S_AXI_AWID" RIGHT="0" SIGNAME="axi4_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="159" LSB="0" MPD_INDEX="7" MSB="159" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="39" LSB="0" MPD_INDEX="8" MSB="39" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="9" MSB="14" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="10" MSB="9" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="11" MSB="9" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="19" LSB="0" MPD_INDEX="12" MSB="19" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="13" MSB="14" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="19" LSB="0" MPD_INDEX="14" MSB="19" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWUSER" DIR="I" ENDIAN="LITTLE" LEFT="24" LSB="0" MPD_INDEX="15" MSB="24" NAME="S_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWVALID" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="16" MSB="4" NAME="S_AXI_AWVALID" RIGHT="0" SIGNAME="axi4_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_AWREADY" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="17" MSB="4" NAME="S_AXI_AWREADY" RIGHT="0" SIGNAME="axi4_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="159" LSB="0" MPD_INDEX="18" MSB="159" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="19" LSB="0" MPD_INDEX="19" MSB="19" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_WLAST" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="20" MSB="4" NAME="S_AXI_WLAST" RIGHT="0" SIGNAME="axi4_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_WUSER" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="21" MSB="4" NAME="S_AXI_WUSER" RIGHT="0" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_WVALID" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="22" MSB="4" NAME="S_AXI_WVALID" RIGHT="0" SIGNAME="axi4_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_WREADY" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="23" MSB="4" NAME="S_AXI_WREADY" RIGHT="0" SIGNAME="axi4_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_BID" DIR="O" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="24" MSB="14" NAME="S_AXI_BID" RIGHT="0" SIGNAME="axi4_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="25" MSB="9" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_BUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="26" MSB="4" NAME="S_AXI_BUSER" RIGHT="0" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_BVALID" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="27" MSB="4" NAME="S_AXI_BVALID" RIGHT="0" SIGNAME="axi4_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_BREADY" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="28" MSB="4" NAME="S_AXI_BREADY" RIGHT="0" SIGNAME="axi4_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARID" DIR="I" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="29" MSB="14" NAME="S_AXI_ARID" RIGHT="0" SIGNAME="axi4_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="159" LSB="0" MPD_INDEX="30" MSB="159" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="39" LSB="0" MPD_INDEX="31" MSB="39" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="32" MSB="14" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="33" MSB="9" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="34" MSB="9" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="19" LSB="0" MPD_INDEX="35" MSB="19" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="36" MSB="14" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="19" LSB="0" MPD_INDEX="37" MSB="19" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARUSER" DIR="I" ENDIAN="LITTLE" LEFT="24" LSB="0" MPD_INDEX="38" MSB="24" NAME="S_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARVALID" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="39" MSB="4" NAME="S_AXI_ARVALID" RIGHT="0" SIGNAME="axi4_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_ARREADY" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="40" MSB="4" NAME="S_AXI_ARREADY" RIGHT="0" SIGNAME="axi4_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_RID" DIR="O" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="41" MSB="14" NAME="S_AXI_RID" RIGHT="0" SIGNAME="axi4_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="159" LSB="0" MPD_INDEX="42" MSB="159" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="43" MSB="9" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_RLAST" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="44" MSB="4" NAME="S_AXI_RLAST" RIGHT="0" SIGNAME="axi4_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_RUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="45" MSB="4" NAME="S_AXI_RUSER" RIGHT="0" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_RVALID" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="46" MSB="4" NAME="S_AXI_RVALID" RIGHT="0" SIGNAME="axi4_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_S_RREADY" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="47" MSB="4" NAME="S_AXI_RREADY" RIGHT="0" SIGNAME="axi4_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="48" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="49" MSB="2" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi4_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="52" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="53" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="55" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="56" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="57" MSB="3" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="59" MSB="4" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWVALID" DIR="O" MPD_INDEX="60" NAME="M_AXI_AWVALID" SIGNAME="axi4_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_AWREADY" DIR="I" MPD_INDEX="61" NAME="M_AXI_AWREADY" SIGNAME="axi4_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="62" MSB="2" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi4_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="64" MSB="3" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_WLAST" DIR="O" MPD_INDEX="65" NAME="M_AXI_WLAST" SIGNAME="axi4_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_WUSER" DIR="O" MPD_INDEX="66" NAME="M_AXI_WUSER" SIGNAME="axi4_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_WVALID" DIR="O" MPD_INDEX="67" NAME="M_AXI_WVALID" SIGNAME="axi4_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_WREADY" DIR="I" MPD_INDEX="68" NAME="M_AXI_WREADY" SIGNAME="axi4_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="69" MSB="2" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi4_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_BUSER" DIR="I" MPD_INDEX="71" NAME="M_AXI_BUSER" SIGNAME="axi4_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_BVALID" DIR="I" MPD_INDEX="72" NAME="M_AXI_BVALID" SIGNAME="axi4_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_BREADY" DIR="O" MPD_INDEX="73" NAME="M_AXI_BREADY" SIGNAME="axi4_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="74" MSB="2" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi4_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="75" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="76" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="77" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="78" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="79" MSB="1" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="81" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="82" MSB="3" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="83" MSB="3" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="84" MSB="4" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARVALID" DIR="O" MPD_INDEX="85" NAME="M_AXI_ARVALID" SIGNAME="axi4_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_ARREADY" DIR="I" MPD_INDEX="86" NAME="M_AXI_ARREADY" SIGNAME="axi4_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="87" MSB="2" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi4_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="88" MSB="31" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="89" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_RLAST" DIR="I" MPD_INDEX="90" NAME="M_AXI_RLAST" SIGNAME="axi4_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_RUSER" DIR="I" MPD_INDEX="91" NAME="M_AXI_RUSER" SIGNAME="axi4_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_RVALID" DIR="I" MPD_INDEX="92" NAME="M_AXI_RVALID" SIGNAME="axi4_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4_0_M_RREADY" DIR="O" MPD_INDEX="93" NAME="M_AXI_RREADY" SIGNAME="axi4_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="interconnect_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+    </MODULE>
+    <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4lite_0" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="axi_interconnect">
+      <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Base Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Number of Slave Slots </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="8">
+          <DESCRIPTION>Number of Master Slots </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>AXI ID Widgth </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Widgth </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
+          <DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
+          <DESCRIPTION>Master AXI Data Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002">
+          <DESCRIPTION>AXI Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000200000002000000020000000200000002000000020000000200000002">
+          <DESCRIPTION>Master AXI Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041c00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041200000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041e00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041240000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040020000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040600000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000074800000">
+          <DESCRIPTION>Master AXI Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000041c0ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004120ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000041e0ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004127ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004002ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004060ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007480ffff">
+          <DESCRIPTION>Master AXI High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100">
+          <DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000010000000100000001000000010000000100000001000000010000000102faf08002faf08005f5e10002faf08002faf08002faf08002faf08002faf080">
+          <DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="50000000">
+          <DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Propagate USER Signals</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>WUSER Signal Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>RUSER Signal Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>BUSER Signal Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff">
+          <DESCRIPTION>AXI Connectivity</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110">
+          <DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Secure</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
+          <DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
+          <DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
+          <DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Slave AXI W Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Slave AXI R Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
+          <DESCRIPTION>Slave AXI B Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Master AXI AW Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Master AXI AR Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Master AXI W Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Master AXI R Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001">
+          <DESCRIPTION>Master AXI B Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Interconnect Architecture</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Generate Interrupts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
+          <DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
+          <DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Simulation debug</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/>
+        <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4lite_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="3" MSB="7" NAME="M_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWID" DIR="I" MPD_INDEX="6" NAME="S_AXI_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi4lite_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="18" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="19" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="I" MPD_INDEX="20" NAME="S_AXI_WLAST" SIGNAME="axi4lite_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_WUSER" DIR="I" MPD_INDEX="21" NAME="S_AXI_WUSER" SIGNAME="axi4lite_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="I" MPD_INDEX="22" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="O" MPD_INDEX="23" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_BID" DIR="O" MPD_INDEX="24" NAME="S_AXI_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_BUSER" DIR="O" MPD_INDEX="26" NAME="S_AXI_BUSER" SIGNAME="axi4lite_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="O" MPD_INDEX="27" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="I" MPD_INDEX="28" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARID" DIR="I" MPD_INDEX="29" NAME="S_AXI_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="30" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="31" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="32" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="33" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="35" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="36" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="37" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARUSER" DIR="I" MPD_INDEX="38" NAME="S_AXI_ARUSER" SIGNAME="axi4lite_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="O" MPD_INDEX="40" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_RID" DIR="O" MPD_INDEX="41" NAME="S_AXI_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="42" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="43" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="O" MPD_INDEX="44" NAME="S_AXI_RLAST" SIGNAME="axi4lite_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_RUSER" DIR="O" MPD_INDEX="45" NAME="S_AXI_RUSER" SIGNAME="axi4lite_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="O" MPD_INDEX="46" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="I" MPD_INDEX="47" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_100_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="48" MSB="7" NAME="M_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_100_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0&amp;clk_50_0000MHzPLL0" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
+          <SIGNALS>
+            <SIGNAL NAME="clk_50_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_50_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_100_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_50_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_50_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_50_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_50_0000MHzPLL0"/>
+            <SIGNAL NAME="clk_50_0000MHzPLL0"/>
+          </SIGNALS>
+        </PORT>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="49" MSB="7" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi4lite_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="255" LSB="0" MPD_INDEX="50" MSB="255" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="51" MSB="63" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="52" MSB="23" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="53" MSB="15" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="54" MSB="15" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="55" MSB="31" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="56" MSB="23" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="57" MSB="31" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4lite_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="58" MSB="31" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="59" MSB="7" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4lite_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="60" MSB="7" NAME="M_AXI_AWVALID" RIGHT="0" SIGNAME="axi4lite_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="61" MSB="7" NAME="M_AXI_AWREADY" RIGHT="0" SIGNAME="axi4lite_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="62" MSB="7" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi4lite_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="255" LSB="0" MPD_INDEX="63" MSB="255" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="64" MSB="31" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_WLAST" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="65" MSB="7" NAME="M_AXI_WLAST" RIGHT="0" SIGNAME="axi4lite_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_WUSER" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="66" MSB="7" NAME="M_AXI_WUSER" RIGHT="0" SIGNAME="axi4lite_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="67" MSB="7" NAME="M_AXI_WVALID" RIGHT="0" SIGNAME="axi4lite_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="68" MSB="7" NAME="M_AXI_WREADY" RIGHT="0" SIGNAME="axi4lite_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="69" MSB="7" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi4lite_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="70" MSB="15" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_BUSER" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="71" MSB="7" NAME="M_AXI_BUSER" RIGHT="0" SIGNAME="axi4lite_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="72" MSB="7" NAME="M_AXI_BVALID" RIGHT="0" SIGNAME="axi4lite_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="73" MSB="7" NAME="M_AXI_BREADY" RIGHT="0" SIGNAME="axi4lite_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="74" MSB="7" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi4lite_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="255" LSB="0" MPD_INDEX="75" MSB="255" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="76" MSB="63" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="77" MSB="23" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="78" MSB="15" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="79" MSB="15" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="80" MSB="31" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="81" MSB="23" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="82" MSB="31" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4lite_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="83" MSB="31" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="84" MSB="7" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4lite_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="85" MSB="7" NAME="M_AXI_ARVALID" RIGHT="0" SIGNAME="axi4lite_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="86" MSB="7" NAME="M_AXI_ARREADY" RIGHT="0" SIGNAME="axi4lite_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="87" MSB="7" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi4lite_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="255" LSB="0" MPD_INDEX="88" MSB="255" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="89" MSB="15" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_RLAST" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="90" MSB="7" NAME="M_AXI_RLAST" RIGHT="0" SIGNAME="axi4lite_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_RUSER" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="91" MSB="7" NAME="M_AXI_RUSER" RIGHT="0" SIGNAME="axi4lite_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="92" MSB="7" NAME="M_AXI_RVALID" RIGHT="0" SIGNAME="axi4lite_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="93" MSB="7" NAME="M_AXI_RREADY" RIGHT="0" SIGNAME="axi4lite_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+    </MODULE>
+    <MODULE HWVERSION="8.10.a" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="2" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE">
+      <DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">The MicroBlaze 32 bit soft processor</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_10_a/doc/microblaze.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="100000000"/>
+        <PARAMETER MPD_INDEX="2" NAME="C_DATA_SIZE" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="3" NAME="C_DYNAMIC_BUS_SIZING" TYPE="integer" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_INSTANCE" TYPE="string" VALUE="microblaze_0"/>
+        <PARAMETER MPD_INDEX="6" NAME="C_FAULT_TOLERANT" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Fault Tolerance Support</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_ECC_USE_CE_EXCEPTION" TYPE="integer" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_ENDIANNESS" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="9" NAME="C_AREA_OPTIMIZED" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Select implementation to optimize area (with lower instruction throughput)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_OPTIMIZATION" TYPE="integer" VALUE="0"/>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="11" NAME="C_INTERCONNECT" TYPE="integer" VALUE="2">
+          <DESCRIPTION>Select Bus Interfaces</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="12" NAME="C_STREAM_INTERCONNECT" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Select Stream Interfaces</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="13" NAME="C_DPLB_DWIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="14" NAME="C_DPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="15" NAME="C_DPLB_BURST_EN" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="16" NAME="C_DPLB_P2P" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="17" NAME="C_IPLB_DWIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="18" NAME="C_IPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="19" NAME="C_IPLB_BURST_EN" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="20" NAME="C_IPLB_P2P" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="21" NAME="C_M_AXI_DP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="22" NAME="C_M_AXI_DP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="23" NAME="C_M_AXI_DP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_DP_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_DP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="26" NAME="C_M_AXI_DP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="27" NAME="C_M_AXI_DP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="28" NAME="C_M_AXI_DP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
+        <PARAMETER MPD_INDEX="29" NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="30" NAME="C_INTERCONNECT_M_AXI_DP_READ_ISSUING" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="31" NAME="C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="32" NAME="C_M_AXI_IP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="33" NAME="C_M_AXI_IP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_IP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="35" NAME="C_M_AXI_IP_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="36" NAME="C_M_AXI_IP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="37" NAME="C_M_AXI_IP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="38" NAME="C_M_AXI_IP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_IP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
+        <PARAMETER MPD_INDEX="40" NAME="C_INTERCONNECT_M_AXI_IP_READ_ISSUING" TYPE="integer" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="41" NAME="C_D_AXI" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="42" NAME="C_D_PLB" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="43" NAME="C_D_LMB" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="44" NAME="C_I_AXI" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="45" NAME="C_I_PLB" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="46" NAME="C_I_LMB" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="47" NAME="C_USE_MSR_INSTR" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Additional Machine Status Register Instructions</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="48" NAME="C_USE_PCMP_INSTR" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Pattern Comparator</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="49" NAME="C_USE_BARREL" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Barrel Shifter</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="50" NAME="C_USE_DIV" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Integer Divider</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="51" NAME="C_USE_HW_MUL" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Integer Multiplier</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="52" NAME="C_USE_FPU" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Floating Point Unit</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="53" NAME="C_UNALIGNED_EXCEPTIONS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Unaligned Data Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="54" NAME="C_ILL_OPCODE_EXCEPTION" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Illegal Instruction Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="55" NAME="C_M_AXI_I_BUS_EXCEPTION" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Instruction-side AXI Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="56" NAME="C_M_AXI_D_BUS_EXCEPTION" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Data-side AXI Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="57" NAME="C_IPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Instruction-side PLB Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="58" NAME="C_DPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Data-side PLB Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="59" NAME="C_DIV_ZERO_EXCEPTION" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Integer Divide Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="60" NAME="C_FPU_EXCEPTION" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Floating Point Unit Exceptions</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="61" NAME="C_FSL_EXCEPTION" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Stream Exception</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="62" NAME="C_USE_STACK_PROTECTION" TYPE="integer" VALUE="0">
+          <DESCRIPTION>&lt;qt&gt;Enable stack protection&lt;/qt&gt;</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="63" NAME="C_PVR" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Specifies Processor Version Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ENDIAN="BIG" LSB="7" MPD_INDEX="64" MSB="0" NAME="C_PVR_USER1" TYPE="std_logic_vector" VALUE="0x00">
+          <DESCRIPTION>Specify USER1 Bits in Processor Version Register</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="65" MSB="0" NAME="C_PVR_USER2" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>Specify USER2 Bits in Processor Version Registers</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="66" NAME="C_DEBUG_ENABLED" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable MicroBlaze Debug Module Interface</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="29" MPD_INDEX="67" NAME="C_NUMBER_OF_PC_BRK" TYPE="integer" VALUE="7">
+          <DESCRIPTION>Number of PC Breakpoints </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="31" MPD_INDEX="68" NAME="C_NUMBER_OF_RD_ADDR_BRK" TYPE="integer" VALUE="2">
+          <DESCRIPTION>Number of Read Address Watchpoints </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="30" MPD_INDEX="69" NAME="C_NUMBER_OF_WR_ADDR_BRK" TYPE="integer" VALUE="2">
+          <DESCRIPTION>Number of Write Address Watchpoints </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="70" NAME="C_INTERRUPT_IS_EDGE" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Sense Interrupt on Edge vs. Level </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="71" NAME="C_EDGE_IS_POSITIVE" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Sense Interrupt on Rising vs. Falling Edge </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="72" NAME="C_RESET_MSR" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>Specify Reset Value for Select MSR Bits</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="73" NAME="C_OPCODE_0x0_ILLEGAL" TYPE="integer" VALUE="0">
+          <DESCRIPTION>&lt;qt&gt;Generate Illegal Instruction Exception for NULL Instruction&lt;/qt&gt;</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="74" NAME="C_FSL_LINKS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Number of Stream Links </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="75" NAME="C_FSL_DATA_SIZE" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="76" NAME="C_USE_EXTENDED_FSL_INSTR" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Additional Stream Instructions</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="77" NAME="C_M0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="78" NAME="C_S0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="79" NAME="C_M1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="80" NAME="C_S1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="81" NAME="C_M2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="82" NAME="C_S2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="83" NAME="C_M3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="84" NAME="C_S3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="85" NAME="C_M4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="86" NAME="C_S4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="87" NAME="C_M5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="88" NAME="C_S5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="89" NAME="C_M6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="90" NAME="C_S6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="91" NAME="C_M7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="92" NAME="C_S7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="93" NAME="C_M8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="94" NAME="C_S8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="95" NAME="C_M9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="96" NAME="C_S9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="97" NAME="C_M10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="98" NAME="C_S10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="99" NAME="C_M11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="100" NAME="C_S11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="101" NAME="C_M12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="102" NAME="C_S12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="103" NAME="C_M13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="104" NAME="C_S13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="105" NAME="C_M14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="106" NAME="C_S14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="107" NAME="C_M15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="108" NAME="C_S15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
+        <PARAMETER MPD_INDEX="109" NAME="C_M0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="110" NAME="C_S0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="111" NAME="C_M1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="112" NAME="C_S1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="113" NAME="C_M2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="114" NAME="C_S2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="115" NAME="C_M3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="116" NAME="C_S3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="117" NAME="C_M4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="118" NAME="C_S4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="119" NAME="C_M5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="120" NAME="C_S5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="121" NAME="C_M6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="122" NAME="C_S6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="123" NAME="C_M7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="124" NAME="C_S7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="125" NAME="C_M8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="126" NAME="C_S8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="127" NAME="C_M9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="128" NAME="C_S9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="129" NAME="C_M10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="130" NAME="C_S10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="131" NAME="C_M11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="132" NAME="C_S11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="133" NAME="C_M12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="134" NAME="C_S12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="135" NAME="C_M13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="136" NAME="C_S13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="137" NAME="C_M14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="138" NAME="C_S14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="139" NAME="C_M15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="140" NAME="C_S15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="141" NAME="C_ICACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000">
+          <DESCRIPTION>I-Cache Base Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="142" NAME="C_ICACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc7ffffff">
+          <DESCRIPTION>I-Cache High Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="143" NAME="C_USE_ICACHE" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Instruction Cache </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="144" NAME="C_ALLOW_ICACHE_WR" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable I-Cache Writes</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="145" NAME="C_ADDR_TAG_BITS" TYPE="integer" VALUE="13"/>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="32" MPD_INDEX="146" NAME="C_CACHE_BYTE_SIZE" TYPE="integer" VALUE="16384">
+          <DESCRIPTION>Size of the I-Cache in Bytes</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="147" NAME="C_ICACHE_USE_FSL" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="148" NAME="C_ICACHE_LINE_LEN" TYPE="integer" VALUE="4">
+          <DESCRIPTION>Instruction Cache Line Length</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="149" NAME="C_ICACHE_ALWAYS_USED" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Use Cache Links for All I-Cache Memory Accesses </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="150" NAME="C_ICACHE_INTERFACE" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="151" NAME="C_ICACHE_VICTIMS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Number of I-Cache Victims</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="152" NAME="C_ICACHE_STREAMS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Number of I-Cache Streams</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="153" NAME="C_ICACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Use Distributed RAM for I-Cache Tags</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="154" NAME="C_ICACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="155" NAME="C_M_AXI_IC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="156" NAME="C_M_AXI_IC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="157" NAME="C_M_AXI_IC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="158" NAME="C_M_AXI_IC_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="159" NAME="C_M_AXI_IC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="160" NAME="C_M_AXI_IC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="161" NAME="C_M_AXI_IC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="162" NAME="C_M_AXI_IC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
+        <PARAMETER MPD_INDEX="163" NAME="C_M_AXI_IC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
+        <PARAMETER MPD_INDEX="164" NAME="C_M_AXI_IC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="165" NAME="C_M_AXI_IC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
+        <PARAMETER MPD_INDEX="166" NAME="C_M_AXI_IC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
+        <PARAMETER MPD_INDEX="167" NAME="C_M_AXI_IC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="168" NAME="C_M_AXI_IC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="169" NAME="C_M_AXI_IC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="170" NAME="C_INTERCONNECT_M_AXI_IC_READ_ISSUING" TYPE="integer" VALUE="2"/>
+        <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="171" NAME="C_DCACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000">
+          <DESCRIPTION>D-Cache Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="172" NAME="C_DCACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc7ffffff">
+          <DESCRIPTION>D-Cache High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="173" NAME="C_USE_DCACHE" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable Data Cache</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="174" NAME="C_ALLOW_DCACHE_WR" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Enable D-Cache Writes</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="175" NAME="C_DCACHE_ADDR_TAG" TYPE="integer" VALUE="13"/>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="33" MPD_INDEX="176" NAME="C_DCACHE_BYTE_SIZE" TYPE="integer" VALUE="16384">
+          <DESCRIPTION>Size of D-Cache in Bytes</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="177" NAME="C_DCACHE_USE_FSL" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="178" NAME="C_DCACHE_LINE_LEN" TYPE="integer" VALUE="4">
+          <DESCRIPTION>Data Cache Line Length</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="179" NAME="C_DCACHE_ALWAYS_USED" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Use Cache Links for All D-Cache Memory Accesses </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="180" NAME="C_DCACHE_INTERFACE" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="181" NAME="C_DCACHE_USE_WRITEBACK" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Write-back Storage Policy</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="182" NAME="C_DCACHE_VICTIMS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Number of D-Cache Victims</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="183" NAME="C_DCACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Use Distributed RAM for D-Cache Tags</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="184" NAME="C_DCACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="185" NAME="C_M_AXI_DC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="186" NAME="C_M_AXI_DC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="187" NAME="C_M_AXI_DC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="188" NAME="C_M_AXI_DC_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="189" NAME="C_M_AXI_DC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="190" NAME="C_M_AXI_DC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="191" NAME="C_M_AXI_DC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="192" NAME="C_M_AXI_DC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
+        <PARAMETER MPD_INDEX="193" NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
+        <PARAMETER MPD_INDEX="194" NAME="C_M_AXI_DC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
+        <PARAMETER MPD_INDEX="195" NAME="C_M_AXI_DC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="196" NAME="C_M_AXI_DC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
+        <PARAMETER MPD_INDEX="197" NAME="C_M_AXI_DC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
+        <PARAMETER MPD_INDEX="198" NAME="C_M_AXI_DC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="199" NAME="C_M_AXI_DC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="200" NAME="C_M_AXI_DC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="201" NAME="C_INTERCONNECT_M_AXI_DC_READ_ISSUING" TYPE="integer" VALUE="2"/>
+        <PARAMETER MPD_INDEX="202" NAME="C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING" TYPE="integer" VALUE="32"/>
+        <PARAMETER MPD_INDEX="203" NAME="C_USE_MMU" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Memory Management</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="204" NAME="C_MMU_DTLB_SIZE" TYPE="integer" VALUE="4">
+          <DESCRIPTION>Data Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="205" NAME="C_MMU_ITLB_SIZE" TYPE="integer" VALUE="2">
+          <DESCRIPTION>Instruction Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="206" NAME="C_MMU_TLB_ACCESS" TYPE="integer" VALUE="3">
+          <DESCRIPTION>Enable Access to Memory Management Special Registers</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="207" NAME="C_MMU_ZONES" TYPE="integer" VALUE="16">
+          <DESCRIPTION>Number of Memory Protection Zones</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="208" NAME="C_MMU_PRIVILEGED_INSTR" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Privileged Instructions</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="209" NAME="C_USE_INTERRUPT" TYPE="integer" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="210" NAME="C_USE_EXT_BRK" TYPE="integer" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="211" NAME="C_USE_EXT_NM_BRK" TYPE="integer" VALUE="1"/>
+        <PARAMETER MPD_INDEX="212" NAME="C_USE_BRANCH_TARGET_CACHE" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Enable Branch Target Cache</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="213" NAME="C_BRANCH_TARGET_CACHE_SIZE" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Branch Target Cache Size</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_M_AXI_DC_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_M_AXI_DC_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" NAME="C_INTERCONNECT_M_AXI_DP_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" NAME="C_INTERCONNECT_M_AXI_DP_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="18" NAME="C_INTERCONNECT_M_AXI_DP_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="19" NAME="C_INTERCONNECT_M_AXI_DP_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="20" NAME="C_INTERCONNECT_M_AXI_DP_B_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="21" NAME="C_INTERCONNECT_M_AXI_DC_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="22" NAME="C_INTERCONNECT_M_AXI_DC_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="23" NAME="C_INTERCONNECT_M_AXI_DC_B_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="24" NAME="C_INTERCONNECT_M_AXI_IC_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="25" NAME="C_INTERCONNECT_M_AXI_IC_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="26" NAME="C_INTERCONNECT_M_AXI_IC_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="27" NAME="C_INTERCONNECT_M_AXI_IC_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="28" NAME="C_INTERCONNECT_M_AXI_IC_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="MB_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/>
+        <PORT BUS="DPLB:IPLB:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt"/>
+        <PORT BUS="DLMB:ILMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="RESET" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
+        <PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_BRK" SIGNAME="Ext_BRK"/>
+        <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="5" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK"/>
+        <PORT DIR="I" MPD_INDEX="6" NAME="DBG_STOP" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="7" NAME="MB_Halted" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="8" NAME="MB_Error" SIGNAME="__NOC__"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="INSTR" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="I" MPD_INDEX="10" NAME="IREADY" SIGNAME="microblaze_0_ilmb_LMB_Ready"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="I" MPD_INDEX="11" NAME="IWAIT" SIGNAME="microblaze_0_ilmb_LMB_Wait"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="I" MPD_INDEX="12" NAME="ICE" SIGNAME="microblaze_0_ilmb_LMB_CE"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="I" MPD_INDEX="13" NAME="IUE" SIGNAME="microblaze_0_ilmb_LMB_UE"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="INSTR_ADDR" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:31]"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="IFETCH" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/>
+        <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="O" MPD_INDEX="16" NAME="I_AS" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="17" NAME="IPLB_M_ABort" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="IPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="IPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="20" MSB="0" NAME="IPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_IPLB_DWIDTH-1)/8]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="21" NAME="IPLB_M_busLock" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="22" NAME="IPLB_M_lockErr" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="IPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="IPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="25" NAME="IPLB_M_rdBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="26" NAME="IPLB_M_request" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="27" NAME="IPLB_M_RNW" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="28" MSB="0" NAME="IPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="29" MSB="0" NAME="IPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="30" MSB="0" NAME="IPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="IPLB_M_wrBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="32" MSB="0" NAME="IPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="IPLB_MBusy" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="IPLB_MRdErr" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="35" NAME="IPLB_MWrErr" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="36" NAME="IPLB_MIRQ" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="37" NAME="IPLB_MWrBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="38" NAME="IPLB_MWrDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="IPLB_MAddrAck" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="40" NAME="IPLB_MRdBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="IPLB_MRdDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="42" MSB="0" NAME="IPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="43" MSB="0" NAME="IPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="IPLB_MRearbitrate" SIGNAME="__NOC__"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="IPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="IPLB_MTimeout" SIGNAME="__NOC__"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="DATA_READ" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="I" MPD_INDEX="48" NAME="DREADY" SIGNAME="microblaze_0_dlmb_LMB_Ready"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="I" MPD_INDEX="49" NAME="DWAIT" SIGNAME="microblaze_0_dlmb_LMB_Wait"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="I" MPD_INDEX="50" NAME="DCE" SIGNAME="microblaze_0_dlmb_LMB_CE"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="I" MPD_INDEX="51" NAME="DUE" SIGNAME="microblaze_0_dlmb_LMB_UE"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="52" MSB="0" NAME="DATA_WRITE" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:31]"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="53" MSB="0" NAME="DATA_ADDR" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:31]"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="O" MPD_INDEX="54" NAME="D_AS" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="O" MPD_INDEX="55" NAME="READ_STROBE" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="O" MPD_INDEX="56" NAME="WRITE_STROBE" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/>
+        <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="BYTE_ENABLE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:3]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="DPLB_M_ABort" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="59" MSB="0" NAME="DPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="60" MSB="0" NAME="DPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="61" MSB="0" NAME="DPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_DPLB_DWIDTH-1)/8]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="62" NAME="DPLB_M_busLock" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="63" NAME="DPLB_M_lockErr" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="64" MSB="0" NAME="DPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="65" MSB="0" NAME="DPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="66" NAME="DPLB_M_rdBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="67" NAME="DPLB_M_request" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="68" NAME="DPLB_M_RNW" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="69" MSB="0" NAME="DPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="70" MSB="0" NAME="DPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="71" MSB="0" NAME="DPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="72" NAME="DPLB_M_wrBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="73" MSB="0" NAME="DPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="DPLB_MBusy" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="DPLB_MRdErr" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="76" NAME="DPLB_MWrErr" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="DPLB_MIRQ" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="DPLB_MWrBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="DPLB_MWrDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="80" NAME="DPLB_MAddrAck" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="81" NAME="DPLB_MRdBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="DPLB_MRdDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="83" MSB="0" NAME="DPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="84" MSB="0" NAME="DPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="85" NAME="DPLB_MRearbitrate" SIGNAME="__NOC__"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="86" MSB="0" NAME="DPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="87" NAME="DPLB_MTimeout" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="M_AXI_IP_AWID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="89" MSB="31" NAME="M_AXI_IP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="90" MSB="7" NAME="M_AXI_IP_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="91" MSB="2" NAME="M_AXI_IP_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="92" MSB="1" NAME="M_AXI_IP_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="M_AXI_IP_AWLOCK" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="94" MSB="3" NAME="M_AXI_IP_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="95" MSB="2" NAME="M_AXI_IP_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="96" MSB="3" NAME="M_AXI_IP_AWQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="M_AXI_IP_AWVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="M_AXI_IP_AWREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="99" MSB="31" NAME="M_AXI_IP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="100" MSB="3" NAME="M_AXI_IP_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_M_AXI_IP_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="M_AXI_IP_WLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="M_AXI_IP_WVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="M_AXI_IP_WREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="M_AXI_IP_BID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="105" MSB="1" NAME="M_AXI_IP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="106" NAME="M_AXI_IP_BVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="107" NAME="M_AXI_IP_BREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="M_AXI_IP_ARID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="109" MSB="31" NAME="M_AXI_IP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="110" MSB="7" NAME="M_AXI_IP_ARLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="111" MSB="2" NAME="M_AXI_IP_ARSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="112" MSB="1" NAME="M_AXI_IP_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="M_AXI_IP_ARLOCK" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="114" MSB="3" NAME="M_AXI_IP_ARCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="115" MSB="2" NAME="M_AXI_IP_ARPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="116" MSB="3" NAME="M_AXI_IP_ARQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="M_AXI_IP_ARVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="118" NAME="M_AXI_IP_ARREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="119" NAME="M_AXI_IP_RID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="120" MSB="31" NAME="M_AXI_IP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="121" MSB="1" NAME="M_AXI_IP_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="122" NAME="M_AXI_IP_RLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="M_AXI_IP_RVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="124" NAME="M_AXI_IP_RREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWID" DIR="O" MPD_INDEX="125" NAME="M_AXI_DP_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="126" MSB="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="M_AXI_DP_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="128" MSB="2" NAME="M_AXI_DP_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="129" MSB="1" NAME="M_AXI_DP_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="O" MPD_INDEX="130" NAME="M_AXI_DP_AWLOCK" SIGNAME="axi4lite_0_S_AWLOCK"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="131" MSB="3" NAME="M_AXI_DP_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="132" MSB="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="133" MSB="3" NAME="M_AXI_DP_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="O" MPD_INDEX="134" NAME="M_AXI_DP_AWVALID" SIGNAME="axi4lite_0_S_AWVALID"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="I" MPD_INDEX="135" NAME="M_AXI_DP_AWREADY" SIGNAME="axi4lite_0_S_AWREADY"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="136" MSB="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="137" MSB="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DP_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="O" MPD_INDEX="138" NAME="M_AXI_DP_WLAST" SIGNAME="axi4lite_0_S_WLAST"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="O" MPD_INDEX="139" NAME="M_AXI_DP_WVALID" SIGNAME="axi4lite_0_S_WVALID"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="I" MPD_INDEX="140" NAME="M_AXI_DP_WREADY" SIGNAME="axi4lite_0_S_WREADY"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BID" DIR="I" MPD_INDEX="141" NAME="M_AXI_DP_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="142" MSB="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="I" MPD_INDEX="143" NAME="M_AXI_DP_BVALID" SIGNAME="axi4lite_0_S_BVALID"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="O" MPD_INDEX="144" NAME="M_AXI_DP_BREADY" SIGNAME="axi4lite_0_S_BREADY"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARID" DIR="O" MPD_INDEX="145" NAME="M_AXI_DP_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="146" MSB="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="147" MSB="7" NAME="M_AXI_DP_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="148" MSB="2" NAME="M_AXI_DP_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="149" MSB="1" NAME="M_AXI_DP_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="O" MPD_INDEX="150" NAME="M_AXI_DP_ARLOCK" SIGNAME="axi4lite_0_S_ARLOCK"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="151" MSB="3" NAME="M_AXI_DP_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="152" MSB="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="153" MSB="3" NAME="M_AXI_DP_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="O" MPD_INDEX="154" NAME="M_AXI_DP_ARVALID" SIGNAME="axi4lite_0_S_ARVALID"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="I" MPD_INDEX="155" NAME="M_AXI_DP_ARREADY" SIGNAME="axi4lite_0_S_ARREADY"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RID" DIR="I" MPD_INDEX="156" NAME="M_AXI_DP_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="157" MSB="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="158" MSB="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="I" MPD_INDEX="159" NAME="M_AXI_DP_RLAST" SIGNAME="axi4lite_0_S_RLAST"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="I" MPD_INDEX="160" NAME="M_AXI_DP_RVALID" SIGNAME="axi4lite_0_S_RVALID"/>
+        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="O" MPD_INDEX="161" NAME="M_AXI_DP_RREADY" SIGNAME="axi4lite_0_S_RREADY"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="162" NAME="M_AXI_IC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="163" MSB="31" NAME="M_AXI_IC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="164" MSB="7" NAME="M_AXI_IC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="165" MSB="2" NAME="M_AXI_IC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="166" MSB="1" NAME="M_AXI_IC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="167" NAME="M_AXI_IC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="168" MSB="3" NAME="M_AXI_IC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="169" MSB="2" NAME="M_AXI_IC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="170" MSB="3" NAME="M_AXI_IC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="171" NAME="M_AXI_IC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="172" NAME="M_AXI_IC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="173" MSB="4" NAME="M_AXI_IC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_IC_AWUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="174" MSB="31" NAME="M_AXI_IC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="175" MSB="3" NAME="M_AXI_IC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_IC_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="176" NAME="M_AXI_IC_WLAST" SIGNAME="axi4_0_S_WLAST"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="177" NAME="M_AXI_IC_WVALID" SIGNAME="axi4_0_S_WVALID"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="178" NAME="M_AXI_IC_WREADY" SIGNAME="axi4_0_S_WREADY"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="179" NAME="M_AXI_IC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_IC_WUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="180" NAME="M_AXI_IC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="181" MSB="1" NAME="M_AXI_IC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="182" NAME="M_AXI_IC_BVALID" SIGNAME="axi4_0_S_BVALID"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="183" NAME="M_AXI_IC_BREADY" SIGNAME="axi4_0_S_BREADY"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="184" NAME="M_AXI_IC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_IC_BUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="185" NAME="M_AXI_IC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="M_AXI_IC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="187" MSB="7" NAME="M_AXI_IC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="188" MSB="2" NAME="M_AXI_IC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="189" MSB="1" NAME="M_AXI_IC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="190" NAME="M_AXI_IC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="191" MSB="3" NAME="M_AXI_IC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="192" MSB="2" NAME="M_AXI_IC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="193" MSB="3" NAME="M_AXI_IC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="194" NAME="M_AXI_IC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="195" NAME="M_AXI_IC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="196" MSB="4" NAME="M_AXI_IC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_IC_ARUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="197" NAME="M_AXI_IC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="198" MSB="31" NAME="M_AXI_IC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="199" MSB="1" NAME="M_AXI_IC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="200" NAME="M_AXI_IC_RLAST" SIGNAME="axi4_0_S_RLAST"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="201" NAME="M_AXI_IC_RVALID" SIGNAME="axi4_0_S_RVALID"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="202" NAME="M_AXI_IC_RREADY" SIGNAME="axi4_0_S_RREADY"/>
+        <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="203" NAME="M_AXI_IC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_IC_RUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="204" NAME="M_AXI_DC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="205" MSB="31" NAME="M_AXI_DC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="206" MSB="7" NAME="M_AXI_DC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="207" MSB="2" NAME="M_AXI_DC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="208" MSB="1" NAME="M_AXI_DC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="209" NAME="M_AXI_DC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="210" MSB="3" NAME="M_AXI_DC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="211" MSB="2" NAME="M_AXI_DC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="212" MSB="3" NAME="M_AXI_DC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="213" NAME="M_AXI_DC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="214" NAME="M_AXI_DC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="215" MSB="4" NAME="M_AXI_DC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_DC_AWUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="216" MSB="31" NAME="M_AXI_DC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="217" MSB="3" NAME="M_AXI_DC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DC_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="218" NAME="M_AXI_DC_WLAST" SIGNAME="axi4_0_S_WLAST"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="219" NAME="M_AXI_DC_WVALID" SIGNAME="axi4_0_S_WVALID"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="220" NAME="M_AXI_DC_WREADY" SIGNAME="axi4_0_S_WREADY"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="221" NAME="M_AXI_DC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_DC_WUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="222" NAME="M_AXI_DC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="223" MSB="1" NAME="M_AXI_DC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="224" NAME="M_AXI_DC_BVALID" SIGNAME="axi4_0_S_BVALID"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="225" NAME="M_AXI_DC_BREADY" SIGNAME="axi4_0_S_BREADY"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="226" NAME="M_AXI_DC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_DC_BUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="227" NAME="M_AXI_DC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="228" MSB="31" NAME="M_AXI_DC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="229" MSB="7" NAME="M_AXI_DC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="230" MSB="2" NAME="M_AXI_DC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="231" MSB="1" NAME="M_AXI_DC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="232" NAME="M_AXI_DC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="233" MSB="3" NAME="M_AXI_DC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="234" MSB="2" NAME="M_AXI_DC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="235" MSB="3" NAME="M_AXI_DC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="236" NAME="M_AXI_DC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="237" NAME="M_AXI_DC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="238" MSB="4" NAME="M_AXI_DC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_DC_ARUSER_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="239" NAME="M_AXI_DC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="240" MSB="31" NAME="M_AXI_DC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="241" MSB="1" NAME="M_AXI_DC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="242" NAME="M_AXI_DC_RLAST" SIGNAME="axi4_0_S_RLAST"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="243" NAME="M_AXI_DC_RVALID" SIGNAME="axi4_0_S_RVALID"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="244" NAME="M_AXI_DC_RREADY" SIGNAME="axi4_0_S_RREADY"/>
+        <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="245" NAME="M_AXI_DC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_DC_RUSER_WIDTH-1):0]"/>
+        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Clk" DIR="I" MPD_INDEX="246" NAME="DBG_CLK" SIGNAME="microblaze_0_debug_Dbg_Clk"/>
+        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_TDI" DIR="I" MPD_INDEX="247" NAME="DBG_TDI" SIGNAME="microblaze_0_debug_Dbg_TDI"/>
+        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_TDO" DIR="O" MPD_INDEX="248" NAME="DBG_TDO" SIGNAME="microblaze_0_debug_Dbg_TDO"/>
+        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Reg_En" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="249" MSB="0" NAME="DBG_REG_EN" RIGHT="7" SIGNAME="microblaze_0_debug_Dbg_Reg_En" VECFORMULA="[0:7]"/>
+        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Shift" DIR="I" MPD_INDEX="250" NAME="DBG_SHIFT" SIGNAME="microblaze_0_debug_Dbg_Shift"/>
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+      </PORTS>
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+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="2" NAME="DPLB" TYPE="MASTER">
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+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_busLock"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_lockErr"/>
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+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_priority"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_rdBurst"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_request"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_RNW"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_size"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_TAttribute"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_type"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrBurst"/>
+            <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrDBus"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MBusy"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MRdErr"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MWrErr"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MIRQ"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MWrBTerm"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MWrDAck"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MAddrAck"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MRdBTerm"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDAck"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDBus"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MRdWdAddr"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MRearbitrate"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MSSize"/>
+            <PORTMAP DIR="I" PHYSICAL="DPLB_MTimeout"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="3" NAME="IPLB" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABort"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABus"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_UABus"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_BE"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_busLock"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_lockErr"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_MSize"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_priority"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_rdBurst"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_request"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_RNW"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_size"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_TAttribute"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_type"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrBurst"/>
+            <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrDBus"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MBusy"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdErr"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MWrErr"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MIRQ"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MWrBTerm"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MWrDAck"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MAddrAck"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdBTerm"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDAck"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDBus"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdWdAddr"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MRearbitrate"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MSSize"/>
+            <PORTMAP DIR="I" PHYSICAL="IPLB_MTimeout"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
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+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="CLK"/>
+            <PORTMAP DIR="I" PHYSICAL="RESET"/>
+            <PORTMAP DIR="I" PHYSICAL="DATA_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="DREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="DWAIT"/>
+            <PORTMAP DIR="I" PHYSICAL="DCE"/>
+            <PORTMAP DIR="I" PHYSICAL="DUE"/>
+            <PORTMAP DIR="O" PHYSICAL="DATA_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="DATA_ADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="D_AS"/>
+            <PORTMAP DIR="O" PHYSICAL="READ_STROBE"/>
+            <PORTMAP DIR="O" PHYSICAL="WRITE_STROBE"/>
+            <PORTMAP DIR="O" PHYSICAL="BYTE_ENABLE"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="ILMB" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="CLK"/>
+            <PORTMAP DIR="I" PHYSICAL="RESET"/>
+            <PORTMAP DIR="I" PHYSICAL="INSTR"/>
+            <PORTMAP DIR="I" PHYSICAL="IREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="IWAIT"/>
+            <PORTMAP DIR="I" PHYSICAL="ICE"/>
+            <PORTMAP DIR="I" PHYSICAL="IUE"/>
+            <PORTMAP DIR="O" PHYSICAL="INSTR_ADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="IFETCH"/>
+            <PORTMAP DIR="O" PHYSICAL="I_AS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="M_AXI_DP" PROTOCOL="AXI4LITE" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" MPD_INDEX="5" NAME="M_AXI_IP" PROTOCOL="AXI4LITE" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_AWREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WSTRB"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_WREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_BREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_ARREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="104" NAME="M_AXI_DC" PROTOCOL="AXI4" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_AWREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWUSER"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WSTRB"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WUSER"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BUSER"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARUSER"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_RREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RUSER"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="5" MPD_INDEX="105" NAME="M_AXI_IC" PROTOCOL="AXI4" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_AWREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWUSER"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WSTRB"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WUSER"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BUSER"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARADDR"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLEN"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARSIZE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARBURST"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLOCK"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARCACHE"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARPROT"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARQOS"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARUSER"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RID"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RRESP"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_RREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RUSER"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="106" NAME="DEBUG" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="DBG_CLK"/>
+            <PORTMAP DIR="I" PHYSICAL="DBG_TDI"/>
+            <PORTMAP DIR="O" PHYSICAL="DBG_TDO"/>
+            <PORTMAP DIR="I" PHYSICAL="DBG_REG_EN"/>
+            <PORTMAP DIR="I" PHYSICAL="DBG_SHIFT"/>
+            <PORTMAP DIR="I" PHYSICAL="DBG_CAPTURE"/>
+            <PORTMAP DIR="I" PHYSICAL="DBG_UPDATE"/>
+            <PORTMAP DIR="I" PHYSICAL="DEBUG_RST"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBTRACE2" MPD_INDEX="107" NAME="TRACE" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Instruction"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Valid_Instr"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_PC"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Write"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Addr"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_MSR_Reg"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_PID_Reg"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_New_Reg_Value"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Taken"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Kind"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Taken"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Delay_Slot"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Address"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Access"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Read"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write_Value"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Byte_Enable"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Req"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Hit"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Rdy"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Read"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Req"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Hit"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Rdy"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_OF_PipeRun"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_EX_PipeRun"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_MEM_PipeRun"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_MB_Halted"/>
+            <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Hit"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="6" NAME="SFSL0" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="38" NAME="DRFSL0" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="7" NAME="MFSL0" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="39" NAME="DWFSL0" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="8" NAME="SFSL1" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="40" NAME="DRFSL1" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="9" NAME="MFSL1" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="41" NAME="DWFSL1" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="10" NAME="SFSL2" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="42" NAME="DRFSL2" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="11" NAME="MFSL2" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="43" NAME="DWFSL2" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="12" NAME="SFSL3" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="44" NAME="DRFSL3" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="13" NAME="MFSL3" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="45" NAME="DWFSL3" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="14" NAME="SFSL4" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="46" NAME="DRFSL4" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="15" NAME="MFSL4" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="47" NAME="DWFSL4" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="16" NAME="SFSL5" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="48" NAME="DRFSL5" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="17" NAME="MFSL5" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="49" NAME="DWFSL5" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="18" NAME="SFSL6" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="50" NAME="DRFSL6" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="19" NAME="MFSL6" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="51" NAME="DWFSL6" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="20" NAME="SFSL7" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="52" NAME="DRFSL7" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="21" NAME="MFSL7" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="53" NAME="DWFSL7" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="22" NAME="SFSL8" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="54" NAME="DRFSL8" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="23" NAME="MFSL8" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="55" NAME="DWFSL8" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="24" NAME="SFSL9" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="56" NAME="DRFSL9" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="25" NAME="MFSL9" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="57" NAME="DWFSL9" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="26" NAME="SFSL10" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="58" NAME="DRFSL10" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="27" NAME="MFSL10" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="59" NAME="DWFSL10" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="28" NAME="SFSL11" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="60" NAME="DRFSL11" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="29" NAME="MFSL11" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="61" NAME="DWFSL11" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="30" NAME="SFSL12" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="62" NAME="DRFSL12" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="31" NAME="MFSL12" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="63" NAME="DWFSL12" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="32" NAME="SFSL13" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="64" NAME="DRFSL13" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="33" NAME="MFSL13" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="65" NAME="DWFSL13" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="34" NAME="SFSL14" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="66" NAME="DRFSL14" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="35" NAME="MFSL14" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="67" NAME="DWFSL14" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="36" NAME="SFSL15" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="68" NAME="DRFSL15" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="37" NAME="MFSL15" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="69" NAME="DWFSL15" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="70" NAME="M0_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M0_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="71" NAME="S0_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S0_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="72" NAME="M1_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M1_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="73" NAME="S1_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S1_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="74" NAME="M2_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M2_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="75" NAME="S2_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S2_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="76" NAME="M3_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M3_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="77" NAME="S3_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S3_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="78" NAME="M4_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M4_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="79" NAME="S4_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S4_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="80" NAME="M5_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M5_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="81" NAME="S5_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S5_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="82" NAME="M6_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M6_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="83" NAME="S6_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S6_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="84" NAME="M7_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M7_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="85" NAME="S7_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S7_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="86" NAME="M8_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M8_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="87" NAME="S8_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S8_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="88" NAME="M9_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M9_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="89" NAME="S9_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S9_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="90" NAME="M10_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M10_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="91" NAME="S10_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S10_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="92" NAME="M11_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M11_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="93" NAME="S11_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S11_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="94" NAME="M12_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M12_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="95" NAME="S12_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S12_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="96" NAME="M13_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M13_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="97" NAME="S13_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S13_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="98" NAME="M14_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M14_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="99" NAME="S14_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S14_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="100" NAME="M15_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="M15_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="101" NAME="S15_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S15_AXIS_TREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="103" NAME="IXCL" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_EXISTS"/>
+            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_OUT_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="102" NAME="DXCL" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_READ"/>
+            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_DATA"/>
+            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_EXISTS"/>
+            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_WRITE"/>
+            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_DATA"/>
+            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CONTROL"/>
+            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_OUT_FULL"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001FFF" INSTANCE="microblaze_0_d_bram_ctrl" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_dlmb"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001FFF" INSTANCE="microblaze_0_i_bram_ctrl" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_ilmb"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480FFFF" INSTANCE="debug_module" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" INSTANCE="RS232_Uart_1" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" INSTANCE="LEDs_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" INSTANCE="Push_Buttons_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="1092878336" BASENAME="C_BASEADDR" BASEVALUE="0x41240000" HIGHDECIMAL="1093140479" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4127ffff" INSTANCE="ETHERNET" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="262144" SIZEABRV="256K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="1105199104" BASENAME="C_BASEADDR" BASEVALUE="0x41e00000" HIGHDECIMAL="1105264639" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41e0ffff" INSTANCE="ETHERNET_dma" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" INSTANCE="microblaze_0_intc" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="2147483648" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0x80000000" HIGHDECIMAL="2155872255" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0x807FFFFF" INSTANCE="MCB_DDR3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8388608" SIZEABRV="8M">
+          <ACCESSROUTE>
+            <ROUTEPNT INDEX="0" INSTANCE="axi4_0"/>
+          </ACCESSROUTE>
+        </MEMRANGE>
+      </MEMORYMAP>
+      <PERIPHERALS>
+        <PERIPHERAL INSTANCE="microblaze_0_d_bram_ctrl"/>
+        <PERIPHERAL INSTANCE="microblaze_0_i_bram_ctrl"/>
+        <PERIPHERAL INSTANCE="debug_module"/>
+        <PERIPHERAL INSTANCE="RS232_Uart_1"/>
+        <PERIPHERAL INSTANCE="LEDs_4Bits"/>
+        <PERIPHERAL INSTANCE="Push_Buttons_4Bits"/>
+        <PERIPHERAL INSTANCE="ETHERNET"/>
+        <PERIPHERAL INSTANCE="ETHERNET_dma"/>
+        <PERIPHERAL INSTANCE="microblaze_0_intc"/>
+        <PERIPHERAL INSTANCE="axi_timer_0"/>
+        <PERIPHERAL INSTANCE="MCB_DDR3"/>
+      </PERIPHERALS>
+      <INTERRUPTINFO TYPE="TARGET">
+        <SOURCE INSTANCE="microblaze_0_intc" INTC_INDEX="0"/>
+      </INTERRUPTINFO>
+    </MODULE>
+    <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_ilmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10">
+      <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Active High External Reset</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
+        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_ilmb_LMB_Rst"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_ilmb_M_WriteStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_ilmb_LMB_Ready"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_ilmb_LMB_Wait"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_ilmb_LMB_UE"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_ilmb_LMB_CE"/>
+        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
+      </PORTS>
+      <BUSINTERFACES/>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
+      </IOINTERFACES>
+    </MODULE>
+    <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_dlmb" IPTYPE="BUS" MHS_INDEX="4" MODCLASS="BUS" MODTYPE="lmb_v10">
+      <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Active High External Reset</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
+        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_dlmb_LMB_Ready"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_dlmb_LMB_Wait"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_dlmb_LMB_UE"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_dlmb_LMB_CE"/>
+        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
+      </PORTS>
+      <BUSINTERFACES/>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
+      </IOINTERFACES>
+    </MODULE>
+    <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_i_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
+      <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001FFF">
+          <DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
+        <PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0xc0000000">
+          <DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Error Correction Code </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Select Interconnect </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Fault Inject Registers </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>ECC Status and Control Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0">
+          <DESCRIPTION>ECC On/Off Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1">
+          <DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2">
+          <DESCRIPTION>Write Access setting </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
+          <DESCRIPTION>Base Address for PLB Interface</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>High Address for PLB Interface</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>Frequency of PLB Slave</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
+          <DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_ilmb_LMB_Rst"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
+        <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001FFF" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="SLMB"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="SPLB_CTRL"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+    </MODULE>
+    <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_d_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
+      <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001FFF">
+          <DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
+        <PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0xc0000000">
+          <DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Error Correction Code </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Select Interconnect </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Fault Inject Registers </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0">
+          <DESCRIPTION>ECC Status and Control Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0">
+          <DESCRIPTION>ECC On/Off Register </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1">
+          <DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0">
+          <DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2">
+          <DESCRIPTION>Write Access setting </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
+          <DESCRIPTION>Base Address for PLB Interface</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>High Address for PLB Interface</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>Frequency of PLB Slave</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
+          <DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE"/>
+        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
+        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
+        <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
+            <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
+            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001FFF" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="SLMB"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="SPLB_CTRL"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+    </MODULE>
+    <MODULE HWVERSION="1.00.a" INSTANCE="microblaze_0_bram_block" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="MEMORY" MODTYPE="bram_block">
+      <DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x2000">
+          <DESCRIPTION>Size of BRAM(s) in Bytes</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>Data Width of Port A and B</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32">
+          <DESCRIPTION>Address Width of Port A and B</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4">
+          <DESCRIPTION>Number of Byte Write Enables</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
+        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
+        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
+        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
+        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
+        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
+        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
+        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
+        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
+        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
+        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
+        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
+        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
+        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_A"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_A"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_EN_A"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_A"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_A"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Din_A"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_A"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_B"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_B"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_EN_B"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_B"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_B"/>
+            <PORTMAP DIR="O" PHYSICAL="BRAM_Din_B"/>
+            <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_B"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE HWVERSION="3.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
+      <DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="t">
+          <DESCRIPTION>Device Subfamily</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4">
+          <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The External Reset Input </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4">
+          <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1">
+          <DESCRIPTION>External Reset Active High </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1">
+          <DESCRIPTION>Auxiliary Reset Active High </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Number of Bus Structure Reset Registered Outputs </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Number of Peripheral Reset Registered Outputs </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_NUM_INTERCONNECT_ARESETN" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Number of Active Low Interconnect Reset Registered Outputs </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_NUM_PERP_ARESETN" TYPE="integer" VALUE="1">
+          <DESCRIPTION>Number of Active Low Peripheral Reset Registered Outputs </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="RESET"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/>
+        <PORT CLKFREQUENCY="50000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]"/>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="18" NAME="BUS_STRUCT_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET" VECFORMULA="[0:C_NUM_BUS_RST-1]"/>
+        <PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_RST-1]"/>
+        <PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_0"/>
+            <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_0"/>
+            <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_0"/>
+            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_0"/>
+            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_0"/>
+            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_0"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_1"/>
+            <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_1"/>
+            <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_1"/>
+            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_1"/>
+            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_1"/>
+            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_1"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
+      </IOINTERFACES>
+    </MODULE>
+    <MODULE HWVERSION="4.01.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="IP" MODTYPE="clock_generator">
+      <DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_01_a/doc/clock_generator.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="6slx45t">
+          <DESCRIPTION>Device</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="fgg484">
+          <DESCRIPTION>Package</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-3">
+          <DESCRIPTION>Speed Grade</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="200000000">
+          <DESCRIPTION>Input Clock Frequency (Hz) </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="600000000">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="PLL0">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Buffered </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="600000000">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="INTEGER" VALUE="180">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="PLL0">
+          <DESCRIPTION>Required Group </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="PLL0">
+          <DESCRIPTION>Required Group </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Varaible Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="125000000">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="200000000">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="PLL0">
+          <DESCRIPTION>Required Group </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="50000000">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="PLL0">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION> Varaible Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION> Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION> Variable Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Clock Deskew</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Required Phase</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Required Group</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE">
+          <DESCRIPTION>Buffered</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE">
+          <DESCRIPTION>Variable Phase Shift</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" VALUE="1"/>
+        <PARAMETER MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE">
+          <DESCRIPTION>Clock Primitive Feedback Buffer</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="94" NAME="C_CLK_GEN" VALUE="UPDATE"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="RESET"/>
+        <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="CLK"/>
+        <PORT CLKFREQUENCY="100000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT CLKFREQUENCY="50000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT CLKFREQUENCY="125000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="clk_125_0000MHz"/>
+        <PORT CLKFREQUENCY="200000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="clk_200_0000MHzPLL0"/>
+        <PORT CLKFREQUENCY="600000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="clk_600_0000MHzPLL0_nobuf"/>
+        <PORT CLKFREQUENCY="600000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="clk_600_0000MHz180PLL0_nobuf"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="24" NAME="LOCKED" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="I" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="I" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/>
+        <PORT DIR="I" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE HWVERSION="2.00.b" INSTANCE="debug_module" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="DEBUG" MODTYPE="mdm">
+      <DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Debug module for MicroBlaze Soft Processor.</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/doc/mdm.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2">
+          <DESCRIPTION>Specifies the JTAG user-defined register used </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_INTERCONNECT" TYPE="INTEGER" VALUE="2">
+          <DESCRIPTION>Specifies the Bus Interface for the JTAG UART </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x74800000">
+          <DESCRIPTION>Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x7480FFFF">
+          <DESCRIPTION>High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="3">
+          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="8">
+          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="12" NAME="C_MB_DBG_PORTS" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Number of MicroBlaze debug ports </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="13" NAME="C_USE_UART" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Enable JTAG UART </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>AXI4LITE protocal</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="Debug_SYS_Rst" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/>
+        <PORT DIR="O" MPD_INDEX="0" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT DEF_SIGNAME="Ext_BRK" DIR="O" MPD_INDEX="2" NAME="Ext_BRK" SIGNAME="Ext_BRK"/>
+        <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="O" MPD_INDEX="3" NAME="Ext_NM_BRK" SIGNAME="Ext_NM_BRK"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="5" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(C_S_AXI_DATA_WIDTH/8-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="11" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="12" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="15" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="17" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="21" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="22" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="__NOC__"/>
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+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="26" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="27" NAME="PLB_PAValid" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="28" NAME="PLB_SAValid" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="29" NAME="PLB_rdPrim" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="30" NAME="PLB_wrPrim" SIGNAME="__NOC__"/>
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+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="PLB_busLock" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="PLB_RNW" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="35" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
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+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="PLB_lockErr" SIGNAME="__NOC__"/>
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+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="PLB_wrBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="PLB_rdBurst" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="PLB_wrPendReq" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="PLB_rdPendReq" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="46" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="48" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="49" NAME="Sl_addrAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="50" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="51" NAME="Sl_wait" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="52" NAME="Sl_rearbitrate" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="53" NAME="Sl_wrDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="54" NAME="Sl_wrComp" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="55" NAME="Sl_wrBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="56" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="Sl_rdDAck" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="Sl_rdComp" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="Sl_rdBTerm" SIGNAME="__NOC__"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="61" MSB="0" NAME="Sl_MBusy" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="62" MSB="0" NAME="Sl_MWrErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="63" MSB="0" NAME="Sl_MRdErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
+        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="64" MSB="0" NAME="Sl_MIRQ" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Clk" DIR="O" MPD_INDEX="65" NAME="Dbg_Clk_0" SIGNAME="microblaze_0_debug_Dbg_Clk"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDI" DIR="O" MPD_INDEX="66" NAME="Dbg_TDI_0" SIGNAME="microblaze_0_debug_Dbg_TDI"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDO" DIR="I" MPD_INDEX="67" NAME="Dbg_TDO_0" SIGNAME="microblaze_0_debug_Dbg_TDO"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Reg_En" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="68" MSB="0" NAME="Dbg_Reg_En_0" RIGHT="7" SIGNAME="microblaze_0_debug_Dbg_Reg_En" VECFORMULA="[0:7]"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Capture" DIR="O" MPD_INDEX="69" NAME="Dbg_Capture_0" SIGNAME="microblaze_0_debug_Dbg_Capture"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Shift" DIR="O" MPD_INDEX="70" NAME="Dbg_Shift_0" SIGNAME="microblaze_0_debug_Dbg_Shift"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Update" DIR="O" MPD_INDEX="71" NAME="Dbg_Update_0" SIGNAME="microblaze_0_debug_Dbg_Update"/>
+        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Debug_Rst" DIR="O" MPD_INDEX="72" NAME="Dbg_Rst_0" SIGNAME="microblaze_0_debug_Debug_Rst"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="73" NAME="Dbg_Clk_1" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="74" NAME="Dbg_TDI_1" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="Dbg_TDO_1" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="76" MSB="0" NAME="Dbg_Reg_En_1" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="77" NAME="Dbg_Capture_1" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="Dbg_Shift_1" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="79" NAME="Dbg_Update_1" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="80" NAME="Dbg_Rst_1" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="81" NAME="Dbg_Clk_2" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="82" NAME="Dbg_TDI_2" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="83" NAME="Dbg_TDO_2" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="84" MSB="0" NAME="Dbg_Reg_En_2" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="85" NAME="Dbg_Capture_2" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="86" NAME="Dbg_Shift_2" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="Dbg_Update_2" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="Dbg_Rst_2" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="89" NAME="Dbg_Clk_3" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="Dbg_TDI_3" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="91" NAME="Dbg_TDO_3" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="92" MSB="0" NAME="Dbg_Reg_En_3" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="Dbg_Capture_3" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="Dbg_Shift_3" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="95" NAME="Dbg_Update_3" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="Dbg_Rst_3" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="Dbg_Clk_4" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="98" NAME="Dbg_TDI_4" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="Dbg_TDO_4" SIGNAME="__NOC__"/>
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+        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="Dbg_Capture_4" SIGNAME="__NOC__"/>
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+        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="Dbg_TDI_7" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="Dbg_TDO_7" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="124" MSB="0" NAME="Dbg_Reg_En_7" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
+        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="125" NAME="Dbg_Capture_7" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="126" NAME="Dbg_Shift_7" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="Dbg_Update_7" SIGNAME="__NOC__"/>
+        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="128" NAME="Dbg_Rst_7" SIGNAME="__NOC__"/>
+        <PORT DEF_SIGNAME="bscan_tdi" DIR="O" MPD_INDEX="129" NAME="bscan_tdi" SIGNAME="bscan_tdi"/>
+        <PORT DEF_SIGNAME="bscan_reset" DIR="O" MPD_INDEX="130" NAME="bscan_reset" SIGNAME="bscan_reset"/>
+        <PORT DEF_SIGNAME="bscan_shift" DIR="O" MPD_INDEX="131" NAME="bscan_shift" SIGNAME="bscan_shift"/>
+        <PORT DEF_SIGNAME="bscan_update" DIR="O" MPD_INDEX="132" NAME="bscan_update" SIGNAME="bscan_update"/>
+        <PORT DEF_SIGNAME="bscan_capture" DIR="O" MPD_INDEX="133" NAME="bscan_capture" SIGNAME="bscan_capture"/>
+        <PORT DEF_SIGNAME="bscan_sel1" DIR="O" MPD_INDEX="134" NAME="bscan_sel1" SIGNAME="bscan_sel1"/>
+        <PORT DEF_SIGNAME="bscan_drck1" DIR="O" MPD_INDEX="135" NAME="bscan_drck1" SIGNAME="bscan_drck1"/>
+        <PORT DEF_SIGNAME="bscan_tdo1" DIR="I" MPD_INDEX="136" NAME="bscan_tdo1" SIGNAME="bscan_tdo1"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="137" NAME="Ext_JTAG_DRCK" SIGNAME="__NOC__"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="138" NAME="Ext_JTAG_RESET" SIGNAME="__NOC__"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="139" NAME="Ext_JTAG_SEL" SIGNAME="__NOC__"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="140" NAME="Ext_JTAG_CAPTURE" SIGNAME="__NOC__"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="141" NAME="Ext_JTAG_SHIFT" SIGNAME="__NOC__"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="Ext_JTAG_UPDATE" SIGNAME="__NOC__"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="143" NAME="Ext_JTAG_TDI" SIGNAME="__NOC__"/>
+        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="144" NAME="Ext_JTAG_TDO" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="1" NAME="SPLB" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
+            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
+            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
+            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="MBDEBUG_0" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_0"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_0"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_0"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_0"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_0"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_0"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_0"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_0"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="3" NAME="MBDEBUG_1" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_1"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_1"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_1"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_1"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_1"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_1"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_1"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_1"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="4" NAME="MBDEBUG_2" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_2"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_2"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_2"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_2"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_2"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_2"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_2"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_2"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="5" NAME="MBDEBUG_3" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_3"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_3"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_3"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_3"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_3"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_3"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_3"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_3"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="6" NAME="MBDEBUG_4" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_4"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_4"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_4"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_4"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_4"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_4"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_4"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_4"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="7" NAME="MBDEBUG_5" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_5"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_5"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_5"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_5"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_5"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_5"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_5"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_5"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="8" NAME="MBDEBUG_6" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_6"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_6"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_6"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_6"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_6"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_6"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_6"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_6"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="9" NAME="MBDEBUG_7" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_7"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_7"/>
+            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_7"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_7"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_7"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_7"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_7"/>
+            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_7"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_BSCAN" MPD_INDEX="10" NAME="XMTC" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_DRCK"/>
+            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_RESET"/>
+            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SEL"/>
+            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_CAPTURE"/>
+            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SHIFT"/>
+            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_UPDATE"/>
+            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_TDI"/>
+            <PORTMAP DIR="I" PHYSICAL="Ext_JTAG_TDO"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480FFFF" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="SPLB"/>
+            <SLAVE BUSINTERFACE="S_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+    </MODULE>
+    <MODULE HWVERSION="1.01.a" INSTANCE="RS232_Uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="axi_uartlite">
+      <DESCRIPTION TYPE="SHORT">AXI UART (Lite)</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_uartlite_v1_01_a/doc/axi_uartlite_ds741.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000">
+          <DESCRIPTION>AXI Clock Frequency </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40600000">
+          <DESCRIPTION>AXI Base Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4060ffff">
+          <DESCRIPTION>AXI High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="C_BAUDRATE" TYPE="INTEGER" VALUE="115200">
+          <DESCRIPTION>UART Lite Baud Rate </DESCRIPTION>
+          <DESCRIPTION>Baud Rate</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_DATA_BITS" TYPE="INTEGER" VALUE="8">
+          <DESCRIPTION>Number of Data Bits in a Serial Frame</DESCRIPTION>
+          <DESCRIPTION>Data Bits</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="8" NAME="C_USE_PARITY" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Use Parity </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="9" NAME="C_ODD_PARITY" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Parity Type </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="21" NAME="TX" SIGNAME="RS232_Uart_1_sout">
+          <DESCRIPTION>Serial Data Out</DESCRIPTION>
+        </PORT>
+        <PORT DIR="I" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="20" NAME="RX" SIGNAME="RS232_Uart_1_sin">
+          <DESCRIPTION>Serial Data In</DESCRIPTION>
+        </PORT>
+        <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="RS232_Uart_1_Interrupt"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="uart_0" TYPE="XIL_UART_V1_hide">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="TX"/>
+            <PORTMAP DIR="I" PHYSICAL="RX"/>
+          </PORTMAPS>
+        </IOINTERFACE>
+      </IOINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="4"/>
+      </INTERRUPTINFO>
+    </MODULE>
+    <MODULE HWVERSION="1.01.a" INSTANCE="LEDs_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
+      <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40020000">
+          <DESCRIPTION>AXI Base Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4002ffff">
+          <DESCRIPTION>AXI High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4">
+          <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
+          <DESCRIPTION>GPIO Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
+          <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
+          <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="LEDs_4Bits_TRI_O" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
+        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
+          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
+        </PORT>
+        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
+          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
+            <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
+            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
+            <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
+            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
+            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
+            <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
+            <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
+          </PORTMAPS>
+        </IOINTERFACE>
+      </IOINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+    </MODULE>
+    <MODULE HWVERSION="1.01.a" INSTANCE="Push_Buttons_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
+      <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40000000">
+          <DESCRIPTION>AXI Base Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4000ffff">
+          <DESCRIPTION>AXI High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4">
+          <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
+          <DESCRIPTION>GPIO Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
+          <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
+          <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
+          <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
+        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
+          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
+        </PORT>
+        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
+          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
+            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
+            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
+            <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
+            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
+            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
+            <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
+            <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
+          </PORTMAPS>
+        </IOINTERFACE>
+      </IOINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="3"/>
+      </INTERRUPTINFO>
+    </MODULE>
+    <MODULE HWVERSION="1.02.a" INSTANCE="MCB_DDR3" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_s6_ddrx">
+      <DESCRIPTION TYPE="SHORT">AXI S6 Memory Controller(DDR/DDR2/DDR3)</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Spartan-6 memory controller</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_s6_ddrx_v1_02_a/doc/axi_s6_ddrx.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER MPD_INDEX="0" NAME="C_MCB_LOC" VALUE="MEMC3"/>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_MCB_RZQ_LOC" TYPE="STRING" VALUE="K7"/>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="C_MCB_ZIO_LOC" TYPE="STRING" VALUE="R7"/>
+        <PARAMETER MPD_INDEX="3" NAME="C_MCB_PERFORMANCE" TYPE="STRING" VALUE="STANDARD"/>
+        <PARAMETER MPD_INDEX="4" NAME="C_BYPASS_CORE_UCF" VALUE="0"/>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="5" NAME="C_S0_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x80000000"/>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="6" NAME="C_S0_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x807FFFFF"/>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="7" NAME="C_S1_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="8" NAME="C_S1_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="9" NAME="C_S2_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="10" NAME="C_S2_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="11" NAME="C_S3_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="12" NAME="C_S3_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="13" NAME="C_S4_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="14" NAME="C_S4_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="15" NAME="C_S5_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="16" NAME="C_S5_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
+        <PARAMETER MPD_INDEX="17" NAME="C_MEM_TYPE" TYPE="STRING" VALUE="DDR3"/>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="18" NAME="C_MEM_PARTNO" TYPE="STRING" VALUE="MT41J64M16XX-187E"/>
+        <PARAMETER MPD_INDEX="19" NAME="C_MEM_BASEPARTNO" TYPE="STRING" VALUE="NOT_SET"/>
+        <PARAMETER MPD_INDEX="20" NAME="C_NUM_DQ_PINS" TYPE="INTEGER" VALUE="16"/>
+        <PARAMETER MPD_INDEX="21" NAME="C_MEM_ADDR_WIDTH" TYPE="INTEGER" VALUE="13"/>
+        <PARAMETER MPD_INDEX="22" NAME="C_MEM_BANKADDR_WIDTH" TYPE="INTEGER" VALUE="3"/>
+        <PARAMETER MPD_INDEX="23" NAME="C_MEM_NUM_COL_BITS" TYPE="INTEGER" VALUE="10"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="24" NAME="C_MEM_TRAS" TYPE="INTEGER" VALUE="37500"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="25" NAME="C_MEM_TRCD" TYPE="INTEGER" VALUE="13130"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="26" NAME="C_MEM_TREFI" TYPE="INTEGER" VALUE="7800000"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="27" NAME="C_MEM_TRFC" TYPE="INTEGER" VALUE="160000"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_MEM_TRP" TYPE="INTEGER" VALUE="13130"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="29" NAME="C_MEM_TWR" TYPE="INTEGER" VALUE="15000"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="30" NAME="C_MEM_TRTP" TYPE="INTEGER" VALUE="7500"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="31" NAME="C_MEM_TWTR" TYPE="INTEGER" VALUE="7500"/>
+        <PARAMETER MPD_INDEX="32" NAME="C_PORT_CONFIG" TYPE="STRING" VALUE="B32_B32_B32_B32"/>
+        <PARAMETER MPD_INDEX="33" NAME="C_SKIP_IN_TERM_CAL" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="34" NAME="C_SKIP_IN_TERM_CAL_VALUE" TYPE="STRING" VALUE="NONE"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_MEMCLK_PERIOD" TYPE="INTEGER" VALUE="3333"/>
+        <PARAMETER MPD_INDEX="36" NAME="C_MEM_ADDR_ORDER" TYPE="STRING" VALUE="ROW_BANK_COLUMN"/>
+        <PARAMETER MPD_INDEX="37" NAME="C_MEM_TZQINIT_MAXCNT" TYPE="INTEGER" VALUE="512"/>
+        <PARAMETER MPD_INDEX="38" NAME="C_MEM_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/>
+        <PARAMETER MPD_INDEX="39" NAME="C_SIMULATION" TYPE="STRING" VALUE="FALSE"/>
+        <PARAMETER MPD_INDEX="40" NAME="C_MEM_DDR1_2_ODS" TYPE="STRING" VALUE="FULL"/>
+        <PARAMETER MPD_INDEX="41" NAME="C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/>
+        <PARAMETER MPD_INDEX="42" NAME="C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/>
+        <PARAMETER MPD_INDEX="43" NAME="C_MEM_DDR2_RTT" TYPE="STRING" VALUE="150OHMS"/>
+        <PARAMETER MPD_INDEX="44" NAME="C_MEM_DDR2_DIFF_DQS_EN" TYPE="STRING" VALUE="YES"/>
+        <PARAMETER MPD_INDEX="45" NAME="C_MEM_DDR2_3_PA_SR" TYPE="STRING" VALUE="FULL"/>
+        <PARAMETER MPD_INDEX="46" NAME="C_MEM_DDR2_3_HIGH_TEMP_SR" TYPE="STRING" VALUE="NORMAL"/>
+        <PARAMETER MPD_INDEX="47" NAME="C_MEM_DDR3_CAS_WR_LATENCY" TYPE="INTEGER" VALUE="5"/>
+        <PARAMETER MPD_INDEX="48" NAME="C_MEM_DDR3_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/>
+        <PARAMETER MPD_INDEX="49" NAME="C_MEM_DDR3_ODS" TYPE="STRING" VALUE="DIV6"/>
+        <PARAMETER MPD_INDEX="50" NAME="C_MEM_DDR3_RTT" TYPE="STRING" VALUE="DIV4"/>
+        <PARAMETER MPD_INDEX="51" NAME="C_MEM_DDR3_AUTO_SR" TYPE="STRING" VALUE="ENABLED"/>
+        <PARAMETER MPD_INDEX="52" NAME="C_MEM_MOBILE_PA_SR" TYPE="STRING" VALUE="FULL"/>
+        <PARAMETER MPD_INDEX="53" NAME="C_MEM_MDDR_ODS" TYPE="STRING" VALUE="FULL"/>
+        <PARAMETER MPD_INDEX="54" NAME="C_ARB_ALGORITHM" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="55" NAME="C_ARB_NUM_TIME_SLOTS" TYPE="INTEGER" VALUE="12"/>
+        <PARAMETER MPD_INDEX="56" NAME="C_ARB_TIME_SLOT_0" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
+        <PARAMETER MPD_INDEX="57" NAME="C_ARB_TIME_SLOT_1" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
+        <PARAMETER MPD_INDEX="58" NAME="C_ARB_TIME_SLOT_2" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
+        <PARAMETER MPD_INDEX="59" NAME="C_ARB_TIME_SLOT_3" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
+        <PARAMETER MPD_INDEX="60" NAME="C_ARB_TIME_SLOT_4" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
+        <PARAMETER MPD_INDEX="61" NAME="C_ARB_TIME_SLOT_5" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
+        <PARAMETER MPD_INDEX="62" NAME="C_ARB_TIME_SLOT_6" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
+        <PARAMETER MPD_INDEX="63" NAME="C_ARB_TIME_SLOT_7" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
+        <PARAMETER MPD_INDEX="64" NAME="C_ARB_TIME_SLOT_8" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
+        <PARAMETER MPD_INDEX="65" NAME="C_ARB_TIME_SLOT_9" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
+        <PARAMETER MPD_INDEX="66" NAME="C_ARB_TIME_SLOT_10" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
+        <PARAMETER MPD_INDEX="67" NAME="C_ARB_TIME_SLOT_11" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
+        <PARAMETER MPD_INDEX="68" NAME="C_S0_AXI_ENABLE" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="69" NAME="C_S0_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="70" NAME="C_S0_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="3"/>
+        <PARAMETER MPD_INDEX="71" NAME="C_S0_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER MPD_INDEX="72" NAME="C_S0_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER MPD_INDEX="73" NAME="C_S0_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="74" NAME="C_S0_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="75" NAME="C_S0_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="76" NAME="C_S0_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/>
+        <PARAMETER MPD_INDEX="77" NAME="C_S0_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="78" NAME="C_S0_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="79" NAME="C_S0_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="80" NAME="C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="81" NAME="C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="82" NAME="C_S1_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="83" NAME="C_S1_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
+        <PARAMETER MPD_INDEX="84" NAME="C_S1_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="85" NAME="C_S1_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER MPD_INDEX="86" NAME="C_S1_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="87" NAME="C_S1_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="88" NAME="C_S1_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="89" NAME="C_S1_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="90" NAME="C_S1_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
+        <PARAMETER MPD_INDEX="91" NAME="C_S1_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
+        <PARAMETER MPD_INDEX="92" NAME="C_S1_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="93" NAME="C_S1_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="94" NAME="C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="95" NAME="C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="96" NAME="C_S2_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="97" NAME="C_S2_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
+        <PARAMETER MPD_INDEX="98" NAME="C_S2_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="99" NAME="C_S2_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER MPD_INDEX="100" NAME="C_S2_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="101" NAME="C_S2_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="102" NAME="C_S2_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="103" NAME="C_S2_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="104" NAME="C_S2_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
+        <PARAMETER MPD_INDEX="105" NAME="C_S2_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
+        <PARAMETER MPD_INDEX="106" NAME="C_S2_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="107" NAME="C_S2_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="108" NAME="C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="109" NAME="C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="110" NAME="C_S3_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="111" NAME="C_S3_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
+        <PARAMETER MPD_INDEX="112" NAME="C_S3_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="113" NAME="C_S3_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER MPD_INDEX="114" NAME="C_S3_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="115" NAME="C_S3_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="116" NAME="C_S3_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="117" NAME="C_S3_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="118" NAME="C_S3_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
+        <PARAMETER MPD_INDEX="119" NAME="C_S3_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
+        <PARAMETER MPD_INDEX="120" NAME="C_S3_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="121" NAME="C_S3_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="122" NAME="C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="123" NAME="C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="124" NAME="C_S4_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="125" NAME="C_S4_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
+        <PARAMETER MPD_INDEX="126" NAME="C_S4_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="127" NAME="C_S4_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER MPD_INDEX="128" NAME="C_S4_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="129" NAME="C_S4_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="130" NAME="C_S4_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="131" NAME="C_S4_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="132" NAME="C_S4_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
+        <PARAMETER MPD_INDEX="133" NAME="C_S4_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
+        <PARAMETER MPD_INDEX="134" NAME="C_S4_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="135" NAME="C_S4_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="136" NAME="C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="137" NAME="C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="138" NAME="C_S5_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="139" NAME="C_S5_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
+        <PARAMETER MPD_INDEX="140" NAME="C_S5_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="141" NAME="C_S5_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER MPD_INDEX="142" NAME="C_S5_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="143" NAME="C_S5_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="144" NAME="C_S5_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="145" NAME="C_S5_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="146" NAME="C_S5_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
+        <PARAMETER MPD_INDEX="147" NAME="C_S5_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
+        <PARAMETER MPD_INDEX="148" NAME="C_S5_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER MPD_INDEX="149" NAME="C_S5_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER MPD_INDEX="150" NAME="C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="151" NAME="C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
+        <PARAMETER MPD_INDEX="152" NAME="C_MCB_USE_EXTERNAL_BUFPLL" TYPE="INTEGER" VALUE="0"/>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="153" NAME="C_SYS_RST_PRESENT" TYPE="INTEGER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S0_AXI_MASTERS" VALUE="microblaze_0.M_AXI_DC &amp; microblaze_0.M_AXI_IC &amp; ETHERNET_dma.M_AXI_SG &amp; ETHERNET_dma.M_AXI_MM2S &amp; ETHERNET_dma.M_AXI_S2MM"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S0_AXI_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S0_AXI_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S0_AXI_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S0_AXI_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S0_AXI_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="17" NAME="mcbx_dram_clk" SIGIS="CLK" SIGNAME="mcbx_dram_clk"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="18" NAME="mcbx_dram_clk_n" SIGIS="CLK" SIGNAME="mcbx_dram_clk_n"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="16" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="26" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="13" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="14" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="15" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="24" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="25" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="9" MPD_INDEX="12" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba" VECFORMULA="[C_MEM_BANKADDR_WIDTH-1:0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="12" LSB="0" MHS_INDEX="10" MPD_INDEX="11" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr" VECFORMULA="[C_MEM_ADDR_WIDTH-1:0]"/>
+        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="27" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
+        <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="15" LSB="0" MHS_INDEX="12" MPD_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq" VECFORMULA="[C_NUM_DQ_PINS-1:0]"/>
+        <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="13" MPD_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
+        <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="14" MPD_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
+        <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="15" MPD_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
+        <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="16" MPD_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
+        <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="17" MPD_INDEX="28" NAME="rzq" SIGNAME="rzq"/>
+        <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="18" MPD_INDEX="29" NAME="zio" SIGNAME="zio"/>
+        <PORT BUS="S0_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="32" NAME="s0_axi_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="30" NAME="ui_clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT CLKFREQUENCY="600000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="0" NAME="sysclk_2x" SIGIS="CLK" SIGNAME="clk_600_0000MHzPLL0_nobuf"/>
+        <PORT CLKFREQUENCY="600000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="1" NAME="sysclk_2x_180" SIGIS="CLK" SIGNAME="clk_600_0000MHz180PLL0_nobuf"/>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="10" NAME="SYS_RST" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
+        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="4" NAME="PLL_LOCK" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
+        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="2" NAME="pll_ce_0" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="3" NAME="pll_ce_90" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="5" NAME="pll_lock_bufpll_o" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="6" NAME="sysclk_2x_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="7" NAME="sysclk_2x_180_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="8" NAME="pll_ce_0_bufpll_o" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="9" NAME="pll_ce_90_bufpll_o" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="31" NAME="uo_done_cal" SIGNAME="__NOC__"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_aresetn" DIR="I" MPD_INDEX="33" NAME="s0_axi_aresetn" SIGIS="RST" SIGNAME="axi4_0_M_aresetn"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awid" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="34" MSB="2" NAME="s0_axi_awid" RIGHT="0" SIGNAME="axi4_0_M_awid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awaddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="35" MSB="31" NAME="s0_axi_awaddr" RIGHT="0" SIGNAME="axi4_0_M_awaddr" VECFORMULA="[(C_S0_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="36" MSB="7" NAME="s0_axi_awlen" RIGHT="0" SIGNAME="axi4_0_M_awlen" VECFORMULA="[7:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="37" MSB="2" NAME="s0_axi_awsize" RIGHT="0" SIGNAME="axi4_0_M_awsize" VECFORMULA="[2:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="38" MSB="1" NAME="s0_axi_awburst" RIGHT="0" SIGNAME="axi4_0_M_awburst" VECFORMULA="[1:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awlock" DIR="I" MPD_INDEX="39" NAME="s0_axi_awlock" SIGNAME="axi4_0_M_awlock" VECFORMULA="[0:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="40" MSB="3" NAME="s0_axi_awcache" RIGHT="0" SIGNAME="axi4_0_M_awcache" VECFORMULA="[3:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="41" MSB="2" NAME="s0_axi_awprot" RIGHT="0" SIGNAME="axi4_0_M_awprot" VECFORMULA="[2:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="42" MSB="3" NAME="s0_axi_awqos" RIGHT="0" SIGNAME="axi4_0_M_awqos" VECFORMULA="[3:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awvalid" DIR="I" MPD_INDEX="43" NAME="s0_axi_awvalid" SIGNAME="axi4_0_M_awvalid"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awready" DIR="O" MPD_INDEX="44" NAME="s0_axi_awready" SIGNAME="axi4_0_M_awready"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wdata" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="45" MSB="31" NAME="s0_axi_wdata" RIGHT="0" SIGNAME="axi4_0_M_wdata" VECFORMULA="[(C_S0_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wstrb" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="46" MSB="3" NAME="s0_axi_wstrb" RIGHT="0" SIGNAME="axi4_0_M_wstrb" VECFORMULA="[((C_S0_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wlast" DIR="I" MPD_INDEX="47" NAME="s0_axi_wlast" SIGNAME="axi4_0_M_wlast"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wvalid" DIR="I" MPD_INDEX="48" NAME="s0_axi_wvalid" SIGNAME="axi4_0_M_wvalid"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wready" DIR="O" MPD_INDEX="49" NAME="s0_axi_wready" SIGNAME="axi4_0_M_wready"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bid" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="50" MSB="2" NAME="s0_axi_bid" RIGHT="0" SIGNAME="axi4_0_M_bid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="51" MSB="1" NAME="s0_axi_bresp" RIGHT="0" SIGNAME="axi4_0_M_bresp" VECFORMULA="[1:0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bvalid" DIR="O" MPD_INDEX="52" NAME="s0_axi_bvalid" SIGNAME="axi4_0_M_bvalid"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_bready" DIR="I" MPD_INDEX="53" NAME="s0_axi_bready" SIGNAME="axi4_0_M_bready"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arid" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="54" MSB="2" NAME="s0_axi_arid" RIGHT="0" SIGNAME="axi4_0_M_arid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_araddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="55" MSB="31" NAME="s0_axi_araddr" RIGHT="0" SIGNAME="axi4_0_M_araddr" VECFORMULA="[(C_S0_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_arlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="56" MSB="7" NAME="s0_axi_arlen" RIGHT="0" SIGNAME="axi4_0_M_arlen" VECFORMULA="[7:0]"/>
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+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="251" MSB="7" NAME="s5_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="252" MSB="2" NAME="s5_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="253" MSB="1" NAME="s5_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="254" NAME="s5_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="255" MSB="3" NAME="s5_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="256" MSB="2" NAME="s5_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="257" MSB="3" NAME="s5_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="258" NAME="s5_axi_arvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="259" NAME="s5_axi_arready" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="260" MSB="3" NAME="s5_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="261" MSB="31" NAME="s5_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="262" MSB="1" NAME="s5_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="263" NAME="s5_axi_rlast" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="s5_axi_rvalid" SIGNAME="__NOC__"/>
+        <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="265" NAME="s5_axi_rready" SIGNAME="__NOC__"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S0_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_aresetn"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awid"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awaddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_awvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_awready"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_wdata"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_wstrb"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_wlast"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_wvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_wready"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_bid"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_bresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_bvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_bready"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arid"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_araddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_arvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_arready"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_rid"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_rdata"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_rresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_rlast"/>
+            <PORTMAP DIR="O" PHYSICAL="s0_axi_rvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s0_axi_rready"/>
+          </PORTMAPS>
+          <MASTERS>
+            <MASTER BUSINTERFACE="M_AXI_DC" INSTANCE="microblaze_0"/>
+            <MASTER BUSINTERFACE="M_AXI_IC" INSTANCE="microblaze_0"/>
+            <MASTER BUSINTERFACE="M_AXI_SG" INSTANCE="ETHERNET_dma"/>
+            <MASTER BUSINTERFACE="M_AXI_MM2S" INSTANCE="ETHERNET_dma"/>
+            <MASTER BUSINTERFACE="M_AXI_S2MM" INSTANCE="ETHERNET_dma"/>
+          </MASTERS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="1" NAME="S1_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_aresetn"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awid"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awaddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_awvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_awready"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_wdata"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_wstrb"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_wlast"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_wvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_wready"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_bid"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_bresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_bvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_bready"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arid"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_araddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_arvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_arready"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_rid"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_rdata"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_rresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_rlast"/>
+            <PORTMAP DIR="O" PHYSICAL="s1_axi_rvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s1_axi_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="2" NAME="S2_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_aresetn"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awid"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awaddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_awvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_awready"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_wdata"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_wstrb"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_wlast"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_wvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_wready"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_bid"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_bresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_bvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_bready"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arid"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_araddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_arvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_arready"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_rid"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_rdata"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_rresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_rlast"/>
+            <PORTMAP DIR="O" PHYSICAL="s2_axi_rvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s2_axi_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S3_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_aresetn"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awid"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awaddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_awvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_awready"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_wdata"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_wstrb"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_wlast"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_wvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_wready"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_bid"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_bresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_bvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_bready"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arid"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_araddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_arvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_arready"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_rid"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_rdata"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_rresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_rlast"/>
+            <PORTMAP DIR="O" PHYSICAL="s3_axi_rvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s3_axi_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="4" NAME="S4_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_aresetn"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awid"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awaddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_awvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_awready"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_wdata"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_wstrb"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_wlast"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_wvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_wready"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_bid"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_bresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_bvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_bready"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arid"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_araddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_arvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_arready"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_rid"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_rdata"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_rresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_rlast"/>
+            <PORTMAP DIR="O" PHYSICAL="s4_axi_rvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s4_axi_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="5" NAME="S5_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_aresetn"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awid"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awaddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_awvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_awready"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_wdata"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_wstrb"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_wlast"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_wvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_wready"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_bid"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_bresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_bvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_bready"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arid"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_araddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arlen"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arsize"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arburst"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arlock"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arcache"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arprot"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arqos"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_arvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_arready"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_rid"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_rdata"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_rresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_rlast"/>
+            <PORTMAP DIR="O" PHYSICAL="s5_axi_rvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s5_axi_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="memory_0" TYPE="hide_122_XIL_MEMORY_V1">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk_n"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cke"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_odt"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ras_n"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cas_n"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_we_n"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_udm"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ldm"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ba"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_addr"/>
+            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ddr3_rst"/>
+            <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dq"/>
+            <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs"/>
+            <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs_n"/>
+            <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs"/>
+            <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs_n"/>
+            <PORTMAP DIR="IO" PHYSICAL="rzq"/>
+            <PORTMAP DIR="IO" PHYSICAL="zio"/>
+          </PORTMAPS>
+        </IOINTERFACE>
+      </IOINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="2147483648" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0x80000000" HIGHDECIMAL="2155872255" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0x807FFFFF" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="8388608" SIZEABRV="8M">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S0_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S1_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S1_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S1_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S2_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S2_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S2_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S3_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S3_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S3_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S4_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S4_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S4_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S5_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S5_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S5_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+    </MODULE>
+    <MODULE HWVERSION="2.01.a" INSTANCE="ETHERNET" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="axi_ethernet">
+      <DESCRIPTION TYPE="SHORT">AXI Ethernet</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">AXI Ethernet MAC</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_ethernet_v2_01_a/doc/ds759_axi_ethernet.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO EXPIRESON="Jan-30-2016" ICON_NAME="ps_core_preferred" STATE="Hardware Evaluation" TYPE="Hardware_Evaluation"/>
+      <PARAMETERS>
+        <PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>AXI Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="1" NAME="C_AXI_STR_TXC_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Stream Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="2" NAME="C_AXI_STR_TXD_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Stream Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_AXI_STR_RXS_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Stream Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_AXI_STR_RXD_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Stream Bus Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_AXI_STR_TXC_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_CTRL">
+          <DESCRIPTION>AXI Stream Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_AXI_STR_TXD_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_DATA">
+          <DESCRIPTION>AXI Stream Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_AXI_STR_RXS_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_CTRL">
+          <DESCRIPTION>AXI Stream Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_AXI_STR_RXD_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_DATA">
+          <DESCRIPTION>AXI Stream Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_AXI_STR_AVBTX_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_AVB_TX">
+          <DESCRIPTION>AXI Stream Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_AXI_STR_AVBRX_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_AVB_RX">
+          <DESCRIPTION>AXI Stream Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000">
+          <DESCRIPTION>AXI Clock Freq in HZ</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="26" MPD_INDEX="13" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41240000">
+          <DESCRIPTION>Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="27" MPD_INDEX="14" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4127ffff">
+          <DESCRIPTION>High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>AXI ID Width </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="18" NAME="C_TRANS" TYPE="STRING" VALUE="A">
+          <DESCRIPTION>Spartan 6 Transceiver Side</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="19" NAME="C_PHYADDR" TYPE="std_logic_vector" VALUE="0B00001">
+          <DESCRIPTION>PHY Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="20" NAME="C_INCLUDE_IO" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Include IO and BUFG as Needed for the PHY Interface Selected</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="21" NAME="C_TYPE" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Type of TEMAC</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="22" NAME="C_PHY_TYPE" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Physical Interface Type</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="23" NAME="C_HALFDUP" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Enable Half Duplex mode</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="24" NAME="C_TXMEM" TYPE="INTEGER" VALUE="4096">
+          <DESCRIPTION>TX Memory Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="25" NAME="C_RXMEM" TYPE="INTEGER" VALUE="4096">
+          <DESCRIPTION>RX Memory Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="26" NAME="C_TXCSUM" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Enable TX Checksum Offload</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="27" NAME="C_RXCSUM" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Enable RX Checksum Offload</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="28" NAME="C_TXVLAN_TRAN" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Transmit VLAN translation</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="29" NAME="C_RXVLAN_TRAN" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Receive VLAN translation</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="30" NAME="C_TXVLAN_TAG" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Transmit VLAN tagging</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="31" NAME="C_RXVLAN_TAG" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Receive VLAN tagging</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="32" NAME="C_TXVLAN_STRP" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Transmit VLAN stripping</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="33" NAME="C_RXVLAN_STRP" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Receive VLAN stripping</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="34" NAME="C_MCAST_EXTEND" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Receive Extended Multicast Address Filtering</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="35" NAME="C_STATS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Statistics Counters</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="36" NAME="C_AVB" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Audio Video Bridging (AVB) - license required</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="37" NAME="C_SIMULATION" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Simulation Mode</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="20" NAME="C_INTERCONNECT_S_AXI_IS_ACLK_ASYNC" VALUE="0"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="21" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="22" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="23" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="24" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="25" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="IO" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="0" MPD_INDEX="108" NAME="MDIO" SIGNAME="ETHERNET_MDIO" TRI_I="MDIO_I" TRI_O="MDIO_O" TRI_T="MDIO_T"/>
+        <PORT DIR="O" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="83" NAME="MDC" SIGNAME="ETHERNET_MDC"/>
+        <PORT DIR="O" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="65" NAME="GMII_TX_ER" SIGNAME="ETHERNET_TX_ER"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="3" MPD_INDEX="63" MSB="7" NAME="GMII_TXD" RIGHT="0" SIGNAME="ETHERNET_TXD" VECFORMULA="[7:0]"/>
+        <PORT DIR="O" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="64" NAME="GMII_TX_EN" SIGNAME="ETHERNET_TX_EN"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="60" NAME="MII_TX_CLK" SIGNAME="ETHERNET_MII_TX_CLK"/>
+        <PORT DIR="O" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="66" NAME="GMII_TX_CLK" SIGNAME="ETHERNET_TX_CLK"/>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="7" MPD_INDEX="67" MSB="7" NAME="GMII_RXD" RIGHT="0" SIGNAME="ETHERNET_RXD" VECFORMULA="[7:0]"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="69" NAME="GMII_RX_ER" SIGNAME="ETHERNET_RX_ER"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="70" NAME="GMII_RX_CLK" SIGNAME="ETHERNET_RX_CLK"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="68" NAME="GMII_RX_DV" SIGNAME="ETHERNET_RX_DV"/>
+        <PORT DIR="O" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="48" NAME="PHY_RST_N" SIGNAME="ETHERNET_PHY_RST_N"/>
+        <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT CLKFREQUENCY="125000000" DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="49" NAME="GTX_CLK" SIGIS="CLK" SIGNAME="clk_125_0000MHz"/>
+        <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="52" NAME="REF_CLK" SIGIS="CLK" SIGNAME="clk_200_0000MHzPLL0"/>
+        <PORT BUS="AXI_STR_TXD" CLKFREQUENCY="100000000" DEF_SIGNAME="ACLK" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="20" NAME="AXI_STR_TXD_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT BUS="AXI_STR_TXC" CLKFREQUENCY="100000000" DEF_SIGNAME="ACLK" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="27" NAME="AXI_STR_TXC_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT BUS="AXI_STR_RXD" CLKFREQUENCY="100000000" DEF_SIGNAME="ACLK" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="34" NAME="AXI_STR_RXD_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT BUS="AXI_STR_RXS" CLKFREQUENCY="100000000" DEF_SIGNAME="ACLK" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="41" NAME="AXI_STR_RXS_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT BUS="S_AXI:AXI_STR_TXC:AXI_STR_TXD:AXI_STR_RXS:AXI_STR_RXD" DEF_SIGNAME="ARESETN" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="21" NAME="AXI_STR_TXD_ARESETN" SIGIS="RST" SIGNAME="AXI_STR_TXD_ARESETN"/>
+        <PORT BUS="S_AXI:AXI_STR_TXC:AXI_STR_TXD:AXI_STR_RXS:AXI_STR_RXD" DEF_SIGNAME="ARESETN" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="28" NAME="AXI_STR_TXC_ARESETN" SIGIS="RST" SIGNAME="AXI_STR_TXC_ARESETN"/>
+        <PORT BUS="S_AXI:AXI_STR_TXC:AXI_STR_TXD:AXI_STR_RXS:AXI_STR_RXD" DEF_SIGNAME="ARESETN" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="35" NAME="AXI_STR_RXD_ARESETN" SIGIS="RST" SIGNAME="AXI_STR_RXD_ARESETN"/>
+        <PORT BUS="S_AXI:AXI_STR_TXC:AXI_STR_TXD:AXI_STR_RXS:AXI_STR_RXD" DEF_SIGNAME="ARESETN" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="42" NAME="AXI_STR_RXS_ARESETN" SIGIS="RST" SIGNAME="AXI_STR_RXS_ARESETN"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="2" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="ETHERNET_INTERRUPT"/>
+        <PORT BUS="S_AXI:AXI_STR_TXC:AXI_STR_TXD:AXI_STR_RXS:AXI_STR_RXD" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
+        <PORT BUS="AXI_STR_TXD" DEF_SIGNAME="ETHERNET_dma_txd_TVALID" DIR="I" MPD_INDEX="22" NAME="AXI_STR_TXD_TVALID" SIGNAME="ETHERNET_dma_txd_TVALID"/>
+        <PORT BUS="AXI_STR_TXD" DEF_SIGNAME="ETHERNET_dma_txd_TREADY" DIR="O" MPD_INDEX="23" NAME="AXI_STR_TXD_TREADY" SIGNAME="ETHERNET_dma_txd_TREADY"/>
+        <PORT BUS="AXI_STR_TXD" DEF_SIGNAME="ETHERNET_dma_txd_TLAST" DIR="I" MPD_INDEX="24" NAME="AXI_STR_TXD_TLAST" SIGNAME="ETHERNET_dma_txd_TLAST"/>
+        <PORT BUS="AXI_STR_TXD" DEF_SIGNAME="ETHERNET_dma_txd_TKEEP" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="AXI_STR_TXD_TKEEP" RIGHT="0" SIGNAME="ETHERNET_dma_txd_TKEEP" VECFORMULA="[3:0]"/>
+        <PORT BUS="AXI_STR_TXD" DEF_SIGNAME="ETHERNET_dma_txd_TDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="26" MSB="31" NAME="AXI_STR_TXD_TDATA" RIGHT="0" SIGNAME="ETHERNET_dma_txd_TDATA" VECFORMULA="[31:0]"/>
+        <PORT BUS="AXI_STR_TXC" DEF_SIGNAME="ETHERNET_dma_txc_TVALID" DIR="I" MPD_INDEX="29" NAME="AXI_STR_TXC_TVALID" SIGNAME="ETHERNET_dma_txc_TVALID"/>
+        <PORT BUS="AXI_STR_TXC" DEF_SIGNAME="ETHERNET_dma_txc_TREADY" DIR="O" MPD_INDEX="30" NAME="AXI_STR_TXC_TREADY" SIGNAME="ETHERNET_dma_txc_TREADY"/>
+        <PORT BUS="AXI_STR_TXC" DEF_SIGNAME="ETHERNET_dma_txc_TLAST" DIR="I" MPD_INDEX="31" NAME="AXI_STR_TXC_TLAST" SIGNAME="ETHERNET_dma_txc_TLAST"/>
+        <PORT BUS="AXI_STR_TXC" DEF_SIGNAME="ETHERNET_dma_txc_TKEEP" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="32" MSB="3" NAME="AXI_STR_TXC_TKEEP" RIGHT="0" SIGNAME="ETHERNET_dma_txc_TKEEP" VECFORMULA="[3:0]"/>
+        <PORT BUS="AXI_STR_TXC" DEF_SIGNAME="ETHERNET_dma_txc_TDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="33" MSB="31" NAME="AXI_STR_TXC_TDATA" RIGHT="0" SIGNAME="ETHERNET_dma_txc_TDATA" VECFORMULA="[31:0]"/>
+        <PORT BUS="AXI_STR_RXD" DEF_SIGNAME="ETHERNET_dma_rxd_TVALID" DIR="O" MPD_INDEX="36" NAME="AXI_STR_RXD_TVALID" SIGNAME="ETHERNET_dma_rxd_TVALID"/>
+        <PORT BUS="AXI_STR_RXD" DEF_SIGNAME="ETHERNET_dma_rxd_TREADY" DIR="I" MPD_INDEX="37" NAME="AXI_STR_RXD_TREADY" SIGNAME="ETHERNET_dma_rxd_TREADY"/>
+        <PORT BUS="AXI_STR_RXD" DEF_SIGNAME="ETHERNET_dma_rxd_TLAST" DIR="O" MPD_INDEX="38" NAME="AXI_STR_RXD_TLAST" SIGNAME="ETHERNET_dma_rxd_TLAST"/>
+        <PORT BUS="AXI_STR_RXD" DEF_SIGNAME="ETHERNET_dma_rxd_TKEEP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="39" MSB="3" NAME="AXI_STR_RXD_TKEEP" RIGHT="0" SIGNAME="ETHERNET_dma_rxd_TKEEP" VECFORMULA="[3:0]"/>
+        <PORT BUS="AXI_STR_RXD" DEF_SIGNAME="ETHERNET_dma_rxd_TDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="40" MSB="31" NAME="AXI_STR_RXD_TDATA" RIGHT="0" SIGNAME="ETHERNET_dma_rxd_TDATA" VECFORMULA="[31:0]"/>
+        <PORT BUS="AXI_STR_RXS" DEF_SIGNAME="ETHERNET_dma_rxs_TVALID" DIR="O" MPD_INDEX="43" NAME="AXI_STR_RXS_TVALID" SIGNAME="ETHERNET_dma_rxs_TVALID"/>
+        <PORT BUS="AXI_STR_RXS" DEF_SIGNAME="ETHERNET_dma_rxs_TREADY" DIR="I" MPD_INDEX="44" NAME="AXI_STR_RXS_TREADY" SIGNAME="ETHERNET_dma_rxs_TREADY"/>
+        <PORT BUS="AXI_STR_RXS" DEF_SIGNAME="ETHERNET_dma_rxs_TLAST" DIR="O" MPD_INDEX="45" NAME="AXI_STR_RXS_TLAST" SIGNAME="ETHERNET_dma_rxs_TLAST"/>
+        <PORT BUS="AXI_STR_RXS" DEF_SIGNAME="ETHERNET_dma_rxs_TKEEP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="46" MSB="3" NAME="AXI_STR_RXS_TKEEP" RIGHT="0" SIGNAME="ETHERNET_dma_rxs_TKEEP" VECFORMULA="[3:0]"/>
+        <PORT BUS="AXI_STR_RXS" DEF_SIGNAME="ETHERNET_dma_rxs_TDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="47" MSB="31" NAME="AXI_STR_RXS_TDATA" RIGHT="0" SIGNAME="ETHERNET_dma_rxs_TDATA" VECFORMULA="[31:0]"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="50" NAME="MGT_CLK_P" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="51" NAME="MGT_CLK_N" SIGNAME="__NOC__"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="53" MSB="3" NAME="MII_TXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="54" NAME="MII_TX_EN" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="55" NAME="MII_TX_ER" SIGNAME="__NOC__"/>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="56" MSB="3" NAME="MII_RXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="57" NAME="MII_RX_DV" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="58" NAME="MII_RX_ER" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="59" NAME="MII_RX_CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="61" NAME="MII_COL" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="62" NAME="MII_CRS" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" MPD_INDEX="71" NAME="GMII_COL" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" MPD_INDEX="72" NAME="GMII_CRS" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="73" NAME="TXP" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="74" NAME="TXN" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="75" NAME="RXP" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="76" NAME="RXN" SIGNAME="__NOC__"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="77" MSB="3" NAME="RGMII_TXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="78" NAME="RGMII_TX_CTL" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="79" NAME="RGMII_TXC" SIGNAME="__NOC__"/>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="RGMII_RXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="81" NAME="RGMII_RX_CTL" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="82" NAME="RGMII_RXC" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="AXIETHERNETIF" MPD_INDEX="84" NAME="MDIO_I" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IOS="AXIETHERNETIF" MPD_INDEX="85" NAME="MDIO_O" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IOS="AXIETHERNETIF" MPD_INDEX="86" NAME="MDIO_T" SIGNAME="__NOC__"/>
+        <PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="AXI_STR_AVBTX_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="88" NAME="AXI_STR_AVBTX_ARESETN" SIGNAME="__NOC__"/>
+        <PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="89" NAME="AXI_STR_AVBTX_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="AXI_STR_AVBTX_TREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="91" NAME="AXI_STR_AVBTX_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="92" MSB="7" NAME="AXI_STR_AVBTX_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="93" NAME="AXI_STR_AVBTX_TUSER" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
+        <PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="AXI_STR_AVBRX_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="AXI_STR_AVBRX_ARESETN" SIGNAME="__NOC__"/>
+        <PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="AXI_STR_AVBRX_TVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="AXI_STR_AVBRX_TLAST" SIGNAME="__NOC__"/>
+        <PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="98" MSB="7" NAME="AXI_STR_AVBRX_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
+        <PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="AXI_STR_AVBRX_TUSER" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
+        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="100" NAME="RTC_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="101" NAME="AV_INTERRUPT_10MS" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="102" NAME="AV_INTERRUPT_PTP_TX" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="103" NAME="AV_INTERRUPT_PTP_RX" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="104" MSB="31" NAME="AV_RTC_NANOSECFIELD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="47" LSB="0" MPD_INDEX="105" MSB="47" NAME="AV_RTC_SECFIELD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[47:0]"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="106" NAME="AV_CLK_8K" SIGNAME="__NOC__"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="107" MSB="31" NAME="AV_RTC_NANOSECFIELD_1722" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="ETHERNET_dma_txd" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="AXI_STR_TXD" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_TXD_TREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_TKEEP"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_TDATA"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="ETHERNET_dma_txc" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="AXI_STR_TXC" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_TXC_TREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_TKEEP"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_TDATA"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="ETHERNET_dma_rxd" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="4" NAME="AXI_STR_RXD" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXD_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_TREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXD_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXD_TKEEP"/>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXD_TDATA"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="ETHERNET_dma_rxs" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="AXI_STR_RXS" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXS_TVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_TREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXS_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXS_TKEEP"/>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXS_TDATA"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="5" NAME="AXI_STR_AVBTX" PROTOCOL="XIL_AXI_STREAM_ETH_AVB_TX" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBTX_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBTX_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBTX_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBTX_TREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBTX_TLAST"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBTX_TDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBTX_TUSER"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="6" NAME="AXI_STR_AVBRX" PROTOCOL="XIL_AXI_STREAM_ETH_AVB_RX" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBRX_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBRX_ARESETN"/>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBRX_TVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBRX_TLAST"/>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBRX_TDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBRX_TUSER"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <IOINTERFACES>
+        <IOINTERFACE MPD_INDEX="0" NAME="AXIETHERNETIF" TYPE="XIL_AXIETHERNET_V1">
+          <PORTMAPS>
+            <PORTMAP DIR="IO" PHYSICAL="MDIO"/>
+            <PORTMAP DIR="O" PHYSICAL="MDC"/>
+            <PORTMAP DIR="O" PHYSICAL="GMII_TX_ER"/>
+            <PORTMAP DIR="O" PHYSICAL="GMII_TXD"/>
+            <PORTMAP DIR="O" PHYSICAL="GMII_TX_EN"/>
+            <PORTMAP DIR="I" PHYSICAL="MII_TX_CLK"/>
+            <PORTMAP DIR="O" PHYSICAL="GMII_TX_CLK"/>
+            <PORTMAP DIR="I" PHYSICAL="GMII_RXD"/>
+            <PORTMAP DIR="I" PHYSICAL="GMII_RX_ER"/>
+            <PORTMAP DIR="I" PHYSICAL="GMII_RX_CLK"/>
+            <PORTMAP DIR="I" PHYSICAL="GMII_RX_DV"/>
+            <PORTMAP DIR="O" PHYSICAL="PHY_RST_N"/>
+            <PORTMAP DIR="I" PHYSICAL="GTX_CLK"/>
+            <PORTMAP DIR="I" PHYSICAL="MGT_CLK_P"/>
+            <PORTMAP DIR="I" PHYSICAL="MGT_CLK_N"/>
+            <PORTMAP DIR="O" PHYSICAL="MII_TXD"/>
+            <PORTMAP DIR="O" PHYSICAL="MII_TX_EN"/>
+            <PORTMAP DIR="O" PHYSICAL="MII_TX_ER"/>
+            <PORTMAP DIR="I" PHYSICAL="MII_RXD"/>
+            <PORTMAP DIR="I" PHYSICAL="MII_RX_DV"/>
+            <PORTMAP DIR="I" PHYSICAL="MII_RX_ER"/>
+            <PORTMAP DIR="I" PHYSICAL="MII_RX_CLK"/>
+            <PORTMAP DIR="I" PHYSICAL="MII_COL"/>
+            <PORTMAP DIR="I" PHYSICAL="MII_CRS"/>
+            <PORTMAP DIR="I" PHYSICAL="GMII_COL"/>
+            <PORTMAP DIR="I" PHYSICAL="GMII_CRS"/>
+            <PORTMAP DIR="O" PHYSICAL="TXP"/>
+            <PORTMAP DIR="O" PHYSICAL="TXN"/>
+            <PORTMAP DIR="I" PHYSICAL="RXP"/>
+            <PORTMAP DIR="I" PHYSICAL="RXN"/>
+            <PORTMAP DIR="O" PHYSICAL="RGMII_TXD"/>
+            <PORTMAP DIR="O" PHYSICAL="RGMII_TX_CTL"/>
+            <PORTMAP DIR="O" PHYSICAL="RGMII_TXC"/>
+            <PORTMAP DIR="I" PHYSICAL="RGMII_RXD"/>
+            <PORTMAP DIR="I" PHYSICAL="RGMII_RX_CTL"/>
+            <PORTMAP DIR="I" PHYSICAL="RGMII_RXC"/>
+            <PORTMAP DIR="I" PHYSICAL="MDIO_I"/>
+            <PORTMAP DIR="O" PHYSICAL="MDIO_O"/>
+            <PORTMAP DIR="O" PHYSICAL="MDIO_T"/>
+          </PORTMAPS>
+        </IOINTERFACE>
+      </IOINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="1092878336" BASENAME="C_BASEADDR" BASEVALUE="0x41240000" HIGHDECIMAL="1093140479" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4127ffff" MEMTYPE="REGISTER" MINSIZE="0x40000" SIZE="262144" SIZEABRV="256K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="0"/>
+      </INTERRUPTINFO>
+    </MODULE>
+    <MODULE HWVERSION="3.00.a" INSTANCE="ETHERNET_dma" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="PERIPHERAL" MODTYPE="axi_dma">
+      <DESCRIPTION TYPE="SHORT">AXI DMA Engine</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">AXI MemoryMap to/from AXI Stream Direct Memory Access Engine</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_dma_v3_00_a/doc/axi_dma_ds781.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER MPD_INDEX="0" NAME="C_S_AXI_LITE_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Lite Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="1" NAME="C_S_AXI_LITE_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Lite Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="2" NAME="C_DLYTMR_RESOLUTION" TYPE="INTEGER" VALUE="1250">
+          <DESCRIPTION>Delay Timer Counter Resolution </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="3" NAME="C_PRMRY_IS_ACLK_ASYNC" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Primary clock Is Asynchronous </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="C_SG_INCLUDE_DESC_QUEUE" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Include Scatter Gather Descriptor Queuing</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="5" NAME="C_SG_INCLUDE_STSCNTRL_STRM" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Include AXI Status and Control Streams</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_SG_USE_STSAPP_LENGTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Use Status Stream App Length</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="7" NAME="C_SG_LENGTH_WIDTH" TYPE="INTEGER" VALUE="16">
+          <DESCRIPTION>Buffer Length Field Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_SG_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI SG Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_M_AXI_SG_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI SG Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Control Stream Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_S_AXIS_S2MM_STS_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Status Stream Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="12" NAME="C_INCLUDE_MM2S" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Include MM2S Channel</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="13" NAME="C_INCLUDE_MM2S_DRE" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Include MM2S Data Realignment Engine</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_MM2S_BURST_SIZE" TYPE="INTEGER" VALUE="16">
+          <DESCRIPTION>Maximum Memory Map Burst Size for MM2S</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_M_AXI_MM2S_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>MM2S Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="16" NAME="C_M_AXI_MM2S_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>MM2S Memory Map Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="17" NAME="C_M_AXIS_MM2S_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>MM2S Stream Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="18" NAME="C_INCLUDE_S2MM" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Include S2MM Channel</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="19" NAME="C_INCLUDE_S2MM_DRE" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Include S2MM Data Realignment Engine</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="20" NAME="C_S2MM_BURST_SIZE" TYPE="INTEGER" VALUE="16">
+          <DESCRIPTION>Maximum Memory Map Burst Size for S2MM (data beats)</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="21" NAME="C_M_AXI_S2MM_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>S2MM Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="22" NAME="C_M_AXI_S2MM_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>S2MM Memory Map Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="23" NAME="C_S_AXIS_S2MM_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>S2MM Stream Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="24" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="32" MPD_INDEX="25" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x41e00000">
+          <DESCRIPTION>Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="33" MPD_INDEX="26" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x41e0ffff">
+          <DESCRIPTION>High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="27" NAME="C_S_AXI_LITE_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>AXI Lite Clock Frequency</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="28" NAME="C_M_AXI_SG_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>AXI Scatter Gather Clock Frequency</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="29" NAME="C_M_AXI_MM2S_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>AXI MM2S Clock Frequency</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="30" NAME="C_M_AXI_S2MM_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
+          <DESCRIPTION>AXI S2MM Clock Frequency</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_LITE_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>AXI Lite Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="32" NAME="C_S_AXI_LITE_SUPPORTS_READ" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>AXI Lite Supports Read Access</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_LITE_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>AXI Lite Supports Write Access</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SG_PROTOCOL" TYPE="STRING" VALUE="AXI4">
+          <DESCRIPTION>AXI SG Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="35" NAME="C_M_AXI_SG_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>AXI SG Support Threads</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="36" NAME="C_M_AXI_SG_THREAD_ID_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Base Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="37" NAME="C_M_AXI_SG_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>AXI SG Supports Narrow Bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="38" NAME="C_M_AXI_SG_SUPPORTS_READ" TYPE="STRING" VALUE="1">
+          <DESCRIPTION>AXI SG Generates Read Accesses</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_SG_SUPPORTS_WRITE" TYPE="STRING" VALUE="1">
+          <DESCRIPTION>AXI SG Generates Write Accesses</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="40" NAME="C_M_AXI_MM2S_PROTOCOL" TYPE="STRING" VALUE="AXI4">
+          <DESCRIPTION>AXI MM2S Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="41" NAME="C_M_AXI_MM2S_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>AXI MM2S Support Threads</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_MM2S_THREAD_ID_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>AXI MM2S Thread ID Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="43" NAME="C_M_AXI_MM2S_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>AXI MM2S Supports Narrow Bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="44" NAME="C_M_AXI_MM2S_SUPPORTS_READ" TYPE="STRING" VALUE="1">
+          <DESCRIPTION>AXI MM2S Generates Read Accesses</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="45" NAME="C_M_AXI_MM2S_SUPPORTS_WRITE" TYPE="STRING" VALUE="0">
+          <DESCRIPTION>AXI MM2S Generates Write Accesses</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="46" NAME="C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING" TYPE="INTEGER" VALUE="4">
+          <DESCRIPTION>AXI MM2S Interface Read Issuing</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="47" NAME="C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH" TYPE="INTEGER" VALUE="512">
+          <DESCRIPTION>AXI MM2S Interface Read FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="48" NAME="C_M_AXI_S2MM_PROTOCOL" TYPE="STRING" VALUE="AXI4">
+          <DESCRIPTION>AXI S2MM Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_S2MM_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>AXI S2MM Support Threads</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_S2MM_THREAD_ID_WIDTH" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>AXI S2MM Thread ID Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_S2MM_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>AXI S2MM Supports Narrow Bursts</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_S2MM_SUPPORTS_WRITE" TYPE="STRING" VALUE="1">
+          <DESCRIPTION>AXI S2MM Generates Write Accesses</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_S2MM_SUPPORTS_READ" TYPE="STRING" VALUE="0">
+          <DESCRIPTION>AXI S2MM Generates Read Accesses</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="54" NAME="C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING" TYPE="INTEGER" VALUE="4">
+          <DESCRIPTION>AXI S2MM Interface Write Issuing</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="55" NAME="C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH" TYPE="INTEGER" VALUE="512">
+          <DESCRIPTION>AXI S2MM Interface Write FIFO Depth</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="56" NAME="C_M_AXIS_MM2S_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_DATA">
+          <DESCRIPTION>AXI MM2S Stream Interface Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="57" NAME="C_S_AXIS_S2MM_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_DATA">
+          <DESCRIPTION>AXI S2MM Stream Interface Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="58" NAME="C_M_AXIS_CNTRL_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_CTRL">
+          <DESCRIPTION>AXI MM2S Control Stream Interface Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="59" NAME="C_S_AXIS_STS_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_CTRL">
+          <DESCRIPTION>AXI S2MM Status Stream Interface Protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="12" NAME="C_INTERCONNECT_S_AXI_LITE_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" NAME="C_INTERCONNECT_S_AXI_LITE_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_S_AXI_LITE_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_S_AXI_LITE_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" NAME="C_INTERCONNECT_S_AXI_LITE_B_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" NAME="C_INTERCONNECT_M_AXI_SG_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="18" NAME="C_INTERCONNECT_M_AXI_SG_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="19" NAME="C_INTERCONNECT_M_AXI_SG_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="20" NAME="C_INTERCONNECT_M_AXI_SG_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="21" NAME="C_INTERCONNECT_M_AXI_SG_B_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="22" NAME="C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="23" NAME="C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="24" NAME="C_INTERCONNECT_M_AXI_MM2S_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="25" NAME="C_INTERCONNECT_M_AXI_MM2S_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="26" NAME="C_INTERCONNECT_M_AXI_MM2S_B_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="27" NAME="C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="28" NAME="C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="29" NAME="C_INTERCONNECT_M_AXI_S2MM_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="30" NAME="C_INTERCONNECT_M_AXI_S2MM_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="31" NAME="C_INTERCONNECT_M_AXI_S2MM_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT BUS="S_AXI_LITE" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="s_axi_lite_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT BUS="M_AXI_SG" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="m_axi_sg_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT BUS="M_AXI_MM2S:M_AXIS_CNTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="m_axi_mm2s_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT BUS="M_AXI_S2MM:S_AXIS_STS" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="m_axi_s2mm_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
+        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="RESET_OUT_N" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="63" NAME="mm2s_prmry_reset_out_n" SIGNAME="AXI_STR_TXD_ARESETN"/>
+        <PORT BUS="M_AXIS_CNTRL" DEF_SIGNAME="RESET_OUT_N" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="69" NAME="mm2s_cntrl_reset_out_n" SIGNAME="AXI_STR_TXC_ARESETN"/>
+        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="RESET_OUT_N" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="91" NAME="s2mm_prmry_reset_out_n" SIGNAME="AXI_STR_RXD_ARESETN"/>
+        <PORT BUS="S_AXIS_STS" DEF_SIGNAME="RESET_OUT_N" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="97" NAME="s2mm_sts_reset_out_n" SIGNAME="AXI_STR_RXS_ARESETN"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="103" NAME="mm2s_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="ETHERNET_dma_mm2s_introut"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="104" NAME="s2mm_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="ETHERNET_dma_s2mm_introut"/>
+        <PORT BUS="S_AXI_LITE:M_AXI_SG:M_AXI_MM2S:M_AXI_S2MM:S_AXIS_STS:M_AXIS_CNTRL:M_AXIS_MM2S:S_AXIS_S2MM" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="4" NAME="axi_resetn" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="5" NAME="s_axi_lite_awvalid" SIGNAME="axi4lite_0_M_AWVALID"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="6" NAME="s_axi_lite_awready" SIGNAME="axi4lite_0_M_AWREADY"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="s_axi_lite_awaddr" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[C_S_AXI_LITE_ADDR_WIDTH-1:0]"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="s_axi_lite_wvalid" SIGNAME="axi4lite_0_M_WVALID"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="s_axi_lite_wready" SIGNAME="axi4lite_0_M_WREADY"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="10" MSB="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[C_S_AXI_LITE_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="12" NAME="s_axi_lite_bvalid" SIGNAME="axi4lite_0_M_BVALID"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="13" NAME="s_axi_lite_bready" SIGNAME="axi4lite_0_M_BREADY"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="s_axi_lite_arvalid" SIGNAME="axi4lite_0_M_ARVALID"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="s_axi_lite_arready" SIGNAME="axi4lite_0_M_ARREADY"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="s_axi_lite_araddr" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[C_S_AXI_LITE_ADDR_WIDTH-1:0]"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="s_axi_lite_rvalid" SIGNAME="axi4lite_0_M_RVALID"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="s_axi_lite_rready" SIGNAME="axi4lite_0_M_RREADY"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[C_S_AXI_LITE_DATA_WIDTH-1:0]"/>
+        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="21" MSB="31" NAME="m_axi_sg_awaddr" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[C_M_AXI_SG_ADDR_WIDTH-1:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="22" MSB="7" NAME="m_axi_sg_awlen" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="23" MSB="2" NAME="m_axi_sg_awsize" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="m_axi_sg_awburst" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="25" MSB="2" NAME="m_axi_sg_awprot" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="m_axi_sg_awcache" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="27" NAME="m_axi_sg_awvalid" SIGNAME="axi4_0_S_AWVALID"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="28" NAME="m_axi_sg_awready" SIGNAME="axi4_0_S_AWREADY"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="29" MSB="31" NAME="m_axi_sg_wdata" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[C_M_AXI_SG_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="30" MSB="3" NAME="m_axi_sg_wstrb" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[(C_M_AXI_SG_DATA_WIDTH/8)-1:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="31" NAME="m_axi_sg_wlast" SIGNAME="axi4_0_S_WLAST"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="32" NAME="m_axi_sg_wvalid" SIGNAME="axi4_0_S_WVALID"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="33" NAME="m_axi_sg_wready" SIGNAME="axi4_0_S_WREADY"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="m_axi_sg_bresp" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="35" NAME="m_axi_sg_bvalid" SIGNAME="axi4_0_S_BVALID"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="36" NAME="m_axi_sg_bready" SIGNAME="axi4_0_S_BREADY"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="37" MSB="31" NAME="m_axi_sg_araddr" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[C_M_AXI_SG_ADDR_WIDTH-1:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="38" MSB="7" NAME="m_axi_sg_arlen" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="39" MSB="2" NAME="m_axi_sg_arsize" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="40" MSB="1" NAME="m_axi_sg_arburst" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="41" MSB="2" NAME="m_axi_sg_arprot" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="42" MSB="3" NAME="m_axi_sg_arcache" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="43" NAME="m_axi_sg_arvalid" SIGNAME="axi4_0_S_ARVALID"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="44" NAME="m_axi_sg_arready" SIGNAME="axi4_0_S_ARREADY"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="45" MSB="31" NAME="m_axi_sg_rdata" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[C_M_AXI_SG_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="46" MSB="1" NAME="m_axi_sg_rresp" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="47" NAME="m_axi_sg_rlast" SIGNAME="axi4_0_S_RLAST"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="48" NAME="m_axi_sg_rvalid" SIGNAME="axi4_0_S_RVALID"/>
+        <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="49" NAME="m_axi_sg_rready" SIGNAME="axi4_0_S_RREADY"/>
+        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="m_axi_mm2s_araddr" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[C_M_AXI_MM2S_ADDR_WIDTH-1:0]"/>
+        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="m_axi_mm2s_arlen" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="52" MSB="2" NAME="m_axi_mm2s_arsize" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="53" MSB="1" NAME="m_axi_mm2s_arburst" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="54" MSB="2" NAME="m_axi_mm2s_arprot" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="55" MSB="3" NAME="m_axi_mm2s_arcache" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="56" NAME="m_axi_mm2s_arvalid" SIGNAME="axi4_0_S_ARVALID"/>
+        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="57" NAME="m_axi_mm2s_arready" SIGNAME="axi4_0_S_ARREADY"/>
+        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="58" MSB="31" NAME="m_axi_mm2s_rdata" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[C_M_AXI_MM2S_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="59" MSB="1" NAME="m_axi_mm2s_rresp" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="60" NAME="m_axi_mm2s_rlast" SIGNAME="axi4_0_S_RLAST"/>
+        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="61" NAME="m_axi_mm2s_rvalid" SIGNAME="axi4_0_S_RVALID"/>
+        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="62" NAME="m_axi_mm2s_rready" SIGNAME="axi4_0_S_RREADY"/>
+        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="ETHERNET_dma_txd_TDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="64" MSB="31" NAME="m_axis_mm2s_tdata" RIGHT="0" SIGNAME="ETHERNET_dma_txd_TDATA" VECFORMULA="[C_M_AXIS_MM2S_TDATA_WIDTH-1:0]"/>
+        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="ETHERNET_dma_txd_TKEEP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="65" MSB="3" NAME="m_axis_mm2s_tkeep" RIGHT="0" SIGNAME="ETHERNET_dma_txd_TKEEP" VECFORMULA="[(C_M_AXIS_MM2S_TDATA_WIDTH/8)-1:0]"/>
+        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="ETHERNET_dma_txd_TVALID" DIR="O" MPD_INDEX="66" NAME="m_axis_mm2s_tvalid" SIGNAME="ETHERNET_dma_txd_TVALID"/>
+        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="ETHERNET_dma_txd_TREADY" DIR="I" MPD_INDEX="67" NAME="m_axis_mm2s_tready" SIGNAME="ETHERNET_dma_txd_TREADY"/>
+        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="ETHERNET_dma_txd_TLAST" DIR="O" MPD_INDEX="68" NAME="m_axis_mm2s_tlast" SIGNAME="ETHERNET_dma_txd_TLAST"/>
+        <PORT BUS="M_AXIS_CNTRL" DEF_SIGNAME="ETHERNET_dma_txc_TDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="70" MSB="31" NAME="m_axis_mm2s_cntrl_tdata" RIGHT="0" SIGNAME="ETHERNET_dma_txc_TDATA" VECFORMULA="[C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1:0]"/>
+        <PORT BUS="M_AXIS_CNTRL" DEF_SIGNAME="ETHERNET_dma_txc_TKEEP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="71" MSB="3" NAME="m_axis_mm2s_cntrl_tkeep" RIGHT="0" SIGNAME="ETHERNET_dma_txc_TKEEP" VECFORMULA="[(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1:0]"/>
+        <PORT BUS="M_AXIS_CNTRL" DEF_SIGNAME="ETHERNET_dma_txc_TVALID" DIR="O" MPD_INDEX="72" NAME="m_axis_mm2s_cntrl_tvalid" SIGNAME="ETHERNET_dma_txc_TVALID"/>
+        <PORT BUS="M_AXIS_CNTRL" DEF_SIGNAME="ETHERNET_dma_txc_TREADY" DIR="I" MPD_INDEX="73" NAME="m_axis_mm2s_cntrl_tready" SIGNAME="ETHERNET_dma_txc_TREADY"/>
+        <PORT BUS="M_AXIS_CNTRL" DEF_SIGNAME="ETHERNET_dma_txc_TLAST" DIR="O" MPD_INDEX="74" NAME="m_axis_mm2s_cntrl_tlast" SIGNAME="ETHERNET_dma_txc_TLAST"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="75" MSB="31" NAME="m_axi_s2mm_awaddr" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[C_M_AXI_S2MM_ADDR_WIDTH-1:0]"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="76" MSB="7" NAME="m_axi_s2mm_awlen" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="77" MSB="2" NAME="m_axi_s2mm_awsize" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="78" MSB="1" NAME="m_axi_s2mm_awburst" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="79" MSB="2" NAME="m_axi_s2mm_awprot" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="m_axi_s2mm_awcache" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="81" NAME="m_axi_s2mm_awvalid" SIGNAME="axi4_0_S_AWVALID"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="82" NAME="m_axi_s2mm_awready" SIGNAME="axi4_0_S_AWREADY"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="83" MSB="31" NAME="m_axi_s2mm_wdata" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[C_M_AXI_S2MM_DATA_WIDTH-1:0]"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="84" MSB="3" NAME="m_axi_s2mm_wstrb" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[(C_M_AXI_S2MM_DATA_WIDTH/8)-1:0]"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="85" NAME="m_axi_s2mm_wlast" SIGNAME="axi4_0_S_WLAST"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="86" NAME="m_axi_s2mm_wvalid" SIGNAME="axi4_0_S_WVALID"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="87" NAME="m_axi_s2mm_wready" SIGNAME="axi4_0_S_WREADY"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="88" MSB="1" NAME="m_axi_s2mm_bresp" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="89" NAME="m_axi_s2mm_bvalid" SIGNAME="axi4_0_S_BVALID"/>
+        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="90" NAME="m_axi_s2mm_bready" SIGNAME="axi4_0_S_BREADY"/>
+        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="ETHERNET_dma_rxd_TDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="92" MSB="31" NAME="s_axis_s2mm_tdata" RIGHT="0" SIGNAME="ETHERNET_dma_rxd_TDATA" VECFORMULA="[C_S_AXIS_S2MM_TDATA_WIDTH-1:0]"/>
+        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="ETHERNET_dma_rxd_TKEEP" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="93" MSB="3" NAME="s_axis_s2mm_tkeep" RIGHT="0" SIGNAME="ETHERNET_dma_rxd_TKEEP" VECFORMULA="[(C_S_AXIS_S2MM_TDATA_WIDTH/8)-1:0]"/>
+        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="ETHERNET_dma_rxd_TVALID" DIR="I" MPD_INDEX="94" NAME="s_axis_s2mm_tvalid" SIGNAME="ETHERNET_dma_rxd_TVALID"/>
+        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="ETHERNET_dma_rxd_TREADY" DIR="O" MPD_INDEX="95" NAME="s_axis_s2mm_tready" SIGNAME="ETHERNET_dma_rxd_TREADY"/>
+        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="ETHERNET_dma_rxd_TLAST" DIR="I" MPD_INDEX="96" NAME="s_axis_s2mm_tlast" SIGNAME="ETHERNET_dma_rxd_TLAST"/>
+        <PORT BUS="S_AXIS_STS" DEF_SIGNAME="ETHERNET_dma_rxs_TDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="98" MSB="31" NAME="s_axis_s2mm_sts_tdata" RIGHT="0" SIGNAME="ETHERNET_dma_rxs_TDATA" VECFORMULA="[C_S_AXIS_S2MM_STS_TDATA_WIDTH-1:0]"/>
+        <PORT BUS="S_AXIS_STS" DEF_SIGNAME="ETHERNET_dma_rxs_TKEEP" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="99" MSB="3" NAME="s_axis_s2mm_sts_tkeep" RIGHT="0" SIGNAME="ETHERNET_dma_rxs_TKEEP" VECFORMULA="[(C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1:0]"/>
+        <PORT BUS="S_AXIS_STS" DEF_SIGNAME="ETHERNET_dma_rxs_TVALID" DIR="I" MPD_INDEX="100" NAME="s_axis_s2mm_sts_tvalid" SIGNAME="ETHERNET_dma_rxs_TVALID"/>
+        <PORT BUS="S_AXIS_STS" DEF_SIGNAME="ETHERNET_dma_rxs_TREADY" DIR="O" MPD_INDEX="101" NAME="s_axis_s2mm_sts_tready" SIGNAME="ETHERNET_dma_rxs_TREADY"/>
+        <PORT BUS="S_AXIS_STS" DEF_SIGNAME="ETHERNET_dma_rxs_TLAST" DIR="I" MPD_INDEX="102" NAME="s_axis_s2mm_sts_tlast" SIGNAME="ETHERNET_dma_rxs_TLAST"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_LITE" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_awvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_awready"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_awaddr"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_wvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_wready"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_wdata"/>
+            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_bresp"/>
+            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_bvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_bready"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_arvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_arready"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_araddr"/>
+            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_rready"/>
+            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rdata"/>
+            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rresp"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="M_AXI_SG" PROTOCOL="AXI4" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_awaddr"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_awlen"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_awsize"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_awburst"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_awprot"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_awcache"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_awvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_awready"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_wdata"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_wstrb"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_wlast"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_wvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_wready"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_bresp"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_bvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_bready"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_araddr"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arlen"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arsize"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arburst"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arprot"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arcache"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_arready"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rdata"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rresp"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rlast"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="M_AXI_MM2S" PROTOCOL="AXI4" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_araddr"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arlen"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arsize"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arburst"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arprot"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arcache"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_arready"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rdata"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rresp"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rlast"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_rready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="ETHERNET_dma_txc" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="6" NAME="M_AXIS_CNTRL" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_aclk"/>
+            <PORTMAP DIR="O" PHYSICAL="mm2s_cntrl_reset_out_n"/>
+            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_cntrl_tdata"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_cntrl_tkeep"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_cntrl_tvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axis_mm2s_cntrl_tready"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_cntrl_tlast"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="M_AXI_S2MM" PROTOCOL="AXI4" TYPE="MASTER">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_aclk"/>
+            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awaddr"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awlen"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awsize"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awburst"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awprot"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awcache"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_awready"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wdata"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wstrb"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wlast"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_wready"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_bresp"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_bvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_bready"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="ETHERNET_dma_rxs" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="7" NAME="S_AXIS_STS" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_aclk"/>
+            <PORTMAP DIR="O" PHYSICAL="s2mm_sts_reset_out_n"/>
+            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_sts_tdata"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_sts_tkeep"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_sts_tvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s_axis_s2mm_sts_tready"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_sts_tlast"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="ETHERNET_dma_txd" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="4" NAME="M_AXIS_MM2S" TYPE="INITIATOR">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="mm2s_prmry_reset_out_n"/>
+            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tdata"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tkeep"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tvalid"/>
+            <PORTMAP DIR="I" PHYSICAL="m_axis_mm2s_tready"/>
+            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tlast"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="ETHERNET_dma_rxd" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="5" NAME="S_AXIS_S2MM" TYPE="TARGET">
+          <PORTMAPS>
+            <PORTMAP DIR="O" PHYSICAL="s2mm_prmry_reset_out_n"/>
+            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tdata"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tkeep"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tvalid"/>
+            <PORTMAP DIR="O" PHYSICAL="s_axis_s2mm_tready"/>
+            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tlast"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="1105199104" BASENAME="C_BASEADDR" BASEVALUE="0x41e00000" HIGHDECIMAL="1105264639" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41e0ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI_LITE"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="1"/>
+        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="2"/>
+      </INTERRUPTINFO>
+    </MODULE>
+    <MODULE HWVERSION="1.01.a" INSTANCE="microblaze_0_intc" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc">
+      <DESCRIPTION TYPE="SHORT">AXI Interrupt Controller</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">intc core attached to the AXI</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_intc_v1_01_a/doc/ds747_axi_intc.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41200000">
+          <DESCRIPTION>AXI Base Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4120ffff">
+          <DESCRIPTION>AXI High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_NUM_INTR_INPUTS" TYPE="INTEGER" VALUE="6">
+          <DESCRIPTION>Number of Interrupt Inputs </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_KIND_OF_INTR" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111000011">
+          <DESCRIPTION>Type of Interrupt for Each Input </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_KIND_OF_EDGE" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
+          <DESCRIPTION>Type of Each Edge Senstive Interrupt </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_KIND_OF_LVL" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
+          <DESCRIPTION>Type of Each Level Sensitive Interrupt </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="9" NAME="C_HAS_IPR" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Support IPR </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_HAS_SIE" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Support SIE </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_HAS_CIE" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Support CIE </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="12" NAME="C_HAS_IVR" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>Support IVR </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="13" NAME="C_IRQ_IS_LEVEL" TYPE="INTEGER" VALUE="1">
+          <DESCRIPTION>IRQ Output Use Level </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="14" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1">
+          <DESCRIPTION>The Sense of IRQ Output </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
+        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="20" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt">
+          <DESCRIPTION>Interrupt Request Output</DESCRIPTION>
+        </PORT>
+        <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="2" MPD_INDEX="19" MSB="5" NAME="INTR" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="ETHERNET_INTERRUPT &amp; ETHERNET_dma_mm2s_introut &amp; ETHERNET_dma_s2mm_introut &amp; Push_Buttons_4Bits_IP2INTC_Irpt &amp; RS232_Uart_1_Interrupt &amp; axi_timer_0_Interrupt" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]">
+          <SIGNALS>
+            <SIGNAL NAME="ETHERNET_INTERRUPT"/>
+            <SIGNAL NAME="ETHERNET_dma_mm2s_introut"/>
+            <SIGNAL NAME="ETHERNET_dma_s2mm_introut"/>
+            <SIGNAL NAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
+            <SIGNAL NAME="RS232_Uart_1_Interrupt"/>
+            <SIGNAL NAME="axi_timer_0_Interrupt"/>
+          </SIGNALS>
+          <DESCRIPTION>Interrupt Inputs</DESCRIPTION>
+        </PORT>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+      <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
+        <SOURCE INSTANCE="ETHERNET" PRIORITY="0" SIGNAME="ETHERNET_INTERRUPT"/>
+        <SOURCE INSTANCE="ETHERNET_dma" PRIORITY="1" SIGNAME="ETHERNET_dma_mm2s_introut"/>
+        <SOURCE INSTANCE="ETHERNET_dma" PRIORITY="2" SIGNAME="ETHERNET_dma_s2mm_introut"/>
+        <SOURCE INSTANCE="Push_Buttons_4Bits" PRIORITY="3" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
+        <SOURCE INSTANCE="RS232_Uart_1" PRIORITY="4" SIGNAME="RS232_Uart_1_Interrupt"/>
+        <SOURCE INSTANCE="axi_timer_0" PRIORITY="5" SIGNAME="axi_timer_0_Interrupt"/>
+        <TARGET INSTANCE="microblaze_0"/>
+      </INTERRUPTINFO>
+    </MODULE>
+    <MODULE HWVERSION="1.01.a" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="18" MODCLASS="PERIPHERAL" MODTYPE="axi_timer">
+      <DESCRIPTION TYPE="SHORT">AXI Timer/Counter</DESCRIPTION>
+      <DESCRIPTION TYPE="LONG">Timer counter with AXI interface</DESCRIPTION>
+      <DOCUMENTATION>
+        <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_timer_v1_01_a/doc/axi_timer_ds764.pdf" TYPE="IP"/>
+      </DOCUMENTATION>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+      <PARAMETERS>
+        <PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
+          <DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
+          <DESCRIPTION>Device Family</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="2" NAME="C_COUNT_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>The Width of Counter in Timer</DESCRIPTION>
+          <DESCRIPTION>Count Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="3" NAME="C_ONE_TIMER_ONLY" TYPE="INTEGER" VALUE="0">
+          <DESCRIPTION>Only One Timer is present</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="4" NAME="C_TRIG0_ASSERT" TYPE="std_logic" VALUE="1">
+          <DESCRIPTION>TRIG0 Active Level</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="5" NAME="C_TRIG1_ASSERT" TYPE="std_logic" VALUE="1">
+          <DESCRIPTION>TRIG1 Active Level</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="6" NAME="C_GEN0_ASSERT" TYPE="std_logic" VALUE="1">
+          <DESCRIPTION>GEN0 Active Level</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="7" NAME="C_GEN1_ASSERT" TYPE="std_logic" VALUE="1">
+          <DESCRIPTION>GEN1 Active Level</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="8" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41c00000">
+          <DESCRIPTION>AXI Base Address </DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="9" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x41c0ffff">
+          <DESCRIPTION>AXI High Address</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Address Width</DESCRIPTION>
+        </PARAMETER>
+        <PARAMETER MPD_INDEX="11" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
+          <DESCRIPTION>AXI Data Width</DESCRIPTION>
+        </PARAMETER>
+      </PARAMETERS>
+      <PORTS>
+        <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="7" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
+        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="5" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="axi_timer_0_Interrupt"/>
+        <PORT DIR="I" MPD_INDEX="0" NAME="CaptureTrig0" SIGNAME="__NOC__">
+          <DESCRIPTION>Capture Trig 0</DESCRIPTION>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="1" NAME="CaptureTrig1" SIGNAME="__NOC__">
+          <DESCRIPTION>Capture Trig 1</DESCRIPTION>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="2" NAME="GenerateOut0" SIGNAME="__NOC__">
+          <DESCRIPTION>Generate Out 0</DESCRIPTION>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="3" NAME="GenerateOut1" SIGNAME="__NOC__">
+          <DESCRIPTION>Generate Out 1</DESCRIPTION>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="4" NAME="PWM0" SIGNAME="__NOC__">
+          <DESCRIPTION>Pulse Width Modulation 0</DESCRIPTION>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="6" NAME="Freeze" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="8" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="10" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="13" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="21" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="22" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="24" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
+        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="25" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
+          <PORTMAPS>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
+            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
+            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
+          <SLAVES>
+            <SLAVE BUSINTERFACE="S_AXI"/>
+          </SLAVES>
+        </MEMRANGE>
+      </MEMORYMAP>
+      <INTERRUPTINFO TYPE="SOURCE">
+        <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="5"/>
+      </INTERRUPTINFO>
+    </MODULE>
+  </MODULES>
+
+</EDKSYSTEM>
\ No newline at end of file

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/HardwareWithEthernetFull/system_bd.bmm b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/HardwareWithEthernetFull/system_bd.bmm
new file mode 100644 (file)
index 0000000..4ccd72a
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/HardwareWithEthernetFull/system_bd.bmm
@@ -0,0 +1,32 @@
+// BMM LOC annotation file.\r
+//\r
+// Release 13.1 - Data2MEM O.40d, build 1.9 Aug 19, 2010\r
+// Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.\r
+\r
+\r
+///////////////////////////////////////////////////////////////////////////////\r
+//\r
+// Processor 'microblaze_0', ID 100, memory map.\r
+//\r
+///////////////////////////////////////////////////////////////////////////////\r
+\r
+ADDRESS_MAP microblaze_0 MICROBLAZE-LE 100\r
+\r
+\r
+    ///////////////////////////////////////////////////////////////////////////////\r
+    //\r
+    // Processor 'microblaze_0' address space 'microblaze_0_bram_block_combined' 0x00000000:0x00001FFF (8 KBytes).\r
+    //\r
+    ///////////////////////////////////////////////////////////////////////////////\r
+\r
+    ADDRESS_SPACE microblaze_0_bram_block_combined RAMB16 [0x00000000:0x00001FFF]\r
+        BUS_BLOCK\r
+            microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_0 [31:24] INPUT = microblaze_0_bram_block_combined_0.mem PLACED = X3Y26;\r
+            microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_1 [23:16] INPUT = microblaze_0_bram_block_combined_1.mem PLACED = X3Y28;\r
+            microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_2 [15:8] INPUT = microblaze_0_bram_block_combined_2.mem PLACED = X2Y30;\r
+            microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_3 [7:0] INPUT = microblaze_0_bram_block_combined_3.mem PLACED = X2Y28;\r
+        END_BUS_BLOCK;\r
+    END_ADDRESS_SPACE;\r
+\r
+END_ADDRESS_MAP;\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/.cproject b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/.cproject
new file mode 100644 (file)
index 0000000..edeebe7
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/.cproject
@@ -0,0 +1,1426 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 4.0.0?>\r
+\r
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
+       <storageModule moduleId="org.eclipse.cdt.core.settings">\r
+               <cconfiguration id="xilinx.gnu.mb.exe.debug.2007678521">\r
+                       <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.mb.exe.debug.2007678521" moduleId="org.eclipse.cdt.core.settings" name="Debug">\r
+                               <externalSettings/>\r
+                               <extensions>\r
+                                       <extension id="com.xilinx.sdk.managedbuilder.XELF.mb" point="org.eclipse.cdt.core.BinaryParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                                       <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+                               </extensions>\r
+                       </storageModule>\r
+                       <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+                               <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="xilinx.gnu.mb.exe.debug.2007678521" name="Debug" parent="xilinx.gnu.mb.exe.debug">\r
+                                       <folderInfo id="xilinx.gnu.mb.exe.debug.2007678521." name="/" resourcePath="">\r
+                                               <toolChain id="xilinx.gnu.mb.exe.debug.toolchain.1264363336" name="Xilinx MicroBlaze GNU Toolchain" superClass="xilinx.gnu.mb.exe.debug.toolchain">\r
+                                                       <targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.mb" id="xilinx.mb.target.gnu.base.debug.622178397" isAbstract="false" name="Debug Platform" superClass="xilinx.mb.target.gnu.base.debug"/>\r
+                                                       <builder buildPath="${workspace_loc:/RTOSDemo/Debug}" enableAutoBuild="true" id="xilinx.gnu.mb.toolchain.builder.debug.249498237" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU make" superClass="xilinx.gnu.mb.toolchain.builder.debug"/>\r
+                                                       <tool id="xilinx.gnu.mb.c.toolchain.assembler.debug.1789010617" name="MicroBlaze gcc assembler" superClass="xilinx.gnu.mb.c.toolchain.assembler.debug">\r
+                                                               <option id="xilinx.gnu.mb.assembler.usele.1259468559" name="Produce little endian code (-mlittle-endian)" superClass="xilinx.gnu.mb.assembler.usele" value="true" valueType="boolean"/>\r
+                                                               <inputType id="xilinx.gnu.assembler.input.434489882" superClass="xilinx.gnu.assembler.input"/>\r
+                                                       </tool>\r
+                                                       <tool id="xilinx.gnu.mb.c.toolchain.compiler.debug.858164244" name="MicroBlaze gcc compiler" superClass="xilinx.gnu.mb.c.toolchain.compiler.debug">\r
+                                                               <option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.1221649561" name="Optimization Level" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.compiler.option.debugging.level.53636576" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.mbversion.623678112" name="MicroBlaze Version" superClass="xilinx.gnu.mb.compiler.inferred.mbversion" value="8.10.a" valueType="string"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usele.1279689701" name="Produce little endian code (-mlittle-endian)" superClass="xilinx.gnu.mb.compiler.inferred.usele" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usebarrel.1957146974" name="Use Barrel Shifter (-mxl-barrel-shift)" superClass="xilinx.gnu.mb.compiler.inferred.usebarrel" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.usepcmp.1099598550" name="Use Pattern Compare (-mxl-pattern-compare)" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>\r
+                                                               <option id="xilinx.gnu.mb.compiler.inferred.mul.307413105" name="Hardware Multiplier" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>\r
+                                                               <option id="xilinx.gnu.compiler.inferred.swplatform.includes.891716405" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">\r
+                                                                       <listOptionValue builtIn="false" value="../../StandAloneBSP/microblaze_0/include"/>\r
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diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/.project b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/.project
new file mode 100644 (file)
index 0000000..f14e5f2
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/.project
@@ -0,0 +1,82 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+       <name>RTOSDemo</name>\r
+       <comment>StandAloneBSP - microblaze_0</comment>\r
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+                                       <value>true</value>\r
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+                                       <value>all</value>\r
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+                                       <value></value>\r
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+                                       <value>make</value>\r
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+                                       <value>${workspace_loc:/RTOSDemo/Debug}</value>\r
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+                                       <value>clean</value>\r
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+                                       <value>true</value>\r
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+                                       <value>true</value>\r
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+                                       <value>true</value>\r
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+                                       <value>all</value>\r
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+       </natures>\r
+</projectDescription>\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/CreateProjectDirectoryStructure.bat b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/CreateProjectDirectoryStructure.bat
new file mode 100644 (file)
index 0000000..3ed26c6
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/CreateProjectDirectoryStructure.bat
@@ -0,0 +1,117 @@
+REM This file should be executed from the command line prior to the first\r
+REM build.  It will be necessary to refresh the Eclipse project once the\r
+REM .bat file has been executed (normally just press F5 to refresh).\r
+\r
+REM Copies all the required files from their location within the standard\r
+REM FreeRTOS directory structure to under the Eclipse project directory.\r
+REM This permits the Eclipse project to be used in 'managed' mode and without\r
+REM having to setup any linked resources.\r
+\r
+REM Files will also be copied into the BSP directory, which can be used to\r
+REM generate FreeRTOS BSP packages directly from within the Xilinx SDK.\r
+SET BSP_SOURCE=..\..\KernelAwareBSPRepository\bsp\freertos_v2_00_a\src\Source\r
+\r
+REM Standard paths\r
+SET FREERTOS_SOURCE=..\..\..\..\Source\r
+SET COMMON_SOURCE=..\..\..\Common\minimal\r
+SET COMMON_INCLUDE=..\..\..\Common\include\r
+SET LWIP_SOURCE=..\..\..\Common\ethernet\lwip-1.4.0\r
+\r
+REM Have the files already been copied?\r
+IF EXIST FreeRTOS_Source Goto END\r
+\r
+    REM Create the required directory structure.\r
+    MD FreeRTOS_Source\r
+    MD FreeRTOS_Source\include    \r
+    MD FreeRTOS_Source\portable\GCC\r
+    MD FreeRTOS_Source\portable\GCC\MicroBlazeV8\r
+    MD FreeRTOS_Source\portable\MemMang    \r
+    MD Demo_Source\r
+    MD Demo_Source\include\r
+    MD lwIP\api\r
+    MD lwIP\core\r
+    MD lwIP\core\ipv4\r
+    MD lwIP\include\r
+    MD lwIP\include\ipv4\r
+    MD lwIP\include\ipv4\lwip\r
+    MD lwIP\include\lwip\r
+    MD lwIP\include\netif\r
+    MD lwIP\netif\r
+    MD lwIP\netif\include\r
+    MD lwIP\netif\include\arch\r
+    \r
+    REM Copy the core kernel files into the SDK projects directory\r
+    copy %FREERTOS_SOURCE%\tasks.c FreeRTOS_Source\r
+    copy %FREERTOS_SOURCE%\queue.c FreeRTOS_Source\r
+    copy %FREERTOS_SOURCE%\list.c FreeRTOS_Source\r
+    copy %FREERTOS_SOURCE%\timers.c FreeRTOS_Source\r
+\r
+    REM Copy the core kernel files into the BSP directory\r
+    copy %FREERTOS_SOURCE%\tasks.c %BSP_SOURCE%\r
+    copy %FREERTOS_SOURCE%\queue.c %BSP_SOURCE%\r
+    copy %FREERTOS_SOURCE%\list.c %BSP_SOURCE%\r
+    copy %FREERTOS_SOURCE%\timers.c %BSP_SOURCE%\r
+    \r
+    REM Copy the common header files into the SDK projects directory\r
+    copy %FREERTOS_SOURCE%\include\*.* FreeRTOS_Source\include\r
+    \r
+    REM Copy the common header files into the BSP directory\r
+    copy %FREERTOS_SOURCE%\include\*.* %BSP_SOURCE%\include\r
+\r
+    REM Copy the portable layer files into the SDK projects directory\r
+    copy %FREERTOS_SOURCE%\portable\GCC\MicroBlazeV8\*.* FreeRTOS_Source\portable\GCC\MicroBlazeV8\r
+    \r
+    REM Copy the portable layer files into the BSP projects directory\r
+    copy %FREERTOS_SOURCE%\portable\GCC\MicroBlazeV8\*.* %BSP_SOURCE%\portable\GCC\MicroBlazeV8\r
+\r
+    REM Copy the basic memory allocation files into the SDK projects directory\r
+    copy %FREERTOS_SOURCE%\portable\MemMang\heap_3.c FreeRTOS_Source\portable\MemMang\r
+\r
+    REM Copy the basic memory allocation files into the BSP directory\r
+    copy %FREERTOS_SOURCE%\portable\MemMang\heap_3.c %BSP_SOURCE%\portable\MemMang\r
+\r
+    REM Copy the files that define the common demo tasks.\r
+    copy %COMMON_SOURCE%\dynamic.c         Demo_Source\r
+    copy %COMMON_SOURCE%\BlockQ.c          Demo_Source\r
+    copy %COMMON_SOURCE%\death.c           Demo_Source\r
+    copy %COMMON_SOURCE%\blocktim.c        Demo_Source\r
+    copy %COMMON_SOURCE%\semtest.c         Demo_Source\r
+    copy %COMMON_SOURCE%\PollQ.c           Demo_Source\r
+    copy %COMMON_SOURCE%\GenQTest.c        Demo_Source\r
+    copy %COMMON_SOURCE%\QPeek.c           Demo_Source\r
+    copy %COMMON_SOURCE%\recmutex.c        Demo_Source\r
+    copy %COMMON_SOURCE%\sp_flop.c         Demo_Source\r
+    copy %COMMON_SOURCE%\flash.c           Demo_Source\r
+    copy %COMMON_SOURCE%\comtest_strings.c Demo_Source\r
+    copy %COMMON_SOURCE%\TimerDemo.c       Demo_Source\r
+    \r
+    REM Copy the common demo file headers.\r
+    copy %COMMON_INCLUDE%\dynamic.h         Demo_Source\include\r
+    copy %COMMON_INCLUDE%\partest.h         Demo_Source\include\r
+    copy %COMMON_INCLUDE%\BlockQ.h          Demo_Source\include\r
+    copy %COMMON_INCLUDE%\death.h           Demo_Source\include\r
+    copy %COMMON_INCLUDE%\blocktim.h        Demo_Source\include\r
+    copy %COMMON_INCLUDE%\semtest.h         Demo_Source\include\r
+    copy %COMMON_INCLUDE%\PollQ.h           Demo_Source\include\r
+    copy %COMMON_INCLUDE%\GenQTest.h        Demo_Source\include\r
+    copy %COMMON_INCLUDE%\QPeek.h           Demo_Source\include\r
+    copy %COMMON_INCLUDE%\recmutex.h        Demo_Source\include\r
+    copy %COMMON_INCLUDE%\flop.h            Demo_Source\include\r
+    copy %COMMON_INCLUDE%\flash.h           Demo_Source\include\r
+    copy %COMMON_INCLUDE%\comtest_strings.h Demo_Source\include\r
+    copy %COMMON_INCLUDE%\serial.h          Demo_Source\include\r
+    copy %COMMON_INCLUDE%\comtest.h         Demo_Source\include\r
+    copy %COMMON_INCLUDE%\TimerDemo.h       Demo_Source\include\r
+    \r
+    REM Copy the required lwIP files\r
+    copy %LWIP_SOURCE%\src\api\*.c                       lwIP\api\r
+    copy %LWIP_SOURCE%\src\core\*.c                      lwIP\core\r
+    copy %LWIP_SOURCE%\src\core\ipv4\*.c                 lwIP\core\ipv4\r
+    copy %LWIP_SOURCE%\src\include\ipv4\lwip\*.h         lwIP\include\ipv4\lwip\r
+    copy %LWIP_SOURCE%\src\include\lwip\*.h              lwIP\include\lwip\r
+    copy %LWIP_SOURCE%\src\include\netif\*.h             lwIP\include\netif\r
+    copy %LWIP_SOURCE%\src\netif\etharp.c                lwIP\netif\r
+    copy %LWIP_SOURCE%\ports\MicroBlaze-Ethernet-Lite    lwip\netif\r
+    copy %LWIP_SOURCE%\ports\MicroBlaze-Ethernet-Lite\include\arch lwip\netif\include\arch\r
+\r
+: END\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/FreeRTOSConfig.h b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/FreeRTOSConfig.h
new file mode 100644 (file)
index 0000000..15585f4
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/FreeRTOSConfig.h
@@ -0,0 +1,181 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+       \r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+\r
+/* The following #error directive is to remind users that a batch file must be\r
+ * executed prior to this project being built.  The batch file *cannot* be \r
+ * executed from within older versions of Eclipse, but probably can be executed\r
+ * from within the Xilinx SDK.  Once it has been executed, re-open or refresh \r
+ * the Eclipse project and remove the #error line below.\r
+ */\r
+//#error Ensure CreateProjectDirectoryStructure.bat has been executed before building.  See comment immediately above.\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+#define configUSE_PREEMPTION                   1\r
+#define configUSE_IDLE_HOOK                            1\r
+#define configUSE_TICK_HOOK                            0\r
+#define configCPU_CLOCK_HZ                             ( XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ ) /* Not actually used in this demo as the timer is set up in main() and uses the peripheral clock, not the CPU clock. */\r
+#define configTICK_RATE_HZ                             ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES                   ( 7 )\r
+#define configTOTAL_HEAP_SIZE                  ( ( size_t ) ( 64 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN                        ( 10 )\r
+#define configUSE_TRACE_FACILITY               1\r
+#define configUSE_16_BIT_TICKS                 0\r
+#define configIDLE_SHOULD_YIELD                        1\r
+#define configUSE_MUTEXES                              1\r
+#define configQUEUE_REGISTRY_SIZE              10\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES            1\r
+#define configUSE_MALLOC_FAILED_HOOK   1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES  1\r
+#define configMINIMAL_STACK_SIZE               ( ( unsigned short ) 200 )\r
+#define configINTERRUPT_STACK_SIZE             configMINIMAL_STACK_SIZE\r
+\r
+/* If configINSTALL_EXCEPTION_HANDLERS is set to 1, then the kernel will\r
+automatically install its own exception handlers before the kernel is started,\r
+if the application writer has not already caused them to be installed using the \r
+vPortExceptionsInstallHandlers() API function.  See the documentation page for\r
+this demo on the FreeRTOS.org web site for more information. */\r
+#define configINSTALL_EXCEPTION_HANDLERS 1\r
+\r
+/* configINTERRUPT_CONTROLLER_TO_USE must be set to the ID of the interrupt\r
+controller that is going to be used directly by FreeRTOS itself.  Most hardware\r
+designs will only include on interrupt controller. */\r
+#define configINTERRUPT_CONTROLLER_TO_USE XPAR_INTC_SINGLE_DEVICE_ID\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES                  0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS                               1\r
+#define configTIMER_TASK_PRIORITY              ( configMAX_PRIORITIES - 4 )\r
+#define configTIMER_QUEUE_LENGTH               10\r
+#define configTIMER_TASK_STACK_DEPTH   ( configMINIMAL_STACK_SIZE )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet               1\r
+#define INCLUDE_uxTaskPriorityGet              1\r
+#define INCLUDE_vTaskDelete                            1\r
+#define INCLUDE_vTaskCleanUpResources  0\r
+#define INCLUDE_vTaskSuspend                   1\r
+#define INCLUDE_vTaskDelayUntil                        1\r
+#define INCLUDE_vTaskDelay                             1\r
+#define INCLUDE_pcTaskNameGet                  1\r
+#define INCLUDE_pcTaskNameGet                  1\r
+\r
+#define configASSERT( x ) if( ( x ) == 0 ) { portDISABLE_INTERRUPTS(); for( ;; ); }\r
+       \r
+\r
+/* Run time stats gathering definitions.  The conditional compilation is to\r
+prevent the C syntax being included in assembly files. */\r
+#ifndef __ASSEMBLER__\r
+       unsigned long ulMainGetRunTimeCounterValue( void );\r
+       void vMainConfigureTimerForRunTimeStats( void );\r
+#endif\r
+#define configGENERATE_RUN_TIME_STATS  1\r
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vMainConfigureTimerForRunTimeStats()\r
+#define portGET_RUN_TIME_COUNTER_VALUE() ulMainGetRunTimeCounterValue()\r
+\r
+\r
+\r
+\r
+\r
+/* Networking configuration follows. */\r
+\r
+#define configLWIP_TASK_PRIORITY       ( configMAX_PRIORITIES - 4 )\r
+\r
+/* MAC address configuration. */\r
+#define configMAC_ADDR0        0x00\r
+#define configMAC_ADDR1        0x12\r
+#define configMAC_ADDR2        0x13\r
+#define configMAC_ADDR3        0x10\r
+#define configMAC_ADDR4        0x15\r
+#define configMAC_ADDR5        0x11\r
+\r
+/* IP address configuration. */\r
+#define configIP_ADDR0         192\r
+#define configIP_ADDR1         168\r
+#define configIP_ADDR2         0\r
+#define configIP_ADDR3         200\r
+\r
+/* Gateway IP address configuration. */\r
+#define configGW_IP_ADDR0      192\r
+#define configGW_IP_ADDR1      168\r
+#define configGW_IP_ADDR2      0\r
+#define configGW_IP_ADDR3      3\r
+\r
+/* Netmask configuration. */\r
+#define configNET_MASK0                255\r
+#define configNET_MASK1                255\r
+#define configNET_MASK2                255\r
+#define configNET_MASK3                0\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/ParTest.c b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/ParTest.c
new file mode 100644 (file)
index 0000000..4037181
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/ParTest.c
@@ -0,0 +1,160 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+       \r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple digital IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+\r
+/* Library includes. */\r
+#include "xgpio.h"\r
+\r
+/* The hardware design that accompanies this demo project has four LED \r
+outputs. */\r
+#define partstMAX_LED  4\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* A hardware specific constant required to use the Xilinx driver library. */\r
+static const unsigned portBASE_TYPE uxGPIOOutputChannel = 1UL;\r
+\r
+/* The current state of the output port. */\r
+static unsigned char ucGPIOState = 0U;\r
+\r
+/* Structure that hold the state of the ouptut peripheral used by this demo.\r
+This is used by the Xilinx peripheral driver API functions. */\r
+static XGpio xOutputGPIOInstance;\r
+\r
+/*\r
+ * Setup the IO for the LED outputs.\r
+ */\r
+void vParTestInitialise( void )\r
+{\r
+portBASE_TYPE xStatus;\r
+const unsigned char ucSetToOutput = 0U;\r
+\r
+       /* Initialise the GPIO for the LEDs. */\r
+       xStatus = XGpio_Initialize( &xOutputGPIOInstance, XPAR_LEDS_4BITS_DEVICE_ID );\r
+       if( xStatus == XST_SUCCESS )\r
+       {\r
+               /* All bits on this channel are going to be outputs (LEDs). */\r
+               XGpio_SetDataDirection( &xOutputGPIOInstance, uxGPIOOutputChannel, ucSetToOutput );\r
+\r
+               /* Start with all LEDs off. */\r
+               ucGPIOState = 0U;\r
+               XGpio_DiscreteWrite( &xOutputGPIOInstance, uxGPIOOutputChannel, ucGPIOState );\r
+       }\r
+       \r
+       configASSERT( xStatus == XST_SUCCESS );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned char ucLED = 1U;\r
+\r
+       /* Only attempt to set the LED if it is in range. */\r
+       if( uxLED < partstMAX_LED )\r
+       {\r
+               ucLED <<= ( unsigned char ) uxLED;\r
+\r
+               portENTER_CRITICAL();\r
+               {\r
+                       if( xValue == pdFALSE )\r
+                       {\r
+                               ucGPIOState &= ~ucLED;\r
+                       }\r
+                       else\r
+                       {\r
+                               ucGPIOState |= ucLED;\r
+                       }\r
+                       XGpio_DiscreteWrite( &xOutputGPIOInstance, uxGPIOOutputChannel, ucGPIOState );\r
+               }\r
+               portEXIT_CRITICAL();\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned char ucLED = 1U;\r
+\r
+       /* Only attempt to toggle the LED if it is in range. */\r
+       if( uxLED < partstMAX_LED )\r
+       {\r
+               ucLED <<= ( unsigned char ) uxLED;\r
+\r
+               portENTER_CRITICAL();\r
+               {\r
+                       if( ( ucGPIOState & ucLED ) != 0 )\r
+                       {\r
+                               ucGPIOState &= ~ucLED;\r
+                       }\r
+                       else\r
+                       {\r
+                               ucGPIOState |= ucLED;\r
+                       }\r
+\r
+                       XGpio_DiscreteWrite( &xOutputGPIOInstance, uxGPIOOutputChannel, ucGPIOState );\r
+               }\r
+               portEXIT_CRITICAL();\r
+       }\r
+}\r
+\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/RegisterTests.c b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/RegisterTests.c
new file mode 100644 (file)
index 0000000..1302a09
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/RegisterTests.c
@@ -0,0 +1,307 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+       \r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/*\r
+ * The register test task as described in the comments at the top of main-full.c.\r
+ */\r
+void vRegisterTest1( void *pvParameters );\r
+void vRegisterTest2( void *pvParameters );\r
+\r
+/* Variables that are incremented on each iteration of the reg test tasks -\r
+provided the tasks have not reported any errors.  The check timer inspects these\r
+variables to ensure they are still incrementing as expected.  If a variable\r
+stops incrementing then it is likely that its associate task has stalled or\r
+detected an error. */\r
+volatile unsigned long ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegisterTest1( void *pvParameters )\r
+{\r
+       /* This task uses an infinite loop that is implemented in the assembly \r
+       code.\r
+       \r
+       First fill the relevant registers with known values. */\r
+       asm volatile (  "       addi r3, r0, 3          \n\t" \\r
+                                       "       addi r4, r0, 4          \n\t" \\r
+                                       "       addi r6, r0, 6          \n\t" \\r
+                                       "       addi r7, r0, 7          \n\t" \\r
+                                       "       addi r8, r0, 8          \n\t" \\r
+                                       "       addi r9, r0, 9          \n\t" \\r
+                                       "       addi r10, r0, 10        \n\t" \\r
+                                       "       addi r11, r0, 11        \n\t" \\r
+                                       "       addi r12, r0, 12        \n\t" \\r
+                                       "       addi r16, r0, 16        \n\t" \\r
+                                       "       addi r19, r0, 19        \n\t" \\r
+                                       "       addi r20, r0, 20        \n\t" \\r
+                                       "       addi r21, r0, 21        \n\t" \\r
+                                       "       addi r22, r0, 22        \n\t" \\r
+                                       "       addi r23, r0, 23        \n\t" \\r
+                                       "       addi r24, r0, 24        \n\t" \\r
+                                       "       addi r25, r0, 25        \n\t" \\r
+                                       "       addi r26, r0, 26        \n\t" \\r
+                                       "       addi r27, r0, 27        \n\t" \\r
+                                       "       addi r28, r0, 28        \n\t" \\r
+                                       "       addi r29, r0, 29        \n\t" \\r
+                                       "       addi r30, r0, 30        \n\t" \\r
+                                       "       addi r31, r0, 31        \n\t"\r
+                               );\r
+\r
+       /* Now test the register values to ensure they contain the same value that\r
+       was written to them above.       This task will get preempted frequently so \r
+       other tasks are likely to have executed since the register values were \r
+       written.  If any register contains an unexpected value then the task will\r
+       branch to Error_Loop_1, which in turn prevents it from incrementing its\r
+       loop counter, enabling the check timer to determine that all is not as it\r
+       should be. */\r
+\r
+       asm volatile (  "Loop_Start_1:                          \n\t" \\r
+                                       "       xori r18, r3, 3                 \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r4, 4                 \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r6, 6                 \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r7, 7                 \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r8, 8                 \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r9, 9                 \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r10, 10               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r11, 11               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r12, 12               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r16, 16               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r19, 19               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r20, 20               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r21, 21               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r22, 22               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r23, 23               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r24, 24               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r25, 25               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r26, 26               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r27, 27               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r28, 28               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r29, 29               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r30, 30               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t" \\r
+                                       "       xori r18, r31, 31               \n\t" \\r
+                                       "       bnei r18, Error_Loop_1  \n\t"\r
+                                );\r
+\r
+       /* If this task has not branched to the error loop, then everything is ok,\r
+       and the check variable can be incremented to indicate that this task\r
+       is still running.  Then, brach back to the top to check the register\r
+       contents again. */\r
+       asm volatile (  "       lwi r18, r0, ulRegTest1CycleCount       \n\t" \\r
+                                       "       addik r18, r18, 1                                       \n\t" \\r
+                                       "       swi r18, r0, ulRegTest1CycleCount       \n\t" \\r
+                                       "                                                                               \n\t" \\r
+                                       "       bri Loop_Start_1 "\r
+                                );\r
+\r
+        /* The test function will branch here if it discovers an error.  This part\r
+       of the code just sits in a NULL loop, which prevents the check variable\r
+       incrementing any further to allow the check timer to recognize that this\r
+       test has failed. */\r
+       asm volatile (  "Error_Loop_1:                  \n\t" \\r
+                                       "       bri 0                           \n\t" \\r
+                                       "       nop                                     \n\t" \\r
+                                );\r
+\r
+       ( void ) pvParameters;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegisterTest2( void *pvParameters )\r
+{\r
+       /* This task uses an infinite loop that is implemented in the assembly \r
+       code.\r
+       \r
+       First fill the registers with known values. */\r
+       asm volatile (  "       addi r16, r0, 1016      \n\t" \\r
+                                       "       addi r19, r0, 1019      \n\t" \\r
+                                       "       addi r20, r0, 1020      \n\t" \\r
+                                       "       addi r21, r0, 1021      \n\t" \\r
+                                       "       addi r22, r0, 1022      \n\t" \\r
+                                       "       addi r23, r0, 1023      \n\t" \\r
+                                       "       addi r24, r0, 1024      \n\t" \\r
+                                       "       addi r25, r0, 1025      \n\t" \\r
+                                       "       addi r26, r0, 1026      \n\t" \\r
+                                       "       addi r27, r0, 1027      \n\t" \\r
+                                       "       addi r28, r0, 1028      \n\t" \\r
+                                       "       addi r29, r0, 1029      \n\t" \\r
+                                       "       addi r30, r0, 1030      \n\t" \\r
+                                       "       addi r31, r0, 1031      \n\t" \\r
+                                       "                                                       " \\r
+                                       "Loop_Start_2:                          "\r
+                               );\r
+\r
+       /* Unlike vRegisterTest1, vRegisterTest2 performs a yield.  This increases\r
+       the test coverage, but does mean volatile registers need re-loading with \r
+       their exepcted values. */\r
+       taskYIELD();\r
+\r
+       /* taskYIELD() could have changed temporaries - set them back to those\r
+       expected by the reg test task. */\r
+       asm volatile (  "       addi r3, r0, 103        \n\t" \\r
+                                       "       addi r4, r0, 104        \n\t" \\r
+                                       "       addi r6, r0, 106        \n\t" \\r
+                                       "       addi r7, r0, 107        \n\t" \\r
+                                       "       addi r8, r0, 108        \n\t" \\r
+                                       "       addi r9, r0, 109        \n\t" \\r
+                                       "       addi r10, r0, 1010      \n\t" \\r
+                                       "       addi r11, r0, 1011      \n\t" \\r
+                                       "       addi r12, r0, 1012      \n\t" \\r
+                               );\r
+\r
+\r
+       /* Now test the register values to ensure they contain the same value that\r
+       was written to them above.       This task will get preempted frequently so \r
+       other tasks are likely to have executed since the register values were \r
+       written. */\r
+       asm volatile (  "       xori r18, r3, 103               \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r4, 104               \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r6, 106               \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r7, 107               \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r8, 108               \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r9, 109               \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r10, 1010             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r11, 1011             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r12, 1012             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r16, 1016             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r19, 1019             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r20, 1020             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r21, 1021             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r22, 1022             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r23, 1023             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r24, 1024             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r25, 1025             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r26, 1026             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r27, 1027             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r28, 1028             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r29, 1029             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r30, 1030             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t" \\r
+                                       "       xori r18, r31, 1031             \n\t" \\r
+                                       "       bnei r18, Error_Loop_2  \n\t"\r
+                                );\r
+\r
+       /* If this task has not branched to the error loop, then everything is ok,\r
+       and the check variable should be incremented to indicate that this task\r
+       is still running.  Then, brach back to the top to check the registers\r
+       again. */\r
+       asm volatile (  "       lwi r18, r0, ulRegTest2CycleCount       \n\t" \\r
+                                       "       addik r18, r18, 1                                       \n\t" \\r
+                                       "       swi r18, r0, ulRegTest2CycleCount       \n\t" \\r
+                                       "                                                                               \n\t" \\r
+                                       "       bri Loop_Start_2 "\r
+                                );\r
+\r
+        /* The test function will branch here if it discovers an error.  This part\r
+       of the code just sits in a NULL loop, which prevents the check variable\r
+       incrementing any further to allow the check timer to recognize that this\r
+       test has failed. */\r
+       asm volatile (  "Error_Loop_2:                  \n\t" \\r
+                                       "       bri 0                           \n\t" \\r
+                                       "       nop                                     \n\t" \\r
+                                );\r
+\r
+       ( void ) pvParameters;\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/fs.c b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/fs.c
new file mode 100644 (file)
index 0000000..993fffc
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/fs.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "fs.h"
+#include "fsdata.h"
+#include <string.h>
+
+/** Set this to 1 to include "fsdata_custom.c" instead of "fsdata.c" for the
+ * file system (to prevent changing the file included in CVS) */
+#ifndef HTTPD_USE_CUSTUM_FSDATA
+#define HTTPD_USE_CUSTUM_FSDATA 0
+#endif
+
+#if HTTPD_USE_CUSTUM_FSDATA
+#include "fsdata_custom.c"
+#else /* HTTPD_USE_CUSTUM_FSDATA */
+#include "fsdata.c"
+#endif /* HTTPD_USE_CUSTUM_FSDATA */
+
+/*-----------------------------------------------------------------------------------*/
+/* Define the number of open files that we can support. */
+#ifndef LWIP_MAX_OPEN_FILES
+#define LWIP_MAX_OPEN_FILES     10
+#endif
+
+/* Define the file system memory allocation structure. */
+struct fs_table {
+  struct fs_file file;
+  u8_t inuse;
+};
+
+/* Allocate file system memory */
+struct fs_table fs_memory[LWIP_MAX_OPEN_FILES];
+
+#if LWIP_HTTPD_CUSTOM_FILES
+int fs_open_custom(struct fs_file *file, const char *name);
+void fs_close_custom(struct fs_file *file);
+#endif /* LWIP_HTTPD_CUSTOM_FILES */
+
+/*-----------------------------------------------------------------------------------*/
+static struct fs_file *
+fs_malloc(void)
+{
+  int i;
+  for(i = 0; i < LWIP_MAX_OPEN_FILES; i++) {
+    if(fs_memory[i].inuse == 0) {
+      fs_memory[i].inuse = 1;
+      return(&fs_memory[i].file);
+    }
+  }
+  return(NULL);
+}
+
+/*-----------------------------------------------------------------------------------*/
+static void
+fs_free(struct fs_file *file)
+{
+  int i;
+  for(i = 0; i < LWIP_MAX_OPEN_FILES; i++) {
+    if(&fs_memory[i].file == file) {
+      fs_memory[i].inuse = 0;
+      break;
+    }
+  }
+  return;
+}
+
+/*-----------------------------------------------------------------------------------*/
+struct fs_file *
+fs_open(const char *name)
+{
+  struct fs_file *file;
+  const struct fsdata_file *f;
+
+  file = fs_malloc();
+  if(file == NULL) {
+    return NULL;
+  }
+
+#if LWIP_HTTPD_CUSTOM_FILES
+  if(fs_open_custom(file, name)) {
+    file->is_custom_file = 1;
+    return file;
+  }
+  file->is_custom_file = 0;
+#endif /* LWIP_HTTPD_CUSTOM_FILES */
+
+  for(f = FS_ROOT; f != NULL; f = f->next) {
+    if (!strcmp(name, (char *)f->name)) {
+      file->data = (const char *)f->data;
+      file->len = f->len;
+      file->index = f->len;
+      file->pextension = NULL;
+      file->http_header_included = f->http_header_included;
+#if HTTPD_PRECALCULATED_CHECKSUM
+      file->chksum_count = f->chksum_count;
+      file->chksum = f->chksum;
+#endif /* HTTPD_PRECALCULATED_CHECKSUM */
+#if LWIP_HTTPD_FILE_STATE
+      file->state = fs_state_init(file, name);
+#endif /* #if LWIP_HTTPD_FILE_STATE */
+      return file;
+    }
+  }
+  fs_free(file);
+  return NULL;
+}
+
+/*-----------------------------------------------------------------------------------*/
+void
+fs_close(struct fs_file *file)
+{
+#if LWIP_HTTPD_CUSTOM_FILES
+  if (file->is_custom_file) {
+    fs_close_custom(file);
+  }
+#endif /* LWIP_HTTPD_CUSTOM_FILES */
+#if LWIP_HTTPD_FILE_STATE
+  fs_state_free(file, file->state);
+#endif /* #if LWIP_HTTPD_FILE_STATE */
+  fs_free(file);
+}
+/*-----------------------------------------------------------------------------------*/
+int
+fs_read(struct fs_file *file, char *buffer, int count)
+{
+  int read;
+
+  if(file->index == file->len) {
+    return -1;
+  }
+
+  read = file->len - file->index;
+  if(read > count) {
+    read = count;
+  }
+
+  MEMCPY(buffer, (file->data + file->index), read);
+  file->index += read;
+
+  return(read);
+}
+/*-----------------------------------------------------------------------------------*/
+int fs_bytes_left(struct fs_file *file)
+{
+  return file->len - file->index;
+}

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/fs.h b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/fs.h
new file mode 100644 (file)
index 0000000..cd76759
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/fs.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __FS_H__
+#define __FS_H__
+
+#include "lwip/opt.h"
+
+/** Set this to 1 and provide the functions:
+ * - "int fs_open_custom(struct fs_file *file, const char *name)"
+ *    Called first for every opened file to allow opening files
+ *    that are not included in fsdata(_custom).c
+ * - "void fs_close_custom(struct fs_file *file)"
+ *    Called to free resources allocated by fs_open_custom().
+ */
+#ifndef LWIP_HTTPD_CUSTOM_FILES
+#define LWIP_HTTPD_CUSTOM_FILES       0
+#endif
+
+/** Set this to 1 to include an application state argument per file
+ * that is opened. This allows to keep a state per connection/file.
+ */
+#ifndef LWIP_HTTPD_FILE_STATE
+#define LWIP_HTTPD_FILE_STATE         0
+#endif
+
+/** HTTPD_PRECALCULATED_CHECKSUM==1: include precompiled checksums for
+ * predefined (MSS-sized) chunks of the files to prevent having to calculate
+ * the checksums at runtime. */
+#ifndef HTTPD_PRECALCULATED_CHECKSUM
+#define HTTPD_PRECALCULATED_CHECKSUM  0
+#endif
+
+#if HTTPD_PRECALCULATED_CHECKSUM
+struct fsdata_chksum {
+  u32_t offset;
+  u16_t chksum;
+  u16_t len;
+};
+#endif /* HTTPD_PRECALCULATED_CHECKSUM */
+
+struct fs_file {
+  const char *data;
+  int len;
+  int index;
+  void *pextension;
+#if HTTPD_PRECALCULATED_CHECKSUM
+  const struct fsdata_chksum *chksum;
+  u16_t chksum_count;
+#endif /* HTTPD_PRECALCULATED_CHECKSUM */
+  u8_t http_header_included;
+#if LWIP_HTTPD_CUSTOM_FILES
+  u8_t is_custom_file;
+#endif /* LWIP_HTTPD_CUSTOM_FILES */
+#if LWIP_HTTPD_FILE_STATE
+  void *state;
+#endif /* LWIP_HTTPD_FILE_STATE */
+};
+
+struct fs_file *fs_open(const char *name);
+void fs_close(struct fs_file *file);
+int fs_read(struct fs_file *file, char *buffer, int count);
+int fs_bytes_left(struct fs_file *file);
+
+#if LWIP_HTTPD_FILE_STATE
+/** This user-defined function is called when a file is opened. */
+void *fs_state_init(struct fs_file *file, const char *name);
+/** This user-defined function is called when a file is closed. */
+void fs_state_free(struct fs_file *file, void *state);
+#endif /* #if LWIP_HTTPD_FILE_STATE */
+
+#endif /* __FS_H__ */

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/fsdata.c b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/fsdata.c
new file mode 100644 (file)
index 0000000..f2ddfd9
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/fsdata.c
@@ -0,0 +1,2068 @@
+#include "fs.h"\r
+#include "lwip/def.h"\r
+#include "fsdata.h"\r
+\r
+\r
+#define file_NULL (struct fsdata_file *) NULL\r
+\r
+\r
+static const unsigned int dummy_align__404_html = 0;\r
+static const unsigned char data__404_html[] = {\r
+/* /404.html (10 chars) */\r
+0x2f,0x34,0x30,0x34,0x2e,0x68,0x74,0x6d,0x6c,0x00,0x00,0x00,\r
+\r
+/* HTTP header */\r
+/* "HTTP/1.0 404 File not found\r
+" (29 bytes) */\r
+0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x34,0x30,0x34,0x20,0x46,0x69,0x6c,\r
+0x65,0x20,0x6e,0x6f,0x74,0x20,0x66,0x6f,0x75,0x6e,0x64,0x0d,0x0a,\r
+/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip)\r
+" (63 bytes) */\r
+0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33,\r
+0x2e,0x31,0x20,0x28,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x73,0x61,0x76,0x61,0x6e,\r
+0x6e,0x61,0x68,0x2e,0x6e,0x6f,0x6e,0x67,0x6e,0x75,0x2e,0x6f,0x72,0x67,0x2f,0x70,\r
+0x72,0x6f,0x6a,0x65,0x63,0x74,0x73,0x2f,0x6c,0x77,0x69,0x70,0x29,0x0d,0x0a,\r
+/* "Content-type: text/html\r
+\r
+" (27 bytes) */\r
+0x43,0x6f,0x6e,0x74,0x65,0x6e,0x74,0x2d,0x74,0x79,0x70,0x65,0x3a,0x20,0x74,0x65,\r
+0x78,0x74,0x2f,0x68,0x74,0x6d,0x6c,0x0d,0x0a,0x0d,0x0a,\r
+/* raw file data (544 bytes) */\r
+0x3c,0x68,0x74,0x6d,0x6c,0x3e,0x0a,0x3c,0x68,0x65,0x61,0x64,0x3e,0x3c,0x74,0x69,\r
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+};\r
+\r
+static const unsigned int dummy_align__index_shtml = 1;\r
+static const unsigned char data__index_shtml[] = {\r
+/* /index.shtml (13 chars) */\r
+0x2f,0x69,0x6e,0x64,0x65,0x78,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x00,0x00,0x00,0x00,\r
+\r
+/* HTTP header */\r
+/* "HTTP/1.0 200 OK\r
+" (17 bytes) */\r
+0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x32,0x30,0x30,0x20,0x4f,0x4b,0x0d,\r
+0x0a,\r
+/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip)\r
+" (63 bytes) */\r
+0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33,\r
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+/* "Content-type: text/html\r
+Expires: Fri, 10 Apr 2008 14:00:00 GMT\r
+Pragma: no-cache\r
+\r
+" (85 bytes) */\r
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+0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,\r
+0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,\r
+0x2a,0x2a,0x2a,0x2a,0x3c,0x62,0x72,0x3e,0x0d,0x0a,0x3c,0x21,0x2d,0x2d,0x23,0x72,\r
+0x74,0x6f,0x73,0x5f,0x73,0x74,0x61,0x74,0x73,0x2d,0x2d,0x3e,0x0d,0x0a,0x3c,0x2f,\r
+0x70,0x72,0x65,0x3e,0x3c,0x2f,0x66,0x6f,0x6e,0x74,0x3e,0x0d,0x0a,0x3c,0x2f,0x66,\r
+0x6f,0x6e,0x74,0x3e,0x0d,0x0a,0x3c,0x2f,0x62,0x6f,0x64,0x79,0x3e,0x0d,0x0a,0x3c,\r
+0x2f,0x68,0x74,0x6d,0x6c,0x3e,0x0d,0x0a,0x0d,0x0a,};\r
+\r
+static const unsigned int dummy_align__logo_jpg = 2;\r
+static const unsigned char data__logo_jpg[] = {\r
+/* /logo.jpg (10 chars) */\r
+0x2f,0x6c,0x6f,0x67,0x6f,0x2e,0x6a,0x70,0x67,0x00,0x00,0x00,\r
+\r
+/* HTTP header */\r
+/* "HTTP/1.0 200 OK\r
+" (17 bytes) */\r
+0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x32,0x30,0x30,0x20,0x4f,0x4b,0x0d,\r
+0x0a,\r
+/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip)\r
+" (63 bytes) */\r
+0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33,\r
+0x2e,0x31,0x20,0x28,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x73,0x61,0x76,0x61,0x6e,\r
+0x6e,0x61,0x68,0x2e,0x6e,0x6f,0x6e,0x67,0x6e,0x75,0x2e,0x6f,0x72,0x67,0x2f,0x70,\r
+0x72,0x6f,0x6a,0x65,0x63,0x74,0x73,0x2f,0x6c,0x77,0x69,0x70,0x29,0x0d,0x0a,\r
+/* "Content-type: image/jpeg\r
+\r
+" (28 bytes) */\r
+0x43,0x6f,0x6e,0x74,0x65,0x6e,0x74,0x2d,0x74,0x79,0x70,0x65,0x3a,0x20,0x69,0x6d,\r
+0x61,0x67,0x65,0x2f,0x6a,0x70,0x65,0x67,0x0d,0x0a,0x0d,0x0a,\r
+/* raw file data (28602 bytes) */\r
+0xff,0xd8,0xff,0xe0,0x00,0x10,0x4a,0x46,0x49,0x46,0x00,0x01,0x01,0x00,0x00,0x01,\r
+0x00,0x01,0x00,0x00,0xff,0xdb,0x00,0x43,0x00,0x03,0x02,0x02,0x03,0x02,0x02,0x03,\r
+0x03,0x03,0x03,0x04,0x03,0x03,0x04,0x05,0x08,0x05,0x05,0x04,0x04,0x05,0x0a,0x07,\r
+0x07,0x06,0x08,0x0c,0x0a,0x0c,0x0c,0x0b,0x0a,0x0b,0x0b,0x0d,0x0e,0x12,0x10,0x0d,\r
+0x0e,0x11,0x0e,0x0b,0x0b,0x10,0x16,0x10,0x11,0x13,0x14,0x15,0x15,0x15,0x0c,0x0f,\r
+0x17,0x18,0x16,0x14,0x18,0x12,0x14,0x15,0x14,0xff,0xdb,0x00,0x43,0x01,0x03,0x04,\r
+0x04,0x05,0x04,0x05,0x09,0x05,0x05,0x09,0x14,0x0d,0x0b,0x0d,0x14,0x14,0x14,0x14,\r
+0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,\r
+0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,\r
+0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0xff,0xc0,\r
+0x00,0x11,0x08,0x00,0xea,0x02,0x71,0x03,0x01,0x22,0x00,0x02,0x11,0x01,0x03,0x11,\r
+0x01,0xff,0xc4,0x00,0x1f,0x00,0x00,0x01,0x05,0x01,0x01,0x01,0x01,0x01,0x01,0x00,\r
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+0x31,0x41,0x06,0x13,0x51,0x61,0x07,0x22,0x71,0x14,0x32,0x81,0x91,0xa1,0x08,0x23,\r
+0x42,0xb1,0xc1,0x15,0x52,0xd1,0xf0,0x24,0x33,0x62,0x72,0x82,0x09,0x0a,0x16,0x17,\r
+0x18,0x19,0x1a,0x25,0x26,0x27,0x28,0x29,0x2a,0x34,0x35,0x36,0x37,0x38,0x39,0x3a,\r
+0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4a,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5a,\r
+0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6a,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7a,\r
+0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8a,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,\r
+0x9a,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7,0xa8,0xa9,0xaa,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7,\r
+0xb8,0xb9,0xba,0xc2,0xc3,0xc4,0xc5,0xc6,0xc7,0xc8,0xc9,0xca,0xd2,0xd3,0xd4,0xd5,\r
+0xd6,0xd7,0xd8,0xd9,0xda,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xf1,\r
+0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xff,0xc4,0x00,0x1f,0x01,0x00,0x03,\r
+0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,\r
+0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0xff,0xc4,0x00,0xb5,0x11,0x00,\r
+0x02,0x01,0x02,0x04,0x04,0x03,0x04,0x07,0x05,0x04,0x04,0x00,0x01,0x02,0x77,0x00,\r
+0x01,0x02,0x03,0x11,0x04,0x05,0x21,0x31,0x06,0x12,0x41,0x51,0x07,0x61,0x71,0x13,\r
+0x22,0x32,0x81,0x08,0x14,0x42,0x91,0xa1,0xb1,0xc1,0x09,0x23,0x33,0x52,0xf0,0x15,\r
+0x62,0x72,0xd1,0x0a,0x16,0x24,0x34,0xe1,0x25,0xf1,0x17,0x18,0x19,0x1a,0x26,0x27,\r
+0x28,0x29,0x2a,0x35,0x36,0x37,0x38,0x39,0x3a,0x43,0x44,0x45,0x46,0x47,0x48,0x49,\r
+0x4a,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5a,0x63,0x64,0x65,0x66,0x67,0x68,0x69,\r
+0x6a,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7a,0x82,0x83,0x84,0x85,0x86,0x87,0x88,\r
+0x89,0x8a,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9a,0xa2,0xa3,0xa4,0xa5,0xa6,\r
+0xa7,0xa8,0xa9,0xaa,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7,0xb8,0xb9,0xba,0xc2,0xc3,0xc4,\r
+0xc5,0xc6,0xc7,0xc8,0xc9,0xca,0xd2,0xd3,0xd4,0xd5,0xd6,0xd7,0xd8,0xd9,0xda,0xe2,\r
+0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,\r
+0xfa,0xff,0xda,0x00,0x0c,0x03,0x01,0x00,0x02,0x11,0x03,0x11,0x00,0x3f,0x00,0xfd,\r
+0x53,0xa2,0x8a,0x28,0x00,0xa2,0x8a,0x28,0x00,0xa2,0x8a,0x28,0x00,0xa4,0x34,0x8e,\r
+0x70,0x09,0xaf,0x0b,0xf1,0xbf,0xc6,0x4b,0x8f,0x13,0x78,0xc2,0xdb,0xc1,0x7e,0x0f,\r
+0xb8,0x2b,0x24,0x93,0x08,0xae,0xf5,0x48,0x88,0x3b,0x47,0xf1,0x2c,0x7f,0x4e,0x72,\r
+0xdf,0x97,0xad,0x72,0x62,0x71,0x54,0xf0,0xb1,0xe6,0x9e,0xef,0x44,0xba,0xb6,0x73,\r
+0x57,0xc4,0x43,0x0e,0x93,0x9e,0xef,0x44,0xba,0xb6,0x77,0xbe,0x3b,0xf8,0xb9,0xa1,\r
+0xf8,0x16,0x39,0x23,0x9d,0xe4,0xd4,0x35,0x05,0x1c,0x58,0x59,0x2e,0xf9,0x3d,0xb7,\r
+0x76,0x51,0xf5,0xfc,0x8d,0x78,0x07,0x8a,0xff,0x00,0x69,0x3f,0x1b,0x6a,0xb3,0x3a,\r
+0x69,0x3a,0x7f,0xf6,0x2d,0xb7,0xf0,0x81,0x09,0x96,0x5f,0xc5,0x98,0x63,0xf2,0x15,\r
+0xf4,0xde,0x83,0xe0,0xdd,0x27,0xc3,0xf6,0x62,0x0b,0x6b,0x38,0xc9,0x3f,0x33,0xcb,\r
+0x20,0xde,0xf2,0x37,0x76,0x66,0x3c,0x92,0x6b,0x40,0xe9,0x16,0x47,0xad,0x9c,0x1f,\r
+0xf7,0xec,0x57,0x9d,0x88,0xc2,0xe3,0x31,0x2b,0xf8,0xbc,0x8b,0xb2,0x5f,0xad,0xce,\r
+0x3c,0x46,0x1b,0x13,0x88,0x56,0x8d,0x5e,0x45,0xe4,0xbf,0x53,0xe0,0x8d,0x4f,0xc6,\r
+0xfe,0x33,0xd5,0x18,0x9b,0xcd,0x5f,0x56,0x90,0x93,0x9c,0x19,0xa4,0x0b,0xf9,0x0e,\r
+0x2b,0x35,0x75,0xff,0x00,0x10,0xc7,0x9c,0x6a,0x3a,0x82,0xfa,0xfe,0xfa,0x41,0xfd,\r
+0x6b,0xf4,0x19,0xb4,0x2d,0x39,0xba,0xd8,0x5b,0x7f,0xdf,0xa1,0xfe,0x15,0x19,0xf0,\r
+0xce,0x94,0xff,0x00,0x7b,0x4d,0xb5,0x3f,0xf6,0xc5,0x7f,0xc2,0xbc,0x79,0x64,0x15,\r
+0xa4,0xef,0xed,0xaf,0xf2,0x7f,0xe6,0x78,0x72,0xc8,0x6a,0x49,0xdd,0xd7,0x7f,0xd7,\r
+0xcc,0xf8,0x0d,0x3c,0x5f,0xe2,0x68,0x94,0x05,0xd6,0x35,0x45,0x03,0xa0,0x17,0x32,\r
+0x0f,0xeb,0x53,0x27,0x8f,0xbc,0x59,0x11,0x25,0x75,0xfd,0x59,0x33,0xe9,0x77,0x28,\r
+0xfe,0xb5,0xf7,0x8b,0x78,0x3b,0x44,0x7e,0xba,0x4d,0x99,0xff,0x00,0xb6,0x2b,0x51,\r
+0x37,0x81,0x7c,0x3c,0xf9,0xce,0x8d,0x66,0x73,0xff,0x00,0x4c,0x56,0xa5,0x64,0x58,\r
+0x85,0xb5,0x6f,0xcc,0x9f,0xec,0x2a,0xeb,0x6a,0xef,0xf1,0xff,0x00,0x33,0xe1,0x6f,\r
+0xf8,0x59,0x3e,0x2f,0x5f,0xf9,0x98,0xb5,0x7f,0xfc,0x0c,0x93,0xfc,0x69,0xeb,0xf1,\r
+0x4f,0xc6,0x51,0x9c,0xaf,0x89,0x35,0x5c,0xfb,0xdd,0x3f,0xf8,0xd7,0xdc,0x0d,0xf0,\r
+0xf3,0xc3,0x6f,0xd7,0x44,0xb2,0x3f,0xf6,0xc8,0x54,0x4f,0xf0,0xcb,0xc2,0xaf,0xf7,\r
+0xb4,0x2b,0x23,0xff,0x00,0x6c,0x85,0x2f,0xec,0x4c,0x5f,0xfc,0xfe,0xfc,0xc5,0xfd,\r
+0x89,0x8a,0x5b,0x57,0x7f,0x89,0xf1,0x54,0x7f,0x17,0xfc,0x6b,0x1f,0xfc,0xcc,0x9a,\r
+0x99,0xfa,0xdc,0x35,0x58,0x8b,0xe3,0x87,0x8e,0xe1,0x6c,0xaf,0x89,0x2f,0x73,0xd3,\r
+0xe6,0x21,0x87,0xe4,0x45,0x7d,0x8e,0xff,0x00,0x09,0x7c,0x20,0xfd,0x74,0x0b,0x3f,\r
+0xc2,0x3c,0x54,0x2f,0xf0,0x6b,0xc1,0xaf,0xd7,0x41,0xb5,0x1f,0x45,0xa4,0xb2,0x7c,\r
+0x72,0xda,0xb7,0xe2,0xc7,0xfd,0x8f,0x8d,0x5b,0x62,0x1f,0xe2,0x7c,0x8a,0x9f,0x1f,\r
+0xbc,0x7e,0x83,0x1f,0xf0,0x91,0x5c,0x7d,0x4c,0x71,0x9f,0xfd,0x96,0xa6,0x1f,0xb4,\r
+0x37,0x8f,0xc7,0xfc,0xcc,0x12,0xfe,0x30,0x45,0xff,0x00,0xc4,0x57,0xd5,0xaf,0xf0,\r
+0x43,0xc1,0x4e,0x0f,0xfc,0x48,0xa0,0x1f,0x4a,0x89,0xbe,0x03,0xf8,0x21,0xf3,0xff,\r
+0x00,0x12,0x48,0x86,0x7d,0x09,0xa7,0xfd,0x95,0x98,0xad,0xab,0x7e,0x2c,0x3f,0xb2,\r
+0xb3,0x15,0xb6,0x21,0xfd,0xec,0xf9,0x69,0x7f,0x68,0xaf,0x1f,0x8f,0xf9,0x8f,0x39,\r
+0xfa,0xdb,0xc5,0xff,0x00,0xc4,0xd4,0x89,0xfb,0x48,0x78,0xf9,0x08,0x3f,0xdb,0x59,\r
+0xc7,0xad,0xb4,0x47,0xff,0x00,0x65,0xaf,0xa6,0x9f,0xf6,0x7d,0xf0,0x33,0x8e,0x74,\r
+0x75,0x1e,0xe1,0x8d,0x42,0xff,0x00,0xb3,0x9f,0x81,0x9c,0x7f,0xc8,0x2d,0x97,0xe9,\r
+0x21,0xa3,0xfb,0x33,0x34,0x5b,0x56,0xff,0x00,0xc9,0x98,0xbf,0xb3,0x33,0x35,0xb5,\r
+0x7f,0xc5,0x9f,0x39,0xc7,0xfb,0x4d,0xf8,0xf1,0x17,0x07,0x52,0x85,0xcf,0xab,0x5a,\r
+0xa6,0x7f,0x95,0x58,0x4f,0xda,0x9b,0xc7,0x49,0x8f,0xf4,0x9b,0x36,0xc7,0xad,0xaa,\r
+0xf3,0xfa,0xd7,0xbe,0xbf,0xec,0xd5,0xe0,0x86,0xc9,0x16,0x32,0xaf,0xd2,0x43,0x50,\r
+0x3f,0xec,0xc5,0xe0,0xa6,0xe9,0x6f,0x3a,0xff,0x00,0xdb,0x4a,0x5f,0xd9,0xf9,0xb2,\r
+0xda,0xaf,0xfe,0x4c,0xc3,0xfb,0x3f,0x36,0x5b,0x57,0xfc,0x59,0xe2,0x0b,0xfb,0x57,\r
+0x78,0xdd,0x7a,0x9d,0x39,0xbe,0xb6,0xc7,0xfa,0x35,0x3d,0x7f,0x6b,0x0f,0x1a,0x82,\r
+0x32,0x9a,0x61,0xff,0x00,0xb7,0x66,0xff,0x00,0xe2,0xeb,0xd9,0xdb,0xf6,0x5a,0xf0,\r
+0x63,0x0e,0x12,0xe5,0x7f,0xed,0xa5,0x42,0xff,0x00,0xb2,0xa7,0x83,0xcf,0x47,0xbb,\r
+0x5f,0xfb,0x69,0x43,0xc1,0xe7,0x0b,0x6a,0x9f,0xf9,0x30,0x7d,0x4b,0x37,0x5b,0x56,\r
+0xfc,0x4f,0x23,0x5f,0xda,0xd7,0xc6,0x43,0xad,0xbe,0x96,0xdf,0xf6,0xc1,0xff,0x00,\r
+0xf8,0xba,0x91,0x3f,0x6b,0x8f,0x16,0x82,0x37,0x59,0x69,0x6d,0xeb,0xfb,0xa7,0xff,\r
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+0x1f,0xfd,0xe5,0x06,0xb3,0x2f,0x3c,0x37,0xa4,0x5d,0xff,0x00,0xaf,0xd2,0xec,0xa6,\r
+0xff,0x00,0xae,0x96,0xe8,0xdf,0xcc,0x57,0x34,0xf0,0x72,0x8f,0xdb,0xfc,0x3f,0xe0,\r
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+0x09,0xaf,0xd4,0x6f,0x14,0x78,0x37,0x40,0x44,0x98,0xae,0x87,0xa6,0x83,0x8e,0xa2,\r
+0xd2,0x3f,0xf0,0xac,0x0f,0x06,0xf8,0x4b,0x43,0x9e,0xf1,0xd6,0x5d,0x1b,0x4f,0x91,\r
+0x72,0x38,0x7b,0x54,0x23,0xf9,0x57,0x1c,0x63,0x25,0x2b,0x2b,0x7d,0xc7,0x8f,0x2c,\r
+0x97,0x0c,0xa5,0xca,0x92,0xfb,0x8f,0xcc,0x9b,0x2f,0x86,0x9e,0x2d,0xf1,0x2d,0xd8,\r
+0xb7,0xb3,0xd3,0xef,0x75,0x19,0xd8,0xf1,0x15,0xbc,0x4c,0xed,0xcf,0xb0,0x15,0xf4,\r
+0x27,0xc2,0x4f,0xf8,0x27,0x6f,0x8a,0x7c,0x4d,0x3c,0x37,0x7e,0x31,0xb9,0x5f,0x0d,\r
+0xe9,0x99,0x05,0xa0,0x52,0x24,0xba,0x71,0xd7,0x85,0x1f,0x2a,0xfd,0x58,0xe4,0x7f,\r
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+0x12,0x08,0xd5,0x00,0xfc,0x00,0xab,0x8b,0x5e,0xfd,0x1c,0x3d,0xd2,0x94,0xdd,0xcf,\r
+0xa2,0xc0,0xf0,0xed,0x18,0x5a,0x75,0x26,0xe4,0xbb,0x5a,0xc8,0xe2,0x7e,0x16,0xfc,\r
+0x1b,0xf0,0xa7,0xc1,0xcd,0x0c,0x69,0x9e,0x18,0xd2,0xe3,0xb3,0x46,0x03,0xce,0xb8,\r
+0x6f,0x9a,0x79,0xc8,0xef,0x23,0xf5,0x3f,0x4e,0x83,0xb0,0x15,0xdb,0x8e,0x28,0x1d,\r
+0x29,0x6b,0xd0,0x49,0x25,0x64,0x7d,0x8c,0x29,0xc6,0x9c,0x54,0x20,0xac,0x90,0x51,\r
+0x45,0x14,0xcd,0x02,0x8a,0x28,0xa0,0x0f,0xff,0xd9,};\r
+\r
+static const unsigned int dummy_align__runtime_shtml = 3;\r
+static const unsigned char data__runtime_shtml[] = {\r
+/* /runtime.shtml (15 chars) */\r
+0x2f,0x72,0x75,0x6e,0x74,0x69,0x6d,0x65,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x00,0x00,\r
+\r
+/* HTTP header */\r
+/* "HTTP/1.0 200 OK\r
+" (17 bytes) */\r
+0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x32,0x30,0x30,0x20,0x4f,0x4b,0x0d,\r
+0x0a,\r
+/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip)\r
+" (63 bytes) */\r
+0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33,\r
+0x2e,0x31,0x20,0x28,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x73,0x61,0x76,0x61,0x6e,\r
+0x6e,0x61,0x68,0x2e,0x6e,0x6f,0x6e,0x67,0x6e,0x75,0x2e,0x6f,0x72,0x67,0x2f,0x70,\r
+0x72,0x6f,0x6a,0x65,0x63,0x74,0x73,0x2f,0x6c,0x77,0x69,0x70,0x29,0x0d,0x0a,\r
+/* "Content-type: text/html\r
+Expires: Fri, 10 Apr 2008 14:00:00 GMT\r
+Pragma: no-cache\r
+\r
+" (85 bytes) */\r
+0x43,0x6f,0x6e,0x74,0x65,0x6e,0x74,0x2d,0x74,0x79,0x70,0x65,0x3a,0x20,0x74,0x65,\r
+0x78,0x74,0x2f,0x68,0x74,0x6d,0x6c,0x0d,0x0a,0x45,0x78,0x70,0x69,0x72,0x65,0x73,\r
+0x3a,0x20,0x46,0x72,0x69,0x2c,0x20,0x31,0x30,0x20,0x41,0x70,0x72,0x20,0x32,0x30,\r
+0x30,0x38,0x20,0x31,0x34,0x3a,0x30,0x30,0x3a,0x30,0x30,0x20,0x47,0x4d,0x54,0x0d,\r
+0x0a,0x50,0x72,0x61,0x67,0x6d,0x61,0x3a,0x20,0x6e,0x6f,0x2d,0x63,0x61,0x63,0x68,\r
+0x65,0x0d,0x0a,0x0d,0x0a,\r
+/* raw file data (758 bytes) */\r
+0x3c,0x21,0x44,0x4f,0x43,0x54,0x59,0x50,0x45,0x20,0x48,0x54,0x4d,0x4c,0x20,0x50,\r
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+0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,\r
+0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,\r
+0x3c,0x62,0x72,0x3e,0x0d,0x0a,0x3c,0x21,0x2d,0x2d,0x23,0x72,0x75,0x6e,0x5f,0x73,\r
+0x74,0x61,0x74,0x73,0x2d,0x2d,0x3e,0x0d,0x0d,0x0a,0x3c,0x2f,0x70,0x72,0x65,0x3e,\r
+0x3c,0x2f,0x66,0x6f,0x6e,0x74,0x3e,0x0d,0x0a,0x3c,0x2f,0x66,0x6f,0x6e,0x74,0x3e,\r
+0x0d,0x0a,0x3c,0x2f,0x62,0x6f,0x64,0x79,0x3e,0x0d,0x0a,0x3c,0x2f,0x68,0x74,0x6d,\r
+0x6c,0x3e,0x0d,0x0a,0x0d,0x0a,};\r
+\r
+\r
+\r
+const struct fsdata_file file__404_html[] = { {\r
+file_NULL,\r
+data__404_html,\r
+data__404_html + 12,\r
+sizeof(data__404_html) - 12,\r
+1,\r
+}};\r
+\r
+const struct fsdata_file file__index_shtml[] = { {\r
+file__404_html,\r
+data__index_shtml,\r
+data__index_shtml + 16,\r
+sizeof(data__index_shtml) - 16,\r
+1,\r
+}};\r
+\r
+const struct fsdata_file file__logo_jpg[] = { {\r
+file__index_shtml,\r
+data__logo_jpg,\r
+data__logo_jpg + 12,\r
+sizeof(data__logo_jpg) - 12,\r
+1,\r
+}};\r
+\r
+const struct fsdata_file file__runtime_shtml[] = { {\r
+file__logo_jpg,\r
+data__runtime_shtml,\r
+data__runtime_shtml + 16,\r
+sizeof(data__runtime_shtml) - 16,\r
+1,\r
+}};\r
+\r
+#define FS_ROOT file__runtime_shtml\r
+#define FS_NUMFILES 4\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/fsdata.h b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/fsdata.h
new file mode 100644 (file)
index 0000000..6f6c557
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/fsdata.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __FSDATA_H__
+#define __FSDATA_H__
+
+#include "lwip/opt.h"
+#include "fs.h"
+
+struct fsdata_file {
+  const struct fsdata_file *next;
+  const unsigned char *name;
+  const unsigned char *data;
+  int len;
+  u8_t http_header_included;
+#if HTTPD_PRECALCULATED_CHECKSUM
+  u16_t chksum_count;
+  const struct fsdata_chksum *chksum;
+#endif /* HTTPD_PRECALCULATED_CHECKSUM */
+};
+
+#endif /* __FSDATA_H__ */

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/httpd.c b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/httpd.c
new file mode 100644 (file)
index 0000000..89676df
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/httpd.c
@@ -0,0 +1,2185 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+/* This httpd supports for a
+ * rudimentary server-side-include facility which will replace tags of the form
+ * <!--#tag--> in any file whose extension is .shtml, .shtm or .ssi with
+ * strings provided by an include handler whose pointer is provided to the
+ * module via function http_set_ssi_handler().
+ * Additionally, a simple common
+ * gateway interface (CGI) handling mechanism has been added to allow clients
+ * to hook functions to particular request URIs.
+ *
+ * To enable SSI support, define label LWIP_HTTPD_SSI in lwipopts.h.
+ * To enable CGI support, define label LWIP_HTTPD_CGI in lwipopts.h.
+ *
+ * By default, the server assumes that HTTP headers are already present in
+ * each file stored in the file system.  By defining LWIP_HTTPD_DYNAMIC_HEADERS in
+ * lwipopts.h, this behavior can be changed such that the server inserts the
+ * headers automatically based on the extension of the file being served.  If
+ * this mode is used, be careful to ensure that the file system image used
+ * does not already contain the header information.
+ *
+ * File system images without headers can be created using the makefsfile
+ * tool with the -h command line option.
+ *
+ *
+ * Notes about valid SSI tags
+ * --------------------------
+ *
+ * The following assumptions are made about tags used in SSI markers:
+ *
+ * 1. No tag may contain '-' or whitespace characters within the tag name.
+ * 2. Whitespace is allowed between the tag leadin "<!--#" and the start of
+ *    the tag name and between the tag name and the leadout string "-->".
+ * 3. The maximum tag name length is LWIP_HTTPD_MAX_TAG_NAME_LEN, currently 8 characters.
+ *
+ * Notes on CGI usage
+ * ------------------
+ *
+ * The simple CGI support offered here works with GET method requests only
+ * and can handle up to 16 parameters encoded into the URI. The handler
+ * function may not write directly to the HTTP output but must return a
+ * filename that the HTTP server will send to the browser as a response to
+ * the incoming CGI request.
+ *
+ * @todo:
+ * - don't use mem_malloc() (for SSI/dynamic headers)
+ * - split too long functions into multiple smaller functions?
+ * - support more file types?
+ */
+#include "lwip/debug.h"
+#include "lwip/stats.h"
+#include "httpd.h"
+#include "httpd_structs.h"
+#include "lwip/tcp.h"
+#include "fs.h"
+
+#include <string.h>
+#include <stdlib.h>
+
+#if LWIP_TCP
+
+#ifndef HTTPD_DEBUG
+#define HTTPD_DEBUG         LWIP_DBG_OFF
+#endif
+
+/** Set this to 1 and add the next line to lwippools.h to use a memp pool
+ * for allocating struct http_state instead of the heap:
+ *
+ * LWIP_MEMPOOL(HTTPD_STATE, 20, 100, "HTTPD_STATE")
+ */
+#ifndef HTTPD_USE_MEM_POOL
+#define HTTPD_USE_MEM_POOL  0
+#endif
+
+/** The server port for HTTPD to use */
+#ifndef HTTPD_SERVER_PORT
+#define HTTPD_SERVER_PORT                   80
+#endif
+
+/** Maximum retries before the connection is aborted/closed.
+ * - number of times pcb->poll is called -> default is 4*500ms = 2s;
+ * - reset when pcb->sent is called
+ */
+#ifndef HTTPD_MAX_RETRIES
+#define HTTPD_MAX_RETRIES                   4
+#endif
+
+/** The poll delay is X*500ms */
+#ifndef HTTPD_POLL_INTERVAL
+#define HTTPD_POLL_INTERVAL                 4
+#endif
+
+/** Priority for tcp pcbs created by HTTPD (very low by default).
+ *  Lower priorities get killed first when running out of memroy.
+ */
+#ifndef HTTPD_TCP_PRIO
+#define HTTPD_TCP_PRIO                      TCP_PRIO_MIN
+#endif
+
+/** Set this to 1 to enabled timing each file sent */
+#ifndef LWIP_HTTPD_TIMING
+#define LWIP_HTTPD_TIMING                   0
+#endif
+#ifndef HTTPD_DEBUG_TIMING
+#define HTTPD_DEBUG_TIMING                  LWIP_DBG_OFF
+#endif
+
+/** Set this to 1 on platforms where strnstr is not available */
+#ifndef LWIP_HTTPD_STRNSTR_PRIVATE
+#define LWIP_HTTPD_STRNSTR_PRIVATE          1
+#endif
+
+/** Set this to one to show error pages when parsing a request fails instead
+    of simply closing the connection. */
+#ifndef LWIP_HTTPD_SUPPORT_EXTSTATUS
+#define LWIP_HTTPD_SUPPORT_EXTSTATUS        0
+#endif
+
+/** Set this to 0 to drop support for HTTP/0.9 clients (to save some bytes) */
+#ifndef LWIP_HTTPD_SUPPORT_V09
+#define LWIP_HTTPD_SUPPORT_V09              1
+#endif
+
+/** Set this to 1 to support HTTP request coming in in multiple packets/pbufs */
+#ifndef LWIP_HTTPD_SUPPORT_REQUESTLIST
+#define LWIP_HTTPD_SUPPORT_REQUESTLIST      0
+#endif
+
+#if LWIP_HTTPD_SUPPORT_REQUESTLIST
+/** Number of rx pbufs to enqueue to parse an incoming request (up to the first
+    newline) */
+#ifndef LWIP_HTTPD_REQ_QUEUELEN
+#define LWIP_HTTPD_REQ_QUEUELEN             10
+#endif
+
+/** Number of (TCP payload-) bytes (in pbufs) to enqueue to parse and incoming
+    request (up to the first double-newline) */
+#ifndef LWIP_HTTPD_REQ_BUFSIZE
+#define LWIP_HTTPD_REQ_BUFSIZE              LWIP_HTTPD_MAX_REQ_LENGTH
+#endif
+
+/** Defines the maximum length of a HTTP request line (up to the first CRLF,
+    copied from pbuf into this a global buffer when pbuf- or packet-queues
+    are received - otherwise the input pbuf is used directly) */
+#ifndef LWIP_HTTPD_MAX_REQ_LENGTH
+#define LWIP_HTTPD_MAX_REQ_LENGTH           1023
+#endif
+#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
+
+/** Maximum length of the filename to send as response to a POST request,
+ * filled in by the application when a POST is finished.
+ */
+#ifndef LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN
+#define LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN 63
+#endif
+
+/** Set this to 0 to not send the SSI tag (default is on, so the tag will
+ * be sent in the HTML page */
+#ifndef LWIP_HTTPD_SSI_INCLUDE_TAG
+#define LWIP_HTTPD_SSI_INCLUDE_TAG           1
+#endif
+
+/** Set this to 1 to call tcp_abort when tcp_close fails with memory error.
+ * This can be used to prevent consuming all memory in situations where the
+ * HTTP server has low priority compared to other communication. */
+#ifndef LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR
+#define LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR  0
+#endif
+
+#ifndef true
+#define true ((u8_t)1)
+#endif
+
+#ifndef false
+#define false ((u8_t)0)
+#endif
+
+/** Minimum length for a valid HTTP/0.9 request: "GET /\r\n" -> 7 bytes */
+#define MIN_REQ_LEN   7
+
+#define CRLF "\r\n"
+
+/** These defines check whether tcp_write has to copy data or not */
+
+/** This was TI's check whether to let TCP copy data or not
+#define HTTP_IS_DATA_VOLATILE(hs) ((hs->file < (char *)0x20000000) ? 0 : TCP_WRITE_FLAG_COPY)*/
+#ifndef HTTP_IS_DATA_VOLATILE
+#if LWIP_HTTPD_SSI
+/* Copy for SSI files, no copy for non-SSI files */
+#define HTTP_IS_DATA_VOLATILE(hs)   ((hs)->tag_check ? TCP_WRITE_FLAG_COPY : 0)
+#else /* LWIP_HTTPD_SSI */
+/** Default: don't copy if the data is sent from file-system directly */
+#define HTTP_IS_DATA_VOLATILE(hs) (((hs->file != NULL) && (hs->handle != NULL) && (hs->file == \
+                                   (char*)hs->handle->data + hs->handle->len - hs->left)) \
+                                   ? 0 : TCP_WRITE_FLAG_COPY)
+#endif /* LWIP_HTTPD_SSI */
+#endif
+
+/** Default: headers are sent from ROM */
+#ifndef HTTP_IS_HDR_VOLATILE
+#define HTTP_IS_HDR_VOLATILE(hs, ptr) 0
+#endif
+
+#if LWIP_HTTPD_SSI
+/** Default: Tags are sent from struct http_state and are therefore volatile */
+#ifndef HTTP_IS_TAG_VOLATILE
+#define HTTP_IS_TAG_VOLATILE(ptr) TCP_WRITE_FLAG_COPY
+#endif
+#endif /* LWIP_HTTPD_SSI */
+
+typedef struct
+{
+  const char *name;
+  u8_t shtml;
+} default_filename;
+
+const default_filename g_psDefaultFilenames[] = {
+  {"/index.shtml", true },
+  {"/index.ssi", true },
+  {"/index.shtm", true },
+  {"/index.html", false },
+  {"/index.htm", false }
+};
+
+#define NUM_DEFAULT_FILENAMES (sizeof(g_psDefaultFilenames) /   \
+                               sizeof(default_filename))
+
+#if LWIP_HTTPD_SUPPORT_REQUESTLIST
+/** HTTP request is copied here from pbufs for simple parsing */
+static char httpd_req_buf[LWIP_HTTPD_MAX_REQ_LENGTH+1];
+#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
+
+#if LWIP_HTTPD_SUPPORT_POST
+/** Filename for response file to send when POST is finished */
+static char http_post_response_filename[LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN+1];
+#endif /* LWIP_HTTPD_SUPPORT_POST */
+
+#if LWIP_HTTPD_DYNAMIC_HEADERS
+/* The number of individual strings that comprise the headers sent before each
+ * requested file.
+ */
+#define NUM_FILE_HDR_STRINGS 3
+#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
+
+#if LWIP_HTTPD_SSI
+
+#define HTTPD_LAST_TAG_PART 0xFFFF
+
+const char * const g_pcSSIExtensions[] = {
+  ".shtml", ".shtm", ".ssi", ".xml"
+};
+
+#define NUM_SHTML_EXTENSIONS (sizeof(g_pcSSIExtensions) / sizeof(const char *))
+
+enum tag_check_state {
+  TAG_NONE,       /* Not processing an SSI tag */
+  TAG_LEADIN,     /* Tag lead in "<!--#" being processed */
+  TAG_FOUND,      /* Tag name being read, looking for lead-out start */
+  TAG_LEADOUT,    /* Tag lead out "-->" being processed */
+  TAG_SENDING     /* Sending tag replacement string */
+};
+#endif /* LWIP_HTTPD_SSI */
+
+struct http_state {
+  struct fs_file *handle;
+  char *file;       /* Pointer to first unsent byte in buf. */
+
+#if LWIP_HTTPD_SUPPORT_REQUESTLIST
+  struct pbuf *req;
+#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
+
+#if LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS
+  char *buf;        /* File read buffer. */
+  int buf_len;      /* Size of file read buffer, buf. */
+#endif /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */
+  u32_t left;       /* Number of unsent bytes in buf. */
+  u8_t retries;
+#if LWIP_HTTPD_SSI
+  const char *parsed;     /* Pointer to the first unparsed byte in buf. */
+#if !LWIP_HTTPD_SSI_INCLUDE_TAG
+  const char *tag_started;/* Poitner to the first opening '<' of the tag. */
+#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG */
+  const char *tag_end;    /* Pointer to char after the closing '>' of the tag. */
+  u32_t parse_left; /* Number of unparsed bytes in buf. */
+  u16_t tag_index;   /* Counter used by tag parsing state machine */
+  u16_t tag_insert_len; /* Length of insert in string tag_insert */
+#if LWIP_HTTPD_SSI_MULTIPART
+  u16_t tag_part; /* Counter passed to and changed by tag insertion function to insert multiple times */
+#endif /* LWIP_HTTPD_SSI_MULTIPART */
+  u8_t tag_check;   /* true if we are processing a .shtml file else false */
+  u8_t tag_name_len; /* Length of the tag name in string tag_name */
+  char tag_name[LWIP_HTTPD_MAX_TAG_NAME_LEN + 1]; /* Last tag name extracted */
+  char tag_insert[LWIP_HTTPD_MAX_TAG_INSERT_LEN + 1]; /* Insert string for tag_name */
+  enum tag_check_state tag_state; /* State of the tag processor */
+#endif /* LWIP_HTTPD_SSI */
+#if LWIP_HTTPD_CGI
+  char *params[LWIP_HTTPD_MAX_CGI_PARAMETERS]; /* Params extracted from the request URI */
+  char *param_vals[LWIP_HTTPD_MAX_CGI_PARAMETERS]; /* Values for each extracted param */
+#endif /* LWIP_HTTPD_CGI */
+#if LWIP_HTTPD_DYNAMIC_HEADERS
+  const char *hdrs[NUM_FILE_HDR_STRINGS]; /* HTTP headers to be sent. */
+  u16_t hdr_pos;     /* The position of the first unsent header byte in the
+                        current string */
+  u16_t hdr_index;   /* The index of the hdr string currently being sent. */
+#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
+#if LWIP_HTTPD_TIMING
+  u32_t time_started;
+#endif /* LWIP_HTTPD_TIMING */
+#if LWIP_HTTPD_SUPPORT_POST
+  u32_t post_content_len_left;
+#if LWIP_HTTPD_POST_MANUAL_WND
+  u32_t unrecved_bytes;
+  struct tcp_pcb *pcb;
+  u8_t no_auto_wnd;
+#endif /* LWIP_HTTPD_POST_MANUAL_WND */
+#endif /* LWIP_HTTPD_SUPPORT_POST*/
+};
+
+static err_t http_find_file(struct http_state *hs, const char *uri, int is_09);
+static err_t http_init_file(struct http_state *hs, struct fs_file *file, int is_09, const char *uri);
+static err_t http_poll(void *arg, struct tcp_pcb *pcb);
+
+#if LWIP_HTTPD_SSI
+/* SSI insert handler function pointer. */
+tSSIHandler g_pfnSSIHandler = NULL;
+int g_iNumTags = 0;
+const char **g_ppcTags = NULL;
+
+#define LEN_TAG_LEAD_IN 5
+const char * const g_pcTagLeadIn = "<!--#";
+
+#define LEN_TAG_LEAD_OUT 3
+const char * const g_pcTagLeadOut = "-->";
+#endif /* LWIP_HTTPD_SSI */
+
+#if LWIP_HTTPD_CGI
+/* CGI handler information */
+const tCGI *g_pCGIs;
+int g_iNumCGIs;
+#endif /* LWIP_HTTPD_CGI */
+
+#if LWIP_HTTPD_STRNSTR_PRIVATE
+/** Like strstr but does not need 'buffer' to be NULL-terminated */
+static char*
+strnstr(const char* buffer, const char* token, size_t n)
+{
+  const char* p;
+  int tokenlen = (int)strlen(token);
+  if (tokenlen == 0) {
+    return (char *)buffer;
+  }
+  for (p = buffer; *p && (p + tokenlen <= buffer + n); p++) {
+    if ((*p == *token) && (strncmp(p, token, tokenlen) == 0)) {
+      return (char *)p;
+    }
+  }
+  return NULL;
+} 
+#endif /* LWIP_HTTPD_STRNSTR_PRIVATE */
+
+/** Allocate a struct http_state. */
+static struct http_state*
+http_state_alloc(void)
+{
+  struct http_state *ret;
+#if HTTPD_USE_MEM_POOL
+  ret = (struct http_state *)memp_malloc(MEMP_HTTPD_STATE);
+#else /* HTTPD_USE_MEM_POOL */
+  ret = (struct http_state *)mem_malloc(sizeof(struct http_state));
+#endif /* HTTPD_USE_MEM_POOL */
+  if (ret != NULL) {
+    /* Initialize the structure. */
+    memset(ret, 0, sizeof(struct http_state));
+#if LWIP_HTTPD_DYNAMIC_HEADERS
+    /* Indicate that the headers are not yet valid */
+    ret->hdr_index = NUM_FILE_HDR_STRINGS;
+#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
+  }
+  return ret;
+}
+
+/** Free a struct http_state.
+ * Also frees the file data if dynamic.
+ */
+static void
+http_state_free(struct http_state *hs)
+{
+  if (hs != NULL) {
+    if(hs->handle) {
+#if LWIP_HTTPD_TIMING
+      u32_t ms_needed = sys_now() - hs->time_started;
+      u32_t needed = LWIP_MAX(1, (ms_needed/100));
+      LWIP_DEBUGF(HTTPD_DEBUG_TIMING, ("httpd: needed %"U32_F" ms to send file of %d bytes -> %"U32_F" bytes/sec\n",
+        ms_needed, hs->handle->len, ((((u32_t)hs->handle->len) * 10) / needed)));
+#endif /* LWIP_HTTPD_TIMING */
+      fs_close(hs->handle);
+      hs->handle = NULL;
+    }
+#if LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS
+    if (hs->buf != NULL) {
+      mem_free(hs->buf);
+      hs->buf = NULL;
+    }
+#endif /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */
+#if HTTPD_USE_MEM_POOL
+    memp_free(MEMP_HTTPD_STATE, hs);
+#else /* HTTPD_USE_MEM_POOL */
+    mem_free(hs);
+#endif /* HTTPD_USE_MEM_POOL */
+  }
+}
+
+/** Call tcp_write() in a loop trying smaller and smaller length
+ *
+ * @param pcb tcp_pcb to send
+ * @param ptr Data to send
+ * @param length Length of data to send (in/out: on return, contains the
+ *        amount of data sent)
+ * @param apiflags directly passed to tcp_write
+ * @return the return value of tcp_write
+ */
+static err_t
+http_write(struct tcp_pcb *pcb, const void* ptr, u16_t *length, u8_t apiflags)
+{
+   u16_t len;
+   err_t err;
+   LWIP_ASSERT("length != NULL", length != NULL);
+   len = *length;
+   do {
+     LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Trying go send %d bytes\n", len));
+     err = tcp_write(pcb, ptr, len, apiflags);
+     if (err == ERR_MEM) {
+       if ((tcp_sndbuf(pcb) == 0) ||
+           (tcp_sndqueuelen(pcb) >= TCP_SND_QUEUELEN)) {
+         /* no need to try smaller sizes */
+         len = 1;
+       } else {
+         len /= 2;
+       }
+       LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, 
+                   ("Send failed, trying less (%d bytes)\n", len));
+     }
+   } while ((err == ERR_MEM) && (len > 1));
+
+   if (err == ERR_OK) {
+     LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Sent %d bytes\n", len));
+   } else {
+     LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Send failed with err %d (\"%s\")\n", err, lwip_strerr(err)));
+   }
+
+   *length = len;
+   return err;
+}
+
+/**
+ * The connection shall be actively closed.
+ * Reset the sent- and recv-callbacks.
+ *
+ * @param pcb the tcp pcb to reset callbacks
+ * @param hs connection state to free
+ */
+static err_t
+http_close_conn(struct tcp_pcb *pcb, struct http_state *hs)
+{
+  err_t err;
+  LWIP_DEBUGF(HTTPD_DEBUG, ("Closing connection %p\n", (void*)pcb));
+
+#if LWIP_HTTPD_SUPPORT_POST
+  if (hs != NULL) {
+    if ((hs->post_content_len_left != 0)
+#if LWIP_HTTPD_POST_MANUAL_WND
+       || ((hs->no_auto_wnd != 0) && (hs->unrecved_bytes != 0))
+#endif /* LWIP_HTTPD_POST_MANUAL_WND */
+       ) {
+      /* make sure the post code knows that the connection is closed */
+      http_post_response_filename[0] = 0;
+      httpd_post_finished(hs, http_post_response_filename, LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN);
+    }
+  }
+#endif /* LWIP_HTTPD_SUPPORT_POST*/
+
+
+  tcp_arg(pcb, NULL);
+  tcp_recv(pcb, NULL);
+  tcp_err(pcb, NULL);
+  tcp_poll(pcb, NULL, 0);
+  tcp_sent(pcb, NULL);
+  if(hs != NULL) {
+    http_state_free(hs);
+  }
+
+  err = tcp_close(pcb);
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(HTTPD_DEBUG, ("Error %d closing %p\n", err, (void*)pcb));
+    /* error closing, try again later in poll */
+    tcp_poll(pcb, http_poll, HTTPD_POLL_INTERVAL);
+  }
+  return err;
+}
+#if LWIP_HTTPD_CGI
+/**
+ * Extract URI parameters from the parameter-part of an URI in the form
+ * "test.cgi?x=y" @todo: better explanation!
+ * Pointers to the parameters are stored in hs->param_vals.
+ *
+ * @param hs http connection state
+ * @param params pointer to the NULL-terminated parameter string from the URI
+ * @return number of parameters extracted
+ */
+static int
+extract_uri_parameters(struct http_state *hs, char *params)
+{
+  char *pair;
+  char *equals;
+  int loop;
+
+  /* If we have no parameters at all, return immediately. */
+  if(!params || (params[0] == '\0')) {
+      return(0);
+  }
+
+  /* Get a pointer to our first parameter */
+  pair = params;
+
+  /* Parse up to LWIP_HTTPD_MAX_CGI_PARAMETERS from the passed string and ignore the
+   * remainder (if any) */
+  for(loop = 0; (loop < LWIP_HTTPD_MAX_CGI_PARAMETERS) && pair; loop++) {
+
+    /* Save the name of the parameter */
+    hs->params[loop] = pair;
+
+    /* Remember the start of this name=value pair */
+    equals = pair;
+
+    /* Find the start of the next name=value pair and replace the delimiter
+     * with a 0 to terminate the previous pair string. */
+    pair = strchr(pair, '&');
+    if(pair) {
+      *pair = '\0';
+      pair++;
+    } else {
+       /* We didn't find a new parameter so find the end of the URI and
+        * replace the space with a '\0' */
+        pair = strchr(equals, ' ');
+        if(pair) {
+            *pair = '\0';
+        }
+
+        /* Revert to NULL so that we exit the loop as expected. */
+        pair = NULL;
+    }
+
+    /* Now find the '=' in the previous pair, replace it with '\0' and save
+     * the parameter value string. */
+    equals = strchr(equals, '=');
+    if(equals) {
+      *equals = '\0';
+      hs->param_vals[loop] = equals + 1;
+    } else {
+      hs->param_vals[loop] = NULL;
+    }
+  }
+
+  return loop;
+}
+#endif /* LWIP_HTTPD_CGI */
+
+#if LWIP_HTTPD_SSI
+/**
+ * Insert a tag (found in an shtml in the form of "<!--#tagname-->" into the file.
+ * The tag's name is stored in hs->tag_name (NULL-terminated), the replacement
+ * should be written to hs->tag_insert (up to a length of LWIP_HTTPD_MAX_TAG_INSERT_LEN).
+ * The amount of data written is stored to hs->tag_insert_len.
+ *
+ * @todo: return tag_insert_len - maybe it can be removed from struct http_state?
+ *
+ * @param hs http connection state
+ */
+static void
+get_tag_insert(struct http_state *hs)
+{
+  int loop;
+  size_t len;
+#if LWIP_HTTPD_SSI_MULTIPART
+  u16_t current_tag_part = hs->tag_part;
+  hs->tag_part = HTTPD_LAST_TAG_PART;
+#endif /* LWIP_HTTPD_SSI_MULTIPART */
+
+  if(g_pfnSSIHandler && g_ppcTags && g_iNumTags) {
+
+    /* Find this tag in the list we have been provided. */
+    for(loop = 0; loop < g_iNumTags; loop++) {
+      if(strcmp(hs->tag_name, g_ppcTags[loop]) == 0) {
+        hs->tag_insert_len = g_pfnSSIHandler(loop, hs->tag_insert,
+           LWIP_HTTPD_MAX_TAG_INSERT_LEN
+#if LWIP_HTTPD_SSI_MULTIPART
+           , current_tag_part, &hs->tag_part
+#endif /* LWIP_HTTPD_SSI_MULTIPART */
+#if LWIP_HTTPD_FILE_STATE
+           , hs->handle->state
+#endif /* LWIP_HTTPD_FILE_STATE */
+           );
+        return;
+      }
+    }
+  }
+
+  /* If we drop out, we were asked to serve a page which contains tags that
+   * we don't have a handler for. Merely echo back the tags with an error
+   * marker. */
+#define UNKNOWN_TAG1_TEXT "<b>***UNKNOWN TAG "
+#define UNKNOWN_TAG1_LEN  18
+#define UNKNOWN_TAG2_TEXT "***</b>"
+#define UNKNOWN_TAG2_LEN  7
+  len = LWIP_MIN(strlen(hs->tag_name),
+    LWIP_HTTPD_MAX_TAG_INSERT_LEN - (UNKNOWN_TAG1_LEN + UNKNOWN_TAG2_LEN));
+  MEMCPY(hs->tag_insert, UNKNOWN_TAG1_TEXT, UNKNOWN_TAG1_LEN);
+  MEMCPY(&hs->tag_insert[UNKNOWN_TAG1_LEN], hs->tag_name, len);
+  MEMCPY(&hs->tag_insert[UNKNOWN_TAG1_LEN + len], UNKNOWN_TAG2_TEXT, UNKNOWN_TAG2_LEN);
+  hs->tag_insert[UNKNOWN_TAG1_LEN + len + UNKNOWN_TAG2_LEN] = 0;
+
+  len = strlen(hs->tag_insert);
+  LWIP_ASSERT("len <= 0xffff", len <= 0xffff);
+  hs->tag_insert_len = (u16_t)len;
+}
+#endif /* LWIP_HTTPD_SSI */
+
+#if LWIP_HTTPD_DYNAMIC_HEADERS
+/**
+ * Generate the relevant HTTP headers for the given filename and write
+ * them into the supplied buffer.
+ */
+static void
+get_http_headers(struct http_state *pState, char *pszURI)
+{
+  unsigned int iLoop;
+  char *pszWork;
+  char *pszExt;
+  char *pszVars;
+
+  /* Ensure that we initialize the loop counter. */
+  iLoop = 0;
+
+  /* In all cases, the second header we send is the server identification
+     so set it here. */
+  pState->hdrs[1] = g_psHTTPHeaderStrings[HTTP_HDR_SERVER];
+
+  /* Is this a normal file or the special case we use to send back the
+     default "404: Page not found" response? */
+  if (pszURI == NULL) {
+    pState->hdrs[0] = g_psHTTPHeaderStrings[HTTP_HDR_NOT_FOUND];
+    pState->hdrs[2] = g_psHTTPHeaderStrings[DEFAULT_404_HTML];
+
+    /* Set up to send the first header string. */
+    pState->hdr_index = 0;
+    pState->hdr_pos = 0;
+    return;
+  } else {
+    /* We are dealing with a particular filename. Look for one other
+       special case.  We assume that any filename with "404" in it must be
+       indicative of a 404 server error whereas all other files require
+       the 200 OK header. */
+    if (strstr(pszURI, "404")) {
+      pState->hdrs[0] = g_psHTTPHeaderStrings[HTTP_HDR_NOT_FOUND];
+    } else if (strstr(pszURI, "400")) {
+      pState->hdrs[0] = g_psHTTPHeaderStrings[HTTP_HDR_BAD_REQUEST];
+    } else if (strstr(pszURI, "501")) {
+      pState->hdrs[0] = g_psHTTPHeaderStrings[HTTP_HDR_NOT_IMPL];
+    } else {
+      pState->hdrs[0] = g_psHTTPHeaderStrings[HTTP_HDR_OK];
+    }
+
+    /* Determine if the URI has any variables and, if so, temporarily remove 
+       them. */
+    pszVars = strchr(pszURI, '?');
+    if(pszVars) {
+      *pszVars = '\0';
+    }
+
+    /* Get a pointer to the file extension.  We find this by looking for the
+       last occurrence of "." in the filename passed. */
+    pszExt = NULL;
+    pszWork = strchr(pszURI, '.');
+    while(pszWork) {
+      pszExt = pszWork + 1;
+      pszWork = strchr(pszExt, '.');
+    }
+
+    /* Now determine the content type and add the relevant header for that. */
+    for(iLoop = 0; (iLoop < NUM_HTTP_HEADERS) && pszExt; iLoop++) {
+      /* Have we found a matching extension? */
+      if(!strcmp(g_psHTTPHeaders[iLoop].extension, pszExt)) {
+        pState->hdrs[2] =
+          g_psHTTPHeaderStrings[g_psHTTPHeaders[iLoop].headerIndex];
+        break;
+      }
+    }
+
+    /* Reinstate the parameter marker if there was one in the original URI. */
+    if(pszVars) {
+      *pszVars = '?';
+    }
+  }
+
+  /* Does the URL passed have any file extension?  If not, we assume it
+     is a special-case URL used for control state notification and we do
+     not send any HTTP headers with the response. */
+  if(!pszExt) {
+    /* Force the header index to a value indicating that all headers
+       have already been sent. */
+    pState->hdr_index = NUM_FILE_HDR_STRINGS;
+  } else {
+    /* Did we find a matching extension? */
+    if(iLoop == NUM_HTTP_HEADERS) {
+      /* No - use the default, plain text file type. */
+      pState->hdrs[2] = g_psHTTPHeaderStrings[HTTP_HDR_DEFAULT_TYPE];
+    }
+
+    /* Set up to send the first header string. */
+    pState->hdr_index = 0;
+    pState->hdr_pos = 0;
+  }
+}
+#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
+
+/**
+ * Try to send more data on this pcb.
+ *
+ * @param pcb the pcb to send data
+ * @param hs connection state
+ */
+static u8_t
+http_send_data(struct tcp_pcb *pcb, struct http_state *hs)
+{
+  err_t err;
+  u16_t len;
+  u16_t mss;
+  u8_t data_to_send = false;
+#if LWIP_HTTPD_DYNAMIC_HEADERS
+  u16_t hdrlen, sendlen;
+#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
+
+  LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_send_data: pcb=%p hs=%p left=%d\n", (void*)pcb,
+    (void*)hs, hs != NULL ? hs->left : 0));
+
+#if LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND
+  if (hs->unrecved_bytes != 0) {
+    return 0;
+  }
+#endif /* LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND */
+
+#if LWIP_HTTPD_DYNAMIC_HEADERS
+  /* If we were passed a NULL state structure pointer, ignore the call. */
+  if (hs == NULL) {
+    return 0;
+  }
+
+  /* Assume no error until we find otherwise */
+  err = ERR_OK;
+
+  /* Do we have any more header data to send for this file? */
+  if(hs->hdr_index < NUM_FILE_HDR_STRINGS) {
+    /* How much data can we send? */
+    len = tcp_sndbuf(pcb);
+    sendlen = len;
+
+    while(len && (hs->hdr_index < NUM_FILE_HDR_STRINGS) && sendlen) {
+      const void *ptr;
+      u16_t old_sendlen;
+      /* How much do we have to send from the current header? */
+      hdrlen = (u16_t)strlen(hs->hdrs[hs->hdr_index]);
+
+      /* How much of this can we send? */
+      sendlen = (len < (hdrlen - hs->hdr_pos)) ? len : (hdrlen - hs->hdr_pos);
+
+      /* Send this amount of data or as much as we can given memory
+      * constraints. */
+      ptr = (const void *)(hs->hdrs[hs->hdr_index] + hs->hdr_pos);
+      old_sendlen = sendlen;
+      err = http_write(pcb, ptr, &sendlen, HTTP_IS_HDR_VOLATILE(hs, ptr));
+      if ((err == ERR_OK) && (old_sendlen != sendlen)) {
+        /* Remember that we added some more data to be transmitted. */
+        data_to_send = true;
+      } else if (err != ERR_OK) {
+         /* special case: http_write does not try to send 1 byte */
+        sendlen = 0;
+      }
+
+      /* Fix up the header position for the next time round. */
+      hs->hdr_pos += sendlen;
+      len -= sendlen;
+
+      /* Have we finished sending this string? */
+      if(hs->hdr_pos == hdrlen) {
+        /* Yes - move on to the next one */
+        hs->hdr_index++;
+        hs->hdr_pos = 0;
+      }
+    }
+
+    /* If we get here and there are still header bytes to send, we send
+    * the header information we just wrote immediately.  If there are no
+    * more headers to send, but we do have file data to send, drop through
+    * to try to send some file data too. */
+    if((hs->hdr_index < NUM_FILE_HDR_STRINGS) || !hs->file) {
+      LWIP_DEBUGF(HTTPD_DEBUG, ("tcp_output\n"));
+      return 1;
+    }
+  }
+#else /* LWIP_HTTPD_DYNAMIC_HEADERS */
+  /* Assume no error until we find otherwise */
+  err = ERR_OK;
+#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
+
+  /* Have we run out of file data to send? If so, we need to read the next
+   * block from the file. */
+  if (hs->left == 0) {
+#if LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS
+    int count;
+#endif /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */
+
+    /* Do we have a valid file handle? */
+    if (hs->handle == NULL) {
+      /* No - close the connection. */
+      http_close_conn(pcb, hs);
+      return 0;
+    }
+    if (fs_bytes_left(hs->handle) <= 0) {
+      /* We reached the end of the file so this request is done.
+       * @todo: don't close here for HTTP/1.1? */
+      LWIP_DEBUGF(HTTPD_DEBUG, ("End of file.\n"));
+      http_close_conn(pcb, hs);
+      return 0;
+    }
+#if LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS
+    /* Do we already have a send buffer allocated? */
+    if(hs->buf) {
+      /* Yes - get the length of the buffer */
+      count = hs->buf_len;
+    } else {
+      /* We don't have a send buffer so allocate one up to 2mss bytes long. */
+      count = 2 * tcp_mss(pcb);
+      do {
+        hs->buf = (char*)mem_malloc((mem_size_t)count);
+        if (hs->buf != NULL) {
+          hs->buf_len = count;
+          break;
+        }
+        count = count / 2;
+      } while (count > 100);
+
+      /* Did we get a send buffer? If not, return immediately. */
+      if (hs->buf == NULL) {
+        LWIP_DEBUGF(HTTPD_DEBUG, ("No buff\n"));
+        return 0;
+      }
+    }
+
+    /* Read a block of data from the file. */
+    LWIP_DEBUGF(HTTPD_DEBUG, ("Trying to read %d bytes.\n", count));
+
+    count = fs_read(hs->handle, hs->buf, count);
+    if(count < 0) {
+      /* We reached the end of the file so this request is done.
+       * @todo: don't close here for HTTP/1.1? */
+      LWIP_DEBUGF(HTTPD_DEBUG, ("End of file.\n"));
+      http_close_conn(pcb, hs);
+      return 1;
+    }
+
+    /* Set up to send the block of data we just read */
+    LWIP_DEBUGF(HTTPD_DEBUG, ("Read %d bytes.\n", count));
+    hs->left = count;
+    hs->file = hs->buf;
+#if LWIP_HTTPD_SSI
+    hs->parse_left = count;
+    hs->parsed = hs->buf;
+#endif /* LWIP_HTTPD_SSI */
+#else /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */
+    LWIP_ASSERT("SSI and DYNAMIC_HEADERS turned off but eof not reached", 0);
+#endif /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */
+  }
+
+#if LWIP_HTTPD_SSI
+  if(!hs->tag_check) {
+#endif /* LWIP_HTTPD_SSI */
+    /* We are not processing an SHTML file so no tag checking is necessary.
+     * Just send the data as we received it from the file. */
+
+    /* We cannot send more data than space available in the send
+       buffer. */
+    if (tcp_sndbuf(pcb) < hs->left) {
+      len = tcp_sndbuf(pcb);
+    } else {
+      len = (u16_t)hs->left;
+      LWIP_ASSERT("hs->left did not fit into u16_t!", (len == hs->left));
+    }
+    mss = tcp_mss(pcb);
+    if(len > (2 * mss)) {
+      len = 2 * mss;
+    }
+
+    err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs));
+    if (err == ERR_OK) {
+      data_to_send = true;
+      hs->file += len;
+      hs->left -= len;
+    }
+#if LWIP_HTTPD_SSI
+  } else {
+    /* We are processing an SHTML file so need to scan for tags and replace
+     * them with insert strings. We need to be careful here since a tag may
+     * straddle the boundary of two blocks read from the file and we may also
+     * have to split the insert string between two tcp_write operations. */
+
+    /* How much data could we send? */
+    len = tcp_sndbuf(pcb);
+
+    /* Do we have remaining data to send before parsing more? */
+    if(hs->parsed > hs->file) {
+      /* We cannot send more data than space available in the send
+         buffer. */
+      if (tcp_sndbuf(pcb) < (hs->parsed - hs->file)) {
+        len = tcp_sndbuf(pcb);
+      } else {
+        LWIP_ASSERT("Data size does not fit into u16_t!",
+                    (hs->parsed - hs->file) <= 0xffff);
+        len = (u16_t)(hs->parsed - hs->file);
+      }
+      mss = tcp_mss(pcb);
+      if(len > (2 * mss)) {
+        len = 2 * mss;
+      }
+
+      err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs));
+      if (err == ERR_OK) {
+        data_to_send = true;
+        hs->file += len;
+        hs->left -= len;
+      }
+
+      /* If the send buffer is full, return now. */
+      if(tcp_sndbuf(pcb) == 0) {
+        return data_to_send;
+      }
+    }
+
+    LWIP_DEBUGF(HTTPD_DEBUG, ("State %d, %d left\n", hs->tag_state, hs->parse_left));
+
+    /* We have sent all the data that was already parsed so continue parsing
+     * the buffer contents looking for SSI tags. */
+    while((hs->parse_left) && (err == ERR_OK)) {
+      /* @todo: somewhere in this loop, 'len' should grow again... */
+      if (len == 0) {
+        return data_to_send;
+      }
+      switch(hs->tag_state) {
+        case TAG_NONE:
+          /* We are not currently processing an SSI tag so scan for the
+           * start of the lead-in marker. */
+          if(*hs->parsed == g_pcTagLeadIn[0]) {
+            /* We found what could be the lead-in for a new tag so change
+             * state appropriately. */
+            hs->tag_state = TAG_LEADIN;
+            hs->tag_index = 1;
+#if !LWIP_HTTPD_SSI_INCLUDE_TAG
+            hs->tag_started = hs->parsed;
+#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG */
+          }
+
+          /* Move on to the next character in the buffer */
+          hs->parse_left--;
+          hs->parsed++;
+          break;
+
+        case TAG_LEADIN:
+          /* We are processing the lead-in marker, looking for the start of
+           * the tag name. */
+
+          /* Have we reached the end of the leadin? */
+          if(hs->tag_index == LEN_TAG_LEAD_IN) {
+            hs->tag_index = 0;
+            hs->tag_state = TAG_FOUND;
+          } else {
+            /* Have we found the next character we expect for the tag leadin? */
+            if(*hs->parsed == g_pcTagLeadIn[hs->tag_index]) {
+              /* Yes - move to the next one unless we have found the complete
+               * leadin, in which case we start looking for the tag itself */
+              hs->tag_index++;
+            } else {
+              /* We found an unexpected character so this is not a tag. Move
+               * back to idle state. */
+              hs->tag_state = TAG_NONE;
+            }
+
+            /* Move on to the next character in the buffer */
+            hs->parse_left--;
+            hs->parsed++;
+          }
+          break;
+
+        case TAG_FOUND:
+          /* We are reading the tag name, looking for the start of the
+           * lead-out marker and removing any whitespace found. */
+
+          /* Remove leading whitespace between the tag leading and the first
+           * tag name character. */
+          if((hs->tag_index == 0) && ((*hs->parsed == ' ') ||
+             (*hs->parsed == '\t') || (*hs->parsed == '\n') ||
+             (*hs->parsed == '\r'))) {
+            /* Move on to the next character in the buffer */
+            hs->parse_left--;
+            hs->parsed++;
+            break;
+          }
+
+          /* Have we found the end of the tag name? This is signalled by
+           * us finding the first leadout character or whitespace */
+          if((*hs->parsed == g_pcTagLeadOut[0]) ||
+             (*hs->parsed == ' ') || (*hs->parsed == '\t') ||
+             (*hs->parsed == '\n')  || (*hs->parsed == '\r')) {
+
+            if(hs->tag_index == 0) {
+              /* We read a zero length tag so ignore it. */
+              hs->tag_state = TAG_NONE;
+            } else {
+              /* We read a non-empty tag so go ahead and look for the
+               * leadout string. */
+              hs->tag_state = TAG_LEADOUT;
+              LWIP_ASSERT("hs->tag_index <= 0xff", hs->tag_index <= 0xff);
+              hs->tag_name_len = (u8_t)hs->tag_index;
+              hs->tag_name[hs->tag_index] = '\0';
+              if(*hs->parsed == g_pcTagLeadOut[0]) {
+                hs->tag_index = 1;
+              } else {
+                hs->tag_index = 0;
+              }
+            }
+          } else {
+            /* This character is part of the tag name so save it */
+            if(hs->tag_index < LWIP_HTTPD_MAX_TAG_NAME_LEN) {
+              hs->tag_name[hs->tag_index++] = *hs->parsed;
+            } else {
+              /* The tag was too long so ignore it. */
+              hs->tag_state = TAG_NONE;
+            }
+          }
+
+          /* Move on to the next character in the buffer */
+          hs->parse_left--;
+          hs->parsed++;
+
+          break;
+
+        /* We are looking for the end of the lead-out marker. */
+        case TAG_LEADOUT:
+          /* Remove leading whitespace between the tag leading and the first
+           * tag leadout character. */
+          if((hs->tag_index == 0) && ((*hs->parsed == ' ') ||
+             (*hs->parsed == '\t') || (*hs->parsed == '\n') ||
+             (*hs->parsed == '\r'))) {
+            /* Move on to the next character in the buffer */
+            hs->parse_left--;
+            hs->parsed++;
+            break;
+          }
+
+          /* Have we found the next character we expect for the tag leadout? */
+          if(*hs->parsed == g_pcTagLeadOut[hs->tag_index]) {
+            /* Yes - move to the next one unless we have found the complete
+             * leadout, in which case we need to call the client to process
+             * the tag. */
+
+            /* Move on to the next character in the buffer */
+            hs->parse_left--;
+            hs->parsed++;
+
+            if(hs->tag_index == (LEN_TAG_LEAD_OUT - 1)) {
+              /* Call the client to ask for the insert string for the
+               * tag we just found. */
+#if LWIP_HTTPD_SSI_MULTIPART
+              hs->tag_part = 0; /* start with tag part 0 */
+#endif /* LWIP_HTTPD_SSI_MULTIPART */
+              get_tag_insert(hs);
+
+              /* Next time through, we are going to be sending data
+               * immediately, either the end of the block we start
+               * sending here or the insert string. */
+              hs->tag_index = 0;
+              hs->tag_state = TAG_SENDING;
+              hs->tag_end = hs->parsed;
+#if !LWIP_HTTPD_SSI_INCLUDE_TAG
+              hs->parsed = hs->tag_started;
+#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/
+
+              /* If there is any unsent data in the buffer prior to the
+               * tag, we need to send it now. */
+              if (hs->tag_end > hs->file) {
+                /* How much of the data can we send? */
+#if LWIP_HTTPD_SSI_INCLUDE_TAG
+                if(len > hs->tag_end - hs->file) {
+                  len = (u16_t)(hs->tag_end - hs->file);
+                }
+#else /* LWIP_HTTPD_SSI_INCLUDE_TAG*/
+                if(len > hs->tag_started - hs->file) {
+                  /* we would include the tag in sending */
+                  len = (u16_t)(hs->tag_started - hs->file);
+                }
+#endif /* LWIP_HTTPD_SSI_INCLUDE_TAG*/
+
+                err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs));
+                if (err == ERR_OK) {
+                  data_to_send = true;
+#if !LWIP_HTTPD_SSI_INCLUDE_TAG
+                  if(hs->tag_started <= hs->file) {
+                    /* pretend to have sent the tag, too */
+                    len += hs->tag_end - hs->tag_started;
+                  }
+#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/
+                  hs->file += len;
+                  hs->left -= len;
+                }
+              }
+            } else {
+              hs->tag_index++;
+            }
+          } else {
+            /* We found an unexpected character so this is not a tag. Move
+             * back to idle state. */
+            hs->parse_left--;
+            hs->parsed++;
+            hs->tag_state = TAG_NONE;
+          }
+          break;
+
+        /*
+         * We have found a valid tag and are in the process of sending
+         * data as a result of that discovery. We send either remaining data
+         * from the file prior to the insert point or the insert string itself.
+         */
+        case TAG_SENDING:
+          /* Do we have any remaining file data to send from the buffer prior
+           * to the tag? */
+          if(hs->tag_end > hs->file) {
+            /* How much of the data can we send? */
+#if LWIP_HTTPD_SSI_INCLUDE_TAG
+            if(len > hs->tag_end - hs->file) {
+              len = (u16_t)(hs->tag_end - hs->file);
+            }
+#else /* LWIP_HTTPD_SSI_INCLUDE_TAG*/
+            LWIP_ASSERT("hs->started >= hs->file", hs->tag_started >= hs->file);
+            if (len > hs->tag_started - hs->file) {
+              /* we would include the tag in sending */
+              len = (u16_t)(hs->tag_started - hs->file);
+            }
+#endif /* LWIP_HTTPD_SSI_INCLUDE_TAG*/
+            if (len != 0) {
+              err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs));
+            } else {
+              err = ERR_OK;
+            }
+            if (err == ERR_OK) {
+              data_to_send = true;
+#if !LWIP_HTTPD_SSI_INCLUDE_TAG
+              if(hs->tag_started <= hs->file) {
+                /* pretend to have sent the tag, too */
+                len += hs->tag_end - hs->tag_started;
+              }
+#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/
+              hs->file += len;
+              hs->left -= len;
+            }
+          } else {
+#if LWIP_HTTPD_SSI_MULTIPART
+            if(hs->tag_index >= hs->tag_insert_len) {
+              /* Did the last SSIHandler have more to send? */
+              if (hs->tag_part != HTTPD_LAST_TAG_PART) {
+                /* If so, call it again */
+                hs->tag_index = 0;
+                get_tag_insert(hs);
+              }
+            }
+#endif /* LWIP_HTTPD_SSI_MULTIPART */
+
+            /* Do we still have insert data left to send? */
+            if(hs->tag_index < hs->tag_insert_len) {
+              /* We are sending the insert string itself. How much of the
+               * insert can we send? */
+              if(len > (hs->tag_insert_len - hs->tag_index)) {
+                len = (hs->tag_insert_len - hs->tag_index);
+              }
+
+              /* Note that we set the copy flag here since we only have a
+               * single tag insert buffer per connection. If we don't do
+               * this, insert corruption can occur if more than one insert
+               * is processed before we call tcp_output. */
+              err = http_write(pcb, &(hs->tag_insert[hs->tag_index]), &len,
+                               HTTP_IS_TAG_VOLATILE(hs));
+              if (err == ERR_OK) {
+                data_to_send = true;
+                hs->tag_index += len;
+                /* Don't return here: keep on sending data */
+              }
+            } else {
+              /* We have sent all the insert data so go back to looking for
+               * a new tag. */
+              LWIP_DEBUGF(HTTPD_DEBUG, ("Everything sent.\n"));
+              hs->tag_index = 0;
+              hs->tag_state = TAG_NONE;
+#if !LWIP_HTTPD_SSI_INCLUDE_TAG
+              hs->parsed = hs->tag_end;
+#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/
+            }
+            break;
+        }
+      }
+    }
+
+    /* If we drop out of the end of the for loop, this implies we must have
+     * file data to send so send it now. In TAG_SENDING state, we've already
+     * handled this so skip the send if that's the case. */
+    if((hs->tag_state != TAG_SENDING) && (hs->parsed > hs->file)) {
+      /* We cannot send more data than space available in the send
+         buffer. */
+      if (tcp_sndbuf(pcb) < (hs->parsed - hs->file)) {
+        len = tcp_sndbuf(pcb);
+      } else {
+        LWIP_ASSERT("Data size does not fit into u16_t!",
+                    (hs->parsed - hs->file) <= 0xffff);
+        len = (u16_t)(hs->parsed - hs->file);
+      }
+      if(len > (2 * tcp_mss(pcb))) {
+        len = 2 * tcp_mss(pcb);
+      }
+
+      err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs));
+      if (err == ERR_OK) {
+        data_to_send = true;
+        hs->file += len;
+        hs->left -= len;
+      }
+    }
+  }
+#endif /* LWIP_HTTPD_SSI */
+
+  if((hs->left == 0) && (fs_bytes_left(hs->handle) <= 0)) {
+    /* We reached the end of the file so this request is done.
+     * This adds the FIN flag right into the last data segment.
+     * @todo: don't close here for HTTP/1.1? */
+    LWIP_DEBUGF(HTTPD_DEBUG, ("End of file.\n"));
+    http_close_conn(pcb, hs);
+    return 0;
+  }
+  LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("send_data end.\n"));
+  return data_to_send;
+}
+
+#if LWIP_HTTPD_SUPPORT_EXTSTATUS
+/** Initialize a http connection with a file to send for an error message
+ *
+ * @param hs http connection state
+ * @param error_nr HTTP error number
+ * @return ERR_OK if file was found and hs has been initialized correctly
+ *         another err_t otherwise
+ */
+static err_t
+http_find_error_file(struct http_state *hs, u16_t error_nr)
+{
+  const char *uri1, *uri2, *uri3;
+  struct fs_file *file;
+
+  if (error_nr == 501) {
+    uri1 = "/501.html";
+    uri2 = "/501.htm";
+    uri3 = "/501.shtml";
+  } else {
+    /* 400 (bad request is the default) */
+    uri1 = "/400.html";
+    uri2 = "/400.htm";
+    uri3 = "/400.shtml";
+  }
+  file = fs_open(uri1);
+  if (file == NULL) {
+    file = fs_open(uri2);
+    if (file == NULL) {
+      file = fs_open(uri3);
+      if (file == NULL) {
+        LWIP_DEBUGF(HTTPD_DEBUG, ("Error page for error %"U16_F" not found\n",
+          error_nr));
+        return ERR_ARG;
+      }
+    }
+  }
+  return http_init_file(hs, file, 0, NULL);
+}
+#else /* LWIP_HTTPD_SUPPORT_EXTSTATUS */
+#define http_find_error_file(hs, error_nr) ERR_ARG
+#endif /* LWIP_HTTPD_SUPPORT_EXTSTATUS */
+
+/**
+ * Get the file struct for a 404 error page.
+ * Tries some file names and returns NULL if none found.
+ *
+ * @param uri pointer that receives the actual file name URI
+ * @return file struct for the error page or NULL no matching file was found
+ */
+static struct fs_file *
+http_get_404_file(const char **uri)
+{
+  struct fs_file *file;
+
+  *uri = "/404.html";
+  file = fs_open(*uri);
+  if(file == NULL) {
+    /* 404.html doesn't exist. Try 404.htm instead. */
+    *uri = "/404.htm";
+    file = fs_open(*uri);
+    if(file == NULL) {
+      /* 404.htm doesn't exist either. Try 404.shtml instead. */
+      *uri = "/404.shtml";
+      file = fs_open(*uri);
+      if(file == NULL) {
+        /* 404.htm doesn't exist either. Indicate to the caller that it should
+         * send back a default 404 page.
+         */
+        *uri = NULL;
+      }
+    }
+  }
+
+  return file;
+}
+
+#if LWIP_HTTPD_SUPPORT_POST
+static err_t
+http_handle_post_finished(struct http_state *hs)
+{
+  /* application error or POST finished */
+  /* NULL-terminate the buffer */
+  http_post_response_filename[0] = 0;
+  httpd_post_finished(hs, http_post_response_filename, LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN);
+  return http_find_file(hs, http_post_response_filename, 0);
+}
+
+/** Pass received POST body data to the application and correctly handle
+ * returning a response document or closing the connection.
+ * ATTENTION: The application is responsible for the pbuf now, so don't free it!
+ *
+ * @param hs http connection state
+ * @param p pbuf to pass to the application
+ * @return ERR_OK if passed successfully, another err_t if the response file
+ *         hasn't been found (after POST finished)
+ */
+static err_t
+http_post_rxpbuf(struct http_state *hs, struct pbuf *p)
+{
+  err_t err;
+
+  /* adjust remaining Content-Length */
+  if (hs->post_content_len_left < p->tot_len) {
+    hs->post_content_len_left = 0;
+  } else {
+    hs->post_content_len_left -= p->tot_len;
+  }
+  err = httpd_post_receive_data(hs, p);
+  if ((err != ERR_OK) || (hs->post_content_len_left == 0)) {
+#if LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND
+    if (hs->unrecved_bytes != 0) {
+       return ERR_OK;
+    }
+#endif /* LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND */
+    /* application error or POST finished */
+    return http_handle_post_finished(hs);
+  }
+
+  return ERR_OK;
+}
+
+/** Handle a post request. Called from http_parse_request when method 'POST'
+ * is found.
+ *
+ * @param pcb The tcp_pcb which received this packet.
+ * @param p The input pbuf (containing the POST header and body).
+ * @param hs The http connection state.
+ * @param data HTTP request (header and part of body) from input pbuf(s).
+ * @param data_len Size of 'data'.
+ * @param uri The HTTP URI parsed from input pbuf(s).
+ * @param uri_end Pointer to the end of 'uri' (here, the rest of the HTTP
+ *                header starts).
+ * @return ERR_OK: POST correctly parsed and accepted by the application.
+ *         ERR_INPROGRESS: POST not completely parsed (no error yet)
+ *         another err_t: Error parsing POST or denied by the application
+ */
+static err_t
+http_post_request(struct tcp_pcb *pcb, struct pbuf **inp, struct http_state *hs,
+                  char *data, u16_t data_len, char *uri, char *uri_end)
+{
+  err_t err;
+  /* search for end-of-header (first double-CRLF) */
+  char* crlfcrlf = strnstr(uri_end + 1, CRLF CRLF, data_len - (uri_end + 1 - data));
+
+#if LWIP_HTTPD_POST_MANUAL_WND
+  hs->pcb = pcb;
+#else /* LWIP_HTTPD_POST_MANUAL_WND */
+  LWIP_UNUSED_ARG(pcb); /* only used for LWIP_HTTPD_POST_MANUAL_WND */
+#endif /*  LWIP_HTTPD_POST_MANUAL_WND */
+
+  if (crlfcrlf != NULL) {
+    /* search for "Content-Length: " */
+#define HTTP_HDR_CONTENT_LEN                "Content-Length: "
+#define HTTP_HDR_CONTENT_LEN_LEN            16
+#define HTTP_HDR_CONTENT_LEN_DIGIT_MAX_LEN  10
+    char *scontent_len = strnstr(uri_end + 1, HTTP_HDR_CONTENT_LEN, crlfcrlf - (uri_end + 1));
+    if (scontent_len != NULL) {
+      char *scontent_len_end = strnstr(scontent_len + HTTP_HDR_CONTENT_LEN_LEN, CRLF, HTTP_HDR_CONTENT_LEN_DIGIT_MAX_LEN);
+      if (scontent_len_end != NULL) {
+        int content_len;
+        char *conten_len_num = scontent_len + HTTP_HDR_CONTENT_LEN_LEN;
+        *scontent_len_end = 0;
+        content_len = atoi(conten_len_num);
+        if (content_len > 0) {
+          /* adjust length of HTTP header passed to application */
+          const char *hdr_start_after_uri = uri_end + 1;
+          u16_t hdr_len = LWIP_MIN(data_len, crlfcrlf + 4 - data);
+          u16_t hdr_data_len = LWIP_MIN(data_len, crlfcrlf + 4 - hdr_start_after_uri);
+          u8_t post_auto_wnd = 1;
+          http_post_response_filename[0] = 0;
+          err = httpd_post_begin(hs, uri, hdr_start_after_uri, hdr_data_len, content_len,
+            http_post_response_filename, LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN, &post_auto_wnd);
+          if (err == ERR_OK) {
+            /* try to pass in data of the first pbuf(s) */
+            struct pbuf *q = *inp;
+            u16_t start_offset = hdr_len;
+#if LWIP_HTTPD_POST_MANUAL_WND
+            hs->no_auto_wnd = !post_auto_wnd;
+#endif /* LWIP_HTTPD_POST_MANUAL_WND */
+            /* set the Content-Length to be received for this POST */
+            hs->post_content_len_left = (u32_t)content_len;
+
+            /* get to the pbuf where the body starts */
+            while((q != NULL) && (q->len <= start_offset)) {
+              struct pbuf *head = q;
+              start_offset -= q->len;
+              q = q->next;
+              /* free the head pbuf */
+              head->next = NULL;
+              pbuf_free(head);
+            }
+            *inp = NULL;
+            if (q != NULL) {
+              /* hide the remaining HTTP header */
+              pbuf_header(q, -(s16_t)start_offset);
+#if LWIP_HTTPD_POST_MANUAL_WND
+              if (!post_auto_wnd) {
+                /* already tcp_recved() this data... */
+                hs->unrecved_bytes = q->tot_len;
+              }
+#endif /* LWIP_HTTPD_POST_MANUAL_WND */
+              return http_post_rxpbuf(hs, q);
+            } else {
+              return ERR_OK;
+            }
+          } else {
+            /* return file passed from application */
+            return http_find_file(hs, http_post_response_filename, 0);
+          }
+        } else {
+          LWIP_DEBUGF(HTTPD_DEBUG, ("POST received invalid Content-Length: %s\n",
+            conten_len_num));
+          return ERR_ARG;
+        }
+      }
+    }
+  }
+  /* if we come here, the POST is incomplete */
+#if LWIP_HTTPD_SUPPORT_REQUESTLIST
+  return ERR_INPROGRESS;
+#else /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
+  return ERR_ARG;
+#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
+}
+
+#if LWIP_HTTPD_POST_MANUAL_WND
+/** A POST implementation can call this function to update the TCP window.
+ * This can be used to throttle data reception (e.g. when received data is
+ * programmed to flash and data is received faster than programmed).
+ *
+ * @param connection A connection handle passed to httpd_post_begin for which
+ *        httpd_post_finished has *NOT* been called yet!
+ * @param recved_len Length of data received (for window update)
+ */
+void httpd_post_data_recved(void *connection, u16_t recved_len)
+{
+  struct http_state *hs = (struct http_state*)connection;
+  if (hs != NULL) {
+    if (hs->no_auto_wnd) {
+      u16_t len = recved_len;
+      if (hs->unrecved_bytes >= recved_len) {
+        hs->unrecved_bytes -= recved_len;
+      } else {
+        LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_LEVEL_WARNING, ("httpd_post_data_recved: recved_len too big\n"));
+        len = (u16_t)hs->unrecved_bytes;
+        hs->unrecved_bytes = 0;
+      }
+      if (hs->pcb != NULL) {
+        if (len != 0) {
+          tcp_recved(hs->pcb, len);
+        }
+        if ((hs->post_content_len_left == 0) && (hs->unrecved_bytes == 0)) {
+          /* finished handling POST */
+          http_handle_post_finished(hs);
+          http_send_data(hs->pcb, hs);
+        }
+      }
+    }
+  }
+}
+#endif /* LWIP_HTTPD_POST_MANUAL_WND */
+
+#endif /* LWIP_HTTPD_SUPPORT_POST */
+
+/**
+ * When data has been received in the correct state, try to parse it
+ * as a HTTP request.
+ *
+ * @param p the received pbuf
+ * @param hs the connection state
+ * @param pcb the tcp_pcb which received this packet
+ * @return ERR_OK if request was OK and hs has been initialized correctly
+ *         ERR_INPROGRESS if request was OK so far but not fully received
+ *         another err_t otherwise
+ */
+static err_t
+http_parse_request(struct pbuf **inp, struct http_state *hs, struct tcp_pcb *pcb)
+{
+  char *data;
+  char *crlf;
+  u16_t data_len;
+  struct pbuf *p = *inp;
+#if LWIP_HTTPD_SUPPORT_REQUESTLIST
+  u16_t clen;
+#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
+#if LWIP_HTTPD_SUPPORT_POST
+  err_t err;
+#endif /* LWIP_HTTPD_SUPPORT_POST */
+
+  LWIP_UNUSED_ARG(pcb); /* only used for post */
+  LWIP_ASSERT("p != NULL", p != NULL);
+  LWIP_ASSERT("hs != NULL", hs != NULL);
+
+  if ((hs->handle != NULL) || (hs->file != NULL)) {
+    LWIP_DEBUGF(HTTPD_DEBUG, ("Received data while sending a file\n"));
+    /* already sending a file */
+    /* @todo: abort? */
+    return ERR_USE;
+  }
+
+#if LWIP_HTTPD_SUPPORT_REQUESTLIST
+
+  LWIP_DEBUGF(HTTPD_DEBUG, ("Received %"U16_F" bytes\n", p->tot_len));
+
+  /* first check allowed characters in this pbuf? */
+
+  /* enqueue the pbuf */
+  if (hs->req == NULL) {
+    LWIP_DEBUGF(HTTPD_DEBUG, ("First pbuf\n"));
+    hs->req = p;
+  } else {
+    LWIP_DEBUGF(HTTPD_DEBUG, ("pbuf enqueued\n"));
+    pbuf_cat(hs->req, p);
+  }
+
+  if (hs->req->next != NULL) {
+    data_len = LWIP_MIN(hs->req->tot_len, LWIP_HTTPD_MAX_REQ_LENGTH);
+    pbuf_copy_partial(hs->req, httpd_req_buf, data_len, 0);
+    data = httpd_req_buf;
+  } else
+#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
+  {
+    data = (char *)p->payload;
+    data_len = p->len;
+    if (p->len != p->tot_len) {
+      LWIP_DEBUGF(HTTPD_DEBUG, ("Warning: incomplete header due to chained pbufs\n"));
+    }
+  }
+
+  /* received enough data for minimal request? */
+  if (data_len >= MIN_REQ_LEN) {
+    /* wait for CRLF before parsing anything */
+    crlf = strnstr(data, CRLF, data_len);
+    if (crlf != NULL) {
+#if LWIP_HTTPD_SUPPORT_POST
+      int is_post = 0;
+#endif /* LWIP_HTTPD_SUPPORT_POST */
+      int is_09 = 0;
+      char *sp1, *sp2;
+      u16_t left_len, uri_len;
+      LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("CRLF received, parsing request\n"));
+      /* parse method */
+      if (!strncmp(data, "GET ", 4)) {
+        sp1 = data + 3;
+        /* received GET request */
+        LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Received GET request\"\n"));
+#if LWIP_HTTPD_SUPPORT_POST
+      } else if (!strncmp(data, "POST ", 5)) {
+        /* store request type */
+        is_post = 1;
+        sp1 = data + 4;
+        /* received GET request */
+        LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Received POST request\n"));
+#endif /* LWIP_HTTPD_SUPPORT_POST */
+      } else {
+        /* null-terminate the METHOD (pbuf is freed anyway wen returning) */
+        data[4] = 0;
+        /* unsupported method! */
+        LWIP_DEBUGF(HTTPD_DEBUG, ("Unsupported request method (not implemented): \"%s\"\n",
+          data));
+        return http_find_error_file(hs, 501);
+      }
+      /* if we come here, method is OK, parse URI */
+      left_len = data_len - ((sp1 +1) - data);
+      sp2 = strnstr(sp1 + 1, " ", left_len);
+#if LWIP_HTTPD_SUPPORT_V09
+      if (sp2 == NULL) {
+        /* HTTP 0.9: respond with correct protocol version */
+        sp2 = strnstr(sp1 + 1, CRLF, left_len);
+        is_09 = 1;
+#if LWIP_HTTPD_SUPPORT_POST
+        if (is_post) {
+          /* HTTP/0.9 does not support POST */
+          goto badrequest;
+        }
+#endif /* LWIP_HTTPD_SUPPORT_POST */
+      }
+#endif /* LWIP_HTTPD_SUPPORT_V09 */
+      uri_len = sp2 - (sp1 + 1);
+      if ((sp2 != 0) && (sp2 > sp1)) {
+        char *uri = sp1 + 1;
+        /* null-terminate the METHOD (pbuf is freed anyway wen returning) */
+        *sp1 = 0;
+        uri[uri_len] = 0;
+        LWIP_DEBUGF(HTTPD_DEBUG, ("Received \"%s\" request for URI: \"%s\"\n",
+                    data, uri));
+#if LWIP_HTTPD_SUPPORT_POST
+        if (is_post) {
+#if LWIP_HTTPD_SUPPORT_REQUESTLIST
+          struct pbuf **q = &hs->req;
+#else /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
+          struct pbuf **q = inp;
+#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
+          err = http_post_request(pcb, q, hs, data, data_len, uri, sp2);
+          if (err != ERR_OK) {
+            /* restore header for next try */
+            *sp1 = ' ';
+            *sp2 = ' ';
+            uri[uri_len] = ' ';
+          }
+          if (err == ERR_ARG) {
+            goto badrequest;
+          }
+          return err;
+        } else
+#endif /* LWIP_HTTPD_SUPPORT_POST */
+        {
+          return http_find_file(hs, uri, is_09);
+        }
+      } else {
+        LWIP_DEBUGF(HTTPD_DEBUG, ("invalid URI\n"));
+      }
+    }
+  }
+
+#if LWIP_HTTPD_SUPPORT_REQUESTLIST
+  clen = pbuf_clen(hs->req);
+  if ((hs->req->tot_len <= LWIP_HTTPD_REQ_BUFSIZE) &&
+    (clen <= LWIP_HTTPD_REQ_QUEUELEN)) {
+    /* request not fully received (too short or CRLF is missing) */
+    return ERR_INPROGRESS;
+  } else
+#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
+  {
+#if LWIP_HTTPD_SUPPORT_POST
+badrequest:
+#endif /* LWIP_HTTPD_SUPPORT_POST */
+    LWIP_DEBUGF(HTTPD_DEBUG, ("bad request\n"));
+    /* could not parse request */
+    return http_find_error_file(hs, 400);
+  }
+}
+
+/** Try to find the file specified by uri and, if found, initialize hs
+ * accordingly.
+ *
+ * @param hs the connection state
+ * @param uri the HTTP header URI
+ * @param is_09 1 if the request is HTTP/0.9 (no HTTP headers in response)
+ * @return ERR_OK if file was found and hs has been initialized correctly
+ *         another err_t otherwise
+ */
+static err_t
+http_find_file(struct http_state *hs, const char *uri, int is_09)
+{
+  size_t loop;
+  struct fs_file *file = NULL;
+  char *params;
+#if LWIP_HTTPD_CGI
+  int i;
+  int count;
+#endif /* LWIP_HTTPD_CGI */
+
+#if LWIP_HTTPD_SSI
+  /*
+   * By default, assume we will not be processing server-side-includes
+   * tags
+   */
+  hs->tag_check = false;
+#endif /* LWIP_HTTPD_SSI */
+
+  /* Have we been asked for the default root file? */
+  if((uri[0] == '/') &&  (uri[1] == 0)) {
+    /* Try each of the configured default filenames until we find one
+       that exists. */
+    for (loop = 0; loop < NUM_DEFAULT_FILENAMES; loop++) {
+      LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Looking for %s...\n", g_psDefaultFilenames[loop].name));
+      file = fs_open((char *)g_psDefaultFilenames[loop].name);
+      uri = (char *)g_psDefaultFilenames[loop].name;
+      if(file != NULL) {
+        LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Opened.\n"));
+#if LWIP_HTTPD_SSI
+        hs->tag_check = g_psDefaultFilenames[loop].shtml;
+#endif /* LWIP_HTTPD_SSI */
+        break;
+      }
+    }
+    if (file == NULL) {
+      /* None of the default filenames exist so send back a 404 page */
+      file = http_get_404_file(&uri);
+#if LWIP_HTTPD_SSI
+      hs->tag_check = false;
+#endif /* LWIP_HTTPD_SSI */
+    }
+  } else {
+    /* No - we've been asked for a specific file. */
+    /* First, isolate the base URI (without any parameters) */
+    params = (char *)strchr(uri, '?');
+    if (params != NULL) {
+      /* URI contains parameters. NULL-terminate the base URI */
+      *params = '\0';
+      params++;
+    }
+
+#if LWIP_HTTPD_CGI
+    /* Does the base URI we have isolated correspond to a CGI handler? */
+    if (g_iNumCGIs && g_pCGIs) {
+      for (i = 0; i < g_iNumCGIs; i++) {
+        if (strcmp(uri, g_pCGIs[i].pcCGIName) == 0) {
+          /*
+           * We found a CGI that handles this URI so extract the
+           * parameters and call the handler.
+           */
+           count = extract_uri_parameters(hs, params);
+           uri = g_pCGIs[i].pfnCGIHandler(i, count, hs->params,
+                                          hs->param_vals);
+           break;
+        }
+      }
+    }
+#endif /* LWIP_HTTPD_CGI */
+
+    LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Opening %s\n", uri));
+
+    file = fs_open(uri);
+    if (file == NULL) {
+      file = http_get_404_file(&uri);
+    }
+#if LWIP_HTTPD_SSI
+    if (file != NULL) {
+      /*
+       * See if we have been asked for an shtml file and, if so,
+       * enable tag checking.
+       */
+      hs->tag_check = false;
+      for (loop = 0; loop < NUM_SHTML_EXTENSIONS; loop++) {
+        if (strstr(uri, g_pcSSIExtensions[loop])) {
+          hs->tag_check = true;
+          break;
+        }
+      }
+    }
+#endif /* LWIP_HTTPD_SSI */
+  }
+  return http_init_file(hs, file, is_09, uri);
+}
+
+/** Initialize a http connection with a file to send (if found).
+ * Called by http_find_file and http_find_error_file.
+ *
+ * @param hs http connection state
+ * @param file file structure to send (or NULL if not found)
+ * @param is_09 1 if the request is HTTP/0.9 (no HTTP headers in response)
+ * @param uri the HTTP header URI
+ * @return ERR_OK if file was found and hs has been initialized correctly
+ *         another err_t otherwise
+ */
+static err_t
+http_init_file(struct http_state *hs, struct fs_file *file, int is_09, const char *uri)
+{
+  if (file != NULL) {
+    /* file opened, initialise struct http_state */
+#if LWIP_HTTPD_SSI
+    hs->tag_index = 0;
+    hs->tag_state = TAG_NONE;
+    hs->parsed = file->data;
+    hs->parse_left = file->len;
+    hs->tag_end = file->data;
+#endif /* LWIP_HTTPD_SSI */
+    hs->handle = file;
+    hs->file = (char*)file->data;
+    LWIP_ASSERT("File length must be positive!", (file->len >= 0));
+    hs->left = file->len;
+    hs->retries = 0;
+#if LWIP_HTTPD_TIMING
+    hs->time_started = sys_now();
+#endif /* LWIP_HTTPD_TIMING */
+#if !LWIP_HTTPD_DYNAMIC_HEADERS
+    LWIP_ASSERT("HTTP headers not included in file system", hs->handle->http_header_included);
+#endif /* !LWIP_HTTPD_DYNAMIC_HEADERS */
+#if LWIP_HTTPD_SUPPORT_V09
+    if (hs->handle->http_header_included && is_09) {
+      /* HTTP/0.9 responses are sent without HTTP header,
+         search for the end of the header. */
+      char *file_start = strnstr(hs->file, CRLF CRLF, hs->left);
+      if (file_start != NULL) {
+        size_t diff = file_start + 4 - hs->file;
+        hs->file += diff;
+        hs->left -= (u32_t)diff;
+      }
+    }
+#endif /* LWIP_HTTPD_SUPPORT_V09*/
+  } else {
+    hs->handle = NULL;
+    hs->file = NULL;
+    hs->left = 0;
+    hs->retries = 0;
+  }
+#if LWIP_HTTPD_DYNAMIC_HEADERS
+    /* Determine the HTTP headers to send based on the file extension of
+   * the requested URI. */
+  if ((hs->handle == NULL) || !hs->handle->http_header_included) {
+    get_http_headers(hs, (char*)uri);
+  }
+#else /* LWIP_HTTPD_DYNAMIC_HEADERS */
+  LWIP_UNUSED_ARG(uri);
+#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
+  return ERR_OK;
+}
+
+/**
+ * The pcb had an error and is already deallocated.
+ * The argument might still be valid (if != NULL).
+ */
+static void
+http_err(void *arg, err_t err)
+{
+  struct http_state *hs = (struct http_state *)arg;
+  LWIP_UNUSED_ARG(err);
+
+  LWIP_DEBUGF(HTTPD_DEBUG, ("http_err: %s", lwip_strerr(err)));
+
+  if (hs != NULL) {
+    http_state_free(hs);
+  }
+}
+
+/**
+ * Data has been sent and acknowledged by the remote host.
+ * This means that more data can be sent.
+ */
+static err_t
+http_sent(void *arg, struct tcp_pcb *pcb, u16_t len)
+{
+  struct http_state *hs = (struct http_state *)arg;
+
+  LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_sent %p\n", (void*)pcb));
+
+  LWIP_UNUSED_ARG(len);
+
+  if (hs == NULL) {
+    return ERR_OK;
+  }
+
+  hs->retries = 0;
+
+  http_send_data(pcb, hs);
+
+  return ERR_OK;
+}
+
+/**
+ * The poll function is called every 2nd second.
+ * If there has been no data sent (which resets the retries) in 8 seconds, close.
+ * If the last portion of a file has not been sent in 2 seconds, close.
+ *
+ * This could be increased, but we don't want to waste resources for bad connections.
+ */
+static err_t
+http_poll(void *arg, struct tcp_pcb *pcb)
+{
+  struct http_state *hs = (struct http_state *)arg;
+  LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_poll: pcb=%p hs=%p pcb_state=%s\n",
+    (void*)pcb, (void*)hs, tcp_debug_state_str(pcb->state)));
+
+  if (hs == NULL) {
+    err_t closed;
+    /* arg is null, close. */
+    LWIP_DEBUGF(HTTPD_DEBUG, ("http_poll: arg is NULL, close\n"));
+    closed = http_close_conn(pcb, hs);
+    LWIP_UNUSED_ARG(closed);
+#if LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR
+    if (closed == ERR_MEM) {
+       tcp_abort(pcb);
+       return ERR_ABRT;
+    }
+#endif /* LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR */
+    return ERR_OK;
+  } else {
+    hs->retries++;
+    if (hs->retries == HTTPD_MAX_RETRIES) {
+      LWIP_DEBUGF(HTTPD_DEBUG, ("http_poll: too many retries, close\n"));
+      http_close_conn(pcb, hs);
+      return ERR_OK;
+    }
+
+    /* If this connection has a file open, try to send some more data. If
+     * it has not yet received a GET request, don't do this since it will
+     * cause the connection to close immediately. */
+    if(hs && (hs->handle)) {
+      LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_poll: try to send more data\n"));
+      if(http_send_data(pcb, hs)) {
+        /* If we wrote anything to be sent, go ahead and send it now. */
+        LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("tcp_output\n"));
+        tcp_output(pcb);
+      }
+    }
+  }
+
+  return ERR_OK;
+}
+
+/**
+ * Data has been received on this pcb.
+ * For HTTP 1.0, this should normally only happen once (if the request fits in one packet).
+ */
+static err_t
+http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  err_t parsed = ERR_ABRT;
+  struct http_state *hs = (struct http_state *)arg;
+  LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_recv: pcb=%p pbuf=%p err=%s\n", (void*)pcb,
+    (void*)p, lwip_strerr(err)));
+
+  if ((err != ERR_OK) || (p == NULL) || (hs == NULL)) {
+    /* error or closed by other side? */
+    if (p != NULL) {
+      /* Inform TCP that we have taken the data. */
+      tcp_recved(pcb, p->tot_len);
+      pbuf_free(p);
+    }
+    if (hs == NULL) {
+      /* this should not happen, only to be robust */
+      LWIP_DEBUGF(HTTPD_DEBUG, ("Error, http_recv: hs is NULL, close\n"));
+    }
+    http_close_conn(pcb, hs);
+    return ERR_OK;
+  }
+
+#if LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND
+  if (hs->no_auto_wnd) {
+     hs->unrecved_bytes += p->tot_len;
+  } else
+#endif /* LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND */
+  {
+    /* Inform TCP that we have taken the data. */
+    tcp_recved(pcb, p->tot_len);
+  }
+
+#if LWIP_HTTPD_SUPPORT_POST
+  if (hs->post_content_len_left > 0) {
+    /* reset idle counter when POST data is received */
+    hs->retries = 0;
+    /* this is data for a POST, pass the complete pbuf to the application */
+    http_post_rxpbuf(hs, p);
+    /* pbuf is passed to the application, don't free it! */
+    if (hs->post_content_len_left == 0) {
+      /* all data received, send response or close connection */
+      http_send_data(pcb, hs);
+    }
+    return ERR_OK;
+  } else
+#endif /* LWIP_HTTPD_SUPPORT_POST */
+  {
+    if (hs->handle == NULL) {
+      parsed = http_parse_request(&p, hs, pcb);
+      LWIP_ASSERT("http_parse_request: unexpected return value", parsed == ERR_OK
+        || parsed == ERR_INPROGRESS ||parsed == ERR_ARG || parsed == ERR_USE);
+    } else {
+      LWIP_DEBUGF(HTTPD_DEBUG, ("http_recv: already sending data\n"));
+    }
+#if LWIP_HTTPD_SUPPORT_REQUESTLIST
+    if (parsed != ERR_INPROGRESS) {
+      /* request fully parsed or error */
+      if (hs->req != NULL) {
+        pbuf_free(hs->req);
+        hs->req = NULL;
+      }
+    }
+#else /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
+    if (p != NULL) {
+      /* pbuf not passed to application, free it now */
+      pbuf_free(p);
+    }
+#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
+    if (parsed == ERR_OK) {
+#if LWIP_HTTPD_SUPPORT_POST
+      if (hs->post_content_len_left == 0)
+#endif /* LWIP_HTTPD_SUPPORT_POST */
+      {
+        LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_recv: data %p len %"S32_F"\n", hs->file, hs->left));
+        http_send_data(pcb, hs);
+      }
+    } else if (parsed == ERR_ARG) {
+      /* @todo: close on ERR_USE? */
+      http_close_conn(pcb, hs);
+    }
+  }
+  return ERR_OK;
+}
+
+/**
+ * A new incoming connection has been accepted.
+ */
+static err_t
+http_accept(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  struct http_state *hs;
+  struct tcp_pcb_listen *lpcb = (struct tcp_pcb_listen*)arg;
+  LWIP_UNUSED_ARG(err);
+  LWIP_DEBUGF(HTTPD_DEBUG, ("http_accept %p / %p\n", (void*)pcb, arg));
+
+  /* Decrease the listen backlog counter */
+  tcp_accepted(lpcb);
+  /* Set priority */
+  tcp_setprio(pcb, HTTPD_TCP_PRIO);
+
+  /* Allocate memory for the structure that holds the state of the
+     connection - initialized by that function. */
+  hs = http_state_alloc();
+  if (hs == NULL) {
+    LWIP_DEBUGF(HTTPD_DEBUG, ("http_accept: Out of memory, RST\n"));
+    return ERR_MEM;
+  }
+
+  /* Tell TCP that this is the structure we wish to be passed for our
+     callbacks. */
+  tcp_nagle_disable(pcb);//_RB_
+  tcp_arg(pcb, hs);
+
+  /* Set up the various callback functions */
+  tcp_recv(pcb, http_recv);
+  tcp_err(pcb, http_err);
+  tcp_poll(pcb, http_poll, HTTPD_POLL_INTERVAL);
+  tcp_sent(pcb, http_sent);
+
+  return ERR_OK;
+}
+
+/**
+ * Initialize the httpd with the specified local address.
+ */
+static void
+httpd_init_addr(ip_addr_t *local_addr)
+{
+  struct tcp_pcb *pcb;
+  err_t err;
+
+  pcb = tcp_new();
+  LWIP_ASSERT("httpd_init: tcp_new failed", pcb != NULL);
+  tcp_setprio(pcb, HTTPD_TCP_PRIO);
+  /* set SOF_REUSEADDR here to explicitly bind httpd to multiple interfaces */
+  err = tcp_bind(pcb, local_addr, HTTPD_SERVER_PORT);
+  LWIP_ASSERT("httpd_init: tcp_bind failed", err == ERR_OK);
+  pcb = tcp_listen(pcb);
+  LWIP_ASSERT("httpd_init: tcp_listen failed", pcb != NULL);
+  /* initialize callback arg and accept callback */
+  tcp_arg(pcb, pcb);
+  tcp_accept(pcb, http_accept);
+}
+
+/**
+ * Initialize the httpd: set up a listening PCB and bind it to the defined port
+ */
+void
+httpd_init(void)
+{
+#if HTTPD_USE_MEM_POOL
+  LWIP_ASSERT("memp_sizes[MEMP_HTTPD_STATE] >= sizeof(http_state)",
+     memp_sizes[MEMP_HTTPD_STATE] >= sizeof(http_state));
+#endif
+  LWIP_DEBUGF(HTTPD_DEBUG, ("httpd_init\n"));
+
+  httpd_init_addr(IP_ADDR_ANY);
+}
+
+#if LWIP_HTTPD_SSI
+/**
+ * Set the SSI handler function.
+ *
+ * @param ssi_handler the SSI handler function
+ * @param tags an array of SSI tag strings to search for in SSI-enabled files
+ * @param num_tags number of tags in the 'tags' array
+ */
+void
+http_set_ssi_handler(tSSIHandler ssi_handler, const char **tags, int num_tags)
+{
+  LWIP_DEBUGF(HTTPD_DEBUG, ("http_set_ssi_handler\n"));
+
+  LWIP_ASSERT("no ssi_handler given", ssi_handler != NULL);
+  LWIP_ASSERT("no tags given", tags != NULL);
+  LWIP_ASSERT("invalid number of tags", num_tags > 0);
+
+  g_pfnSSIHandler = ssi_handler;
+  g_ppcTags = tags;
+  g_iNumTags = num_tags;
+}
+#endif /* LWIP_HTTPD_SSI */
+
+#if LWIP_HTTPD_CGI
+/**
+ * Set an array of CGI filenames/handler functions
+ *
+ * @param cgis an array of CGI filenames/handler functions
+ * @param num_handlers number of elements in the 'cgis' array
+ */
+void
+http_set_cgi_handlers(const tCGI *cgis, int num_handlers)
+{
+  LWIP_ASSERT("no cgis given", cgis != NULL);
+  LWIP_ASSERT("invalid number of handlers", num_handlers > 0);
+  
+  g_pCGIs = cgis;
+  g_iNumCGIs = num_handlers;
+}
+#endif /* LWIP_HTTPD_CGI */
+
+#endif /* LWIP_TCP */

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/httpd.h b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/httpd.h
new file mode 100644 (file)
index 0000000..8c3c03d
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/httpd.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ * This version of the file has been modified by Texas Instruments to offer
+ * simple server-side-include (SSI) and Common Gateway Interface (CGI)
+ * capability.
+ */
+
+#ifndef __HTTPD_H__
+#define __HTTPD_H__
+
+#include "lwip/opt.h"
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+
+
+/** Set this to 1 to support CGI */
+#ifndef LWIP_HTTPD_CGI
+#define LWIP_HTTPD_CGI            0
+#endif
+
+/** Set this to 1 to support SSI (Server-Side-Includes) */
+#ifndef LWIP_HTTPD_SSI
+#define LWIP_HTTPD_SSI            1     
+#endif
+
+/** Set this to 1 to support HTTP POST */
+#ifndef LWIP_HTTPD_SUPPORT_POST
+#define LWIP_HTTPD_SUPPORT_POST   0
+#endif
+
+
+#if LWIP_HTTPD_CGI
+
+/*
+ * Function pointer for a CGI script handler.
+ *
+ * This function is called each time the HTTPD server is asked for a file
+ * whose name was previously registered as a CGI function using a call to
+ * http_set_cgi_handler. The iIndex parameter provides the index of the
+ * CGI within the ppcURLs array passed to http_set_cgi_handler. Parameters
+ * pcParam and pcValue provide access to the parameters provided along with
+ * the URI. iNumParams provides a count of the entries in the pcParam and
+ * pcValue arrays. Each entry in the pcParam array contains the name of a
+ * parameter with the corresponding entry in the pcValue array containing the
+ * value for that parameter. Note that pcParam may contain multiple elements
+ * with the same name if, for example, a multi-selection list control is used
+ * in the form generating the data.
+ *
+ * The function should return a pointer to a character string which is the
+ * path and filename of the response that is to be sent to the connected
+ * browser, for example "/thanks.htm" or "/response/error.ssi".
+ *
+ * The maximum number of parameters that will be passed to this function via
+ * iNumParams is defined by LWIP_HTTPD_MAX_CGI_PARAMETERS. Any parameters in the incoming
+ * HTTP request above this number will be discarded.
+ *
+ * Requests intended for use by this CGI mechanism must be sent using the GET
+ * method (which encodes all parameters within the URI rather than in a block
+ * later in the request). Attempts to use the POST method will result in the
+ * request being ignored.
+ *
+ */
+typedef const char *(*tCGIHandler)(int iIndex, int iNumParams, char *pcParam[],
+                             char *pcValue[]);
+
+/*
+ * Structure defining the base filename (URL) of a CGI and the associated
+ * function which is to be called when that URL is requested.
+ */
+typedef struct
+{
+    const char *pcCGIName;
+    tCGIHandler pfnCGIHandler;
+} tCGI;
+
+void http_set_cgi_handlers(const tCGI *pCGIs, int iNumHandlers);
+
+
+/* The maximum number of parameters that the CGI handler can be sent. */
+#ifndef LWIP_HTTPD_MAX_CGI_PARAMETERS
+#define LWIP_HTTPD_MAX_CGI_PARAMETERS 16
+#endif
+
+#endif /* LWIP_HTTPD_CGI */
+
+#if LWIP_HTTPD_SSI
+
+/** LWIP_HTTPD_SSI_MULTIPART==1: SSI handler function is called with 2 more
+ * arguments indicating a counter for insert string that are too long to be
+ * inserted at once: the SSI handler function must then set 'next_tag_part'
+ * which will be passed back to it in the next call. */
+#ifndef LWIP_HTTPD_SSI_MULTIPART
+#define LWIP_HTTPD_SSI_MULTIPART    0
+#endif
+
+/*
+ * Function pointer for the SSI tag handler callback.
+ *
+ * This function will be called each time the HTTPD server detects a tag of the
+ * form <!--#name--> in a .shtml, .ssi or .shtm file where "name" appears as
+ * one of the tags supplied to http_set_ssi_handler in the ppcTags array.  The
+ * returned insert string, which will be appended after the the string
+ * "<!--#name-->" in file sent back to the client,should be written to pointer
+ * pcInsert.  iInsertLen contains the size of the buffer pointed to by
+ * pcInsert.  The iIndex parameter provides the zero-based index of the tag as
+ * found in the ppcTags array and identifies the tag that is to be processed.
+ *
+ * The handler returns the number of characters written to pcInsert excluding
+ * any terminating NULL or a negative number to indicate a failure (tag not
+ * recognized, for example).
+ *
+ * Note that the behavior of this SSI mechanism is somewhat different from the
+ * "normal" SSI processing as found in, for example, the Apache web server.  In
+ * this case, the inserted text is appended following the SSI tag rather than
+ * replacing the tag entirely.  This allows for an implementation that does not
+ * require significant additional buffering of output data yet which will still
+ * offer usable SSI functionality.  One downside to this approach is when
+ * attempting to use SSI within JavaScript.  The SSI tag is structured to
+ * resemble an HTML comment but this syntax does not constitute a comment
+ * within JavaScript and, hence, leaving the tag in place will result in
+ * problems in these cases.  To work around this, any SSI tag which needs to
+ * output JavaScript code must do so in an encapsulated way, sending the whole
+ * HTML <script>...</script> section as a single include.
+ */
+typedef u16_t (*tSSIHandler)(int iIndex, char *pcInsert, int iInsertLen
+#if LWIP_HTTPD_SSI_MULTIPART
+                             , u16_t current_tag_part, u16_t *next_tag_part
+#endif /* LWIP_HTTPD_SSI_MULTIPART */
+#if LWIP_HTTPD_FILE_STATE
+                             , void *connection_state
+#endif /* LWIP_HTTPD_FILE_STATE */
+                             );
+
+void http_set_ssi_handler(tSSIHandler pfnSSIHandler,
+                          const char **ppcTags, int iNumTags);
+
+/* The maximum length of the string comprising the tag name */
+#ifndef LWIP_HTTPD_MAX_TAG_NAME_LEN
+#define LWIP_HTTPD_MAX_TAG_NAME_LEN 8
+#endif
+
+/* The maximum length of string that can be returned to replace any given tag */
+#ifndef LWIP_HTTPD_MAX_TAG_INSERT_LEN
+#define LWIP_HTTPD_MAX_TAG_INSERT_LEN 192
+#endif
+
+#endif /* LWIP_HTTPD_SSI */
+
+#if LWIP_HTTPD_SUPPORT_POST
+
+/* These functions must be implemented by the application */
+
+/** Called when a POST request has been received. The application can decide
+ * whether to accept it or not.
+ *
+ * @param connection Unique connection identifier, valid until httpd_post_end
+ *        is called.
+ * @param uri The HTTP header URI receiving the POST request.
+ * @param http_request The raw HTTP request (the first packet, normally).
+ * @param http_request_len Size of 'http_request'.
+ * @param content_len Content-Length from HTTP header.
+ * @param response_uri Filename of response file, to be filled when denying the
+ *        request
+ * @param response_uri_len Size of the 'response_uri' buffer.
+ * @param post_auto_wnd Set this to 0 to let the callback code handle window
+ *        updates by calling 'httpd_post_data_recved' (to throttle rx speed)
+ *        default is 1 (httpd handles window updates automatically)
+ * @return ERR_OK: Accept the POST request, data may be passed in
+ *         another err_t: Deny the POST request, send back 'bad request'.
+ */
+err_t httpd_post_begin(void *connection, const char *uri, const char *http_request,
+                       u16_t http_request_len, int content_len, char *response_uri,
+                       u16_t response_uri_len, u8_t *post_auto_wnd);
+
+/** Called for each pbuf of data that has been received for a POST.
+ * ATTENTION: The application is responsible for freeing the pbufs passed in!
+ *
+ * @param connection Unique connection identifier.
+ * @param p Received data.
+ * @return ERR_OK: Data accepted.
+ *         another err_t: Data denied, http_post_get_response_uri will be called.
+ */
+err_t httpd_post_receive_data(void *connection, struct pbuf *p);
+
+/** Called when all data is received or when the connection is closed.
+ * The application must return the filename/URI of a file to send in response
+ * to this POST request. If the response_uri buffer is untouched, a 404
+ * response is returned.
+ *
+ * @param connection Unique connection identifier.
+ * @param response_uri Filename of response file, to be filled when denying the request
+ * @param response_uri_len Size of the 'response_uri' buffer.
+ */
+void httpd_post_finished(void *connection, char *response_uri, u16_t response_uri_len);
+
+#ifndef LWIP_HTTPD_POST_MANUAL_WND
+#define LWIP_HTTPD_POST_MANUAL_WND  0
+#endif
+
+#if LWIP_HTTPD_POST_MANUAL_WND
+void httpd_post_data_recved(void *connection, u16_t recved_len);
+#endif /* LWIP_HTTPD_POST_MANUAL_WND */
+
+#endif /* LWIP_HTTPD_SUPPORT_POST */
+
+void httpd_init(void);
+
+#endif /* __HTTPD_H__ */

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/httpd_structs.h b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/httpd_structs.h
new file mode 100644 (file)
index 0000000..1080a55
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/httpd_structs.h
@@ -0,0 +1,115 @@
+#ifndef __HTTPD_STRUCTS_H__
+#define __HTTPD_STRUCTS_H__
+
+#include "httpd.h"
+
+/** This string is passed in the HTTP header as "Server: " */
+#ifndef HTTPD_SERVER_AGENT
+#define HTTPD_SERVER_AGENT "lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip)"
+#endif
+
+/** Set this to 1 if you want to include code that creates HTTP headers
+ * at runtime. Default is off: HTTP headers are then created statically
+ * by the makefsdata tool. Static headers mean smaller code size, but
+ * the (readonly) fsdata will grow a bit as every file includes the HTTP
+ * header. */
+#ifndef LWIP_HTTPD_DYNAMIC_HEADERS
+#define LWIP_HTTPD_DYNAMIC_HEADERS 0
+#endif
+
+
+#if LWIP_HTTPD_DYNAMIC_HEADERS
+/** This struct is used for a list of HTTP header strings for various
+ * filename extensions. */
+typedef struct
+{
+  const char *extension;
+  int headerIndex;
+} tHTTPHeader;
+
+/** A list of strings used in HTTP headers */
+static const char * const g_psHTTPHeaderStrings[] =
+{
+ "Content-type: text/html\r\n\r\n",
+ "Content-type: text/html\r\nExpires: Fri, 10 Apr 2008 14:00:00 GMT\r\nPragma: no-cache\r\n\r\n",
+ "Content-type: image/gif\r\n\r\n",
+ "Content-type: image/png\r\n\r\n",
+ "Content-type: image/jpeg\r\n\r\n",
+ "Content-type: image/bmp\r\n\r\n",
+ "Content-type: image/x-icon\r\n\r\n",
+ "Content-type: application/octet-stream\r\n\r\n",
+ "Content-type: application/x-javascript\r\n\r\n",
+ "Content-type: application/x-javascript\r\n\r\n",
+ "Content-type: text/css\r\n\r\n",
+ "Content-type: application/x-shockwave-flash\r\n\r\n",
+ "Content-type: text/xml\r\n\r\n",
+ "Content-type: text/plain\r\n\r\n",
+ "HTTP/1.0 200 OK\r\n",
+ "HTTP/1.0 404 File not found\r\n",
+ "HTTP/1.0 400 Bad Request\r\n",
+ "HTTP/1.0 501 Not Implemented\r\n",
+ "HTTP/1.1 200 OK\r\n",
+ "HTTP/1.1 404 File not found\r\n",
+ "HTTP/1.1 400 Bad Request\r\n",
+ "HTTP/1.1 501 Not Implemented\r\n",
+ "Content-Length: ",
+ "Connection: Close\r\n",
+ "Server: "HTTPD_SERVER_AGENT"\r\n",
+ "\r\n<html><body><h2>404: The requested file cannot be found.</h2></body></html>\r\n"
+};
+
+/* Indexes into the g_psHTTPHeaderStrings array */
+#define HTTP_HDR_HTML           0  /* text/html */
+#define HTTP_HDR_SSI            1  /* text/html Expires... */
+#define HTTP_HDR_GIF            2  /* image/gif */
+#define HTTP_HDR_PNG            3  /* image/png */
+#define HTTP_HDR_JPG            4  /* image/jpeg */
+#define HTTP_HDR_BMP            5  /* image/bmp */
+#define HTTP_HDR_ICO            6  /* image/x-icon */
+#define HTTP_HDR_APP            7  /* application/octet-stream */
+#define HTTP_HDR_JS             8  /* application/x-javascript */
+#define HTTP_HDR_RA             9  /* application/x-javascript */
+#define HTTP_HDR_CSS            10 /* text/css */
+#define HTTP_HDR_SWF            11 /* application/x-shockwave-flash */
+#define HTTP_HDR_XML            12 /* text/xml */
+#define HTTP_HDR_DEFAULT_TYPE   13 /* text/plain */
+#define HTTP_HDR_OK             14 /* 200 OK */
+#define HTTP_HDR_NOT_FOUND      15 /* 404 File not found */
+#define HTTP_HDR_BAD_REQUEST    16 /* 400 Bad request */
+#define HTTP_HDR_NOT_IMPL       17 /* 501 Not Implemented */
+#define HTTP_HDR_OK_11          18 /* 200 OK */
+#define HTTP_HDR_NOT_FOUND_11   19 /* 404 File not found */
+#define HTTP_HDR_BAD_REQUEST_11 20 /* 400 Bad request */
+#define HTTP_HDR_NOT_IMPL_11    21 /* 501 Not Implemented */
+#define HTTP_HDR_CONTENT_LENGTH 22 /* Content-Length: (HTTP 1.1)*/
+#define HTTP_HDR_CONN_CLOSE     23 /* Connection: Close (HTTP 1.1) */
+#define HTTP_HDR_SERVER         24 /* Server: HTTPD_SERVER_AGENT */
+#define DEFAULT_404_HTML        25 /* default 404 body */
+
+/** A list of extension-to-HTTP header strings */
+const static tHTTPHeader g_psHTTPHeaders[] =
+{
+ { "html", HTTP_HDR_HTML},
+ { "htm",  HTTP_HDR_HTML},
+ { "shtml",HTTP_HDR_SSI},
+ { "shtm", HTTP_HDR_SSI},
+ { "ssi",  HTTP_HDR_SSI},
+ { "gif",  HTTP_HDR_GIF},
+ { "png",  HTTP_HDR_PNG},
+ { "jpg",  HTTP_HDR_JPG},
+ { "bmp",  HTTP_HDR_BMP},
+ { "ico",  HTTP_HDR_ICO},
+ { "class",HTTP_HDR_APP},
+ { "cls",  HTTP_HDR_APP},
+ { "js",   HTTP_HDR_JS},
+ { "ram",  HTTP_HDR_RA},
+ { "css",  HTTP_HDR_CSS},
+ { "swf",  HTTP_HDR_SWF},
+ { "xml",  HTTP_HDR_XML}
+};
+
+#define NUM_HTTP_HEADERS (sizeof(g_psHTTPHeaders) / sizeof(tHTTPHeader))
+
+#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */
+
+#endif /* __HTTPD_STRUCTS_H__ */

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/fs/404.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/fs/404.html
new file mode 100644 (file)
index 0000000..40b343a
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/fs/404.html
@@ -0,0 +1,21 @@
+<html>
+<head><title>lwIP - A Lightweight TCP/IP Stack</title></head>
+<body bgcolor="white" text="black">
+
+    <table width="100%">
+      <tr valign="top"><td width="80">   
+         <a href="http://www.sics.se/"><img src="/img/sics.gif"
+         border="0" alt="SICS logo" title="SICS logo"></a>
+       </td><td width="500">     
+         <h1>lwIP - A Lightweight TCP/IP Stack</h1>
+         <h2>404 - Page not found</h2>
+         <p>
+           Sorry, the page you are requesting was not found on this
+           server. 
+         </p>
+       </td><td>
+         &nbsp;
+       </td></tr>
+      </table>
+</body>
+</html>

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/fs/index.shtml b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/fs/index.shtml
new file mode 100644 (file)
index 0000000..90358d1
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/fs/index.shtml
@@ -0,0 +1,20 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+  <head>\r
+    <title>FreeRTOS.org lwIP WEB server demo</title>\r
+  </head>\r
+  <BODY onLoad="window.setTimeout(&quot;location.href='index.shtml'&quot;,2000)">\r
+<font face="arial">\r
+<a href="index.shtml">Task Stats</a> <b>|</b> <a href="runtime.shtml">Run Time Stats</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS Homepage</a> <b>|</b> <a href="logo.jpg">37K jpg</a>\r
+<br><p>\r
+<hr>\r
+<br><p>\r
+<h2>Task statistics</h2>\r
+Page will refresh every 2 seconds.<p>\r
+<font face="courier"><pre>Task          State  Priority  Stack #<br>************************************************<br>\r
+<!--#rtos_stats-->\r
+</pre></font>\r
+</font>\r
+</body>\r
+</html>\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/fs/logo.jpg b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/fs/logo.jpg
new file mode 100644 (file)
index 0000000..d3670e4
Binary files /dev/null and b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/fs/logo.jpg differ

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/fs/runtime.shtml b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/fs/runtime.shtml
new file mode 100644 (file)
index 0000000..e66202b
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/fs/runtime.shtml
@@ -0,0 +1,20 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+  <head>\r
+    <title>FreeRTOS.org lwIP WEB server demo</title>\r
+  </head>\r
+  <BODY onLoad="window.setTimeout(&quot;location.href='runtime.shtml'&quot;,2000)">\r
+<font face="arial">\r
+<a href="index.shtml">Task Stats</a> <b>|</b> <a href="runtime.shtml">Run Time Stats</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS Homepage</a> <b>|</b> <a href="logo.jpg">37K jpg</a>\r
+<br><p>\r
+<hr>\r
+<br><p>\r
+<h2>Run-time statistics</h2>\r
+Page will refresh every 2 seconds.<p>\r
+<font face="courier"><pre>Task            Abs Time      % Time<br>****************************************<br>\r
+<!--#run_stats-->\r\r
+</pre></font>\r
+</font>\r
+</body>\r
+</html>\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/makefsdata.c-source-file b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/makefsdata.c-source-file
new file mode 100644 (file)
index 0000000..b065caa
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/makefsdata.c-source-file
@@ -0,0 +1,610 @@
+/**
+ * makefsdata: Converts a directory structure for use with the lwIP httpd.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Jim Pettinato
+ *         Simon Goldschmidt
+ *
+ * @todo:
+ * - take TCP_MSS, LWIP_TCP_TIMESTAMPS and
+ *   PAYLOAD_ALIGN_TYPE/PAYLOAD_ALIGNMENT as arguments
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#ifdef WIN32
+#define WIN32_LEAN_AND_MEAN
+#include "windows.h"
+#else
+#include <dir.h>
+#endif
+#include <dos.h>
+#include <string.h>
+
+/* Compatibility defines Win32 vs. DOS */
+#ifdef WIN32
+
+#define FIND_T                        WIN32_FIND_DATAA
+#define FIND_T_FILENAME(fInfo)        (fInfo.cFileName)
+#define FIND_T_IS_DIR(fInfo)          ((fInfo.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) != 0)
+#define FIND_T_IS_FILE(fInfo)         ((fInfo.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) == 0)
+#define FIND_RET_T                    HANDLE
+#define FINDFIRST_FILE(path, result)  FindFirstFileA(path, result)
+#define FINDFIRST_DIR(path, result)   FindFirstFileA(path, result)
+#define FINDNEXT(ff_res, result)      FindNextFileA(ff_res, result)
+#define FINDFIRST_SUCCEEDED(ret)      (ret != INVALID_HANDLE_VALUE)
+#define FINDNEXT_SUCCEEDED(ret)       (ret == TRUE)
+
+#define GETCWD(path, len)             GetCurrentDirectoryA(len, path)
+#define CHDIR(path)                   SetCurrentDirectoryA(path)
+
+#define NEWLINE     "\r\n"
+#define NEWLINE_LEN 2
+
+#else
+
+#define FIND_T                        struct fflbk
+#define FIND_T_FILENAME(fInfo)        (fInfo.ff_name)
+#define FIND_T_IS_DIR(fInfo)          ((fInfo.ff_attrib & FA_DIREC) == FA_DIREC)
+#define FIND_T_IS_FILE(fInfo)         (1)
+#define FIND_RET_T                    int
+#define FINDFIRST_FILE(path, result)  findfirst(path, result, FA_ARCH)
+#define FINDFIRST_DIR(path, result)   findfirst(path, result, FA_DIREC)
+#define FINDNEXT(ff_res, result)      FindNextFileA(ff_res, result)
+#define FINDFIRST_SUCCEEDED(ret)      (ret == 0)
+#define FINDNEXT_SUCCEEDED(ret)       (ret == 0)
+
+#define GETCWD(path, len)             getcwd(path, len)
+#define CHDIR(path)                   chdir(path)
+
+#endif
+
+/* define this to get the header variables we use to build HTTP headers */
+#define LWIP_HTTPD_DYNAMIC_HEADERS 1
+#include "../httpd_structs.h"
+
+#include "../../../lwip-1.4.0/src/core/ipv4/inet_chksum.c"
+#include "../../../lwip-1.4.0/src/core/def.c"
+
+/** (Your server name here) */
+const char *serverID = "Server: "HTTPD_SERVER_AGENT"\r\n";
+
+/* change this to suit your MEM_ALIGNMENT */
+#define PAYLOAD_ALIGNMENT 4
+/* set this to 0 to prevent aligning payload */
+#define ALIGN_PAYLOAD 1
+/* define this to a type that has the required alignment */
+#define PAYLOAD_ALIGN_TYPE "unsigned int"
+static int payload_alingment_dummy_counter = 0;
+
+#define HEX_BYTES_PER_LINE 16
+
+#define MAX_PATH_LEN 256
+
+#define COPY_BUFSIZE 10240
+
+int process_sub(FILE *data_file, FILE *struct_file);
+int process_file(FILE *data_file, FILE *struct_file, const char *filename);
+int file_write_http_header(FILE *data_file, const char *filename, int file_size,
+                           u16_t *http_hdr_len, u16_t *http_hdr_chksum);
+int file_put_ascii(FILE *file, const char *ascii_string, int len, int *i);
+int s_put_ascii(char *buf, const char *ascii_string, int len, int *i);
+void concat_files(const char *file1, const char *file2, const char *targetfile);
+
+static unsigned char file_buffer_raw[COPY_BUFSIZE];
+/* 5 bytes per char + 3 bytes per line */
+static char file_buffer_c[COPY_BUFSIZE * 5 + ((COPY_BUFSIZE / HEX_BYTES_PER_LINE) * 3)];
+
+char curSubdir[MAX_PATH_LEN];
+char lastFileVar[MAX_PATH_LEN];
+char hdr_buf[4096];
+
+unsigned char processSubs = 1;
+unsigned char includeHttpHeader = 1;
+unsigned char useHttp11 = 0;
+unsigned char precalcChksum = 0;
+
+int main(int argc, char *argv[])
+{
+  FIND_T fInfo;
+  FIND_RET_T fret;
+  char path[MAX_PATH_LEN];
+  char appPath[MAX_PATH_LEN];
+  FILE *data_file;
+  FILE *struct_file;
+  int filesProcessed;
+  int i;
+  char targetfile[MAX_PATH_LEN];
+  strcpy(targetfile, "fsdata.c");
+
+  memset(path, 0, sizeof(path));
+  memset(appPath, 0, sizeof(appPath));
+
+  printf(NEWLINE " makefsdata - HTML to C source converter" NEWLINE);
+  printf("     by Jim Pettinato               - circa 2003 " NEWLINE);
+  printf("     extended by Simon Goldschmidt  - 2009 " NEWLINE NEWLINE);
+
+  strcpy(path, "fs");
+  for(i = 1; i < argc; i++) {
+    if (argv[i][0] == '-') {
+      if (strstr(argv[i], "-s")) {
+        processSubs = 0;
+      } else if (strstr(argv[i], "-e")) {
+        includeHttpHeader = 0;
+      } else if (strstr(argv[i], "-11")) {
+        useHttp11 = 1;
+      } else if (strstr(argv[i], "-c")) {
+        precalcChksum = 1;
+      } else if((argv[i][1] == 'f') && (argv[i][2] == ':')) {
+        strcpy(targetfile, &argv[i][3]);
+        printf("Writing to file \"%s\"\n", targetfile);
+      }
+    } else {
+      strcpy(path, argv[i]);
+    }
+  }
+
+  /* if command line param or subdir named 'fs' not found spout usage verbiage */
+  fret = FINDFIRST_DIR(path, &fInfo);
+  if (!FINDFIRST_SUCCEEDED(fret)) {
+    /* if no subdir named 'fs' (or the one which was given) exists, spout usage verbiage */
+    printf(" Failed to open directory \"%s\"." NEWLINE NEWLINE, path);
+    printf(" Usage: htmlgen [targetdir] [-s] [-i] [-f:<filename>]" NEWLINE NEWLINE);
+    printf("   targetdir: relative or absolute path to files to convert" NEWLINE);
+    printf("   switch -s: toggle processing of subdirectories (default is on)" NEWLINE);
+    printf("   switch -e: exclude HTTP header from file (header is created at runtime, default is off)" NEWLINE);
+    printf("   switch -11: include HTTP 1.1 header (1.0 is default)" NEWLINE);
+    printf("   switch -c: precalculate checksums for all pages (default is off)" NEWLINE);
+    printf("   switch -f: target filename (default is \"fsdata.c\")" NEWLINE);
+    printf("   if targetdir not specified, htmlgen will attempt to" NEWLINE);
+    printf("   process files in subdirectory 'fs'" NEWLINE);
+    exit(-1);
+  }
+
+  printf("HTTP %sheader will %s statically included." NEWLINE,
+    (includeHttpHeader ? (useHttp11 ? "1.1 " : "1.0 ") : ""),
+    (includeHttpHeader ? "be" : "not be"));
+
+  sprintf(curSubdir, "");  /* start off in web page's root directory - relative paths */
+  printf("  Processing all files in directory %s", path);
+  if (processSubs) {
+    printf(" and subdirectories..." NEWLINE NEWLINE);
+  } else {
+    printf("..." NEWLINE NEWLINE);
+  }
+
+  GETCWD(appPath, MAX_PATH_LEN);
+  data_file = fopen("fsdata.tmp", "wb");
+  if (data_file == NULL) {
+    printf("Failed to create file \"fsdata.tmp\"\n");
+    exit(-1);
+  }
+  struct_file = fopen("fshdr.tmp", "wb");
+  if (struct_file == NULL) {
+    printf("Failed to create file \"fshdr.tmp\"\n");
+    exit(-1);
+  }
+
+  CHDIR(path);
+
+  fprintf(data_file, "#include \"fs.h\"" NEWLINE);
+  fprintf(data_file, "#include \"lwip/def.h\"" NEWLINE);
+  fprintf(data_file, "#include \"fsdata.h\"" NEWLINE NEWLINE NEWLINE);
+
+  fprintf(data_file, "#define file_NULL (struct fsdata_file *) NULL" NEWLINE NEWLINE NEWLINE);
+
+  sprintf(lastFileVar, "NULL");
+
+  filesProcessed = process_sub(data_file, struct_file);
+
+  /* data_file now contains all of the raw data.. now append linked list of
+   * file header structs to allow embedded app to search for a file name */
+  fprintf(data_file, NEWLINE NEWLINE);
+  fprintf(struct_file, "#define FS_ROOT file_%s" NEWLINE, lastFileVar);
+  fprintf(struct_file, "#define FS_NUMFILES %d" NEWLINE NEWLINE, filesProcessed);
+
+  fclose(data_file);
+  fclose(struct_file);
+
+  CHDIR(appPath);
+  /* append struct_file to data_file */
+  printf(NEWLINE "Creating target file..." NEWLINE NEWLINE);
+  concat_files("fsdata.tmp", "fshdr.tmp", targetfile);
+
+  /* if succeeded, delete the temporary files */
+  remove("fsdata.tmp");
+  remove("fshdr.tmp"); 
+
+  printf(NEWLINE "Processed %d files - done." NEWLINE NEWLINE, filesProcessed);
+
+  return 0;
+}
+
+static void copy_file(const char *filename_in, FILE *fout)
+{
+  FILE *fin;
+  size_t len;
+  fin = fopen(filename_in, "rb");
+  if (fin == NULL) {
+    printf("Failed to open file \"%s\"\n", filename_in);
+    exit(-1);
+  }
+
+  while((len = fread(file_buffer_raw, 1, COPY_BUFSIZE, fin)) > 0)
+  {
+    fwrite(file_buffer_raw, 1, len, fout);
+  }
+  fclose(fin);
+}
+
+void concat_files(const char *file1, const char *file2, const char *targetfile)
+{
+  FILE *fout;
+  fout = fopen(targetfile, "wb");
+  if (fout == NULL) {
+    printf("Failed to open file \"%s\"\n", targetfile);
+    exit(-1);
+  }
+  copy_file(file1, fout);
+  copy_file(file2, fout);
+  fclose(fout);
+}
+
+int process_sub(FILE *data_file, FILE *struct_file)
+{
+  FIND_T fInfo;
+  FIND_RET_T fret;
+  int filesProcessed = 0;
+  char oldSubdir[MAX_PATH_LEN];
+
+  if (processSubs) {
+    /* process subs recursively */
+    strcpy(oldSubdir, curSubdir);
+    fret = FINDFIRST_DIR("*", &fInfo);
+    if (FINDFIRST_SUCCEEDED(fret)) {
+      do {
+        const char *curName = FIND_T_FILENAME(fInfo);
+        if (curName == NULL) continue;
+        if (curName[0] == '.') continue;
+        if (strcmp(curName, "CVS") == 0) continue;
+        if (!FIND_T_IS_DIR(fInfo)) continue;
+        CHDIR(curName);
+        strcat(curSubdir, "/");
+        strcat(curSubdir, curName);
+        printf(NEWLINE "processing subdirectory %s/..." NEWLINE, curSubdir);
+        filesProcessed += process_sub(data_file, struct_file);
+        CHDIR("..");
+        strcpy(curSubdir, oldSubdir);
+      } while (FINDNEXT_SUCCEEDED(FINDNEXT(fret, &fInfo)));
+    }
+  }
+
+  fret = FINDFIRST_FILE("*.*", &fInfo);
+  if (FINDFIRST_SUCCEEDED(fret)) {
+    /* at least one file in directory */
+    do {
+      if (FIND_T_IS_FILE(fInfo)) {
+        const char *curName = FIND_T_FILENAME(fInfo);
+        printf("processing %s/%s..." NEWLINE, curSubdir, curName);
+        if (process_file(data_file, struct_file, curName) < 0) {
+          printf(NEWLINE "Error... aborting" NEWLINE);
+          return -1;
+        }
+        filesProcessed++;
+      }
+    } while (FINDNEXT_SUCCEEDED(FINDNEXT(fret, &fInfo)));
+  }
+  return filesProcessed;
+}
+
+int get_file_size(const char* filename)
+{
+  FILE *inFile;
+  int file_size = -1;
+  inFile = fopen(filename, "rb");
+  if (inFile == NULL) {
+    printf("Failed to open file \"%s\"\n", filename);
+    exit(-1);
+  }
+  fseek(inFile, 0, SEEK_END);
+  file_size = ftell(inFile);
+  fclose(inFile);
+  return file_size;
+}
+
+void process_file_data(const char *filename, FILE *data_file)
+{
+  FILE *source_file;
+  size_t len, written, i, src_off=0;
+
+  source_file = fopen(filename, "rb");
+
+  do {
+    size_t off = 0;
+    len = fread(file_buffer_raw, 1, COPY_BUFSIZE, source_file);
+    if (len > 0) {
+      for (i = 0; i < len; i++) {
+        sprintf(&file_buffer_c[off], "0x%02.2x,", file_buffer_raw[i]);
+        off += 5;
+        if ((++src_off % HEX_BYTES_PER_LINE) == 0) {
+          memcpy(&file_buffer_c[off], NEWLINE, NEWLINE_LEN);
+          off += NEWLINE_LEN;
+        }
+      }
+      written = fwrite(file_buffer_c, 1, off, data_file);
+    }
+  } while(len > 0);
+  fclose(source_file);
+}
+
+int write_checksums(FILE *struct_file, const char *filename, const char *varname,
+                    u16_t hdr_len, u16_t hdr_chksum)
+{
+  int chunk_size = TCP_MSS;
+  int offset;
+  size_t len;
+  int i = 0;
+  FILE *f;
+#if LWIP_TCP_TIMESTAMPS
+  /* when timestamps are used, usable space is 12 bytes less per segment */
+  chunk_size -= 12;
+#endif
+
+  fprintf(struct_file, "#if HTTPD_PRECALCULATED_CHECKSUM" NEWLINE);
+  fprintf(struct_file, "const struct fsdata_chksum chksums_%s[] = {" NEWLINE, varname);
+
+  memset(file_buffer_raw, 0xab, sizeof(file_buffer_raw));
+  f = fopen(filename, "rb");
+  if (f == INVALID_HANDLE_VALUE) {
+    printf("Failed to open file \"%s\"\n", filename);
+    exit(-1);
+  }
+  if (hdr_len > 0) {
+    /* add checksum for HTTP header */
+    fprintf(struct_file, "{%d, 0x%04x, %d}," NEWLINE, 0, hdr_chksum, hdr_len);
+    i++;
+  }
+  for (offset = hdr_len; ; offset += len) {
+    unsigned short chksum;
+    len = fread(file_buffer_raw, 1, chunk_size, f);
+    if (len == 0) {
+      break;
+    }
+    chksum = ~inet_chksum(file_buffer_raw, (u16_t)len);
+    /* add checksum for data */
+    fprintf(struct_file, "{%d, 0x%04x, %d}," NEWLINE, offset, chksum, len);
+    i++;
+  }
+  fclose(f);
+  fprintf(struct_file, "};" NEWLINE);
+  fprintf(struct_file, "#endif /* HTTPD_PRECALCULATED_CHECKSUM */" NEWLINE);
+  return i;
+}
+
+int process_file(FILE *data_file, FILE *struct_file, const char *filename)
+{
+  char *pch;
+  char varname[MAX_PATH_LEN];
+  int i = 0;
+  char qualifiedName[MAX_PATH_LEN];
+  int file_size;
+  u16_t http_hdr_chksum = 0;
+  u16_t http_hdr_len = 0;
+  int chksum_count = 0;
+
+  /* create qualified name (TODO: prepend slash or not?) */
+  sprintf(qualifiedName,"%s/%s", curSubdir, filename);
+  /* create C variable name */
+  strcpy(varname, qualifiedName);
+  /* convert slashes & dots to underscores */
+  while ((pch = strpbrk(varname, "./\\")) != NULL) {
+    *pch = '_';
+  }
+#if ALIGN_PAYLOAD
+  /* to force even alignment of array */
+  fprintf(data_file, "static const " PAYLOAD_ALIGN_TYPE " dummy_align_%s = %d;" NEWLINE, varname, payload_alingment_dummy_counter++);
+#endif /* ALIGN_PAYLOAD */
+  fprintf(data_file, "static const unsigned char data_%s[] = {" NEWLINE, varname);
+  /* encode source file name (used by file system, not returned to browser) */
+  fprintf(data_file, "/* %s (%d chars) */" NEWLINE, qualifiedName, strlen(qualifiedName)+1);
+  file_put_ascii(data_file, qualifiedName, strlen(qualifiedName)+1, &i);
+#if ALIGN_PAYLOAD
+  /* pad to even number of bytes to assure payload is on aligned boundary */
+  while(i % PAYLOAD_ALIGNMENT != 0) {
+    fprintf(data_file, "0x%02.2x,", 0);
+    i++;
+  }
+#endif /* ALIGN_PAYLOAD */
+  fprintf(data_file, NEWLINE);
+
+  file_size = get_file_size(filename);
+  if (includeHttpHeader) {
+    file_write_http_header(data_file, filename, file_size, &http_hdr_len, &http_hdr_chksum);
+  }
+  if (precalcChksum) {
+    chksum_count = write_checksums(struct_file, filename, varname, http_hdr_len, http_hdr_chksum);
+  }
+
+  /* build declaration of struct fsdata_file in temp file */
+  fprintf(struct_file, "const struct fsdata_file file_%s[] = { {" NEWLINE, varname);
+  fprintf(struct_file, "file_%s," NEWLINE, lastFileVar);
+  fprintf(struct_file, "data_%s," NEWLINE, varname);
+  fprintf(struct_file, "data_%s + %d," NEWLINE, varname, i);
+  fprintf(struct_file, "sizeof(data_%s) - %d," NEWLINE, varname, i);
+  fprintf(struct_file, "%d," NEWLINE, includeHttpHeader);
+  if (precalcChksum) {
+    fprintf(struct_file, "#if HTTPD_PRECALCULATED_CHECKSUM" NEWLINE);
+    fprintf(struct_file, "%d, chksums_%s," NEWLINE, chksum_count, varname);
+    fprintf(struct_file, "#endif /* HTTPD_PRECALCULATED_CHECKSUM */" NEWLINE);
+  }
+  fprintf(struct_file, "}};" NEWLINE NEWLINE);
+  strcpy(lastFileVar, varname);
+
+  /* write actual file contents */
+  i = 0;
+  fprintf(data_file, NEWLINE "/* raw file data (%d bytes) */" NEWLINE, file_size);
+  process_file_data(filename, data_file);
+  fprintf(data_file, "};" NEWLINE NEWLINE);
+
+  return 0;
+}
+
+int file_write_http_header(FILE *data_file, const char *filename, int file_size,
+                           u16_t *http_hdr_len, u16_t *http_hdr_chksum)
+{
+  int i = 0;
+  int response_type = HTTP_HDR_OK;
+  int file_type = HTTP_HDR_DEFAULT_TYPE;
+  const char *cur_string;
+  size_t cur_len;
+  int written = 0;
+  size_t hdr_len = 0;
+  u16_t acc;
+  const char *file_ext;
+  int j;
+
+  memset(hdr_buf, 0, sizeof(hdr_buf));
+  
+  if (useHttp11) {
+    response_type = HTTP_HDR_OK_11;
+  }
+
+  fprintf(data_file, NEWLINE "/* HTTP header */");
+  if (strstr(filename, "404") == filename) {
+    response_type = HTTP_HDR_NOT_FOUND;
+    if (useHttp11) {
+      response_type = HTTP_HDR_NOT_FOUND_11;
+    }
+  } else if (strstr(filename, "400") == filename) {
+    response_type = HTTP_HDR_BAD_REQUEST;
+    if (useHttp11) {
+      response_type = HTTP_HDR_BAD_REQUEST_11;
+    }
+  } else if (strstr(filename, "501") == filename) {
+    response_type = HTTP_HDR_NOT_IMPL;
+    if (useHttp11) {
+      response_type = HTTP_HDR_NOT_IMPL_11;
+    }
+  }
+  cur_string = g_psHTTPHeaderStrings[response_type];
+  cur_len = strlen(cur_string);
+  fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len);
+  written += file_put_ascii(data_file, cur_string, cur_len, &i);
+  i = 0;
+  if (precalcChksum) {
+    memcpy(&hdr_buf[hdr_len], cur_string, cur_len);
+    hdr_len += cur_len;
+  }
+
+  cur_string = serverID;
+  cur_len = strlen(cur_string);
+  fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len);
+  written += file_put_ascii(data_file, cur_string, cur_len, &i);
+  i = 0;
+  if (precalcChksum) {
+    memcpy(&hdr_buf[hdr_len], cur_string, cur_len);
+    hdr_len += cur_len;
+  }
+
+  file_ext = filename;
+  while(strstr(file_ext, ".") != NULL) {
+    file_ext = strstr(file_ext, ".");
+    file_ext++;
+  }
+  if((file_ext == NULL) || (*file_ext == 0)) {
+    printf("failed to get extension for file \"%s\", using default.\n", filename);
+  } else {
+    for(j = 0; j < NUM_HTTP_HEADERS; j++) {
+      if(!strcmp(file_ext, g_psHTTPHeaders[j].extension)) {
+        file_type = g_psHTTPHeaders[j].headerIndex;
+        break;
+      }
+    }
+    if (j >= NUM_HTTP_HEADERS) {
+      printf("failed to get file type for extension \"%s\", using default.\n", file_ext);
+      file_type = HTTP_HDR_DEFAULT_TYPE;
+    }
+  }
+
+  if (useHttp11) {
+    char intbuf[MAX_PATH_LEN];
+    memset(intbuf, 0, sizeof(intbuf));
+
+    cur_string = g_psHTTPHeaderStrings[HTTP_HDR_CONTENT_LENGTH];
+    cur_len = strlen(cur_string);
+    fprintf(data_file, NEWLINE "/* \"%s%d\r\n\" (%d+ bytes) */" NEWLINE, cur_string, file_size, cur_len+2);
+    written += file_put_ascii(data_file, cur_string, cur_len, &i);
+    if (precalcChksum) {
+      memcpy(&hdr_buf[hdr_len], cur_string, cur_len);
+      hdr_len += cur_len;
+    }
+
+    _itoa(file_size, intbuf, 10);
+    strcat(intbuf, "\r\n");
+    cur_len = strlen(intbuf);
+    written += file_put_ascii(data_file, intbuf, cur_len, &i);
+    i = 0;
+    if (precalcChksum) {
+      memcpy(&hdr_buf[hdr_len], intbuf, cur_len);
+      hdr_len += cur_len;
+    }
+
+    cur_string = g_psHTTPHeaderStrings[HTTP_HDR_CONN_CLOSE];
+    cur_len = strlen(cur_string);
+    fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len);
+    written += file_put_ascii(data_file, cur_string, cur_len, &i);
+    i = 0;
+    if (precalcChksum) {
+      memcpy(&hdr_buf[hdr_len], cur_string, cur_len);
+      hdr_len += cur_len;
+    }
+  }
+
+  cur_string = g_psHTTPHeaderStrings[file_type];
+  cur_len = strlen(cur_string);
+  fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len);
+  written += file_put_ascii(data_file, cur_string, cur_len, &i);
+  i = 0;
+  if (precalcChksum) {
+    memcpy(&hdr_buf[hdr_len], cur_string, cur_len);
+    hdr_len += cur_len;
+
+    LWIP_ASSERT("hdr_len <= 0xffff", hdr_len <= 0xffff);
+    LWIP_ASSERT("strlen(hdr_buf) == hdr_len", strlen(hdr_buf) == hdr_len);
+    acc = ~inet_chksum(hdr_buf, (u16_t)hdr_len);
+    *http_hdr_len = (u16_t)hdr_len;
+    *http_hdr_chksum = acc;
+  }
+
+  return written;
+}
+
+int file_put_ascii(FILE *file, const char* ascii_string, int len, int *i)
+{
+  int x;
+  for(x = 0; x < len; x++) {
+    unsigned char cur = ascii_string[x];
+    fprintf(file, "0x%02.2x,", cur);
+    if ((++(*i) % HEX_BYTES_PER_LINE) == 0) {
+      fprintf(file, NEWLINE);
+    }
+  }
+  return len;
+}
+
+int s_put_ascii(char *buf, const char *ascii_string, int len, int *i)
+{
+  int x;
+  int idx = 0;
+  for(x = 0; x < len; x++) {
+    unsigned char cur = ascii_string[x];
+    sprintf(&buf[idx], "0x%02.2x,", cur);
+    idx += 5;
+    if ((++(*i) % HEX_BYTES_PER_LINE) == 0) {
+      sprintf(&buf[idx], NEWLINE);
+      idx += NEWLINE_LEN;
+    }
+  }
+  return len;
+}

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/makefsdata.exe b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/makefsdata.exe
new file mode 100644 (file)
index 0000000..7d4271d
Binary files /dev/null and b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/apps/httpserver_raw/makefsdata/makefsdata.exe differ

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/lwIP_Apps.c b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/lwIP_Apps.c
new file mode 100644 (file)
index 0000000..78995f6
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/lwIP_Apps.c
@@ -0,0 +1,161 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+       \r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* lwIP core includes */\r
+#include "lwip/opt.h"\r
+#include "lwip/tcpip.h"\r
+\r
+/* lwIP netif includes */\r
+#include "netif/etharp.h"\r
+\r
+/* applications includes */\r
+#include "apps/httpserver_raw/httpd.h"\r
+\r
+/* The constants that define the IP address, net mask, gateway address and MAC\r
+address are located at the bottom of FreeRTOSConfig.h. */\r
+#define LWIP_PORT_INIT_IPADDR(addr)   IP4_ADDR((addr), configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 )\r
+#define LWIP_PORT_INIT_GW(addr)       IP4_ADDR((addr), configGW_IP_ADDR0, configGW_IP_ADDR1, configGW_IP_ADDR2, configGW_IP_ADDR3 )\r
+#define LWIP_PORT_INIT_NETMASK(addr)  IP4_ADDR((addr), configNET_MASK0,configNET_MASK1,configNET_MASK2,configNET_MASK3)\r
+#define LWIP_MAC_ADDR_BASE            { configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 }\r
+\r
+/* Definitions of the various SSI callback functions within the pccSSITags \r
+array.  If pccSSITags is updated, then these definitions must also be updated. */\r
+#define ssiTASK_STATS_INDEX                    0\r
+#define ssiRUN_TIME_STATS_INDEX                1\r
+\r
+/*\r
+ * The SSI handler callback function passed to lwIP.\r
+ */\r
+static unsigned short uslwIPAppsSSIHandler( int iIndex, char *pcBuffer, int iBufferLength );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The SSI strings that are embedded in the served html files.  If this array\r
+is changed, then the index position defined by the #defines such as \r
+ssiTASK_STATS_INDEX above must also be updated. */\r
+static const char *pccSSITags[] = \r
+{\r
+       "rtos_stats",\r
+       "run_stats"\r
+};\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Called from the TCP/IP thread. */\r
+void lwIPAppsInit( void *pvArgument )\r
+{\r
+ip_addr_t xIPAddr, xNetMask, xGateway;\r
+extern err_t ethernetif_init( struct netif *xNetIf );\r
+static struct netif xNetIf;\r
+\r
+       ( void ) pvArgument;\r
+\r
+       /* Set up the network interface. */\r
+       ip_addr_set_zero( &xGateway );\r
+       ip_addr_set_zero( &xIPAddr );\r
+       ip_addr_set_zero( &xNetMask );\r
+\r
+       LWIP_PORT_INIT_GW(&xGateway);\r
+       LWIP_PORT_INIT_IPADDR(&xIPAddr);\r
+       LWIP_PORT_INIT_NETMASK(&xNetMask);\r
+\r
+       netif_set_default( netif_add( &xNetIf, &xIPAddr, &xNetMask, &xGateway, NULL, ethernetif_init, tcpip_input ) );\r
+       netif_set_up( &xNetIf );\r
+\r
+       /* Initialise the raw http server. */\r
+       httpd_init();\r
+\r
+       /* Install the server side include handler. */\r
+       http_set_ssi_handler( uslwIPAppsSSIHandler, pccSSITags, sizeof( pccSSITags ) / sizeof( char * ) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static unsigned short uslwIPAppsSSIHandler( int iIndex, char *pcBuffer, int iBufferLength )\r
+{\r
+static unsigned int uiUpdateCount = 0;\r
+static char cUpdateString[ 200 ];\r
+extern char *pcMainGetTaskStatusMessage( void );\r
+\r
+       /* Unused parameter. */\r
+       ( void ) iBufferLength;\r
+\r
+       /* The SSI handler function that generates text depending on the index of\r
+       the SSI tag encountered. */\r
+       \r
+       switch( iIndex )\r
+       {\r
+               case ssiTASK_STATS_INDEX :\r
+                       vTaskList( ( signed char * ) pcBuffer );\r
+                       break;\r
+\r
+               case ssiRUN_TIME_STATS_INDEX :\r
+                       vTaskGetRunTimeStats( ( signed char * ) pcBuffer );\r
+                       break;\r
+       }\r
+\r
+       /* Include a count of the number of times an SSI function has been executed\r
+       in the returned string. */\r
+       uiUpdateCount++;\r
+       sprintf( cUpdateString, "\r\n\r\n%u\r\nStatus - %s", uiUpdateCount, pcMainGetTaskStatusMessage() );\r
+       strcat( pcBuffer, cUpdateString );\r
+       return strlen( pcBuffer );\r
+}\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/lwipcfg_MicroBlaze.h b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/lwipcfg_MicroBlaze.h
new file mode 100644 (file)
index 0000000..f7109fa
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/lwipcfg_MicroBlaze.h
@@ -0,0 +1,15 @@
+
+#define LWIP_PORT_INIT_IPADDR(addr)   IP4_ADDR((addr), configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 )
+#define LWIP_PORT_INIT_GW(addr)       IP4_ADDR((addr), configGW_IP_ADDR0, configGW_IP_ADDR1, configGW_IP_ADDR2, configGW_IP_ADDR3 )
+#define LWIP_PORT_INIT_NETMASK(addr)  IP4_ADDR((addr), configNET_MASK0,configNET_MASK1,configNET_MASK2,configNET_MASK3)
+
+/* remember to change this MAC address to suit your needs!
+   the last octet will be increased by netif->num for each netif */
+#define LWIP_MAC_ADDR_BASE            { configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 }
+
+/* configuration for applications */
+
+#define LWIP_CHARGEN_APP              0
+#define LWIP_DNS_APP                  0
+#define LWIP_HTTPD_APP                1
+

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/lwipopts.h b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/lwipopts.h
new file mode 100644 (file)
index 0000000..9d396cf
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/lwIP/lwIP_Apps/lwipopts.h
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *     derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIPOPTS_H__
+#define __LWIPOPTS_H__
+
+#include "xparameters.h"
+
+/* Define platform endianness (might already be defined) */
+#ifndef BYTE_ORDER
+       #if XPAR_MICROBLAZE_0_ENDIANNESS == 1
+               #define BYTE_ORDER LITTLE_ENDIAN
+       #else
+               #define BYTE_ORDER BIG_ENDIAN
+       #endif
+#endif /* BYTE_ORDER */
+
+/* Using the Lite Ethernet IP. */
+#define XLWIP_CONFIG_INCLUDE_EMACLITE 1
+
+/* SSI options. */
+#define TCPIP_THREAD_NAME                              "tcpip"
+#define LWIP_HTTPD_MAX_TAG_NAME_LEN    20
+#define LWIP_HTTPD_MAX_TAG_INSERT_LEN  1500
+#define TCPIP_THREAD_PRIO                              configLWIP_TASK_PRIORITY
+#define TCPIP_THREAD_STACKSIZE                         configMINIMAL_STACK_SIZE * 3
+
+/* MBox sizes cannot be zer, which is their default. */
+#define DEFAULT_TCP_RECVMBOX_SIZE              5
+#define DEFAULT_ACCEPTMBOX_SIZE                5
+#define TCPIP_MBOX_SIZE                                        10
+
+/* FreeRTOS is used. */
+#define NO_SYS                                                 0
+
+/* In this example, sockets are not used, only the raw API. */
+#define LWIP_SOCKET                            0
+
+/* In this example, only the raw API is used. */
+#define LWIP_NETCONN                           0
+
+/* SNMP and IGMP are not required by this simple demo.  ICMP is always useful
+though. */
+#define LWIP_SNMP                                              0
+#define LWIP_IGMP                                              0
+#define LWIP_ICMP                                              1
+
+/* DNS is not going to be used as this is a simple local example. */
+#define LWIP_DNS                                               0
+
+#define LWIP_HAVE_LOOPIF                               0
+#define TCP_LISTEN_BACKLOG                             0
+#define LWIP_SO_RCVTIMEO                               1
+#define LWIP_SO_RCVBUF                                 1
+
+#ifdef LWIP_DEBUG
+       #define LWIP_DBG_MIN_LEVEL                      0
+       #define PPP_DEBUG                                       LWIP_DBG_OFF
+       #define MEM_DEBUG                                       LWIP_DBG_ON
+       #define MEMP_DEBUG                                      LWIP_DBG_ON
+       #define PBUF_DEBUG                                      LWIP_DBG_ON
+       #define API_LIB_DEBUG                           LWIP_DBG_OFF
+       #define API_MSG_DEBUG                           LWIP_DBG_OFF
+       #define TCPIP_DEBUG                                     LWIP_DBG_OFF
+       #define NETIF_DEBUG                                     LWIP_DBG_OFF
+       #define SOCKETS_DEBUG                           LWIP_DBG_OFF
+       #define DNS_DEBUG                                       LWIP_DBG_OFF
+       #define AUTOIP_DEBUG                            LWIP_DBG_OFF
+       #define DHCP_DEBUG                                      LWIP_DBG_OFF
+       #define IP_DEBUG                                        LWIP_DBG_OFF
+       #define IP_REASS_DEBUG                          LWIP_DBG_OFF
+       #define ICMP_DEBUG                                      LWIP_DBG_OFF
+       #define IGMP_DEBUG                                      LWIP_DBG_OFF
+       #define UDP_DEBUG                                       LWIP_DBG_OFF
+       #define TCP_DEBUG                                       LWIP_DBG_OFF
+       #define TCP_INPUT_DEBUG                         LWIP_DBG_OFF
+       #define TCP_OUTPUT_DEBUG                        LWIP_DBG_OFF
+       #define TCP_RTO_DEBUG                           LWIP_DBG_OFF
+       #define TCP_CWND_DEBUG                          LWIP_DBG_OFF
+       #define TCP_WND_DEBUG                           LWIP_DBG_OFF
+       #define TCP_FR_DEBUG                            LWIP_DBG_OFF
+       #define TCP_QLEN_DEBUG                          LWIP_DBG_OFF
+       #define TCP_RST_DEBUG                           LWIP_DBG_OFF
+#endif
+
+#define LWIP_DBG_TYPES_ON                              (LWIP_DBG_ON|LWIP_DBG_TRACE|LWIP_DBG_STATE|LWIP_DBG_FRESH|LWIP_DBG_HALT)
+
+
+
+/* ---------- Memory options ---------- */
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
+   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
+   byte alignment -> define MEM_ALIGNMENT to 2. */
+/* MSVC port: intel processors don't need 4-byte alignment,
+   but are faster that way! */
+#define MEM_ALIGNMENT                  4
+
+/* MEM_SIZE: the size of the heap memory. If the application will send
+a lot of data that needs to be copied, this should be set high. */
+#define MEM_SIZE                               10240
+
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
+   sends a lot of data out of ROM (or other static memory), this
+   should be set high. */
+#define MEMP_NUM_PBUF                  10
+
+/* MEMP_NUM_RAW_PCB: the number of UDP protocol control blocks. One
+   per active RAW "connection". */
+#define LWIP_RAW                               0
+#define MEMP_NUM_RAW_PCB               0
+
+/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+   per active UDP "connection". */
+#define MEMP_NUM_UDP_PCB               2
+
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
+   connections. */
+#define MEMP_NUM_TCP_PCB               40
+
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
+   connections. */
+#define MEMP_NUM_TCP_PCB_LISTEN 2
+
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
+   segments. */
+#define MEMP_NUM_TCP_SEG               10
+
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
+   timeouts. */
+#define MEMP_NUM_SYS_TIMEOUT   15
+
+/* The following four are used only with the sequential API and can be
+   set to 0 if the application only will use the raw API. */
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */
+#define MEMP_NUM_NETBUF         0
+
+/* MEMP_NUM_NETCONN: the number of struct netconns. */
+#define MEMP_NUM_NETCONN        0
+
+/* MEMP_NUM_TCPIP_MSG_*: the number of struct tcpip_msg, which is used
+   for sequential API communication and incoming packets. Used in
+   src/api/tcpip.c. */
+#define MEMP_NUM_TCPIP_MSG_API   4
+#define MEMP_NUM_TCPIP_MSG_INPKT 4
+
+#define MEMP_NUM_ARP_QUEUE             5
+
+/* ---------- Pbuf options ---------- */
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
+#define PBUF_POOL_SIZE                 10
+
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
+#define PBUF_POOL_BUFSIZE              375
+
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+   link level header. */
+#define PBUF_LINK_HLEN                 16
+
+/** SYS_LIGHTWEIGHT_PROT
+ * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#define SYS_LIGHTWEIGHT_PROT   (NO_SYS==0)
+
+
+/* ---------- TCP options ---------- */
+#define LWIP_TCP                               1
+#define TCP_TTL                                        255
+
+/* Controls if TCP should queue segments that arrive out of
+   order. Define to 0 if your device is low on memory. */
+#define TCP_QUEUE_OOSEQ                        1
+
+/* TCP Maximum segment size. */
+#define TCP_MSS                                        1460
+
+/* TCP sender buffer space (bytes). */
+#define TCP_SND_BUF                            2048
+
+/* TCP sender buffer space (pbufs). This must be at least = 2 *
+   TCP_SND_BUF/TCP_MSS for things to work. */
+#define TCP_SND_QUEUELEN               (4 * TCP_SND_BUF/TCP_MSS)
+
+/* TCP writable space (bytes). This must be less than or equal
+   to TCP_SND_BUF. It is the amount of space which must be
+   available in the tcp snd_buf for select to return writable */
+#define TCP_SNDLOWAT                   (TCP_SND_BUF/2)
+
+/* TCP receive window. */
+#define TCP_WND                                        4048
+
+/* Maximum number of retransmissions of data segments. */
+#define TCP_MAXRTX                             12
+
+/* Maximum number of retransmissions of SYN segments. */
+#define TCP_SYNMAXRTX                  4
+
+
+/* ---------- ARP options ---------- */
+#define LWIP_ARP                               1
+#define ARP_TABLE_SIZE                 10
+#define ARP_QUEUEING                   1
+
+
+/* ---------- IP options ---------- */
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward
+   IP packets across network interfaces. If you are going to run lwIP
+   on a device with only one network interface, define this to 0. */
+#define IP_FORWARD                             0
+
+/* IP reassembly and segmentation.These are orthogonal even
+ * if they both deal with IP fragments */
+#define IP_REASSEMBLY                  0
+#define IP_REASS_MAX_PBUFS             10
+#define MEMP_NUM_REASSDATA             10
+#define IP_FRAG                                        0
+
+
+/* ---------- ICMP options ---------- */
+#define ICMP_TTL                               255
+
+
+/* ---------- DHCP options ---------- */
+/* Define LWIP_DHCP to 1 if you want DHCP configuration of
+   interfaces. */
+#define LWIP_DHCP                              0
+
+/* 1 if you want to do an ARP check on the offered address
+   (recommended). */
+#define DHCP_DOES_ARP_CHECK            (LWIP_DHCP)
+
+
+/* ---------- AUTOIP options ------- */
+#define LWIP_AUTOIP                            0
+#define LWIP_DHCP_AUTOIP_COOP  (LWIP_DHCP && LWIP_AUTOIP)
+
+
+/* ---------- UDP options ---------- */
+#define LWIP_UDP                               1
+#define LWIP_UDPLITE                   1
+#define UDP_TTL                                        255
+
+
+/* ---------- Statistics options ---------- */
+
+#define LWIP_STATS                             1
+#define LWIP_STATS_DISPLAY             0
+
+#if LWIP_STATS
+       #define LINK_STATS                              1
+       #define IP_STATS                                1
+       #define ICMP_STATS                              0
+       #define IGMP_STATS                              0
+       #define IPFRAG_STATS                    0
+       #define UDP_STATS                               1
+       #define TCP_STATS                               1
+       #define MEM_STATS                               1
+       #define MEMP_STATS                              1
+       #define PBUF_STATS                              1
+       #define SYS_STATS                               1
+#endif /* LWIP_STATS */
+
+
+/* ---------- PPP options ---------- */
+
+#define PPP_SUPPORT                     0        /* Set > 0 for PPP */
+
+#if PPP_SUPPORT
+
+       #define NUM_PPP                                 1         /* Max PPP sessions. */
+
+       /* Select modules to enable.  Ideally these would be set in the makefile but
+        * we're limited by the command line length so you need to modify the settings
+        * in this file.
+        */
+       #define PPPOE_SUPPORT                   1
+       #define PPPOS_SUPPORT                   1
+       #define PAP_SUPPORT                             1         /* Set > 0 for PAP. */
+       #define CHAP_SUPPORT                    1         /* Set > 0 for CHAP. */
+       #define MSCHAP_SUPPORT                  0         /* Set > 0 for MSCHAP (NOT FUNCTIONAL!) */
+       #define CBCP_SUPPORT                    0         /* Set > 0 for CBCP (NOT FUNCTIONAL!) */
+       #define CCP_SUPPORT                             0         /* Set > 0 for CCP (NOT FUNCTIONAL!) */
+       #define VJ_SUPPORT                              1         /* Set > 0 for VJ header compression. */
+       #define MD5_SUPPORT                             1         /* Set > 0 for MD5 (see also CHAP) */
+
+#endif /* PPP_SUPPORT */
+
+#endif /* __LWIPOPTS_H__ */

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/main-blinky.c b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/main-blinky.c
new file mode 100644 (file)
index 0000000..1f04da0
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/main-blinky.c
@@ -0,0 +1,536 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+       FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:\r
+       Atollic AB - Atollic provides professional embedded systems development\r
+       tools for C/C++ development, code analysis and test automation.\r
+       See http://www.atollic.com\r
+\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/*\r
+ * main-blinky.c is included when the "Blinky" build configuration is used.\r
+ * main-full.c is included when the "Full" build configuration is used.\r
+ *\r
+ * main-blinky.c (this file) defines a very simple demo that creates two tasks,\r
+ * one queue, and one timer.  It also demonstrates how MicroBlaze interrupts\r
+ * can interact with FreeRTOS tasks/timers.\r
+ *\r
+ * This simple demo project was developed and tested on the Spartan-6 SP605 \r
+ * development board, using the hardware configuration found in the hardware\r
+ * project that is already included in the Eclipse project.\r
+ *\r
+ * The idle hook function:\r
+ * The idle hook function demonstrates how to query the amount of FreeRTOS heap\r
+ * space that is remaining (see vApplicationIdleHook() defined in this file).\r
+ *\r
+ * The main() Function:\r
+ * main() creates one software timer, one queue, and two tasks.  It then starts\r
+ * the scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file.  prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main().  Once the value is sent, the task loops back\r
+ * around to block for another 200 milliseconds.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file.  prvQueueReceiveTask() sits in a loop that causes it to\r
+ * repeatedly attempt to read data from the queue that was created within\r
+ * main().  When data is received, the task checks the value of the data, and\r
+ * if the value equals the expected 100, toggles an LED.  The 'block time' \r
+ * parameter passed to the queue receive function specifies that the task\r
+ * should be held in the Blocked state indefinitely to wait for data to be\r
+ * available on the queue.  The queue receive task will only leave the Blocked\r
+ * state when the queue send task writes to the queue.  As the queue send task\r
+ * writes to the queue every 200 milliseconds, the queue receive task leaves\r
+ * the Blocked state every 200 milliseconds, and therefore toggles the LED\r
+ * every 200 milliseconds.\r
+ *\r
+ * The LED Software Timer and the Button Interrupt:\r
+ * The user buttons are configured to generate an interrupt each time one is\r
+ * pressed.  The interrupt service routine switches an LED on, and resets the\r
+ * LED software timer.  The LED timer has a 5000 millisecond (5 second) period,\r
+ * and uses a callback function that is defined to just turn the LED off again.\r
+ * Therefore, pressing the user button will turn the LED on, and the LED will\r
+ * remain on until a full five seconds pass without the button being pressed.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "timers.h"\r
+\r
+/* BSP includes. */\r
+#include "xtmrctr.h"\r
+#include "xgpio.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY                ( tskIDLE_PRIORITY + 2 )\r
+#define        mainQUEUE_SEND_TASK_PRIORITY            ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue, specified in milliseconds, and\r
+converted to ticks using the portTICK_RATE_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS                    ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold.  This is 1 as the receive task\r
+will remove items as they are added because it has the higher priority, meaning \r
+the send task should always find the queue empty. */\r
+#define mainQUEUE_LENGTH                                       ( 1 )\r
+\r
+/* The LED toggled by the queue receive task. */\r
+#define mainTASK_CONTROLLED_LED                                0x01UL\r
+\r
+/* The LED turned on by the button interrupt, and turned off by the LED timer. */\r
+#define mainTIMER_CONTROLLED_LED                       0x02UL\r
+\r
+/* A block time of 0 simply means, "don't block". */\r
+#define mainDONT_BLOCK                                         ( portTickType ) 0\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the NVIC, LED outputs, and button inputs.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * The LED timer callback function.  This does nothing but switch off the\r
+ * LED defined by the mainTIMER_CONTROLLED_LED constant.\r
+ */\r
+static void vLEDTimerCallback( xTimerHandle xTimer );\r
+\r
+/* \r
+ * The handler executed each time a button interrupt is generated.  This ensures\r
+ * the LED defined by mainTIMER_CONTROLLED_LED is on, and resets the timer so\r
+ * the timer will not turn the LED off for a full 5 seconds after the button\r
+ * interrupt occurred.\r
+ */\r
+static void prvButtonInputInterruptHandler( void *pvUnused );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by the queue send and queue receive tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/* The LED software timer.  This uses vLEDTimerCallback() as its callback\r
+function. */\r
+static xTimerHandle xLEDTimer = NULL;\r
+\r
+/* Maintains the current LED output state. */\r
+static volatile unsigned char ucGPIOState = 0U;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Structures that hold the state of the various peripherals used by this demo.\r
+These are used by the Xilinx peripheral driver API functions. */\r
+static XTmrCtr xTimer0Instance;\r
+static XGpio xOutputGPIOInstance, xInputGPIOInstance;\r
+\r
+/* Constants required by the Xilinx peripheral driver API functions that are\r
+relevant to the particular hardware set up. */\r
+static const unsigned long ulGPIOOutputChannel = 1UL, ulGPIOInputChannel = 1UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+       /* *************************************************************************\r
+       This is a very simple project suitable for getting started with FreeRTOS.  \r
+       If you would prefer a more complex project that demonstrates a lot more \r
+       features and tests, then select the 'Full' build configuration within the \r
+       SDK Eclipse IDE. \r
+       ***************************************************************************/\r
+\r
+       /* Configure the interrupt controller, LED outputs and button inputs. */\r
+       prvSetupHardware();\r
+\r
+       /* Create the queue used by the queue send and queue receive tasks as\r
+       described in the comments at the top of this file. */\r
+       xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+       /* Sanity check that the queue was created. */\r
+       configASSERT( xQueue );\r
+\r
+       /* Start the two tasks as described in the comments at the top of this \r
+       file. */\r
+       xTaskCreate( prvQueueReceiveTask, ( signed char * ) "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL );\r
+       xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+       /* Create the software timer that is responsible for turning off the LED\r
+       if the button is not pushed within 5000ms, as described at the top of\r
+       this file.  The timer is not actually started until a button interrupt is\r
+       pushed, as it is not until that point that the LED is turned on. */\r
+       xLEDTimer = xTimerCreate(       ( const signed char * ) "LEDTimer", /* A text name, purely to help debugging. */\r
+                                                               ( 5000 / portTICK_RATE_MS ),            /* The timer period, in this case 5000ms (5s). */\r
+                                                               pdFALSE,                                                        /* This is a one shot timer, so xAutoReload is set to pdFALSE. */\r
+                                                               ( void * ) 0,                                           /* The ID is not used, so can be set to anything. */\r
+                                                               vLEDTimerCallback                                       /* The callback function that switches the LED off. */\r
+                                                       );\r
+\r
+       /* Start the tasks and timer running. */\r
+       vTaskStartScheduler();\r
+\r
+       /* If all is well, the scheduler will now be running, and the following line\r
+       will never be reached.  If the following line does execute, then there was\r
+       insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
+       to be created.  See the memory management section on the FreeRTOS web site\r
+       for more details. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The callback is executed when the LED timer expires. */\r
+static void vLEDTimerCallback( xTimerHandle xTimer )\r
+{\r
+       /* The timer has expired - so no button pushes have occurred in the last\r
+       five seconds - turn the LED off.  NOTE - accessing the LED port should use\r
+       a critical section because it is accessed from multiple tasks, and the\r
+       button interrupt - in this trivial case, for simplicity, the critical\r
+       section is omitted. */\r
+       ucGPIOState &= ~mainTIMER_CONTROLLED_LED;\r
+       XGpio_DiscreteWrite( &xOutputGPIOInstance, ulGPIOOutputChannel, ucGPIOState );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The ISR is executed when the user button is pushed. */\r
+static void prvButtonInputInterruptHandler( void *pvUnused )\r
+{\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+       /* The button was pushed, so ensure the LED is on before resetting the\r
+       LED timer.  The LED timer will turn the LED off if the button is not\r
+       pushed within 5000ms. */\r
+       ucGPIOState |= mainTIMER_CONTROLLED_LED;\r
+       XGpio_DiscreteWrite( &xOutputGPIOInstance, ulGPIOOutputChannel, ucGPIOState );\r
+\r
+       /* Ensure only the ISR safe reset API function is used, as this is executed\r
+       in an interrupt context. */\r
+       xTimerResetFromISR( xLEDTimer, &lHigherPriorityTaskWoken );\r
+\r
+       /* Clear the interrupt before leaving. */\r
+       XGpio_InterruptClear( &xInputGPIOInstance, ulGPIOInputChannel );\r
+\r
+       /* If calling xTimerResetFromISR() caused a task (in this case the timer\r
+       service/daemon task) to unblock, and the unblocked task has a priority\r
+       higher than or equal to the task that was interrupted, then\r
+       lHigherPriorityTaskWoken will now be set to pdTRUE, and calling\r
+       portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */\r
+       portYIELD_FROM_ISR( lHigherPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+       /* Initialise xNextWakeTime - this only needs to be done once. */\r
+       xNextWakeTime = xTaskGetTickCount();\r
+\r
+       for( ;; )\r
+       {\r
+               /* Place this task in the blocked state until it is time to run again.\r
+               The block time is specified in ticks, the constant used converts ticks\r
+               to ms.  While in the Blocked state this task will not consume any CPU\r
+               time. */\r
+               vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+               /* Send to the queue - causing the queue receive task to unblock and\r
+               toggle an LED.  0 is used as the block time so the sending operation\r
+               will not block - it shouldn't need to block as the queue should always\r
+               be empty at this point in the code. */\r
+               xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+       for( ;; )\r
+       {\r
+               /* Wait until something arrives in the queue - this task will block\r
+               indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+               FreeRTOSConfig.h. */\r
+               xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+               /*  To get here something must have been received from the queue, but\r
+               is it the expected value?  If it is, toggle the green LED. */\r
+               if( ulReceivedValue == 100UL )\r
+               {\r
+                       /* NOTE - accessing the LED port should use a critical section\r
+                       because it is accessed from multiple tasks, and the button interrupt\r
+                       - in this trivial case, for simplicity, the critical section is\r
+                       omitted. */\r
+                       if( ( ucGPIOState & mainTASK_CONTROLLED_LED ) != 0 )\r
+                       {\r
+                               ucGPIOState &= ~mainTASK_CONTROLLED_LED;\r
+                       }\r
+                       else\r
+                       {\r
+                               ucGPIOState |= mainTASK_CONTROLLED_LED;\r
+                       }\r
+\r
+                       XGpio_DiscreteWrite( &xOutputGPIOInstance, ulGPIOOutputChannel, ucGPIOState );\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+portBASE_TYPE xStatus;\r
+const unsigned char ucSetToOutput = 0U;\r
+\r
+       /* Initialize the GPIO for the LEDs. */\r
+       xStatus = XGpio_Initialize( &xOutputGPIOInstance, XPAR_LEDS_4BITS_DEVICE_ID );\r
+       if( xStatus == XST_SUCCESS )\r
+       {\r
+               /* All bits on this channel are going to be outputs (LEDs). */\r
+               XGpio_SetDataDirection( &xOutputGPIOInstance, ulGPIOOutputChannel, ucSetToOutput );\r
+\r
+               /* Start with all LEDs off. */\r
+               ucGPIOState = 0U;\r
+               XGpio_DiscreteWrite( &xOutputGPIOInstance, ulGPIOOutputChannel, ucGPIOState );\r
+       }\r
+\r
+       /* Initialise the GPIO for the button inputs. */\r
+       if( xStatus == XST_SUCCESS )\r
+       {\r
+               xStatus = XGpio_Initialize( &xInputGPIOInstance, XPAR_PUSH_BUTTONS_4BITS_DEVICE_ID );\r
+       }\r
+\r
+       if( xStatus == XST_SUCCESS )\r
+       {\r
+               /* Install the handler defined in this task for the button input. \r
+               *NOTE* The FreeRTOS defined xPortInstallInterruptHandler() API function\r
+               must be used for this purpose. */\r
+               xStatus = xPortInstallInterruptHandler( XPAR_MICROBLAZE_0_INTC_PUSH_BUTTONS_4BITS_IP2INTC_IRPT_INTR, prvButtonInputInterruptHandler, NULL );\r
+\r
+               if( xStatus == pdPASS )\r
+               {\r
+                       /* Set buttons to input. */\r
+                       XGpio_SetDataDirection( &xInputGPIOInstance, ulGPIOInputChannel, ~( ucSetToOutput ) );\r
+                       \r
+                       /* Enable the button input interrupts in the interrupt controller.\r
+                       *NOTE* The vPortEnableInterrupt() API function must be used for this\r
+                       purpose. */\r
+                       vPortEnableInterrupt( XPAR_MICROBLAZE_0_INTC_PUSH_BUTTONS_4BITS_IP2INTC_IRPT_INTR );\r
+\r
+                       /* Enable GPIO channel interrupts. */\r
+                       XGpio_InterruptEnable( &xInputGPIOInstance, ulGPIOInputChannel );\r
+                       XGpio_InterruptGlobalEnable( &xInputGPIOInstance );\r
+               }\r
+       }\r
+\r
+       configASSERT( ( xStatus == pdPASS ) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+       /* vApplicationMallocFailedHook() will only be called if\r
+       configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h.  It is a hook\r
+       function that will get called if a call to pvPortMalloc() fails. \r
+       pvPortMalloc() is called internally by the kernel whenever a task, queue or\r
+       semaphore is created.  It is also called by various parts of the demo\r
+       application.  If heap_1.c or heap_2.c are used, then the size of the heap\r
+       available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+       FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+       to query the size of free heap space that remains (although it does not\r
+       provide information on how the remaining heap might be fragmented). */\r
+       taskDISABLE_INTERRUPTS();\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
+{\r
+       ( void ) pcTaskName;\r
+       ( void ) pxTask;\r
+\r
+       /* vApplicationStackOverflowHook() will only be called if\r
+       configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2.  The handle and name\r
+       of the offending task will be passed into the hook function via its \r
+       parameters.  However, when a stack has overflowed, it is possible that the\r
+       parameters will have been corrupted, in which case the pxCurrentTCB variable\r
+       can be inspected directly. */\r
+       taskDISABLE_INTERRUPTS();\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+#ifdef EXAMPLE_CODE_ONLY\r
+\r
+       The following code can only be included if heap_1.c or heap_2.c is used in\r
+       the project.  By default, heap_3.c is used, so the example code is\r
+       excluded.  See http://www.freertos.org/a00111.html for more information on\r
+       memory management options.\r
+\r
+       volatile size_t xFreeHeapSpace;\r
+\r
+               /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+               to 1 in FreeRTOSConfig.h.  It will be called on each iteration of the idle\r
+               task.  It is essential that code added to this hook function never attempts\r
+               to block in any way (for example, call xQueueReceive() with a block time\r
+               specified, or call vTaskDelay()).  If the application makes use of the\r
+               vTaskDelete() API function (as this demo application does) then it is also\r
+               important that vApplicationIdleHook() is permitted to return to its calling\r
+               function, because it is the responsibility of the idle task to clean up\r
+               memory allocated by the kernel to any task that has since been deleted. */\r
+\r
+               /* This implementation of vApplicationIdleHook() simply demonstrates how\r
+               the xPortGetFreeHeapSize() function can be used. */\r
+               xFreeHeapSpace = xPortGetFreeHeapSize();\r
+\r
+               if( xFreeHeapSpace > 100 )\r
+               {\r
+                       /* By now, the kernel has allocated everything it is going to, so\r
+                       if there is a lot of heap remaining unallocated then\r
+                       the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be\r
+                       reduced accordingly. */\r
+               }\r
+#endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is an application defined callback function used to install the tick\r
+interrupt handler.  It is provided as an application callback because the kernel\r
+will run on lots of different MicroBlaze and FPGA configurations - not all of\r
+which will have the same timer peripherals defined or available.  This example\r
+uses the AXI Timer 0.  If that is available on your hardware platform then this\r
+example callback implementation should not require modification.   The name of\r
+the interrupt handler that should be installed is vPortTickISR(), which the \r
+function below declares as an extern. */\r
+void vApplicationSetupTimerInterrupt( void )\r
+{\r
+portBASE_TYPE xStatus;\r
+const unsigned char ucTimerCounterNumber = ( unsigned char ) 0U;\r
+const unsigned long ulCounterValue = ( ( XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ / configTICK_RATE_HZ ) - 1UL );\r
+extern void vPortTickISR( void *pvUnused );\r
+\r
+       /* Initialise the timer/counter. */\r
+       xStatus = XTmrCtr_Initialize( &xTimer0Instance, XPAR_AXI_TIMER_0_DEVICE_ID );\r
+\r
+       if( xStatus == XST_SUCCESS )\r
+       {\r
+               /* Install the tick interrupt handler as the timer ISR. \r
+               *NOTE* The xPortInstallInterruptHandler() API function must be used for\r
+               this purpose. */\r
+               xStatus = xPortInstallInterruptHandler( XPAR_INTC_0_TMRCTR_0_VEC_ID, vPortTickISR, NULL );\r
+       }\r
+\r
+       if( xStatus == pdPASS )\r
+       {\r
+               /* Enable the timer interrupt in the interrupt controller.\r
+               *NOTE* The vPortEnableInterrupt() API function must be used for this\r
+               purpose. */\r
+               vPortEnableInterrupt( XPAR_INTC_0_TMRCTR_0_VEC_ID );\r
+\r
+               /* Configure the timer interrupt handler. */\r
+               XTmrCtr_SetHandler( &xTimer0Instance, ( void * ) vPortTickISR, NULL );\r
+\r
+               /* Set the correct period for the timer. */\r
+               XTmrCtr_SetResetValue( &xTimer0Instance, ucTimerCounterNumber, ulCounterValue );\r
+\r
+               /* Enable the interrupts.  Auto-reload mode is used to generate a\r
+               periodic tick.  Note that interrupts are disabled when this function is\r
+               called, so interrupts will not start to be processed until the first\r
+               task has started to run. */\r
+               XTmrCtr_SetOptions( &xTimer0Instance, ucTimerCounterNumber, ( XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION | XTC_DOWN_COUNT_OPTION ) );\r
+\r
+               /* Start the timer. */\r
+               XTmrCtr_Start( &xTimer0Instance, ucTimerCounterNumber );\r
+       }\r
+\r
+       /* Sanity check that the function executed as expected. */\r
+       configASSERT( ( xStatus == pdPASS ) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is an application defined callback function used to clear whichever\r
+interrupt was installed by the the vApplicationSetupTimerInterrupt() callback\r
+function - in this case the interrupt generated by the AXI timer.  It is \r
+provided as an application callback because the kernel will run on lots of \r
+different MicroBlaze and FPGA configurations - not all of which will have the \r
+same timer peripherals defined or available.  This example uses the AXI Timer 0.  \r
+If that is available on your hardware platform then this example callback \r
+implementation should not require modification provided the example definition\r
+of vApplicationSetupTimerInterrupt() is also not modified. */\r
+void vApplicationClearTimerInterrupt( void )\r
+{\r
+unsigned long ulCSR;\r
+\r
+       /* Clear the timer interrupt */\r
+       ulCSR = XTmrCtr_GetControlStatusReg( XPAR_AXI_TIMER_0_BASEADDR, 0 );\r
+       XTmrCtr_SetControlStatusReg( XPAR_AXI_TIMER_0_BASEADDR, 0, ulCSR );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* These functions are not used by the Blinky build configuration.  However,\r
+they need to be defined because the Blinky and Full build configurations share\r
+a FreeRTOSConifg.h configuration file. */
+void vMainConfigureTimerForRunTimeStats( void ) {}\r
+unsigned long ulMainGetRunTimeCounterValue( void ) { return 1; }\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/main-full.c b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/main-full.c
new file mode 100644 (file)
index 0000000..1862f37
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/main-full.c
@@ -0,0 +1,669 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+       \r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/* ****************************************************************************\r
+ * main-blinky.c is included when the "Blinky" build configuration is used.\r
+ * main-full.c is included when the "Full" build configuration is used.\r
+ *\r
+ * main-full.c creates a lot of demo and test tasks and timers,  and is \r
+ * therefore very comprehensive but also complex.  If you would prefer a much \r
+ * simpler project to get started with, then select the 'Blinky' build \r
+ * configuration within the SDK Eclipse IDE.  See the documentation page for\r
+ * this demo on the http://www.FreeRTOS.org web site for more information.\r
+ * ****************************************************************************\r
+ *\r
+ * main() creates all the demo application tasks and timers, then starts the \r
+ * scheduler.  The web documentation provides more details of the standard demo \r
+ * application tasks, which provide no particular functionality, but do provide \r
+ * a good example of how to use the FreeRTOS API.  \r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * TCP/IP ("lwIP") task - lwIP is used to create a basic web server.  The web\r
+ * server uses server side includes (SSI) to generate tables of task statistics,\r
+ * and run time statistics (run time statistics show how much processing time\r
+ * each task has consumed).  See\r
+ * http://www.FreeRTOS.org/Free-RTOS-for-Xilinx-MicroBlaze-on-Spartan-6-FPGA.html\r
+ * for details on setting up and using the embedded web server.\r
+ *\r
+ * "Reg test" tasks - These test the task context switch mechanism by first \r
+ * filling the MicroBlaze registers with known values, before checking that each\r
+ * register maintains the value that was written to it as the tasks are switched\r
+ * in and out.  The two register test tasks do not use the same values, and\r
+ * execute at a very low priority, to ensure they are pre-empted regularly.\r
+ *\r
+ * "Check" timer - The check timer period is initially set to five seconds.  \r
+ * The check timer callback function checks that all the standard demo tasks,\r
+ * and the register check tasks, are not only still executing, but are executing\r
+ * without reporting any errors.  If the check timer discovers that a task has\r
+ * either stalled, or reported an error, then it changes its own period from\r
+ * the initial five seconds, to just 200ms.  The check timer callback function\r
+ * also toggles an LED each time it is called.  This provides a visual\r
+ * indication of the system status:  If the LED toggles every five seconds then\r
+ * no issues have been discovered.  If the LED toggles every 200ms then an issue\r
+ * has been discovered with at least one task.  The last reported issue is\r
+ * latched into the pcStatusMessage variable, and can also be viewed at the\r
+ * bottom of the pages served by the embedded web server.\r
+ *\r
+ * ***NOTE*** This demo uses the standard comtest tasks, which has special\r
+ * hardware requirements.  See\r
+ * http://www.FreeRTOS.org/Free-RTOS-for-Xilinx-MicroBlaze-on-Spartan-6-FPGA.html\r
+ * for more information.\r
+ *\r
+ * This file also includes example implementations of the\r
+ * vApplicationIdleHook(), vApplicationStackOverflowHook(),\r
+ * vApplicationMallocFailedHook(), vApplicationClearTimerInterrupt(), and\r
+ * vApplicationSetupTimerInterrupt() callback (hook) functions.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <string.h>\r
+#include <stdio.h>\r
+\r
+/* BSP includes. */\r
+#include "xtmrctr.h"\r
+#include "microblaze_exceptions_g.h"\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+\r
+/* Standard demo includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "blocktim.h"\r
+#include "semtest.h"\r
+#include "PollQ.h"\r
+#include "GenQTest.h"\r
+#include "QPeek.h"\r
+#include "recmutex.h"\r
+#include "flop.h"\r
+#include "dynamic.h"\r
+#include "comtest_strings.h"\r
+#include "TimerDemo.h"\r
+\r
+/* lwIP includes. */\r
+#include "lwip/tcpip.h"\r
+\r
+\r
+/* Priorities at which the various tasks are created. */\r
+#define mainQUEUE_POLL_PRIORITY                ( tskIDLE_PRIORITY + 1 )\r
+#define mainSEM_TEST_PRIORITY          ( tskIDLE_PRIORITY + 2 )\r
+#define mainBLOCK_Q_PRIORITY           ( tskIDLE_PRIORITY + 1 )\r
+#define mainCREATOR_TASK_PRIORITY   ( tskIDLE_PRIORITY + 3 )\r
+#define mainFLASH_TASK_PRIORITY                ( tskIDLE_PRIORITY + 1 )\r
+#define mainCOM_TEST_PRIORITY          ( tskIDLE_PRIORITY + 2 )\r
+#define mainINTEGER_TASK_PRIORITY   ( tskIDLE_PRIORITY )\r
+#define mainGEN_QUEUE_TASK_PRIORITY    ( tskIDLE_PRIORITY )\r
+#define mainFLOP_TASK_PRIORITY         ( tskIDLE_PRIORITY )\r
+\r
+/* The LED toggled by the check task. */\r
+#define mainCHECK_LED                          ( 3 )\r
+\r
+/* The rate at which mainCHECK_LED will toggle when all the tasks are running\r
+without error.  See the description of the check timer in the comments at the\r
+top of this file. */\r
+#define mainNO_ERROR_CHECK_TIMER_PERIOD                ( 5000 / portTICK_RATE_MS )\r
+\r
+/* The rate at which mainCHECK_LED will toggle when an error has been reported\r
+by at least one task.  See the description of the check timer in the comments at \r
+the top of this file. */\r
+#define mainERROR_CHECK_TIMER_PERIOD           ( 200 / portTICK_RATE_MS )\r
+\r
+/* A block time of zero simply means "don't block". */
+#define mainDONT_BLOCK                                         ( ( portTickType ) 0 )\r
+\r
+/* The LED used by the comtest tasks. See the comtest_strings.c file for more\r
+information.  In this case an invalid LED number is provided as all four\r
+available LEDs (LEDs 0 to 3) are already in use. */\r
+#define mainCOM_TEST_LED                       ( 4 )\r
+\r
+/* Baud rate used by the comtest tasks.  The baud rate used is actually fixed in \r
+UARTLite IP when the hardware was built, but the standard serial init function \r
+required a baud rate parameter to be provided - in this case it is just \r
+ignored. */\r
+#define mainCOM_TEST_BAUD_RATE                         ( XPAR_RS232_UART_1_BAUDRATE )\r
+\r
+/* The timer test task generates a lot of timers that all use a different \r
+period that is a multiple of the mainTIMER_TEST_PERIOD definition. */\r
+#define mainTIMER_TEST_PERIOD                  ( 20 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The register test tasks as described in the comments at the top of this file.\r
+ * The nature of the register test tasks means they have to be implemented in\r
+ * assembler.\r
+ */\r
+extern void vRegisterTest1( void *pvParameters );\r
+extern void vRegisterTest2( void *pvParameters );\r
+\r
+/*\r
+ * Defines the 'check' timer functionality as described at the top of this file.  \r
+ * This function is the callback function associated with the 'check' timer.\r
+ */\r
+static void vCheckTimerCallback( xTimerHandle xTimer );\r
+\r
+/* \r
+ * Configure the interrupt controller, LED outputs and button inputs. \r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/* Defined in lwIPApps.c. */\r
+extern void lwIPAppsInit( void *pvArguments );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The check timer callback function sets pcStatusMessage to a string that\r
+indicates the last reported error that it discovered. */\r
+static const char *pcStatusMessage = NULL;\r
+\r
+/* Structures that hold the state of the various peripherals used by this demo.\r
+These are used by the Xilinx peripheral driver API functions.  In this case,\r
+only the timer/counter is used directly within this file. */\r
+static XTmrCtr xTimer0Instance;\r
+\r
+/* The 'check' timer, as described at the top of this file. */\r
+static xTimerHandle xCheckTimer = NULL;\r
+\r
+/* Used in the run time stats calculations. */\r
+static unsigned long ulClocksPer10thOfAMilliSecond = 0UL;\r
+\r
+/* Constants used to set up the AXI timer to generate ticks. */\r
+static const unsigned char ucTimerCounterNumber = ( unsigned char ) 0U;\r
+static const unsigned long ulCounterReloadValue = ( ( XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ / configTICK_RATE_HZ ) - 1UL );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+       /***************************************************************************\r
+       This project includes a lot of demo and test tasks and timers,  and is \r
+       therefore comprehensive, but complex.  If you would prefer a much simpler \r
+       project to get started with, then select the 'Blinky' build configuration \r
+       within the SDK Eclipse IDE.\r
+       ***************************************************************************/\r
+\r
+       /* Configure the interrupt controller, LED outputs and button inputs. */\r
+       prvSetupHardware();\r
+\r
+       /* This call creates the TCP/IP thread. */\r
+       tcpip_init( lwIPAppsInit, NULL );\r
+\r
+       /* Start the reg test tasks, as described in the comments at the top of this\r
+       file. */\r
+       xTaskCreate( vRegisterTest1, ( const signed char * const ) "RegTst1", configMINIMAL_STACK_SIZE, ( void * ) 0, tskIDLE_PRIORITY, NULL );\r
+       xTaskCreate( vRegisterTest2, ( const signed char * const ) "RegTst2", configMINIMAL_STACK_SIZE, ( void * ) 0, tskIDLE_PRIORITY, NULL );\r
+\r
+       /* Create the standard demo tasks. */\r
+       vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+       vCreateBlockTimeTasks();\r
+       vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+       vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+       vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+       vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );\r
+       vStartQueuePeekTasks();\r
+       vStartRecursiveMutexTasks();\r
+       vStartComTestStringsTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+       vStartDynamicPriorityTasks();\r
+       vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
+\r
+       /* Note - the set of standard demo tasks contains two versions of\r
+       vStartMathTasks.c.  One is defined in flop.c, and uses double precision\r
+       floating point numbers and variables.  The other is defined in sp_flop.c,\r
+       and uses single precision floating point numbers and variables.  The\r
+       MicroBlaze floating point unit only handles single precision floating.\r
+       Therefore, to test the floating point hardware, sp_flop.c should be included\r
+       in this project. */\r
+       vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
+\r
+       /* The suicide tasks must be created last as they need to know how many\r
+       tasks were running prior to their creation.  This then allows them to \r
+       ascertain whether or not the correct/expected number of tasks are running at \r
+       any given time. */\r
+       vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+       /* Create the 'check' timer - the timer that periodically calls the\r
+       check function as described in the comments at the top of this file.  Note \r
+       that, for reasons stated in the comments within vApplicationIdleHook()\r
+       (defined in this file), the check timer is not actually started until after \r
+       the scheduler has been started. */\r
+       xCheckTimer = xTimerCreate( ( const signed char * ) "Check timer", mainNO_ERROR_CHECK_TIMER_PERIOD, pdTRUE, ( void * ) 0, vCheckTimerCallback );\r
+\r
+       /* Start the scheduler running.  From this point on, only tasks and \r
+       interrupts will be executing. */\r
+       vTaskStartScheduler();\r
+\r
+       /* If all is well then the following line will never be reached.  If\r
+       execution does reach here, then it is highly probably that the heap size\r
+       is too small for the idle and/or timer tasks to be created within \r
+       vTaskStartScheduler(). */\r
+       taskDISABLE_INTERRUPTS();\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCheckTimerCallback( xTimerHandle xTimer )\r
+{\r
+extern unsigned long ulRegTest1CycleCount, ulRegTest2CycleCount;\r
+static volatile unsigned long ulLastRegTest1CycleCount = 0UL, ulLastRegTest2CycleCount = 0UL;\r
+static long lErrorAlreadyLatched = pdFALSE;\r
+portTickType xExecutionRate = mainNO_ERROR_CHECK_TIMER_PERIOD;\r
+\r
+       /* This is the callback function used by the 'check' timer, as described\r
+       in the comments at the top of this file. */\r
+\r
+       /* Don't overwrite any errors that have already been latched. */\r
+       if( pcStatusMessage == NULL )\r
+       {\r
+               /* Check the standard demo tasks are running without error. */\r
+               if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+               {\r
+                       pcStatusMessage = "Error: GenQueue";\r
+               }\r
+               else if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+               {\r
+                       pcStatusMessage = "Error: QueuePeek\r\n";\r
+               }\r
+               else if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+               {\r
+                       pcStatusMessage = "Error: BlockQueue\r\n";\r
+               }\r
+               else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+               {\r
+                       pcStatusMessage = "Error: BlockTime\r\n";\r
+               }\r
+               else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+               {\r
+                       pcStatusMessage = "Error: SemTest\r\n";\r
+               }\r
+               else if( xArePollingQueuesStillRunning() != pdTRUE )\r
+               {\r
+                       pcStatusMessage = "Error: PollQueue\r\n";\r
+               }\r
+               else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+               {\r
+                       pcStatusMessage = "Error: Death\r\n";\r
+               }\r
+               else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+               {\r
+                       pcStatusMessage = "Error: RecMutex\r\n";\r
+               }\r
+               else if( xAreMathsTaskStillRunning() != pdPASS )\r
+               {\r
+                       pcStatusMessage = "Error: Flop\r\n";\r
+               }\r
+               else if( xAreComTestTasksStillRunning() != pdPASS )\r
+               {\r
+                       pcStatusMessage = "Error: Comtest\r\n";\r
+               }\r
+               else if( xAreDynamicPriorityTasksStillRunning() != pdPASS )\r
+               {\r
+                       pcStatusMessage = "Error: Dynamic\r\n";\r
+               }\r
+               else if( xAreTimerDemoTasksStillRunning( xExecutionRate ) != pdTRUE )\r
+               {\r
+                       pcStatusMessage = "Error: TimerDemo";\r
+               }\r
+               else if( ulRegTest1CycleCount == ulLastRegTest1CycleCount )\r
+               {\r
+                       /* Check the reg test tasks are still cycling.  They will stop\r
+                       incrementing their loop counters if they encounter an error. */\r
+                       pcStatusMessage = "Error: RegTest1\r\n";\r
+               }\r
+               else if( ulRegTest2CycleCount == ulLastRegTest2CycleCount )\r
+               {\r
+                       pcStatusMessage = "Error: RegTest2\r\n";\r
+               }\r
+       }\r
+\r
+       /* Store a local copy of the current reg test loop counters.  If these have\r
+       not incremented the next time this callback function is executed then the\r
+       reg test tasks have either stalled or discovered an error. */\r
+       ulLastRegTest1CycleCount = ulRegTest1CycleCount;\r
+       ulLastRegTest2CycleCount = ulRegTest2CycleCount;\r
+\r
+       /* Toggle the check LED to give an indication of the system status.  If\r
+       the LED toggles every 5 seconds then everything is ok.  A faster toggle\r
+       indicates an error. */\r
+       vParTestToggleLED( mainCHECK_LED );\r
+\r
+       if( pcStatusMessage != NULL )\r
+       {\r
+               if( lErrorAlreadyLatched == pdFALSE )\r
+               {\r
+                       /* An error has occurred, so change the period of the timer that\r
+                       calls this callback function.  This results in the LED toggling at\r
+                       a faster rate - giving the user visual feedback that something is not\r
+                       as it should be.  This function is called from the context of the\r
+                       timer service task so must ***not*** attempt to block while calling\r
+                       this function. */
+                       if( xTimerChangePeriod( xTimer, mainERROR_CHECK_TIMER_PERIOD, mainDONT_BLOCK ) == pdPASS )\r
+                       {\r
+                               /* If the command to change the timer period was sent to the\r
+                               timer command queue successfully, then latch the fact that the\r
+                               timer period has already been changed.  This is just done to\r
+                               prevent xTimerChangePeriod() being called on every execution of\r
+                               this function once an error has been discovered.  */\r
+                               lErrorAlreadyLatched = pdTRUE;\r
+                       }\r
+\r
+                       /* Update the xExecutionRate variable too as the rate at which this\r
+                       callback is executed has to be passed into the\r
+                       xAreTimerDemoTasksStillRunning() function. */\r
+                       xExecutionRate = mainERROR_CHECK_TIMER_PERIOD;\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is an application defined callback function used to install the tick\r
+interrupt handler.  It is provided as an application callback because the kernel\r
+will run on lots of different MicroBlaze and FPGA configurations - not all of\r
+which will have the same timer peripherals defined or available.  This example\r
+uses the AXI Timer 0.  If that is available on your hardware platform then this\r
+example callback implementation should not require modification.   The name of\r
+the interrupt handler that should be installed is vPortTickISR(), which the \r
+function below declares as an extern. */\r
+void vApplicationSetupTimerInterrupt( void )\r
+{\r
+portBASE_TYPE xStatus;\r
+extern void vPortTickISR( void *pvUnused );\r
+\r
+       /* Initialise the timer/counter. */\r
+       xStatus = XTmrCtr_Initialize( &xTimer0Instance, XPAR_AXI_TIMER_0_DEVICE_ID );\r
+\r
+       if( xStatus == XST_SUCCESS )\r
+       {\r
+               /* Install the tick interrupt handler as the timer ISR. \r
+               *NOTE* The xPortInstallInterruptHandler() API function must be used for\r
+               this purpose. */\r
+               xStatus = xPortInstallInterruptHandler( XPAR_INTC_0_TMRCTR_0_VEC_ID, vPortTickISR, NULL );\r
+       }\r
+\r
+       if( xStatus == pdPASS )\r
+       {\r
+               /* Enable the timer interrupt in the interrupt controller.\r
+               *NOTE* The vPortEnableInterrupt() API function must be used for this\r
+               purpose. */\r
+               vPortEnableInterrupt( XPAR_INTC_0_TMRCTR_0_VEC_ID );\r
+\r
+               /* Configure the timer interrupt handler. */\r
+               XTmrCtr_SetHandler( &xTimer0Instance, ( void * ) vPortTickISR, NULL );\r
+\r
+               /* Set the correct period for the timer. */\r
+               XTmrCtr_SetResetValue( &xTimer0Instance, ucTimerCounterNumber, ulCounterReloadValue );\r
+\r
+               /* Enable the interrupts.  Auto-reload mode is used to generate a\r
+               periodic tick.  Note that interrupts are disabled when this function is\r
+               called, so interrupts will not start to be processed until the first\r
+               task has started to run. */\r
+               XTmrCtr_SetOptions( &xTimer0Instance, ucTimerCounterNumber, ( XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION | XTC_DOWN_COUNT_OPTION ) );\r
+\r
+               /* Start the timer. */\r
+               XTmrCtr_Start( &xTimer0Instance, ucTimerCounterNumber );\r
+       }\r
+\r
+       /* Sanity check that the function executed as expected. */\r
+       configASSERT( ( xStatus == pdPASS ) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is an application defined callback function used to clear whichever\r
+interrupt was installed by the the vApplicationSetupTimerInterrupt() callback\r
+function - in this case the interrupt generated by the AXI timer.  It is \r
+provided as an application callback because the kernel will run on lots of \r
+different MicroBlaze and FPGA configurations - not all of which will have the \r
+same timer peripherals defined or available.  This example uses the AXI Timer 0.  \r
+If that is available on your hardware platform then this example callback \r
+implementation should not require modification provided the example definition\r
+of vApplicationSetupTimerInterrupt() is also not modified. */\r
+void vApplicationClearTimerInterrupt( void )\r
+{\r
+unsigned long ulCSR;\r
+\r
+       /* Clear the timer interrupt */\r
+       ulCSR = XTmrCtr_GetControlStatusReg( XPAR_AXI_TIMER_0_BASEADDR, 0 );\r
+       XTmrCtr_SetControlStatusReg( XPAR_AXI_TIMER_0_BASEADDR, 0, ulCSR );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+       /* vApplicationMallocFailedHook() will only be called if\r
+       configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h.  It is a hook\r
+       function that will get called if a call to pvPortMalloc() fails. \r
+       pvPortMalloc() is called internally by the kernel whenever a task, queue or\r
+       semaphore is created.  It is also called by various parts of the demo\r
+       application.  If heap_1.c or heap_2.c are used, then the size of the heap\r
+       available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+       FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+       to query the size of free heap space that remains (although it does not\r
+       provide information on how the remaining heap might be fragmented). */\r
+       taskDISABLE_INTERRUPTS();\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
+{\r
+       ( void ) pcTaskName;\r
+       ( void ) pxTask;\r
+\r
+       /* vApplicationStackOverflowHook() will only be called if\r
+       configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2.  The handle and name\r
+       of the offending task will be passed into the hook function via its \r
+       parameters.  However, when a stack has overflowed, it is possible that the\r
+       parameters will have been corrupted, in which case the pxCurrentTCB variable\r
+       can be inspected directly. */\r
+       taskDISABLE_INTERRUPTS();\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+static long lCheckTimerStarted = pdFALSE;\r
+\r
+       /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set \r
+       to 1 in FreeRTOSConfig.h.  It will be called on each iteration of the idle \r
+       task.  It is essential that code added to this hook function never attempts \r
+       to block in any way (for example, call xQueueReceive() with a block time \r
+       specified, or call vTaskDelay()).  If the application makes use of the \r
+       vTaskDelete() API function (as this demo application does) then it is also \r
+       important that vApplicationIdleHook() is permitted to return to its calling \r
+       function, because it is the responsibility of the idle task to clean up \r
+       memory allocated by the kernel to any task that has since been deleted. */\r
+\r
+       /* If the check timer has not already been started, then start it now.\r
+       Normally, the xTimerStart() API function can be called immediately after the\r
+       timer is created - how this demo application includes the timer demo tasks.\r
+       The timer demo tasks, as part of their test function, deliberately fill up\r
+       the timer command queue - meaning the check timer cannot be started until\r
+       after the scheduler has been started - at which point the timer command\r
+       queue will have been drained. */\r
+       if( lCheckTimerStarted == pdFALSE )\r
+       {\r
+               xTimerStart( xCheckTimer, mainDONT_BLOCK ); \r
+               lCheckTimerStarted = pdTRUE;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )\r
+{\r
+       ( void ) xRegisterDump;\r
+\r
+       /* If configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h, then \r
+       the kernel will automatically install its own exception handlers before the \r
+       kernel is started, if the application writer has not already caused them to \r
+       be installed by calling either of the vPortExceptionsInstallHandlers() \r
+       or xPortInstallInterruptHandler() API functions before that time.  The \r
+       kernels exception handler populates an xPortRegisterDump structure with\r
+       the processor state at the point that the exception was triggered - and also\r
+       includes a strings that say what the exception cause was and which task was\r
+       running at the time.  The exception handler then passes the populated\r
+       xPortRegisterDump structure into vApplicationExceptionRegisterDump() to\r
+       allow the application writer to perform any debugging that may be necessary.\r
+       However, defining vApplicationExceptionRegisterDump() within the application\r
+       itself is optional.  The kernel will use a default implementation if the\r
+       application writer chooses not to provide their own. */\r
+       for( ;; )\r
+       {\r
+               portNOP();\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+       taskDISABLE_INTERRUPTS();\r
+       \r
+       /* Configure the LED outputs. */\r
+       vParTestInitialise();\r
+\r
+       /* Tasks inherit the exception and cache configuration of the MicroBlaze\r
+       at the point that they are created. */\r
+       #if MICROBLAZE_EXCEPTIONS_ENABLED == 1\r
+               microblaze_enable_exceptions();\r
+       #endif\r
+\r
+       #if XPAR_MICROBLAZE_USE_ICACHE == 1\r
+               microblaze_invalidate_icache();\r
+               microblaze_enable_icache();\r
+       #endif\r
+\r
+       #if XPAR_MICROBLAZE_USE_DCACHE == 1\r
+               microblaze_invalidate_dcache();\r
+               microblaze_enable_dcache();\r
+       #endif\r
+\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vMainConfigureTimerForRunTimeStats( void )\r
+{\r
+       /* How many times does the counter counter increment in 10ms? */\r
+       ulClocksPer10thOfAMilliSecond = XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ / 10000UL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned long ulMainGetRunTimeCounterValue( void )\r
+{\r
+unsigned long ulTimerCounts1, ulTimerCounts2, ulTickCount, ulReturn;\r
+\r
+       /* NOTE: This can get called from a yield, in which case interrupts are\r
+       disabled, or from a tick ISR, in which case the effect is the same as if\r
+       interrupts were disabled.  In either case, it is going to run atomically. */\r
+\r
+       /* The timer is in down count mode.  How many clocks have passed since it\r
+       was last reloaded? */\r
+       ulTimerCounts1 = ulCounterReloadValue - XTmrCtr_GetValue( &xTimer0Instance, ucTimerCounterNumber );\r
+\r
+       /* How many times has it overflowed? */\r
+       ulTickCount = xTaskGetTickCountFromISR();\r
+\r
+       /* If this is being called from a yield, has the counter overflowed since\r
+       it was read?  If that is the case then ulTickCounts will need incrementing\r
+       again as it will not yet have been incremented from the tick interrupt. */
+       ulTimerCounts2 = ulCounterReloadValue - XTmrCtr_GetValue( &xTimer0Instance, ucTimerCounterNumber );\r
+       if( ulTimerCounts2 < ulTimerCounts1 )\r
+       {\r
+               /* There is a tick interrupt pending but the tick count not yet\r
+               incremented. */\r
+               ulTickCount++;\r
+\r
+               /* Use the second timer reading. */\r
+               ulTimerCounts1 = ulTimerCounts2;\r
+       }\r
+\r
+       /* Convert the tick count into tenths of a millisecond.  THIS ASSUMES\r
+       configTICK_RATE_HZ is 1000! */\r
+       ulReturn = ( ulTickCount * 10UL );\r
+\r
+       /* Add on the number of tenths of a millisecond that have passed since the\r
+       tick count last got updated. */\r
+       ulReturn += ( ulTimerCounts1 / ulClocksPer10thOfAMilliSecond );\r
+\r
+       /* Some crude rounding. */\r
+       if( ( ulTimerCounts1 % ulClocksPer10thOfAMilliSecond ) > ( ulClocksPer10thOfAMilliSecond >> 1UL ) )\r
+       {\r
+               ulReturn++;\r
+       }\r
+\r
+       return ulReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+char *pcMainGetTaskStatusMessage( void )\r
+{\r
+char * pcReturn;\r
+\r
+       if( pcStatusMessage == NULL )\r
+       {\r
+               pcReturn = ( char * ) "OK";\r
+       }\r
+       else\r
+       {\r
+               pcReturn = ( char * ) pcStatusMessage;\r
+       }\r
+\r
+       return pcReturn;\r
+}\r
+\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/printf-stdarg.c b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/printf-stdarg.c
new file mode 100644 (file)
index 0000000..e93d97b
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/printf-stdarg.c
@@ -0,0 +1,282 @@
+/*\r
+       Copyright 2001, 2002 Georges Menie (www.menie.org)\r
+       stdarg version contributed by Christian Ettinger\r
+\r
+    This program is free software; you can redistribute it and/or modify\r
+    it under the terms of the GNU Lesser General Public License as published by\r
+    the Free Software Foundation; either version 2 of the License, or\r
+    (at your option) any later version.\r
+\r
+    This program is distributed in the hope that it will be useful,\r
+    but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+    GNU Lesser General Public License for more details.\r
+\r
+    You should have received a copy of the GNU Lesser General Public License\r
+    along with this program; if not, write to the Free Software\r
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+*/\r
+\r
+/*\r
+       putchar is the only external dependency for this file,\r
+       if you have a working putchar, leave it commented out.\r
+       If not, uncomment the define below and\r
+       replace outbyte(c) by your own function call.\r
+\r
+#define putchar(c) outbyte(c)\r
+*/\r
+\r
+#include <stdarg.h>\r
+\r
+static void printchar(char **str, int c)\r
+{\r
+       extern int putchar(int c);\r
+       \r
+       if (str) {\r
+               **str = c;\r
+               ++(*str);\r
+       }\r
+       else (void)putchar(c);\r
+}\r
+\r
+#define PAD_RIGHT 1\r
+#define PAD_ZERO 2\r
+\r
+static int prints(char **out, const char *string, int width, int pad)\r
+{\r
+       register int pc = 0, padchar = ' ';\r
+\r
+       if (width > 0) {\r
+               register int len = 0;\r
+               register const char *ptr;\r
+               for (ptr = string; *ptr; ++ptr) ++len;\r
+               if (len >= width) width = 0;\r
+               else width -= len;\r
+               if (pad & PAD_ZERO) padchar = '0';\r
+       }\r
+       if (!(pad & PAD_RIGHT)) {\r
+               for ( ; width > 0; --width) {\r
+                       printchar (out, padchar);\r
+                       ++pc;\r
+               }\r
+       }\r
+       for ( ; *string ; ++string) {\r
+               printchar (out, *string);\r
+               ++pc;\r
+       }\r
+       for ( ; width > 0; --width) {\r
+               printchar (out, padchar);\r
+               ++pc;\r
+       }\r
+\r
+       return pc;\r
+}\r
+\r
+/* the following should be enough for 32 bit int */\r
+#define PRINT_BUF_LEN 12\r
+\r
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)\r
+{\r
+       char print_buf[PRINT_BUF_LEN];\r
+       register char *s;\r
+       register int t, neg = 0, pc = 0;\r
+       register unsigned int u = i;\r
+\r
+       if (i == 0) {\r
+               print_buf[0] = '0';\r
+               print_buf[1] = '\0';\r
+               return prints (out, print_buf, width, pad);\r
+       }\r
+\r
+       if (sg && b == 10 && i < 0) {\r
+               neg = 1;\r
+               u = -i;\r
+       }\r
+\r
+       s = print_buf + PRINT_BUF_LEN-1;\r
+       *s = '\0';\r
+\r
+       while (u) {\r
+               t = u % b;\r
+               if( t >= 10 )\r
+                       t += letbase - '0' - 10;\r
+               *--s = t + '0';\r
+               u /= b;\r
+       }\r
+\r
+       if (neg) {\r
+               if( width && (pad & PAD_ZERO) ) {\r
+                       printchar (out, '-');\r
+                       ++pc;\r
+                       --width;\r
+               }\r
+               else {\r
+                       *--s = '-';\r
+               }\r
+       }\r
+\r
+       return pc + prints (out, s, width, pad);\r
+}\r
+\r
+static int print( char **out, const char *format, va_list args )\r
+{\r
+       register int width, pad;\r
+       register int pc = 0;\r
+       char scr[2];\r
+\r
+       for (; *format != 0; ++format) {\r
+               if (*format == '%') {\r
+                       ++format;\r
+                       width = pad = 0;\r
+                       if (*format == '\0') break;\r
+                       if (*format == '%') goto out;\r
+                       if (*format == '-') {\r
+                               ++format;\r
+                               pad = PAD_RIGHT;\r
+                       }\r
+                       while (*format == '0') {\r
+                               ++format;\r
+                               pad |= PAD_ZERO;\r
+                       }\r
+                       for ( ; *format >= '0' && *format <= '9'; ++format) {\r
+                               width *= 10;\r
+                               width += *format - '0';\r
+                       }\r
+                       if( *format == 's' ) {\r
+                               register char *s = (char *)va_arg( args, int );\r
+                               pc += prints (out, s?s:"(null)", width, pad);\r
+                               continue;\r
+                       }\r
+                       if( *format == 'd' ) {\r
+                               pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'x' ) {\r
+                               pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'X' ) {\r
+                               pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'u' ) {\r
+                               pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'c' ) {\r
+                               /* char are converted to int then pushed on the stack */\r
+                               scr[0] = (char)va_arg( args, int );\r
+                               scr[1] = '\0';\r
+                               pc += prints (out, scr, width, pad);\r
+                               continue;\r
+                       }\r
+               }\r
+               else {\r
+               out:\r
+                       printchar (out, *format);\r
+                       ++pc;\r
+               }\r
+       }\r
+       if (out) **out = '\0';\r
+       va_end( args );\r
+       return pc;\r
+}\r
+\r
+int printf(const char *format, ...)\r
+{\r
+        va_list args;\r
+        \r
+        va_start( args, format );\r
+        return print( 0, format, args );\r
+}\r
+\r
+int sprintf(char *out, const char *format, ...)\r
+{\r
+        va_list args;\r
+        \r
+        va_start( args, format );\r
+        return print( &out, format, args );\r
+}\r
+\r
+\r
+int snprintf( char *buf, unsigned int count, const char *format, ... )\r
+{\r
+        va_list args;\r
+        \r
+        ( void ) count;\r
+        \r
+        va_start( args, format );\r
+        return print( &buf, format, args );\r
+}\r
+\r
+\r
+#ifdef TEST_PRINTF\r
+int main(void)\r
+{\r
+       char *ptr = "Hello world!";\r
+       char *np = 0;\r
+       int i = 5;\r
+       unsigned int bs = sizeof(int)*8;\r
+       int mi;\r
+       char buf[80];\r
+\r
+       mi = (1 << (bs-1)) + 1;\r
+       printf("%s\n", ptr);\r
+       printf("printf test\n");\r
+       printf("%s is null pointer\n", np);\r
+       printf("%d = 5\n", i);\r
+       printf("%d = - max int\n", mi);\r
+       printf("char %c = 'a'\n", 'a');\r
+       printf("hex %x = ff\n", 0xff);\r
+       printf("hex %02x = 00\n", 0);\r
+       printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);\r
+       printf("%d %s(s)%", 0, "message");\r
+       printf("\n");\r
+       printf("%d %s(s) with %%\n", 0, "message");\r
+       sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);\r
+       sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);\r
+       sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);\r
+       sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);\r
+       sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);\r
+       sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);\r
+       sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);\r
+       sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);\r
+\r
+       return 0;\r
+}\r
+\r
+/*\r
+ * if you compile this file with\r
+ *   gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c\r
+ * you will get a normal warning:\r
+ *   printf.c:214: warning: spurious trailing `%' in format\r
+ * this line is testing an invalid % at the end of the format string.\r
+ *\r
+ * this should display (on 32bit int machine) :\r
+ *\r
+ * Hello world!\r
+ * printf test\r
+ * (null) is null pointer\r
+ * 5 = 5\r
+ * -2147483647 = - max int\r
+ * char a = 'a'\r
+ * hex ff = ff\r
+ * hex 00 = 00\r
+ * signed -3 = unsigned 4294967293 = hex fffffffd\r
+ * 0 message(s)\r
+ * 0 message(s) with %\r
+ * justif: "left      "\r
+ * justif: "     right"\r
+ *  3: 0003 zero padded\r
+ *  3: 3    left justif.\r
+ *  3:    3 right justif.\r
+ * -3: -003 zero padded\r
+ * -3: -3   left justif.\r
+ * -3:   -3 right justif.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/serial.c b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/serial.c
new file mode 100644 (file)
index 0000000..f32e40a
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/serial.c
@@ -0,0 +1,209 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+       \r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/*\r
+       BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR a UARTLite peripheral.\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "comtest_strings.h"\r
+\r
+/* Library includes. */\r
+#include "xuartlite.h"\r
+#include "xuartlite_l.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Functions that are installed as the handler for interrupts that are caused by\r
+Rx and Tx events respectively. */\r
+static void prvRxHandler( void *pvUnused, unsigned portBASE_TYPE uxByteCount );\r
+static void prvTxHandler( void *pvUnused, unsigned portBASE_TYPE uxByteCount );\r
+\r
+/* Structure that hold the state of the UARTLite peripheral used by this demo.\r
+This is used by the Xilinx peripheral driver API functions. */\r
+static XUartLite xUartLiteInstance;\r
+\r
+/* The queue used to hold received characters. */\r
+static xQueueHandle xRxedChars;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+portBASE_TYPE xStatus;\r
+\r
+       /* The standard demo header file requires a baud rate to be passed into this\r
+       function.  However, in this case the baud rate is configured when the\r
+       hardware is generated, leaving the ulWantedBaud parameter redundant. */\r
+       ( void ) ulWantedBaud;\r
+\r
+       /* Create the queue used to hold Rx characters. */\r
+       xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
+\r
+       /* If the queue was created correctly, then setup the serial port\r
+       hardware. */\r
+       if( xRxedChars != NULL )\r
+       {\r
+               xStatus = XUartLite_Initialize( &xUartLiteInstance, XPAR_UARTLITE_1_DEVICE_ID );\r
+\r
+               if( xStatus == XST_SUCCESS )\r
+               {\r
+                       /* Complete initialisation of the UART and its associated\r
+                       interrupts. */\r
+                       XUartLite_ResetFifos( &xUartLiteInstance );\r
+                       \r
+                       /* Install the handlers that the standard Xilinx library interrupt\r
+                       service routine will call when Rx and Tx events occur \r
+                       respectively. */\r
+                       XUartLite_SetRecvHandler( &xUartLiteInstance, ( XUartLite_Handler ) prvRxHandler, NULL );\r
+                       XUartLite_SetSendHandler( &xUartLiteInstance, ( XUartLite_Handler ) prvTxHandler, NULL );\r
+                       \r
+                       /* Install the standard Xilinx library interrupt handler itself.\r
+                       *NOTE* The xPortInstallInterruptHandler() API function must be used \r
+                       for     this purpose. */                        \r
+                       xStatus = xPortInstallInterruptHandler( XPAR_INTC_0_UARTLITE_1_VEC_ID, ( XInterruptHandler ) XUartLite_InterruptHandler, &xUartLiteInstance );\r
+                       \r
+                       /* Enable the interrupt in the peripheral. */\r
+                       XUartLite_EnableIntr( xUartLiteInstance.RegBaseAddress );\r
+                       \r
+                       /* Enable the interrupt in the interrupt controller.\r
+                       *NOTE* The vPortEnableInterrupt() API function must be used for this\r
+                       purpose. */\r
+                       vPortEnableInterrupt( XPAR_INTC_0_UARTLITE_1_VEC_ID );\r
+               }\r
+\r
+               configASSERT( xStatus == pdPASS );\r
+       }\r
+\r
+       /* This demo file only supports a single port but something must be\r
+       returned to comply with the standard demo header file. */\r
+       return ( xComPortHandle ) 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )\r
+{\r
+       /* The port handle is not required as this driver only supports one port. */\r
+       ( void ) pxPort;\r
+\r
+       /* Get the next character from the receive queue.  Return false if no \r
+       characters are available, or arrive before xBlockTime expires. */\r
+       if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+       {\r
+               return pdTRUE;\r
+       }\r
+       else\r
+       {\r
+               return pdFALSE;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )\r
+{\r
+       ( void ) pxPort;\r
+\r
+       /* Output uxStringLength bytes starting from pcString. */\r
+       XUartLite_Send( &xUartLiteInstance, ( unsigned char * ) pcString, usStringLength );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRxHandler( void *pvUnused, unsigned portBASE_TYPE uxByteCount )\r
+{\r
+signed char cRxedChar;\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+       ( void ) pvUnused;\r
+       ( void ) uxByteCount;\r
+\r
+       /* Place any received characters into the receive queue. */\r
+       while( XUartLite_IsReceiveEmpty( xUartLiteInstance.RegBaseAddress ) == pdFALSE )\r
+       {\r
+               cRxedChar = XUartLite_ReadReg( xUartLiteInstance.RegBaseAddress, XUL_RX_FIFO_OFFSET);\r
+               xQueueSendFromISR( xRxedChars, &cRxedChar, &xHigherPriorityTaskWoken );\r
+       }\r
+\r
+       /* If calling xQueueSendFromISR() caused a task to unblock, and the task \r
+       that unblocked has a priority equal to or greater than the task currently\r
+       in the Running state (the task that was interrupted), then \r
+       xHigherPriorityTaskWoken will have been set to pdTRUE internally within the\r
+       xQueueSendFromISR() API function.  If xHigherPriorityTaskWoken is equal to\r
+       pdTRUE then a context switch should be requested to ensure that the \r
+       interrupt returns to the highest priority task that is able     to run. */\r
+       portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTxHandler( void *pvUnused, unsigned portBASE_TYPE uxByteCount )\r
+{\r
+       ( void ) pvUnused;\r
+       ( void ) uxByteCount;\r
+\r
+       /* Nothing to do here.  The Xilinx library function takes care of the\r
+       transmission. */\r
+       portNOP();\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+       \r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/src/README.txt b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/src/README.txt
new file mode 100644 (file)
index 0000000..c4d32ef
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/src/README.txt
@@ -0,0 +1 @@
+Empty application. Add your own sources.

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/src/lscript.ld b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/src/lscript.ld
new file mode 100644 (file)
index 0000000..85a61d6
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/RTOSDemo/src/lscript.ld
@@ -0,0 +1,213 @@
+/*******************************************************************/\r
+/*                                                                 */\r
+/* This file is automatically generated by linker script generator.*/\r
+/*                                                                 */\r
+/* Version: Xilinx EDK 13.1 EDK_O.40d                                */\r
+/*                                                                 */\r
+/* Copyright (c) 2010 Xilinx, Inc.  All rights reserved.           */\r
+/*                                                                 */\r
+/* Description : MicroBlaze Linker Script                          */\r
+/*                                                                 */\r
+/*******************************************************************/\r
+\r
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;\r
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x10000;\r
+\r
+/* Define Memories in the system */\r
+\r
+MEMORY\r
+{\r
+   microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl : ORIGIN = 0x00000050, LENGTH = 0x00001FB0\r
+   MCB_DDR3_S0_AXI_BASEADDR : ORIGIN = 0x80000000, LENGTH = 0x00800000\r
+}\r
+\r
+/* Specify the default entry point to the program */\r
+\r
+ENTRY(_start)\r
+\r
+/* Define the sections, and where they are mapped in memory */\r
+\r
+SECTIONS\r
+{\r
+.vectors.reset 0x00000000 : {\r
+   *(.vectors.reset)\r
+} \r
+\r
+.vectors.sw_exception 0x00000008 : {\r
+   *(.vectors.sw_exception)\r
+} \r
+\r
+.vectors.interrupt 0x00000010 : {\r
+   *(.vectors.interrupt)\r
+} \r
+\r
+.vectors.hw_exception 0x00000020 : {\r
+   *(.vectors.hw_exception)\r
+} \r
+\r
+.text : {\r
+   *(.text)\r
+   *(.text.*)\r
+   *(.gnu.linkonce.t.*)\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.init : {\r
+   KEEP (*(.init))\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.fini : {\r
+   KEEP (*(.fini))\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.rodata : {\r
+   __rodata_start = .;\r
+   *(.rodata)\r
+   *(.rodata.*)\r
+   *(.gnu.linkonce.r.*)\r
+   __rodata_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.sdata2 : {\r
+   . = ALIGN(8);\r
+   __sdata2_start = .;\r
+   *(.sdata2)\r
+   *(.sdata2.*)\r
+   *(.gnu.linkonce.s2.*)\r
+   . = ALIGN(8);\r
+   __sdata2_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.sbss2 : {\r
+   __sbss2_start = .;\r
+   *(.sbss2)\r
+   *(.sbss2.*)\r
+   *(.gnu.linkonce.sb2.*)\r
+   __sbss2_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.data : {\r
+   . = ALIGN(4);\r
+   __data_start = .;\r
+   *(.data)\r
+   *(.data.*)\r
+   *(.gnu.linkonce.d.*)\r
+   __data_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.got : {\r
+   *(.got)\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.got1 : {\r
+   *(.got1)\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.got2 : {\r
+   *(.got2)\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.ctors : {\r
+   __CTOR_LIST__ = .;\r
+   ___CTORS_LIST___ = .;\r
+   KEEP (*crtbegin.o(.ctors))\r
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))\r
+   KEEP (*(SORT(.ctors.*)))\r
+   KEEP (*(.ctors))\r
+   __CTOR_END__ = .;\r
+   ___CTORS_END___ = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.dtors : {\r
+   __DTOR_LIST__ = .;\r
+   ___DTORS_LIST___ = .;\r
+   KEEP (*crtbegin.o(.dtors))\r
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))\r
+   KEEP (*(SORT(.dtors.*)))\r
+   KEEP (*(.dtors))\r
+   __DTOR_END__ = .;\r
+   ___DTORS_END___ = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.eh_frame : {\r
+   *(.eh_frame)\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.jcr : {\r
+   *(.jcr)\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.gcc_except_table : {\r
+   *(.gcc_except_table)\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.sdata : {\r
+   . = ALIGN(8);\r
+   __sdata_start = .;\r
+   *(.sdata)\r
+   *(.sdata.*)\r
+   *(.gnu.linkonce.s.*)\r
+   __sdata_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.sbss : {\r
+   . = ALIGN(4);\r
+   __sbss_start = .;\r
+   *(.sbss)\r
+   *(.sbss.*)\r
+   *(.gnu.linkonce.sb.*)\r
+   . = ALIGN(8);\r
+   __sbss_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.tdata : {\r
+   __tdata_start = .;\r
+   *(.tdata)\r
+   *(.tdata.*)\r
+   *(.gnu.linkonce.td.*)\r
+   __tdata_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.tbss : {\r
+   __tbss_start = .;\r
+   *(.tbss)\r
+   *(.tbss.*)\r
+   *(.gnu.linkonce.tb.*)\r
+   __tbss_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.bss : {\r
+   . = ALIGN(4);\r
+   __bss_start = .;\r
+   *(.bss)\r
+   *(.bss.*)\r
+   *(.gnu.linkonce.b.*)\r
+   *(COMMON)\r
+   . = ALIGN(4);\r
+   __bss_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );\r
+\r
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );\r
+\r
+/* Generate Stack and Heap definitions */\r
+\r
+.heap : {\r
+   . = ALIGN(8);\r
+   _heap = .;\r
+   _heap_start = .;\r
+   . += _HEAP_SIZE;\r
+   _heap_end = .;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+.stack : {\r
+   _stack_end = .;\r
+   . += _STACK_SIZE;\r
+   . = ALIGN(8);\r
+   _stack = .;\r
+   __stack = _stack;\r
+} > MCB_DDR3_S0_AXI_BASEADDR\r
+\r
+_end = .;\r
+}\r
+\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/.cproject b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/.cproject
new file mode 100644 (file)
index 0000000..47795f5
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/.cproject
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 4.0.0?>\r
+\r
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
+       <storageModule moduleId="org.eclipse.cdt.core.settings">\r
+               <cconfiguration id="org.eclipse.cdt.core.default.config.1232762083">\r
+                       <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1232762083" moduleId="org.eclipse.cdt.core.settings" name="Configuration">\r
+                               <externalSettings/>\r
+                               <extensions/>\r
+                       </storageModule>\r
+                       <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+               </cconfiguration>\r
+       </storageModule>\r
+</cproject>\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/.project b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/.project
new file mode 100644 (file)
index 0000000..0b1da09
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/.project
@@ -0,0 +1,77 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+       <name>StandAloneBSP</name>\r
+       <comment></comment>\r
+       <projects>\r
+               <project>HardwareWithEthernetFull</project>\r
+       </projects>\r
+       <buildSpec>\r
+               <buildCommand>\r
+                       <name>org.eclipse.cdt.make.core.makeBuilder</name>\r
+                       <triggers>clean,full,incremental,</triggers>\r
+                       <arguments>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.core.errorOutputParser</key>\r
+                                       <value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.append_environment</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.build.arguments</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.build.command</key>\r
+                                       <value>make</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.build.target.auto</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.build.target.clean</key>\r
+                                       <value>clean</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.build.target.inc</key>\r
+                                       <value>all</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableAutoBuild</key>\r
+                                       <value>false</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableCleanBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enableFullBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.environment</key>\r
+                                       <value></value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.stopOnError</key>\r
+                                       <value>false</value>\r
+                               </dictionary>\r
+                               <dictionary>\r
+                                       <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>\r
+                                       <value>true</value>\r
+                               </dictionary>\r
+                       </arguments>\r
+               </buildCommand>\r
+       </buildSpec>\r
+       <natures>\r
+               <nature>com.xilinx.sdk.sw.SwProjectNature</nature>\r
+               <nature>org.eclipse.cdt.core.cnature</nature>\r
+               <nature>org.eclipse.cdt.make.core.makeNature</nature>\r
+       </natures>\r
+</projectDescription>\r

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/.sdkproject b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/.sdkproject
new file mode 100644 (file)
index 0000000..d75738c
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/.sdkproject
@@ -0,0 +1,3 @@
+THIRPARTY=false
+PROCESSOR=microblaze_0
+MSS_FILE=system.mss

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/Makefile b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/Makefile
new file mode 100644 (file)
index 0000000..fe2a0ef
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/Makefile
@@ -0,0 +1,21 @@
+# Makefile generated by Xilinx SDK.
+
+-include libgen.options
+
+LIBRARIES = ${PROCESSOR}/lib/libxil.a
+MSS = system.mss
+
+all: libs
+       @echo 'Finished building libraries'
+
+libs: $(LIBRARIES)
+
+$(LIBRARIES): $(MSS)
+       libgen -hw ${HWSPEC}\
+              ${REPOSITORIES}\
+              -pe ${PROCESSOR} \
+              -log libgen.log \
+              $(MSS)
+
+clean:
+       rm -rf ${PROCESSOR}

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/libgen.log b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/libgen.log
new file mode 100644 (file)
index 0000000..23782ce
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/libgen.log
@@ -0,0 +1,20 @@
+Release 13.1 - libgen Xilinx EDK 13.1 Build EDK_O.40d
+ (nt)
+Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
+
+Command Line: libgen -hw ../HardwareWithEthernetFull/system.xml -lp\r
+../../KernelAwareBSPRepository -pe microblaze_0 -log libgen.log system.mss 
+
+
+Staging source files.
+Running DRCs.
+Running generate.
+Running post_generate.
+Running include - 'make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar"\r
+"COMPILER_FLAGS=-mlittle-endian -mno-xl-soft-mul -mxl-barrel-shift\r
+-mxl-pattern-compare -mcpu=v8.10.a  -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.
+
+Running libs - 'make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar"\r
+"COMPILER_FLAGS=-mlittle-endian -mno-xl-soft-mul -mxl-barrel-shift\r
+-mxl-pattern-compare -mcpu=v8.10.a  -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.
+Running execs_generate.

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/libgen.options b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/libgen.options
new file mode 100644 (file)
index 0000000..4dbed55
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/libgen.options
@@ -0,0 +1,3 @@
+PROCESSOR=microblaze_0
+REPOSITORIES=-lp ../../KernelAwareBSPRepository
+HWSPEC=../HardwareWithEthernetFull/system.xml

diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/system.mss b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/system.mss
new file mode 100644 (file)
index 0000000..e72c63e
--- /dev/null
+++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/SDKProjects/StandAloneBSP/system.mss
@@ -0,0 +1,87 @@
+\r
+ PARAMETER VERSION = 2.2.0\r
+\r
+\r
+BEGIN OS\r
+ PARAMETER OS_NAME = standalone\r
+ PARAMETER OS_VER = 3.01.a\r
+ PARAMETER PROC_INSTANCE = microblaze_0\r
+ PARAMETER STDIN = RS232_Uart_1\r
+ PARAMETER STDOUT = RS232_Uart_1\r
+END\r
+\r
+\r
+BEGIN PROCESSOR\r
+ PARAMETER DRIVER_NAME = cpu\r
+ PARAMETER DRIVER_VER = 1.13.a\r
+ PARAMETER HW_INSTANCE = microblaze_0\r
+END\r
+\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = axiethernet\r
+ PARAMETER DRIVER_VER = 1.01.a\r
+ PARAMETER HW_INSTANCE = ETHERNET\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = axidma\r
+ PARAMETER DRIVER_VER = 3.00.a\r
+ PARAMETER HW_INSTANCE = ETHERNET_dma\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = gpio\r
+ PARAMETER DRIVER_VER = 3.00.a\r
+ PARAMETER HW_INSTANCE = LEDs_4Bits\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = gpio\r
+ PARAMETER DRIVER_VER = 3.00.a\r
+ PARAMETER HW_INSTANCE = Push_Buttons_4Bits\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = uartlite\r
+ PARAMETER DRIVER_VER = 2.00.a\r
+ PARAMETER HW_INSTANCE = RS232_Uart_1\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = tmrctr\r
+ PARAMETER DRIVER_VER = 2.03.a\r
+ PARAMETER HW_INSTANCE = axi_timer_0\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = uartlite\r
+ PARAMETER DRIVER_VER = 2.00.a\r
+ PARAMETER HW_INSTANCE = debug_module\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = bram\r
+ PARAMETER DRIVER_VER = 3.00.a\r
+ PARAMETER HW_INSTANCE = microblaze_0_d_bram_ctrl\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = bram\r
+ PARAMETER DRIVER_VER = 3.00.a\r
+ PARAMETER HW_INSTANCE = microblaze_0_i_bram_ctrl\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = intc\r
+ PARAMETER DRIVER_VER = 2.02.a\r
+ PARAMETER HW_INSTANCE = microblaze_0_intc\r
+END\r
+\r
+BEGIN DRIVER\r
+ PARAMETER DRIVER_NAME = s6_ddrx\r
+ PARAMETER DRIVER_VER = 1.00.a\r
+ PARAMETER HW_INSTANCE = MCB_DDR3\r
+END\r
+\r
+\r