}
}
-inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
+/* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
+__inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
{
/* while the sector list isn't built, only accesses to sector 0 work */
if (sector == 0)
flash_errmsg(int err);
#ifndef __ECOS
-#define FLASH_ERR_OK 0x00 // No error - operation complete
-#define FLASH_ERR_INVALID 0x01 // Invalid FLASH address
-#define FLASH_ERR_ERASE 0x02 // Error trying to erase
-#define FLASH_ERR_LOCK 0x03 // Error trying to lock/unlock
-#define FLASH_ERR_PROGRAM 0x04 // Error trying to program
-#define FLASH_ERR_PROTOCOL 0x05 // Generic error
-#define FLASH_ERR_PROTECT 0x06 // Device/region is write-protected
-#define FLASH_ERR_NOT_INIT 0x07 // FLASH info not yet initialized
-#define FLASH_ERR_HWR 0x08 // Hardware (configuration?) problem
-#define FLASH_ERR_ERASE_SUSPEND 0x09 // Device is in erase suspend mode
-#define FLASH_ERR_PROGRAM_SUSPEND 0x0a // Device is in in program suspend mode
-#define FLASH_ERR_DRV_VERIFY 0x0b // Driver failed to verify data
-#define FLASH_ERR_DRV_TIMEOUT 0x0c // Driver timed out waiting for device
-#define FLASH_ERR_DRV_WRONG_PART 0x0d // Driver does not support device
-#define FLASH_ERR_LOW_VOLTAGE 0x0e // Not enough juice to complete job
+#define FLASH_ERR_OK 0x00 /* No error - operation complete */
+#define FLASH_ERR_INVALID 0x01 /* Invalid FLASH address */
+#define FLASH_ERR_ERASE 0x02 /* Error trying to erase */
+#define FLASH_ERR_LOCK 0x03 /* Error trying to lock/unlock */
+#define FLASH_ERR_PROGRAM 0x04 /* Error trying to program */
+#define FLASH_ERR_PROTOCOL 0x05 /* Generic error */
+#define FLASH_ERR_PROTECT 0x06 /* Device/region is write-protected */
+#define FLASH_ERR_NOT_INIT 0x07 /* FLASH info not yet initialized */
+#define FLASH_ERR_HWR 0x08 /* Hardware (configuration?) problem */
+#define FLASH_ERR_ERASE_SUSPEND 0x09 /* Device is in erase suspend mode */
+#define FLASH_ERR_PROGRAM_SUSPEND 0x0a /* Device is in in program suspend mode */
+#define FLASH_ERR_DRV_VERIFY 0x0b /* Driver failed to verify data */
+#define FLASH_ERR_DRV_TIMEOUT 0x0c /* Driver timed out waiting for device */
+#define FLASH_ERR_DRV_WRONG_PART 0x0d /* Driver does not support device */
+#define FLASH_ERR_LOW_VOLTAGE 0x0e /* Not enough juice to complete job */
char *
bank->driver_priv = info;
info->driverPath=strdup(args[6]);
- // eCos flash sector sizes are not exposed to OpenOCD, use 0x10000 as
- // a way to improve impeadance matach between OpenOCD and eCos flash
- // driver
+ /* eCos flash sector sizes are not exposed to OpenOCD, use 0x10000 as
+ * a way to improve impeadance matach between OpenOCD and eCos flash
+ * driver.
+ */
int i = 0;
u32 offset = 0;
bank->num_sectors=bank->size/sectorSize;
int runCode(ecosflash_flash_bank_t *info,
u32 codeStart, u32 codeStop, u32 r0, u32 r1, u32 r2,
u32 *result,
- // timeout in ms
+ /* timeout in ms */
int timeout)
{
target_t *target=info->target;
if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
return ERROR_FLASH_OPERATION_FAILED;
- //if ((status & ISC_STATUS_INT_ERROR) != STR9XPEC_ISC_INTFAIL)
- // return ERROR_FLASH_OPERATION_FAILED;
+ /* if ((status & ISC_STATUS_INT_ERROR) != STR9XPEC_ISC_INTFAIL)
+ return ERROR_FLASH_OPERATION_FAILED; */
dwords_remaining--;
bytes_written += 8;
if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
return ERROR_FLASH_OPERATION_FAILED;
- //if ((status & ISC_STATUS_INT_ERROR) != STR9XPEC_ISC_INTFAIL)
- // return ERROR_FLASH_OPERATION_FAILED;
+ /* if ((status & ISC_STATUS_INT_ERROR) != STR9XPEC_ISC_INTFAIL)
+ return ERROR_FLASH_OPERATION_FAILED; */
}
free(scanbuf);
* the following macros. Which is the default way.
*/
-//#define malloc(_a) clear_malloc(_a)
-//#define malloc(_a) fill_malloc(_a)
+/* #define malloc(_a) clear_malloc(_a) */
+/* #define malloc(_a) fill_malloc(_a) */
/* GNU extensions to the C library that may be missing on some systems */
#ifndef HAVE_STRNDUP
BUFFER_ADD = TAP_MOVE(cur_state, TAP_SD);
cur_state = TAP_SD;
}
- //DEBUG("added TMS scan (no read)");
+ /* DEBUG("added TMS scan (no read)"); */
}
/* add command for complete bytes */
{
/* Clock Data Bytes In and Out LSB First */
BUFFER_ADD = 0x39;
- //DEBUG("added TDI bytes (io %i)", num_bytes);
+ /* DEBUG("added TDI bytes (io %i)", num_bytes); */
}
else if (type == SCAN_OUT)
{
/* Clock Data Bytes Out on -ve Clock Edge LSB First (no Read) */
BUFFER_ADD = 0x19;
- //DEBUG("added TDI bytes (o)");
+ /* DEBUG("added TDI bytes (o)"); */
}
else if (type == SCAN_IN)
{
/* Clock Data Bytes In on +ve Clock Edge LSB First (no Write) */
BUFFER_ADD = 0x28;
- //DEBUG("added TDI bytes (i %i)", num_bytes);
+ /* DEBUG("added TDI bytes (i %i)", num_bytes); */
}
thisrun_bytes = (num_bytes > 65537) ? 65536 : (num_bytes - 1);
num_bytes -= thisrun_bytes;
{
/* Clock Data Bits In and Out LSB First */
BUFFER_ADD = 0x3b;
- //DEBUG("added TDI bits (io) %i", bits_left - 1);
+ /* DEBUG("added TDI bits (io) %i", bits_left - 1); */
}
else if (type == SCAN_OUT)
{
/* Clock Data Bits Out on -ve Clock Edge LSB First (no Read) */
BUFFER_ADD = 0x1b;
- //DEBUG("added TDI bits (o)");
+ /* DEBUG("added TDI bits (o)"); */
}
else if (type == SCAN_IN)
{
/* Clock Data Bits In on +ve Clock Edge LSB First (no Write) */
BUFFER_ADD = 0x2a;
- //DEBUG("added TDI bits (i %i)", bits_left - 1);
+ /* DEBUG("added TDI bits (i %i)", bits_left - 1); */
}
BUFFER_ADD = bits_left - 2;
if (type != SCAN_IN)
{
/* Clock Data Bits In and Out LSB First */
BUFFER_ADD = 0x3b;
- //DEBUG("added TDI bits (io) %i", bits_left - 1);
+ /* DEBUG("added TDI bits (io) %i", bits_left - 1); */
}
else if (type == SCAN_OUT)
{
/* Clock Data Bits Out on -ve Clock Edge LSB First (no Read) */
BUFFER_ADD = 0x1b;
- //DEBUG("added TDI bits (o)");
+ /* DEBUG("added TDI bits (o)"); */
}
else if (type == SCAN_IN)
{
/* Clock Data Bits In on +ve Clock Edge LSB First (no Write) */
BUFFER_ADD = 0x2a;
- //DEBUG("added TDI bits (i %i)", bits_left - 1);
+ /* DEBUG("added TDI bits (i %i)", bits_left - 1); */
}
BUFFER_ADD = 0x0;
BUFFER_ADD = last_bit;
{
/* Clock Data to TMS/CS Pin with Read */
BUFFER_ADD = 0x6b;
- //DEBUG("added TMS scan (read)");
+ /* DEBUG("added TMS scan (read)"); */
}
else
{
/* Clock Data to TMS/CS Pin (no Read) */
BUFFER_ADD = 0x4b;
- //DEBUG("added TMS scan (no read)");
+ /* DEBUG("added TMS scan (no read)"); */
}
BUFFER_ADD = 0x6;
BUFFER_ADD = TAP_MOVE(cur_state, end_state) | (last_bit << 7);
{
/* Clock Data Bytes In and Out LSB First */
BUFFER_ADD = 0x39;
- //DEBUG("added TDI bytes (io %i)", num_bytes);
+ /* DEBUG("added TDI bytes (io %i)", num_bytes); */
}
else if (type == SCAN_OUT)
{
/* Clock Data Bytes Out on -ve Clock Edge LSB First (no Read) */
BUFFER_ADD = 0x19;
- //DEBUG("added TDI bytes (o)");
+ /* DEBUG("added TDI bytes (o)"); */
}
else if (type == SCAN_IN)
{
/* Clock Data Bytes In on +ve Clock Edge LSB First (no Write) */
BUFFER_ADD = 0x28;
- //DEBUG("added TDI bytes (i %i)", num_bytes);
+ /* DEBUG("added TDI bytes (i %i)", num_bytes); */
}
thisrun_bytes = (num_bytes > 65537) ? 65536 : (num_bytes - 1);
thisrun_read = thisrun_bytes;
{
/* Clock Data Bits In and Out LSB First */
BUFFER_ADD = 0x3b;
- //DEBUG("added TDI bits (io) %i", bits_left - 1);
+ /* DEBUG("added TDI bits (io) %i", bits_left - 1); */
}
else if (type == SCAN_OUT)
{
/* Clock Data Bits Out on -ve Clock Edge LSB First (no Read) */
BUFFER_ADD = 0x1b;
- //DEBUG("added TDI bits (o)");
+ /* DEBUG("added TDI bits (o)"); */
}
else if (type == SCAN_IN)
{
/* Clock Data Bits In on +ve Clock Edge LSB First (no Write) */
BUFFER_ADD = 0x2a;
- //DEBUG("added TDI bits (i %i)", bits_left - 1);
+ /* DEBUG("added TDI bits (i %i)", bits_left - 1); */
}
BUFFER_ADD = bits_left - 2;
if (type != SCAN_IN)
{
/* Clock Data Bits In and Out LSB First */
BUFFER_ADD = 0x3b;
- //DEBUG("added TDI bits (io) %i", bits_left - 1);
+ /* DEBUG("added TDI bits (io) %i", bits_left - 1); */
}
else if (type == SCAN_OUT)
{
/* Clock Data Bits Out on -ve Clock Edge LSB First (no Read) */
BUFFER_ADD = 0x1b;
- //DEBUG("added TDI bits (o)");
+ /* DEBUG("added TDI bits (o)"); */
}
else if (type == SCAN_IN)
{
/* Clock Data Bits In on +ve Clock Edge LSB First (no Write) */
BUFFER_ADD = 0x2a;
- //DEBUG("added TDI bits (i %i)", bits_left - 1);
+ /* DEBUG("added TDI bits (i %i)", bits_left - 1); */
}
BUFFER_ADD = 0x0;
BUFFER_ADD = last_bit;
{
/* Clock Data to TMS/CS Pin with Read */
BUFFER_ADD = 0x6b;
- //DEBUG("added TMS scan (read)");
+ /* DEBUG("added TMS scan (read)"); */
}
else
{
/* Clock Data to TMS/CS Pin (no Read) */
BUFFER_ADD = 0x4b;
- //DEBUG("added TMS scan (no read)");
+ /* DEBUG("added TMS scan (no read)"); */
}
BUFFER_ADD = 0x6;
BUFFER_ADD = TAP_MOVE(cur_state, end_state) | (last_bit << 7);
predicted_size += 1;
}
- //DEBUG("scan_size: %i, predicted_size: %i", scan_size, predicted_size);
+ /* DEBUG("scan_size: %i, predicted_size: %i", scan_size, predicted_size); */
return predicted_size;
}
BUFFER_ADD = 0x0;
cur_state = TAP_RTI;
i -= (i > 7) ? 7 : i;
- //DEBUG("added TMS scan (no read)");
+ /* DEBUG("added TMS scan (no read)"); */
}
if (cmd->cmd.runtest->end_state != -1)
ft2232_end_state(cmd->cmd.runtest->end_state);
/* TMS data bits */
BUFFER_ADD = TAP_MOVE(cur_state, end_state);
cur_state = end_state;
- //DEBUG("added TMS scan (no read)");
+ /* DEBUG("added TMS scan (no read)"); */
}
require_send = 1;
#ifdef _DEBUG_JTAG_IO_
BUFFER_ADD = 0x6;
/* TMS data bits */
BUFFER_ADD = TAP_MOVE(cur_state, end_state);
- //DEBUG("added TMS scan (no read)");
+ /* DEBUG("added TMS scan (no read)"); */
cur_state = end_state;
require_send = 1;
#ifdef _DEBUG_JTAG_IO_
first_unsent = cmd;
}
ft2232_expect_read += ft2232_predict_scan_in(scan_size, type);
- //DEBUG("new read size: %i", ft2232_expect_read);
+ /* DEBUG("new read size: %i", ft2232_expect_read); */
if (cmd->cmd.scan->end_state != -1)
ft2232_end_state(cmd->cmd.scan->end_state);
ft2232_add_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size);
#endif
/* system includes */
-// -ino: 060521-1036
+/* -ino: 060521-1036 */
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
#include <sys/types.h>
#include "bitbang.h"
/* system includes */
-// -ino: 060521-1036
+/* -ino: 060521-1036 */
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
#include <sys/types.h>
return 0;
}
-static inline void parport_write_data(void)
+static __inline__ void parport_write_data(void)
{
u8 output;
output = dataport_value ^ cable->OUTPUT_INVERT;
}
else
{
- *bytes_written = retval;
+ *bytes_written = presto->retval; /* FIXME: Correct? */
return ERROR_OK;
}
#endif
ERROR("ftdi_read_data: %s", ftdi_get_error_string(&presto->ftdic));
return ERROR_JTAG_DEVICE_ERROR;
}
- *bytes_read += retval;
+ *bytes_read += presto->retval; /* FIXME: Correct? */
}
#endif
{
if (tap_transitions[cur_state].low == cmd->path[state_count])
{
- //INFO("1");
+ /* INFO("1"); */
usbprog_write(0, 0, 0);
usbprog_write(1, 0, 0);
}
else if (tap_transitions[cur_state].high == cmd->path[state_count])
{
- //INFO("2");
+ /* INFO("2"); */
usbprog_write(0, 1, 0);
usbprog_write(1, 1, 0);
}
else
{
usbprog_jtag_tms_send(usbprog_jtag_handle);
- //INFO("NUM CYCLES %i",num_cycles);
+ /* INFO("NUM CYCLES %i",num_cycles); */
}
for (i = 0; i < num_cycles; i++)
else
usbprog_end_state(TAP_SD);
- //usbprog_jtag_tms_send(usbprog_jtag_handle);
+ /* usbprog_jtag_tms_send(usbprog_jtag_handle); */
usbprog_state_move();
usbprog_end_state(saved_end_state);
return 1;
if (res == msglen)
{
- //INFO("HALLLLOOO %i",(int)msg[0]);
+ /* INFO("HALLLLOOO %i",(int)msg[0]); */
res = usb_bulk_read(usbprog_jtag->usb_handle, 0x82, msg, 2, 100);
if (res > 0)
return (unsigned char)msg[1];
if (usb_bulk_write(usbprog_jtag->usb_handle, 3, tmp, 64, 1000) == 64)
{
- //INFO("HALLLLOOO2 %i",(int)tmp[0]);
+ /* INFO("HALLLLOOO2 %i",(int)tmp[0]); */
usleep(1);
int timeout = 0;
while (usb_bulk_read(usbprog_jtag->usb_handle, 0x82, tmp, 64, 1000) < 1)
usb_bulk_write(usbprog_jtag->usb_handle, 3, tmp, 3, 1000);
- //INFO("HALLLLOOO3 %i",(int)tmp[0]);
+ /* INFO("HALLLLOOO3 %i",(int)tmp[0]); */
int timeout = 0;
usleep(1);
while (usb_bulk_read(usbprog_jtag->usb_handle, 0x82, tmp, 64, 10) < 1)
{
send_bits = size;
loops = size/8;
- //if(loops==0)
+ /* if(loops==0) */
loops++;
size = 0;
}
void usbprog_jtag_tms_send(struct usbprog_jtag *usbprog_jtag)
{
int i;
- //INFO("TMS SEND");
+ /* INFO("TMS SEND"); */
if (tms_chain_index > 0)
{
char tmp[tms_chain_index + 2];
arm11_write_DSCR(arm11, new_dscr);
-// jtag_execute_queue();
+ /* jtag_execute_queue(); */
+/*
+ DEBUG("SAVE DSCR %08x", R(DSCR));
-// DEBUG("SAVE DSCR %08x", R(DSCR));
-
-// if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
-// DEBUG("SAVE wDTR %08x", R(WDTR));
+ if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
+ DEBUG("SAVE wDTR %08x", R(WDTR));
+*/
/* From the spec:
while (1)
{
/* MRC p14,0,R0,c5,c10,0 */
-// arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
+ /* arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000); */
/* mcr 15, 0, r0, cr7, cr10, {4} */
arm11_run_instr_no_data1(arm11, 0xee070f9a);
arm11->reg_values[ARM11_RC_PC] -= 8;
}
-// DEBUG("SAVE PC %08x", R(PC));
+ /* DEBUG("SAVE PC %08x", R(PC)); */
arm11_run_instr_data_finish(arm11);
/* MRC p14,0,r?,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
-// DEBUG("RESTORE R%d %08x", i, R(RX + i));
+ /* DEBUG("RESTORE R%d %08x", i, R(RX + i)); */
}}
arm11_run_instr_data_finish(arm11);
{
FNC_INFO;
-// DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
-// current, address, handle_breakpoints, debug_execution);
+/*
+ DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
+ current, address, handle_breakpoints, debug_execution);
+*/
arm11_common_t * arm11 = target->arch_info;
arm11_on_enter_debug_state(arm11);
}
-// target->state = TARGET_HALTED;
+ /* target->state = TARGET_HALTED; */
target->debug_reason = DBG_REASON_SINGLESTEP;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
arm11_common_t *arm11 = target->arch_info;
-// const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
+ /* const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index; */
arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
reg->valid = 1;
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
(*cache_p) = cache;
-// armv7m->core_cache = cache;
-// armv7m->process_context = cache;
+ /* armv7m->core_cache = cache; */
+ /* armv7m->process_context = cache; */
size_t i;
return ERROR_TARGET_NOT_HALTED;
}
- //retval = armv4_5->armv4_5_common->full_context(target);
+ /* retval = armv4_5->armv4_5_common->full_context(target); */
retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode);
return retval;
"sp", "lr", "pc",
"xPSR", "msp", "psp",
/* Registers accessed through MSR instructions */
-// "apsr", "iapsr", "ipsr", "epsr",
+ /* "apsr", "iapsr", "ipsr", "epsr", */
"primask", "basepri", "faultmask", "control"
};
"sp", "lr", "pc",
"xPSR", "msp", "psp",
/* Registers accessed through MSR instructions */
-// "dbg_apsr", "iapsr", "ipsr", "epsr",
+ /* "dbg_apsr", "iapsr", "ipsr", "epsr", */
"primask", "basepri", "faultmask", "dbg_control"
};
{18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
/* CORE_SP are accesible using MSR and MRS instructions */
+#if 0
// {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
// {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
// {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
// {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
+#endif
{0x10, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
{0x11, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
{
if (i < ARMV7NUMCOREREGS)
(*reg_list)[i] = &armv7m->process_context->reg_list[i];
- //(*reg_list)[i] = &armv7m->core_cache->reg_list[i];
+ /* (*reg_list)[i] = &armv7m->core_cache->reg_list[i]; */
else
(*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
}
int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
{
- // get pointers to arch-specific information
+ /* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
enum armv7m_state core_state = armv7m->core_state;
void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc);
-// void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
-// void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
-// void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
+/*
+ void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
+ void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
+ void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
+*/
/*
void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
return ERROR_OK;
}
-//int irqstepcount=0;
+/* int irqstepcount=0; */
int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
{
/* get pointers to arch-specific information */
ERROR("JTAG failure %i",retval);
return ERROR_JTAG_DEVICE_ERROR;
}
- //DEBUG("load from core reg %i value 0x%x",num,*value);
+ /* DEBUG("load from core reg %i value 0x%x",num,*value); */
}
else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
{
armv7m->arch_info = cortex_m3;
armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
-// armv7m->full_context = cortex_m3_full_context;
+ /* armv7m->full_context = cortex_m3_full_context; */
target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
typedef struct cortex_m3_common_s
{
int common_magic;
-// int (*full_context)(struct target_s *target);
+ /* int (*full_context)(struct target_s *target); */
arm_jtag_t jtag_info;
csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
if (csw != swjdp->ap_csw_value)
{
- //DEBUG("swjdp : Set CSW %x",csw);
+ /* DEBUG("swjdp : Set CSW %x",csw); */
ahbap_write_reg_u32(swjdp, AHBAP_CSW, csw );
swjdp->ap_csw_value = csw;
}
if (tar != swjdp->ap_tar_value)
{
- //DEBUG("swjdp : Set TAR %x",tar);
+ /* DEBUG("swjdp : Set TAR %x",tar); */
ahbap_write_reg_u32(swjdp, AHBAP_TAR, tar );
swjdp->ap_tar_value = tar;
}
/* Internal functions used in the module, partial transactions, use with caution */
extern int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
-//extern int swjdp_write_apacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
+/* extern int swjdp_write_apacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr); */
extern int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr);
-//extern int swjdp_read_apacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr);
+/* extern int swjdp_read_apacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr); */
extern int ahbap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf);
extern int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf);