cfg: update for target's that support cortex_m AIRCR SYSRESETREQ

If the target supports SYSRESETREQ make sure we use that as the default
if srst is not fitted/configured.

Change-Id: I24c907493134506320e69c1218702930629c1cdc
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/792
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>

diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg
index 63759e3f5a67d90888c2ea99ef215468801c775f..b90e3f0157c93fcbeb1d9b9e78452f7eba9e907d 100644 (file)
--- a/tcl/target/at91sam3XXX.cfg
+++ b/tcl/target/at91sam3XXX.cfg
@@ -66,3 +66,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-ar
 $_TARGETNAME configure -event gdb-flash-erase-start {
     halt
 }
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq

diff --git a/tcl/target/at91sam3nXX.cfg b/tcl/target/at91sam3nXX.cfg
index 9e362b26698abcfeb6de47d03589cd0d6c9a725b..b628103ced608c29bec1d5a6ae2fe06f87ed5793 100644 (file)
--- a/tcl/target/at91sam3nXX.cfg
+++ b/tcl/target/at91sam3nXX.cfg
@@ -22,3 +22,8 @@ target create $_TARGETNAME cortex_m3 -endian little -chain-position $_TARGETNAME
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq
+

diff --git a/tcl/target/at91sam4XXX.cfg b/tcl/target/at91sam4XXX.cfg
index d9f57461dae5523a157bfef1fc6c7ef68e40c235..c34121847798cee495d481f3ea7a33ab11821eb0 100644 (file)
--- a/tcl/target/at91sam4XXX.cfg
+++ b/tcl/target/at91sam4XXX.cfg
@@ -43,3 +43,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-ar
 $_TARGETNAME configure -event gdb-flash-erase-start {
     halt
 }
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq

diff --git a/tcl/target/k40.cfg b/tcl/target/k40.cfg
index 26b952b9952a3aa3c49e7680c3918dd96cca2a95..57aa849201dc5d0c236f9ed703e4079312fe1552 100644 (file)
--- a/tcl/target/k40.cfg
+++ b/tcl/target/k40.cfg
@@ -33,3 +33,7 @@ target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
 
 $_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
 $_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq

diff --git a/tcl/target/k60.cfg b/tcl/target/k60.cfg
index d1247f31d4dae509fd67758df894ed1cfc7b0fda..a85fa909bf1240167e2d2756619e8ce3ecbb81d6 100644 (file)
--- a/tcl/target/k60.cfg
+++ b/tcl/target/k60.cfg
@@ -33,3 +33,7 @@ target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
 
 $_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
 $_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq

diff --git a/tcl/target/lpc17xx.cfg b/tcl/target/lpc17xx.cfg
index 379bcfb93e31846ead8feea14ec09e312a9b577d..a64783dab2e75edb6119b5552eb7a8dc5785be71 100644 (file)
--- a/tcl/target/lpc17xx.cfg
+++ b/tcl/target/lpc17xx.cfg
@@ -91,3 +91,7 @@ $_TARGETNAME configure -event reset-init {
 
        mww 0x400FC040 0x01
 }
+
+# if srst is not fitted use VECTRESET to
+# perform a soft reset - SYSRESETREQ is not supported
+cortex_m3 reset_config vectreset

diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg
index 63d130796a773d792f4c9cfdbb68dccc735e5788..6614383b89dff72a0e71f3f1ee2e1d9c9f075dcb 100644 (file)
--- a/tcl/target/lpc4350.cfg
+++ b/tcl/target/lpc4350.cfg
@@ -42,3 +42,7 @@ jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
 
 target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4
 target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq