- grub-efi-ia32-bin
- rpm2cpio
- wget
- - device-tree-compiler
install:
# install latest device tree compiler
- #- git clone --depth=1 git://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
- #- make -j4 -C /tmp/dtc
+ - git clone --depth=1 git://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
+ - make -j4 -C /tmp/dtc
# Clone uboot-test-hooks
- git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
- ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
env:
global:
- - PATH=/tmp/dtc:/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:$PATH
+ - PATH=/tmp/dtc:/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:/usr/bin:/bin
- PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
- BUILD_DIR=build
- HOSTCC="cc"
KBUILD_CFLAGS := -Wall -Wstrict-prototypes \
-Wno-format-security \
-fno-builtin -ffreestanding
+KBUILD_CFLAGS += -fshort-wchar
KBUILD_AFLAGS := -D__ASSEMBLY__
# Read UBOOTRELEASE from include/config/uboot.release (if it exists)
kernel configuration options. The intention is to make it easier to
build a config tool - later.
+- ARM Platform Bus Type(CCI):
+ CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
+ provides full cache coherency between two clusters of multi-core
+ CPUs and I/O coherency for devices and I/O masters
+
+ CONFIG_SYS_FSL_HAS_CCI400
+
+ Defined For SoC that has cache coherent interconnect
+ CCN-400
+
+ CONFIG_SYS_FSL_HAS_CCN504
+
+ Defined for SoC that has cache coherent interconnect CCN-504
The following options need to be configured:
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
+config TARGET_LS1088AQDS
+ bool "Support ls1088aqds"
+ select ARCH_LS1088A
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select ARCH_MISC_INIT
+ select BOARD_LATE_INIT
+ help
+ Support for NXP LS1088AQDS platform
+ The LS1088A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS1088A
+ Layerscape Architecture processor.
+
config TARGET_LS2080AQDS
bool "Support ls2080aqds"
select ARCH_LS2080A
development platform that supports the QorIQ LS1012A
Layerscape Architecture processor.
+config TARGET_LS1088ARDB
+ bool "Support ls1088ardb"
+ select ARCH_LS1088A
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select ARCH_MISC_INIT
+ select BOARD_LATE_INIT
+ help
+ Support for NXP LS1088ARDB platform.
+ The LS1088A Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1088A
+ Layerscape Architecture processor.
+
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select BOARD_LATE_INIT
source "board/freescale/ls2080a/Kconfig"
source "board/freescale/ls2080aqds/Kconfig"
source "board/freescale/ls2080ardb/Kconfig"
+source "board/freescale/ls1088a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
bool
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008407
+ select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
+ select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_HAS_CCI400
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
Enable Freescale Secure Boot feature. Normally selected
by defconfig. If unsure, do not change.
+config SYS_CCI400_OFFSET
+ hex "Offset for CCI400 base"
+ depends on SYS_FSL_HAS_CCI400
+ default 0x180000
+ help
+ Offset for CCI400 base.
+ CCI400 base addr = CCSRBAR + CCI400_OFFSET
+
+config SYS_FSL_ERRATUM_A008997
+ bool
+ help
+ Workaround for USB PHY erratum A008997
+
+config SYS_FSL_ERRATUM_A009007
+ bool
+ help
+ Workaround for USB PHY erratum A009007
+
+config SYS_FSL_ERRATUM_A009008
+ bool
+ help
+ Workaround for USB PHY erratum A009008
+
+config SYS_FSL_ERRATUM_A009798
+ bool
+ help
+ Workaround for USB PHY erratum A009798
+
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
+config SYS_FSL_HAS_CCI400
+ bool
+
config SYS_FSL_SRDS_1
bool
return major;
}
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+ clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4,
+ 0xF << 6,
+ SCFG_USB_TXVREFTUNE << 6);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+ clrbits_be32(scfg + SCFG_USB3PRM1CR / 4,
+ SCFG_USB_SQRXTUNE_MASK << 23);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+ clrsetbits_be32(scfg + SCFG_USB3PRM2CR / 4,
+ SCFG_USB_PCSTXSWINGFULL_MASK,
+ SCFG_USB_PCSTXSWINGFULL_VAL);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+ void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+
+ out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);
+ out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);
+ out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);
+ out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
void s_init(void)
{
}
int arch_soc_init(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
*/
out_be32(&scfg->eddrtqcfg, 0x63b20042);
+ /* Erratum */
+ erratum_a009008();
+ erratum_a009798();
+ erratum_a008997();
+ erratum_a009007();
+
return 0;
}
depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
!TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
!TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
+ !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008850
+ select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
+ select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009660
select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009929
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A008336
select SYS_FSL_ERRATUM_A008511
select SYS_FSL_ERRATUM_A008850
+ select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
+ select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009801
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
select BOARD_EARLY_INIT_F
imply SCSI
+config ARCH_LS1088A
+ bool
+ select ARMV8_SET_SMPEN
+ select FSL_LSCH3
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_LE
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_EC1
+ select SYS_FSL_EC2
+ select SYS_FSL_ERRATUM_A009803
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_A010165
+ select SYS_FSL_ERRATUM_A008511
+ select SYS_FSL_ERRATUM_A008850
+ select SYS_FSL_HAS_CCI400
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_RGMII
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_LE
+ select SYS_FSL_SRDS_1
+ select SYS_FSL_SRDS_2
+ select FSL_TZASC_1
+ select ARCH_EARLY_INIT_R
+ select BOARD_EARLY_INIT_F
+
config ARCH_LS2080A
bool
select ARMV8_SET_SMPEN
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
+ select SYS_FSL_HAS_CCN504
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_HAS_SEC
select SYS_FSL_HAS_DDR4
select SYS_FSL_ERRATUM_A008511
select SYS_FSL_ERRATUM_A008514
select SYS_FSL_ERRATUM_A008585
+ select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
+ select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009635
select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009801
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
config FSL_LSCH2
bool
+ select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_BE
config FSL_MC_ENET
bool "Management Complex network"
- depends on ARCH_LS2080A
+ depends on ARCH_LS2080A || ARCH_LS1088A
default y
select RESV_RAM
help
default "fsl,ls1043a-pcie" if ARCH_LS1043A
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
+ default "fsl,ls1088a-pcie" if ARCH_LS1088A
help
This compatible is used to find pci controller node in Kernel DT
to complete fixup.
default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
+ default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
default 0x400000 if SYS_LS_PPA_FW_IN_MMC
default 0x400000 if SYS_LS_PPA_FW_IN_NAND
config SYS_LS_PPA_ESBC_ADDR
hex "hdr address of PPA firmware loading from"
depends on FSL_LS_PPA && CHAIN_OF_TRUST
- default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
- default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
- default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
- default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
- default 0x700000 if SYS_LS_PPA_FW_IN_MMC
- default 0x700000 if SYS_LS_PPA_FW_IN_NAND
+ default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
+ default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
+ default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
+ default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
+ default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
+ default 0x680000 if SYS_LS_PPA_FW_IN_MMC
+ default 0x680000 if SYS_LS_PPA_FW_IN_NAND
help
If the PPA header firmware locate at XIP flash, such as NOR or
QSPI flash, this address is a directly memory-mapped.
endmenu
+config SYS_FSL_ERRATUM_A008997
+ bool "Workaround for USB PHY erratum A008997"
+
+config SYS_FSL_ERRATUM_A009007
+ bool
+ help
+ Workaround for USB PHY erratum A009007
+
+config SYS_FSL_ERRATUM_A009008
+ bool "Workaround for USB PHY erratum A009008"
+
+config SYS_FSL_ERRATUM_A009798
+ bool "Workaround for USB PHY erratum A009798"
+
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 16 if ARCH_LS2080A
+ default 8 if ARCH_LS1088A
default 1
help
Set this number to the maximum number of possible CPUs in the SoC.
But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
bus for those flashes to support the full QSPI flash size.
+config SYS_CCI400_OFFSET
+ hex "Offset for CCI400 base"
+ depends on SYS_FSL_HAS_CCI400
+ default 0x3090000 if ARCH_LS1088A
+ default 0x180000 if FSL_LSCH2
+ help
+ Offset for CCI400 base
+ CCI400 base addr = CCSRBAR + CCI400_OFFSET
+
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
- depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+ depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
- default 8 if ARCH_LS2080A
+ default 8 if ARCH_LS2080A || ARCH_LS1088A
+
+config SYS_FSL_HAS_CCI400
+ bool
+
+config SYS_FSL_HAS_CCN504
+ bool
config SYS_FSL_HAS_DP_DDR
bool
int "Platform clock divider"
default 1 if ARCH_LS1043A
default 1 if ARCH_LS1046A
+ default 1 if ARCH_LS1088A
default 2
help
This is the divider that is used to derive Platform clock from
be at the high end of physical memory. The reserve RAM may be
excluded from memory bank(s) passed to OS, or marked as reserved.
+config SYS_FSL_EC1
+ bool
+ help
+ Ethernet controller 1, this is connected to MAC3.
+ Provides DPAA2 capabilities
+
+config SYS_FSL_EC2
+ bool
+ help
+ Ethernet controller 2, this is connected to MAC4.
+ Provides DPAA2 capabilities
+
config SYS_FSL_ERRATUM_A008336
bool
config SYS_FSL_ERRATUM_A009929
bool
+
+config SYS_FSL_HAS_RGMII
+ bool
+ depends on SYS_FSL_EC1 || SYS_FSL_EC2
+
+
config SYS_MC_RSV_MEM_ALIGN
hex "Management Complex reserved memory alignment"
depends on RESV_RAM
- default 0x20000000
+ default 0x20000000 if ARCH_LS2080A
+ default 0x70000000 if ARCH_LS1088A
help
Reserved memory needs to be aligned for MC to use. Default value
is 512MB.
ifneq ($(CONFIG_ARCH_LS1046A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
endif
+
+ifneq ($(CONFIG_ARCH_LS1088A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
+endif
#include <asm/arch/soc.h>
#include <asm/arch/cpu.h>
#include <asm/arch/speed.h>
+#include <fsl_immap.h>
#include <asm/arch/mp.h>
#include <efi_loader.h>
#include <fm_eth.h>
printf("Did not wake secondary cores\n");
}
+#ifdef CONFIG_SYS_FSL_HAS_RGMII
+ fsl_rgmii_init();
+#endif
+
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#endif
#endif
+/*
+ * Calculate reserved memory with given memory bank
+ * Return aligned memory size on success
+ * Return (ram_size + needed size) for failure
+ */
phys_size_t board_reserve_ram_top(phys_size_t ram_size)
{
phys_size_t ram_top = ram_size;
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+ ram_top = mc_get_dram_block_size();
+ if (ram_top > ram_size)
+ return ram_size + ram_top;
+
+ ram_top = ram_size - ram_top;
/* The start address of MC reserved memory needs to be aligned. */
- ram_top -= mc_get_dram_block_size();
ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
#endif
/* Check if we have enough memory for MC */
if (rem < board_reserve_ram_top(rem)) {
/* Not enough memory in high region to reserve */
- if (ea_size > board_reserve_ram_top(rem))
- ea_size -= board_reserve_ram_top(rem);
+ if (ea_size > board_reserve_ram_top(ea_size))
+ ea_size -= board_reserve_ram_top(ea_size);
else
printf("Error: No enough space for reserved memory.\n");
}
SoC overview
1. LS1043A
- 2. LS2080A
- 3. LS1012A
- 4. LS1046A
- 5. LS2088A
- 6. LS2081A
+ 2. LS1088A
+ 3. LS2080A
+ 4. LS1012A
+ 5. LS1046A
+ 6. LS2088A
+ 7. LS2081A
LS1043A
---------
- Integrated flash controller supporting NAND and NOR flash
- QorIQ platform's trust architecture 2.1
+LS1088A
+--------
+The QorIQ LS1088A processor is built on the Layerscape
+architecture combining eight ARM A53 processor cores
+with advanced, high-performance datapath acceleration
+and networks, peripheral interfaces required for
+networking, wireless infrastructure, and general-purpose
+embedded applications.
+
+LS1088A is compliant with the Layerscape Chassis Generation 3.
+
+Features summary:
+ - 8 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
+ - Cores are in 2 cluster of 4-cores each
+ - 1MB L2 - Cache per cluster
+ - Cache coherent interconnect (CCI-400)
+ - 1 64-bit DDR4 SDRAM memory controller with ECC
+ - Data path acceleration architecture 2.0 (DPAA2)
+ - 4-Lane 10GHz SerDes comprising of WRIOP
+ - 4-Lane 10GHz SerDes comprising of PCI, SATA, uQE(TDM/HLDC/UART)
+ - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
+ - QSPI, SPI, IFC2.0 supporting NAND, NOR flash
+ - 3 PCIe3.0 , 1 SATA3.0, 2 USB3.0, 1 SDXC, 2 DUARTs etc
+ - 2 DUARTs
+ - 4 I2C, GPIO
+ - Thermal monitor unit(TMU)
+ - 4 Flextimers and 1 generic timer
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ platform's trust architecture 3.0
+ - Service processor (SP) provides pre-boot initialization and secure-boot
+ capabilities
+
LS2080A
--------
The LS2080A integrated multicore processor combines eight ARM Cortex-A57
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob);
#endif
-#ifndef CONFIG_LS1012A
+#ifndef CONFIG_ARCH_LS1012A
fsl_fdt_disable_usb(blob);
#endif
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
return;
}
+/*
+ *The return value of this func is the serdes protocol used.
+ *Typically this function is called number of times depending
+ *upon the number of serdes blocks in the Silicon.
+ *Zero is used to denote that no serdes was enabled,
+ *this is the case when golden RCW was used where DPAA2 bring was
+ *intentionally removed to achieve boot to prompt
+*/
+
+__weak int serdes_get_number(int serdes, int cfg)
+{
+ return cfg;
+}
+
int is_serdes_configured(enum srds_prtcl device)
{
int ret = 0;
printf("invalid SerDes%d\n", sd);
break;
}
+
+ cfg = serdes_get_number(sd, cfg);
+
/* Is serdes enabled at all? */
if (cfg == 0)
return -ENODEV;
cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
cfg >>= sd_prctl_shift;
+
+ cfg = serdes_get_number(sd, cfg);
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
if (!is_serdes_prtcl_valid(sd, cfg))
switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
1:
-#ifdef CONFIG_FSL_LSCH3
+#if defined (CONFIG_SYS_FSL_HAS_CCN504)
/* Set Wuo bit for RN-I 20 */
#ifdef CONFIG_ARCH_LS2080A
ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
ldr x1, =0x00FF000C
bl ccn504_set_qos
-#endif
+#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef SMMU_BASE
/* Set the SMMU page size in the sACR register */
ldr x1, =FSL_LSCH3_SVR
ldr w0, [x1]
ret
+#endif
+#ifdef CONFIG_SYS_FSL_HAS_CCN504
hnf_pstate_poll:
/* x0 has the desired status, return 0 for success, 1 for timeout
* clobber x1, x2, x3, x4, x6, x7
mov x29, lr
mov x8, #0
- switch_el x0, 1f, 100f, 100f /* skip if not in EL3 */
-
-1:
dsb sy
mov x0, #0x1 /* HNFPSTAT_SFONLY */
bl hnf_set_pstate
bl hnf_pstate_poll
cbz x0, 1f
add x8, x8, #0x2
-100:
1:
mov x0, x8
mov lr, x29
ret
ENDPROC(__asm_flush_l3_dcache)
-#endif
+#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef CONFIG_MP
/* Keep literals not used by the secondary boot code outside it */
--- /dev/null
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+
+struct serdes_config {
+ u8 ip_protocol;
+ u8 lanes[SRDS_MAX_LANES];
+ u8 rcw_lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {0x12, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 3 } },
+ {0x15, {SGMII3, SGMII7, XFI1, XFI2 }, {3, 3, 1, 1 } },
+ {0x16, {SGMII3, SGMII7, SGMII1, XFI2 }, {3, 3, 3, 1 } },
+ {0x17, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 2 } },
+ {0x18, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 2, 2 } },
+ {0x19, {SGMII3, QSGMII_B, XFI1, XFI2}, {3, 4, 1, 1 } },
+ {0x1A, {SGMII3, QSGMII_B, SGMII1, XFI2 }, {3, 4, 3, 1 } },
+ {0x1B, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 2 } },
+ {0x1C, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 2, 2 } },
+ {0x1D, {QSGMII_A, QSGMII_B, XFI1, XFI2 }, {4, 4, 1, 1 } },
+ {0x1E, {QSGMII_A, QSGMII_B, SGMII1, XFI2 }, {4, 4, 3, 1 } },
+ {0x1F, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 2 } },
+ {0x20, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 2, 2 } },
+ {0x35, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 3 } },
+ {0x36, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 3 } },
+ {0x3A, {SGMII3, PCIE1, SGMII1, SGMII2 }, {3, 5, 3, 3 } },
+ {}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+ /* SerDes 2 */
+ {0x0C, {PCIE1, PCIE1, PCIE1, PCIE1 }, {8, 8, 8, 8 } },
+ {0x0D, {PCIE1, PCIE2, PCIE3, SATA1 }, {5, 5, 5, 9 } },
+ {0x0E, {PCIE1, PCIE1, PCIE2, SATA1 }, {7, 7, 6, 9 } },
+ {0x13, {PCIE1, PCIE1, PCIE3, PCIE3 }, {7, 7, 7, 7 } },
+ {0x14, {PCIE1, PCIE2, PCIE3, PCIE3 }, {5, 5, 7, 7 } },
+ {0x3C, {NONE, PCIE2, NONE, PCIE3 }, {0, 5, 0, 6 } },
+ {}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+ serdes1_cfg_tbl,
+ serdes2_cfg_tbl,
+};
+
+int serdes_get_number(int serdes, int cfg)
+{
+ struct serdes_config *ptr;
+ int i, j, index, lnk;
+ int is_found, max_lane = SRDS_MAX_LANES;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+
+ while (ptr->ip_protocol) {
+ is_found = 1;
+ for (i = 0, j = max_lane - 1; i < max_lane; i++, j--) {
+ lnk = cfg & (0xf << 4 * i);
+ lnk = lnk >> (4 * i);
+
+ index = (serdes == FSL_SRDS_1) ? j : i;
+
+ if (ptr->rcw_lanes[index] == lnk && is_found)
+ is_found = 1;
+ else
+ is_found = 0;
+ }
+
+ if (is_found)
+ return ptr->ip_protocol;
+ ptr++;
+ }
+
+ return 0;
+}
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->ip_protocol) {
+ if (ptr->ip_protocol == cfg)
+ return ptr->lanes[lane];
+ ptr++;
+ }
+
+ return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->ip_protocol) {
+ if (ptr->ip_protocol == prtcl)
+ break;
+ ptr++;
+ }
+
+ if (!ptr->ip_protocol)
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (ptr->lanes[i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
return -EIO;
}
- /* flush cache after read */
- flush_cache((ulong)fitp, cnt * 512);
-
ret = fdt_check_header(fitp);
if (ret) {
free(fitp);
}
debug("Read PPA header to 0x%p\n", ppa_hdr_ddr);
- /* flush cache after read */
- flush_cache((ulong)ppa_hdr_ddr, cnt * 512);
-
ppa_esbc_hdr = (uintptr_t)ppa_hdr_ddr;
#endif
return -EIO;
}
- /* flush cache after read */
- flush_cache((ulong)ppa_fit_addr, cnt * 512);
-
#elif defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
struct fdt_header fit;
}
debug("Read PPA header to 0x%p\n", ppa_hdr_ddr);
- /* flush cache after read */
- flush_cache((ulong)ppa_hdr_ddr, fw_length);
-
ppa_esbc_hdr = (uintptr_t)ppa_hdr_ddr;
#endif
CONFIG_SYS_LS_PPA_FW_ADDR);
return -EIO;
}
-
- /* flush cache after read */
- flush_cache((ulong)ppa_fit_addr, fw_length);
#else
#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
#endif
*/
#include <common.h>
+#include <fsl_immap.h>
#include <fsl_ifc.h>
#include <ahci.h>
#include <scsi.h>
#ifdef CONFIG_CHAIN_OF_TRUST
#include <fsl_validate.h>
#endif
+#include <fsl_immap.h>
DECLARE_GLOBAL_DATA_PTR;
return false;
}
+static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
+{
+ scfg_clrsetbits32(scfg + offset / 4,
+ 0xF << 6,
+ SCFG_USB_TXVREFTUNE << 6);
+}
+
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
+ set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
+ set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
+#elif defined(CONFIG_ARCH_LS2080A)
+ set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
+static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
+{
+ scfg_clrbits32(scfg + offset / 4,
+ SCFG_USB_SQRXTUNE_MASK << 23);
+}
+
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
+ set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
+ set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
+#elif defined(CONFIG_ARCH_LS2080A)
+ set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
+{
+ scfg_clrsetbits32(scfg + offset / 4,
+ 0x7F << 9,
+ SCFG_USB_PCSTXSWINGFULL << 9);
+}
+#endif
+
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+ set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
+ set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
+ set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+
+#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
+ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
+ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
+ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
+ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
+
+#elif defined(CONFIG_ARCH_LS2080A)
+
+#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
+ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
+ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
+ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
+ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
+
+#endif
+
+static void erratum_a009007(void)
+{
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
+
+ PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+
+ usb_phy = (void __iomem *)SCFG_USB_PHY2;
+ PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+
+ usb_phy = (void __iomem *)SCFG_USB_PHY3;
+ PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+#elif defined(CONFIG_ARCH_LS2080A)
+ void __iomem *dcsr = (void __iomem *)DCSR_BASE;
+
+ PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
+ PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
#endif
erratum_a008514();
erratum_a008336();
+ erratum_a009008();
+ erratum_a009798();
+ erratum_a008997();
+ erratum_a009007();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
/* part 1 of 2 */
- struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
/* Skip if running at lower exception level */
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
/* part 2 of 2 */
- struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
u32 tmp;
void fsl_lsch2_early_init_f(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
erratum_a009929();
erratum_a009660();
erratum_a010539();
+ erratum_a009008();
+ erratum_a009798();
+ erratum_a008997();
+ erratum_a009007();
}
#endif
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
+ rk3288-vyasa.dtb \
rk3328-evb.dtb \
rk3368-lion.dtb \
rk3368-sheep.dtb \
socfpga_cyclone5_vining_fpga.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
- dra72-evm-revc.dtb dra71-evm.dtb
+ dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
am57xx-beagle-x15-revb1.dtb \
+ am57xx-beagle-x15-revc.dtb \
am572x-idk.dtb \
am571x-idk.dtb
dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb \
fsl-ls2081a-rdb.dtb \
- fsl-ls2088a-rdb-qspi.dtb
+ fsl-ls2088a-rdb-qspi.dtb \
+ fsl-ls1088a-rdb.dtb \
+ fsl-ls1088a-qds.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
+dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \
+ at91-sama5d27_som1_ek.dtb
+
dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
sama5d31ek.dtb \
sama5d33ek.dtb \
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"
+#include "dra72x-mmc-iodelay.dtsi"
/ {
model = "TI AM5718 IDK";
linux,default-trigger = "mmc0";
};
};
+};
+
+&omap_dwc3_2 {
+ extcon = <&extcon_usb2>;
+};
- extcon_usb2: extcon_usb2 {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
+&extcon_usb2 {
+ id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
+ vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>;
+};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
};
};
-&mmc1 {
+&mailbox6 {
status = "okay";
- vmmc-supply = <&ldo1_reg>;
- bus-width = <4>;
- cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
};
-&omap_dwc3_2 {
- extcon = <&extcon_usb2>;
+&pcie1_rc {
+ status = "okay";
+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie1_ep {
+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&mmc1 {
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
};
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"
+#include "dra74x-mmc-iodelay.dtsi"
/ {
model = "TI AM5728 IDK";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
- extcon_usb2: extcon_usb2 {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
- };
-
status-leds {
compatible = "gpio-leds";
cpu0-led {
};
};
+&mmc1 {
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_rev20>;
+};
+
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
-&mmc1 {
+&extcon_usb2 {
+ id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
+};
+
+&sn65hvs882 {
+ load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+};
+
+&pcie1_rc {
status = "okay";
- vmmc-supply = <&v3_3d>;
- vmmc_aux-supply = <&ldo1_reg>;
- bus-width = <4>;
- cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie1_ep {
+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ status = "okay";
+ };
};
#include "dra74x.dtsi"
#include "am57xx-commercial-grade.dtsi"
+#include "dra74x-mmc-iodelay.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
- chosen {
- stdout-path = &uart3;
- };
-
aliases {
rtc0 = &mcp_rtc;
rtc1 = &tps659038_rtc;
display0 = &hdmi0;
};
+ chosen {
+ stdout-path = &uart3;
+ };
+
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
};
-&dra7_pmx_core {
- mmc1_pins_default: mmc1_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
- >;
- };
-
- mmc2_pins_default: mmc2_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
- >;
- };
-};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
interrupt-controller;
ti,system-power-controller;
+ ti,palmas-override-powerhold;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
};
eeprom: eeprom@50 {
- compatible = "at,24c32";
+ compatible = "atmel,24c32";
reg = <0x50>;
};
};
<&dra7_pmx_core 0x3f8>;
};
+&davinci_mdio {
+ phy0: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy1: ethernet-phy@2 {
+ reg = <2>;
+ };
+};
+
&mac {
status = "okay";
dual_emac;
};
&cpsw_emac0 {
- phy_id = <&davinci_mdio>, <1>;
+ phy-handle = <&phy0>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <2>;
+ phy-handle = <&phy1>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
};
};
};
-&pcie1 {
+&pcie1_rc {
+ status = "ok";
+ gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+};
+
+&pcie1_ep {
gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
};
};
&mmc1 {
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
vmmc-supply = <&vdd_3v3>;
- vmmc-aux-supply = <&ldo1_reg>;
+ vqmmc-supply = <&ldo1_reg>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;
+};
+
+/* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
+&phy1 {
+ max-speed = <100>;
};
--- /dev/null
+/*
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "am57xx-beagle-x15-common.dtsi"
+
+/ {
+ model = "TI AM5728 BeagleBoard-X15 rev C";
+};
+
+&tpd12s015 {
+ gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
+ <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */
+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
+};
+
+&mmc1 {
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
+ vmmc-supply = <&vdd_3v3>;
+ vqmmc-supply = <&ldo1_reg>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_rev20>;
+};
};
&mmc1 {
+ pinctrl-names = "default", "hs";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+
vmmc-supply = <&ldo1_reg>;
};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;
+};
+
+/* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
+&phy1 {
+ max-speed = <100>;
+};
--- /dev/null
+/*
+ * Support for CompuLab CL-SOM-AM57x System-on-Module
+ *
+ * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
+ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "dra74x.dtsi"
+
+/ {
+ model = "CompuLab CL-SOM-AM57x";
+ compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_pins_default>;
+
+ led0 {
+ label = "cl-som-am57x:green";
+ gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+
+ vdd_3v3: fixedregulator-vdd_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ads7846reg: fixedregulator-ads7846-reg {
+ compatible = "regulator-fixed";
+ regulator-name = "ads7846-reg";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ sound0: sound0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "CL-SOM-AM57x-Sound-Card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink0_master>;
+ simple-audio-card,frame-master = <&dailink0_master>;
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Microphone", "Microphone Jack",
+ "Line", "Line Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "RHPOUT",
+ "Headphone Jack", "LHPOUT",
+ "LLINEIN", "Line Jack",
+ "MICIN", "Mic Bias",
+ "Mic Bias", "Microphone Jack";
+
+ dailink0_master: simple-audio-card,cpu {
+ sound-dai = <&mcasp3>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&wm8731>;
+ system-clock-frequency = <12000000>;
+ };
+ };
+};
+
+&dra7_pmx_core {
+ leds_pins_default: leds_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14) /* gpmc_a15.gpio2_5 */
+ >;
+ };
+
+ i2c1_pins_default: i2c1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
+ DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
+ >;
+ };
+
+ i2c3_pins_default: i2c3_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
+ DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
+ >;
+ };
+
+ i2c4_pins_default: i2c4_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10) /* mcasp1_acl.i2c4_sda */
+ DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10) /* mcasp1_fsr.i2c4_scl */
+ >;
+ };
+
+ tps659038_pins_default: tps659038_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ qspi1_pins: pinmux_qspi1_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
+ DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d0 */
+ DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d1 */
+ DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
+ DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
+ DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
+ >;
+ };
+
+ cpsw_pins_default: cpsw_pins_default {
+ pinctrl-single,pins = <
+ /* Slave at addr 0x0 */
+ DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tclk */
+ DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tctl */
+ DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3 */
+ DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td2 */
+ DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td1 */
+ DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td0 */
+ DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rclk */
+ DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rctl */
+ DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd3 */
+ DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd2 */
+ DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd1 */
+ DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd0 */
+
+ /* Slave at addr 0x1 */
+ DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_tclk */
+ DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
+ DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
+ DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
+ DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
+ DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
+ DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
+ DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
+ DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
+ DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
+ DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
+ DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
+ >;
+ };
+
+ cpsw_pins_sleep: cpsw_pins_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15)
+
+ /* Slave 2 */
+ DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15)
+ >;
+ };
+
+ davinci_mdio_pins_default: davinci_mdio_pins_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | MUX_MODE3)/* vin2a_d10.mdio_mclk */
+ DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT_PULLUP | MUX_MODE3) /* vin2a_d11.mdio_d */
+ >;
+ };
+
+ davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT | MUX_MODE15)
+ >;
+ };
+
+ ads7846_pins: pinmux_ads7846_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpmc_a9.gpio1_31 */
+ >;
+ };
+
+ mcasp3_pins_default: mcasp3_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */
+ DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
+ DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
+ DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
+ >;
+ };
+
+ mcasp3_pins_sleep: mcasp3_pins_sleep {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15)
+ >;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&i2c3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&i2c4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins_default>;
+ clock-frequency = <400000>;
+
+ tps659038: tps659038@58 {
+ compatible = "ti,tps659038";
+ reg = <0x58>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tps659038_pins_default>;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ tps659038_pmic {
+ compatible = "ti,tps659038-pmic";
+
+ regulators {
+ smps12_reg: smps12 {
+ /* VDD_MPU */
+ regulator-name = "smps12";
+ regulator-min-microvolt = < 850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps3_reg: smps3 {
+ /* VDD_DDR */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps45_reg: smps45 {
+ /* VDD_DSPEVE */
+ regulator-name = "smps45";
+ regulator-min-microvolt = < 850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps6_reg: smps6 {
+ /* VDD_GPU */
+ regulator-name = "smps6";
+ regulator-min-microvolt = < 850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps7_reg: smps7 {
+ /* VDD_CORE */
+ regulator-name = "smps7";
+ regulator-min-microvolt = < 850000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps8_reg: smps8 {
+ /* VDD_IVA */
+ regulator-name = "smps8";
+ regulator-min-microvolt = < 850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps9_reg: smps9 {
+ /* PMIC_3V3 */
+ regulator-name = "smps9";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+
+ ldo1_reg: ldo1 {
+ /* VDD_SD / VDDSHV8 */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: ldo2 {
+ /* VDD_1V8 */
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo3_reg: ldo3 {
+ /* VDDA_1V8_PHYA - supplies VDDA_SATA, VDDA_USB1/2/3 */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ /* VDDA_1V8_PHYB - supplies VDDA_HDMI, VDDA_PCIE/0/1 */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo9_reg: ldo9 {
+ /* VDD_RTC */
+ regulator-name = "ldo9";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldoln_reg: ldoln {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldoln";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldousb_reg: ldousb {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldousb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* regen1 not used */
+ };
+ };
+
+ tps659038_pwr_button: tps659038_pwr_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps659038>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <12>;
+ };
+
+ tps659038_gpio: tps659038_gpio {
+ compatible = "ti,palmas-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ rtc0: rtc@56 {
+ compatible = "emmicro,em3027";
+ reg = <0x56>;
+ };
+
+ eeprom_module: atmel@50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ wm8731: wm8731@1a {
+ #sound-dai-cells = <0>;
+ compatible = "wlf,wm8731";
+ reg = <0x1a>;
+ status = "okay";
+ };
+};
+
+&cpu0 {
+ cpu0-supply = <&smps12_reg>;
+ voltage-tolerance = <1>;
+};
+
+&sata {
+ status = "okay";
+};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ status = "okay";
+ };
+};
+
+&mmc2 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_default>;
+
+ vmmc-supply = <&vdd_3v3>;
+ bus-width = <8>;
+ ti,non-removable;
+ cap-mmc-dual-data-rate;
+};
+
+&qspi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi1_pins>;
+
+ spi-max-frequency = <48000000>;
+
+ spi_flash: spi_flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,m25p80", "jedec,spi-nor";
+ reg = <0>; /* CS0 */
+ spi-max-frequency = <48000000>;
+
+ partition@0 {
+ label = "uboot";
+ reg = <0x0 0xc0000>;
+ };
+
+ partition@c0000 {
+ label = "uboot environment";
+ reg = <0xc0000 0x40000>;
+ };
+
+ partition@100000 {
+ label = "reserved";
+ reg = <0x100000 0x0>;
+ };
+ };
+
+ /* touch controller */
+ ads7846@0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ads7846_pins>;
+
+ compatible = "ti,ads7846";
+ vcc-supply = <&ads7846reg>;
+
+ reg = <1>; /* CS1 */
+ spi-max-frequency = <1500000>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <31 0>;
+ pendown-gpio = <&gpio1 31 0>;
+
+
+ ti,x-min = /bits/ 16 <0x0>;
+ ti,x-max = /bits/ 16 <0x0fff>;
+ ti,y-min = /bits/ 16 <0x0>;
+ ti,y-max = /bits/ 16 <0x0fff>;
+
+ ti,x-plate-ohms = /bits/ 16 <180>;
+ ti,pressure-max = /bits/ 16 <255>;
+
+ ti,debounce-max = /bits/ 16 <30>;
+ ti,debounce-tol = /bits/ 16 <10>;
+ ti,debounce-rep = /bits/ 16 <1>;
+
+ wakeup-source;
+ };
+};
+
+&mac {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_pins_default>;
+ pinctrl-1 = <&cpsw_pins_sleep>;
+ dual_emac;
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "rgmii-txid";
+ dual_emac_res_vlan = <0>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rgmii-txid";
+ dual_emac_res_vlan = <1>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_pins_default>;
+ pinctrl-1 = <&davinci_mdio_pins_sleep>;
+};
+
+&usb2_phy1 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&usb1 {
+ dr_mode = "host";
+};
+
+&usb2 {
+ dr_mode = "host";
+};
+
+&mcasp3 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mcasp3_pins_default>;
+ pinctrl-1 = <&mcasp3_pins_sleep>;
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializers */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+};
+
+&gpio3 {
+ status = "okay";
+ ti,no-reset-on-init;
+};
+
+&gpio2 {
+ status = "okay";
+ ti,no-reset-on-init;
+};
regulator-always-on;
regulator-boot-on;
};
+
+ leds-iio {
+ status = "disabled";
+ compatible = "gpio-leds";
+ led-out0 {
+ label = "out0";
+ gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out1 {
+ label = "out1";
+ gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out2 {
+ label = "out2";
+ gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out3 {
+ label = "out3";
+ gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out4 {
+ label = "out4";
+ gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out5 {
+ label = "out5";
+ gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out6 {
+ label = "out6";
+ gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-out7 {
+ label = "out7";
+ gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&dra7_pmx_core {
+ dcan1_pins_default: dcan1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
+ DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0) /* dcan1_rx */
+ >;
+ };
+
+ dcan1_pins_sleep: dcan1_pins_sleep {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
+ DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */
+ >;
+ };
};
&i2c1 {
#interrupt-cells = <2>;
interrupt-controller;
ti,system-power-controller;
+ ti,palmas-override-powerhold;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
gpio-controller;
#gpio-cells = <2>;
};
+
+ extcon_usb2: tps659038_usb {
+ compatible = "ti,palmas-usb-vid";
+ ti,enable-vbus-detection;
+ ti,enable-id-detection;
+ /* ID & VBUS GPIOs provided in board dts */
+ };
+ };
+
+ tpic2810: tpic2810@60 {
+ compatible = "ti,tpic2810";
+ reg = <0x60>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&mcspi3 {
+ status = "okay";
+ ti,pindir-d0-out-d1-in;
+
+ sn65hvs882: sn65hvs882@0 {
+ compatible = "pisosr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpol;
};
};
};
&usb2 {
- dr_mode = "otg";
+ dr_mode = "peripheral";
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&v3_3d>;
+ vqmmc-supply = <&ldo1_reg>;
+ bus-width = <4>;
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
};
&mmc2 {
max-frequency = <96000000>;
};
+&dcan1 {
+ status = "okay";
+ pinctrl-names = "default", "sleep", "active";
+ pinctrl-0 = <&dcan1_pins_sleep>;
+ pinctrl-1 = <&dcan1_pins_sleep>;
+ pinctrl-2 = <&dcan1_pins_default>;
+};
+
&qspi {
status = "okay";
spi-max-frequency = <76800000>;
m25p80@0 {
- compatible = "s25fl256s1", "spi-flash", "jedec,spi-nor";
+ compatible = "s25fl256s1", "jedec,spi-nor";
spi-max-frequency = <76800000>;
reg = <0>;
spi-tx-bus-width = <1>;
--- /dev/null
+/*
+ * Support for CompuLab SBC-AM57x single board computer
+ *
+ * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
+ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#include "am57xx-cl-som-am57x.dts"
+#include "compulab-sb-som.dtsi"
+
+/ {
+ model = "CompuLab CL-SOM-AM57x on SB-SOM-AM57x";
+ compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
+
+ aliases {
+ display0 = &lcd0;
+ display1 = &hdmi;
+ };
+};
+
+&dra7_pmx_core {
+ uart3_pins_default: uart3_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
+ DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
+ >;
+ };
+
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1_sdcd.gpio6_27 */
+ DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT | MUX_MODE14) /* mmc1_sdwp.gpio6_28 */
+ >;
+ };
+
+ usb1_pins: pinmux_usb1_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
+ >;
+ };
+
+ i2c5_pins_default: i2c5_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
+ DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
+ >;
+ };
+
+ lcd_pins_default: lcd_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14) /* vin2a_vsync0.gpio4_0 */
+ >;
+ };
+
+ hdmi_pins: pinmux_hdmi_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
+ DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
+ >;
+ };
+
+ hdmi_conn_pins: pinmux_hdmi_conn_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT | MUX_MODE14) /* spi1_cs2.gpio7_12 */
+ >;
+ };
+};
+
+&uart3 {
+ status = "okay";
+ interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <&dra7_pmx_core 0x3f8>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins_default>;
+};
+
+&mmc1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_default>;
+
+ vmmc-supply = <&ldo1_reg>;
+ bus-width = <4>;
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>;
+};
+
+&usb1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins>;
+};
+
+&i2c5 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom_base: atmel@54 {
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ pagesize = <16>;
+ };
+
+ pca9555: pca9555@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&dss {
+ status = "ok";
+
+ vdda_video-supply = <&ldoln_reg>;
+
+ port {
+ dpi_lcd_out: endpoint {
+ remote-endpoint = <&lcd_in>;
+ data-lines = <24>;
+ };
+ };
+};
+
+&lcd0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pins_default>;
+
+ enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH
+ &gpio4 0 GPIO_ACTIVE_HIGH>;
+
+ port {
+ lcd_in: endpoint {
+ remote-endpoint = <&dpi_lcd_out>;
+ data-lines = <24>;
+ };
+ };
+};
+
+&hdmi {
+ status = "ok";
+ vdda-supply = <&ldo4_reg>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ lanes = <1 0 3 2 5 4 7 6>;
+ };
+ };
+};
+
+&hdmi_conn {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_conn_pins>;
+
+ hpd-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+};
--- /dev/null
+/*
+ * at91-sama5d27_som1_ek.dts - Device Tree file for SAMA5D27 SOM1 EK board
+ *
+ * Copyright (C) 2017 Microchip Corporation
+ * Wenyou Yang <wenyou.yang@microchip.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "sama5d27_som1.dtsi"
+
+/ {
+ model = "Atmel SAMA5D27 SOM1 EK";
+ compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d2", "atmel,sama5";
+
+ chosen {
+ u-boot,dm-pre-reloc;
+ stdout-path = &uart1;
+ };
+
+ ahb {
+ usb1: ohci@00400000 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <&pioA 42 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+ };
+
+ usb2: ehci@00500000 {
+ status = "okay";
+ };
+
+ sdmmc0: sdio-host@a0000000 {
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ sdmmc1: sdio-host@b0000000 {
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>;
+ status = "okay"; /* conflict with qspi0 */
+ u-boot,dm-pre-reloc;
+ };
+
+ apb {
+ hlcdc: hlcdc@f0000000 {
+ atmel,vl-bpix = <4>;
+ atmel,guard-time = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ display-timings {
+ u-boot,dm-pre-reloc;
+ 480x272 {
+ clock-frequency = <9000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hsync-len = <41>;
+ hfront-porch = <2>;
+ hback-porch = <2>;
+ vfront-porch = <2>;
+ vback-porch = <2>;
+ vsync-len = <11>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+ };
+
+ uart1: serial@f8020000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ pioA: gpio@fc038000 {
+ pinctrl {
+ pinctrl_lcd_base: pinctrl_lcd_base {
+ pinmux = <PIN_PC5__LCDVSYNC>,
+ <PIN_PC6__LCDHSYNC>,
+ <PIN_PC8__LCDDEN>,
+ <PIN_PC7__LCDPCK>;
+ bias-disable;
+ };
+
+ pinctrl_lcd_pwm: pinctrl_lcd_pwm {
+ pinmux = <PIN_PC3__LCDPWM>;
+ bias-disable;
+ };
+
+ pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 {
+ pinmux = <PIN_PB13__LCDDAT2>,
+ <PIN_PB14__LCDDAT3>,
+ <PIN_PB15__LCDDAT4>,
+ <PIN_PB16__LCDDAT5>,
+ <PIN_PB17__LCDDAT6>,
+ <PIN_PB18__LCDDAT7>,
+ <PIN_PB21__LCDDAT10>,
+ <PIN_PB22__LCDDAT11>,
+ <PIN_PB23__LCDDAT12>,
+ <PIN_PB24__LCDDAT13>,
+ <PIN_PB25__LCDDAT14>,
+ <PIN_PB26__LCDDAT15>,
+ <PIN_PB29__LCDDAT18>,
+ <PIN_PB30__LCDDAT19>,
+ <PIN_PB31__LCDDAT20>,
+ <PIN_PC0__LCDDAT21>,
+ <PIN_PC1__LCDDAT22>,
+ <PIN_PC2__LCDDAT23>;
+ bias-disable;
+ };
+
+ pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
+ pinmux = <PIN_PA1__SDMMC0_CMD>,
+ <PIN_PA2__SDMMC0_DAT0>,
+ <PIN_PA3__SDMMC0_DAT1>,
+ <PIN_PA4__SDMMC0_DAT2>,
+ <PIN_PA5__SDMMC0_DAT3>,
+ <PIN_PA6__SDMMC0_DAT4>,
+ <PIN_PA7__SDMMC0_DAT5>,
+ <PIN_PA8__SDMMC0_DAT6>,
+ <PIN_PA9__SDMMC0_DAT7>;
+ bias-pull-up;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
+ pinmux = <PIN_PA0__SDMMC0_CK>,
+ <PIN_PA10__SDMMC0_RSTN>,
+ <PIN_PA13__SDMMC0_CD>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default {
+ pinmux = <PIN_PA28__SDMMC1_CMD>,
+ <PIN_PA18__SDMMC1_DAT0>,
+ <PIN_PA19__SDMMC1_DAT1>,
+ <PIN_PA20__SDMMC1_DAT2>,
+ <PIN_PA21__SDMMC1_DAT3>;
+ bias-pull-up;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default {
+ pinmux = <PIN_PA22__SDMMC1_CK>,
+ <PIN_PA30__SDMMC1_CD>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_uart1_default: uart1_default {
+ pinmux = <PIN_PD2__URXD1>,
+ <PIN_PD3__UTXD1>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_usb_default: usb_default {
+ pinmux = <PIN_PB10__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_usba_vbus: usba_vbus {
+ pinmux = <PIN_PA31__GPIO>;
+ bias-disable;
+ };
+ };
+ };
+ };
+ };
+};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "okay";
+
+ i2c_eeprom: i2c_eeprom@5c {
+ compatible = "atmel,24mac402";
+ reg = <0x5c>;
+ };
};
pioA: gpio@fc038000 {
i2c0: i2c@f8014000 {
status = "okay";
+
+ i2c_eeprom: i2c_eeprom@5c {
+ compatible = "atmel,24mac402";
+ reg = <0x5c>;
+ };
};
macb0: ethernet@f8020000 {
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clk/ti-dra7-atl.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ extcon_usb1: extcon_usb1 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ sound0: sound0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "DRA7xx-EVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Out",
+ "Microphone", "Mic Jack",
+ "Line", "Line In";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT",
+ "MIC3L", "Mic Jack",
+ "MIC3R", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;
+ simple-audio-card,bitclock-inversion;
+
+ sound0_master: simple-audio-card,cpu {
+ sound-dai = <&mcasp3>;
+ system-clock-frequency = <5644800>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ clocks = <&atl_clkin2_ck>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led0 {
+ label = "dra7:usr1";
+ gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led1 {
+ label = "dra7:usr2";
+ gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led2 {
+ label = "dra7:usr3";
+ gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "dra7:usr4";
+ gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ USER1 {
+ label = "btnUser1";
+ linux,code = <BTN_0>;
+ gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
+ };
+
+ USER2 {
+ label = "btnUser2";
+ linux,code = <BTN_1>;
+ gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&i2c3 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&mcspi1 {
+ status = "okay";
+};
+
+&mcspi2 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+ interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <&dra7_pmx_core 0x3e0>;
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+
+ spi-max-frequency = <76800000>;
+ m25p80@0 {
+ compatible = "s25fl256s1";
+ spi-max-frequency = <76800000>;
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* MTD partition table.
+ * The ROM checks the first four physical blocks
+ * for a valid file to boot and the flash here is
+ * 64KiB block size.
+ */
+ partition@0 {
+ label = "QSPI.SPL";
+ reg = <0x00000000 0x000010000>;
+ };
+ partition@1 {
+ label = "QSPI.SPL.backup1";
+ reg = <0x00010000 0x00010000>;
+ };
+ partition@2 {
+ label = "QSPI.SPL.backup2";
+ reg = <0x00020000 0x00010000>;
+ };
+ partition@3 {
+ label = "QSPI.SPL.backup3";
+ reg = <0x00030000 0x00010000>;
+ };
+ partition@4 {
+ label = "QSPI.u-boot";
+ reg = <0x00040000 0x00100000>;
+ };
+ partition@5 {
+ label = "QSPI.u-boot-spl-os";
+ reg = <0x00140000 0x00080000>;
+ };
+ partition@6 {
+ label = "QSPI.u-boot-env";
+ reg = <0x001c0000 0x00010000>;
+ };
+ partition@7 {
+ label = "QSPI.u-boot-env.backup1";
+ reg = <0x001d0000 0x0010000>;
+ };
+ partition@8 {
+ label = "QSPI.kernel";
+ reg = <0x001e0000 0x0800000>;
+ };
+ partition@9 {
+ label = "QSPI.file-system";
+ reg = <0x009e0000 0x01620000>;
+ };
+ };
+};
+
+&omap_dwc3_1 {
+ extcon = <&extcon_usb1>;
+};
+
+&usb1 {
+ dr_mode = "otg";
+ extcon = <&extcon_usb1>;
+};
+
+&usb2 {
+ dr_mode = "host";
+};
+
+&atl {
+ assigned-clocks = <&abe_dpll_sys_clk_mux>,
+ <&atl_gfclk_mux>,
+ <&dpll_abe_ck>,
+ <&dpll_abe_m2x2_ck>,
+ <&atl_clkin2_ck>;
+ assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
+ assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
+
+ status = "okay";
+
+ atl2 {
+ bws = <DRA7_ATL_WS_MCASP2_FSX>;
+ aws = <DRA7_ATL_WS_MCASP3_FSX>;
+ };
+};
+
+&mcasp3 {
+ #sound-dai-cells = <0>;
+
+ assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clock-parents = <&atl_clkin2_ck>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ status = "okay";
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "omap5-u-boot.dtsi"
+
+&pcf_gpio_21{
+ u-boot,i2c-offset-len = <0>;
+};
+
+&pcf_hdmi{
+ u-boot,i2c-offset-len = <0>;
+};
/dts-v1/;
#include "dra74x.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clk/ti-dra7-atl.h>
-#include <dt-bindings/input/input.h>
+#include "dra7-evm-common.dtsi"
+#include "dra74x-mmc-iodelay.dtsi"
/ {
model = "TI DRA742";
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
- chosen {
- stdout-path = &uart1;
- tick-timer = &timer2;
- };
-
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
};
+ evm_1v8_sw: fixedregulator-evm_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_1v8";
+ vin-supply = <&smps9_reg>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
evm_3v3_sd: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sd";
regulator-max-microvolt = <1800000>;
};
- extcon_usb1: extcon_usb1 {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
- };
-
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
};
- sound0: sound0 {
- compatible = "simple-audio-card";
- simple-audio-card,name = "DRA7xx-EVM";
- simple-audio-card,widgets =
- "Headphone", "Headphone Jack",
- "Line", "Line Out",
- "Microphone", "Mic Jack",
- "Line", "Line In";
- simple-audio-card,routing =
- "Headphone Jack", "HPLOUT",
- "Headphone Jack", "HPROUT",
- "Line Out", "LLOUT",
- "Line Out", "RLOUT",
- "MIC3L", "Mic Jack",
- "MIC3R", "Mic Jack",
- "Mic Jack", "Mic Bias",
- "LINE1L", "Line In",
- "LINE1R", "Line In";
- simple-audio-card,format = "dsp_b";
- simple-audio-card,bitclock-master = <&sound0_master>;
- simple-audio-card,frame-master = <&sound0_master>;
- simple-audio-card,bitclock-inversion;
-
- sound0_master: simple-audio-card,cpu {
- sound-dai = <&mcasp3>;
- system-clock-frequency = <5644800>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&tlv320aic3106>;
- clocks = <&atl_clkin2_ck>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- led0 {
- label = "dra7:usr1";
- gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led1 {
- label = "dra7:usr2";
- gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led2 {
- label = "dra7:usr3";
- gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led3 {
- label = "dra7:usr4";
- gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- autorepeat;
-
- USER1 {
- label = "btnUser1";
- linux,code = <BTN_0>;
- gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
- };
-
- USER2 {
- label = "btnUser2";
- linux,code = <BTN_1>;
- gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
- };
- };
};
&dra7_pmx_core {
- pinctrl-names = "default";
- pinctrl-0 = <&vtt_pin>;
-
- vtt_pin: pinmux_vtt_pin {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
- >;
- };
-
- i2c1_pins: pinmux_i2c1_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
- DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
- >;
- };
-
- i2c2_pins: pinmux_i2c2_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
- DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
- >;
- };
-
- i2c3_pins: pinmux_i2c3_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
- DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
- >;
- };
-
- mcspi1_pins: pinmux_mcspi1_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */
- DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */
- DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */
- DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
- DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
- DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
- >;
- };
-
- mcspi2_pins: pinmux_mcspi2_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */
- DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
- DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
- DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
- >;
- };
-
- uart1_pins: pinmux_uart1_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
- DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
- DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
- DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
- >;
- };
-
- uart2_pins: pinmux_uart2_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */
- DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */
- DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
- DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
- >;
- };
-
- uart3_pins: pinmux_uart3_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
- DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
- >;
- };
-
- usb1_pins: pinmux_usb1_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
- >;
- };
-
- usb2_pins: pinmux_usb2_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
- >;
- };
-
- nand_flash_x16: nand_flash_x16 {
- /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
- * So NAND flash requires following switch settings:
- * SW5.1 (NAND_BOOTn) = ON (LOW)
- * SW5.9 (GPMC_WPN) = OFF (HIGH)
- */
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
- DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
- DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
- DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
- DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
- DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
- DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
- DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
- DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
- DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
- DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
- DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
- DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
- DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
- DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
- DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
- DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
- DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
- DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
- DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
- DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
- DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
- >;
- };
-
- cpsw_default: cpsw_default {
- pinctrl-single,pins = <
- /* Slave 1 */
- DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
- DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
- DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
- DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
- DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
- DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
- DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
- DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
- DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
- DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
- DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
- DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
-
- /* Slave 2 */
- DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
- DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
- DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
- DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
- DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
- DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
- DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
- DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
- DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
- DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
- DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
- DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
- >;
-
- };
-
- cpsw_sleep: cpsw_sleep {
- pinctrl-single,pins = <
- /* Slave 1 */
- DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15)
-
- /* Slave 2 */
- DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
- >;
- };
-
- davinci_mdio_default: davinci_mdio_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
- DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
- >;
- };
-
- davinci_mdio_sleep: davinci_mdio_sleep {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
- >;
- };
-
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
>;
};
- atl_pins: pinmux_atl_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
- DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
- >;
- };
-
- mcasp3_pins: pinmux_mcasp3_pins {
+ mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
- DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
- DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
- DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
+ DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
- mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
+ mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15)
- DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
};
&i2c1 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
tps659038: tps659038@58 {
compatible = "ti,tps659038";
reg = <0x58>;
+ ti,palmas-override-powerhold;
+ ti,system-power-controller;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
- u-boot,i2c-offset-len = <0>;
};
tlv320aic3106: tlv320aic3106@19 {
&i2c2 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
pcf_hdmi: gpio@26 {
};
};
-&i2c3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins>;
- clock-frequency = <400000>;
-};
-
-&mcspi1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcspi1_pins>;
-};
-
-&mcspi2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcspi2_pins>;
-};
-
-&uart1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
- interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <&dra7_pmx_core 0x3e0>;
-};
-
-&uart2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
-};
-
-&uart3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
-};
-
&mmc1 {
status = "okay";
vmmc-supply = <&evm_3v3_sd>;
- vmmc_aux-supply = <&ldo1_reg>;
+ vqmmc-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is always hardwired.
*/
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
+ pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
+ pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};
&mmc2 {
status = "okay";
- vmmc-supply = <&evm_3v3_sw>;
+ vmmc-supply = <&evm_1v8_sw>;
bus-width = <8>;
+ pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>;
+ pinctrl-3 = <&mmc2_pins_ddr_rev20>;
+ pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>;
+ pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
};
&cpu0 {
cpu0-supply = <&smps123_reg>;
};
-&qspi {
- status = "okay";
-
- spi-max-frequency = <76800000>;
- m25p80@0 {
- compatible = "s25fl256s1", "spi-flash";
- spi-max-frequency = <76800000>;
- reg = <0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* MTD partition table.
- * The ROM checks the first four physical blocks
- * for a valid file to boot and the flash here is
- * 64KiB block size.
- */
- partition@0 {
- label = "QSPI.SPL";
- reg = <0x00000000 0x000010000>;
- };
- partition@1 {
- label = "QSPI.SPL.backup1";
- reg = <0x00010000 0x00010000>;
- };
- partition@2 {
- label = "QSPI.SPL.backup2";
- reg = <0x00020000 0x00010000>;
- };
- partition@3 {
- label = "QSPI.SPL.backup3";
- reg = <0x00030000 0x00010000>;
- };
- partition@4 {
- label = "QSPI.u-boot";
- reg = <0x00040000 0x00100000>;
- };
- partition@5 {
- label = "QSPI.u-boot-spl-os";
- reg = <0x00140000 0x00080000>;
- };
- partition@6 {
- label = "QSPI.u-boot-env";
- reg = <0x001c0000 0x00010000>;
- };
- partition@7 {
- label = "QSPI.u-boot-env.backup1";
- reg = <0x001d0000 0x0010000>;
- };
- partition@8 {
- label = "QSPI.kernel";
- reg = <0x001e0000 0x0800000>;
- };
- partition@9 {
- label = "QSPI.file-system";
- reg = <0x009e0000 0x01620000>;
- };
- };
-};
-
-&omap_dwc3_1 {
- extcon = <&extcon_usb1>;
-};
-
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
-&usb1 {
- dr_mode = "peripheral";
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins>;
-};
-
-&usb2 {
- dr_mode = "host";
- pinctrl-names = "default";
- pinctrl-0 = <&usb2_pins>;
-};
-
&elm {
status = "okay";
};
&gpmc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&nand_flash_x16>;
+ /*
+ * For the existing IOdelay configuration via U-Boot we don't
+ * support NAND on dra7-evm. Keep it disabled. Enabling it
+ * requires a different configuration by U-Boot.
+ */
+ status = "disabled";
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
compatible = "ti,omap2-nand";
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
+ ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
&mac {
status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&cpsw_default>;
- pinctrl-1 = <&cpsw_sleep>;
dual_emac;
};
dual_emac_res_vlan = <2>;
};
-&davinci_mdio {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&davinci_mdio_default>;
- pinctrl-1 = <&davinci_mdio_sleep>;
-};
-
&dcan1 {
status = "ok";
pinctrl-names = "default", "sleep", "active";
pinctrl-2 = <&dcan1_pins_default>;
};
-&atl {
- pinctrl-names = "default";
- pinctrl-0 = <&atl_pins>;
-
- assigned-clocks = <&abe_dpll_sys_clk_mux>,
- <&atl_gfclk_mux>,
- <&dpll_abe_ck>,
- <&dpll_abe_m2x2_ck>,
- <&atl_clkin2_ck>;
- assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
- assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
-
+&pcie1_rc {
status = "okay";
-
- atl2 {
- bws = <DRA7_ATL_WS_MCASP2_FSX>;
- aws = <DRA7_ATL_WS_MCASP3_FSX>;
- };
-};
-
-&mcasp3 {
- #sound-dai-cells = <0>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&mcasp3_pins>;
- pinctrl-1 = <&mcasp3_sleep_pins>;
-
- assigned-clocks = <&mcasp3_ahclkx_mux>;
- assigned-clock-parents = <&atl_clkin2_ck>;
-
- status = "okay";
-
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
- /* 4 serializer */
- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
- 1 2 0 0
- >;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
-};
-
-&mailbox5 {
- status = "okay";
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
- status = "okay";
- };
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
- status = "okay";
- };
-};
-
-&mailbox6 {
- status = "okay";
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
- status = "okay";
- };
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
- status = "okay";
- };
};
compatible = "ti,dra7xx";
interrupt-parent = <&crossbar_mpu>;
+ chosen { };
aliases {
i2c0 = &i2c1;
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x0 0x48211000 0x0 0x1000>,
- <0x0 0x48212000 0x0 0x1000>,
+ <0x0 0x48212000 0x0 0x2000>,
<0x0 0x48214000 0x0 0x2000>,
<0x0 0x48216000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
compatible = "arm,cortex-a15";
reg = <0>;
- operating-points = <
- /* kHz uV */
- 1000000 1060000
- 1176000 1160000
- >;
+ operating-points-v2 = <&cpu0_opp_table>;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
};
};
+ cpu0_opp_table: opp-table {
+ compatible = "operating-points-v2-ti-cpu";
+ syscon = <&scm_wkup>;
+
+ opp_nom-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1060000 850000 1150000>;
+ opp-supported-hw = <0xFF 0x01>;
+ opp-suspend;
+ };
+
+ opp_od-1176000000 {
+ opp-hz = /bits/ 64 <1176000000>;
+ opp-microvolt = <1160000 885000 1160000>;
+ opp-supported-hw = <0xFF 0x02>;
+ };
+ };
+
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
reg = <0x1400 0x0468>;
#address-cells = <1>;
#size-cells = <0>;
+ #pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
scm_conf1: scm_conf@1c04 {
compatible = "syscon";
reg = <0x1c04 0x0020>;
+ #syscon-cells = <2>;
};
scm_conf_pcie: scm_conf@1c24 {
#address-cells = <1>;
ranges = <0x51000000 0x51000000 0x3000
0x0 0x20000000 0x10000000>;
- pcie1: pcie@51000000 {
+ /**
+ * To enable PCI endpoint mode, disable the pcie1_rc
+ * node and enable pcie1_ep mode.
+ */
+ pcie1_rc: pcie@51000000 {
compatible = "ti,dra7-pcie";
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
device_type = "pci";
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
+ bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
num-lanes = <1>;
linux,pci-domain = <0>;
<0 0 0 2 &pcie1_intc 2>,
<0 0 0 3 &pcie1_intc 3>,
<0 0 0 4 &pcie1_intc 4>;
+ status = "disabled";
pcie1_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
+
+ pcie1_ep: pcie_ep@51000000 {
+ compatible = "ti,dra7-pcie-ep";
+ reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
+ reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
+ interrupts = <0 232 0x4>;
+ num-lanes = <1>;
+ num-ib-windows = <4>;
+ num-ob-windows = <16>;
+ ti,hwmods = "pcie1";
+ phys = <&pcie1_phy>;
+ phy-names = "pcie-phy0";
+ ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
+ status = "disabled";
+ };
};
axi@1 {
device_type = "pci";
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x30013000 0x13000 0 0xffed000>;
+ bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
num-lanes = <1>;
linux,pci-domain = <1>;
reg = <0x40d00000 0x100>;
};
+ dra7_iodelay_core: padconf@4844a000 {
+ compatible = "ti,dra7-iodelay";
+ reg = <0x4844a000 0x0d1c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <2>;
+ };
+
sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>;
uart1: serial@4806a000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806a000 0x100>;
- reg-shift = <2>;
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
uart2: serial@4806c000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806c000 0x100>;
- reg-shift = <2>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
clock-frequency = <48000000>;
uart3: serial@48020000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48020000 0x100>;
- reg-shift = <2>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
clock-frequency = <48000000>;
uart4: serial@4806e000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806e000 0x100>;
- reg-shift = <2>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
clock-frequency = <48000000>;
uart5: serial@48066000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48066000 0x100>;
- reg-shift = <2>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart5";
clock-frequency = <48000000>;
uart6: serial@48068000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48068000 0x100>;
- reg-shift = <2>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart6";
clock-frequency = <48000000>;
uart7: serial@48420000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48420000 0x100>;
- reg-shift = <2>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart7";
clock-frequency = <48000000>;
uart8: serial@48422000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48422000 0x100>;
- reg-shift = <2>;
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart8";
clock-frequency = <48000000>;
uart9: serial@48424000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48424000 0x100>;
- reg-shift = <2>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart9";
clock-frequency = <48000000>;
uart10: serial@4ae2b000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4ae2b000 0x100>;
- reg-shift = <2>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart10";
clock-frequency = <48000000>;
dma-names = "tx", "rx";
status = "disabled";
pbias-supply = <&pbias_mmc_reg>;
+ max-frequency = <192000000>;
};
mmc2: mmc@480b4000 {
dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
dma-names = "tx", "rx";
status = "disabled";
+ max-frequency = <192000000>;
};
mmc3: mmc@480ad000 {
dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
dma-names = "tx", "rx";
status = "disabled";
+ /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
+ max-frequency = <64000000>;
};
mmc4: mmc@480d1000 {
dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
dma-names = "tx", "rx";
status = "disabled";
+ max-frequency = <192000000>;
};
mmu0_dsp1: mmu@40d01000 {
phy-names = "sata-phy";
clocks = <&sata_ref_clk>;
ti,hwmods = "sata";
+ ports-implemented = <0x1>;
};
rtc: rtc@48838000 {
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
- no_bd_ram = <0>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
cpts_clock_mult = <0x784CFE14>;
cpts_clock_shift = <29>;
- syscon = <&scm_conf>;
reg = <0x48484000 0x1000
0x48485200 0x2E00>;
#address-cells = <1>;
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
ranges;
+ syscon = <&scm_conf>;
status = "disabled";
davinci_mdio: mdio@48485000 {
&cpu_thermal {
polling-delay = <500>; /* milliseconds */
+ coefficients = <0 2000>;
+};
+
+&gpu_thermal {
+ coefficients = <0 2000>;
+};
+
+&core_thermal {
+ coefficients = <0 2000>;
+};
+
+&dspeve_thermal {
+ coefficients = <0 2000>;
+};
+
+&iva_thermal {
+ coefficients = <0 2000>;
+};
+
+&cpu_crit {
+ temperature = <120000>; /* milli Celsius */
};
/include/ "dra7xx-clocks.dtsi"
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "omap5-u-boot.dtsi"
+
+&pcf_gpio_21{
+ u-boot,i2c-offset-len = <0>;
+};
+
+&pcf_hdmi{
+ u-boot,i2c-offset-len = <0>;
+};
+
+&cpsw_emac0 {
+ phy-handle = <&dp83867_0>;
+};
+
+&cpsw_emac1 {
+ phy-handle = <&dp83867_1>;
+};
*/
#include "dra72-evm-common.dtsi"
+#include "dra72x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
3000000 0x1>;
};
+ evm_1v8_sw: fixedregulator-evm_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&lp8732_buck0_reg>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
poweroff: gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>;
};
};
+&pcf_lcd {
+ interrupt-parent = <&gpio7>;
+ interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
+};
+
&pcf_gpio_21 {
interrupt-parent = <&gpio7>;
interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
};
&mmc1 {
- vmmc_aux-supply = <&vpo_sd_1v8_3v3>;
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
+ vqmmc-supply = <&vpo_sd_1v8_3v3>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
+ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
+ vmmc-supply = <&evm_1v8_sw>;
};
&mac {
};
&cpsw_emac0 {
- phy-handle = <&dp83867_0>;
+ phy_id = <&davinci_mdio>, <2>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
- phy-handle = <&dp83867_1>;
+ phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <2>;
};
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
- ti,impedance-control = <0x1f>;
+ ti,min-output-impedance;
+ ti,dp83867-rxctrl-strap-quirk;
};
dp83867_1: ethernet-phy@3 {
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
- ti,impedance-control = <0x1f>;
+ ti,min-output-impedance;
+ ti,dp83867-rxctrl-strap-quirk;
};
};
chosen {
stdout-path = &uart1;
- tick-timer = &timer2;
};
evm_12v0: fixedregulator-evm12v0 {
status = "okay";
clock-frequency = <400000>;
+ pcf_lcd: gpio@20 {
+ compatible = "nxp,pcf8575";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
pcf_gpio_21: gpio@21 {
compatible = "ti,pcf8575", "nxp,pcf8575";
- u-boot,i2c-offset-len = <0>;
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
pcf_hdmi: pcf8575@26 {
compatible = "ti,pcf8575", "nxp,pcf8575";
- u-boot,i2c-offset-len = <0>;
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
};
&gpmc {
- status = "okay";
+ /*
+ * For the existing IOdelay configuration via U-Boot we don't
+ * support NAND on dra72-evm. Keep it disabled. Enabling it
+ * requires a different configuration by U-Boot.
+ */
+ status = "disabled";
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
/* To use NAND, DIP switch SW5 must be set like so:
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
+ ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
};
&usb1 {
- dr_mode = "peripheral";
+ dr_mode = "otg";
+ extcon = <&extcon_usb1>;
};
&usb2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_default>;
-
- vmmc-supply = <&evm_3v3_sw>;
bus-width = <8>;
ti,non-removable;
max-frequency = <192000000>;
spi-max-frequency = <76800000>;
m25p80@0 {
- compatible = "s25fl256s1", "spi-flash";
+ compatible = "s25fl256s1";
spi-max-frequency = <76800000>;
reg = <0>;
spi-tx-bus-width = <1>;
status = "okay";
};
};
+
+&pcie1_rc {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "omap5-u-boot.dtsi"
+
+&pcf_gpio_21{
+ u-boot,i2c-offset-len = <0>;
+};
+
+&pcf_hdmi{
+ u-boot,i2c-offset-len = <0>;
+};
+
+&cpsw_emac0 {
+ phy-handle = <&dp83867_0>;
+};
+
+&cpsw_emac1 {
+ phy-handle = <&dp83867_1>;
+};
* published by the Free Software Foundation.
*/
#include "dra72-evm-common.dtsi"
+#include "dra72x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
};
+
+ evm_1v8_sw: fixedregulator-evm_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&smps4_reg>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&i2c1 {
};
&cpsw_emac0 {
- phy-handle = <&dp83867_0>;
+ phy_id = <&davinci_mdio>, <2>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
- phy-handle = <&dp83867_1>;
+ phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <2>;
};
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
+ interrupt-parent = <&gpio6>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ ti,dp83867-rxctrl-strap-quirk;
};
dp83867_1: ethernet-phy@3 {
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
+ interrupt-parent = <&gpio6>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ ti,dp83867-rxctrl-strap-quirk;
};
};
+
+&mmc1 {
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
+ vqmmc-supply = <&ldo1_reg>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
+ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
+ vmmc-supply = <&evm_1v8_sw>;
+};
ti,palmas-long-press-seconds = <6>;
};
};
+
+&usb2_phy1 {
+ phy-supply = <&ldo4_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&ldo4_reg>;
+};
+
+&dss {
+ vdda_video-supply = <&ldo5_reg>;
+};
+
+&mmc1 {
+ vqmmc-supply = <&ldo1_reg>;
+};
* published by the Free Software Foundation.
*/
#include "dra72-evm-common.dtsi"
+#include "dra72x-mmc-iodelay.dtsi"
/ {
model = "TI DRA722";
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
};
+
+ evm_1v8_sw: fixedregulator-evm_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&smps4_reg>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&i2c1 {
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii";
};
+
+&mmc1 {
+ pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
+ pinctrl-2 = <&mmc1_pins_sdr12>;
+ pinctrl-3 = <&mmc1_pins_sdr25>;
+ pinctrl-4 = <&mmc1_pins_sdr50>;
+ pinctrl-5 = <&mmc1_pins_ddr50_rev10>;
+ pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>;
+ vqmmc-supply = <&ldo1_reg>;
+};
+
+&mmc2 {
+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
+ pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr_rev10>;
+ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>;
+ vmmc-supply = <&evm_1v8_sw>;
+};
--- /dev/null
+/*
+ * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs.
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Rules for modifying this file:
+ * a) Update of this file should typically correspond to a datamanual revision.
+ * Datamanual revision that was used should be updated in comment below.
+ * If there is no update to datamanual, do not update the values. If you
+ * need to use values different from that recommended by the datamanual
+ * for your design, then you should consider adding values to the device-
+ * -tree file for your board directly.
+ * b) We keep the mode names as close to the datamanual as possible. So
+ * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
+ * we follow that in code too.
+ * c) If the values change between multiple revisions of silicon, we add
+ * a revision tag to both the new and old entry. Use 'rev10' for PG 1.0,
+ * 'rev20' for PG 2.0 and so on.
+ * d) The node name and node label should be the exact same string. This is
+ * to curb naming creativity and achieve consistency.
+ * e) If in future, DRA71x and DRA72x values differ, then add 'dra71_' and
+ * 'dra72_' tag to entries. Both the new and old entries should gain a tag.
+ *
+ * Datamanual Revisions:
+ *
+ * AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017
+ * AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017
+ * DRA71x : SPRS960B, Revised February 2017
+ */
+
+&dra7_pmx_core {
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr12: mmc1_pins_sdr12 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_hs: mmc1_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr25: mmc1_pins_sdr25 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr50: mmc1_pins_sdr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_ddr50_rev10: mmc1_pins_ddr50_rev10 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_clk.mmc1_clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
+ DRA7XX_CORE_IOPAD(0x375C, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
+ >;
+ };
+
+ mmc1_pins_ddr50_rev20: mmc1_pins_ddr50_rev20 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr104: mmc1_pins_sdr104 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_hs: mmc2_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_ddr_rev10: mmc2_pins_ddr_rev10 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ >;
+ };
+
+ mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_hs200: mmc2_pins_hs200 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+};
+
+&dra7_iodelay_core {
+
+ /* Corresponds to MMC1_MANUAL1 in datamanual */
+ mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
+ pinctrl-pin-array = <
+ 0x618 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */
+ 0x624 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */
+ 0x630 A_DELAY_PS(1375) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */
+ 0x63C A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */
+ 0x648 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */
+ 0x654 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
+ 0x620 A_DELAY_PS(1230) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
+ 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x638 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x644 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x650 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x65C A_DELAY_PS(99) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ >;
+ };
+
+ /* Corresponds to MMC1_MANUAL2 in datamanual */
+ mmc1_iodelay_sdr104_rev10_conf: mmc1_iodelay_sdr104_rev10_conf {
+ pinctrl-pin-array = <
+ 0x620 A_DELAY_PS(560) G_DELAY_PS(365) /* CFG_MMC1_CLK_OUT */
+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x638 A_DELAY_PS(29) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x650 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x65c A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ 0x628 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x634 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x640 A_DELAY_PS(433) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x64c A_DELAY_PS(287) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x658 A_DELAY_PS(351) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ >;
+ };
+
+ /* Corresponds to MMC1_MANUAL2 in datamanual */
+ mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
+ pinctrl-pin-array = <
+ 0x620 A_DELAY_PS(520) G_DELAY_PS(320) /* CFG_MMC1_CLK_OUT */
+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x638 A_DELAY_PS(40) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x644 A_DELAY_PS(83) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x650 A_DELAY_PS(98) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x65c A_DELAY_PS(106) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ 0x628 A_DELAY_PS(51) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x640 A_DELAY_PS(363) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x64c A_DELAY_PS(199) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x658 A_DELAY_PS(273) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ >;
+ };
+
+ /* Corresponds to MMC2_MANUAL1 in datamanual */
+ mmc2_iodelay_ddr_conf: mmc2_iodelay_ddr_conf {
+ pinctrl-pin-array = <
+ 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */
+ 0x1a4 A_DELAY_PS(119) G_DELAY_PS(0) /* CFG_GPMC_A20_IN */
+ 0x1b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_IN */
+ 0x1bc A_DELAY_PS(18) G_DELAY_PS(0) /* CFG_GPMC_A22_IN */
+ 0x1c8 A_DELAY_PS(894) G_DELAY_PS(0) /* CFG_GPMC_A23_IN */
+ 0x1d4 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_IN */
+ 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
+ 0x1ec A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
+ 0x1f8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_IN */
+ 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
+ 0x194 A_DELAY_PS(152) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
+ 0x1ac A_DELAY_PS(206) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b8 A_DELAY_PS(78) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1c4 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1d0 A_DELAY_PS(266) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1f4 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x368 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ >;
+ };
+
+ /* Corresponds to MMC2_MANUAL3 in datamanual */
+ mmc2_iodelay_hs200_rev10_conf: mmc2_iodelay_hs200_rev10_conf {
+ pinctrl-pin-array = <
+ 0x194 A_DELAY_PS(150) G_DELAY_PS(95) /* CFG_GPMC_A19_OUT */
+ 0x1ac A_DELAY_PS(250) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b8 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1c4 A_DELAY_PS(100) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1d0 A_DELAY_PS(870) G_DELAY_PS(415) /* CFG_GPMC_A23_OUT */
+ 0x1dc A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e8 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x368 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ 0x190 A_DELAY_PS(695) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x1a8 A_DELAY_PS(924) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1b4 A_DELAY_PS(719) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1c0 A_DELAY_PS(824) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1d8 A_DELAY_PS(877) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1e4 A_DELAY_PS(446) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1f0 A_DELAY_PS(847) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1fc A_DELAY_PS(586) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x364 A_DELAY_PS(1039) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ >;
+ };
+
+ /* Corresponds to MMC2_MANUAL3 in datamanual */
+ mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {
+ pinctrl-pin-array = <
+ 0x194 A_DELAY_PS(285) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
+ 0x1ac A_DELAY_PS(189) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b8 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_OUT */
+ 0x1c4 A_DELAY_PS(0) G_DELAY_PS(70) /* CFG_GPMC_A22_OUT */
+ 0x1d0 A_DELAY_PS(730) G_DELAY_PS(360) /* CFG_GPMC_A23_OUT */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1f4 A_DELAY_PS(70) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x368 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_CS1_OUT */
+ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x1a8 A_DELAY_PS(231) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1b4 A_DELAY_PS(39) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1c0 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1d8 A_DELAY_PS(176) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1f0 A_DELAY_PS(101) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x364 A_DELAY_PS(360) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ >;
+ };
+};
/ {
compatible = "ti,dra722", "ti,dra72", "ti,dra7";
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0>;
-
- /* cooling options */
- cooling-min-level = <0>;
- cooling-max-level = <2>;
- #cooling-cells = <2>; /* min followed by max */
- };
- };
-
pmu {
compatible = "arm,cortex-a15-pmu";
interrupt-parent = <&wakeupgen>;
<&dss_video1_clk>;
clock-names = "fck", "video1_clk";
};
+
+&mailbox5 {
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ ti,mbox-tx = <6 2 2>;
+ ti,mbox-rx = <4 2 2>;
+ status = "disabled";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ ti,mbox-tx = <5 2 2>;
+ ti,mbox-rx = <1 2 2>;
+ status = "disabled";
+ };
+};
+
+&mailbox6 {
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ ti,mbox-tx = <6 2 2>;
+ ti,mbox-rx = <4 2 2>;
+ status = "disabled";
+ };
+};
--- /dev/null
+/*
+ * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs.
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Rules for modifying this file:
+ * a) Update of this file should typically correspond to a datamanual revision.
+ * Datamanual revision that was used should be updated in comment below.
+ * If there is no update to datamanual, do not update the values. If you
+ * need to use values different from that recommended by the datamanual
+ * for your design, then you should consider adding values to the device-
+ * -tree file for your board directly.
+ * b) We keep the mode names as close to the datamanual as possible. So
+ * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
+ * we follow that in code too.
+ * c) If the values change between multiple revisions of silicon, we add
+ * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,
+ * 'rev20' for PG 2.0 and so on.
+ * d) The node name and node label should be the exact same string. This is
+ * to curb naming creativity and achieve consistency.
+ *
+ * Datamanual Revisions:
+ *
+ * AM572x Silicon Revision 2.0: SPRS953B, Revised November 2016
+ * AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016
+ *
+ */
+
+&dra7_pmx_core {
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr12: mmc1_pins_sdr12 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_hs: mmc1_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr25: mmc1_pins_sdr25 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr50: mmc1_pins_sdr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_ddr50: mmc1_pins_ddr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr104: mmc1_pins_sdr104 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_hs: mmc2_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_ddr_3_3v_rev11: mmc2_pins_ddr_3_3v_rev11 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_ddr_1_8v_rev11: mmc2_pins_ddr_1_8v_rev11 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_hs200: mmc2_pins_hs200 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc4_pins_default: mmc4_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+
+ mmc4_pins_hs: mmc4_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+
+ mmc3_pins_default: mmc3_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc3_pins_hs: mmc3_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc3_pins_sdr12: mmc3_pins_sdr12 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc3_pins_sdr25: mmc3_pins_sdr25 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc3_pins_sdr50: mmc3_pins_sdr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc4_pins_sdr12: mmc4_pins_sdr12 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+
+ mmc4_pins_sdr25: mmc4_pins_sdr25 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+};
+
+&dra7_iodelay_core {
+
+ /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
+ mmc1_iodelay_ddr_rev11_conf: mmc1_iodelay_ddr_rev11_conf {
+ pinctrl-pin-array = <
+ 0x618 A_DELAY_PS(572) G_DELAY_PS(540) /* CFG_MMC1_CLK_IN */
+ 0x620 A_DELAY_PS(1525) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
+ 0x624 A_DELAY_PS(0) G_DELAY_PS(600) /* CFG_MMC1_CMD_IN */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62c A_DELAY_PS(55) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x630 A_DELAY_PS(403) G_DELAY_PS(120) /* CFG_MMC1_DAT0_IN */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x63c A_DELAY_PS(23) G_DELAY_PS(60) /* CFG_MMC1_DAT1_IN */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x648 A_DELAY_PS(25) G_DELAY_PS(60) /* CFG_MMC1_DAT2_IN */
+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
+ mmc1_iodelay_ddr_rev20_conf: mmc1_iodelay_ddr50_rev20_conf {
+ pinctrl-pin-array = <
+ 0x618 A_DELAY_PS(1076) G_DELAY_PS(330) /* CFG_MMC1_CLK_IN */
+ 0x620 A_DELAY_PS(1271) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
+ 0x624 A_DELAY_PS(722) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x630 A_DELAY_PS(751) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(20) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x63C A_DELAY_PS(256) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x648 A_DELAY_PS(263) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */
+ 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
+ mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf {
+ pinctrl-pin-array = <
+ 0x620 A_DELAY_PS(1063) G_DELAY_PS(17) /* CFG_MMC1_CLK_OUT */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62c A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
+ mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
+ pinctrl-pin-array = <
+ 0x620 A_DELAY_PS(600) G_DELAY_PS(400) /* CFG_MMC1_CLK_OUT */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
+ mmc2_iodelay_hs200_rev11_conf: mmc2_iodelay_hs200_rev11_conf {
+ pinctrl-pin-array = <
+ 0x190 A_DELAY_PS(621) G_DELAY_PS(600) /* CFG_GPMC_A19_OEN */
+ 0x194 A_DELAY_PS(300) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
+ 0x1a8 A_DELAY_PS(739) G_DELAY_PS(600) /* CFG_GPMC_A20_OEN */
+ 0x1ac A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b4 A_DELAY_PS(812) G_DELAY_PS(600) /* CFG_GPMC_A21_OEN */
+ 0x1b8 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1c0 A_DELAY_PS(954) G_DELAY_PS(600) /* CFG_GPMC_A22_OEN */
+ 0x1c4 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1d0 A_DELAY_PS(1340) G_DELAY_PS(420) /* CFG_GPMC_A23_OUT */
+ 0x1d8 A_DELAY_PS(935) G_DELAY_PS(600) /* CFG_GPMC_A24_OEN */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e4 A_DELAY_PS(525) G_DELAY_PS(600) /* CFG_GPMC_A25_OEN */
+ 0x1e8 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1f0 A_DELAY_PS(767) G_DELAY_PS(600) /* CFG_GPMC_A26_OEN */
+ 0x1f4 A_DELAY_PS(225) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x1fc A_DELAY_PS(565) G_DELAY_PS(600) /* CFG_GPMC_A27_OEN */
+ 0x200 A_DELAY_PS(60) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x364 A_DELAY_PS(969) G_DELAY_PS(600) /* CFG_GPMC_CS1_OEN */
+ 0x368 A_DELAY_PS(180) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
+ mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {
+ pinctrl-pin-array = <
+ 0x190 A_DELAY_PS(274) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x194 A_DELAY_PS(162) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
+ 0x1a8 A_DELAY_PS(401) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1ac A_DELAY_PS(73) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b4 A_DELAY_PS(465) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1b8 A_DELAY_PS(115) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1c0 A_DELAY_PS(633) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1c4 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1d0 A_DELAY_PS(935) G_DELAY_PS(280) /* CFG_GPMC_A23_OUT */
+ 0x1d8 A_DELAY_PS(621) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e4 A_DELAY_PS(183) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1f0 A_DELAY_PS(467) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x1fc A_DELAY_PS(262) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x200 A_DELAY_PS(46) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x364 A_DELAY_PS(684) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ 0x368 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ >;
+ };
+
+ /* Correspnds to MMC2_DDR_3V3_MANUAL1 in datamanual */
+ mmc2_iodelay_ddr_3_3v_rev11_conf: mmc2_iodelay_ddr_3_3v_rev11_conf {
+ pinctrl-pin-array = <
+ 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
+ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
+ 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
+ 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
+ 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
+ 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
+ 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */
+ 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
+ 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
+ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1ec A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A26_IN */
+ 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */
+ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
+ 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC2_DDR_1V8_MANUAL1 in datamanual */
+ mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf {
+ pinctrl-pin-array = <
+ 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */
+ 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x194 A_DELAY_PS(174) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */
+ 0x1a4 A_DELAY_PS(274) G_DELAY_PS(240) /* CFG_GPMC_A20_IN */
+ 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1ac A_DELAY_PS(168) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b0 A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A21_IN */
+ 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1b8 A_DELAY_PS(136) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1bc A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A22_IN */
+ 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1c4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1c8 A_DELAY_PS(514) G_DELAY_PS(360) /* CFG_GPMC_A23_IN */
+ 0x1d0 A_DELAY_PS(879) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */
+ 0x1d4 A_DELAY_PS(187) G_DELAY_PS(120) /* CFG_GPMC_A24_IN */
+ 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
+ 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1e8 A_DELAY_PS(34) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1ec A_DELAY_PS(0) G_DELAY_PS(60) /* CFG_GPMC_A26_IN */
+ 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1f4 A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x1f8 A_DELAY_PS(121) G_DELAY_PS(60) /* CFG_GPMC_A27_IN */
+ 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
+ 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ 0x368 A_DELAY_PS(11) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC3_MANUAL1 in datamanual */
+ mmc3_iodelay_manual1_rev20_conf: mmc3_iodelay_manual1_conf {
+ pinctrl-pin-array = <
+ 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */
+ 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
+ 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
+ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
+ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
+ 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
+ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
+ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
+ 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
+ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
+ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
+ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
+ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
+ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
+ 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
+ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
+ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC3_MANUAL1 in datamanual */
+ mmc3_iodelay_manual1_rev11_conf: mmc3_iodelay_manual1_conf {
+ pinctrl-pin-array = <
+ 0x678 A_DELAY_PS(406) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */
+ 0x680 A_DELAY_PS(659) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
+ 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
+ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
+ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
+ 0x690 A_DELAY_PS(130) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
+ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
+ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
+ 0x69c A_DELAY_PS(169) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
+ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
+ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
+ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
+ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
+ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
+ 0x6b4 A_DELAY_PS(457) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
+ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
+ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_DS_MANUAL1 in datamanual */
+ mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(96) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(582) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(391) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(561) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_DS_MANUAL1 in datamanual */
+ mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_MANUAL1 in datamanual */
+ mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(2651) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(1572) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(1913) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(1721) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(1891) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(1919) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_MANUAL1 in datamanual */
+ mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+};
compatible = "ti,dra742", "ti,dra74", "ti,dra7";
cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0>;
-
- operating-points = <
- /* kHz uV */
- 1000000 1060000
- 1176000 1160000
- >;
-
- clocks = <&dpll_mpu_ck>;
- clock-names = "cpu";
-
- clock-latency = <300000>; /* From omap-cpufreq driver */
-
- /* cooling options */
- cooling-min-level = <0>;
- cooling-max-level = <2>;
- #cooling-cells = <2>; /* min followed by max */
- };
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
};
};
ocp {
+ dsp2_system: dsp_system@41500000 {
+ compatible = "syscon";
+ reg = <0x41500000 0x100>;
+ };
+
omap_dwc3_4: omap_dwc3_4@48940000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss4";
usb4: usb@48950000 {
compatible = "snps,dwc3";
reg = <0x48950000 0x17000>;
- interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
- tx-fifo-resize;
+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
maximum-speed = "high-speed";
dr_mode = "otg";
};
};
+
+ mmu0_dsp2: mmu@41501000 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x41501000 0x100>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu0_dsp2";
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp2_system 0x0>;
+ status = "disabled";
+ };
+
+ mmu1_dsp2: mmu@41502000 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x41502000 0x100>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu1_dsp2";
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp2_system 0x1>;
+ status = "disabled";
+ };
};
};
+&cpu0_opp_table {
+ opp-shared;
+};
+
&dss {
reg = <0x58000000 0x80>,
<0x58004054 0x4>,
<0x58004300 0x20>,
- <0x58005054 0x4>,
- <0x58005300 0x20>;
+ <0x58009054 0x4>,
+ <0x58009300 0x20>;
reg-names = "dss", "pll1_clkctrl", "pll1",
"pll2_clkctrl", "pll2";
<&dss_video2_clk>;
clock-names = "fck", "video1_clk", "video2_clk";
};
+
+&mailbox5 {
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ ti,mbox-tx = <6 2 2>;
+ ti,mbox-rx = <4 2 2>;
+ status = "disabled";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ ti,mbox-tx = <5 2 2>;
+ ti,mbox-rx = <1 2 2>;
+ status = "disabled";
+ };
+};
+
+&mailbox6 {
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ ti,mbox-tx = <6 2 2>;
+ ti,mbox-rx = <4 2 2>;
+ status = "disabled";
+ };
+ mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ ti,mbox-tx = <5 2 2>;
+ ti,mbox-rx = <1 2 2>;
+ status = "disabled";
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "omap5-u-boot.dtsi"
+
+&cpsw_emac0 {
+ phy-handle = <&dp83867_0>;
+};
+
+&cpsw_emac1 {
+ phy-handle = <&dp83867_1>;
+};
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra76x.dtsi"
+#include "dra7-evm-common.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ model = "TI DRA762 EVM";
+ compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+
+ vsys_12v0: fixedregulator-vsys12v0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_5v0: fixedregulator-vsys5v0 {
+ /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vsys_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vio_3v3: fixedregulator-vio_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vio_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vio_3v3_sd: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vio_3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vio_3v3>;
+ enable-active-high;
+ gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ vio_1v8: fixedregulator-vio_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&smps5_reg>;
+ };
+
+ vtt_fixed: fixedregulator-vtt {
+ compatible = "regulator-fixed";
+ regulator-name = "vtt_fixed";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ aic_dvdd: fixedregulator-aic_dvdd {
+ /* TPS77018DBVT */
+ compatible = "regulator-fixed";
+ regulator-name = "aic_dvdd";
+ vin-supply = <&vio_3v3>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+};
+
+&dra7_pmx_core {
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps65917: tps65917@58 {
+ compatible = "ti,tps65917";
+ reg = <0x58>;
+ ti,system-power-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ tps65917_pmic {
+ compatible = "ti,tps65917-pmic";
+
+ smps12-in-supply = <&vsys_3v3>;
+ smps3-in-supply = <&vsys_3v3>;
+ smps4-in-supply = <&vsys_3v3>;
+ smps5-in-supply = <&vsys_3v3>;
+ ldo1-in-supply = <&vsys_3v3>;
+ ldo2-in-supply = <&vsys_3v3>;
+ ldo3-in-supply = <&vsys_5v0>;
+ ldo4-in-supply = <&vsys_5v0>;
+ ldo5-in-supply = <&vsys_3v3>;
+
+ tps65917_regulators: regulators {
+ smps12_reg: smps12 {
+ /* VDD_DSPEVE */
+ regulator-name = "smps12";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps3_reg: smps3 {
+ /* VDD_CORE */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps4_reg: smps4 {
+ /* VDD_IVA */
+ regulator-name = "smps4";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps5_reg: smps5 {
+ /* VDDS1V8 */
+ regulator-name = "smps5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ /* LDO1_OUT --> VDA_PHY1_1V8 */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-allow-bypass;
+ };
+
+ ldo2_reg: ldo2 {
+ /* LDO2_OUT --> VDA_PHY2_1V8 */
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-bypass;
+ regulator-always-on;
+ };
+
+ ldo3_reg: ldo3 {
+ /* VDA_USB_3V3 */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: ldo5 {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ /* VDD_SDIO_DV */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ tps65917_power_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps65917>;
+ interrupts = <1 IRQ_TYPE_NONE>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <6>;
+ };
+ };
+
+ lp87565: lp87565@60 {
+ compatible = "ti,lp87565-q1";
+ reg = <0x60>;
+
+ buck10-in-supply =<&vsys_3v3>;
+ buck23-in-supply =<&vsys_3v3>;
+
+ regulators: regulators {
+ buck10_reg: buck10 {
+ /*VDD_MPU*/
+ regulator-name = "buck10";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck23_reg: buck23 {
+ /* VDD_GPU*/
+ regulator-name = "buck23";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ pcf_lcd: pcf8757@20 {
+ compatible = "ti,pcf8575", "nxp,pcf8575";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ pcf_gpio_21: pcf8757@21 {
+ compatible = "ti,pcf8575", "nxp,pcf8575";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcf_hdmi: pcf8575@26 {
+ compatible = "ti,pcf8575", "nxp,pcf8575";
+ reg = <0x26>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ p1 {
+ /* vin6_sel_s0: high: VIN6, low: audio */
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "vin6_sel_s0";
+ };
+ };
+
+ tlv320aic3106: tlv320aic3106@19 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x19>;
+ adc-settle-ms = <40>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+ status = "okay";
+
+ /* Regulators */
+ AVDD-supply = <&vio_3v3>;
+ IOVDD-supply = <&vio_3v3>;
+ DRVDD-supply = <&vio_3v3>;
+ DVDD-supply = <&aic_dvdd>;
+ };
+};
+
+&cpu0 {
+ vdd-supply = <&buck10_reg>;
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vio_3v3_sd>;
+ vmmc_aux-supply = <&ldo4_reg>;
+ bus-width = <4>;
+ /*
+ * SDCD signal is not being used here - using the fact that GPIO mode
+ * is always hardwired.
+ */
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_default>;
+};
+
+&mmc2 {
+ status = "okay";
+ vmmc-supply = <&vio_1v8>;
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_default>;
+};
+
+/* No RTC on this device */
+&rtc {
+ status = "disabled";
+};
+
+&mac {
+ status = "okay";
+
+ dual_emac;
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <2>;
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <3>;
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+ dp83867_0: ethernet-phy@2 {
+ reg = <2>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,min-output-impedance;
+ ti,dp83867-rxctrl-strap-quirk;
+ };
+
+ dp83867_1: ethernet-phy@3 {
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,min-output-impedance;
+ ti,dp83867-rxctrl-strap-quirk;
+ };
+};
+
+&usb2_phy1 {
+ phy-supply = <&ldo3_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&ldo3_reg>;
+};
+
+&qspi {
+ spi-max-frequency = <96000000>;
+ m25p80@0 {
+ spi-max-frequency = <96000000>;
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "dra74x.dtsi"
+
+/ {
+ compatible = "ti,dra762", "ti,dra7";
+
+};
+
+/* MCAN interrupts are hard-wired to irqs 67, 68 */
+&crossbar_mpu {
+ ti,irqs-skip = <10 67 68 133 139 140>;
+};
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
+ assigned-clocks = <&dpll_dsp_ck>;
+ assigned-clock-rates = <600000000>;
};
dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
reg = <0x0244>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_dsp_m2_ck>;
+ assigned-clock-rates = <600000000>;
};
iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+ assigned-clocks = <&dpll_iva_ck>;
+ assigned-clock-rates = <1165000000>;
};
dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
reg = <0x01b0>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_iva_m2_ck>;
+ assigned-clock-rates = <388333334>;
};
iva_dclk: iva_dclk {
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
+ assigned-clocks = <&dpll_gpu_ck>;
+ assigned-clock-rates = <1277000000>;
};
dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
reg = <0x02e8>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_gpu_m2_ck>;
+ assigned-clock-rates = <425666667>;
};
dpll_core_m2_ck: dpll_core_m2_ck@130 {
reg = <0x0248>;
ti,index-starts-at-one;
ti,invert-autoidle-bit;
+ assigned-clocks = <&dpll_dsp_m3x2_ck>;
+ assigned-clock-rates = <400000000>;
};
dpll_gmac_x2_ck: dpll_gmac_x2_ck {
clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
ti,bit-shift = <24>;
reg = <0x0520>;
+ assigned-clocks = <&ipu1_gfclk_mux>;
+ assigned-clock-parents = <&dpll_core_h22x2_ck>;
};
mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <24>;
reg = <0x1220>;
+ assigned-clocks = <&gpu_core_gclk_mux>;
+ assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
ti,bit-shift = <26>;
reg = <0x1220>;
+ assigned-clocks = <&gpu_hyd_gclk_mux>;
+ assigned-clock-parents = <&dpll_gpu_m2_ck>;
};
l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
};
i2c-gpio-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "okay";
pcf8563@50 {
--- /dev/null
+/*
+ * NXP ls1088a QDS board device tree source
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1088a.dtsi"
+
+/ {
+ model = "NXP Layerscape 1088a QDS Board";
+ compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
+ aliases {
+ spi0 = &qspi;
+ spi1 = &dspi;
+ };
+};
+
+&dspi {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <1000000>; /* input clock */
+ };
+
+ dflash1: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3500000>;
+ reg = <1>;
+ };
+
+ dflash2: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3500000>;
+ reg = <2>;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fs512s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+
+ qflash1: s25fs512s@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <1>;
+ };
+};
--- /dev/null
+/*
+ * NXP ls1088a RDB board device tree source
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "fsl-ls1088a.dtsi"
+
+/ {
+ model = "NXP Layerscape 1088a RDB Board";
+ compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
+ aliases {
+ spi0 = &qspi;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fs512s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+
+ qflash1: s25fs512s@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <1>;
+ };
+};
--- /dev/null
+/*
+ * NXP ls1088a SOC common device tree source
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ compatible = "fsl,ls1088a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x80000000>;
+ /* DRAM space - 1, size : 2 GB DRAM */
+ };
+
+ gic: interrupt-controller@6000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
+ <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <1 9 0x4>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
+ <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
+ <1 11 0x8>, /* Virtual PPI, active-low */
+ <1 10 0x8>; /* Hypervisor PPI, active-low */
+ };
+
+ serial0: serial@21c0500 {
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0500 0x0 0x100>;
+ clock-frequency = <0>; /* Updated by bootloader */
+ interrupts = <0 32 0x1>; /* edge triggered */
+ };
+
+ serial1: serial@21c0600 {
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0600 0x0 0x100>;
+ clock-frequency = <0>; /* Updated by bootloader */
+ interrupts = <0 32 0x1>; /* edge triggered */
+ };
+
+ fsl_mc: fsl-mc@80c000000 {
+ compatible = "fsl,qoriq-mc";
+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+ };
+
+ dspi: dspi@2100000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <0 26 0x4>; /* Level high type */
+ num-cs = <6>;
+ };
+
+ qspi: quadspi@1550000 {
+ compatible = "fsl,vf610-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ num-cs = <4>;
+ };
+
+ pcie@3400000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03480000 0x0 0x80000 /* lut registers */
+ 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
+ 0x20 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie@3500000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03580000 0x0 0x80000 /* lut registers */
+ 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
+ 0x28 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie@3600000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03680000 0x0 0x80000 /* lut registers */
+ 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
+ 0x30 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2017
+ * Logic PD - http://www.logicpd.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+};
+
+&mmc1 {
+ cd-inverted;
+};
+
+&mmc2 {
+ status = "disabled";
+};
+
+&mmc3 {
+ status = "disabled";
+};
+
+&uart1 {
+ reg-shift = <2>;
+};
+
+&uart2 {
+ reg-shift = <2>;
+};
+
+&uart3 {
+ reg-shift = <2>;
+};
+
model = "LogicPD Zoom DM3730 Torpedo + Wireless Development Kit";
compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3";
- chosen {
- stdout-path = &uart1;
- };
-
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins &mmc1_cd>;
+ cd-gpios = <&gpio4 31 IRQ_TYPE_LEVEL_LOW>; /* gpio127 */
vmmc-supply = <&vmmc1>;
bus-width = <4>;
cap-power-off-card;
};
-&mmc2 {
- status = "disabled";
-};
-
&omap3_pmx_core {
gpio_key_pins: pinmux_gpio_key_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0) /* cam_xclka.cam_xclka */
OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0) /* cam_pclk.cam_pclk */
- OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */
- OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */
- OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */
+ OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */
+ OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */
+ OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */
OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0) /* cam_d3.cam_d3 */
OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0) /* cam_d4.cam_d4 */
OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0) /* cam_d5.cam_d5 */
--- /dev/null
+/*
+ * Device Tree Source for OMAP3 SoC CPU thermal
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+cpu_thermal: cpu_thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+ coefficients = <0 20000>;
+
+ /* sensor ID */
+ thermal-sensors = <&bandgap 0>;
+};
--- /dev/null
+/*
+ * Copyright (C) 2017
+ * Logic PD - http://www.logicpd.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&uart1 {
+ reg-shift = <2>;
+};
+
+&uart2 {
+ reg-shift = <2>;
+};
+
+&uart3 {
+ reg-shift = <2>;
+};
+
#include <dt-bindings/pinctrl/omap.h>
/ {
- compatible = "ti,omap3430", "ti,omap3";
- interrupt-parent = <&intc>;
- #address-cells = <1>;
- #size-cells = <1>;
- chosen { };
-
- aliases {
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- i2c2 = &i2c3;
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- compatible = "arm,cortex-a8";
- device_type = "cpu";
- reg = <0x0>;
-
- clocks = <&dpll1_ck>;
- clock-names = "cpu";
-
- clock-latency = <300000>; /* From omap-cpufreq driver */
- };
- };
-
- pmu@54000000 {
- compatible = "arm,cortex-a8-pmu";
- reg = <0x54000000 0x800000>;
- interrupts = <3>;
- ti,hwmods = "debugss";
- };
-
- /*
- * The soc node represents the soc top level view. It is used for IPs
- * that are not memory mapped in the MPU view or for the MPU itself.
- */
- soc {
- compatible = "ti,omap-infra";
- mpu {
- compatible = "ti,omap3-mpu";
- ti,hwmods = "mpu";
- };
-
- iva: iva {
- compatible = "ti,iva2.2";
- ti,hwmods = "iva";
-
- dsp {
- compatible = "ti,omap3-c64";
- };
- };
- };
-
- /*
- * XXX: Use a flat representation of the OMAP3 interconnect.
- * The real OMAP interconnect network is quite complex.
- * Since it will not bring real advantage to represent that in DT for
- * the moment, just use a fake OCP bus entry to represent the whole bus
- * hierarchy.
- */
- ocp@68000000 {
- compatible = "ti,omap3-l3-smx", "simple-bus";
- reg = <0x68000000 0x10000>;
- interrupts = <9 10>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,hwmods = "l3_main";
-
- l4_core: l4@48000000 {
- compatible = "ti,omap3-l4-core", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x48000000 0x1000000>;
-
- scm: scm@2000 {
- compatible = "ti,omap3-scm", "simple-bus";
- reg = <0x2000 0x2000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x2000 0x2000>;
-
- omap3_pmx_core: pinmux@30 {
- compatible = "ti,omap3-padconf",
- "pinctrl-single";
- reg = <0x30 0x238>;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- pinctrl-single,register-width = <16>;
- pinctrl-single,function-mask = <0xff1f>;
- };
-
- scm_conf: scm_conf@270 {
- compatible = "syscon", "simple-bus";
- reg = <0x270 0x330>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x270 0x330>;
-
- pbias_regulator: pbias_regulator@2b0 {
- compatible = "ti,pbias-omap3", "ti,pbias-omap";
- reg = <0x2b0 0x4>;
- syscon = <&scm_conf>;
- pbias_mmc_reg: pbias_mmc_omap2430 {
- regulator-name = "pbias_mmc_omap2430";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- };
- };
-
- scm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- scm_clockdomains: clockdomains {
- };
-
- omap3_pmx_wkup: pinmux@a00 {
- compatible = "ti,omap3-padconf",
- "pinctrl-single";
- reg = <0xa00 0x5c>;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- pinctrl-single,register-width = <16>;
- pinctrl-single,function-mask = <0xff1f>;
- };
- };
- };
-
- aes: aes@480c5000 {
- compatible = "ti,omap3-aes";
- ti,hwmods = "aes";
- reg = <0x480c5000 0x50>;
- interrupts = <0>;
- dmas = <&sdma 65 &sdma 66>;
- dma-names = "tx", "rx";
- };
-
- prm: prm@48306000 {
- compatible = "ti,omap3-prm";
- reg = <0x48306000 0x4000>;
- interrupts = <11>;
-
- prm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- prm_clockdomains: clockdomains {
- };
- };
-
- cm: cm@48004000 {
- compatible = "ti,omap3-cm";
- reg = <0x48004000 0x4000>;
-
- cm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- cm_clockdomains: clockdomains {
- };
- };
-
- counter32k: counter@48320000 {
- compatible = "ti,omap-counter32k";
- reg = <0x48320000 0x20>;
- ti,hwmods = "counter_32k";
- };
-
- intc: interrupt-controller@48200000 {
- compatible = "ti,omap3-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x48200000 0x1000>;
- };
-
- sdma: dma-controller@48056000 {
- compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
- reg = <0x48056000 0x1000>;
- interrupts = <12>,
- <13>,
- <14>,
- <15>;
- #dma-cells = <1>;
- dma-channels = <32>;
- dma-requests = <96>;
- };
-
- gpio1: gpio@48310000 {
- compatible = "ti,omap3-gpio";
- reg = <0x48310000 0x200>;
- interrupts = <29>;
- ti,hwmods = "gpio1";
- ti,gpio-always-on;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@49050000 {
- compatible = "ti,omap3-gpio";
- reg = <0x49050000 0x200>;
- interrupts = <30>;
- ti,hwmods = "gpio2";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@49052000 {
- compatible = "ti,omap3-gpio";
- reg = <0x49052000 0x200>;
- interrupts = <31>;
- ti,hwmods = "gpio3";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@49054000 {
- compatible = "ti,omap3-gpio";
- reg = <0x49054000 0x200>;
- interrupts = <32>;
- ti,hwmods = "gpio4";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio5: gpio@49056000 {
- compatible = "ti,omap3-gpio";
- reg = <0x49056000 0x200>;
- interrupts = <33>;
- ti,hwmods = "gpio5";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio6: gpio@49058000 {
- compatible = "ti,omap3-gpio";
- reg = <0x49058000 0x200>;
- interrupts = <34>;
- ti,hwmods = "gpio6";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- uart1: serial@4806a000 {
- compatible = "ti,omap3-uart";
- reg = <0x4806a000 0x2000>;
- reg-shift = <2>;
- interrupts-extended = <&intc 72>;
- dmas = <&sdma 49 &sdma 50>;
- dma-names = "tx", "rx";
- ti,hwmods = "uart1";
- clock-frequency = <48000000>;
- };
-
- uart2: serial@4806c000 {
- compatible = "ti,omap3-uart";
- reg = <0x4806c000 0x400>;
- interrupts-extended = <&intc 73>;
- dmas = <&sdma 51 &sdma 52>;
- dma-names = "tx", "rx";
- ti,hwmods = "uart2";
- clock-frequency = <48000000>;
- };
-
- uart3: serial@49020000 {
- compatible = "ti,omap3-uart";
- reg = <0x49020000 0x400>;
- interrupts-extended = <&intc 74>;
- dmas = <&sdma 53 &sdma 54>;
- dma-names = "tx", "rx";
- ti,hwmods = "uart3";
- clock-frequency = <48000000>;
- };
-
- i2c1: i2c@48070000 {
- compatible = "ti,omap3-i2c";
- reg = <0x48070000 0x80>;
- interrupts = <56>;
- dmas = <&sdma 27 &sdma 28>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "i2c1";
- };
-
- i2c2: i2c@48072000 {
- compatible = "ti,omap3-i2c";
- reg = <0x48072000 0x80>;
- interrupts = <57>;
- dmas = <&sdma 29 &sdma 30>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "i2c2";
- };
-
- i2c3: i2c@48060000 {
- compatible = "ti,omap3-i2c";
- reg = <0x48060000 0x80>;
- interrupts = <61>;
- dmas = <&sdma 25 &sdma 26>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "i2c3";
- };
-
- mailbox: mailbox@48094000 {
- compatible = "ti,omap3-mailbox";
- ti,hwmods = "mailbox";
- reg = <0x48094000 0x200>;
- interrupts = <26>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <2>;
- ti,mbox-num-fifos = <2>;
- mbox_dsp: dsp {
- ti,mbox-tx = <0 0 0>;
- ti,mbox-rx = <1 0 0>;
- };
- };
-
- mcspi1: spi@48098000 {
- compatible = "ti,omap2-mcspi";
- reg = <0x48098000 0x100>;
- interrupts = <65>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "mcspi1";
- ti,spi-num-cs = <4>;
- dmas = <&sdma 35>,
- <&sdma 36>,
- <&sdma 37>,
- <&sdma 38>,
- <&sdma 39>,
- <&sdma 40>,
- <&sdma 41>,
- <&sdma 42>;
- dma-names = "tx0", "rx0", "tx1", "rx1",
- "tx2", "rx2", "tx3", "rx3";
- };
-
- mcspi2: spi@4809a000 {
- compatible = "ti,omap2-mcspi";
- reg = <0x4809a000 0x100>;
- interrupts = <66>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "mcspi2";
- ti,spi-num-cs = <2>;
- dmas = <&sdma 43>,
- <&sdma 44>,
- <&sdma 45>,
- <&sdma 46>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
- };
-
- mcspi3: spi@480b8000 {
- compatible = "ti,omap2-mcspi";
- reg = <0x480b8000 0x100>;
- interrupts = <91>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "mcspi3";
- ti,spi-num-cs = <2>;
- dmas = <&sdma 15>,
- <&sdma 16>,
- <&sdma 23>,
- <&sdma 24>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
- };
-
- mcspi4: spi@480ba000 {
- compatible = "ti,omap2-mcspi";
- reg = <0x480ba000 0x100>;
- interrupts = <48>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "mcspi4";
- ti,spi-num-cs = <1>;
- dmas = <&sdma 70>, <&sdma 71>;
- dma-names = "tx0", "rx0";
- };
-
- hdqw1w: 1w@480b2000 {
- compatible = "ti,omap3-1w";
- reg = <0x480b2000 0x1000>;
- interrupts = <58>;
- ti,hwmods = "hdq1w";
- };
-
- mmc1: mmc@4809c000 {
- compatible = "ti,omap3-hsmmc";
- reg = <0x4809c000 0x200>;
- interrupts = <83>;
- ti,hwmods = "mmc1";
- ti,dual-volt;
- dmas = <&sdma 61>, <&sdma 62>;
- dma-names = "tx", "rx";
- pbias-supply = <&pbias_mmc_reg>;
- };
-
- mmc2: mmc@480b4000 {
- compatible = "ti,omap3-hsmmc";
- reg = <0x480b4000 0x200>;
- interrupts = <86>;
- ti,hwmods = "mmc2";
- dmas = <&sdma 47>, <&sdma 48>;
- dma-names = "tx", "rx";
- };
-
- mmc3: mmc@480ad000 {
- compatible = "ti,omap3-hsmmc";
- reg = <0x480ad000 0x200>;
- interrupts = <94>;
- ti,hwmods = "mmc3";
- dmas = <&sdma 77>, <&sdma 78>;
- dma-names = "tx", "rx";
- };
-
- mmu_isp: mmu@480bd400 {
- #iommu-cells = <0>;
- compatible = "ti,omap2-iommu";
- reg = <0x480bd400 0x80>;
- interrupts = <24>;
- ti,hwmods = "mmu_isp";
- ti,#tlb-entries = <8>;
- };
-
- mmu_iva: mmu@5d000000 {
- #iommu-cells = <0>;
- compatible = "ti,omap2-iommu";
- reg = <0x5d000000 0x80>;
- interrupts = <28>;
- ti,hwmods = "mmu_iva";
- status = "disabled";
- };
-
- wdt2: wdt@48314000 {
- compatible = "ti,omap3-wdt";
- reg = <0x48314000 0x80>;
- ti,hwmods = "wd_timer2";
- };
-
- mcbsp1: mcbsp@48074000 {
- compatible = "ti,omap3-mcbsp";
- reg = <0x48074000 0xff>;
- reg-names = "mpu";
- interrupts = <16>, /* OCP compliant interrupt */
- <59>, /* TX interrupt */
- <60>; /* RX interrupt */
- interrupt-names = "common", "tx", "rx";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp1";
- dmas = <&sdma 31>,
- <&sdma 32>;
- dma-names = "tx", "rx";
- clocks = <&mcbsp1_fck>;
- clock-names = "fck";
- status = "disabled";
- };
-
- mcbsp2: mcbsp@49022000 {
- compatible = "ti,omap3-mcbsp";
- reg = <0x49022000 0xff>,
- <0x49028000 0xff>;
- reg-names = "mpu", "sidetone";
- interrupts = <17>, /* OCP compliant interrupt */
- <62>, /* TX interrupt */
- <63>, /* RX interrupt */
- <4>; /* Sidetone */
- interrupt-names = "common", "tx", "rx", "sidetone";
- ti,buffer-size = <1280>;
- ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
- dmas = <&sdma 33>,
- <&sdma 34>;
- dma-names = "tx", "rx";
- clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
- clock-names = "fck", "ick";
- status = "disabled";
- };
-
- mcbsp3: mcbsp@49024000 {
- compatible = "ti,omap3-mcbsp";
- reg = <0x49024000 0xff>,
- <0x4902a000 0xff>;
- reg-names = "mpu", "sidetone";
- interrupts = <22>, /* OCP compliant interrupt */
- <89>, /* TX interrupt */
- <90>, /* RX interrupt */
- <5>; /* Sidetone */
- interrupt-names = "common", "tx", "rx", "sidetone";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
- dmas = <&sdma 17>,
- <&sdma 18>;
- dma-names = "tx", "rx";
- clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
- clock-names = "fck", "ick";
- status = "disabled";
- };
-
- mcbsp4: mcbsp@49026000 {
- compatible = "ti,omap3-mcbsp";
- reg = <0x49026000 0xff>;
- reg-names = "mpu";
- interrupts = <23>, /* OCP compliant interrupt */
- <54>, /* TX interrupt */
- <55>; /* RX interrupt */
- interrupt-names = "common", "tx", "rx";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp4";
- dmas = <&sdma 19>,
- <&sdma 20>;
- dma-names = "tx", "rx";
- clocks = <&mcbsp4_fck>;
- clock-names = "fck";
- status = "disabled";
- };
-
- mcbsp5: mcbsp@48096000 {
- compatible = "ti,omap3-mcbsp";
- reg = <0x48096000 0xff>;
- reg-names = "mpu";
- interrupts = <27>, /* OCP compliant interrupt */
- <81>, /* TX interrupt */
- <82>; /* RX interrupt */
- interrupt-names = "common", "tx", "rx";
- ti,buffer-size = <128>;
- ti,hwmods = "mcbsp5";
- dmas = <&sdma 21>,
- <&sdma 22>;
- dma-names = "tx", "rx";
- clocks = <&mcbsp5_fck>;
- clock-names = "fck";
- status = "disabled";
- };
-
- sham: sham@480c3000 {
- compatible = "ti,omap3-sham";
- ti,hwmods = "sham";
- reg = <0x480c3000 0x64>;
- interrupts = <49>;
- dmas = <&sdma 69>;
- dma-names = "rx";
- };
-
- smartreflex_core: smartreflex@480cb000 {
- compatible = "ti,omap3-smartreflex-core";
- ti,hwmods = "smartreflex_core";
- reg = <0x480cb000 0x400>;
- interrupts = <19>;
- };
-
- smartreflex_mpu_iva: smartreflex@480c9000 {
- compatible = "ti,omap3-smartreflex-iva";
- ti,hwmods = "smartreflex_mpu_iva";
- reg = <0x480c9000 0x400>;
- interrupts = <18>;
- };
-
- timer1: timer@48318000 {
- compatible = "ti,omap3430-timer";
- reg = <0x48318000 0x400>;
- interrupts = <37>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
- };
-
- timer2: timer@49032000 {
- compatible = "ti,omap3430-timer";
- reg = <0x49032000 0x400>;
- interrupts = <38>;
- ti,hwmods = "timer2";
- };
-
- timer3: timer@49034000 {
- compatible = "ti,omap3430-timer";
- reg = <0x49034000 0x400>;
- interrupts = <39>;
- ti,hwmods = "timer3";
- };
-
- timer4: timer@49036000 {
- compatible = "ti,omap3430-timer";
- reg = <0x49036000 0x400>;
- interrupts = <40>;
- ti,hwmods = "timer4";
- };
-
- timer5: timer@49038000 {
- compatible = "ti,omap3430-timer";
- reg = <0x49038000 0x400>;
- interrupts = <41>;
- ti,hwmods = "timer5";
- ti,timer-dsp;
- };
-
- timer6: timer@4903a000 {
- compatible = "ti,omap3430-timer";
- reg = <0x4903a000 0x400>;
- interrupts = <42>;
- ti,hwmods = "timer6";
- ti,timer-dsp;
- };
-
- timer7: timer@4903c000 {
- compatible = "ti,omap3430-timer";
- reg = <0x4903c000 0x400>;
- interrupts = <43>;
- ti,hwmods = "timer7";
- ti,timer-dsp;
- };
-
- timer8: timer@4903e000 {
- compatible = "ti,omap3430-timer";
- reg = <0x4903e000 0x400>;
- interrupts = <44>;
- ti,hwmods = "timer8";
- ti,timer-pwm;
- ti,timer-dsp;
- };
-
- timer9: timer@49040000 {
- compatible = "ti,omap3430-timer";
- reg = <0x49040000 0x400>;
- interrupts = <45>;
- ti,hwmods = "timer9";
- ti,timer-pwm;
- };
-
- timer10: timer@48086000 {
- compatible = "ti,omap3430-timer";
- reg = <0x48086000 0x400>;
- interrupts = <46>;
- ti,hwmods = "timer10";
- ti,timer-pwm;
- };
-
- timer11: timer@48088000 {
- compatible = "ti,omap3430-timer";
- reg = <0x48088000 0x400>;
- interrupts = <47>;
- ti,hwmods = "timer11";
- ti,timer-pwm;
- };
-
- timer12: timer@48304000 {
- compatible = "ti,omap3430-timer";
- reg = <0x48304000 0x400>;
- interrupts = <95>;
- ti,hwmods = "timer12";
- ti,timer-alwon;
- ti,timer-secure;
- };
-
- usbhstll: usbhstll@48062000 {
- compatible = "ti,usbhs-tll";
- reg = <0x48062000 0x1000>;
- interrupts = <78>;
- ti,hwmods = "usb_tll_hs";
- };
-
- usbhshost: usbhshost@48064000 {
- compatible = "ti,usbhs-host";
- reg = <0x48064000 0x400>;
- ti,hwmods = "usb_host_hs";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- usbhsohci: ohci@48064400 {
- compatible = "ti,ohci-omap3";
- reg = <0x48064400 0x400>;
- interrupt-parent = <&intc>;
- interrupts = <76>;
- };
-
- usbhsehci: ehci@48064800 {
- compatible = "ti,ehci-omap";
- reg = <0x48064800 0x400>;
- interrupt-parent = <&intc>;
- interrupts = <77>;
- };
- };
-
- gpmc: gpmc@6e000000 {
- compatible = "ti,omap3430-gpmc";
- ti,hwmods = "gpmc";
- reg = <0x6e000000 0x02d0>;
- interrupts = <20>;
- dmas = <&sdma 4>;
- dma-names = "rxtx";
- gpmc,num-cs = <8>;
- gpmc,num-waitpins = <4>;
- #address-cells = <2>;
- #size-cells = <1>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- usb_otg_hs: usb_otg_hs@480ab000 {
- compatible = "ti,omap3-musb";
- reg = <0x480ab000 0x1000>;
- interrupts = <92>, <93>;
- interrupt-names = "mc", "dma";
- ti,hwmods = "usb_otg_hs";
- multipoint = <1>;
- num-eps = <16>;
- ram-bits = <12>;
- };
-
- dss: dss@48050000 {
- compatible = "ti,omap3-dss";
- reg = <0x48050000 0x200>;
- status = "disabled";
- ti,hwmods = "dss_core";
- clocks = <&dss1_alwon_fck>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- dispc@48050400 {
- compatible = "ti,omap3-dispc";
- reg = <0x48050400 0x400>;
- interrupts = <25>;
- ti,hwmods = "dss_dispc";
- clocks = <&dss1_alwon_fck>;
- clock-names = "fck";
- };
-
- dsi: encoder@4804fc00 {
- compatible = "ti,omap3-dsi";
- reg = <0x4804fc00 0x200>,
- <0x4804fe00 0x40>,
- <0x4804ff00 0x20>;
- reg-names = "proto", "phy", "pll";
- interrupts = <25>;
- status = "disabled";
- ti,hwmods = "dss_dsi1";
- clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
- clock-names = "fck", "sys_clk";
- };
-
- rfbi: encoder@48050800 {
- compatible = "ti,omap3-rfbi";
- reg = <0x48050800 0x100>;
- status = "disabled";
- ti,hwmods = "dss_rfbi";
- clocks = <&dss1_alwon_fck>, <&dss_ick>;
- clock-names = "fck", "ick";
- };
-
- venc: encoder@48050c00 {
- compatible = "ti,omap3-venc";
- reg = <0x48050c00 0x100>;
- status = "disabled";
- ti,hwmods = "dss_venc";
- clocks = <&dss_tv_fck>;
- clock-names = "fck";
- };
- };
-
- ssi: ssi-controller@48058000 {
- compatible = "ti,omap3-ssi";
- ti,hwmods = "ssi";
-
- status = "disabled";
-
- reg = <0x48058000 0x1000>,
- <0x48059000 0x1000>;
- reg-names = "sys",
- "gdd";
-
- interrupts = <71>;
- interrupt-names = "gdd_mpu";
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- ssi_port1: ssi-port@4805a000 {
- compatible = "ti,omap3-ssi-port";
-
- reg = <0x4805a000 0x800>,
- <0x4805a800 0x800>;
- reg-names = "tx",
- "rx";
-
- interrupt-parent = <&intc>;
- interrupts = <67>,
- <68>;
- };
-
- ssi_port2: ssi-port@4805b000 {
- compatible = "ti,omap3-ssi-port";
-
- reg = <0x4805b000 0x800>,
- <0x4805b800 0x800>;
- reg-names = "tx",
- "rx";
-
- interrupt-parent = <&intc>;
- interrupts = <69>,
- <70>;
- };
- };
- };
+ compatible = "ti,omap3430", "ti,omap3";
+ interrupt-parent = <&intc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a8";
+ device_type = "cpu";
+ reg = <0x0>;
+
+ clocks = <&dpll1_ck>;
+ clock-names = "cpu";
+
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+ };
+ };
+
+ pmu@54000000 {
+ compatible = "arm,cortex-a8-pmu";
+ reg = <0x54000000 0x800000>;
+ interrupts = <3>;
+ ti,hwmods = "debugss";
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is used for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap3-mpu";
+ ti,hwmods = "mpu";
+ };
+
+ iva: iva {
+ compatible = "ti,iva2.2";
+ ti,hwmods = "iva";
+
+ dsp {
+ compatible = "ti,omap3-c64";
+ };
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the OMAP3 interconnect.
+ * The real OMAP interconnect network is quite complex.
+ * Since it will not bring real advantage to represent that in DT for
+ * the moment, just use a fake OCP bus entry to represent the whole bus
+ * hierarchy.
+ */
+ ocp@68000000 {
+ compatible = "ti,omap3-l3-smx", "simple-bus";
+ reg = <0x68000000 0x10000>;
+ interrupts = <9 10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main";
+
+ l4_core: l4@48000000 {
+ compatible = "ti,omap3-l4-core", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x48000000 0x1000000>;
+
+ scm: scm@2000 {
+ compatible = "ti,omap3-scm", "simple-bus";
+ reg = <0x2000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2000 0x2000>;
+
+ omap3_pmx_core: pinmux@30 {
+ compatible = "ti,omap3-padconf",
+ "pinctrl-single";
+ reg = <0x30 0x238>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0xff1f>;
+ };
+
+ scm_conf: scm_conf@270 {
+ compatible = "syscon", "simple-bus";
+ reg = <0x270 0x330>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x270 0x330>;
+
+ pbias_regulator: pbias_regulator@2b0 {
+ compatible = "ti,pbias-omap3", "ti,pbias-omap";
+ reg = <0x2b0 0x4>;
+ syscon = <&scm_conf>;
+ pbias_mmc_reg: pbias_mmc_omap2430 {
+ regulator-name = "pbias_mmc_omap2430";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ };
+
+ scm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ scm_clockdomains: clockdomains {
+ };
+
+ omap3_pmx_wkup: pinmux@a00 {
+ compatible = "ti,omap3-padconf",
+ "pinctrl-single";
+ reg = <0xa00 0x5c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0xff1f>;
+ };
+ };
+ };
+
+ aes: aes@480c5000 {
+ compatible = "ti,omap3-aes";
+ ti,hwmods = "aes";
+ reg = <0x480c5000 0x50>;
+ interrupts = <0>;
+ dmas = <&sdma 65 &sdma 66>;
+ dma-names = "tx", "rx";
+ };
+
+ prm: prm@48306000 {
+ compatible = "ti,omap3-prm";
+ reg = <0x48306000 0x4000>;
+ interrupts = <11>;
+
+ prm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prm_clockdomains: clockdomains {
+ };
+ };
+
+ cm: cm@48004000 {
+ compatible = "ti,omap3-cm";
+ reg = <0x48004000 0x4000>;
+
+ cm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm_clockdomains: clockdomains {
+ };
+ };
+
+ counter32k: counter@48320000 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x48320000 0x20>;
+ ti,hwmods = "counter_32k";
+ };
+
+ intc: interrupt-controller@48200000 {
+ compatible = "ti,omap3-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x48200000 0x1000>;
+ };
+
+ sdma: dma-controller@48056000 {
+ compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
+ reg = <0x48056000 0x1000>;
+ interrupts = <12>,
+ <13>,
+ <14>,
+ <15>;
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ dma-requests = <96>;
+ };
+
+ gpio1: gpio@48310000 {
+ compatible = "ti,omap3-gpio";
+ reg = <0x48310000 0x200>;
+ interrupts = <29>;
+ ti,hwmods = "gpio1";
+ ti,gpio-always-on;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@49050000 {
+ compatible = "ti,omap3-gpio";
+ reg = <0x49050000 0x200>;
+ interrupts = <30>;
+ ti,hwmods = "gpio2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@49052000 {
+ compatible = "ti,omap3-gpio";
+ reg = <0x49052000 0x200>;
+ interrupts = <31>;
+ ti,hwmods = "gpio3";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@49054000 {
+ compatible = "ti,omap3-gpio";
+ reg = <0x49054000 0x200>;
+ interrupts = <32>;
+ ti,hwmods = "gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@49056000 {
+ compatible = "ti,omap3-gpio";
+ reg = <0x49056000 0x200>;
+ interrupts = <33>;
+ ti,hwmods = "gpio5";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio@49058000 {
+ compatible = "ti,omap3-gpio";
+ reg = <0x49058000 0x200>;
+ interrupts = <34>;
+ ti,hwmods = "gpio6";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uart1: serial@4806a000 {
+ compatible = "ti,omap3-uart";
+ reg = <0x4806a000 0x2000>;
+ reg-shift = <2>;
+ interrupts-extended = <&intc 72>;
+ dmas = <&sdma 49 &sdma 50>;
+ dma-names = "tx", "rx";
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ };
+
+ uart2: serial@4806c000 {
+ compatible = "ti,omap3-uart";
+ reg = <0x4806c000 0x400>;
+ reg-shift = <2>;
+ interrupts-extended = <&intc 73>;
+ dmas = <&sdma 51 &sdma 52>;
+ dma-names = "tx", "rx";
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ };
+
+ uart3: serial@49020000 {
+ compatible = "ti,omap3-uart";
+ reg = <0x49020000 0x400>;
+ reg-shift = <2>;
+ interrupts-extended = <&intc 74>;
+ dmas = <&sdma 53 &sdma 54>;
+ dma-names = "tx", "rx";
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ };
+
+ i2c1: i2c@48070000 {
+ compatible = "ti,omap3-i2c";
+ reg = <0x48070000 0x80>;
+ interrupts = <56>;
+ dmas = <&sdma 27 &sdma 28>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c1";
+ };
+
+ i2c2: i2c@48072000 {
+ compatible = "ti,omap3-i2c";
+ reg = <0x48072000 0x80>;
+ interrupts = <57>;
+ dmas = <&sdma 29 &sdma 30>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c2";
+ };
+
+ i2c3: i2c@48060000 {
+ compatible = "ti,omap3-i2c";
+ reg = <0x48060000 0x80>;
+ interrupts = <61>;
+ dmas = <&sdma 25 &sdma 26>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c3";
+ };
+
+ mailbox: mailbox@48094000 {
+ compatible = "ti,omap3-mailbox";
+ ti,hwmods = "mailbox";
+ reg = <0x48094000 0x200>;
+ interrupts = <26>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <2>;
+ ti,mbox-num-fifos = <2>;
+ mbox_dsp: dsp {
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <1 0 0>;
+ };
+ };
+
+ mcspi1: spi@48098000 {
+ compatible = "ti,omap2-mcspi";
+ reg = <0x48098000 0x100>;
+ interrupts = <65>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi1";
+ ti,spi-num-cs = <4>;
+ dmas = <&sdma 35>,
+ <&sdma 36>,
+ <&sdma 37>,
+ <&sdma 38>,
+ <&sdma 39>,
+ <&sdma 40>,
+ <&sdma 41>,
+ <&sdma 42>;
+ dma-names = "tx0", "rx0", "tx1", "rx1",
+ "tx2", "rx2", "tx3", "rx3";
+ };
+
+ mcspi2: spi@4809a000 {
+ compatible = "ti,omap2-mcspi";
+ reg = <0x4809a000 0x100>;
+ interrupts = <66>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi2";
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 43>,
+ <&sdma 44>,
+ <&sdma 45>,
+ <&sdma 46>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ };
+
+ mcspi3: spi@480b8000 {
+ compatible = "ti,omap2-mcspi";
+ reg = <0x480b8000 0x100>;
+ interrupts = <91>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi3";
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 15>,
+ <&sdma 16>,
+ <&sdma 23>,
+ <&sdma 24>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ };
+
+ mcspi4: spi@480ba000 {
+ compatible = "ti,omap2-mcspi";
+ reg = <0x480ba000 0x100>;
+ interrupts = <48>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi4";
+ ti,spi-num-cs = <1>;
+ dmas = <&sdma 70>, <&sdma 71>;
+ dma-names = "tx0", "rx0";
+ };
+
+ hdqw1w: 1w@480b2000 {
+ compatible = "ti,omap3-1w";
+ reg = <0x480b2000 0x1000>;
+ interrupts = <58>;
+ ti,hwmods = "hdq1w";
+ };
+
+ mmc1: mmc@4809c000 {
+ compatible = "ti,omap3-hsmmc";
+ reg = <0x4809c000 0x200>;
+ interrupts = <83>;
+ ti,hwmods = "mmc1";
+ ti,dual-volt;
+ dmas = <&sdma 61>, <&sdma 62>;
+ dma-names = "tx", "rx";
+ pbias-supply = <&pbias_mmc_reg>;
+ };
+
+ mmc2: mmc@480b4000 {
+ compatible = "ti,omap3-hsmmc";
+ reg = <0x480b4000 0x200>;
+ interrupts = <86>;
+ ti,hwmods = "mmc2";
+ dmas = <&sdma 47>, <&sdma 48>;
+ dma-names = "tx", "rx";
+ };
+
+ mmc3: mmc@480ad000 {
+ compatible = "ti,omap3-hsmmc";
+ reg = <0x480ad000 0x200>;
+ interrupts = <94>;
+ ti,hwmods = "mmc3";
+ dmas = <&sdma 77>, <&sdma 78>;
+ dma-names = "tx", "rx";
+ };
+
+ mmu_isp: mmu@480bd400 {
+ #iommu-cells = <0>;
+ compatible = "ti,omap2-iommu";
+ reg = <0x480bd400 0x80>;
+ interrupts = <24>;
+ ti,hwmods = "mmu_isp";
+ ti,#tlb-entries = <8>;
+ };
+
+ mmu_iva: mmu@5d000000 {
+ #iommu-cells = <0>;
+ compatible = "ti,omap2-iommu";
+ reg = <0x5d000000 0x80>;
+ interrupts = <28>;
+ ti,hwmods = "mmu_iva";
+ status = "disabled";
+ };
+
+ wdt2: wdt@48314000 {
+ compatible = "ti,omap3-wdt";
+ reg = <0x48314000 0x80>;
+ ti,hwmods = "wd_timer2";
+ };
+
+ mcbsp1: mcbsp@48074000 {
+ compatible = "ti,omap3-mcbsp";
+ reg = <0x48074000 0xff>;
+ reg-names = "mpu";
+ interrupts = <16>, /* OCP compliant interrupt */
+ <59>, /* TX interrupt */
+ <60>; /* RX interrupt */
+ interrupt-names = "common", "tx", "rx";
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp1";
+ dmas = <&sdma 31>,
+ <&sdma 32>;
+ dma-names = "tx", "rx";
+ clocks = <&mcbsp1_fck>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ mcbsp2: mcbsp@49022000 {
+ compatible = "ti,omap3-mcbsp";
+ reg = <0x49022000 0xff>,
+ <0x49028000 0xff>;
+ reg-names = "mpu", "sidetone";
+ interrupts = <17>, /* OCP compliant interrupt */
+ <62>, /* TX interrupt */
+ <63>, /* RX interrupt */
+ <4>; /* Sidetone */
+ interrupt-names = "common", "tx", "rx", "sidetone";
+ ti,buffer-size = <1280>;
+ ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
+ dmas = <&sdma 33>,
+ <&sdma 34>;
+ dma-names = "tx", "rx";
+ clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
+ clock-names = "fck", "ick";
+ status = "disabled";
+ };
+
+ mcbsp3: mcbsp@49024000 {
+ compatible = "ti,omap3-mcbsp";
+ reg = <0x49024000 0xff>,
+ <0x4902a000 0xff>;
+ reg-names = "mpu", "sidetone";
+ interrupts = <22>, /* OCP compliant interrupt */
+ <89>, /* TX interrupt */
+ <90>, /* RX interrupt */
+ <5>; /* Sidetone */
+ interrupt-names = "common", "tx", "rx", "sidetone";
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
+ dmas = <&sdma 17>,
+ <&sdma 18>;
+ dma-names = "tx", "rx";
+ clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
+ clock-names = "fck", "ick";
+ status = "disabled";
+ };
+
+ mcbsp4: mcbsp@49026000 {
+ compatible = "ti,omap3-mcbsp";
+ reg = <0x49026000 0xff>;
+ reg-names = "mpu";
+ interrupts = <23>, /* OCP compliant interrupt */
+ <54>, /* TX interrupt */
+ <55>; /* RX interrupt */
+ interrupt-names = "common", "tx", "rx";
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp4";
+ dmas = <&sdma 19>,
+ <&sdma 20>;
+ dma-names = "tx", "rx";
+ clocks = <&mcbsp4_fck>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ mcbsp5: mcbsp@48096000 {
+ compatible = "ti,omap3-mcbsp";
+ reg = <0x48096000 0xff>;
+ reg-names = "mpu";
+ interrupts = <27>, /* OCP compliant interrupt */
+ <81>, /* TX interrupt */
+ <82>; /* RX interrupt */
+ interrupt-names = "common", "tx", "rx";
+ ti,buffer-size = <128>;
+ ti,hwmods = "mcbsp5";
+ dmas = <&sdma 21>,
+ <&sdma 22>;
+ dma-names = "tx", "rx";
+ clocks = <&mcbsp5_fck>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ sham: sham@480c3000 {
+ compatible = "ti,omap3-sham";
+ ti,hwmods = "sham";
+ reg = <0x480c3000 0x64>;
+ interrupts = <49>;
+ dmas = <&sdma 69>;
+ dma-names = "rx";
+ };
+
+ smartreflex_core: smartreflex@480cb000 {
+ compatible = "ti,omap3-smartreflex-core";
+ ti,hwmods = "smartreflex_core";
+ reg = <0x480cb000 0x400>;
+ interrupts = <19>;
+ };
+
+ smartreflex_mpu_iva: smartreflex@480c9000 {
+ compatible = "ti,omap3-smartreflex-iva";
+ ti,hwmods = "smartreflex_mpu_iva";
+ reg = <0x480c9000 0x400>;
+ interrupts = <18>;
+ };
+
+ timer1: timer@48318000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x48318000 0x400>;
+ interrupts = <37>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
+
+ timer2: timer@49032000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x49032000 0x400>;
+ interrupts = <38>;
+ ti,hwmods = "timer2";
+ };
+
+ timer3: timer@49034000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x49034000 0x400>;
+ interrupts = <39>;
+ ti,hwmods = "timer3";
+ };
+
+ timer4: timer@49036000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x49036000 0x400>;
+ interrupts = <40>;
+ ti,hwmods = "timer4";
+ };
+
+ timer5: timer@49038000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x49038000 0x400>;
+ interrupts = <41>;
+ ti,hwmods = "timer5";
+ ti,timer-dsp;
+ };
+
+ timer6: timer@4903a000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x4903a000 0x400>;
+ interrupts = <42>;
+ ti,hwmods = "timer6";
+ ti,timer-dsp;
+ };
+
+ timer7: timer@4903c000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x4903c000 0x400>;
+ interrupts = <43>;
+ ti,hwmods = "timer7";
+ ti,timer-dsp;
+ };
+
+ timer8: timer@4903e000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x4903e000 0x400>;
+ interrupts = <44>;
+ ti,hwmods = "timer8";
+ ti,timer-pwm;
+ ti,timer-dsp;
+ };
+
+ timer9: timer@49040000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x49040000 0x400>;
+ interrupts = <45>;
+ ti,hwmods = "timer9";
+ ti,timer-pwm;
+ };
+
+ timer10: timer@48086000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x48086000 0x400>;
+ interrupts = <46>;
+ ti,hwmods = "timer10";
+ ti,timer-pwm;
+ };
+
+ timer11: timer@48088000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x48088000 0x400>;
+ interrupts = <47>;
+ ti,hwmods = "timer11";
+ ti,timer-pwm;
+ };
+
+ timer12: timer@48304000 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x48304000 0x400>;
+ interrupts = <95>;
+ ti,hwmods = "timer12";
+ ti,timer-alwon;
+ ti,timer-secure;
+ };
+
+ usbhstll: usbhstll@48062000 {
+ compatible = "ti,usbhs-tll";
+ reg = <0x48062000 0x1000>;
+ interrupts = <78>;
+ ti,hwmods = "usb_tll_hs";
+ };
+
+ usbhshost: usbhshost@48064000 {
+ compatible = "ti,usbhs-host";
+ reg = <0x48064000 0x400>;
+ ti,hwmods = "usb_host_hs";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usbhsohci: ohci@48064400 {
+ compatible = "ti,ohci-omap3";
+ reg = <0x48064400 0x400>;
+ interrupt-parent = <&intc>;
+ interrupts = <76>;
+ };
+
+ usbhsehci: ehci@48064800 {
+ compatible = "ti,ehci-omap";
+ reg = <0x48064800 0x400>;
+ interrupt-parent = <&intc>;
+ interrupts = <77>;
+ };
+ };
+
+ gpmc: gpmc@6e000000 {
+ compatible = "ti,omap3430-gpmc";
+ ti,hwmods = "gpmc";
+ reg = <0x6e000000 0x02d0>;
+ interrupts = <20>;
+ dmas = <&sdma 4>;
+ dma-names = "rxtx";
+ gpmc,num-cs = <8>;
+ gpmc,num-waitpins = <4>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ usb_otg_hs: usb_otg_hs@480ab000 {
+ compatible = "ti,omap3-musb";
+ reg = <0x480ab000 0x1000>;
+ interrupts = <92>, <93>;
+ interrupt-names = "mc", "dma";
+ ti,hwmods = "usb_otg_hs";
+ multipoint = <1>;
+ num-eps = <16>;
+ ram-bits = <12>;
+ };
+
+ dss: dss@48050000 {
+ compatible = "ti,omap3-dss";
+ reg = <0x48050000 0x200>;
+ status = "disabled";
+ ti,hwmods = "dss_core";
+ clocks = <&dss1_alwon_fck>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dispc@48050400 {
+ compatible = "ti,omap3-dispc";
+ reg = <0x48050400 0x400>;
+ interrupts = <25>;
+ ti,hwmods = "dss_dispc";
+ clocks = <&dss1_alwon_fck>;
+ clock-names = "fck";
+ };
+
+ dsi: encoder@4804fc00 {
+ compatible = "ti,omap3-dsi";
+ reg = <0x4804fc00 0x200>,
+ <0x4804fe00 0x40>,
+ <0x4804ff00 0x20>;
+ reg-names = "proto", "phy", "pll";
+ interrupts = <25>;
+ status = "disabled";
+ ti,hwmods = "dss_dsi1";
+ clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
+ clock-names = "fck", "sys_clk";
+ };
+
+ rfbi: encoder@48050800 {
+ compatible = "ti,omap3-rfbi";
+ reg = <0x48050800 0x100>;
+ status = "disabled";
+ ti,hwmods = "dss_rfbi";
+ clocks = <&dss1_alwon_fck>, <&dss_ick>;
+ clock-names = "fck", "ick";
+ };
+
+ venc: encoder@48050c00 {
+ compatible = "ti,omap3-venc";
+ reg = <0x48050c00 0x100>;
+ status = "disabled";
+ ti,hwmods = "dss_venc";
+ clocks = <&dss_tv_fck>;
+ clock-names = "fck";
+ };
+ };
+
+ ssi: ssi-controller@48058000 {
+ compatible = "ti,omap3-ssi";
+ ti,hwmods = "ssi";
+
+ status = "disabled";
+
+ reg = <0x48058000 0x1000>,
+ <0x48059000 0x1000>;
+ reg-names = "sys",
+ "gdd";
+
+ interrupts = <71>;
+ interrupt-names = "gdd_mpu";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ssi_port1: ssi-port@4805a000 {
+ compatible = "ti,omap3-ssi-port";
+
+ reg = <0x4805a000 0x800>,
+ <0x4805a800 0x800>;
+ reg-names = "tx",
+ "rx";
+
+ interrupt-parent = <&intc>;
+ interrupts = <67>,
+ <68>;
+ };
+
+ ssi_port2: ssi-port@4805b000 {
+ compatible = "ti,omap3-ssi-port";
+
+ reg = <0x4805b000 0x800>,
+ <0x4805b800 0x800>;
+ reg-names = "tx",
+ "rx";
+
+ interrupt-parent = <&intc>;
+ interrupts = <69>,
+ <70>;
+ };
+ };
+ };
};
/include/ "omap3xxx-clocks.dtsi"
* published by the Free Software Foundation.
*/
&cm_clocks {
- security_l4_ick2: security_l4_ick2 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l4_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
+ security_l4_ick2: security_l4_ick2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
- aes1_ick: aes1_ick@a14 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&security_l4_ick2>;
- ti,bit-shift = <3>;
- reg = <0x0a14>;
- };
+ aes1_ick: aes1_ick@a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ ti,bit-shift = <3>;
+ reg = <0x0a14>;
+ };
- rng_ick: rng_ick@a14 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&security_l4_ick2>;
- reg = <0x0a14>;
- ti,bit-shift = <2>;
- };
+ rng_ick: rng_ick@a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x0a14>;
+ ti,bit-shift = <2>;
+ };
- sha11_ick: sha11_ick@a14 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&security_l4_ick2>;
- reg = <0x0a14>;
- ti,bit-shift = <1>;
- };
+ sha11_ick: sha11_ick@a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x0a14>;
+ ti,bit-shift = <1>;
+ };
- des1_ick: des1_ick@a14 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&security_l4_ick2>;
- reg = <0x0a14>;
- ti,bit-shift = <0>;
- };
+ des1_ick: des1_ick@a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l4_ick2>;
+ reg = <0x0a14>;
+ ti,bit-shift = <0>;
+ };
- cam_mclk: cam_mclk@f00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll4_m5x2_ck>;
- ti,bit-shift = <0>;
- reg = <0x0f00>;
- ti,set-rate-parent;
- };
+ cam_mclk: cam_mclk@f00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m5x2_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0f00>;
+ ti,set-rate-parent;
+ };
- cam_ick: cam_ick@f10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-no-wait-interface-clock";
- clocks = <&l4_ick>;
- reg = <0x0f10>;
- ti,bit-shift = <0>;
- };
+ cam_ick: cam_ick@f10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-no-wait-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x0f10>;
+ ti,bit-shift = <0>;
+ };
- csi2_96m_fck: csi2_96m_fck@f00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0f00>;
- ti,bit-shift = <1>;
- };
+ csi2_96m_fck: csi2_96m_fck@f00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0f00>;
+ ti,bit-shift = <1>;
+ };
- security_l3_ick: security_l3_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l3_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
+ security_l3_ick: security_l3_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
- pka_ick: pka_ick@a14 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&security_l3_ick>;
- reg = <0x0a14>;
- ti,bit-shift = <4>;
- };
+ pka_ick: pka_ick@a14 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&security_l3_ick>;
+ reg = <0x0a14>;
+ ti,bit-shift = <4>;
+ };
- icr_ick: icr_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <29>;
- };
+ icr_ick: icr_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <29>;
+ };
- des2_ick: des2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <26>;
- };
+ des2_ick: des2_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <26>;
+ };
- mspro_ick: mspro_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <23>;
- };
+ mspro_ick: mspro_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <23>;
+ };
- mailboxes_ick: mailboxes_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <7>;
- };
+ mailboxes_ick: mailboxes_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <7>;
+ };
- ssi_l4_ick: ssi_l4_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l4_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
+ ssi_l4_ick: ssi_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
- sr1_fck: sr1_fck@c00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&sys_ck>;
- reg = <0x0c00>;
- ti,bit-shift = <6>;
- };
+ sr1_fck: sr1_fck@c00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x0c00>;
+ ti,bit-shift = <6>;
+ };
- sr2_fck: sr2_fck@c00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&sys_ck>;
- reg = <0x0c00>;
- ti,bit-shift = <7>;
- };
+ sr2_fck: sr2_fck@c00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x0c00>;
+ ti,bit-shift = <7>;
+ };
- sr_l4_ick: sr_l4_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l4_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
+ sr_l4_ick: sr_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
- dpll2_fck: dpll2_fck@40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <19>;
- ti,max-div = <7>;
- reg = <0x0040>;
- ti,index-starts-at-one;
- };
+ dpll2_fck: dpll2_fck@40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <19>;
+ ti,max-div = <7>;
+ reg = <0x0040>;
+ ti,index-starts-at-one;
+ };
- dpll2_ck: dpll2_ck@4 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dpll-clock";
- clocks = <&sys_ck>, <&dpll2_fck>;
- reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
- ti,low-power-stop;
- ti,lock;
- ti,low-power-bypass;
- };
+ dpll2_ck: dpll2_ck@4 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&dpll2_fck>;
+ reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
+ ti,low-power-stop;
+ ti,lock;
+ ti,low-power-bypass;
+ };
- dpll2_m2_ck: dpll2_m2_ck@44 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll2_ck>;
- ti,max-div = <31>;
- reg = <0x0044>;
- ti,index-starts-at-one;
- };
+ dpll2_m2_ck: dpll2_m2_ck@44 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0044>;
+ ti,index-starts-at-one;
+ };
- iva2_ck: iva2_ck@0 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&dpll2_m2_ck>;
- reg = <0x0000>;
- ti,bit-shift = <0>;
- };
+ iva2_ck: iva2_ck@0 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&dpll2_m2_ck>;
+ reg = <0x0000>;
+ ti,bit-shift = <0>;
+ };
- modem_fck: modem_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&sys_ck>;
- reg = <0x0a00>;
- ti,bit-shift = <31>;
- };
+ modem_fck: modem_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&sys_ck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <31>;
+ };
- sad2d_ick: sad2d_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l3_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <3>;
- };
+ sad2d_ick: sad2d_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l3_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <3>;
+ };
- mad2d_ick: mad2d_ick@a18 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&l3_ick>;
- reg = <0x0a18>;
- ti,bit-shift = <3>;
- };
+ mad2d_ick: mad2d_ick@a18 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&l3_ick>;
+ reg = <0x0a18>;
+ ti,bit-shift = <3>;
+ };
- mspro_fck: mspro_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <23>;
- };
+ mspro_fck: mspro_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <23>;
+ };
};
&cm_clockdomains {
- cam_clkdm: cam_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&cam_ick>, <&csi2_96m_fck>;
- };
+ cam_clkdm: cam_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&cam_ick>, <&csi2_96m_fck>;
+ };
- iva2_clkdm: iva2_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&iva2_ck>;
- };
+ iva2_clkdm: iva2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&iva2_ck>;
+ };
- dpll2_clkdm: dpll2_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll2_ck>;
- };
+ dpll2_clkdm: dpll2_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll2_ck>;
+ };
- wkup_clkdm: wkup_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
- <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
- <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
- };
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+ <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+ <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
+ };
- d2d_clkdm: d2d_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
- };
+ d2d_clkdm: d2d_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
+ };
- core_l4_clkdm: core_l4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
- <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
- <&mspro_fck>;
- };
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+ <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+ <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+ <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+ <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+ <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+ <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+ <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+ <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
+ <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
+ <&mspro_fck>;
+ };
};
* published by the Free Software Foundation.
*/
&prm_clocks {
- corex2_d3_fck: corex2_d3_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&corex2_fck>;
- clock-mult = <1>;
- clock-div = <3>;
- };
-
- corex2_d5_fck: corex2_d5_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&corex2_fck>;
- clock-mult = <1>;
- clock-div = <5>;
- };
+ corex2_d3_fck: corex2_d3_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&corex2_fck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ corex2_d5_fck: corex2_d5_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&corex2_fck>;
+ clock-mult = <1>;
+ clock-div = <5>;
+ };
};
&cm_clocks {
- dpll5_ck: dpll5_ck@d04 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dpll-clock";
- clocks = <&sys_ck>, <&sys_ck>;
- reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
- ti,low-power-stop;
- ti,lock;
- };
-
- dpll5_m2_ck: dpll5_m2_ck@d50 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll5_ck>;
- ti,max-div = <31>;
- reg = <0x0d50>;
- ti,index-starts-at-one;
- };
-
- sgx_gate_fck: sgx_gate_fck@b00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <1>;
- reg = <0x0b00>;
- };
-
- core_d3_ck: core_d3_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <3>;
- };
-
- core_d4_ck: core_d4_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- core_d6_ck: core_d6_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <6>;
- };
-
- omap_192m_alwon_fck: omap_192m_alwon_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll4_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- core_d2_ck: core_d2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_ck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- sgx_mux_fck: sgx_mux_fck@b40 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
- reg = <0x0b40>;
- };
-
- sgx_fck: sgx_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
- };
-
- sgx_ick: sgx_ick@b10 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&l3_ick>;
- reg = <0x0b10>;
- ti,bit-shift = <0>;
- };
-
- cpefuse_fck: cpefuse_fck@a08 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_ck>;
- reg = <0x0a08>;
- ti,bit-shift = <0>;
- };
-
- ts_fck: ts_fck@a08 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&omap_32k_fck>;
- reg = <0x0a08>;
- ti,bit-shift = <1>;
- };
-
- usbtll_fck: usbtll_fck@a08 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&dpll5_m2_ck>;
- reg = <0x0a08>;
- ti,bit-shift = <2>;
- };
-
- usbtll_ick: usbtll_ick@a18 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a18>;
- ti,bit-shift = <2>;
- };
-
- mmchs3_ick: mmchs3_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <30>;
- };
-
- mmchs3_fck: mmchs3_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <30>;
- };
-
- dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 {
- #clock-cells = <0>;
- compatible = "ti,dss-gate-clock";
- clocks = <&dpll4_m4x2_ck>;
- ti,bit-shift = <0>;
- reg = <0x0e00>;
- ti,set-rate-parent;
- };
-
- dss_ick: dss_ick_3430es2@e10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dss-interface-clock";
- clocks = <&l4_ick>;
- reg = <0x0e10>;
- ti,bit-shift = <0>;
- };
-
- usbhost_120m_fck: usbhost_120m_fck@1400 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll5_m2_ck>;
- reg = <0x1400>;
- ti,bit-shift = <1>;
- };
-
- usbhost_48m_fck: usbhost_48m_fck@1400 {
- #clock-cells = <0>;
- compatible = "ti,dss-gate-clock";
- clocks = <&omap_48m_fck>;
- reg = <0x1400>;
- ti,bit-shift = <0>;
- };
-
- usbhost_ick: usbhost_ick@1410 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dss-interface-clock";
- clocks = <&l4_ick>;
- reg = <0x1410>;
- ti,bit-shift = <0>;
- };
+ dpll5_ck: dpll5_ck@d04 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
+ ti,low-power-stop;
+ ti,lock;
+ };
+
+ dpll5_m2_ck: dpll5_m2_ck@d50 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll5_ck>;
+ ti,max-div = <31>;
+ reg = <0x0d50>;
+ ti,index-starts-at-one;
+ };
+
+ sgx_gate_fck: sgx_gate_fck@b00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x0b00>;
+ };
+
+ core_d3_ck: core_d3_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ core_d4_ck: core_d4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ core_d6_ck: core_d6_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <6>;
+ };
+
+ omap_192m_alwon_fck: omap_192m_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ core_d2_ck: core_d2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ sgx_mux_fck: sgx_mux_fck@b40 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
+ reg = <0x0b40>;
+ };
+
+ sgx_fck: sgx_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
+ };
+
+ sgx_ick: sgx_ick@b10 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&l3_ick>;
+ reg = <0x0b10>;
+ ti,bit-shift = <0>;
+ };
+
+ cpefuse_fck: cpefuse_fck@a08 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x0a08>;
+ ti,bit-shift = <0>;
+ };
+
+ ts_fck: ts_fck@a08 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&omap_32k_fck>;
+ reg = <0x0a08>;
+ ti,bit-shift = <1>;
+ };
+
+ usbtll_fck: usbtll_fck@a08 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&dpll5_m2_ck>;
+ reg = <0x0a08>;
+ ti,bit-shift = <2>;
+ };
+
+ usbtll_ick: usbtll_ick@a18 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a18>;
+ ti,bit-shift = <2>;
+ };
+
+ mmchs3_ick: mmchs3_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <30>;
+ };
+
+ mmchs3_fck: mmchs3_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <30>;
+ };
+
+ dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 {
+ #clock-cells = <0>;
+ compatible = "ti,dss-gate-clock";
+ clocks = <&dpll4_m4x2_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0e00>;
+ ti,set-rate-parent;
+ };
+
+ dss_ick: dss_ick_3430es2@e10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dss-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x0e10>;
+ ti,bit-shift = <0>;
+ };
+
+ usbhost_120m_fck: usbhost_120m_fck@1400 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll5_m2_ck>;
+ reg = <0x1400>;
+ ti,bit-shift = <1>;
+ };
+
+ usbhost_48m_fck: usbhost_48m_fck@1400 {
+ #clock-cells = <0>;
+ compatible = "ti,dss-gate-clock";
+ clocks = <&omap_48m_fck>;
+ reg = <0x1400>;
+ ti,bit-shift = <0>;
+ };
+
+ usbhost_ick: usbhost_ick@1410 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dss-interface-clock";
+ clocks = <&l4_ick>;
+ reg = <0x1410>;
+ ti,bit-shift = <0>;
+ };
};
&cm_clockdomains {
- dpll5_clkdm: dpll5_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll5_ck>;
- };
-
- sgx_clkdm: sgx_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&sgx_ick>;
- };
-
- dss_clkdm: dss_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
- <&dss1_alwon_fck>, <&dss_ick>;
- };
-
- core_l4_clkdm: core_l4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
- <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
- <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
- };
-
- usbhost_clkdm: usbhost_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
- <&usbhost_ick>;
- };
+ dpll5_clkdm: dpll5_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll5_ck>;
+ };
+
+ sgx_clkdm: sgx_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sgx_ick>;
+ };
+
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
+ <&dss1_alwon_fck>, <&dss_ick>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+ <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+ <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+ <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+ <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+ <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+ <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+ <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+ <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+ <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+ <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
+ };
+
+ usbhost_clkdm: usbhost_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
+ <&usbhost_ick>;
+ };
};
* published by the Free Software Foundation.
*/
&cm_clocks {
- dpll4_ck: dpll4_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dpll-per-j-type-clock";
- clocks = <&sys_ck>, <&sys_ck>;
- reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
- };
+ dpll4_ck: dpll4_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-per-j-type-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
+ };
- dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,hsdiv-gate-clock";
- clocks = <&dpll4_m5x2_mul_ck>;
- ti,bit-shift = <0x1e>;
- reg = <0x0d00>;
- ti,set-rate-parent;
- ti,set-bit-to-disable;
- };
+ dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m5x2_mul_ck>;
+ ti,bit-shift = <0x1e>;
+ reg = <0x0d00>;
+ ti,set-rate-parent;
+ ti,set-bit-to-disable;
+ };
- dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,hsdiv-gate-clock";
- clocks = <&dpll4_m2x2_mul_ck>;
- ti,bit-shift = <0x1b>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
+ dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m2x2_mul_ck>;
+ ti,bit-shift = <0x1b>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
- dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,hsdiv-gate-clock";
- clocks = <&dpll3_m3x2_mul_ck>;
- ti,bit-shift = <0xc>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
+ dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll3_m3x2_mul_ck>;
+ ti,bit-shift = <0xc>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
- dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,hsdiv-gate-clock";
- clocks = <&dpll4_m3x2_mul_ck>;
- ti,bit-shift = <0x1c>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
+ dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m3x2_mul_ck>;
+ ti,bit-shift = <0x1c>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
- dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,hsdiv-gate-clock";
- clocks = <&dpll4_m6x2_mul_ck>;
- ti,bit-shift = <0x1f>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
+ dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,hsdiv-gate-clock";
+ clocks = <&dpll4_m6x2_mul_ck>;
+ ti,bit-shift = <0x1f>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
- uart4_fck: uart4_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&per_48m_fck>;
- reg = <0x1000>;
- ti,bit-shift = <18>;
- };
+ uart4_fck: uart4_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&per_48m_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <18>;
+ };
};
&dpll4_m2x2_mul_ck {
- clock-mult = <1>;
+ clock-mult = <1>;
};
&dpll4_m3x2_mul_ck {
- clock-mult = <1>;
+ clock-mult = <1>;
};
&dpll4_m4x2_mul_ck {
- ti,clock-mult = <1>;
+ ti,clock-mult = <1>;
};
&dpll4_m5x2_mul_ck {
- ti,clock-mult = <1>;
+ ti,clock-mult = <1>;
};
&dpll4_m6x2_mul_ck {
- clock-mult = <1>;
+ clock-mult = <1>;
};
&cm_clockdomains {
- dpll4_clkdm: dpll4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll4_ck>;
- };
+ dpll4_clkdm: dpll4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll4_ck>;
+ };
- per_clkdm: per_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
- <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
- <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
- <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
- <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
- <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
- <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
- <&mcbsp4_ick>, <&uart4_fck>;
- };
+ per_clkdm: per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
+ <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
+ <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
+ <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
+ <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
+ <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
+ <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
+ <&mcbsp4_ick>, <&uart4_fck>;
+ };
};
* published by the Free Software Foundation.
*/
&cm_clocks {
- ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&corex2_fck>;
- ti,bit-shift = <0>;
- reg = <0x0a00>;
- };
-
- ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {
- #clock-cells = <0>;
- compatible = "ti,composite-divider-clock";
- clocks = <&corex2_fck>;
- ti,bit-shift = <8>;
- reg = <0x0a40>;
- ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
- };
-
- ssi_ssr_fck: ssi_ssr_fck_3430es2 {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
- };
-
- ssi_sst_fck: ssi_sst_fck_3430es2 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&ssi_ssr_fck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-hsotgusb-interface-clock";
- clocks = <&core_l3_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <4>;
- };
-
- ssi_l4_ick: ssi_l4_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l4_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- ssi_ick: ssi_ick_3430es2@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-ssi-interface-clock";
- clocks = <&ssi_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <0>;
- };
-
- usim_gate_fck: usim_gate_fck@c00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&omap_96m_fck>;
- ti,bit-shift = <9>;
- reg = <0x0c00>;
- };
-
- sys_d2_ck: sys_d2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&sys_ck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- omap_96m_d2_fck: omap_96m_d2_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_96m_fck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- omap_96m_d4_fck: omap_96m_d4_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_96m_fck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- omap_96m_d8_fck: omap_96m_d8_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_96m_fck>;
- clock-mult = <1>;
- clock-div = <8>;
- };
-
- omap_96m_d10_fck: omap_96m_d10_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_96m_fck>;
- clock-mult = <1>;
- clock-div = <10>;
- };
-
- dpll5_m2_d4_ck: dpll5_m2_d4_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll5_m2_ck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- dpll5_m2_d8_ck: dpll5_m2_d8_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll5_m2_ck>;
- clock-mult = <1>;
- clock-div = <8>;
- };
-
- dpll5_m2_d16_ck: dpll5_m2_d16_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll5_m2_ck>;
- clock-mult = <1>;
- clock-div = <16>;
- };
-
- dpll5_m2_d20_ck: dpll5_m2_d20_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll5_m2_ck>;
- clock-mult = <1>;
- clock-div = <20>;
- };
-
- usim_mux_fck: usim_mux_fck@c40 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
- ti,bit-shift = <3>;
- reg = <0x0c40>;
- ti,index-starts-at-one;
- };
-
- usim_fck: usim_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&usim_gate_fck>, <&usim_mux_fck>;
- };
-
- usim_ick: usim_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <9>;
- };
+ ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&corex2_fck>;
+ ti,bit-shift = <0>;
+ reg = <0x0a00>;
+ };
+
+ ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-divider-clock";
+ clocks = <&corex2_fck>;
+ ti,bit-shift = <8>;
+ reg = <0x0a40>;
+ ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+ };
+
+ ssi_ssr_fck: ssi_ssr_fck_3430es2 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
+ };
+
+ ssi_sst_fck: ssi_sst_fck_3430es2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&ssi_ssr_fck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-hsotgusb-interface-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <4>;
+ };
+
+ ssi_l4_ick: ssi_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ ssi_ick: ssi_ick_3430es2@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-ssi-interface-clock";
+ clocks = <&ssi_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <0>;
+ };
+
+ usim_gate_fck: usim_gate_fck@c00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&omap_96m_fck>;
+ ti,bit-shift = <9>;
+ reg = <0x0c00>;
+ };
+
+ sys_d2_ck: sys_d2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ omap_96m_d2_fck: omap_96m_d2_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ omap_96m_d4_fck: omap_96m_d4_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ omap_96m_d8_fck: omap_96m_d8_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ omap_96m_d10_fck: omap_96m_d10_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <10>;
+ };
+
+ dpll5_m2_d4_ck: dpll5_m2_d4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ dpll5_m2_d8_ck: dpll5_m2_d8_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ dpll5_m2_d16_ck: dpll5_m2_d16_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+ };
+
+ dpll5_m2_d20_ck: dpll5_m2_d20_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll5_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <20>;
+ };
+
+ usim_mux_fck: usim_mux_fck@c40 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x0c40>;
+ ti,index-starts-at-one;
+ };
+
+ usim_fck: usim_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&usim_gate_fck>, <&usim_mux_fck>;
+ };
+
+ usim_ick: usim_ick@c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x0c10>;
+ ti,bit-shift = <9>;
+ };
};
&cm_clockdomains {
- core_l3_clkdm: core_l3_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
- };
-
- wkup_clkdm: wkup_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
- <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
- <&gpt1_ick>, <&usim_ick>;
- };
-
- core_l4_clkdm: core_l4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
- <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
- <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
- <&ssi_ick>;
- };
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
+ };
+
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+ <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+ <&gpt1_ick>, <&usim_ick>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+ <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
+ <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+ <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+ <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+ <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+ <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+ <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+ <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+ <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+ <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+ <&ssi_ick>;
+ };
};
--- /dev/null
+/*
+ * Copyright (C) 2017
+ * Logic PD - http://www.logicpd.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&uart4 {
+ reg-shift = <2>;
+};
#include "omap3.dtsi"
/ {
- aliases {
- serial3 = &uart4;
- };
+ aliases {
+ serial3 = &uart4;
+ };
- cpus {
- /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
- cpu@0 {
- operating-points = <
- /* kHz uV */
- 300000 1012500
- 600000 1200000
- 800000 1325000
- >;
- clock-latency = <300000>; /* From legacy driver */
- };
- };
+ cpus {
+ /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
+ cpu: cpu@0 {
+ operating-points = <
+ /* kHz uV */
+ 300000 1012500
+ 600000 1200000
+ 800000 1325000
+ >;
+ clock-latency = <300000>; /* From legacy driver */
+ };
+ };
- ocp@68000000 {
- uart4: serial@49042000 {
- compatible = "ti,omap3-uart";
- reg = <0x49042000 0x400>;
- interrupts = <80>;
- dmas = <&sdma 81 &sdma 82>;
- dma-names = "tx", "rx";
- ti,hwmods = "uart4";
- clock-frequency = <48000000>;
- };
+ ocp@68000000 {
+ uart4: serial@49042000 {
+ compatible = "ti,omap3-uart";
+ reg = <0x49042000 0x400>;
+ reg-shift = <2>;
+ interrupts = <80>;
+ dmas = <&sdma 81 &sdma 82>;
+ dma-names = "tx", "rx";
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ };
- abb_mpu_iva: regulator-abb-mpu {
- compatible = "ti,abb-v1";
- regulator-name = "abb_mpu_iva";
- #address-cells = <0>;
- #size-cells = <0>;
- reg = <0x483072f0 0x8>, <0x48306818 0x4>;
- reg-names = "base-address", "int-address";
- ti,tranxdone-status-mask = <0x4000000>;
- clocks = <&sys_ck>;
- ti,settling-time = <30>;
- ti,clock-cycles = <8>;
- ti,abb_info = <
- /*uV ABB efuse rbb_m fbb_m vset_m*/
- 1012500 0 0 0 0 0
- 1200000 0 0 0 0 0
- 1325000 0 0 0 0 0
- 1375000 1 0 0 0 0
- >;
- };
+ abb_mpu_iva: regulator-abb-mpu {
+ compatible = "ti,abb-v1";
+ regulator-name = "abb_mpu_iva";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ reg = <0x483072f0 0x8>, <0x48306818 0x4>;
+ reg-names = "base-address", "int-address";
+ ti,tranxdone-status-mask = <0x4000000>;
+ clocks = <&sys_ck>;
+ ti,settling-time = <30>;
+ ti,clock-cycles = <8>;
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1012500 0 0 0 0 0
+ 1200000 0 0 0 0 0
+ 1325000 0 0 0 0 0
+ 1375000 1 0 0 0 0
+ >;
+ };
- omap3_pmx_core2: pinmux@480025a0 {
- compatible = "ti,omap3-padconf", "pinctrl-single";
- reg = <0x480025a0 0x5c>;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- pinctrl-single,register-width = <16>;
- pinctrl-single,function-mask = <0xff1f>;
- };
+ omap3_pmx_core2: pinmux@480025a0 {
+ compatible = "ti,omap3-padconf", "pinctrl-single";
+ reg = <0x480025a0 0x5c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0xff1f>;
+ };
- isp: isp@480bc000 {
- compatible = "ti,omap3-isp";
- reg = <0x480bc000 0x12fc
- 0x480bd800 0x0600>;
- interrupts = <24>;
- iommus = <&mmu_isp>;
- syscon = <&scm_conf 0x2f0>;
- ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
- #clock-cells = <1>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
+ isp: isp@480bc000 {
+ compatible = "ti,omap3-isp";
+ reg = <0x480bc000 0x12fc
+ 0x480bd800 0x0600>;
+ interrupts = <24>;
+ iommus = <&mmu_isp>;
+ syscon = <&scm_conf 0x2f0>;
+ ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
+ #clock-cells = <1>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
- bandgap@48002524 {
- reg = <0x48002524 0x4>;
- compatible = "ti,omap36xx-bandgap";
- #thermal-sensor-cells = <0>;
- };
- };
+ bandgap: bandgap@48002524 {
+ reg = <0x48002524 0x4>;
+ compatible = "ti,omap36xx-bandgap";
+ #thermal-sensor-cells = <0>;
+ };
+ };
+
+ thermal_zones: thermal-zones {
+ #include "omap3-cpu-thermal.dtsi"
+ };
};
/* OMAP3630 needs dss_96m_fck for VENC */
&venc {
- clocks = <&dss_tv_fck>, <&dss_96m_fck>;
- clock-names = "fck", "tv_dac_clk";
+ clocks = <&dss_tv_fck>, <&dss_96m_fck>;
+ clock-names = "fck", "tv_dac_clk";
};
&ssi {
- status = "ok";
+ status = "ok";
- clocks = <&ssi_ssr_fck>,
- <&ssi_sst_fck>,
- <&ssi_ick>;
- clock-names = "ssi_ssr_fck",
- "ssi_sst_fck",
- "ssi_ick";
+ clocks = <&ssi_ssr_fck>,
+ <&ssi_sst_fck>,
+ <&ssi_ick>;
+ clock-names = "ssi_ssr_fck",
+ "ssi_sst_fck",
+ "ssi_ick";
};
/include/ "omap34xx-omap36xx-clocks.dtsi"
* published by the Free Software Foundation.
*/
&prm_clocks {
- virt_16_8m_ck: virt_16_8m_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <16800000>;
- };
-
- osc_sys_ck: osc_sys_ck@d40 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
- reg = <0x0d40>;
- };
-
- sys_ck: sys_ck@1270 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&osc_sys_ck>;
- ti,bit-shift = <6>;
- ti,max-div = <3>;
- reg = <0x1270>;
- ti,index-starts-at-one;
- };
-
- sys_clkout1: sys_clkout1@d70 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&osc_sys_ck>;
- reg = <0x0d70>;
- ti,bit-shift = <7>;
- };
-
- dpll3_x2_ck: dpll3_x2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll3_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- dpll3_m2x2_ck: dpll3_m2x2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll3_m2_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- dpll4_x2_ck: dpll4_x2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll4_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- corex2_fck: corex2_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll3_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- wkup_l4_ick: wkup_l4_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&sys_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
+ virt_16_8m_ck: virt_16_8m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+ };
+
+ osc_sys_ck: osc_sys_ck@d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
+ reg = <0x0d40>;
+ };
+
+ sys_ck: sys_ck@1270 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&osc_sys_ck>;
+ ti,bit-shift = <6>;
+ ti,max-div = <3>;
+ reg = <0x1270>;
+ ti,index-starts-at-one;
+ };
+
+ sys_clkout1: sys_clkout1@d70 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&osc_sys_ck>;
+ reg = <0x0d70>;
+ ti,bit-shift = <7>;
+ };
+
+ dpll3_x2_ck: dpll3_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ dpll3_m2x2_ck: dpll3_m2x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m2_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ dpll4_x2_ck: dpll4_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ corex2_fck: corex2_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ wkup_l4_ick: wkup_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
};
&scm_clocks {
- mcbsp5_mux_fck: mcbsp5_mux_fck@68 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&core_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <4>;
- reg = <0x68>;
- };
-
- mcbsp5_fck: mcbsp5_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
- };
-
- mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&core_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <2>;
- reg = <0x04>;
- };
-
- mcbsp1_fck: mcbsp1_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
- };
-
- mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&per_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <6>;
- reg = <0x04>;
- };
-
- mcbsp2_fck: mcbsp2_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
- };
-
- mcbsp3_mux_fck: mcbsp3_mux_fck@68 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&per_96m_fck>, <&mcbsp_clks>;
- reg = <0x68>;
- };
-
- mcbsp3_fck: mcbsp3_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
- };
-
- mcbsp4_mux_fck: mcbsp4_mux_fck@68 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&per_96m_fck>, <&mcbsp_clks>;
- ti,bit-shift = <2>;
- reg = <0x68>;
- };
-
- mcbsp4_fck: mcbsp4_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
- };
+ mcbsp5_mux_fck: mcbsp5_mux_fck@68 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&core_96m_fck>, <&mcbsp_clks>;
+ ti,bit-shift = <4>;
+ reg = <0x68>;
+ };
+
+ mcbsp5_fck: mcbsp5_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
+ };
+
+ mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&core_96m_fck>, <&mcbsp_clks>;
+ ti,bit-shift = <2>;
+ reg = <0x04>;
+ };
+
+ mcbsp1_fck: mcbsp1_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
+ };
+
+ mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ ti,bit-shift = <6>;
+ reg = <0x04>;
+ };
+
+ mcbsp2_fck: mcbsp2_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
+ };
+
+ mcbsp3_mux_fck: mcbsp3_mux_fck@68 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ reg = <0x68>;
+ };
+
+ mcbsp3_fck: mcbsp3_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
+ };
+
+ mcbsp4_mux_fck: mcbsp4_mux_fck@68 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&per_96m_fck>, <&mcbsp_clks>;
+ ti,bit-shift = <2>;
+ reg = <0x68>;
+ };
+
+ mcbsp4_fck: mcbsp4_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
+ };
};
&cm_clocks {
- dummy_apb_pclk: dummy_apb_pclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0x0>;
- };
-
- omap_32k_fck: omap_32k_fck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- virt_12m_ck: virt_12m_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12000000>;
- };
-
- virt_13m_ck: virt_13m_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <13000000>;
- };
-
- virt_19200000_ck: virt_19200000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <19200000>;
- };
-
- virt_26000000_ck: virt_26000000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <26000000>;
- };
-
- virt_38_4m_ck: virt_38_4m_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <38400000>;
- };
-
- dpll4_ck: dpll4_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dpll-per-clock";
- clocks = <&sys_ck>, <&sys_ck>;
- reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
- };
-
- dpll4_m2_ck: dpll4_m2_ck@d48 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll4_ck>;
- ti,max-div = <63>;
- reg = <0x0d48>;
- ti,index-starts-at-one;
- };
-
- dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll4_m2_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll4_m2x2_mul_ck>;
- ti,bit-shift = <0x1b>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
-
- omap_96m_alwon_fck: omap_96m_alwon_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll4_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- dpll3_ck: dpll3_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dpll-core-clock";
- clocks = <&sys_ck>, <&sys_ck>;
- reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
- };
-
- dpll3_m3_ck: dpll3_m3_ck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll3_ck>;
- ti,bit-shift = <16>;
- ti,max-div = <31>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
- dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll3_m3_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll3_m3x2_mul_ck>;
- ti,bit-shift = <0xc>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
-
- emu_core_alwon_ck: emu_core_alwon_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll3_m3x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- sys_altclk: sys_altclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0x0>;
- };
-
- mcbsp_clks: mcbsp_clks {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0x0>;
- };
-
- dpll3_m2_ck: dpll3_m2_ck@d40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll3_ck>;
- ti,bit-shift = <27>;
- ti,max-div = <31>;
- reg = <0x0d40>;
- ti,index-starts-at-one;
- };
-
- core_ck: core_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll3_m2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- dpll1_fck: dpll1_fck@940 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <19>;
- ti,max-div = <7>;
- reg = <0x0940>;
- ti,index-starts-at-one;
- };
-
- dpll1_ck: dpll1_ck@904 {
- #clock-cells = <0>;
- compatible = "ti,omap3-dpll-clock";
- clocks = <&sys_ck>, <&dpll1_fck>;
- reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
- };
-
- dpll1_x2_ck: dpll1_x2_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll1_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- dpll1_x2m2_ck: dpll1_x2m2_ck@944 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll1_x2_ck>;
- ti,max-div = <31>;
- reg = <0x0944>;
- ti,index-starts-at-one;
- };
-
- cm_96m_fck: cm_96m_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_96m_alwon_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- omap_96m_fck: omap_96m_fck@d40 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&cm_96m_fck>, <&sys_ck>;
- ti,bit-shift = <6>;
- reg = <0x0d40>;
- };
-
- dpll4_m3_ck: dpll4_m3_ck@e40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll4_ck>;
- ti,bit-shift = <8>;
- ti,max-div = <32>;
- reg = <0x0e40>;
- ti,index-starts-at-one;
- };
-
- dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll4_m3_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll4_m3x2_mul_ck>;
- ti,bit-shift = <0x1c>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
-
- omap_54m_fck: omap_54m_fck@d40 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
- ti,bit-shift = <5>;
- reg = <0x0d40>;
- };
-
- cm_96m_d2_fck: cm_96m_d2_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&cm_96m_fck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- omap_48m_fck: omap_48m_fck@d40 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
- ti,bit-shift = <3>;
- reg = <0x0d40>;
- };
-
- omap_12m_fck: omap_12m_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_48m_fck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- dpll4_m4_ck: dpll4_m4_ck@e40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll4_ck>;
- ti,max-div = <32>;
- reg = <0x0e40>;
- ti,index-starts-at-one;
- };
-
- dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
- #clock-cells = <0>;
- compatible = "ti,fixed-factor-clock";
- clocks = <&dpll4_m4_ck>;
- ti,clock-mult = <2>;
- ti,clock-div = <1>;
- ti,set-rate-parent;
- };
-
- dpll4_m4x2_ck: dpll4_m4x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll4_m4x2_mul_ck>;
- ti,bit-shift = <0x1d>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- ti,set-rate-parent;
- };
-
- dpll4_m5_ck: dpll4_m5_ck@f40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll4_ck>;
- ti,max-div = <63>;
- reg = <0x0f40>;
- ti,index-starts-at-one;
- };
-
- dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
- #clock-cells = <0>;
- compatible = "ti,fixed-factor-clock";
- clocks = <&dpll4_m5_ck>;
- ti,clock-mult = <2>;
- ti,clock-div = <1>;
- ti,set-rate-parent;
- };
-
- dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll4_m5x2_mul_ck>;
- ti,bit-shift = <0x1e>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- ti,set-rate-parent;
- };
-
- dpll4_m6_ck: dpll4_m6_ck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll4_ck>;
- ti,bit-shift = <24>;
- ti,max-div = <63>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
- dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll4_m6_ck>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll4_m6x2_mul_ck>;
- ti,bit-shift = <0x1f>;
- reg = <0x0d00>;
- ti,set-bit-to-disable;
- };
-
- emu_per_alwon_ck: emu_per_alwon_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll4_m6x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- clkout2_src_gate_ck: clkout2_src_gate_ck@d70 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&core_ck>;
- ti,bit-shift = <7>;
- reg = <0x0d70>;
- };
-
- clkout2_src_mux_ck: clkout2_src_mux_ck@d70 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
- reg = <0x0d70>;
- };
-
- clkout2_src_ck: clkout2_src_ck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
- };
-
- sys_clkout2: sys_clkout2@d70 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&clkout2_src_ck>;
- ti,bit-shift = <3>;
- ti,max-div = <64>;
- reg = <0x0d70>;
- ti,index-power-of-two;
- };
-
- mpu_ck: mpu_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll1_x2m2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- arm_fck: arm_fck@924 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&mpu_ck>;
- reg = <0x0924>;
- ti,max-div = <2>;
- };
-
- emu_mpu_alwon_ck: emu_mpu_alwon_ck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&mpu_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- l3_ick: l3_ick@a40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&core_ck>;
- ti,max-div = <3>;
- reg = <0x0a40>;
- ti,index-starts-at-one;
- };
-
- l4_ick: l4_ick@a40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&l3_ick>;
- ti,bit-shift = <2>;
- ti,max-div = <3>;
- reg = <0x0a40>;
- ti,index-starts-at-one;
- };
-
- rm_ick: rm_ick@c40 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&l4_ick>;
- ti,bit-shift = <1>;
- ti,max-div = <3>;
- reg = <0x0c40>;
- ti,index-starts-at-one;
- };
-
- gpt10_gate_fck: gpt10_gate_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <11>;
- reg = <0x0a00>;
- };
-
- gpt10_mux_fck: gpt10_mux_fck@a40 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <6>;
- reg = <0x0a40>;
- };
-
- gpt10_fck: gpt10_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
- };
-
- gpt11_gate_fck: gpt11_gate_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <12>;
- reg = <0x0a00>;
- };
-
- gpt11_mux_fck: gpt11_mux_fck@a40 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <7>;
- reg = <0x0a40>;
- };
-
- gpt11_fck: gpt11_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
- };
-
- core_96m_fck: core_96m_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_96m_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- mmchs2_fck: mmchs2_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <25>;
- };
-
- mmchs1_fck: mmchs1_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <24>;
- };
-
- i2c3_fck: i2c3_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <17>;
- };
-
- i2c2_fck: i2c2_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <16>;
- };
-
- i2c1_fck: i2c1_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_96m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <15>;
- };
-
- mcbsp5_gate_fck: mcbsp5_gate_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <10>;
- reg = <0x0a00>;
- };
-
- mcbsp1_gate_fck: mcbsp1_gate_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <9>;
- reg = <0x0a00>;
- };
-
- core_48m_fck: core_48m_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_48m_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- mcspi4_fck: mcspi4_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <21>;
- };
-
- mcspi3_fck: mcspi3_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <20>;
- };
-
- mcspi2_fck: mcspi2_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <19>;
- };
-
- mcspi1_fck: mcspi1_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <18>;
- };
-
- uart2_fck: uart2_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <14>;
- };
-
- uart1_fck: uart1_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_48m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <13>;
- };
-
- core_12m_fck: core_12m_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_12m_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- hdq_fck: hdq_fck@a00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_12m_fck>;
- reg = <0x0a00>;
- ti,bit-shift = <22>;
- };
-
- core_l3_ick: core_l3_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l3_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- sdrc_ick: sdrc_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&core_l3_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <1>;
- };
-
- gpmc_fck: gpmc_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&core_l3_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- core_l4_ick: core_l4_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l4_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- mmchs2_ick: mmchs2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <25>;
- };
-
- mmchs1_ick: mmchs1_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <24>;
- };
-
- hdq_ick: hdq_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <22>;
- };
-
- mcspi4_ick: mcspi4_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <21>;
- };
-
- mcspi3_ick: mcspi3_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <20>;
- };
-
- mcspi2_ick: mcspi2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <19>;
- };
-
- mcspi1_ick: mcspi1_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <18>;
- };
-
- i2c3_ick: i2c3_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <17>;
- };
-
- i2c2_ick: i2c2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <16>;
- };
-
- i2c1_ick: i2c1_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <15>;
- };
-
- uart2_ick: uart2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <14>;
- };
-
- uart1_ick: uart1_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <13>;
- };
-
- gpt11_ick: gpt11_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <12>;
- };
-
- gpt10_ick: gpt10_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <11>;
- };
-
- mcbsp5_ick: mcbsp5_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <10>;
- };
-
- mcbsp1_ick: mcbsp1_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <9>;
- };
-
- omapctrl_ick: omapctrl_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <6>;
- };
-
- dss_tv_fck: dss_tv_fck@e00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&omap_54m_fck>;
- reg = <0x0e00>;
- ti,bit-shift = <2>;
- };
-
- dss_96m_fck: dss_96m_fck@e00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&omap_96m_fck>;
- reg = <0x0e00>;
- ti,bit-shift = <2>;
- };
-
- dss2_alwon_fck: dss2_alwon_fck@e00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_ck>;
- reg = <0x0e00>;
- ti,bit-shift = <1>;
- };
-
- dummy_ck: dummy_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-
- gpt1_gate_fck: gpt1_gate_fck@c00 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <0>;
- reg = <0x0c00>;
- };
-
- gpt1_mux_fck: gpt1_mux_fck@c40 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- reg = <0x0c40>;
- };
-
- gpt1_fck: gpt1_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
- };
-
- aes2_ick: aes2_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- ti,bit-shift = <28>;
- reg = <0x0a10>;
- };
-
- wkup_32k_fck: wkup_32k_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_32k_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- gpio1_dbck: gpio1_dbck@c00 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&wkup_32k_fck>;
- reg = <0x0c00>;
- ti,bit-shift = <3>;
- };
-
- sha12_ick: sha12_ick@a10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&core_l4_ick>;
- reg = <0x0a10>;
- ti,bit-shift = <27>;
- };
-
- wdt2_fck: wdt2_fck@c00 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&wkup_32k_fck>;
- reg = <0x0c00>;
- ti,bit-shift = <5>;
- };
-
- wdt2_ick: wdt2_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <5>;
- };
-
- wdt1_ick: wdt1_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <4>;
- };
-
- gpio1_ick: gpio1_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <3>;
- };
-
- omap_32ksync_ick: omap_32ksync_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <2>;
- };
-
- gpt12_ick: gpt12_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <1>;
- };
-
- gpt1_ick: gpt1_ick@c10 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&wkup_l4_ick>;
- reg = <0x0c10>;
- ti,bit-shift = <0>;
- };
-
- per_96m_fck: per_96m_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_96m_alwon_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- per_48m_fck: per_48m_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_48m_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- uart3_fck: uart3_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&per_48m_fck>;
- reg = <0x1000>;
- ti,bit-shift = <11>;
- };
-
- gpt2_gate_fck: gpt2_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <3>;
- reg = <0x1000>;
- };
-
- gpt2_mux_fck: gpt2_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- reg = <0x1040>;
- };
-
- gpt2_fck: gpt2_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
- };
-
- gpt3_gate_fck: gpt3_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <4>;
- reg = <0x1000>;
- };
-
- gpt3_mux_fck: gpt3_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <1>;
- reg = <0x1040>;
- };
-
- gpt3_fck: gpt3_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
- };
-
- gpt4_gate_fck: gpt4_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <5>;
- reg = <0x1000>;
- };
-
- gpt4_mux_fck: gpt4_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <2>;
- reg = <0x1040>;
- };
-
- gpt4_fck: gpt4_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
- };
-
- gpt5_gate_fck: gpt5_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <6>;
- reg = <0x1000>;
- };
-
- gpt5_mux_fck: gpt5_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <3>;
- reg = <0x1040>;
- };
-
- gpt5_fck: gpt5_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
- };
-
- gpt6_gate_fck: gpt6_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <7>;
- reg = <0x1000>;
- };
-
- gpt6_mux_fck: gpt6_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <4>;
- reg = <0x1040>;
- };
-
- gpt6_fck: gpt6_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
- };
-
- gpt7_gate_fck: gpt7_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <8>;
- reg = <0x1000>;
- };
-
- gpt7_mux_fck: gpt7_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <5>;
- reg = <0x1040>;
- };
-
- gpt7_fck: gpt7_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
- };
-
- gpt8_gate_fck: gpt8_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <9>;
- reg = <0x1000>;
- };
-
- gpt8_mux_fck: gpt8_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <6>;
- reg = <0x1040>;
- };
-
- gpt8_fck: gpt8_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
- };
-
- gpt9_gate_fck: gpt9_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&sys_ck>;
- ti,bit-shift = <10>;
- reg = <0x1000>;
- };
-
- gpt9_mux_fck: gpt9_mux_fck@1040 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&omap_32k_fck>, <&sys_ck>;
- ti,bit-shift = <7>;
- reg = <0x1040>;
- };
-
- gpt9_fck: gpt9_fck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
- };
-
- per_32k_alwon_fck: per_32k_alwon_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&omap_32k_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- gpio6_dbck: gpio6_dbck@1000 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <17>;
- };
-
- gpio5_dbck: gpio5_dbck@1000 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <16>;
- };
-
- gpio4_dbck: gpio4_dbck@1000 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <15>;
- };
-
- gpio3_dbck: gpio3_dbck@1000 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <14>;
- };
-
- gpio2_dbck: gpio2_dbck@1000 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <13>;
- };
-
- wdt3_fck: wdt3_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,wait-gate-clock";
- clocks = <&per_32k_alwon_fck>;
- reg = <0x1000>;
- ti,bit-shift = <12>;
- };
-
- per_l4_ick: per_l4_ick {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l4_ick>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- gpio6_ick: gpio6_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <17>;
- };
-
- gpio5_ick: gpio5_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <16>;
- };
-
- gpio4_ick: gpio4_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <15>;
- };
-
- gpio3_ick: gpio3_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <14>;
- };
-
- gpio2_ick: gpio2_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <13>;
- };
-
- wdt3_ick: wdt3_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <12>;
- };
-
- uart3_ick: uart3_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <11>;
- };
-
- uart4_ick: uart4_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <18>;
- };
-
- gpt9_ick: gpt9_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <10>;
- };
-
- gpt8_ick: gpt8_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <9>;
- };
-
- gpt7_ick: gpt7_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <8>;
- };
-
- gpt6_ick: gpt6_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <7>;
- };
-
- gpt5_ick: gpt5_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <6>;
- };
-
- gpt4_ick: gpt4_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <5>;
- };
-
- gpt3_ick: gpt3_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <4>;
- };
-
- gpt2_ick: gpt2_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <3>;
- };
-
- mcbsp2_ick: mcbsp2_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <0>;
- };
-
- mcbsp3_ick: mcbsp3_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <1>;
- };
-
- mcbsp4_ick: mcbsp4_ick@1010 {
- #clock-cells = <0>;
- compatible = "ti,omap3-interface-clock";
- clocks = <&per_l4_ick>;
- reg = <0x1010>;
- ti,bit-shift = <2>;
- };
-
- mcbsp2_gate_fck: mcbsp2_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <0>;
- reg = <0x1000>;
- };
-
- mcbsp3_gate_fck: mcbsp3_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <1>;
- reg = <0x1000>;
- };
-
- mcbsp4_gate_fck: mcbsp4_gate_fck@1000 {
- #clock-cells = <0>;
- compatible = "ti,composite-gate-clock";
- clocks = <&mcbsp_clks>;
- ti,bit-shift = <2>;
- reg = <0x1000>;
- };
-
- emu_src_mux_ck: emu_src_mux_ck@1140 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
- reg = <0x1140>;
- };
-
- emu_src_ck: emu_src_ck {
- #clock-cells = <0>;
- compatible = "ti,clkdm-gate-clock";
- clocks = <&emu_src_mux_ck>;
- };
-
- pclk_fck: pclk_fck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&emu_src_ck>;
- ti,bit-shift = <8>;
- ti,max-div = <7>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
- pclkx2_fck: pclkx2_fck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&emu_src_ck>;
- ti,bit-shift = <6>;
- ti,max-div = <3>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
- atclk_fck: atclk_fck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&emu_src_ck>;
- ti,bit-shift = <4>;
- ti,max-div = <3>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
- traceclk_src_fck: traceclk_src_fck@1140 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
- ti,bit-shift = <2>;
- reg = <0x1140>;
- };
-
- traceclk_fck: traceclk_fck@1140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&traceclk_src_fck>;
- ti,bit-shift = <11>;
- ti,max-div = <7>;
- reg = <0x1140>;
- ti,index-starts-at-one;
- };
-
- secure_32k_fck: secure_32k_fck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- gpt12_fck: gpt12_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&secure_32k_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- wdt1_fck: wdt1_fck {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&secure_32k_fck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
+ dummy_apb_pclk: dummy_apb_pclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+ };
+
+ omap_32k_fck: omap_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ virt_12m_ck: virt_12m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ virt_13m_ck: virt_13m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+ };
+
+ virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ };
+
+ virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ };
+
+ virt_38_4m_ck: virt_38_4m_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+ };
+
+ dpll4_ck: dpll4_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-per-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
+ };
+
+ dpll4_m2_ck: dpll4_m2_ck@d48 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ ti,max-div = <63>;
+ reg = <0x0d48>;
+ ti,index-starts-at-one;
+ };
+
+ dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m2x2_mul_ck>;
+ ti,bit-shift = <0x1b>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
+
+ omap_96m_alwon_fck: omap_96m_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll3_ck: dpll3_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-core-clock";
+ clocks = <&sys_ck>, <&sys_ck>;
+ reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
+ };
+
+ dpll3_m3_ck: dpll3_m3_ck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll3_ck>;
+ ti,bit-shift = <16>;
+ ti,max-div = <31>;
+ reg = <0x1140>;
+ ti,index-starts-at-one;
+ };
+
+ dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m3_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll3_m3x2_mul_ck>;
+ ti,bit-shift = <0xc>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
+
+ emu_core_alwon_ck: emu_core_alwon_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ sys_altclk: sys_altclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+ };
+
+ mcbsp_clks: mcbsp_clks {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x0>;
+ };
+
+ dpll3_m2_ck: dpll3_m2_ck@d40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll3_ck>;
+ ti,bit-shift = <27>;
+ ti,max-div = <31>;
+ reg = <0x0d40>;
+ ti,index-starts-at-one;
+ };
+
+ core_ck: core_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll3_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll1_fck: dpll1_fck@940 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <19>;
+ ti,max-div = <7>;
+ reg = <0x0940>;
+ ti,index-starts-at-one;
+ };
+
+ dpll1_ck: dpll1_ck@904 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-dpll-clock";
+ clocks = <&sys_ck>, <&dpll1_fck>;
+ reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
+ };
+
+ dpll1_x2_ck: dpll1_x2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll1_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ dpll1_x2m2_ck: dpll1_x2m2_ck@944 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll1_x2_ck>;
+ ti,max-div = <31>;
+ reg = <0x0944>;
+ ti,index-starts-at-one;
+ };
+
+ cm_96m_fck: cm_96m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_alwon_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ omap_96m_fck: omap_96m_fck@d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&cm_96m_fck>, <&sys_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x0d40>;
+ };
+
+ dpll4_m3_ck: dpll4_m3_ck@e40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ ti,bit-shift = <8>;
+ ti,max-div = <32>;
+ reg = <0x0e40>;
+ ti,index-starts-at-one;
+ };
+
+ dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m3_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m3x2_mul_ck>;
+ ti,bit-shift = <0x1c>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
+
+ omap_54m_fck: omap_54m_fck@d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
+ ti,bit-shift = <5>;
+ reg = <0x0d40>;
+ };
+
+ cm_96m_d2_fck: cm_96m_d2_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&cm_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ omap_48m_fck: omap_48m_fck@d40 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
+ ti,bit-shift = <3>;
+ reg = <0x0d40>;
+ };
+
+ omap_12m_fck: omap_12m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_48m_fck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ dpll4_m4_ck: dpll4_m4_ck@e40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ ti,max-div = <32>;
+ reg = <0x0e40>;
+ ti,index-starts-at-one;
+ };
+
+ dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "ti,fixed-factor-clock";
+ clocks = <&dpll4_m4_ck>;
+ ti,clock-mult = <2>;
+ ti,clock-div = <1>;
+ ti,set-rate-parent;
+ };
+
+ dpll4_m4x2_ck: dpll4_m4x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m4x2_mul_ck>;
+ ti,bit-shift = <0x1d>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ ti,set-rate-parent;
+ };
+
+ dpll4_m5_ck: dpll4_m5_ck@f40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ ti,max-div = <63>;
+ reg = <0x0f40>;
+ ti,index-starts-at-one;
+ };
+
+ dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "ti,fixed-factor-clock";
+ clocks = <&dpll4_m5_ck>;
+ ti,clock-mult = <2>;
+ ti,clock-div = <1>;
+ ti,set-rate-parent;
+ };
+
+ dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m5x2_mul_ck>;
+ ti,bit-shift = <0x1e>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ ti,set-rate-parent;
+ };
+
+ dpll4_m6_ck: dpll4_m6_ck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll4_ck>;
+ ti,bit-shift = <24>;
+ ti,max-div = <63>;
+ reg = <0x1140>;
+ ti,index-starts-at-one;
+ };
+
+ dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m6_ck>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll4_m6x2_mul_ck>;
+ ti,bit-shift = <0x1f>;
+ reg = <0x0d00>;
+ ti,set-bit-to-disable;
+ };
+
+ emu_per_alwon_ck: emu_per_alwon_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll4_m6x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ clkout2_src_gate_ck: clkout2_src_gate_ck@d70 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-no-wait-gate-clock";
+ clocks = <&core_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x0d70>;
+ };
+
+ clkout2_src_mux_ck: clkout2_src_mux_ck@d70 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
+ reg = <0x0d70>;
+ };
+
+ clkout2_src_ck: clkout2_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
+ };
+
+ sys_clkout2: sys_clkout2@d70 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&clkout2_src_ck>;
+ ti,bit-shift = <3>;
+ ti,max-div = <64>;
+ reg = <0x0d70>;
+ ti,index-power-of-two;
+ };
+
+ mpu_ck: mpu_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll1_x2m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ arm_fck: arm_fck@924 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mpu_ck>;
+ reg = <0x0924>;
+ ti,max-div = <2>;
+ };
+
+ emu_mpu_alwon_ck: emu_mpu_alwon_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&mpu_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ l3_ick: l3_ick@a40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&core_ck>;
+ ti,max-div = <3>;
+ reg = <0x0a40>;
+ ti,index-starts-at-one;
+ };
+
+ l4_ick: l4_ick@a40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l3_ick>;
+ ti,bit-shift = <2>;
+ ti,max-div = <3>;
+ reg = <0x0a40>;
+ ti,index-starts-at-one;
+ };
+
+ rm_ick: rm_ick@c40 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&l4_ick>;
+ ti,bit-shift = <1>;
+ ti,max-div = <3>;
+ reg = <0x0c40>;
+ ti,index-starts-at-one;
+ };
+
+ gpt10_gate_fck: gpt10_gate_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <11>;
+ reg = <0x0a00>;
+ };
+
+ gpt10_mux_fck: gpt10_mux_fck@a40 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x0a40>;
+ };
+
+ gpt10_fck: gpt10_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
+ };
+
+ gpt11_gate_fck: gpt11_gate_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <12>;
+ reg = <0x0a00>;
+ };
+
+ gpt11_mux_fck: gpt11_mux_fck@a40 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x0a40>;
+ };
+
+ gpt11_fck: gpt11_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
+ };
+
+ core_96m_fck: core_96m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ mmchs2_fck: mmchs2_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <25>;
+ };
+
+ mmchs1_fck: mmchs1_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <24>;
+ };
+
+ i2c3_fck: i2c3_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <17>;
+ };
+
+ i2c2_fck: i2c2_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <16>;
+ };
+
+ i2c1_fck: i2c1_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_96m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <15>;
+ };
+
+ mcbsp5_gate_fck: mcbsp5_gate_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <10>;
+ reg = <0x0a00>;
+ };
+
+ mcbsp1_gate_fck: mcbsp1_gate_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <9>;
+ reg = <0x0a00>;
+ };
+
+ core_48m_fck: core_48m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_48m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ mcspi4_fck: mcspi4_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <21>;
+ };
+
+ mcspi3_fck: mcspi3_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <20>;
+ };
+
+ mcspi2_fck: mcspi2_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <19>;
+ };
+
+ mcspi1_fck: mcspi1_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <18>;
+ };
+
+ uart2_fck: uart2_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <14>;
+ };
+
+ uart1_fck: uart1_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_48m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <13>;
+ };
+
+ core_12m_fck: core_12m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_12m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ hdq_fck: hdq_fck@a00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_12m_fck>;
+ reg = <0x0a00>;
+ ti,bit-shift = <22>;
+ };
+
+ core_l3_ick: core_l3_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ sdrc_ick: sdrc_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&core_l3_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <1>;
+ };
+
+ gpmc_fck: gpmc_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&core_l3_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ core_l4_ick: core_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ mmchs2_ick: mmchs2_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <25>;
+ };
+
+ mmchs1_ick: mmchs1_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <24>;
+ };
+
+ hdq_ick: hdq_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <22>;
+ };
+
+ mcspi4_ick: mcspi4_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <21>;
+ };
+
+ mcspi3_ick: mcspi3_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <20>;
+ };
+
+ mcspi2_ick: mcspi2_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <19>;
+ };
+
+ mcspi1_ick: mcspi1_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <18>;
+ };
+
+ i2c3_ick: i2c3_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <17>;
+ };
+
+ i2c2_ick: i2c2_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <16>;
+ };
+
+ i2c1_ick: i2c1_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <15>;
+ };
+
+ uart2_ick: uart2_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <14>;
+ };
+
+ uart1_ick: uart1_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <13>;
+ };
+
+ gpt11_ick: gpt11_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <12>;
+ };
+
+ gpt10_ick: gpt10_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <11>;
+ };
+
+ mcbsp5_ick: mcbsp5_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <10>;
+ };
+
+ mcbsp1_ick: mcbsp1_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <9>;
+ };
+
+ omapctrl_ick: omapctrl_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <6>;
+ };
+
+ dss_tv_fck: dss_tv_fck@e00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&omap_54m_fck>;
+ reg = <0x0e00>;
+ ti,bit-shift = <2>;
+ };
+
+ dss_96m_fck: dss_96m_fck@e00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&omap_96m_fck>;
+ reg = <0x0e00>;
+ ti,bit-shift = <2>;
+ };
+
+ dss2_alwon_fck: dss2_alwon_fck@e00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_ck>;
+ reg = <0x0e00>;
+ ti,bit-shift = <1>;
+ };
+
+ dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ gpt1_gate_fck: gpt1_gate_fck@c00 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <0>;
+ reg = <0x0c00>;
+ };
+
+ gpt1_mux_fck: gpt1_mux_fck@c40 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ reg = <0x0c40>;
+ };
+
+ gpt1_fck: gpt1_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
+ };
+
+ aes2_ick: aes2_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ ti,bit-shift = <28>;
+ reg = <0x0a10>;
+ };
+
+ wkup_32k_fck: wkup_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ gpio1_dbck: gpio1_dbck@c00 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&wkup_32k_fck>;
+ reg = <0x0c00>;
+ ti,bit-shift = <3>;
+ };
+
+ sha12_ick: sha12_ick@a10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&core_l4_ick>;
+ reg = <0x0a10>;
+ ti,bit-shift = <27>;
+ };
+
+ wdt2_fck: wdt2_fck@c00 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&wkup_32k_fck>;
+ reg = <0x0c00>;
+ ti,bit-shift = <5>;
+ };
+
+ wdt2_ick: wdt2_ick@c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x0c10>;
+ ti,bit-shift = <5>;
+ };
+
+ wdt1_ick: wdt1_ick@c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x0c10>;
+ ti,bit-shift = <4>;
+ };
+
+ gpio1_ick: gpio1_ick@c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x0c10>;
+ ti,bit-shift = <3>;
+ };
+
+ omap_32ksync_ick: omap_32ksync_ick@c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x0c10>;
+ ti,bit-shift = <2>;
+ };
+
+ gpt12_ick: gpt12_ick@c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x0c10>;
+ ti,bit-shift = <1>;
+ };
+
+ gpt1_ick: gpt1_ick@c10 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&wkup_l4_ick>;
+ reg = <0x0c10>;
+ ti,bit-shift = <0>;
+ };
+
+ per_96m_fck: per_96m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_96m_alwon_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ per_48m_fck: per_48m_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_48m_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ uart3_fck: uart3_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&per_48m_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <11>;
+ };
+
+ gpt2_gate_fck: gpt2_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x1000>;
+ };
+
+ gpt2_mux_fck: gpt2_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ reg = <0x1040>;
+ };
+
+ gpt2_fck: gpt2_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
+ };
+
+ gpt3_gate_fck: gpt3_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <4>;
+ reg = <0x1000>;
+ };
+
+ gpt3_mux_fck: gpt3_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <1>;
+ reg = <0x1040>;
+ };
+
+ gpt3_fck: gpt3_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
+ };
+
+ gpt4_gate_fck: gpt4_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <5>;
+ reg = <0x1000>;
+ };
+
+ gpt4_mux_fck: gpt4_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x1040>;
+ };
+
+ gpt4_fck: gpt4_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
+ };
+
+ gpt5_gate_fck: gpt5_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x1000>;
+ };
+
+ gpt5_mux_fck: gpt5_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x1040>;
+ };
+
+ gpt5_fck: gpt5_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
+ };
+
+ gpt6_gate_fck: gpt6_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x1000>;
+ };
+
+ gpt6_mux_fck: gpt6_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <4>;
+ reg = <0x1040>;
+ };
+
+ gpt6_fck: gpt6_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
+ };
+
+ gpt7_gate_fck: gpt7_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1000>;
+ };
+
+ gpt7_mux_fck: gpt7_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <5>;
+ reg = <0x1040>;
+ };
+
+ gpt7_fck: gpt7_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
+ };
+
+ gpt8_gate_fck: gpt8_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <9>;
+ reg = <0x1000>;
+ };
+
+ gpt8_mux_fck: gpt8_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x1040>;
+ };
+
+ gpt8_fck: gpt8_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
+ };
+
+ gpt9_gate_fck: gpt9_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&sys_ck>;
+ ti,bit-shift = <10>;
+ reg = <0x1000>;
+ };
+
+ gpt9_mux_fck: gpt9_mux_fck@1040 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-mux-clock";
+ clocks = <&omap_32k_fck>, <&sys_ck>;
+ ti,bit-shift = <7>;
+ reg = <0x1040>;
+ };
+
+ gpt9_fck: gpt9_fck {
+ #clock-cells = <0>;
+ compatible = "ti,composite-clock";
+ clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
+ };
+
+ per_32k_alwon_fck: per_32k_alwon_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&omap_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ gpio6_dbck: gpio6_dbck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <17>;
+ };
+
+ gpio5_dbck: gpio5_dbck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <16>;
+ };
+
+ gpio4_dbck: gpio4_dbck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <15>;
+ };
+
+ gpio3_dbck: gpio3_dbck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <14>;
+ };
+
+ gpio2_dbck: gpio2_dbck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <13>;
+ };
+
+ wdt3_fck: wdt3_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,wait-gate-clock";
+ clocks = <&per_32k_alwon_fck>;
+ reg = <0x1000>;
+ ti,bit-shift = <12>;
+ };
+
+ per_l4_ick: per_l4_ick {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l4_ick>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ gpio6_ick: gpio6_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <17>;
+ };
+
+ gpio5_ick: gpio5_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <16>;
+ };
+
+ gpio4_ick: gpio4_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <15>;
+ };
+
+ gpio3_ick: gpio3_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <14>;
+ };
+
+ gpio2_ick: gpio2_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <13>;
+ };
+
+ wdt3_ick: wdt3_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <12>;
+ };
+
+ uart3_ick: uart3_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <11>;
+ };
+
+ uart4_ick: uart4_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <18>;
+ };
+
+ gpt9_ick: gpt9_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <10>;
+ };
+
+ gpt8_ick: gpt8_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <9>;
+ };
+
+ gpt7_ick: gpt7_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <8>;
+ };
+
+ gpt6_ick: gpt6_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <7>;
+ };
+
+ gpt5_ick: gpt5_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <6>;
+ };
+
+ gpt4_ick: gpt4_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <5>;
+ };
+
+ gpt3_ick: gpt3_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <4>;
+ };
+
+ gpt2_ick: gpt2_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <3>;
+ };
+
+ mcbsp2_ick: mcbsp2_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <0>;
+ };
+
+ mcbsp3_ick: mcbsp3_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <1>;
+ };
+
+ mcbsp4_ick: mcbsp4_ick@1010 {
+ #clock-cells = <0>;
+ compatible = "ti,omap3-interface-clock";
+ clocks = <&per_l4_ick>;
+ reg = <0x1010>;
+ ti,bit-shift = <2>;
+ };
+
+ mcbsp2_gate_fck: mcbsp2_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <0>;
+ reg = <0x1000>;
+ };
+
+ mcbsp3_gate_fck: mcbsp3_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <1>;
+ reg = <0x1000>;
+ };
+
+ mcbsp4_gate_fck: mcbsp4_gate_fck@1000 {
+ #clock-cells = <0>;
+ compatible = "ti,composite-gate-clock";
+ clocks = <&mcbsp_clks>;
+ ti,bit-shift = <2>;
+ reg = <0x1000>;
+ };
+
+ emu_src_mux_ck: emu_src_mux_ck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+ reg = <0x1140>;
+ };
+
+ emu_src_ck: emu_src_ck {
+ #clock-cells = <0>;
+ compatible = "ti,clkdm-gate-clock";
+ clocks = <&emu_src_mux_ck>;
+ };
+
+ pclk_fck: pclk_fck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&emu_src_ck>;
+ ti,bit-shift = <8>;
+ ti,max-div = <7>;
+ reg = <0x1140>;
+ ti,index-starts-at-one;
+ };
+
+ pclkx2_fck: pclkx2_fck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&emu_src_ck>;
+ ti,bit-shift = <6>;
+ ti,max-div = <3>;
+ reg = <0x1140>;
+ ti,index-starts-at-one;
+ };
+
+ atclk_fck: atclk_fck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&emu_src_ck>;
+ ti,bit-shift = <4>;
+ ti,max-div = <3>;
+ reg = <0x1140>;
+ ti,index-starts-at-one;
+ };
+
+ traceclk_src_fck: traceclk_src_fck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+ ti,bit-shift = <2>;
+ reg = <0x1140>;
+ };
+
+ traceclk_fck: traceclk_fck@1140 {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&traceclk_src_fck>;
+ ti,bit-shift = <11>;
+ ti,max-div = <7>;
+ reg = <0x1140>;
+ ti,index-starts-at-one;
+ };
+
+ secure_32k_fck: secure_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ gpt12_fck: gpt12_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&secure_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ wdt1_fck: wdt1_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&secure_32k_fck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
};
&cm_clockdomains {
- core_l3_clkdm: core_l3_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&sdrc_ick>;
- };
-
- dpll3_clkdm: dpll3_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll3_ck>;
- };
-
- dpll1_clkdm: dpll1_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll1_ck>;
- };
-
- per_clkdm: per_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
- <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
- <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
- <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
- <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
- <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
- <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
- <&mcbsp4_ick>;
- };
-
- emu_clkdm: emu_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&emu_src_ck>;
- };
-
- dpll4_clkdm: dpll4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll4_ck>;
- };
-
- wkup_clkdm: wkup_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
- <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
- <&gpt1_ick>;
- };
-
- dss_clkdm: dss_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
- };
-
- core_l4_clkdm: core_l4_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
- <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
- <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
- <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
- <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
- <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
- <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
- <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;
- };
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sdrc_ick>;
+ };
+
+ dpll3_clkdm: dpll3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll3_ck>;
+ };
+
+ dpll1_clkdm: dpll1_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll1_ck>;
+ };
+
+ per_clkdm: per_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
+ <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
+ <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
+ <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
+ <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
+ <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
+ <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
+ <&mcbsp4_ick>;
+ };
+
+ emu_clkdm: emu_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&emu_src_ck>;
+ };
+
+ dpll4_clkdm: dpll4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll4_ck>;
+ };
+
+ wkup_clkdm: wkup_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+ <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+ <&gpt1_ick>;
+ };
+
+ dss_clkdm: dss_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
+ };
+
+ core_l4_clkdm: core_l4_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+ <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+ <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+ <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+ <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+ <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+ <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+ <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+ <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;
+ };
};
*/
/{
+ chosen {
+ tick-timer = &timer2;
+ };
+
ocp {
u-boot,dm-spl;
&uart1 {
u-boot,dm-spl;
+ reg-shift = <2>;
};
&uart3 {
u-boot,dm-spl;
+ reg-shift = <2>;
};
&mmc1 {
u-boot,dm-spl;
m25p80@0 {
+ compatible = "spi-flash";
u-boot,dm-spl;
};
};
--- /dev/null
+/*
+ * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3288.dtsi"
+
+/ {
+ model = "Amarula Vyasa-RK3288";
+ compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwr>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_sys: vsys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&dmc {
+ rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+ 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+ 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+ 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+ 0x5 0x0>;
+ rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+ 0xa60 0x40 0x10 0x0>;
+ /* Add a dummy value to cause of-platdata think this is bytes */
+ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
+};
+
+&cpu0 {
+ cpu0-supply = <&vdd_cpu>;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int &global_pwroff>;
+ wakeup-source;
+ rockchip,system-power-controller;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_io>;
+ vcc9-supply = <&vcc_sys>;
+ vcc10-supply = <&vcc_sys>;
+ vcc11-supply = <&vcc_sys>;
+ vcc12-supply = <&vcc_io>;
+
+ regulators {
+ vdd_cpu: vdd_log: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-name = "vdd_log";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd_gpu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_io";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_tp: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_tp";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_codec: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_codec";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd_10";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_gps: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_gps";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc10_lcd: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vcc10_lcd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_18: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_18";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_lcd: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_lcd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc33_sd: SWITCH_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33_sd";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_lan: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_lan";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vccio_sd>;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_pwr: sdmmc-pwr {
+ rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
chosen {
stdout-path = "serial0:115200n8";
u-boot,spl-boot-order = &emmc, &sdmmc;
+ tick-timer = "/timer@ff810000";
};
};
};
&emmc {
- u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
};
&spi1 {
- u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
spiflash: w25q32dw@0 {
- u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
};
};
&timer0 {
u-boot,dm-pre-reloc;
clock-frequency = <24000000>;
+ status = "okay";
};
};
};
+ usbhub_enable: usbhub_enable {
+ compatible = "regulator-fixed";
+ regulator-name = "usbhub_enable";
+ enable-active-low;
+ gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
vccadc_ref: vccadc-ref {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_sys";
};
&dwc3_typec1 {
- rockchip,vbus-gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
chosen {
stdout-path = "serial2:1500000n8";
};
+
+ vcc5v0_otg: vcc5v0-otg-drv {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ regulator-name = "vcc5v0_otg";
+ gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
};
&gmac {
&uart2 {
status = "okay";
};
+
+&usb20_otg {
+ vbus-supply = <&vcc5v0_otg>;
+ status = "okay";
+};
+
+&usb_host_ehci {
+ status = "okay";
+};
+
+&usb_host_ohci {
+ status = "okay";
+};
status = "disabled";
};
+ usb_host_ehci: usb@30140000 {
+ compatible = "generic-ehci";
+ reg = <0x30140000 0x20000>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ usb_host_ohci: usb@30160000 {
+ compatible = "generic-ohci";
+ reg = <0x30160000 0x20000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ usb20_otg: usb@30180000 {
+ compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb",
+ "snps,dwc2";
+ reg = <0x30180000 0x40000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ hnp-srp-disable;
+ dr_mode = "otg";
+ status = "disabled";
+ };
+
sfc: sfc@301c0000 {
compatible = "rockchip,sfc";
reg = <0x301c0000 0x200>;
compatible = "atmel,at91sam9x5-clk-utmi";
#clock-cells = <0>;
clocks = <&main>;
+ regmap-sfr = <&sfr>;
u-boot,dm-pre-reloc;
};
qspi0_clk: qspi0_clk@52 {
#clock-cells = <0>;
reg = <52>;
+ u-boot,dm-pre-reloc;
};
qspi1_clk: qspi1_clk@53 {
#clock-cells = <0>;
reg = <53>;
+ u-boot,dm-pre-reloc;
};
};
status = "disabled";
};
+ qspi1: spi@f0024000 {
+ compatible = "atmel,sama5d2-qspi";
+ reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&qspi1_clk>;
+ status = "disabled";
+ };
+
spi0: spi@f8000000 {
compatible = "atmel,at91rm9200-spi";
reg = <0xf8000000 0x100>;
status = "disabled";
};
+ sfr: sfr@f8030000 {
+ compatible = "atmel,sama5d2-sfr", "syscon";
+ reg = <0xf8030000 0x98>;
+ };
+
sckc@f8048050 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xf8048050 0x4>;
status = "disabled";
};
+ uart3: serial@fc008000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfc008000 0x100>;
+ clocks = <&uart3_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
i2c1: i2c@fc028000 {
compatible = "atmel,sama5d2-i2c";
reg = <0xfc028000 0x100>;
--- /dev/null
+/*
+ * sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SOM1
+ *
+ * Copyright (C) 2017 Microchip Corporation
+ * Wenyou Yang <wenyou.yang@microchip.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+/ {
+ model = "Atmel SAMA5D27 SOM1 EK";
+ compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d2", "atmel,sama5";
+
+ memory {
+ reg = <0x20000000 0x8000000>;
+ };
+
+ aliases {
+ spi0 = &qspi1;
+ u-boot,dm-pre-reloc;
+ };
+
+ ahb {
+ apb {
+ qspi1: spi@f0024000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_sck_cs_default &pinctrl_qspi1_dat_default>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ spi_flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ macb0: ethernet@f8008000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
+ phy-mode = "rmii";
+ status = "okay";
+
+ ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ };
+
+ i2c0: i2c@f8028000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ status = "okay";
+
+ i2c_eeprom: i2c_eeprom@50 {
+ compatible = "microchip,24aa02e48";
+ reg = <0x50>;
+ };
+ };
+
+ i2c1: i2c@fc028000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ status = "okay";
+ };
+
+ pioA: gpio@fc038000 {
+ pinctrl {
+ pinctrl_i2c0_default: i2c0_default {
+ pinmux = <PIN_PD21__TWD0>,
+ <PIN_PD22__TWCK0>;
+ bias-disable;
+ };
+
+ pinctrl_i2c1_default: i2c1_default {
+ pinmux = <PIN_PD4__TWD1>,
+ <PIN_PD5__TWCK1>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_phy_irq: macb0_phy_irq {
+ pinmux = <PIN_PD31__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_rmii: macb0_rmii {
+ pinmux = <PIN_PD9__GTXCK>,
+ <PIN_PD10__GTXEN>,
+ <PIN_PD11__GRXDV>,
+ <PIN_PD12__GRXER>,
+ <PIN_PD13__GRX0>,
+ <PIN_PD14__GRX1>,
+ <PIN_PD15__GTX0>,
+ <PIN_PD16__GTX1>,
+ <PIN_PD17__GMDC>,
+ <PIN_PD18__GMDIO>;
+ bias-disable;
+ };
+
+ pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default {
+ pinmux = <PIN_PB5__QSPI1_SCK>,
+ <PIN_PB6__QSPI1_CS>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_qspi1_dat_default: qspi1_dat_default {
+ pinmux = <PIN_PB7__QSPI1_IO0>,
+ <PIN_PB8__QSPI1_IO1>,
+ <PIN_PB9__QSPI1_IO2>,
+ <PIN_PB10__QSPI1_IO3>;
+ bias-pull-up;
+ u-boot,dm-pre-reloc;
+ };
+ };
+ };
+ };
+ };
+};
interrupt-parent = <&pmc>;
interrupts = <AT91_PMC_LOCKU>;
clocks = <&main>;
+ regmap-sfr = <&sfr>;
+ u-boot,dm-pre-reloc;
};
mck: masterck {
#define CONFIG_SYS_FSL_ERRATUM_A008751
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+
+#elif defined(CONFIG_ARCH_LS1088A)
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
+#define CONFIG_GICV3
+#define CONFIG_FSL_TZPC_BP147
+#define CONFIG_FSL_TZASC_400
+#define CONFIG_SYS_PAGE_SIZE 0x10000
+
+#define SRDS_MAX_LANES 4
+
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE 0x02200000
+#define TZPCR0SIZE_BASE (TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0x06000000
+#define GICR_BASE 0x06100000
+
+/* SMMU Defintions */
+#define SMMU_BASE 0x05000000 /* GR0 Base */
+
+/* DDR */
+#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
+
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
+
#elif defined(CONFIG_FSL_LSCH2)
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
#define GICC_BASE 0x01420000
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
-
#else
#error SoC not defined
#endif
CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+ CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
+ CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
+ CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
+ CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
};
#ifndef CONFIG_SYS_DCACHE_OFF
},
{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
CONFIG_SYS_FSL_QSPI_SIZE2,
},
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
CONFIG_SYS_FSL_IFC_SIZE2,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
CONFIG_SYS_FSL_DCSR_SIZE,
#include <config.h>
-#ifdef CONFIG_ARCH_LS2080A
+#ifdef CONFIG_FSL_LSCH3
enum srds_prtcl {
/*
* Nobody will check whether the device 'NONE' has been configured,
int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+int serdes_get_number(int serdes, int cfg);
+void fsl_rgmii_init(void);
#ifdef CONFIG_FSL_LSCH2
const char *serdes_clock_to_string(u32 clock);
#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
#define SCFG_USBPWRFAULT_USB2_SHIFT 2
#define SCFG_USBPWRFAULT_USB1_SHIFT 0
+#define SCFG_BASE 0x01570000
+#define SCFG_USB3PRM1CR_USB1 0x070
+#define SCFG_USB3PRM2CR_USB1 0x074
+#define SCFG_USB3PRM1CR_USB2 0x07C
+#define SCFG_USB3PRM2CR_USB2 0x080
+#define SCFG_USB3PRM1CR_USB3 0x088
+#define SCFG_USB3PRM2CR_USB3 0x08c
+#define SCFG_USB_TXVREFTUNE 0x9
+#define SCFG_USB_SQRXTUNE_MASK 0x7
+#define SCFG_USB_PCSTXSWINGFULL 0x47
+#define SCFG_USB_PHY1 0x084F0000
+#define SCFG_USB_PHY2 0x08500000
+#define SCFG_USB_PHY3 0x08510000
+#define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x0080
+#define USB_PHY_RX_EQ_VAL_3 0x0380
+#define USB_PHY_RX_EQ_VAL_4 0x0b80
+
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
};
-#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
-#define CCI400_CTRLORD_EN_BARRIER 0
-#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
-#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
-#define CCI400_SNOOP_REQ_EN 0x00000001
-
-/* CCI-400 registers */
-struct ccsr_cci400 {
- u32 ctrl_ord; /* Control Override */
- u32 spec_ctrl; /* Speculation Control */
- u32 secure_access; /* Secure Access */
- u32 status; /* Status */
- u32 impr_err; /* Imprecise Error */
- u8 res_14[0x100 - 0x14];
- u32 pmcr; /* Performance Monitor Control */
- u8 res_104[0xfd0 - 0x104];
- u32 pid[8]; /* Peripheral ID */
- u32 cid[4]; /* Component ID */
- struct {
- u32 snoop_ctrl; /* Snoop Control */
- u32 sha_ord; /* Shareable Override */
- u8 res_1008[0x1100 - 0x1008];
- u32 rc_qos_ord; /* read channel QoS Value Override */
- u32 wc_qos_ord; /* read channel QoS Value Override */
- u8 res_1108[0x110c - 0x1108];
- u32 qos_ctrl; /* QoS Control */
- u32 max_ot; /* Max OT */
- u8 res_1114[0x1130 - 0x1114];
- u32 target_lat; /* Target Latency */
- u32 latency_regu; /* Latency Regulation */
- u32 qos_range; /* QoS Range */
- u8 res_113c[0x2000 - 0x113c];
- } slave[5]; /* Slave Interface */
- u8 res_6000[0x9004 - 0x6000];
- u32 cycle_counter; /* Cycle counter */
- u32 count_ctrl; /* Count Control */
- u32 overflow_status; /* Overflow Flag Status */
- u8 res_9010[0xa000 - 0x9010];
- struct {
- u32 event_select; /* Event Select */
- u32 event_count; /* Event Count */
- u32 counter_ctrl; /* Counter Control */
- u32 overflow_status; /* Overflow Flag Status */
- u8 res_a010[0xb000 - 0xa010];
- } pcounter[4]; /* Performance Counter */
- u8 res_e004[0x10000 - 0xe004];
-};
-
/* MMU 500 */
#define SMMU_SCR0 (SMMU_BASE + 0x0)
#define SMMU_SCR1 (SMMU_BASE + 0x4)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
+#ifdef CONFIG_ARCH_LS1088A
+#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL
+#else
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
+#endif
/* Device Configuration */
#define DCFG_BASE 0x01e00000
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
+#define SCFG_USB_TXVREFTUNE 0x9
+#define SCFG_USB_SQRXTUNE_MASK 0x7
#define SCFG_QSPICLKCTLR 0x10
+#define DCSR_BASE 0x700000000ULL
+#define DCSR_USB_PHY1 0x4600000
+#define DCSR_USB_PHY2 0x4610000
+#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x0080
+#define USB_PHY_RX_EQ_VAL_3 0x0380
+#define USB_PHY_RX_EQ_VAL_4 0x0b80
+
#define TP_ITYP_AV 0x00000001 /* Initiator available */
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
#define TP_ITYP_TYPE_ARM 0x0
#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
#define FSL_CHASSIS3_SRDS1_REGSR 29
#define FSL_CHASSIS3_SRDS2_REGSR 29
+#elif defined(CONFIG_ARCH_LS1088A)
+#define FSL_CHASSIS3_EC1_REGSR 26
+#define FSL_CHASSIS3_EC2_REGSR 26
+#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007
+#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0
+#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038
+#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3
+#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
+#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
+#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF
+#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0
+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS1_REGSR 29
+#define FSL_CHASSIS3_SRDS2_REGSR 30
#endif
#define RCW_SB_EN_REG_INDEX 9
#define RCW_SB_EN_MASK 0x00000400
#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
#define scfg_in32(a) in_le32(a)
#define scfg_out32(a, v) out_le32(a, v)
+#define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear)
+#define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set)
#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
#define scfg_in32(a) in_be32(a)
#define scfg_out32(a, v) out_be32(a, v)
+#define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
+#define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
#endif
#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
#define SVR_LS1023A 0x879208
#define SVR_LS1046A 0x870700
#define SVR_LS1026A 0x870708
+#define SVR_LS1048A 0x870320
+#define SVR_LS1084A 0x870302
+#define SVR_LS1088A 0x870300
+#define SVR_LS1044A 0x870322
#define SVR_LS2045A 0x870120
#define SVR_LS2080A 0x870110
#define SVR_LS2085A 0x870100
#define FSL_USB2_STREAM_ID 2
#define FSL_SDMMC_STREAM_ID 3
#define FSL_SATA1_STREAM_ID 4
+
+#if defined(CONFIG_ARCH_LS2080A)
#define FSL_SATA2_STREAM_ID 5
+#endif
+
+#if defined(CONFIG_ARCH_LS2080A)
#define FSL_DMA_STREAM_ID 6
+#elif defined(CONFIG_ARCH_LS1088A)
+#define FSL_DMA_STREAM_ID 5
+#endif
/* PCI - programmed in PEXn_LUT */
#define FSL_PEX_STREAM_ID_START 7
+
+#if defined(CONFIG_ARCH_LS2080A)
#define FSL_PEX_STREAM_ID_END 22
+#elif defined(CONFIG_ARCH_LS1088A)
+#define FSL_PEX_STREAM_ID_END 18
+#endif
+
/* DPAA2 - set in MC DPC and alloced by MC */
#define FSL_DPAA2_STREAM_ID_START 23
#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#ifndef __ASM_ARCH_LS102XA_IMMAP_H_
#define __ASM_ARCH_LS102XA_IMMAP_H_
+#include <fsl_immap.h>
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
#define SCFG_PMCINTECR_ETSECERRG1 0x00040000
#define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000
+#define SCFG_BASE 0x01570000
+#define SCFG_USB3PRM1CR 0x070
+#define SCFG_USB_TXVREFTUNE 0x9
+#define SCFG_USB_SQRXTUNE_MASK 0x7
+#define SCFG_USB3PRM2CR 0x074
+#define SCFG_USB_PCSTXSWINGFULL_MASK 0x0000FE00
+#define SCFG_USB_PCSTXSWINGFULL_VAL 0x00008E00
+
+#define USB_PHY_BASE 0x08510000
+#define USB_PHY_RX_OVRD_IN_HI 0x200c
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8004
+#define USB_PHY_RX_EQ_VAL_4 0x800C
+
/* Supplemental Configuration Unit */
struct ccsr_scfg {
u32 dpslpcr;
u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
};
-#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
-#define CCI400_CTRLORD_EN_BARRIER 0
-#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
-#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
-#define CCI400_SNOOP_REQ_EN 0x00000001
-
-/* CCI-400 registers */
-struct ccsr_cci400 {
- u32 ctrl_ord; /* Control Override */
- u32 spec_ctrl; /* Speculation Control */
- u32 secure_access; /* Secure Access */
- u32 status; /* Status */
- u32 impr_err; /* Imprecise Error */
- u8 res_14[0x100 - 0x14];
- u32 pmcr; /* Performance Monitor Control */
- u8 res_104[0xfd0 - 0x104];
- u32 pid[8]; /* Peripheral ID */
- u32 cid[4]; /* Component ID */
- struct {
- u32 snoop_ctrl; /* Snoop Control */
- u32 sha_ord; /* Shareable Override */
- u8 res_1008[0x1100 - 0x1008];
- u32 rc_qos_ord; /* read channel QoS Value Override */
- u32 wc_qos_ord; /* read channel QoS Value Override */
- u8 res_1108[0x110c - 0x1108];
- u32 qos_ctrl; /* QoS Control */
- u32 max_ot; /* Max OT */
- u8 res_1114[0x1130 - 0x1114];
- u32 target_lat; /* Target Latency */
- u32 latency_regu; /* Latency Regulation */
- u32 qos_range; /* QoS Range */
- u8 res_113c[0x2000 - 0x113c];
- } slave[5]; /* Slave Interface */
- u8 res_6000[0x9004 - 0x6000];
- u32 cycle_counter; /* Cycle counter */
- u32 count_ctrl; /* Count Control */
- u32 overflow_status; /* Overflow Flag Status */
- u8 res_9010[0xa000 - 0x9010];
- struct {
- u32 event_select; /* Event Select */
- u32 event_count; /* Event Count */
- u32 counter_ctrl; /* Counter Control */
- u32 overflow_status; /* Overflow Flag Status */
- u8 res_a010[0xb000 - 0xa010];
- } pcounter[4]; /* Performance Counter */
- u8 res_e004[0x10000 - 0xe004];
-};
+
/* AHCI (sata) register map */
struct ccsr_ahci {
*/
#include <asm/mach-imx/sys_proto.h>
+
+#define USBPHY_PWD 0x00000000
+
+#define USBPHY_PWD_RXPWDRX (1 << 20) /* receiver block power down */
+
+#define is_usbotg_phy_active(void) (!(readl(USB_PHY0_BASE_ADDR + USBPHY_PWD) & \
+ USBPHY_PWD_RXPWDRX))
};
enum enet_freq {
- ENET_25MHz,
- ENET_50MHz,
- ENET_125MHz,
+ ENET_25MHZ,
+ ENET_50MHZ,
+ ENET_125MHZ,
};
u32 get_root_clk(enum clk_root_index clock_id);
/* Offset is 0.73V for LP873x */
#define LP873X_BUCK_BASE_VOLT_UV 730000
+/* Offset is 0.73V for LP87565 */
+#define LP87565_BUCK_BASE_VOLT_UV 730000
+
/* TPS659038 */
#define TPS659038_I2C_SLAVE_ADDR 0x58
#define TPS659038_REG_ADDR_SMPS12 0x23
#define TPS65917_REG_ADDR_SMPS1 0x23
#define TPS65917_REG_ADDR_SMPS2 0x27
#define TPS65917_REG_ADDR_SMPS3 0x2F
+#define TPS65917_REG_ADDR_SMPS4 0x33
/* LP873X */
#define LP873X_I2C_SLAVE_ADDR 0x60
#define LP873X_REG_ADDR_BUCK1 0x7
#define LP873X_REG_ADDR_LDO1 0xA
+/* LP87565 */
+#define LP87565_I2C_SLAVE_ADDR 0x61
+#define LP87565_REG_ADDR_BUCK01 0xA
+#define LP87565_REG_ADDR_BUCK23 0xE
+
/* TPS */
#define TPS62361_I2C_SLAVE_ADDR 0x60
#define TPS62361_REG_ADDR_SET0 0x0
#include <asm/types.h>
-#define FSC (1 << 19)
-#define SSC (0 << 19)
-
-#define IEN (1 << 18)
-#define IDIS (0 << 18)
-
-#define PTU (1 << 17)
-#define PTD (0 << 17)
-#define PEN (1 << 16)
-#define PDIS (0 << 16)
-
-#define WKEN (1 << 24)
-#define WKDIS (0 << 24)
-
#define PULL_ENA (0 << 16)
#define PULL_DIS (1 << 16)
#define PULL_UP (1 << 17)
#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
+#define DRA762_CONTROL_ID_CODE_ES1_0 0x0BB5002F
#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F
#define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F
#define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F
#define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F
+#define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F
/* UART */
#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
unsigned int os_reg[8];
unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
unsigned int ddrc_stat;
+ unsigned int reserved10[(0x680 - 0x604) / 4 - 1];
+ unsigned int sig_detect_con[2];
+ unsigned int reserved11[(0x690 - 0x684) / 4 - 1];
+ unsigned int sig_detect_status[2];
+ unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1];
+ unsigned int sig_detect_clr[2];
+ unsigned int reserved13[(0x6b0 - 0x6a4) / 4 - 1];
+ unsigned int emmc_det;
+ unsigned int reserved14[(0x700 - 0x6b0) / 4 - 1];
+ unsigned int host0_con[3];
+ unsigned int reserved15;
+ unsigned int host1_con[3];
+ unsigned int reserved16;
+ unsigned int host2_con[3];
+ unsigned int reserved17[(0x760 - 0x728) / 4 - 1];
+ unsigned int usbphy0_con[27];
+ unsigned int reserved18[(0x800 - 0x7c8) / 4 - 1];
+ unsigned int usbphy1_con[27];
+ unsigned int reserved19[(0x880 - 0x868) / 4 - 1];
+ unsigned int otg_con0;
+ unsigned int uoc_status0;
+ unsigned int reserved20[(0x900 - 0x884) / 4 - 1];
+ unsigned int mac_con[2];
+ unsigned int reserved21[(0xb00 - 0x904) / 4 - 1];
+ unsigned int macphy_con[4];
+ unsigned int macphy_status;
};
check_member(rk322x_grf, ddrc_stat, 0x604);
CON_IOMUX_PWM0SEL_SHIFT = 0,
CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
};
+
+/* GRF_MACPHY_CON0 */
+enum {
+ MACPHY_CFG_ENABLE_SHIFT = 0,
+ MACPHY_CFG_ENABLE_MASK = 1 << MACPHY_CFG_ENABLE_SHIFT,
+};
#endif
#ifndef _ASM_ARMV8_MMU_H_
#define _ASM_ARMV8_MMU_H_
-/***************************************************************/
-/*
- * The following definitions are related each other, shoud be
- * calculated specifically.
- */
-
-#define VA_BITS CONFIG_SYS_VA_BITS
-#define PTE_BLOCK_BITS CONFIG_SYS_PTL2_BITS
-
/*
* block/section address mask and size definitions.
*/
#undef PAGE_SIZE
#define PAGE_SHIFT 12
#define PAGE_SIZE (1 << PAGE_SHIFT)
-#define PAGE_MASK (~(PAGE_SIZE-1))
+#define PAGE_MASK (~(PAGE_SIZE - 1))
/***************************************************************/
#ifndef __ASM_ARM_DMA_MAPPING_H
#define __ASM_ARM_DMA_MAPPING_H
-#define dma_mapping_error(x, y) 0
+#include <linux/dma-direction.h>
-enum dma_data_direction {
- DMA_BIDIRECTIONAL = 0,
- DMA_TO_DEVICE = 1,
- DMA_FROM_DEVICE = 2,
-};
+#define dma_mapping_error(x, y) 0
static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
{
/*
* Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
* DDR memory map
*/
#ifdef CONFIG_FSL_LSCH3
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000
-#define CONFIG_BS_ADDR_DEVICE 0x580e00000
-#define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000
-#define CONFIG_BS_ADDR_RAM 0xa0e00000
-#define CONFIG_BS_HDR_SIZE 0x00002000
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_BS_ADDR_DEVICE 0x20600000
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x20640000
+#else /* NOR BOOT */
+#define CONFIG_BS_ADDR_DEVICE 0x580600000
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x580640000
+#endif /*ifdef CONFIG_QSPI_BOOT */
#define CONFIG_BS_SIZE 0x00001000
+#define CONFIG_BS_HDR_SIZE 0x00004000
+#define CONFIG_BS_ADDR_RAM 0xa0600000
+#define CONFIG_BS_HDR_ADDR_RAM 0xa0640000
#else
#ifdef CONFIG_SD_BOOT
/* For SD boot address and size are assigned in terms of sector
* offset and no. of sectors respectively.
*/
-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000920
-#else
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900
-#endif
-#define CONFIG_BS_ADDR_DEVICE 0x00000940
-#define CONFIG_BS_HDR_SIZE 0x00000010
+#define CONFIG_BS_ADDR_DEVICE 0x00003000
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x00003200
#define CONFIG_BS_SIZE 0x00000008
+#define CONFIG_BS_HDR_SIZE 0x00000010
#elif defined(CONFIG_NAND_BOOT)
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
-#define CONFIG_BS_ADDR_DEVICE 0x00802000
-#define CONFIG_BS_HDR_SIZE 0x00002000
-#define CONFIG_BS_SIZE 0x00001000
-#elif defined(CONFIG_QSPI_BOOT)
-#ifdef CONFIG_ARCH_LS1046A
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x40780000
-#define CONFIG_BS_ADDR_DEVICE 0x40800000
-#elif defined(CONFIG_ARCH_LS1012A)
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x400c0000
-#define CONFIG_BS_ADDR_DEVICE 0x40060000
-#else
-#error "Platform not supported"
-#endif
+#define CONFIG_BS_ADDR_DEVICE 0x00600000
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x00640000
+#define CONFIG_BS_SIZE 0x00001000
#define CONFIG_BS_HDR_SIZE 0x00002000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_BS_ADDR_DEVICE 0x40600000
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x40640000
#define CONFIG_BS_SIZE 0x00001000
-#else /* Default NOR Boot */
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000
-#define CONFIG_BS_ADDR_DEVICE 0x60060000
#define CONFIG_BS_HDR_SIZE 0x00002000
+#else /* Default NOR Boot */
+#define CONFIG_BS_ADDR_DEVICE 0x60600000
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x60640000
#define CONFIG_BS_SIZE 0x00001000
+#define CONFIG_BS_HDR_SIZE 0x00002000
#endif
-#define CONFIG_BS_HDR_ADDR_RAM 0x81000000
-#define CONFIG_BS_ADDR_RAM 0x81020000
+#define CONFIG_BS_ADDR_RAM 0x81000000
+#define CONFIG_BS_HDR_ADDR_RAM 0x81020000
#endif
#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
-#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
+#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
#else
#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE
/* BOOTSCRIPT_ADDR is not required */
extern struct prcm_regs const dra7xx_prcm;
extern struct dplls const **dplls_data;
extern struct dplls dra7xx_dplls;
+extern struct dplls dra72x_dplls;
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
extern struct omap_sys_ctrl_regs const **ctrl;
extern struct pmic_data tps659038;
extern struct pmic_data lp8733;
+extern struct pmic_data lp87565;
void hw_data_init(void);
#define DRA7XX 0x07000000
#define DRA72X 0x07200000
+#define DRA76X 0x07600000
static inline u8 is_dra7xx(void)
{
extern u32 *const omap_si_rev;
return (*omap_si_rev & 0xFFF00000) == DRA72X;
}
+
+static inline u8 is_dra76x(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xFFF00000) == DRA76X;
+}
#endif
/*
#define OMAP5432_ES2_0 0x54320200
/* DRA7XX */
+#define DRA762_ES1_0 0x07620100
#define DRA752_ES1_0 0x07520100
#define DRA752_ES1_1 0x07520110
#define DRA752_ES2_0 0x07520200
#define DRA722_ES1_0 0x07220100
#define DRA722_ES2_0 0x07220200
+#define DRA722_ES2_1 0x07220210
/*
* silicon device type
int wp_gpio);
void vmmc_pbias_config(uint voltage);
+void board_mmc_poweron_ldo(uint voltage);
#endif /* OMAP_MMC_H_ */
if ARCH_AT91
+config AT91FAMILY
+ def_bool y
+
+config AT91SAM9260
+ bool
+ select CPU_ARM926EJS
+
+config AT91SAM9G20
+ bool
+ select CPU_ARM926EJS
+
+config AT91SAM9XE
+ bool
+ select CPU_ARM926EJS
+
+config AT91SAM9261
+ bool
+ select CPU_ARM926EJS
+
+config AT91SAM9263
+ bool
+ select CPU_ARM926EJS
+
+config AT91SAM9G45
+ bool
+ select CPU_ARM926EJS
+
+config AT91SAM9M10G45
+ bool
+ select CPU_ARM926EJS
+
+config AT91SAM9N12
+ bool
+ select CPU_ARM926EJS
+
+config AT91SAM9RL
+ bool
+ select CPU_ARM926EJS
+
+config AT91SAM9X5
+ bool
+ select CPU_ARM926EJS
+
+config SAMA5D2
+ bool
+ select CPU_V7
+
+config SAMA5D3
+ bool
+ select CPU_V7
+
+config SAMA5D4
+ bool
+ select CPU_V7
+
choice
prompt "Atmel AT91 board select"
optional
config TARGET_AT91SAM9260EK
bool "Atmel at91sam9260 reference board"
- select CPU_ARM926EJS
+ select AT91SAM9260
select BOARD_EARLY_INIT_F
config TARGET_ETHERNUT5
bool "Ethernut5 board"
- select CPU_ARM926EJS
+ select AT91SAM9XE
config TARGET_SNAPPER9260
bool "Support snapper9260"
- select CPU_ARM926EJS
+ select AT91SAM9260
select DM
select DM_SERIAL
select DM_GPIO
config TARGET_GURNARD
bool "Support gurnard"
+ select AT91SAM9G45
select BOARD_LATE_INIT
- select CPU_ARM926EJS
select DM
select DM_SERIAL
select DM_GPIO
config TARGET_AT91SAM9261EK
bool "Atmel at91sam9261 reference board"
- select CPU_ARM926EJS
+ select AT91SAM9261
select BOARD_EARLY_INIT_F
config TARGET_PM9261
bool "Ronetix pm9261 board"
- select CPU_ARM926EJS
+ select AT91SAM9261
config TARGET_AT91SAM9263EK
bool "Atmel at91sam9263 reference board"
- select CPU_ARM926EJS
+ select AT91SAM9263
select BOARD_EARLY_INIT_F
config TARGET_USB_A9263
bool "Caloa USB A9260 board"
- select CPU_ARM926EJS
+ select AT91SAM9263
config TARGET_PM9263
bool "Ronetix pm9263 board"
- select CPU_ARM926EJS
+ select AT91SAM9263
config TARGET_AT91SAM9M10G45EK
bool "Atmel AT91SAM9M10G45-EK board"
- select CPU_ARM926EJS
+ select AT91SAM9M10G45
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
config TARGET_PM9G45
bool "Ronetix pm9g45 board"
- select CPU_ARM926EJS
+ select AT91SAM9G45
config TARGET_PICOSAM9G45
bool "Mini-box picosam9g45 board"
- select CPU_ARM926EJS
+ select AT91SAM9M10G45
select SUPPORT_SPL
config TARGET_AT91SAM9N12EK
bool "Atmel AT91SAM9N12-EK board"
- select CPU_ARM926EJS
+ select AT91SAM9N12
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
config TARGET_AT91SAM9RLEK
bool "Atmel at91sam9rl reference board"
- select CPU_ARM926EJS
+ select AT91SAM9RL
select BOARD_EARLY_INIT_F
config TARGET_AT91SAM9X5EK
bool "Atmel AT91SAM9X5-EK board"
- select CPU_ARM926EJS
+ select AT91SAM9X5
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
config TARGET_SAMA5D2_PTC
bool "SAMA5D2 PTC board"
- select CPU_V7
+ select SAMA5D2
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
config TARGET_SAMA5D2_XPLAINED
bool "SAMA5D2 Xplained board"
+ select SAMA5D2
+ select SUPPORT_SPL
+ select BOARD_EARLY_INIT_F
+
+config TARGET_SAMA5D27_SOM1_EK
+ bool "SAMA5D27 SOM1 EK board"
select CPU_V7
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ help
+ The SAMA5D27 SOM1 embeds SAMA5D2 SiP(System in Package),
+ a 64Mbit QSPI flash, KSZ8081 Phy and a Mac-address EEPROM
+ 24AA02E48. The SAMA5D2 SiP integrates the ARM Cortex-A5
+ processor-based SAMA5D2 MPU with up to 1 Gbit DDR2-SDRAM
+ in a single package.
config TARGET_SAMA5D3_XPLAINED
bool "SAMA5D3 Xplained board"
- select CPU_V7
+ select SAMA5D3
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
config TARGET_SAMA5D3XEK
bool "SAMA5D3X-EK board"
+ select SAMA5D3
select BOARD_LATE_INIT
- select CPU_V7
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
config TARGET_SAMA5D4_XPLAINED
bool "SAMA5D4 Xplained board"
- select CPU_V7
+ select SAMA5D4
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
config TARGET_SAMA5D4EK
bool "SAMA5D4 Evaluation Kit"
- select CPU_V7
+ select SAMA5D4
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
config TARGET_MA5D4EVK
bool "Aries MA5D4EVK Evaluation Kit"
- select CPU_V7
+ select SAMA5D4
select SUPPORT_SPL
config TARGET_MEESC
bool "Support meesc"
- select CPU_ARM926EJS
+ select AT91SAM9263
config TARGET_CORVUS
bool "Support corvus"
- select CPU_ARM926EJS
+ select AT91SAM9M10G45
select SUPPORT_SPL
select DM
select DM_SERIAL
config TARGET_TAURUS
bool "Support taurus"
- select CPU_ARM926EJS
+ select AT91SAM9G20
select SUPPORT_SPL
select DM
select DM_SERIAL
config TARGET_SMARTWEB
bool "Support smartweb"
- select CPU_ARM926EJS
+ select AT91SAM9260
select SUPPORT_SPL
select DM
select DM_SERIAL
config TARGET_VINCO
bool "Support VINCO"
- select CPU_V7
+ select SAMA5D4
select SUPPORT_SPL
endchoice
source "board/atmel/at91sam9x5ek/Kconfig"
source "board/atmel/sama5d2_ptc/Kconfig"
source "board/atmel/sama5d2_xplained/Kconfig"
+source "board/atmel/sama5d27_som1_ek/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
;
}
+/*
+ * For the Master Clock Controller Register(MCKR), while switching
+ * to a lower clock source, we must switch the clock source first
+ * instead of last. Otherwise, we could end up with too high frequency
+ * on the internal bus and peripherals.
+ */
+void at91_mck_init_down(u32 mckr)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ u32 tmp;
+
+ tmp = readl(&pmc->mckr);
+ tmp &= (~AT91_PMC_MCKR_CSS_MASK);
+ tmp |= (mckr & AT91_PMC_MCKR_CSS_MASK);
+ writel(tmp, &pmc->mckr);
+
+ while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+ ;
+
+#ifdef CPU_HAS_H32MXDIV
+ tmp = readl(&pmc->mckr);
+ tmp &= (~AT91_PMC_MCKR_H32MXDIV);
+ tmp |= (mckr & AT91_PMC_MCKR_H32MXDIV);
+ writel(tmp, &pmc->mckr);
+#endif
+
+ tmp = readl(&pmc->mckr);
+ tmp &= (~AT91_PMC_MCKR_PLLADIV_MASK);
+ tmp |= (mckr & AT91_PMC_MCKR_PLLADIV_MASK);
+ writel(tmp, &pmc->mckr);
+
+ tmp = readl(&pmc->mckr);
+ tmp &= (~AT91_PMC_MCKR_MDIV_MASK);
+ tmp |= (mckr & AT91_PMC_MCKR_MDIV_MASK);
+ writel(tmp, &pmc->mckr);
+
+ tmp = readl(&pmc->mckr);
+ tmp &= (~AT91_PMC_MCKR_PRES_MASK);
+ tmp |= (mckr & AT91_PMC_MCKR_PRES_MASK);
+ writel(tmp, &pmc->mckr);
+}
+
int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
#include <asm/arch/clk.h>
#include <asm/arch/sama5d2.h>
-char *get_cpu_name()
+int cpu_is_sama5d2(void)
{
+ unsigned int chip_id = get_chip_id();
+
+ return ((chip_id == ARCH_ID_SAMA5D2) ||
+ (chip_id == ARCH_ID_SAMA5D2_SIP)) ? 1 : 0;
+}
+
+char *get_cpu_name(void)
+{
+ unsigned int chip_id = get_chip_id();
unsigned int extension_id = get_extension_chip_id();
- if (cpu_is_sama5d2()) {
+ if (chip_id == ARCH_ID_SAMA5D2) {
switch (extension_id) {
case ARCH_EXID_SAMA5D21CU:
return "SAMA5D21";
}
}
+ if ((chip_id == ARCH_ID_SAMA5D2) || (chip_id == ARCH_ID_SAMA5D2_SIP)) {
+ switch (extension_id) {
+ case ARCH_EXID_SAMA5D225C_D1M:
+ return "SAMA5D225 128M bits DDR2 SDRAM";
+ case ARCH_EXID_SAMA5D27C_D5M:
+ return "SAMA5D27 512M bits DDR2 SDRAM";
+ case ARCH_EXID_SAMA5D27C_D1G:
+ return "SAMA5D27 1G bits DDR2 SDRAM";
+ case ARCH_EXID_SAMA5D28C_D1G:
+ return "SAMA5D28 1G bits DDR2 SDRAM";
+ }
+ }
+
return "Unknown CPU type";
}
*/
#include <common.h>
+#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/arch/sama5_sfr.h>
void at91_plla_init(u32 pllar);
void at91_pllb_init(u32 pllar);
void at91_mck_init(u32 mckr);
+void at91_mck_init_down(u32 mckr);
void at91_pmc_init(void);
void mem_init(void);
void at91_phy_reset(void);
void redirect_int_from_saic_to_aic(void);
void configure_2nd_sram_as_l2_cache(void);
+int at91_set_ethaddr(int offset);
+int at91_video_show_board_info(void);
+
#endif /* AT91_COMMON_H */
#define AT91_PMC_MCFR_MAINRDY 0x00010000
#define AT91_PMC_MCFR_MAINF_MASK 0x0000FFFF
+#define AT91_PMC_MCFR_RCMEAS 0x00100000
+#define AT91_PMC_MCFR_CCSS_XTAL_OSC 0x01000000
#define AT91_PMC_MCKR_CSS_SLOW 0x00000000
#define AT91_PMC_MCKR_CSS_MAIN 0x00000001
#ifndef __AT91RM9200_H__
#define __AT91RM9200_H__
-#define CONFIG_AT91FAMILY /* it's a member of AT91 family */
#define CONFIG_ARCH_CPU_INIT /* we need arch_cpu_init() for hw timers */
#define CONFIG_AT91_GPIO /* and require always gpio features */
#ifndef AT91SAM9260_H
#define AT91SAM9260_H
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY /* it's a member of AT91 */
-
/*
* Peripheral identifiers/interrupts.
*/
#ifndef AT91SAM9261_H
#define AT91SAM9261_H
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY /* it's a member of AT91 */
-
/*
* Peripheral identifiers/interrupts.
*/
#ifndef AT91SAM9263_H
#define AT91SAM9263_H
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY /* it's a member of AT91 */
-
/*
* Peripheral identifiers/interrupts.
*/
#ifndef AT91SAM9G45_H
#define AT91SAM9G45_H
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY /* it's a member of AT91 */
-
/*
* Peripheral identifiers/interrupts.
*/
#ifndef AT91SAM9RL_H
#define AT91SAM9RL_H
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY /* it's a member of AT91 */
-
/*
* Peripheral identifiers/interrupts.
*/
#ifndef __AT91SAM9X5_H__
#define __AT91SAM9X5_H__
-#define CONFIG_AT91FAMILY /* it's a member of AT91 family */
-
/*
* Peripheral identifiers/interrupts.
*/
#define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7)
#define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8)
#define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9)
+#define ATMEL_MPDDRC_CR_ZQ_INIT (0x0 << 10)
+#define ATMEL_MPDDRC_CR_ZQ_LONG (0x1 << 10)
+#define ATMEL_MPDDRC_CR_ZQ_SHORT (0x2 << 10)
+#define ATMEL_MPDDRC_CR_ZQ_RESET (0x3 << 10)
#define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12)
#define ATMEL_MPDDRC_CR_DQMS_SHARED (0x1 << 16)
#define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17)
u32 l2cc_hramc; /* 0x58 */
};
+/* Register Mapping*/
+#define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */
+
/* Bit field in DDRCFG */
#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000
#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
#define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12)
#define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12)
+#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)
+
/* Bit field in AICREDIR */
#define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
#ifndef __SAMA5D2_H
#define __SAMA5D2_H
-/*
- * definitions to be used in other places
- */
-#define CONFIG_AT91FAMILY /* It's a member of AT91 */
-
/*
* Peripheral identifiers/interrupts.
*/
#define ARCH_EXID_SAMA5D28CU 0x00000010
#define ARCH_EXID_SAMA5D28CN 0x00000020
-#define cpu_is_sama5d2() (get_chip_id() == ARCH_ID_SAMA5D2)
+#define ARCH_ID_SAMA5D2_SIP 0x8a5c08c2
+#define ARCH_EXID_SAMA5D225C_D1M 0x00000053
+#define ARCH_EXID_SAMA5D27C_D5M 0x00000032
+#define ARCH_EXID_SAMA5D27C_D1G 0x00000033
+#define ARCH_EXID_SAMA5D28C_D1G 0x00000013
/* PIT Timer(PIT_PIIR) */
#define CONFIG_SYS_TIMER_COUNTER 0xf804803c
#ifndef __ASSEMBLY__
unsigned int get_chip_id(void);
unsigned int get_extension_chip_id(void);
+int cpu_is_sama5d2(void);
unsigned int has_lcdc(void);
char *get_cpu_name(void);
#endif
#ifndef SAMA5D3_H
#define SAMA5D3_H
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY /* it's a member of AT91 */
-
/*
* Peripheral identifiers/interrupts.
*/
#ifndef __SAMA5D4_H
#define __SAMA5D4_H
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY /* It's a member of AT91 */
-
/*
* Peripheral identifiers/interrupts.
*/
*/
#include <common.h>
+#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/arch/sama5_matrix.h>
*/
#include <common.h>
+#include <asm/hardware.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <asm/arch/at91_rstc.h>
u32 off = (bootrom_stash.r4 >> ATMEL_SAMA5_BOOT_DEV_ID_OFF) &
ATMEL_SAMA5_BOOT_DEV_ID_MASK;
-#if defined(CONFIG_SYS_USE_MMC)
+#if defined(CONFIG_SYS_USE_MMC) || defined(CONFIG_SD_BOOT)
if (dev == ATMEL_SAMA5_BOOT_FROM_MCI) {
#if defined(CONFIG_SPL_OF_CONTROL)
return BOOT_DEVICE_MMC1;
}
#endif
-#if defined(CONFIG_SYS_USE_SERIALFLASH) || defined(CONFIG_SYS_USE_SPIFLASH)
+#if defined(CONFIG_SYS_USE_SERIALFLASH) || \
+ defined(CONFIG_SYS_USE_SPIFLASH) || \
+ defined(CONFIG_SPI_BOOT)
if (dev == ATMEL_SAMA5_BOOT_FROM_SPI)
return BOOT_DEVICE_SPI;
#endif
+ if (dev == ATMEL_SAMA5_BOOT_FROM_QSPI)
+ return BOOT_DEVICE_SPI;
if (dev == ATMEL_SAMA5_BOOT_FROM_SMC)
return BOOT_DEVICE_NAND;
#else
u32 spl_boot_device(void)
{
-#ifdef CONFIG_SYS_USE_MMC
+#if defined(CONFIG_SYS_USE_MMC) || defined(CONFIG_SD_BOOT)
return BOOT_DEVICE_MMC1;
-#elif CONFIG_SYS_USE_NANDFLASH
+#elif defined(CONFIG_SYS_USE_NANDFLASH) || defined(CONFIG_NAND_BOOT)
return BOOT_DEVICE_NAND;
-#elif CONFIG_SYS_USE_SERIALFLASH || CONFIG_SYS_USE_SPIFLASH
+#elif defined(CONFIG_SYS_USE_SERIALFLASH) || \
+ defined(CONFIG_SYS_USE_SPIFLASH) || \
+ defined(CONFIG_SPI_BOOT)
return BOOT_DEVICE_SPI;
#endif
return BOOT_DEVICE_NONE;
u32 spl_boot_mode(const u32 boot_device)
{
switch (boot_device) {
-#ifdef CONFIG_SYS_USE_MMC
+#if defined(CONFIG_SYS_USE_MMC) || defined(CONFIG_SD_BOOT)
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
return MMCSD_MODE_FS;
while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS))
;
+#if defined(CONFIG_SAMA5D2)
+ /* Enable a measurement of the external oscillator */
+ tmp = readl(&pmc->mcfr);
+ tmp |= AT91_PMC_MCFR_CCSS_XTAL_OSC;
+ tmp |= AT91_PMC_MCFR_RCMEAS;
+ writel(tmp, &pmc->mcfr);
+
+ while (!(readl(&pmc->mcfr) & AT91_PMC_MCFR_MAINRDY))
+ ;
+
+ if (!(readl(&pmc->mcfr) & AT91_PMC_MCFR_MAINF_MASK))
+ hang();
+#endif
+
tmp = readl(&pmc->mor);
tmp &= ~AT91_PMC_MOR_OSCBYPASS;
tmp &= ~AT91_PMC_MOR_KEY(0xff);
while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCSELS))
;
+#if !defined(CONFIG_SAMA5D2)
/* Wait until MAINRDY field is set to make sure main clock is stable */
while (!(readl(&pmc->mcfr) & AT91_PMC_MAINRDY))
;
+#endif
-#ifndef CONFIG_SAMA5D4
+#if !defined(CONFIG_SAMA5D4) && !defined(CONFIG_SAMA5D2)
tmp = readl(&pmc->mor);
tmp &= ~AT91_PMC_MOR_MOSCRCEN;
tmp &= ~AT91_PMC_MOR_KEY(0xff);
obj-$(CONFIG_SOC_DM365) += dm365.o
obj-$(CONFIG_SOC_DM644X) += dm644x.o
obj-$(CONFIG_SOC_DM646X) += dm646x.o
-obj-$(CONFIG_SOC_DA830) += da830_pinmux.o
obj-$(CONFIG_SOC_DA850) += da850_pinmux.o
obj-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o
+++ /dev/null
-/*
- * Pinmux configurations for the DA830 SoCs
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pinmux_defs.h>
-
-/* SPI0 pin muxer settings */
-const struct pinmux_config spi0_pins_base[] = {
- { pinmux(7), 1, 3 }, /* SPI0_SOMI */
- { pinmux(7), 1, 4 }, /* SPI0_SIMO */
- { pinmux(7), 1, 6 } /* SPI0_CLK */
-};
-
-const struct pinmux_config spi0_pins_scs0[] = {
- { pinmux(7), 1, 7 } /* SPI0_SCS[0] */
-};
-
-const struct pinmux_config spi0_pins_ena[] = {
- { pinmux(7), 1, 5 } /* SPI0_ENA */
-};
-
-/* NAND pin muxer settings */
-const struct pinmux_config emifa_pins_cs0[] = {
- { pinmux(18), 1, 2 } /* EMA_CS[0] */
-};
-
-const struct pinmux_config emifa_pins_cs2[] = {
- { pinmux(18), 1, 3 } /* EMA_CS[2] */
-};
-
-const struct pinmux_config emifa_pins_cs3[] = {
- { pinmux(18), 1, 4 } /* EMA_CS[3] */
-};
-
-#ifdef CONFIG_USE_NAND
-const struct pinmux_config emifa_pins[] = {
- { pinmux(13), 1, 6 }, /* EMA_D[0] */
- { pinmux(13), 1, 7 }, /* EMA_D[1] */
- { pinmux(14), 1, 0 }, /* EMA_D[2] */
- { pinmux(14), 1, 1 }, /* EMA_D[3] */
- { pinmux(14), 1, 2 }, /* EMA_D[4] */
- { pinmux(14), 1, 3 }, /* EMA_D[5] */
- { pinmux(14), 1, 4 }, /* EMA_D[6] */
- { pinmux(14), 1, 5 }, /* EMA_D[7] */
- { pinmux(14), 1, 6 }, /* EMA_D[8] */
- { pinmux(14), 1, 7 }, /* EMA_D[9] */
- { pinmux(15), 1, 0 }, /* EMA_D[10] */
- { pinmux(15), 1, 1 }, /* EMA_D[11] */
- { pinmux(15), 1, 2 }, /* EMA_D[12] */
- { pinmux(15), 1, 3 }, /* EMA_D[13] */
- { pinmux(15), 1, 4 }, /* EMA_D[14] */
- { pinmux(15), 1, 5 }, /* EMA_D[15] */
- { pinmux(15), 1, 6 }, /* EMA_A[0] */
- { pinmux(15), 1, 7 }, /* EMA_A[1] */
- { pinmux(16), 1, 0 }, /* EMA_A[2] */
- { pinmux(16), 1, 1 }, /* EMA_A[3] */
- { pinmux(16), 1, 2 }, /* EMA_A[4] */
- { pinmux(16), 1, 3 }, /* EMA_A[5] */
- { pinmux(16), 1, 4 }, /* EMA_A[6] */
- { pinmux(16), 1, 5 }, /* EMA_A[7] */
- { pinmux(16), 1, 6 }, /* EMA_A[8] */
- { pinmux(16), 1, 7 }, /* EMA_A[9] */
- { pinmux(17), 1, 0 }, /* EMA_A[10] */
- { pinmux(17), 1, 1 }, /* EMA_A[11] */
- { pinmux(17), 1, 2 }, /* EMA_A[12] */
- { pinmux(17), 1, 3 }, /* EMA_BA[1] */
- { pinmux(17), 1, 4 }, /* EMA_BA[0] */
- { pinmux(17), 1, 5 }, /* EMA_CLK */
- { pinmux(17), 1, 6 }, /* EMA_SDCKE */
- { pinmux(17), 1, 7 }, /* EMA_CAS */
- { pinmux(18), 1, 0 }, /* EMA_CAS */
- { pinmux(18), 1, 1 }, /* EMA_WE */
- { pinmux(18), 1, 5 }, /* EMA_OE */
- { pinmux(18), 1, 6 }, /* EMA_WE_DQM[1] */
- { pinmux(18), 1, 7 }, /* EMA_WE_DQM[0] */
- { pinmux(10), 1, 0 } /* Tristate */
-};
-#endif
-
-/* EMAC PHY interface pins */
-const struct pinmux_config emac_pins_rmii[] = {
- { pinmux(10), 2, 1 }, /* RMII_TXD[0] */
- { pinmux(10), 2, 2 }, /* RMII_TXD[1] */
- { pinmux(10), 2, 3 }, /* RMII_TXEN */
- { pinmux(10), 2, 4 }, /* RMII_CRS_DV */
- { pinmux(10), 2, 5 }, /* RMII_RXD[0] */
- { pinmux(10), 2, 6 }, /* RMII_RXD[1] */
- { pinmux(10), 2, 7 } /* RMII_RXER */
-};
-
-const struct pinmux_config emac_pins_mdio[] = {
- { pinmux(11), 2, 0 }, /* MDIO_CLK */
- { pinmux(11), 2, 1 } /* MDIO_D */
-};
-
-const struct pinmux_config emac_pins_rmii_clk_source[] = {
- { pinmux(9), 0, 5 } /* ref.clk from external source */
-};
-
-/* UART2 pin muxer settings */
-const struct pinmux_config uart2_pins_txrx[] = {
- { pinmux(8), 2, 7 }, /* UART2_RXD */
- { pinmux(9), 2, 0 } /* UART2_TXD */
-};
-
-/* I2C0 pin muxer settings */
-const struct pinmux_config i2c0_pins[] = {
- { pinmux(8), 2, 3 }, /* I2C0_SDA */
- { pinmux(8), 2, 4 } /* I2C0_SCL */
-};
-
-/* USB0_DRVVBUS pin muxer settings */
-const struct pinmux_config usb_pins[] = {
- { pinmux(9), 1, 1 } /* USB0_DRVVBUS */
-};
-
-#ifdef CONFIG_MMC_DAVINCI
-/* MMC0 pin muxer settings */
-const struct pinmux_config mmc0_pins_8bit[] = {
- { pinmux(15), 2, 7 }, /* MMCSD0_CLK */
- { pinmux(16), 2, 0 }, /* MMCSD0_CMD */
- { pinmux(13), 2, 6 }, /* MMCSD0_DAT_0 */
- { pinmux(13), 2, 7 }, /* MMCSD0_DAT_1 */
- { pinmux(14), 2, 0 }, /* MMCSD0_DAT_2 */
- { pinmux(14), 2, 1 }, /* MMCSD0_DAT_3 */
- { pinmux(14), 2, 2 }, /* MMCSD0_DAT_4 */
- { pinmux(14), 2, 3 }, /* MMCSD0_DAT_5 */
- { pinmux(14), 2, 4 }, /* MMCSD0_DAT_6 */
- { pinmux(14), 2, 5 } /* MMCSD0_DAT_7 */
- /* DA830 supports 8-bit mode */
-};
-#endif
clock_enable(CCGR_ENET2, 0);
switch (type) {
- case ENET_125MHz:
+ case ENET_125MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
break;
- case ENET_50MHz:
+ case ENET_50MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
break;
- case ENET_25MHz:
+ case ENET_25MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
break;
#include <asm/spl.h>
#include <spl.h>
#include <asm/mach-imx/hab.h>
+#include <g_dnl.h>
DECLARE_GLOBAL_DATA_PTR;
if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
return BOOT_DEVICE_BOARD;
+ /*
+ * The above method does not detect that the boot ROM used
+ * serial downloader in case the boot ROM decided to use the
+ * serial downloader as a fall back (primary boot source failed).
+ *
+ * Infer that the boot ROM used the USB serial downloader by
+ * checking whether the USB PHY is currently active... This
+ * assumes that SPL did not (yet) initialize the USB PHY...
+ */
+ if (is_usbotg_phy_active())
+ return BOOT_DEVICE_BOARD;
+
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
switch ((reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
/* EIM: See 8.5.1, Table 8-9 */
}
return BOOT_DEVICE_NONE;
}
+
+#ifdef CONFIG_SPL_USB_GADGET_SUPPORT
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+ put_unaligned(CONFIG_G_DNL_PRODUCT_NUM + 0xfff, &dev->idProduct);
+
+ return 0;
+}
+#endif
#endif
#if defined(CONFIG_SPL_MMC_SUPPORT)
select DM
select DM_SERIAL
select DM_GPIO
+ select OMAP3_GPIO_3
select OMAP3_GPIO_4
select OMAP3_GPIO_6
endchoice
+choice
+ prompt "Memory Controller"
+ default SDRC
+
+config SDRC
+ bool "SDRC controller"
+ help
+ The default memory controller on most OMAP3 boards is SDRC.
+
+config EMIF4
+ bool "EMIF4 controller"
+ help
+ Enable this on boards like AM3517 which use EMIF4 controller
+endchoice
+
config SPL_OMAP3_ID_NAND
bool "Support OMAP3-specific ID and MFR function"
help
select TI_I2C_BOARD_DETECT
select PHYS_64BIT
imply SCSI
+ imply DM_PMIC
+ imply PMIC_LP87565
+ imply DM_REGULATOR
+ imply DM_REGULATOR_LP87565
config TARGET_AM57XX_EVM
bool "AM57XX"
{10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
};
+static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = {
+ {32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 12 MHz */
+ {96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 20 MHz */
+ {160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 16.8 MHz */
+ {20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 19.2 MHz */
+ {192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 38.4 MHz */
+};
+
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
.ddr = NULL
};
+struct dplls dra76x_dplls = {
+ .mpu = mpu_dpll_params_1ghz,
+ .core = core_dpll_params_2128mhz_dra7xx,
+ .per = per_dpll_params_768mhz_dra76x,
+ .abe = abe_dpll_params_sysclk2_361267khz,
+ .iva = iva_dpll_params_2330mhz_dra7xx,
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = ddr_dpll_params_2664mhz,
+ .gmac = gmac_dpll_params_2000mhz,
+};
+
struct dplls dra7xx_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_dra7xx,
.gpio_en = 0,
};
+/* The LP87565*/
+struct pmic_data lp87565 = {
+ .base_offset = LP873X_BUCK_BASE_VOLT_UV,
+ .step = 5000, /* 5 mV represented in uV */
+ /*
+ * Offset codes 0 - 0x13 Invalid.
+ * Offset codes 0x14 0x17 give 10mV steps
+ * Offset codes 0x17 through 0x9D give 5mV steps
+ * So let us start with our operating range from .73V
+ */
+ .start_code = 0x17,
+ .i2c_slave_addr = 0x60,
+ .pmic_bus_init = gpi2c_init,
+ .pmic_write = palmas_i2c_write_u8,
+};
+
/* The LP8732 and LP8733 are software-compatible, use common struct */
struct pmic_data lp8733 = {
.base_offset = LP873X_BUCK_BASE_VOLT_UV,
*ctrl = &omap5_ctrl;
break;
+ case DRA762_ES1_0:
+ *prcm = &dra7xx_prcm;
+ *dplls_data = &dra76x_dplls;
+ *ctrl = &dra7xx_ctrl;
+ break;
+
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
case DRA722_ES1_0:
case DRA722_ES2_0:
+ case DRA722_ES2_1:
*prcm = &dra7xx_prcm;
*dplls_data = &dra72x_dplls;
*ctrl = &dra7xx_ctrl;
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
+ case DRA762_ES1_0:
*regs = &ioregs_dra7xx_es1;
break;
case DRA722_ES1_0:
*regs = &ioregs_dra72x_es1;
break;
case DRA722_ES2_0:
+ case DRA722_ES2_1:
*regs = &ioregs_dra72x_es2;
break;
case OMAP5432_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = OMAP5432_ES2_0;
break;
+ case DRA762_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = DRA762_ES1_0;
+ break;
case DRA752_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = DRA752_ES1_0;
break;
case DRA722_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = DRA722_ES2_0;
break;
+ case DRA722_CONTROL_ID_CODE_ES2_1:
+ *omap_si_rev = DRA722_ES2_1;
+ break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}
}
#if defined(CONFIG_PALMAS_POWER)
+__weak void board_mmc_poweron_ldo(uint voltage)
+{
+ palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
+}
+
void vmmc_pbias_config(uint voltage)
{
u32 value = 0;
- struct vcores_data const *vcores = *omap_vcores;
value = readl((*ctrl)->control_pbias);
value &= ~SDCARD_PWRDNZ;
value &= ~SDCARD_BIAS_PWRDNZ;
writel(value, (*ctrl)->control_pbias);
- if (vcores->core.pmic->i2c_slave_addr == 0x60) {
- if (voltage == LDO_VOLT_3V0)
- voltage = 0x19;
- else if (voltage == LDO_VOLT_1V8)
- voltage = 0xa;
- lp873x_mmc1_poweron_ldo(voltage);
- } else {
- palmas_mmc1_poweron_ldo(voltage);
- }
+ board_mmc_poweron_ldo(voltage);
value = readl((*ctrl)->control_pbias);
value |= SDCARD_BIAS_PWRDNZ;
*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
break;
+ case DRA762_ES1_0:
case DRA722_ES2_0:
+ case DRA722_ES2_1:
*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
break;
*iterations = sizeof(omap5_bug_00339_regs)/
sizeof(omap5_bug_00339_regs[0]);
break;
+ case DRA762_ES1_0:
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
case DRA722_ES1_0:
case DRA722_ES2_0:
+ case DRA722_ES2_1:
bug_00339_regs_ptr = dra_bug_00339_regs;
*iterations = sizeof(dra_bug_00339_regs)/
sizeof(dra_bug_00339_regs[0]);
if ((hdr->magic != OPTEE_MAGIC) ||
(hdr->version != OPTEE_VERSION) ||
- (hdr->init_load_addr_hi != 0) ||
- (hdr->init_load_addr_lo < (sec_mem_start + sizeof(struct optee_header))) ||
- (tee_file_size > size) ||
- ((hdr->init_load_addr_lo + tee_file_size - 1) >
- (sec_mem_start + size - 1))) {
- printf("Error in TEE header. Check load address and sizes\n");
+ (tee_file_size > size)) {
+ printf("Error in TEE header. Check firewall and TEE sizes\n");
unmap_sysmem(hdr);
return CMD_RET_FAILURE;
}
#include <clk.h>
#include <dm.h>
#include <ram.h>
+#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
CON_IOMUX_UART2SEL_MASK,
CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
+ /*
+ * The integrated macphy is enabled by default, disable it
+ * for saving power consuming.
+ */
+ rk_clrsetreg(&grf->macphy_con[0],
+ MACPHY_CFG_ENABLE_MASK,
+ 0 << MACPHY_CFG_ENABLE_SHIFT);
+
return 0;
}
return 0;
}
#endif
+
+#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
+int fb_set_reboot_flag(void)
+{
+ struct rk322x_grf *grf;
+
+ printf("Setting reboot to fastboot flag ...\n");
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ /* Set boot mode to fastboot */
+ writel(BOOT_FASTBOOT, &grf->os_reg[0]);
+
+ return 0;
+}
+#endif
2GB DDR3. Expansion connectors provide access to I2C, SPI, UART,
GPIOs and display interface.
+config TARGET_VYASA_RK3288
+ bool "Vyasa-RK3288"
+ select BOARD_LATE_INIT
+ help
+ Vyasa is a RK3288-based development board with 2 USB ports,
+ HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
+ also includes on-board eMMC and 2GB of SDRAM. Expansion connectors
+ provide access to display pins, I2C, SPI, UART and GPIOs.
+
config TARGET_ROCK2
bool "Radxa Rock 2"
select BOARD_LATE_INIT
config SPL_SERIAL_SUPPORT
default y
+source "board/amarula/vyasa-rk3288/Kconfig"
+
source "board/chipspark/popmetal_rk3288/Kconfig"
source "board/firefly/firefly-rk3288/Kconfig"
*/
#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <ram.h>
-#include <spl.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3399.h>
#include <asm/arch/hardware.h>
#include <asm/arch/periph.h>
-#include <asm/arch/sdram.h>
-#include <asm/arch/timer.h>
+#include <asm/io.h>
+#include <debug_uart.h>
+#include <dm.h>
#include <dm/pinctrl.h>
-#include <power/regulator.h>
+#include <ram.h>
+#include <spl.h>
+#include <syscon.h>
DECLARE_GLOBAL_DATA_PTR;
void board_debug_uart_init(void)
{
-#include <asm/arch/grf_rk3399.h>
#define GRF_BASE 0xff770000
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
#endif
}
-#define GRF_EMMCCORE_CON11 0xff77f02c
-#define SGRF_DDR_RGN_CON16 0xff330040
-#define SGRF_SLV_SECURE_CON4 0xff33e3d0
void board_init_f(ulong dummy)
{
struct udevice *pinctrl;
struct udevice *dev;
+ struct rk3399_pmusgrf_regs *sgrf;
+ struct rk3399_grf_regs *grf;
int ret;
#define EARLY_UART
printascii("U-Boot SPL board init");
#endif
- /* Emmc clock generator: disable the clock multipilier */
- rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
-
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
* driver, which tries to DMA from/to the stack (likely)
* located in this range.
*/
- rk_clrsetreg(SGRF_DDR_RGN_CON16, 0x1FF, 0);
- rk_clrreg(SGRF_SLV_SECURE_CON4, 0x2000);
+ sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
+ rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
+ rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
+
+ /* eMMC clock generator: disable the clock multipilier */
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrreg(&grf->emmccore_con[11], 0x0ff);
secure_timer_init();
int ret;
ret = regmap_init_mem_platdata(dev, dtplat->reg,
- ARRAY_SIZE(dtplat->reg) / 4,
+ ARRAY_SIZE(dtplat->reg) / 2,
&plat->map);
if (ret)
return ret;
config->name = ofnode_get_name(node);
- for (subnode = ofnode_first_subnode(node);
- ofnode_valid(subnode);
- subnode = ofnode_next_subnode(subnode)) {
+ ofnode_for_each_subnode(subnode, node) {
struct tegra_xusb_padctl_group *group;
int err;
return err;
}
- for (subnode = ofnode_first_subnode(node);
- ofnode_valid(subnode);
- subnode = ofnode_next_subnode(subnode)) {
+ ofnode_for_each_subnode(subnode, node) {
struct tegra_xusb_padctl_config *config = &padctl->config;
debug("%s: subnode=%s\n", __func__, ofnode_get_name(subnode));
choice
prompt "UniPhier SoC select"
- default ARCH_UNIPHIER_PRO4
+ default ARCH_UNIPHIER_V8_MULTI
config ARCH_UNIPHIER_LD4_SLD8
bool "UniPhier LD4/sLD8 SoCs"
select ARCH_UNIPHIER_32BIT
-config ARCH_UNIPHIER_PRO4
- bool "UniPhier Pro4 SoC"
- select ARCH_UNIPHIER_32BIT
-
-config ARCH_UNIPHIER_PRO5_PXS2_LD6B
- bool "UniPhier Pro5/PXs2/LD6b SoCs"
+config ARCH_UNIPHIER_V7_MULTI
+ bool "UniPhier Pro4/Pro5/PXs2/LD6b SoCs"
select ARCH_UNIPHIER_32BIT
config ARCH_UNIPHIER_V8_MULTI
depends on ARCH_UNIPHIER_LD4_SLD8
default y
+config ARCH_UNIPHIER_PRO4
+ bool "Enable UniPhier Pro4 SoC support"
+ depends on ARCH_UNIPHIER_V7_MULTI
+ default y
+
config ARCH_UNIPHIER_PRO5
bool "Enable UniPhier Pro5 SoC support"
- depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
+ depends on ARCH_UNIPHIER_V7_MULTI
default y
config ARCH_UNIPHIER_PXS2
bool "Enable UniPhier Pxs2 SoC support"
- depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
+ depends on ARCH_UNIPHIER_V7_MULTI
default y
config ARCH_UNIPHIER_LD6B
bool "Enable UniPhier LD6b SoC support"
- depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
+ depends on ARCH_UNIPHIER_V7_MULTI
default y
config ARCH_UNIPHIER_LD11
int ch;
tmp = readl(SC_CLKCTRL4);
- tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC;
+ tmp |= BIT(10) | BIT(8); /* MIO, STDMAC */
writel(tmp, SC_CLKCTRL4);
for (ch = 0; ch < 3; ch++) {
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <linux/bitops.h>
#include <linux/io.h>
#include "../init.h"
+#include "../sc64-regs.h"
#define SDCTRL_EMMC_HW_RESET 0x59810280
void uniphier_ld20_clk_init(void)
{
+ u32 tmp;
+
+ tmp = readl(SC_RSTCTRL6);
+ tmp |= BIT(8); /* Mali */
+ writel(tmp, SC_RSTCTRL6);
+
+ tmp = readl(SC_CLKCTRL6);
+ tmp |= BIT(8); /* Mali */
+ writel(tmp, SC_CLKCTRL6);
+
/* TODO: use "mmc-pwrseq-emmc" */
writel(1, SDCTRL_EMMC_HW_RESET);
}
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <linux/bitops.h>
#include <linux/io.h>
#include "../init.h"
+#include "../sc64-regs.h"
#define SDCTRL_EMMC_HW_RESET 0x59810280
void uniphier_pxs3_clk_init(void)
{
+ u32 tmp;
+
+ tmp = readl(SC_RSTCTRL6);
+ tmp |= BIT(8); /* Mali */
+ writel(tmp, SC_RSTCTRL6);
+
+ tmp = readl(SC_CLKCTRL6);
+ tmp |= BIT(8); /* Mali */
+ writel(tmp, SC_CLKCTRL6);
+
/* TODO: use "mmc-pwrseq-emmc" */
writel(1, SDCTRL_EMMC_HW_RESET);
}
#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
-#define SC_RSTCTRL4_ETHER (1 << 6)
-#define SC_RSTCTRL4_NAND (1 << 0)
#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
#define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018)
-#define SC_RSTCTRL7_UMCSB (1 << 16)
-#define SC_RSTCTRL7_UMCA2 (1 << 10)
-#define SC_RSTCTRL7_UMCA1 (1 << 9)
-#define SC_RSTCTRL7_UMCA0 (1 << 8)
-#define SC_RSTCTRL7_UMC32 (1 << 2)
-#define SC_RSTCTRL7_UMC31 (1 << 1)
-#define SC_RSTCTRL7_UMC30 (1 << 0)
#define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
#define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108)
#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
-#define SC_CLKCTRL4_MIO (1 << 10)
-#define SC_CLKCTRL4_STDMAC (1 << 8)
-#define SC_CLKCTRL4_PERI (1 << 7)
-#define SC_CLKCTRL4_ETHER (1 << 6)
-#define SC_CLKCTRL4_NAND (1 << 0)
#define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110)
#define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114)
#define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118)
-#define SC_CLKCTRL7_UMCSB (1 << 16)
-#define SC_CLKCTRL7_UMC32 (1 << 2)
-#define SC_CLKCTRL7_UMC31 (1 << 1)
-#define SC_CLKCTRL7_UMC30 (1 << 0)
#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000)
#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004)
/* set IVIC, vector size: 4 bytes, base: 0x0 */
mtsr $r0, $ivb
/*
- * MMU_CTL NTC0 Cacheable/Write-Back
+ * MMU_CTL NTC0 Non-cacheable
*/
+ li $r0, ~0x6
+ mfsr $r1, $mr0
+ and $r1, $r1, $r0
+ mtsr $r1, $mr0
+
li $r0, ~0x3
mfsr $r1, $mr8
and $r1, $r1, $r0
mtsr $r1, $mr8
#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
+/*
+ * MMU_CTL NTC0 Cacheable/Write-Back
+ */
li $r0, 0x4
mfsr $r1, $mr0
or $r1, $r1, $r0
mtsr $r1, $mr0
#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+#ifdef CONFIG_ARCH_MAP_SYSMEM
+/*
+ * MMU_CTL NTC1 Non-cacheable
+ */
+ li $r0, ~0x18
+ mfsr $r1, $mr0
+ and $r1, $r1, $r0
+ mtsr $r1, $mr0
+/*
+ * MMU_CTL NTM1 mapping for partition 0
+ */
+ li $r0, ~0x6000
+ mfsr $r1, $mr0
+ and $r1, $r1, $r0
+ mtsr $r1, $mr0
+#endif
+#endif
+
#if !defined(CONFIG_SYS_ICACHE_OFF)
li $r0, 0x1
mfsr $r1, $mr8
aliases {
uart0 = &serial0;
ethernet0 = &mac0;
+ spi0 = &spi;
} ;
chosen {
reg = <0x00000000 0x40000000>;
};
+ spiclk: virt_100mhz {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
device-width = <1>;
};
+ spi: spi@f0b00000 {
+ compatible = "andestech,atcspi200";
+ reg = <0xf0b00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <1>;
+ clocks = <&spiclk>;
+ interrupts = <3 4>;
+ flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ spi-cpol;
+ spi-cpha;
+ };
+ };
};
#ifndef NDS32_BOOTM_H
#define NDS32_BOOTM_H
+#include <asm/setup.h>
+
extern void udc_disconnect(void);
#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
#ifndef __ASM_NDS_DMA_MAPPING_H
#define __ASM_NDS_DMA_MAPPING_H
-enum dma_data_direction {
- DMA_BIDIRECTIONAL = 0,
- DMA_TO_DEVICE = 1,
- DMA_FROM_DEVICE = 2,
-};
+#include <linux/dma-direction.h>
static void *dma_alloc_coherent(size_t len, unsigned long *handle)
{
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
+#ifdef CONFIG_ARCH_MAP_SYSMEM
+static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
+{
+ if(paddr <PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE)
+ paddr = paddr | 0x40000000;
+ return (void *)(uintptr_t)paddr;
+}
+
+static inline void *unmap_sysmem(const void *vaddr)
+{
+ phys_addr_t paddr = (phys_addr_t)vaddr;
+ paddr = paddr & ~0x40000000;
+ return (void *)(uintptr_t)paddr;
+}
+
+static inline phys_addr_t map_to_sysmem(const void *ptr)
+{
+ return (phys_addr_t)(uintptr_t)ptr;
+}
+#endif
+
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
#include <asm/bootm.h>
-#include <asm/setup.h>
DECLARE_GLOBAL_DATA_PTR;
default "sandbox_spl" if SANDBOX_SPL
default "sandbox" if !SANDBOX_SPL
+choice
+ prompt "Run sandbox on 32/64-bit host"
+ default SANDBOX_64BIT
+ help
+ Sandbox can be built on 32-bit and 64-bit hosts.
+ The default is to build on a 64-bit host and run
+ on a 64-bit host. If you want to run sandbox on
+ a 32-bit host, change it here.
+
+config SANDBOX_32BIT
+ bool "32-bit host"
+
+config SANDBOX_64BIT
+ bool "64-bit host"
+
+endchoice
+
+config SANDBOX_BITS_PER_LONG
+ int
+ default 32 if SANDBOX_32BIT
+ default 64 if SANDBOX_64BIT
+
endmenu
compatible = "denx,u-boot-fdt-test";
};
- clk_fixed: clk-fixed {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1234>;
+ clocks {
+ clk_fixed: clk-fixed {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1234>;
+ };
};
clk_sandbox: clk-sbox {
# platform-specific options below
source "arch/x86/cpu/baytrail/Kconfig"
+source "arch/x86/cpu/braswell/Kconfig"
source "arch/x86/cpu/broadwell/Kconfig"
source "arch/x86/cpu/coreboot/Kconfig"
source "arch/x86/cpu/ivybridge/Kconfig"
address of 0xfff90000 indicates that the image will be put at offset
0x90000 from the beginning of a 1MB flash device.
+config HAVE_VBT
+ bool "Add a Video BIOS Table (VBT) image"
+ depends on HAVE_FSP
+ help
+ Select this option if you have a Video BIOS Table (VBT) image that
+ you would like to add to your ROM. This is normally required if you
+ are using an Intel FSP firmware that is complaint with spec 1.1 or
+ later to initialize the integrated graphics device (IGD).
+
+ Video BIOS Table, or VBT, provides platform and board specific
+ configuration information to the driver that is not discoverable
+ or available through other means. By other means the most used
+ method here is to read EDID table from the attached monitor, over
+ Display Data Channel (DDC) using two pin I2C serial interface. VBT
+ configuration is related to display hardware and is available via
+ the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
+
+config VBT_FILE
+ string "Video BIOS Table (VBT) image filename"
+ depends on HAVE_VBT
+ default "vbt.bin"
+ help
+ The filename of the file to use as Video BIOS Table (VBT) image
+ in the board directory.
+
+config VBT_ADDR
+ hex "Video BIOS Table (VBT) image location"
+ depends on HAVE_VBT
+ default 0xfff90000
+ help
+ The location of Video BIOS Table (VBT) image in the SPI flash. For
+ example, base address of 0xfff90000 indicates that the image will
+ be put at offset 0x90000 from the beginning of a 1MB flash device.
+
+config VIDEO_FSP
+ bool "Enable FSP framebuffer driver support"
+ depends on HAVE_VBT && DM_VIDEO
+ help
+ Turn on this option to enable a framebuffer driver when U-Boot is
+ using Video BIOS Table (VBT) image for FSP firmware to initialize
+ the integrated graphics device.
+
config ROM_TABLE_ADDR
hex
default 0xf0000
obj-y += intel_common/
obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
+obj-$(CONFIG_INTEL_BRASWELL) += braswell/
obj-$(CONFIG_INTEL_BROADWELL) += broadwell/
obj-$(CONFIG_SYS_COREBOOT) += coreboot/
obj-$(CONFIG_EFI_APP) += efi/
--- /dev/null
+#
+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+config INTEL_BRASWELL
+ bool
+ select HAVE_FSP
+ select ARCH_MISC_INIT
+ select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+ imply HAVE_INTEL_ME
+ imply HAVE_VBT
+ imply ENABLE_MRC_CACHE
+ imply ENV_IS_IN_SPI_FLASH
+ imply AHCI_PCI
+ imply ICH_SPI
+ imply MMC
+ imply MMC_PCI
+ imply MMC_SDHCI
+ imply MMC_SDHCI_SDMA
+ imply SCSI
+ imply SPI_FLASH
+ imply SYS_NS16550
+ imply USB
+ imply USB_XHCI_HCD
+ imply VIDEO_FSP
+
+if INTEL_BRASWELL
+
+config FSP_ADDR
+ hex
+ default 0xfff20000
+
+config FSP_LOCKDOWN_SPI
+ bool
+ default y
+
+endif
--- /dev/null
+#
+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += braswell.o cpu.o early_uart.o fsp_configs.o
--- /dev/null
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mrccache.h>
+#include <asm/post.h>
+
+int arch_cpu_init(void)
+{
+ post_code(POST_CPU_INIT);
+
+ return x86_cpu_init_f();
+}
+
+int arch_misc_init(void)
+{
+#ifdef CONFIG_ENABLE_MRC_CACHE
+ /*
+ * We intend not to check any return value here, as even MRC cache
+ * is not saved successfully, it is not a severe error that will
+ * prevent system from continuing to boot.
+ */
+ mrccache_save();
+#endif
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ /* cold reset */
+ x86_full_reset();
+}
--- /dev/null
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Derived from arch/x86/cpu/baytrail/cpu.c
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <asm/cpu.h>
+#include <asm/cpu_x86.h>
+#include <asm/io.h>
+#include <asm/lapic.h>
+#include <asm/msr.h>
+#include <asm/turbo.h>
+
+static const unsigned int braswell_bus_freq_table[] = {
+ 83333333,
+ 100000000,
+ 133333333,
+ 116666666,
+ 80000000,
+ 93333333,
+ 90000000,
+ 88900000,
+ 87500000
+};
+
+static unsigned int braswell_bus_freq(void)
+{
+ msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
+
+ if ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table)))
+ return braswell_bus_freq_table[clk_info.lo & 0xf];
+
+ return 0;
+}
+
+static unsigned long braswell_tsc_freq(void)
+{
+ msr_t platform_info;
+ ulong bclk = braswell_bus_freq();
+
+ if (!bclk)
+ return 0;
+
+ platform_info = msr_read(MSR_PLATFORM_INFO);
+
+ return bclk * ((platform_info.lo >> 8) & 0xff);
+}
+
+static int braswell_get_info(struct udevice *dev, struct cpu_info *info)
+{
+ info->cpu_freq = braswell_tsc_freq();
+ info->features = (1 << CPU_FEAT_L1_CACHE) | (1 << CPU_FEAT_MMU);
+
+ return 0;
+}
+
+static int braswell_get_count(struct udevice *dev)
+{
+ int ecx = 0;
+
+ /*
+ * Use the algorithm described in Intel 64 and IA-32 Architectures
+ * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
+ * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
+ * of CPUID Extended Topology Leaf.
+ */
+ while (1) {
+ struct cpuid_result leaf_b;
+
+ leaf_b = cpuid_ext(0xb, ecx);
+
+ /*
+ * Braswell doesn't have hyperthreading so just determine the
+ * number of cores by from level type (ecx[15:8] == * 2)
+ */
+ if ((leaf_b.ecx & 0xff00) == 0x0200)
+ return leaf_b.ebx & 0xffff;
+
+ ecx++;
+ }
+
+ return 0;
+}
+
+static void braswell_set_max_freq(void)
+{
+ msr_t perf_ctl;
+ msr_t msr;
+
+ /* Enable speed step */
+ msr = msr_read(MSR_IA32_MISC_ENABLES);
+ msr.lo |= (1 << 16);
+ msr_write(MSR_IA32_MISC_ENABLES, msr);
+
+ /* Enable Burst Mode */
+ msr = msr_read(MSR_IA32_MISC_ENABLES);
+ msr.hi = 0;
+ msr_write(MSR_IA32_MISC_ENABLES, msr);
+
+ /*
+ * Set guaranteed ratio [21:16] from IACORE_TURBO_RATIOS to
+ * bits [15:8] of the PERF_CTL
+ */
+ msr = msr_read(MSR_IACORE_TURBO_RATIOS);
+ perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
+
+ /*
+ * Set guaranteed vid [22:16] from IACORE_TURBO_VIDS to
+ * bits [7:0] of the PERF_CTL
+ */
+ msr = msr_read(MSR_IACORE_TURBO_VIDS);
+ perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
+
+ perf_ctl.hi = 0;
+ msr_write(MSR_IA32_PERF_CTL, perf_ctl);
+}
+
+static int braswell_probe(struct udevice *dev)
+{
+ debug("Init Braswell core\n");
+
+ /*
+ * On Braswell the turbo disable bit is actually scoped at the
+ * building-block level, not package. For non-BSP cores that are
+ * within a building block, enable turbo. The cores within the BSP's
+ * building block will just see it already enabled and move on.
+ */
+ if (lapicid())
+ turbo_enable();
+
+ /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
+ msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f080f, 0xe0008),
+ msr_clrsetbits_64(MSR_POWER_MISC,
+ ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK, 0);
+
+ /* Disable C1E */
+ msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);
+ msr_setbits_64(MSR_POWER_MISC, 0x44);
+
+ /* Set this core to max frequency ratio */
+ braswell_set_max_freq();
+
+ return 0;
+}
+
+static const struct udevice_id braswell_ids[] = {
+ { .compatible = "intel,braswell-cpu" },
+ { }
+};
+
+static const struct cpu_ops braswell_ops = {
+ .get_desc = cpu_x86_get_desc,
+ .get_info = braswell_get_info,
+ .get_count = braswell_get_count,
+ .get_vendor = cpu_x86_get_vendor,
+};
+
+U_BOOT_DRIVER(cpu_x86_braswell_drv) = {
+ .name = "cpu_x86_braswell",
+ .id = UCLASS_CPU,
+ .of_match = braswell_ids,
+ .bind = cpu_x86_bind,
+ .probe = braswell_probe,
+ .ops = &braswell_ops,
+};
--- /dev/null
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define PCI_DEV_CONFIG(segbus, dev, fn) ( \
+ (((segbus) & 0xfff) << 20) | \
+ (((dev) & 0x1f) << 15) | \
+ (((fn) & 0x07) << 12))
+
+/* Platform Controller Unit */
+#define LPC_DEV 0x1f
+#define LPC_FUNC 0
+
+/* Enable UART */
+#define UART_CONT 0x80
+
+/* UART PAD definitions */
+#define UART_RXD_COMMUITY 1
+#define UART_TXD_COMMUITY 1
+#define UART_RXD_FAMILY 4
+#define UART_TXD_FAMILY 4
+#define UART_RXD_PAD 2
+#define UART_TXD_PAD 7
+#define UART_RXD_FUNC 3
+#define UART_TXD_FUNC 3
+
+/* IO Memory */
+#define IO_BASE_ADDRESS 0xfed80000
+
+static inline uint32_t gpio_pconf0(int community, int family, int pad)
+{
+ return IO_BASE_ADDRESS + community * 0x8000 + 0x4400 +
+ family * 0x400 + pad * 8;
+}
+
+static void gpio_select_func(int community, int family, int pad, int func)
+{
+ uint32_t pconf0_addr = gpio_pconf0(community, family, pad);
+
+ clrsetbits_le32(pconf0_addr, 0xf << 16, func << 16);
+}
+
+static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
+{
+ unsigned long addr;
+
+ addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
+ writel(value, addr);
+}
+
+/* This can be called after memory-mapped PCI is working */
+int setup_internal_uart(int enable)
+{
+ /* Enable or disable the legacy UART hardware */
+ x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
+ enable);
+
+ /* All done for the disable part, so just return */
+ if (!enable)
+ return 0;
+
+ /*
+ * Set up the pads to the UART function. This allows the signals to
+ * leave the chip
+ */
+ gpio_select_func(UART_RXD_COMMUITY, UART_RXD_FAMILY,
+ UART_RXD_PAD, UART_RXD_FUNC);
+ gpio_select_func(UART_TXD_COMMUITY, UART_TXD_FAMILY,
+ UART_TXD_PAD, UART_TXD_FUNC);
+
+ return 0;
+}
+
+void board_debug_uart_init(void)
+{
+ setup_internal_uart(1);
+}
--- /dev/null
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * Override the FSP's Azalia configuration data
+ *
+ * @azalia: pointer to be updated to point to a ROM address where Azalia
+ * configuration data is stored
+ */
+__weak void update_fsp_azalia_configs(struct azalia_config **azalia)
+{
+ *azalia = NULL;
+}
+
+/**
+ * Override the FSP's GPIO configuration data
+ *
+ * @family: pointer to be updated to point to a ROM address where GPIO
+ * family configuration data is stored
+ * @pad: pointer to be updated to point to a ROM address where GPIO
+ * pad configuration data is stored
+ */
+__weak void update_fsp_gpio_configs(struct gpio_family **family,
+ struct gpio_pad **pad)
+{
+ *family = NULL;
+ *pad = NULL;
+}
+
+/**
+ * Override the FSP's configuration data.
+ * If the device tree does not specify an integer setting, use the default
+ * provided in Intel's Braswell release FSP/BraswellFsp.bsf file.
+ */
+void update_fsp_configs(struct fsp_config_data *config,
+ struct fspinit_rtbuf *rt_buf)
+{
+ struct upd_region *fsp_upd = &config->fsp_upd;
+ struct memory_upd *memory_upd = &fsp_upd->memory_upd;
+ struct silicon_upd *silicon_upd = &fsp_upd->silicon_upd;
+ const void *blob = gd->fdt_blob;
+ int node;
+
+ /* Initialize runtime buffer for fsp_init() */
+ rt_buf->common.stack_top = config->common.stack_top - 32;
+ rt_buf->common.boot_mode = config->common.boot_mode;
+ rt_buf->common.upd_data = &config->fsp_upd;
+
+ node = fdt_node_offset_by_compatible(blob, 0, "intel,braswell-fsp");
+ if (node < 0) {
+ debug("%s: Cannot find FSP node\n", __func__);
+ return;
+ }
+
+ node = fdt_node_offset_by_compatible(blob, node,
+ "intel,braswell-fsp-memory");
+ if (node < 0) {
+ debug("%s: Cannot find FSP memory node\n", __func__);
+ return;
+ }
+
+ /* Override memory UPD contents */
+ memory_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node,
+ "fsp,mrc-init-tseg-size", MRC_INIT_TSEG_SIZE_4MB);
+ memory_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node,
+ "fsp,mrc-init-mmio-size", MRC_INIT_MMIO_SIZE_2048MB);
+ memory_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
+ "fsp,mrc-init-spd-addr1", 0xa0);
+ memory_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node,
+ "fsp,mrc-init-spd-addr2", 0xa2);
+ memory_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node,
+ "fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_32MB);
+ memory_upd->aperture_size = fdtdec_get_int(blob, node,
+ "fsp,aperture-size", APERTURE_SIZE_256MB);
+ memory_upd->gtt_size = fdtdec_get_int(blob, node,
+ "fsp,gtt-size", GTT_SIZE_1MB);
+ memory_upd->legacy_seg_decode = fdtdec_get_bool(blob, node,
+ "fsp,legacy-seg-decode");
+ memory_upd->enable_dvfs = fdtdec_get_bool(blob, node,
+ "fsp,enable-dvfs");
+ memory_upd->memory_type = fdtdec_get_int(blob, node,
+ "fsp,memory-type", DRAM_TYPE_DDR3);
+ memory_upd->enable_ca_mirror = fdtdec_get_bool(blob, node,
+ "fsp,enable-ca-mirror");
+
+ node = fdt_node_offset_by_compatible(blob, node,
+ "intel,braswell-fsp-silicon");
+ if (node < 0) {
+ debug("%s: Cannot find FSP silicon node\n", __func__);
+ return;
+ }
+
+ /* Override silicon UPD contents */
+ silicon_upd->sdcard_mode = fdtdec_get_int(blob, node,
+ "fsp,sdcard-mode", SDCARD_MODE_PCI);
+ silicon_upd->enable_hsuart0 = fdtdec_get_bool(blob, node,
+ "fsp,enable-hsuart0");
+ silicon_upd->enable_hsuart1 = fdtdec_get_bool(blob, node,
+ "fsp,enable-hsuart1");
+ silicon_upd->enable_azalia = fdtdec_get_bool(blob, node,
+ "fsp,enable-azalia");
+ if (silicon_upd->enable_azalia)
+ update_fsp_azalia_configs(&silicon_upd->azalia_cfg_ptr);
+ silicon_upd->enable_sata = fdtdec_get_bool(blob, node,
+ "fsp,enable-sata");
+ silicon_upd->enable_xhci = fdtdec_get_bool(blob, node,
+ "fsp,enable-xhci");
+ silicon_upd->lpe_mode = fdtdec_get_int(blob, node,
+ "fsp,lpe-mode", LPE_MODE_PCI);
+ silicon_upd->enable_dma0 = fdtdec_get_bool(blob, node,
+ "fsp,enable-dma0");
+ silicon_upd->enable_dma1 = fdtdec_get_bool(blob, node,
+ "fsp,enable-dma1");
+ silicon_upd->enable_i2c0 = fdtdec_get_bool(blob, node,
+ "fsp,enable-i2c0");
+ silicon_upd->enable_i2c1 = fdtdec_get_bool(blob, node,
+ "fsp,enable-i2c1");
+ silicon_upd->enable_i2c2 = fdtdec_get_bool(blob, node,
+ "fsp,enable-i2c2");
+ silicon_upd->enable_i2c3 = fdtdec_get_bool(blob, node,
+ "fsp,enable-i2c3");
+ silicon_upd->enable_i2c4 = fdtdec_get_bool(blob, node,
+ "fsp,enable-i2c4");
+ silicon_upd->enable_i2c5 = fdtdec_get_bool(blob, node,
+ "fsp,enable-i2c5");
+ silicon_upd->enable_i2c6 = fdtdec_get_bool(blob, node,
+ "fsp,enable-i2c6");
+#ifdef CONFIG_HAVE_VBT
+ silicon_upd->graphics_config_ptr = CONFIG_VBT_ADDR;
+#endif
+ update_fsp_gpio_configs(&silicon_upd->gpio_familiy_ptr,
+ &silicon_upd->gpio_pad_ptr);
+ /*
+ * For Braswell B0 stepping, disable_punit_pwr_config must be set to 1
+ * otherwise it just hangs in fsp_init().
+ */
+ if (gd->arch.x86_mask == 2)
+ silicon_upd->disable_punit_pwr_config = 1;
+ silicon_upd->emmc_mode = fdtdec_get_int(blob, node,
+ "fsp,emmc-mode", EMMC_MODE_PCI);
+ silicon_upd->sata_speed = fdtdec_get_int(blob, node,
+ "fsp,sata-speed", SATA_SPEED_GEN3);
+ silicon_upd->pmic_i2c_bus = fdtdec_get_int(blob, node,
+ "fsp,pmic-i2c-bus", 0);
+ silicon_upd->enable_isp = fdtdec_get_bool(blob, node,
+ "fsp,enable-isp");
+ silicon_upd->isp_pci_dev_config = fdtdec_get_int(blob, node,
+ "fsp,isp-pci-dev-config", ISP_PCI_DEV_CONFIG_2);
+ silicon_upd->turbo_mode = fdtdec_get_bool(blob, node,
+ "fsp,turbo-mode");
+ silicon_upd->pnp_settings = fdtdec_get_int(blob, node,
+ "fsp,pnp-settings", PNP_SETTING_POWER_AND_PERF);
+ silicon_upd->sd_detect_chk = fdtdec_get_bool(blob, node,
+ "fsp,sd-detect-chk");
+}
return bridge_id | stepping;
}
-/*
- * Reserve everything between A segment and 1MB:
- *
- * 0xa0000 - 0xbffff: legacy VGA
- * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
- * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
- */
-static const int legacy_hole_base_k = 0xa0000 / 1024;
-static const int legacy_hole_size_k = 384;
-
static int get_pcie_bar(struct udevice *dev, u32 *base, u32 *len)
{
u32 pciexbar_reg;
#
dtb-y += bayleybay.dtb \
+ cherryhill.dtb \
chromebook_link.dtb \
chromebox_panther.dtb \
chromebook_samus.dtb \
--- /dev/null
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include <asm/arch-braswell/fsp/fsp_configs.h>
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+ model = "Intel Cherry Hill";
+ compatible = "intel,cherryhill", "intel,braswell";
+
+ aliases {
+ serial0 = &serial;
+ spi0 = &spi;
+ };
+
+ config {
+ silent_console = <0>;
+ };
+
+ chosen {
+ stdout-path = "/serial";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "intel,braswell-cpu";
+ reg = <0>;
+ intel,apic-id = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "intel,braswell-cpu";
+ reg = <1>;
+ intel,apic-id = <2>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "intel,braswell-cpu";
+ reg = <2>;
+ intel,apic-id = <4>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "intel,braswell-cpu";
+ reg = <3>;
+ intel,apic-id = <6>;
+ };
+ };
+
+ pci {
+ compatible = "pci-x86";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
+ 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
+ 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+ pch@1f,0 {
+ reg = <0x0000f800 0 0 0 0>;
+ compatible = "intel,pch9";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "ibase";
+ intel,ibase-offset = <0x50>;
+ intel,pirq-link = <8 8>;
+ intel,pirq-mask = <0xdee0>;
+ intel,pirq-routing = <
+ /* Braswell PCI devices */
+ PCI_BDF(0, 2, 0) INTA PIRQA
+ PCI_BDF(0, 3, 0) INTA PIRQA
+ PCI_BDF(0, 11, 0) INTA PIRQA
+ PCI_BDF(0, 16, 0) INTA PIRQA
+ PCI_BDF(0, 17, 0) INTA PIRQA
+ PCI_BDF(0, 18, 0) INTA PIRQA
+ PCI_BDF(0, 19, 0) INTA PIRQA
+ PCI_BDF(0, 20, 0) INTA PIRQA
+ PCI_BDF(0, 21, 0) INTA PIRQA
+ PCI_BDF(0, 24, 0) INTA PIRQA
+ PCI_BDF(0, 24, 1) INTC PIRQC
+ PCI_BDF(0, 24, 2) INTD PIRQD
+ PCI_BDF(0, 24, 3) INTB PIRQB
+ PCI_BDF(0, 24, 4) INTA PIRQA
+ PCI_BDF(0, 24, 5) INTC PIRQC
+ PCI_BDF(0, 24, 6) INTD PIRQD
+ PCI_BDF(0, 24, 7) INTB PIRQB
+ PCI_BDF(0, 26, 0) INTA PIRQA
+ PCI_BDF(0, 27, 0) INTA PIRQA
+ PCI_BDF(0, 28, 0) INTA PIRQA
+ PCI_BDF(0, 28, 1) INTB PIRQB
+ PCI_BDF(0, 28, 2) INTC PIRQC
+ PCI_BDF(0, 28, 3) INTD PIRQD
+ PCI_BDF(0, 30, 0) INTA PIRQA
+ PCI_BDF(0, 30, 3) INTA PIRQA
+ PCI_BDF(0, 30, 4) INTA PIRQA
+ PCI_BDF(0, 31, 0) INTB PIRQB
+ PCI_BDF(0, 31, 3) INTB PIRQB
+
+ /*
+ * PCIe root ports downstream
+ * interrupts
+ */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(1, 0, 0) INTB PIRQB
+ PCI_BDF(1, 0, 0) INTC PIRQC
+ PCI_BDF(1, 0, 0) INTD PIRQD
+ PCI_BDF(2, 0, 0) INTA PIRQB
+ PCI_BDF(2, 0, 0) INTB PIRQC
+ PCI_BDF(2, 0, 0) INTC PIRQD
+ PCI_BDF(2, 0, 0) INTD PIRQA
+ PCI_BDF(3, 0, 0) INTA PIRQC
+ PCI_BDF(3, 0, 0) INTB PIRQD
+ PCI_BDF(3, 0, 0) INTC PIRQA
+ PCI_BDF(3, 0, 0) INTD PIRQB
+ PCI_BDF(4, 0, 0) INTA PIRQD
+ PCI_BDF(4, 0, 0) INTB PIRQA
+ PCI_BDF(4, 0, 0) INTC PIRQB
+ PCI_BDF(4, 0, 0) INTD PIRQC
+ >;
+ };
+
+ spi: spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich9-spi";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "macronix,mx25u6435f", "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ rw-mrc-cache {
+ label = "rw-mrc-cache";
+ reg = <0x005e0000 0x00010000>;
+ };
+ };
+ };
+ };
+ };
+
+ fsp {
+ compatible = "intel,braswell-fsp";
+ fsp,memory-upd {
+ compatible = "intel,braswell-fsp-memory";
+ fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_4MB>;
+ fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
+ fsp,mrc-init-spd-addr1 = <0xa0>;
+ fsp,mrc-init-spd-addr2 = <0xa2>;
+ fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_32MB>;
+ fsp,aperture-size = <APERTURE_SIZE_256MB>;
+ fsp,gtt-size = <GTT_SIZE_1MB>;
+ fsp,enable-dvfs;
+ fsp,memory-type = <DRAM_TYPE_DDR3>;
+ };
+ fsp,silicon-upd {
+ compatible = "intel,braswell-fsp-silicon";
+ fsp,sdcard-mode = <SDCARD_MODE_PCI>;
+ fsp,enable-hsuart1;
+ fsp,enable-sata;
+ fsp,enable-xhci;
+ fsp,lpe-mode = <LPE_MODE_PCI>;
+ fsp,enable-dma0;
+ fsp,enable-dma1;
+ fsp,enable-i2c0;
+ fsp,enable-i2c1;
+ fsp,enable-i2c2;
+ fsp,enable-i2c3;
+ fsp,enable-i2c4;
+ fsp,enable-i2c5;
+ fsp,enable-i2c6;
+ fsp,emmc-mode = <EMMC_MODE_PCI>;
+ fsp,sata-speed = <SATA_SPEED_GEN3>;
+ fsp,pmic-i2c-bus = <0>;
+ fsp,enable-isp;
+ fsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>;
+ fsp,turbo-mode;
+ fsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>;
+ fsp,sd-detect-chk;
+ };
+ };
+
+ microcode {
+ update@0 {
+#include "microcode/m01406c2220.dtsi"
+ };
+ update@1 {
+#include "microcode/m01406c3363.dtsi"
+ };
+ update@2 {
+#include "microcode/m01406c440a.dtsi"
+ };
+ };
+
+};
--- /dev/null
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x220>;
+intel,date-code = <0x1142015>;
+intel,processor-signature = <0x406c2>;
+intel,checksum = <0x21a02433>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x20020000 0x15201401 0xc2060400
+ 0x3324a021 0x01000000 0x01000000 0xd00b0100
+ 0x000c0100 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x20020000
+ 0x00000000 0x00000000 0x14011520 0xe1420000
+ 0x01000000 0xc2060400 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x17ce1b3d 0x74fb4eb5 0x2f27d633 0x14060671
+ 0x6b4d57b0 0xaa1ad327 0x6022d785 0x5fa91aad
+ 0xef44e4c3 0xf91d4958 0x230883b7 0x7382ab6e
+ 0xf14324ef 0xf94c28d7 0x9131d196 0xebcf2faa
+ 0xc049cb37 0xd1577abd 0x5edbe45a 0x17e1ca1e
+ 0xbe9a92c3 0x1c8e1790 0xb3c08b8a 0xca799851
+ 0x3f2a8c92 0x1b7e15d8 0x1f44ecb2 0xaeda1838
+ 0x0ace8669 0xae9d497e 0x424c680c 0x21b3a3ed
+ 0xd924acfe 0xddc126a2 0x26363596 0x21cd999b
+ 0x193f9df3 0x037d1953 0xf97a3dc5 0x4c94ad7e
+ 0x98b360f0 0xeb90461f 0x438e6d2e 0x30851a0e
+ 0xfd623681 0x18782d3c 0x702938c5 0x462df0dd
+ 0xf7d67cc1 0x161076a0 0xf06e5db3 0xd861a76b
+ 0xa40b06bc 0xed37c69b 0x2b25f98b 0x2b67887d
+ 0xbf0131b5 0x571b7c25 0x34eb3752 0x992e406e
+ 0x031ba8e7 0xccfc5b1d 0x33f487e9 0xeccc3098
+ 0xe452737b 0xb38cc286 0x817bc58f 0x852a7fde
+ 0xcbcd1b19 0xab11894a 0xa1f278d7 0x360829c9
+ 0x11000000 0x67a4c01f 0x3f863221 0xf4b82fe4
+ 0xf464c489 0x36b8d097 0xfa9ab17e 0x9bccf4e6
+ 0x9f836ffd 0x647c263c 0x03c7bede 0xf20172e9
+ 0x8bd6e772 0x8621aca5 0xbdf4eade 0xac27528a
+ 0xb562042b 0x23d0304c 0x964558ea 0xb5c03c97
+ 0xe0bd0467 0xe8a6d50a 0xe5d4b902 0xb164253e
+ 0x8306959c 0xd1cd57d5 0xf7d1d586 0x4eb5152b
+ 0xf488caca 0xaa47f32f 0x366676b3 0x96b27e47
+ 0xc8f4fdda 0x9f6854bb 0x89921eb5 0xbb7fe720
+ 0x59709d36 0x01a5880c 0xee526518 0x586055d6
+ 0xfac43c7a 0x7ce6da62 0x301be309 0xf48c261e
+ 0xdd7d6b27 0x6783c81a 0xf9151492 0x92a57bd1
+ 0x94607cfc 0xd70700ed 0x18136034 0x16d26594
+ 0xeadd5210 0xf2fa345f 0xba7e9be4 0x548b8db1
+ 0xd9d81a27 0xb361bae3 0xe2c5c033 0xd34d0488
+ 0x07925cd2 0xaf57a669 0xf7f634b6 0x58408a6f
+ 0x2c8b4c46 0xe71e9a53 0x65bc42be 0x77db4bf1
+ 0x4c839bf5 0xd6dbc641 0x4fbf6fef 0x6b71eb34
+ 0x808898b9 0x7ecea348 0x608a1d5e 0x81225ea2
+ 0x487a3d44 0xc2443f3e 0xff580d9a 0xefd915b1
+ 0xe867848b 0x73c48e53 0x84d211d4 0x77a45152
+ 0x146f95fc 0x088157cb 0x9661fa65 0x6b998636
+ 0xd8d8748d 0x16bb32b5 0x3eb3be6a 0x29a2aa6e
+ 0xcbd08ca6 0x74317789 0xe9e8f1ea 0x7c555679
+ 0xd7f19a7b 0xcead34da 0xe584403c 0xbfae80e2
+ 0x4e9a7a52 0x0eefa659 0x00eb4354 0xe6f0cf6d
+ 0x69374a24 0xdb59e992 0x2d4a51eb 0x4cdb46ca
+ 0x03613349 0x24d146ab 0x1cca9b58 0x6db9989a
+ 0x534dedef 0xab90d703 0x75a8331b 0xec865e24
+ 0x8415faf2 0x851022e8 0x4ee795cd 0x7af2b1a8
+ 0x65ec359a 0x0a16c7d8 0x76d51f56 0x7e1e10ec
+ 0xbab138d8 0x0d69389e 0x0a50fc3a 0x7746732d
+ 0x98f692d2 0xf97254ff 0xd31185d4 0x1a7104b4
+ 0x1382fbff 0x4660f775 0x187ed97f 0x880cb07a
+ 0x566157d2 0x1ec58c53 0xc1fff1e3 0x30cde9d6
+ 0x933993eb 0x365c5318 0x30a5df05 0x91744f18
+ 0xac99ae3a 0xacb5cc81 0x6af06584 0xcbfcb5dc
+ 0x10e3cdd1 0x8d31a621 0x36851aa8 0x718c1d81
+ 0x4a574346 0x70fb532a 0xc97b70e3 0x4e61d0d1
+ 0x9e5e2563 0xd86da543 0xb6c07a52 0x417e59f2
+ 0xee4c48d6 0xca38e12e 0x9188a73d 0x6624af3c
+ 0x62a1d33f 0xcf8afe37 0xd0173727 0x378470e3
+ 0x35067424 0x0775c48c 0x7cab8eb0 0xfeb84d6c
+ 0x187fbb8c 0xe2cab639 0xedfc3f59 0xbace1601
+ 0xbc2535e9 0x74b7d16e 0xbc351b20 0xf4a41f6f
+ 0x996a0c11 0xec1e5d06 0x8dae9d53 0xe92082ce
+ 0x8bfb678f 0xb4ae58e4 0xbecbf0de 0xfdbd1df9
+ 0x0cf5ffe2 0x362f4eb5 0x90cc7b4e 0x813a329d
+ 0xd6b5c9fc 0x19dea293 0x4bc51036 0x10570f4b
+ 0xd904d7b6 0x348da9e4 0x2fd7a32d 0xfc79b430
+ 0x0b9c30dd 0xe0289eb6 0xc6ef55ef 0xfae73fe2
+ 0xbd4a65d1 0x463804e8 0xc1d6c9d9 0xa94cea7a
+ 0xa23f954d 0x2d76b17e 0x5851be88 0xcf829e51
+ 0xe6c5c2a6 0x94f9772b 0xe6c22b45 0x3a6cb78f
+ 0xb7f13d24 0x4c45d9f3 0xa8c115ec 0x3156aea1
+ 0x8076cddc 0x191032dc 0xc7e3c577 0x04ff6b8e
+ 0x4b048a66 0x61645b1e 0x49c1f2da 0x428518b8
+ 0x5270837d 0x25aee268 0xa0d1bbaa 0x7c2b6cdc
+ 0x95251e7d 0x47eb8833 0x4b274412 0x9df92f4d
+ 0xc9165ad1 0x928605dd 0xed0ca542 0x59899c98
+ 0xbe0a0295 0xaa9cc0ae 0x1a03db3f 0x00adb561
+ 0xecfda91f 0xc4ba7882 0x38ec4207 0x55bc0855
+ 0xced7c3e9 0x3e783ec0 0xe5085047 0x120366cb
+ 0x56161c5b 0x2cda197c 0x4b855ae0 0xdebd39ef
+ 0xe077f8c5 0x831346fc 0x119cf5bc 0x1f856af0
+ 0x71be6741 0x94946c60 0x320ff78f 0xb24955bf
+ 0xcaeaa452 0xcf673cad 0x83dee256 0xc1ca89d6
+ 0x9a99b0c8 0x0506634a 0x43825141 0x93b261da
+ 0x110fc9e7 0x1fff550f 0xff64e483 0x8ab28045
+ 0xdc8a20e1 0x64f0125b 0x02b35cc1 0xae9a45a0
+ 0x1ba02775 0x4ca78c43 0x00492b04 0xca28b4c6
+ 0x2986d389 0x277de0ac 0x115a59fc 0x03c55ef6
+ 0xeb2d37d4 0x8f6091a6 0x5589954b 0xd6a76cfe
+ 0x52f90c11 0xc880f0aa 0x674e9009 0xd1cf458a
+ 0xcbf97f4e 0x8b1a7a5e 0x52aca0bb 0x7562f0bb
+ 0x27351468 0xf1ec9a0e 0x8300fefd 0x34358af1
+ 0x1c33380b 0x29c5eae7 0x8ad5fedc 0x1fd8288b
+ 0xb87a0fa8 0x0ed4830d 0x034a4536 0x9479d467
+ 0xe6d0aafe 0x941d6d97 0x4e3b0d6f 0x057a6b8d
+ 0x62cc8d8f 0xdcc01061 0x13217f10 0x6e5ddaa3
+ 0xd9ebc375 0x1d54b3f2 0xed12af1c 0x48ff2428
+ 0xe65ca319 0x6c699865 0x2d101e05 0xd28a495a
+ 0x8bd948d8 0xa0b503b1 0x447158c1 0x662e03d2
+ 0x0150fb5f 0x55288aa2 0x3e74f75d 0x5c111c33
+ 0x802fe4c9 0x4d90bb9b 0x8b0a9377 0x9c215cdd
+ 0x75602db3 0xf990e4a2 0xb41c8f6a 0x8a044b56
+ 0x56214d80 0x95a51d94 0x957256ad 0xbc4bcfa2
+ 0x82325276 0xe03231d9 0xb30b1dba 0x62974827
+ 0x75c311f5 0x73081c86 0x6caedca9 0xfd65a79c
+ 0x8a0a51b1 0x69f69434 0x1ec5f9ac 0x4379a9b8
+ 0x25ee82e2 0xb8de5ce8 0x4dddef11 0x1f287f04
+ 0x3438be45 0xa9f615c0 0xc4b4885d 0x4463603c
+ 0x17a51586 0xb941900e 0x55f6b1fc 0x827adf71
+ 0x2be9133f 0x98fcacec 0x7db549ff 0xf2172b4d
+ 0x389a1ee7 0x28b04504 0x091e5333 0x9b3d5323
+ 0xab29ddb5 0xf67748c3 0x838b320d 0xc2cd0deb
+ 0x40b166b2 0xafe61841 0xbb915676 0x060235f5
+ 0x68cbea2d 0xa7e4415c 0x9b67dcf9 0xd40da108
+ 0xa6f53ede 0x395f766c 0xfd2b8267 0x84cbdd78
+ 0x5dea645a 0x188cc462 0x471782c5 0x716f5c34
+ 0x12b64f0a 0xc4e5d287 0x008469cf 0x74023871
+ 0x280e14e8 0xa4cd2075 0xd6741c46 0x39228423
+ 0x1d33880d 0x0fe5a8b2 0x09a0d784 0x43f282e0
+ 0xe1fb9193 0x0c1d6d00 0x4618bb7e 0xa2346753
+ 0xac82efb0 0x50c97aed 0x5e08b6da 0x1540d8d4
+ 0xaaefaa57 0x0ae69a20 0x304ca040 0xc8e6ba4d
+ 0x43b79690 0x5955117f 0x31e602b0 0xc650acbb
+ 0x74fd2f1c 0xaa0ae398 0x83f8a97b 0xe2b2c874
+ 0xfcb179bd 0xe2c54c23 0x1fa7d92f 0xfbafaf63
+ 0xcc581a06 0x6a75505b 0xb1a35d63 0x9830e0e5
+ 0xfdb7327f 0xa806c4db 0x0f146d1a 0xe848b52e
+ 0x468a29bc 0x29ea4c2c 0x35ab0da3 0x0e81c222
+ 0x86567478 0x1e8e8296 0x565fbd9a 0x37028b11
+ 0xa477474d 0x97d39513 0x037b58a7 0x9c5b00eb
+ 0xa72d199f 0xa7435b0d 0x2504561d 0xabb17c92
+ 0xd4266638 0xcad2a41f 0x80527d70 0xcf6ced92
+ 0x66f2fb6b 0xb8c51f64 0xb6afb635 0x32ad2078
+ 0x117eab32 0x9a1304a1 0x0291a57a 0xea6bc7b5
+ 0x0bfaa751 0x1e07d4af 0x2e09ea27 0x84dee2e8
+ 0x6fe9e22e 0x3fc0a825 0xd34a7310 0x2e91e3ac
+ 0x72c41ca4 0xe054f5c9 0xd41cf7a3 0x1451734b
+ 0xf22c4d4c 0x6ff1ddbb 0x8322a1a2 0x169f77ca
+ 0x8d948d3a 0x6ea0b0f5 0x59688992 0xefe70251
+ 0x77dbfe62 0xcb4a6d76 0x765fa85c 0xb971b63f
+ 0xf0991fe5 0xd3adf7c6 0xcd96811b 0xa49d5613
+ 0x68263809 0xd97dd8e5 0xa402e5d0 0x4ee84e99
+ 0x5458f785 0xdd7c356a 0x8ab65316 0xfed03904
+ 0xa416a959 0x6507893a 0xc0efcfa7 0xf3f6c537
+ 0x1f36838f 0x4abd214a 0x3e7f80c0 0x8f806c17
+ 0xac8a7c48 0x92a9d45e 0xb923b35a 0x2e0dc4b5
+ 0x38033851 0x469df49b 0x9493372a 0xe9615673
+ 0x90d6cf75 0xc161311b 0xb58a84c3 0x03a5f485
+ 0x59aaf326 0xb7332227 0xeed2691b 0xe0151563
+ 0x90724196 0xda93f7bc 0x2928e854 0xeada9582
+ 0x650c43e6 0xaef61786 0xfbedec7c 0xc31eb425
+ 0x950719a9 0xa12c80d7 0x4024b15f 0xa9f81f31
+ 0xd1381f85 0xb7287ed7 0x5fb7679e 0x1933734c
+ 0x5ede6770 0x1ed50817 0x9b9e3605 0xf9432e65
+ 0xe5537255 0xa2216726 0x5a58b595 0x197b2a54
+ 0x36050287 0xebedeb87 0x362d920c 0x7b0a455f
+ 0x84cae44d 0xa8862ae6 0x85a968fe 0x30e77406
+ 0x36a4a4a3 0x94f0f11d 0xe94b7c54 0x6ca83879
+ 0x2612a797 0xcb794096 0xe865a5c1 0x2a0be103
+ 0x02e32985 0x476f701c 0xc71ba33d 0x4a028652
+ 0x9876c689 0x1c3a44fa 0x26ac3755 0xaff3b350
+ 0xadeb81ea 0xbdbd1786 0x3476e7a0 0xec4f3ad6
+ 0xe0c48b27 0xa79b18ee 0x97f483ab 0xc99f011d
+ 0x7e2eed90 0x7dc8b1db 0xa0cc452a 0xf6b42f90
+ 0x75fad6db 0x9c5bdca7 0x5a01f8a8 0x6014dd88
+ 0x0a01294c 0xbc5cea06 0xd503b150 0x6060d7fa
+ 0xe873dbf2 0xa325211c 0x933c6ef8 0x7ea9b2ee
+ 0x394f6927 0x56531513 0x99f0662d 0x86554329
+ 0xf3251f93 0x54c593f1 0xb5255252 0x26a7b639
+ 0x23ab770b 0xa6acb21a 0xe599b798 0xb95143f5
+ 0x8c806fe3 0x19978f7e 0xb4d37f44 0xd187235f
+ 0xe4bed961 0x6fa2eed6 0x9fc0c7b2 0xf893b168
+ 0x87b33909 0x78cd7ca9 0xd3f90120 0x0c807273
+ 0x26f6418b 0xd31524d0 0x714c9c3f 0x07eb97a8
+ 0x858bdb17 0x5a588101 0x5018f39c 0x74dda380
+ 0x8fbf21c5 0x3093a68e 0x8ff3944f 0x066a211a
+ 0x420f71b2 0x526a827d 0xfa801547 0x5087ccc4
+ 0xf137741e 0x0938d58f 0x3c69fe23 0x017c35e8
+ 0x029ded16 0x036dc14c 0x770c59a2 0xd4670464
+ 0x0c8d2275 0x45a911c5 0x6cb60b1f 0x3891138d
+ 0xc45336a4 0x1e86ff67 0xa4b0e708 0x2c273632
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+ 0x0d68d90d 0x9063b417 0x63764a13 0xe46589e8
+ 0x4c464469 0x01da5cd7 0xda3d955f 0xa9cb6bda
+ 0x74c5905a 0x022a3068 0x99785d4d 0x4aa81734
+ 0x65f0e347 0x38cae44a 0x41445dd6 0xa8d298e6
+ 0xe135a8c6 0x9e36cc39 0x450fd746 0xb4c9282e
+ 0x5f902e54 0x52047a0a 0x054dcd41 0xa7f54f76
+ 0x7e064c5d 0x1840b8dc 0xa42b3fc2 0x89959221
+ 0x3670527e 0x0033bf58 0x6d01b3e7 0x153a4523
+ 0xfdbede48 0xeb37591e 0xe9dcd198 0xe19b32b3
+ 0x0ce76cc6 0x07fd8a8b 0x7861aea7 0x0e6ef7cc
+ 0x295dcc81 0xeed43565 0x85e6b1b4 0x1c36176e
+ 0x4de5e5ea 0xad417cd3 0xa0b502d7 0x4f4f26ad
+ 0x55f0a11a 0x70414fff 0x578f513f 0x1a0036d4
+ 0x65cb54d0 0xdbe91469 0xb613a236 0x73c05182
+ 0x8da00dae 0xbc1c8526 0xff0ad02c 0x9289e4ef
+ 0x245d0636 0x162603db 0x0e5a40fa 0x0cfeefd3
+ 0xc355fae2 0xf2866c99 0xc65dfc8f 0xb7ab492f
+ 0xf811fcf6 0xceaef429 0x4ecdb0e5 0x54bf4e1c
+ 0x02c83d94 0x174cf22e 0x3c304b8d 0x9ad51572
+ 0x444ab420 0x7c41fcb7 0x70193210 0xdc59b8da
+ 0x9042a368 0x2c73167e 0x47dfb476 0xc07c86a0
+ 0x0341e3aa 0x8ee97f19 0x65a47f28 0xe9221e76
+ 0xac7ce5b2 0x5dc2293a 0x575436c1 0xb897b186
+ 0xb6722e1b 0x0cede865 0x641884f8 0x87784739
+ 0xb2cdbe39 0xf53210b5 0x819b5b5e 0x7e993c71
+ 0x088c20d9 0x1ff3c97a 0xe348600f 0xb9434df3
+ 0x4e2404ee 0x72ab1fb6 0x80922cc4 0x1239aa8b
+ 0x180c6d70 0x47f0e6c8 0x04c35fa4 0x861eee82
+ 0x4a5b0130 0xd29740e4 0x1200e288 0xd8aa1b4a
+ 0x45cf055b 0xf0970e66 0x7e82c921 0x038a1be7
+ 0x0f12a078 0x89ad1d6a 0x1c97ef2b 0xd3a3abb8
+ 0xd6026f4e 0x2b9e13d4 0x5d5611d7 0xb35b1222
+ 0x6a0715d6 0xe93cceea 0xbdc957a3 0x998dad9d
+ 0xecfec721 0x09f02421 0x4c971582 0xe4fc588d
+ 0x3a8f1c64 0xaeb5a6de 0x94bdd5e3 0xca0c1072
+ 0x352fd723 0x6257b138 0xfee44d09 0x9a3d6c87
+ 0x1031ae4d 0x6f2ebcac 0x97611fc4 0x37799303
+ 0x9566d4f0 0xf6a69a64 0xd089ecc2 0x06c7a3b0
+ >;
--- /dev/null
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x363>;
+intel,date-code = <0x12182015>;
+intel,processor-signature = <0x406c3>;
+intel,checksum = <0x3ecdece5>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x63030000 0x15201812 0xc3060400
+ 0xe5eccd3e 0x01000000 0x01000000 0xd00b0100
+ 0x000c0100 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x63030000
+ 0x00000000 0x00000000 0x18121520 0xf1420000
+ 0x01000000 0xc3060400 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x6abbab24 0x789752cb 0x83003819 0x616df082
+ 0xf0952c2c 0x7fbf7fbe 0xe1ca9540 0x47bb7ec7
+ 0xef44e4c3 0xf91d4958 0x230883b7 0x7382ab6e
+ 0xf14324ef 0xf94c28d7 0x9131d196 0xebcf2faa
+ 0xc049cb37 0xd1577abd 0x5edbe45a 0x17e1ca1e
+ 0xbe9a92c3 0x1c8e1790 0xb3c08b8a 0xca799851
+ 0x3f2a8c92 0x1b7e15d8 0x1f44ecb2 0xaeda1838
+ 0x0ace8669 0xae9d497e 0x424c680c 0x21b3a3ed
+ 0xd924acfe 0xddc126a2 0x26363596 0x21cd999b
+ 0x193f9df3 0x037d1953 0xf97a3dc5 0x4c94ad7e
+ 0x98b360f0 0xeb90461f 0x438e6d2e 0x30851a0e
+ 0xfd623681 0x18782d3c 0x702938c5 0x462df0dd
+ 0xf7d67cc1 0x161076a0 0xf06e5db3 0xd861a76b
+ 0xa40b06bc 0xed37c69b 0x2b25f98b 0x2b67887d
+ 0xbf0131b5 0x571b7c25 0x34eb3752 0x992e406e
+ 0x031ba8e7 0xccfc5b1d 0x33f487e9 0xeccc3098
+ 0xe452737b 0xb38cc286 0x817bc58f 0x852a7fde
+ 0xcbcd1b19 0xab11894a 0xa1f278d7 0x360829c9
+ 0x11000000 0x34af9103 0xd674d0ce 0xa551e6a8
+ 0xa4ecdc9d 0x1cc02761 0x9c6e5450 0xa160c598
+ 0x52f99daf 0xec0347b8 0x3da61ab4 0xf567197c
+ 0xfd8bb83f 0xcc995bef 0x54d178b6 0x1671de11
+ 0xac092895 0x9debbed1 0x6c92142c 0x6323623d
+ 0x0eb91ca9 0x5c295220 0xfbaa9c0e 0x589cb9fc
+ 0xec23fbf8 0xa4a586a7 0x199f007f 0xdf3216db
+ 0xc0d57da5 0x5f4725e3 0x5726d9c9 0x17667c8d
+ 0xc1c79708 0x9e2256eb 0xfdd0d08f 0x60c7bed3
+ 0x5845511d 0xd7082ef8 0x3baa9a81 0x79e5bbdb
+ 0x5fa1d140 0x1a9dd574 0x65ab8603 0x3d09b760
+ 0x5d5370dd 0x20cbfc54 0x6bb53528 0xd0d59569
+ 0x3072c8e0 0x8d041e8a 0x393ff37c 0xa924e167
+ 0xdc321c2e 0x758ef7f9 0x75d45a77 0xa162493e
+ 0x541efc10 0x10adfa66 0x1ec98113 0x2adbfc4e
+ 0x6f72ee57 0xb6135602 0x6bb1aaa5 0x8b28671d
+ 0x52cd7438 0xe23e5714 0x541d71b8 0x1edeaecd
+ 0x66099798 0x273aafe2 0x94c4bcfa 0xd2a91918
+ 0xbfb900b7 0x7bffd9a6 0x98f3cc81 0x25418789
+ 0xe4827c24 0xf91a6587 0xa8f37dce 0xed2bb02a
+ 0x55e3d863 0xf75d0279 0x2d08e3a9 0x04447fc8
+ 0x5b8a7d2d 0x7feac814 0x49f424a3 0xf3875991
+ 0x7ba76639 0x15c5c756 0x351ce3b5 0x3f6c510c
+ 0x99f05511 0xbf82e8cc 0x3a08ff2e 0x27ce0320
+ 0x156823c8 0xea93277e 0xd4f644ee 0xed19db7c
+ 0x883aa3cc 0x477659d8 0x328f8021 0x5f5027be
+ 0xdc5dc6b0 0x7be0a222 0x3eeac5c3 0xd550feb0
+ 0xe536e7f1 0x286636de 0x853b327c 0x89c0fb10
+ 0xf3ca1f99 0xdfac434b 0x77629984 0xbf9089ab
+ 0x4c485305 0xeeb11fc0 0x287f76db 0x30930095
+ 0x6903c661 0x2b8cdcc7 0xdde71952 0xe608b18c
+ 0x92c949a1 0x8aad2b8f 0x65862768 0x9cee8ac0
+ 0x823d78c3 0x847136fe 0xd9310ed3 0xb8b42493
+ 0x29ace469 0x42888461 0xded8e619 0xdf05ba83
+ 0xbdff529b 0x200b50aa 0xa68969a3 0x852839f8
+ 0xe990c70b 0x4646940c 0x97d3cc15 0xfbc684fd
+ 0x670dc5bb 0x9221de80 0x4c8e6b5f 0x0d8e97a0
+ 0xad70fce0 0xeae31c56 0x285bf809 0xe8875db3
+ 0x90b80642 0xd3823067 0xcc83a749 0xf9ca429a
+ 0x67422236 0x1391a167 0x0bf82b36 0xc9765751
+ 0xe716e34a 0xe0a8a4f3 0x98c3a88c 0xc6e2f8a4
+ 0x7fac67f1 0x1dc95999 0x506bbfcd 0xca368479
+ 0xb40279c4 0x55bcf309 0xa33edb78 0x82136a30
+ 0x5b12a8f7 0x760c01d3 0x5db7a4db 0x74f5bbf7
+ 0x88d8cf63 0xbc44938d 0x3b8aa64c 0xa619841b
+ 0x938ef7b6 0x4e62db80 0xec29b936 0x12c88360
+ 0xd13fd368 0x049fedc3 0x980d670c 0x751d7334
+ 0xe275082c 0xa856923e 0xcf718388 0x91c05a55
+ 0x1feea2d0 0x973e9ef4 0xfdb50bdb 0xc9f0d356
+ 0x1fb535f4 0xac8935e1 0x54ca8daa 0x5236b3f6
+ 0x96077418 0x7cd145ee 0x4c3eac4c 0x96708111
+ 0x2d0d2818 0xdf8d4d8c 0x1e0dc74d 0x55563148
+ 0x8ded787c 0x8b23817c 0x2791cb6b 0xfe592eeb
+ 0xc291504a 0x594803f6 0x5cb40c93 0x0fb42830
+ 0xdc805110 0xa04177c6 0x5b196cff 0xa8389595
+ 0xc22006a4 0x48f63bed 0x956fe2ab 0x8326bac5
+ 0xf607d430 0x4db75e7c 0x5abe98f3 0x1ce11559
+ 0x9a6bf85a 0x38332b5f 0xd5d89037 0xc68921c6
+ 0xa0076717 0x7a8825e0 0xeca2298b 0x78202f5f
+ 0xe9fb2a84 0x0a190fbb 0xacd7c21a 0x7c1b5df8
+ 0x8bec1b4c 0x269507e6 0x8890150a 0xaba688e7
+ 0x3bfe89e6 0xa2b9f1c1 0xe073b921 0x8886f1ec
+ 0x8e70e13e 0x32a1a95e 0xaf7eb731 0x76ef3515
+ 0x4e90039d 0x8e469581 0x076c7437 0x136549ac
+ 0x357e3610 0x63a28516 0x19d505b8 0x43c971a6
+ 0x0472035b 0x756164f2 0xbe6062a4 0xa1c37b2d
+ 0xb07d2cf8 0x8476f6b6 0xc715da8d 0xb2afed44
+ 0x249f6d7c 0xb5d69bab 0xcebfac4a 0x79dbe92b
+ 0x27885a7a 0x36e23920 0x22974454 0xdb75e82a
+ 0x9ed157a9 0x66b7f446 0x8dd61b49 0x1ec542a6
+ 0x2f1602c7 0xfef7c1f0 0xf0e03fd1 0x7c5d27ba
+ 0x1aab9e49 0x320c70a0 0x8428e51f 0x6518c994
+ 0x4b1dd367 0x43e7759e 0x2e3a273b 0x02e96af6
+ 0x7d7fd596 0x76fb392f 0x01e0575a 0x34c3c159
+ 0x58ad09c1 0xff429aa9 0x542c728e 0x960c1be4
+ 0xd993a44d 0xbe66f3b0 0x097dffa0 0x63ffa221
+ 0x4e9d0eeb 0x059ac1e7 0xc8a98f69 0xba154f66
+ 0x4c32444b 0x16c6b875 0x90ece67b 0xac649e61
+ 0x9e8f0cf7 0x428e6df3 0xc9ceb8ef 0xa66bab0f
+ 0xd499148e 0xbc453d7b 0x10064f2b 0x839a2b6d
+ 0x8cf150bf 0xef4ff034 0x5f760dad 0x3ca17566
+ 0xc469b66b 0x59389505 0xe731e5ef 0x436cf37c
+ 0x07430a9d 0x4ec457cc 0xbb9b3569 0x39e66440
+ 0x51508550 0x14e9282f 0x9019d229 0x4f1f91a8
+ 0x52ed0975 0xb0f8c69e 0xc95dd930 0x58613f85
+ 0xef94c1bb 0x4763c396 0x0271e452 0x199cf8f5
+ 0xb5459017 0xd30a46f7 0x4a882adb 0xd81c67fe
+ 0x560d3066 0x1c54e221 0xcff36db6 0x10ba2ad6
+ 0x2a2f3b5c 0xb49815be 0x23d8e3a1 0x199ace76
+ 0x14cabe0d 0xdcdb74ec 0x7ba0ee4e 0xcd8ade16
+ 0x6fff6e9b 0xe7ebf779 0x3cd0d4bd 0x1d5988ba
+ 0x41a869e6 0x938f3f7c 0x1c32d1cb 0x32cd7d32
+ 0xd5f6c5b5 0x18f6ce02 0x355e6a02 0x1ce3fe19
+ 0xef2db61e 0x53569367 0x2143daf2 0x9ff48c31
+ 0xa8f2ae31 0xb942b0c5 0x5322e9fd 0x5c86f025
+ 0x4564eb04 0xbf84637f 0x72649b68 0xbcfa9479
+ 0x92160cd7 0x6a82f2ed 0x56e95854 0x8de8854e
+ 0x3a6f9ae7 0xc600810a 0x3b916a72 0xc7757b0b
+ 0x5c509f76 0x671a3e65 0x557be597 0xbfa43c40
+ 0x75ad1bd1 0xef6e4e5e 0xc925131b 0x0b23f0df
+ 0x8872d439 0xe7c68436 0x66948273 0x52c5820e
+ 0x8bcdd308 0x5961f832 0x8b9e05b3 0x1877dc15
+ 0x677c923f 0x9275f82c 0xb63ab226 0x2ebed52f
+ 0x709be956 0x029efa11 0x181b9d17 0x85b196bd
+ 0xd0ef2b24 0xdb40ed0f 0x64cd9131 0x6d4591ce
+ 0x39b07cad 0x5d93a4fa 0xc72ab75f 0x411c103c
+ 0x0e543f47 0x82326a56 0x97e74672 0x8ff175c5
+ 0xa4af4aa4 0x7d486409 0x3c4f0022 0x8c340a17
+ 0xbb78a4de 0xcd8347d6 0x3b413b09 0xc5ea0d4f
+ 0xc04924fe 0x775b3449 0x5177508d 0x7837f058
+ 0xad7585b2 0x04de4c25 0x62045a0d 0x795cdf60
+ 0x20895612 0x927248ac 0xdec3682b 0x5f624760
+ 0xd1eb3249 0x3c258434 0x5471ce68 0x63dfc40a
+ 0x972e356c 0x248921e6 0x2c6c68d3 0xc7934632
+ 0x21b3e041 0xe261b970 0x872c8f48 0xbc83ee9b
+ 0x7fc5365e 0xbf811695 0x7421fbf8 0x351251fe
+ 0x2fa69f93 0x1b0e076e 0x844620b6 0x34ae0b82
+ 0xb4397ce5 0xc8c334c2 0x3b83e4a3 0x9400ac98
+ 0x77ef3b8d 0x9e99a943 0xc9dea3e9 0xc79bcc15
+ 0x97adb857 0xcf3628a5 0x5fb9dcd8 0x1fb48b0d
+ 0x912814a2 0xd90cc6c5 0x8d41c708 0x31f3f996
+ 0xd3cdc511 0x3548427b 0xb61e440d 0xa37184ed
+ 0x4046b193 0xd4fa3e6c 0x49be92e7 0xffc4d769
+ 0x2a612567 0xc0e47c24 0xb4cd56dc 0x642e0d3c
+ 0x28f29fcc 0xade72ab6 0xb2b4e692 0x45f1d977
+ 0xf6cb5893 0xd5de01db 0x8e12fe1d 0xda7387d8
+ 0xe7ffe1a8 0x0b2dcacf 0x303d217e 0x755c391e
+ 0x182f0fad 0x5c3b4c52 0x005ea5af 0xce544cd8
+ 0x85a42ec0 0x5d7efb0d 0xb902ae0e 0x25dc0faf
+ 0x31f94bdd 0x4a3ea693 0xa3715564 0x356f9547
+ 0x10f6c847 0x306c053b 0x12a2b255 0xd12abc31
+ 0x692c4e07 0x26e8fe46 0x893e5fb7 0xd592abdb
+ 0x48135ecc 0x1c433483 0x83e52581 0xa984e767
+ 0xa65b1461 0x0d32513c 0x0932221d 0x0fcfb020
+ 0x20bbdc83 0x2fbad27c 0x9eb4a08b 0x947301a3
+ 0x7776ddac 0x04e8ac11 0x40e42a9d 0xaf74d77d
+ 0xc9e1e938 0x7af6c1d4 0xc8dc1650 0x24ad902f
+ 0xe009278f 0x905d5de6 0x638d3a74 0x937d4685
+ 0xaf0e95d4 0xcf1d2012 0xf9c608a0 0x6fce7bb9
+ 0x8b421310 0x23efaa4c 0xa52bdf67 0x1898d46c
+ 0x8f3834de 0xba7c2fb4 0xfe84eabd 0x0e66e78e
+ 0x1c636cef 0x8c9c5d30 0x665e1ae3 0x5eb5888f
+ 0xa832e9a9 0x8e9c37e9 0xcfb38ace 0x93ee97fb
+ 0x1c191d98 0x276c4d6e 0xd18ab928 0xf86a8dd9
+ 0xf975c062 0x8cc952c0 0x69c5f436 0xcd50d9d6
+ 0x916dd94e 0xfe6645cf 0xb7dacd07 0xb1bbc45d
+ 0x564b887d 0x587b5323 0xc0706aa2 0x14a7dcfa
+ 0xad918e14 0x27edb562 0x71467cc6 0x544931c6
+ 0xa003a9d3 0x9d5bc429 0x891c3a2e 0xa838c8ca
+ 0xf2e664da 0xd6e6fccf 0xa4a65c77 0x845eaac8
+ 0x5f15eac0 0xa0c6f671 0x6a506930 0xcc44355e
+ 0xe379041c 0xee2434b6 0xcd186246 0xf7ca9b32
+ 0x6150775c 0x6b8b53dc 0xc1c929fa 0x73747210
+ 0xa96bbd50 0x5e3fbb16 0xb10042d8 0xe0214515
+ 0x572302b6 0xd501abb8 0x39250387 0x95dee388
+ 0x50c64c16 0x799e94bc 0x323bde9e 0x0148ecc4
+ 0x8fa3aca3 0xbbab92ef 0xeaaa2864 0x59fc47d6
+ 0xe9973a97 0xeff10530 0x2ee64dca 0x26549b06
+ 0x0c8c2e08 0xae8e5415 0x3c40bbf0 0x89c50b81
+ 0xb4fcfba9 0xb9c4c555 0xf2968416 0x7091257b
+ 0xc70896ef 0xb3086b29 0x5b224365 0x516c78cc
+ 0xc36c7b04 0xeae540ec 0x7b50490b 0x1c0681ba
+ 0xdbdb6bc1 0x1892d735 0xc55d1f7d 0x43a13e09
+ 0x64fb4fc7 0x63d9f7be 0xd94a1264 0x7c29c0c2
+ 0xbc80d0e5 0xcc0f8ba9 0xd9ffcbe2 0xe6cbbfd7
+ 0xa393ea13 0x9c1d2cb8 0xf6b30c8d 0x774ab520
+ 0x902f1f82 0x591e8fcb 0x54a49a0f 0xea92775f
+ 0x32db070d 0x46871147 0x71db3643 0x46ec5752
+ 0x60b676d7 0x000e6315 0xda2f8ed1 0xa02774f8
+ 0x5b10b0c9 0x745201fa 0x64cdb756 0xdbac8197
+ 0x8ccda850 0x03376e2a 0x30b1bd37 0x40879940
+ 0x0a94a9fd 0x45f5a94d 0xd291c228 0x63e8dce6
+ 0xc0e92d5d 0x94f4af95 0xa6493cb2 0xaf6796d1
+ 0x1b92305d 0x90cb1f96 0x52b6a25d 0x60adaaa6
+ 0xc39b1758 0x90365599 0x1fd8ba91 0x9d8142d3
+ 0x35de6e66 0x8c3c97c2 0xe080a68a 0x0c1212a4
+ 0x432e0909 0x4617fbc2 0x8c64a51c 0x83cadb95
+ 0x61e751bc 0x5a1f6e50 0xc18bf429 0x44796e3c
+ 0x9196cb25 0xaa458f0d 0x17a892e2 0x0fa38b9a
+ 0x27d433ad 0xbf81824c 0xc554ecde 0x3e0e0ec5
+ 0x3d0507fa 0x8e01868b 0xe9890628 0x95462999
+ 0x78d3c488 0x7c11e37e 0x744f486e 0x382b91a4
+ 0x92b5aaa4 0xe5ced181 0x538c6405 0xef665333
+ 0x0f2c9006 0x817b1d64 0x8ed18582 0x4762ebed
+ 0x793e8754 0x7ffc1370 0x83e97a2f 0x0097efbb
+ 0x3af550b8 0xe8b5d326 0x1328badc 0x1b876137
+ 0x87d0a5f9 0xa886af93 0x84d82661 0xd59c25a7
+ 0x9436457a 0x33657675 0xc2e84838 0xb69dfb0f
+ 0x7cd5f62b 0x4aefc230 0x55dfae89 0x09303273
+ 0x99df1289 0x91a8a253 0x308c3493 0x82ffc531
+ 0xbe46de4a 0x95018289 0xb3f1484a 0xfab68007
+ 0xda22a10f 0x52dc5477 0xc6c0cd11 0xd7432402
+ 0x66b3b9b9 0x2d9e453c 0x61b9f88f 0x7c0eb965
+ 0xcfea53f6 0x2128bef3 0xc70cd033 0x0b64e589
+ 0x83b6c8fe 0x90f7f205 0x746ad9a9 0x60dc76f9
+ 0x8853da22 0x77af258d 0x392bbcc6 0x4bbcee30
+ 0x5109f557 0x6a54ad0e 0x8f88d2a7 0x26b23261
+ 0xaacf9560 0x8fee9392 0x2305214d 0x700c4bc7
+ 0x5e6fa646 0x81c09c02 0x124edc15 0x0952d2c5
+ 0xac95aaa1 0xc942e831 0x59def5cd 0xf973bca3
+ 0x8804722d 0x35b6502c 0xee05d2d2 0x47df0499
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+ 0x1542f8aa 0x22fdc4b0 0xce0727d9 0xc00509c0
+ 0xe2e9da83 0x85e58cd3 0xc3a4cc2a 0x05b733d9
+ 0xd142b1b8 0x9b50b224 0x24a4f235 0x7e26e4ff
+ 0x72d74616 0xa8118811 0x845249c8 0xb385bea6
+ 0x9ae48f64 0x4f3fc38c 0xfb92d503 0xb348fd91
+ >;
--- /dev/null
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x40a>;
+intel,date-code = <0x12182015>;
+intel,processor-signature = <0x406c4>;
+intel,checksum = <0x5807e19a>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x0a040000 0x15201812 0xc4060400
+ 0x9ae10758 0x01000000 0x01000000 0xd00b0100
+ 0x000c0100 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x0a040000
+ 0x00000000 0x00000000 0x18121520 0xe1420000
+ 0x01000000 0xc4060400 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x624800aa 0xf01ac54c 0x5a84228f 0xcc79131d
+ 0x9feff6a3 0x4a87b5a3 0xac874956 0x7dfe6197
+ 0xef44e4c3 0xf91d4958 0x230883b7 0x7382ab6e
+ 0xf14324ef 0xf94c28d7 0x9131d196 0xebcf2faa
+ 0xc049cb37 0xd1577abd 0x5edbe45a 0x17e1ca1e
+ 0xbe9a92c3 0x1c8e1790 0xb3c08b8a 0xca799851
+ 0x3f2a8c92 0x1b7e15d8 0x1f44ecb2 0xaeda1838
+ 0x0ace8669 0xae9d497e 0x424c680c 0x21b3a3ed
+ 0xd924acfe 0xddc126a2 0x26363596 0x21cd999b
+ 0x193f9df3 0x037d1953 0xf97a3dc5 0x4c94ad7e
+ 0x98b360f0 0xeb90461f 0x438e6d2e 0x30851a0e
+ 0xfd623681 0x18782d3c 0x702938c5 0x462df0dd
+ 0xf7d67cc1 0x161076a0 0xf06e5db3 0xd861a76b
+ 0xa40b06bc 0xed37c69b 0x2b25f98b 0x2b67887d
+ 0xbf0131b5 0x571b7c25 0x34eb3752 0x992e406e
+ 0x031ba8e7 0xccfc5b1d 0x33f487e9 0xeccc3098
+ 0xe452737b 0xb38cc286 0x817bc58f 0x852a7fde
+ 0xcbcd1b19 0xab11894a 0xa1f278d7 0x360829c9
+ 0x11000000 0x242e4460 0x190ba541 0xd3a20d0c
+ 0x7de0fc1d 0xafbe0a08 0x3233d6f4 0x82d82901
+ 0x12c67fea 0x927c5686 0x8d45c03e 0xdb650016
+ 0x88e39816 0xa493cdea 0x81a87c12 0xadbd5724
+ 0xd402794b 0xdde114da 0xa32c6058 0xd820b63c
+ 0x712726d9 0xf99787b2 0x1b8628b6 0xbd4c94ff
+ 0x70952446 0xa00d56ba 0x36911787 0x5f3ca7d7
+ 0x7cc87a67 0x10c77f6f 0x63bb3eaf 0x85f294d3
+ 0x3283b281 0x71c85eb4 0x69a72f05 0x5e0f08e0
+ 0xdedd727a 0x8f300d0e 0xe1998f90 0x340f0e3f
+ 0x8ce037fa 0x801f7160 0x671b364c 0x09c2ba50
+ 0x6d506296 0x4760ba91 0x046e581b 0xd5711e70
+ 0x58c7279b 0x4376b9b5 0x63cabe1e 0x9c22ec14
+ 0xb6752bf0 0x1b4da16f 0x09a0c65f 0xc6dbaf78
+ 0x04e7d9aa 0x20895400 0x9516e20b 0x8cb87942
+ 0x16f1e580 0x4dc7b3c0 0xec4ea2a3 0xd57a22c3
+ 0x51306f3f 0xa9ef572d 0x261efc37 0x9d9e7b4a
+ 0xe3024514 0x4a2e2c58 0x3a77c165 0xafab4790
+ 0x6ce34d1b 0x04f0ab75 0x2d437f08 0x1d790312
+ 0xbac94faa 0x976b9ce9 0xf770def7 0x6ed8427c
+ 0xce8a6521 0x1ec7251b 0x10379d55 0x882b8ef8
+ 0x58c4e197 0xb2c48b35 0xb3311655 0x8ccdf15a
+ 0xf4368e46 0x5e41fe36 0xc6eae59d 0xe4b01c2d
+ 0x506e5bc1 0x522095cb 0x32c19087 0x67d400ab
+ 0xc46ca675 0xd1b4dc87 0xc41aaf74 0xb75e5de1
+ 0x53588482 0x6e168b15 0x3cf9d2eb 0x2a26c991
+ 0x868d92e6 0xefd21291 0x0d7d393b 0xd28a6693
+ 0xbf850f8b 0x8bab78fa 0x06ef9ab5 0x96bf071e
+ 0x4de55407 0x72997fcb 0xc6416709 0x9ba6d026
+ 0xf8d588bc 0xbbacd314 0xdbb65892 0x49ce4e3f
+ 0x9f7f23c6 0xf3bfb271 0xe3b039ef 0x9721d9d2
+ 0xcfeff460 0xf9770555 0x8ecbd41f 0xdbc8de19
+ 0x7f16eff1 0x50702a87 0x4e893e88 0xd0fe5546
+ 0xd75c268d 0x3b325a3e 0xccb8f848 0xf116b116
+ 0xd53bc36b 0x69c3fbca 0x78fca5a7 0xde29e62a
+ 0x087fe22c 0xa2341056 0x4d8e470c 0x0897e8e0
+ 0x1231c549 0x29fe1948 0x1510df78 0x27dfdf9f
+ 0xfa7ac39d 0x02a2d8a3 0xf4e92fcc 0x65f8a856
+ 0x0a620586 0x9d8168c6 0xfc2b73e8 0x51aa73cf
+ 0x790d1ff2 0xe2eec1ee 0x2b6bf6ae 0x016d719f
+ 0x4299ce1e 0xf5b6fb08 0x616eeef7 0x58e7838a
+ 0x983a59c5 0xaab03473 0xb493c5cc 0x8f895d01
+ 0x7eeb95ed 0xc751e74b 0xd56b648c 0x73397d44
+ 0x2044779e 0x76ebf0ac 0xde6e453d 0x314e2211
+ 0x75da63a0 0xaebc257e 0x3ed500ca 0xcb90731f
+ 0x0e061298 0x202e853c 0x5475c57e 0xf7d590c9
+ 0x50d855ad 0xa9a1740a 0xad86458c 0xac935753
+ 0x443950f0 0x679449c7 0xfecdc458 0xda126f52
+ 0xf95db8ad 0xce83faca 0xd50e170d 0x8985c89a
+ 0x21300e90 0x45681348 0x77d41f24 0x7771eae6
+ 0x7c649019 0x776f433f 0x1176f3a2 0xba7771a5
+ 0xac9add02 0x80a77d73 0x9d532385 0x32a3bf43
+ 0x3812be26 0x5f0b64e2 0x661150bf 0x1cda3da3
+ 0x25901706 0x5566fc2a 0x4196324b 0xdaf55897
+ 0xa182d0d1 0x27753c5c 0x7ed91479 0x670dd712
+ 0x79f5e8c5 0xc2a882f7 0x99387af4 0xfbc30997
+ 0xb2cbb413 0xe205d416 0x9c380f50 0x3ba30c90
+ 0xf80b317f 0x06b74c14 0x5b8780de 0x98735ad4
+ 0x335d6f43 0xb2de8a5b 0xeab51ec0 0x6b9bb87b
+ 0x49f621d9 0x6dee0720 0xa5a5fbf8 0x576383ad
+ 0x8d9fb03e 0xc7c6836f 0xc2b98f2a 0x157973e9
+ 0xc3054865 0xb5d5a8f0 0xb2a939d4 0xda7d660c
+ 0x5bea5713 0xcd9fb93c 0xd04225a5 0x469c6ef5
+ 0x6e1b2189 0xec2038a5 0x48d864c9 0xf96ad8b8
+ 0xc311c9f4 0xf293d447 0xda23084d 0xc0cec16b
+ 0x4fa98f1d 0x1d65cb44 0x25241ce4 0xec6e71ba
+ 0x5c060508 0x864e7590 0xa7bdf4df 0x05fb9183
+ 0x70a2ed5e 0x8a7bdfd5 0xea411027 0x19a6c9ff
+ 0xcbbc17ac 0x401aa669 0xe6bf3370 0x72f681cb
+ 0xbe77a1a9 0xbc6ae060 0x8378299a 0x926ee257
+ 0xff603c73 0xdeecde51 0x519d6956 0x5c4c6dd0
+ 0xfd29f3e6 0x846667e5 0x2105ef33 0x158f5778
+ 0xb894867e 0x162fe780 0x70d1570d 0x27ce89cb
+ 0x3bad8e45 0x439d8dce 0xe8667d8b 0x4d47880a
+ 0x652c7019 0x5f414acc 0x4339c1a7 0x833ca27c
+ 0x32c92aa1 0x243b00bf 0x8e50fe5f 0x7efc7591
+ 0x2e0d41f6 0xc67c978f 0x87f2eb1b 0xdcf5e604
+ 0x801c6f5c 0x3caaf323 0x82d252d6 0x99fe2e39
+ 0xb76a1e41 0x134d9628 0xfc095714 0x45a0825f
+ 0x48c60f59 0x2c959a36 0x3d60f4d7 0xe24a8f04
+ 0xa3b5f596 0xd9e67450 0x186af1d5 0xa1a1bb77
+ 0x031cbf72 0x273f96e1 0x6938dbd2 0xc9613d71
+ 0x786056b4 0x41bfff37 0x90dc1359 0x88291b7e
+ 0xe087ea2f 0x2a307121 0x8f9ce425 0xeaf83930
+ 0x63b737a2 0x63e23ab1 0xbfd9e458 0x423603de
+ 0x3fc30a6f 0xcb6142e6 0xa64299b4 0x61c68b5f
+ 0x1ba06ed2 0x91887c3e 0xb9aff67f 0x64784f73
+ 0x34b0824c 0xc12f97e1 0x94441a34 0xd2080b65
+ 0xe1c21c9a 0xa74732a0 0xefa59483 0x5d8a01a7
+ 0x1dd6c22e 0x4d480d8f 0xb63a8354 0xa72c3581
+ 0xf1df301e 0x5b3f517e 0x26b2082b 0x2b41052b
+ 0x9154629f 0xabc7702c 0x1025b356 0x9e85e8ba
+ 0x1f544d99 0x2c8ec998 0xe4440160 0xb0deb1a3
+ 0x201e3fe8 0x70a7792c 0xfcf41de1 0xe2b2e6aa
+ 0x10fc055b 0x373e9fbf 0xffee3e7d 0x2d1baa79
+ 0xdb411a57 0xf30ea568 0xe30497de 0xb4682d8c
+ 0xb458fbd2 0x5d1d68de 0x02da095c 0x71471bce
+ 0x543edc68 0x52187bde 0x98743b08 0x0674aa49
+ 0x5dad1705 0x74b009a2 0x765840c7 0x3e1cf377
+ 0x3ecbb54e 0x6d5934b9 0x8a67c9ac 0xe1a15fbe
+ 0x6e096703 0x24fbe4b3 0x99c9e345 0xd2d520f3
+ 0xc5aefea5 0xe9e828b9 0x4e8f47b2 0x92653def
+ 0xa7b8249d 0x5f53eb02 0xe3233073 0x1c933c46
+ 0xcb682c30 0x7e6e4f1a 0x42015257 0x8cdb5897
+ 0xc9cb6caf 0xfd8834a4 0xf353bbb4 0x6a37526a
+ 0xadf7562d 0x151f071a 0x960a244f 0x7ca3adb3
+ 0x9408588d 0x54bfc516 0x8b66a80b 0x2ed849ec
+ 0xf408d6f8 0x20bf2961 0x38131c67 0x79f4be5c
+ 0xe439ce8e 0xa497411a 0x75e67d7b 0x89e55132
+ 0x5775d8d7 0x945cfe97 0xcb3fab49 0x0f776050
+ 0x6a6d6600 0x669e6d18 0x9e919045 0xa4fceac8
+ 0xcb9cbb97 0x44ff0303 0x5ab4c9f4 0x6356e012
+ 0x153c7cfc 0xd6e436eb 0xff02c626 0xb8c6b9a0
+ 0x649e7186 0x7ca5666b 0x7d79feff 0x96a659b7
+ 0x52c99b9d 0xcfc545ff 0xe694e092 0x0978951e
+ 0x23c1fa45 0xa196acc1 0xfa43a0e7 0xd02e58ac
+ 0xa437a7ed 0x928bee99 0xab7a4203 0x476afb0e
+ 0x85720b30 0x24c1aa4f 0xf0f5aa46 0xb370c71b
+ 0x72c28056 0x6476c6bc 0x371e15a9 0xf1dd6370
+ 0x20c99f9c 0xd41af717 0xed13673c 0xcb6c24c9
+ 0x76d3038f 0x13ca83ec 0x92f89264 0xf15f7b8f
+ 0xf58caccb 0x8c35c1e3 0x09ab9fbb 0xe43b29c3
+ 0xab4ea87e 0x38115de0 0x6907638b 0x42348cc1
+ 0x46c0541f 0xce20b070 0x85f96b9e 0xfa6a55e2
+ 0xde7508eb 0x9f8f1b4f 0xed64d64c 0x440fb418
+ 0x58ddfb97 0x13762796 0x7a19e78c 0x1f4532a2
+ 0xd77581f6 0x95d2e36e 0xb43f3e07 0x4ee36289
+ 0x8e02424c 0x59413984 0x25a857b1 0x85d7f421
+ 0xad16de66 0x89889e00 0x41a2419a 0xaa4d9734
+ 0x054c611b 0x163792a3 0x5024a4a7 0x28e8c480
+ 0xd8d0a170 0xac2789b6 0x9e901eac 0x8dd4c756
+ 0xb7e7a78a 0x09cb2f8f 0xcefbf036 0xd76d6b90
+ 0x97195548 0x2cb9a698 0x0d8bf470 0xd47a53c5
+ 0x7cde7ca3 0x86752d36 0x2b247ff0 0xf88824a6
+ 0xffa16b3b 0x6cdce7fc 0x3b4616a0 0xa10175d7
+ 0x9582056c 0x430e2b58 0x87fc2c37 0x9f6e818c
+ 0xbc1139f1 0x84760da0 0x27a89d38 0x71c5e1af
+ 0x131dc64a 0xadd87cc3 0x1e803420 0x742fd011
+ 0xd72bd1db 0x0fb75ab1 0x94b49dee 0x72c056ad
+ 0x5e6792a0 0x6d555dd0 0x74b1b90b 0x6ad51aca
+ 0xfabbeff2 0x100ac64a 0x4809c8d9 0xc34c3576
+ 0xea9e97da 0x16e7c254 0x67bb276e 0x051352b1
+ 0xa876828c 0xb9050b68 0x220b1342 0x194adca9
+ 0x91c155a0 0x13840fb9 0x3d84c855 0x0f556748
+ 0xec5c095c 0x843a3203 0xa481fa2c 0xfab143e4
+ 0x21644052 0x8c78b21e 0x9aebfce8 0xec06d25f
+ 0x3de84e4f 0xf6fcc4ff 0x14939e02 0xdbc002bd
+ 0xaf9bb5fa 0x2b2577ec 0xb58e2198 0x8695c42c
+ 0xbd4134b3 0x339ad83d 0xb068e618 0x55a79546
+ 0xa9d25584 0x8c2686dd 0x65c1fa6c 0x1b923e1a
+ 0xf85508f1 0x35405141 0xebc72b0f 0x61dad5d5
+ 0xd494ef56 0xce496144 0x95ac0f6a 0x22feb180
+ 0x314fa6a2 0x6fdb5569 0x3b545d45 0x04993ded
+ 0xcbde0b29 0x79f8402e 0x438f03a4 0x697a2395
+ 0xa60c9399 0x6773e016 0x0239bd45 0xb481fb75
+ 0x9fa5c550 0x411ef264 0x67860ed6 0x27b2c816
+ 0xb51d6798 0xad6fd700 0xc3bda74e 0x56aed35b
+ 0xd8c5ccc3 0xfe5f41e4 0xd6bf9729 0x823aced3
+ 0xea7be38f 0xab1dc712 0x5cd0bf3a 0x668a68bf
+ 0x28456fbf 0xa2dac02b 0x20ace936 0x95b0ba3d
+ 0x377b8a1e 0x0dd9c396 0x3c7f2925 0x76818503
+ 0xc359dc77 0x00ac4c3f 0xc51174cf 0xc75b0427
+ 0x9cddf343 0x5976c090 0xb940ae71 0x67b3149a
+ 0x2126db25 0xa0c32f5c 0x0d4478ad 0x7fefc9b0
+ 0xb142782d 0xa150a3cf 0x64ad041f 0x0fca8532
+ 0x0e8e5348 0x969950ad 0xdd3d8704 0x8ae1c3d2
+ 0xc9110da4 0x8d1d9e53 0xdcf5ccd2 0x283b2954
+ 0xe9bc7d4c 0x4e3dacfd 0x2101a11f 0xc8931fcb
+ 0x248a7c32 0x2f1bad2f 0xa4d4ba90 0x842d6a97
+ 0x9688a63e 0xca0c8ad2 0x9f580417 0x46e7fd85
+ 0x2d3ebc79 0x47aa9462 0xebbe843f 0xd78153e2
+ 0x909560b2 0xf46c5e3f 0x7c290a30 0x56b869f4
+ 0x41fd075e 0x0a5b6e52 0x36d2d38a 0xd18b2b9a
+ 0xce905361 0x421cdd95 0x8a12d791 0x95ffe01f
+ 0xa0164308 0x49a9ee60 0x1905f05a 0xd7d654a1
+ 0xf3231a7e 0xd0576e98 0xc24f44e1 0xe2860d3c
+ 0x391bd3ef 0x9e69bf4f 0xe72c6172 0x59500290
+ 0x3d34636c 0xbd04b4fa 0x895b8094 0x5cc90dd3
+ 0xc199504e 0xe9fd3199 0xbc45079f 0xe90b08d1
+ 0x73e17406 0x28173cdd 0x99cbd64a 0x7b6d0f22
+ 0x841d5dfd 0xdf5ac032 0xd4816d36 0x1f4a3984
+ 0xeae96366 0x50ed8bb9 0x4d33650b 0x7128cee3
+ 0x37277426 0x471cdd80 0x25fff263 0x6f474b74
+ 0xe9aa07cd 0xe1d7efb2 0xc22815f8 0xc608745e
+ 0xdbefd2d1 0xd153fcb5 0x6e6bc7f9 0x4882ccfe
+ 0xc81e1310 0x81cbd86b 0xbababff2 0xd907a1fa
+ 0xcd8cc1fd 0x6189dcb3 0xc09856b7 0x561b5eb7
+ 0xca1a86ca 0x44d14be5 0x09e0d9b1 0xabafa3ec
+ 0xb195d7ee 0x6bd4ac69 0xd96ca290 0x4646b3de
+ 0x946a8de5 0x62e7811f 0x8576b1df 0xd801d15a
+ 0xea3b3d1c 0x4b5d2213 0xac6d698d 0x4e6688ba
+ 0xa8bd3c7c 0x61b00447 0x636290b7 0x21ea494d
+ 0x3f54301b 0xf3fd3625 0x761ee539 0x940e3e52
+ 0x83170a07 0xd22f0a78 0x953dec00 0xa38ab91c
+ 0xf92c8998 0x67009969 0x87672384 0xe491f9cf
+ 0x6b6ddf09 0xff109fa0 0x76a8b76a 0x180ee54d
+ 0xcaeb9a0a 0x92c5648f 0x85ff11e2 0x9b2df67b
+ 0x4201d9b8 0x8aaf347b 0x4a9dbe10 0xec862b6a
+ 0xb71c8b69 0x18b610e6 0x74308a4a 0x48f932f0
+ 0xab89e3cd 0x7c8f0ea8 0x1bb5f1bc 0xcdb4357a
+ 0xaaf85d77 0xade08dcb 0x590d0607 0x193b1e39
+ 0x4a2c0ad8 0xb537ede3 0x18028be0 0xdfdc9b3e
+ 0x4ed44a28 0xd99088fb 0x5f463afa 0x30b3406f
+ 0x9a841acc 0xe99b8e91 0xd7b8a939 0x681ffaa2
+ 0xadbb1fd1 0xfcad4167 0x0112b6f6 0xdc7f9eef
+ 0x9fe2e8c3 0x2a6c0b92 0x52455d9c 0x6c8d1640
+ 0xbde4c4f8 0x898f0c75 0x888be513 0x547d135c
+ 0x1eb060b3 0x065d0c94 0x29dccb26 0x7e8c7b31
+ 0xa5447074 0x284dfd0e 0xbf1d6663 0x18c99457
+ 0x00347d9b 0xf61a7399 0x97295200 0x5b8496d1
+ 0xcbafa538 0x5d98baf9 0x90cee1e6 0x96ff22c0
+ 0x18c2a3ac 0x543af7ed 0xeea413c6 0x5bae5343
+ 0x8e448ca0 0x6e7d4242 0xaa3f43ce 0x28215051
+ 0xf64810cd 0xb5a7e727 0xd7f81460 0x35308099
+ 0xeebca740 0x01df1f57 0xb7e65871 0x3ab3b9e9
+ 0xee122b31 0x1ac1db5e 0x5e99528f 0x564692be
+ 0xea2b238c 0xfee52d82 0xbf986e8f 0x822c1414
+ 0xca6d9632 0xf9a2f73b 0x26991573 0xdf31a166
+ 0xefd371c8 0xe6a8c9e5 0x98ec2cd3 0xe36a2f4b
+ 0x64f72616 0xa7d08fd6 0x93363a09 0x05601635
+ 0x1f525f29 0xd63ac5e1 0x6a09abe8 0x3992b4fe
+ 0x1d0aaeee 0xb32d924e 0x2d364a4d 0xcc3676a1
+ 0xa3570ad3 0xcc42a28e 0xe1209e02 0x5a7a939e
+ 0x8baae5a7 0x37970d2e 0x9ad75409 0xc3fe31db
+ 0xcbb9e37f 0x00e73ed5 0x03d10ffe 0x7e1abed0
+ 0x6184e0a1 0x04dd9992 0xe1a4c0ed 0x1accdc34
+ 0xf75029e1 0xeb908c2d 0x7182338b 0x153c755d
+ 0xbd920e61 0xb7d99e35 0xd76b3cfb 0xc48e4427
+ 0x4918ffa7 0xc3f70d6d 0x7d5b47d4 0x20e585e5
+ 0x846d305e 0xd1953927 0x9ecd3367 0x7ea7af8d
+ 0xb99c02b9 0x9ff7bcb9 0xe2f9dd77 0x91f7c422
+ 0x0b6d6df5 0xb52ee017 0x0c7ac175 0xba7f84a3
+ 0x940030e8 0xf3361cf3 0x2c79691e 0xf9f4cbb6
+ 0x2adbcc7c 0x4e3216fa 0xeed50c23 0xdfc14253
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+ 0x03abe771 0xe0cfdff2 0x02b946f6 0x3e28b51c
+ 0x00d1a074 0x630d047d 0x3774bde0 0xd54d848f
+ 0x519df7c8 0x2f795cdd 0x2be0979a 0xffc9336f
+ 0x865b9fe4 0x989ef40e 0xe8e1937f 0x70c73c37
+ 0xd47ce2c1 0x84747455 0xd29ffe8f 0x7d5f7e59
+ 0x54503948 0x33a43626 0xcb21bfaf 0x372754eb
+ 0xf4e9fef0 0x7ef72486 0xea5981f7 0x6f460236
+ 0xe562a5d5 0x50529138 0xe6a53b06 0x39b362e8
+ 0x84899918 0xb9748fb3 0x8263ef83 0x5c6a28e4
+ 0x081cc763 0x5635c0bd 0xf45de0a9 0xf676e138
+ 0x70358031 0x0c96d004 0x9c7a26bd 0x621f7620
+ 0x0f5f2d5d 0x4b884b34 0xe97c5049 0xc3dc680a
+ 0xabd96144 0x581eb22a 0x9a21e4c9 0xa65945a9
+ 0x3cb2eb06 0x198dfbcc 0xeed765e4 0xa79433b5
+ 0x1eab8e7c 0xaf0caa85 0x1f64e75d 0xe5ac6d33
+ 0x566cb0bc 0x99a1dd23 0x07488351 0x20420ef8
+ 0xee4c584f 0x4b16ec16 0x9c22d1b6 0x0677a344
+ 0xd675b2e6 0x3699da5d 0xfcd9c9a9 0xaf39754d
+ 0xc20e780f 0x6a313594 0xad4d8e05 0x0b745217
+ 0x1caeeaea 0x8d33c5dd 0xb5134401 0x25897152
+ 0xabc5620c 0x5c6a6e2f 0x7f9bfcc6 0x4e23c064
+ 0x915851ee 0x10cde250 0xd43ce4a3 0x77e3d669
+ 0x83c5acd0 0xd556601c 0xb4b9b0d1 0x5fc0197d
+ 0x6fe1b764 0x98736a2e 0x8f9c5d6c 0x5a3c73a0
+ 0xbb9223e9 0x477fb96c 0x76e212d4 0x852c7448
+ 0xe3df0ebd 0xd26e786d 0x5adf03f2 0x43a19194
+ 0x39e95e1e 0x312c2c01 0xf28f5bb9 0xad9b066a
+ 0x50c6804c 0xb3cb2412 0x27736125 0x2d75b115
+ 0x878b9808 0xcee5e550 0xd3b21a84 0x7f73c6f6
+ 0xf31048f8 0x9c27baf7 0xcbe28ae5 0xf16f55e8
+ 0xff1d883a 0xb917dee3 0xd84bcba9 0x99d9bc06
+ 0xd3254c6e 0x913fb216 0x33bae4b3 0x3ab2b856
+ 0xe40edf7a 0x3f8e9842 0x6dcb2c20 0xb08a42bb
+ 0xf82b32bc 0xd6e65b9a 0x8280902a 0x13bde0c4
+ 0x5749ee1d 0xe09a44f9 0xa1ed7a47 0x92325cb1
+ 0xba37e230 0x08bf455b 0xf7a8e6b1 0xf999b250
+ 0x279eb5f6 0xae471b0d 0xe3ddc073 0x99a4a6d4
+ 0x6f0c9b2e 0xea2ec118 0x6930dd92 0x76f731fd
+ 0x3ced82b8 0xac77a11c 0xf6d40ae3 0x9709b288
+ 0x066bee60 0x366e4442 0xc682e70b 0xcf3f5ee6
+ 0xeb669330 0xb2bfec9f 0xd9d02229 0xe506c12c
+ 0x5c499813 0x1acd8364 0x5dea0305 0x11b8cdcb
+ 0xae9d46f8 0xe92f7cff 0xe47da028 0xa96b7996
+ 0x3c24981c 0x8218d0dc 0xcdc423f8 0x5783ec85
+ 0x71031f87 0x75f91d5b 0x7dbd9347 0x89320bd3
+ 0x44ea6e5b 0xf52fed47 0x8cfba940 0xc568ba2c
+ 0x32e64a48 0x467f2af2 0xe1c81736 0xd677c3c4
+ 0xb691033f 0xf05f91ae 0x3ab34af4 0xb7f77aa8
+ 0xec235606 0x2dd4f5d9 0x51918489 0xed4ccd82
+ 0x7388c7e8 0x1b4c953d 0xa4dbc23d 0x47f6896e
+ 0x5df966e6 0x51077388 0xdc110c3d 0xd784b6d1
+ 0x16a759c6 0x23e10e0e 0x1ff60d5b 0xc8a0b014
+ 0x23b0bac1 0x99a220ef 0x53af8b8c 0x07ac467d
+ 0xc906cc36 0x3f94abe0 0x175fd4ec 0x18d9644f
+ 0xad6ea521 0xb6c70a07 0x32f6af52 0x9f62ad48
+ 0xe1f3d447 0x407b2768 0x1e081391 0x29a24dca
+ 0x92d3b535 0x2a445762 0x066c94fa 0x6da4b159
+ 0xbcb3c6e3 0x67127ece 0x75cb186a 0x31c96430
+ 0xa8bdacd8 0x8e73d453 0xcd809a5c 0x6e651761
+ 0x6b594127 0xff12aab7 0x91d08ff8 0x86080248
+ 0x52107544 0x80894884 0x05e57b3f 0x80cab344
+ 0xfe8e16fa 0xf65fe16e 0xe2265c3e 0xe2cbb1d6
+ 0x7330dbd6 0x2c9535e6 0x6a1e434c 0xf575b138
+ 0x7a6f4b59 0x24fb8bf5 0x62502c89 0x92e0442b
+ 0x5c77ab13 0x1d83ce27 0xfa7e3916 0x5eb18873
+ 0xcc314bbb 0x9d641295 0x7fff5b4f 0x10cf0507
+ 0x4bdf7795 0x77536166 0x6746a004 0x4886b845
+ 0x5aa46f6d 0xe30d9ba2 0xef7f14e7 0xdca44530
+ 0x0516615d 0x43927969 0xc80235f7 0xd8473012
+ 0x8b4b2e12 0x841ec702 0xfa110fbe 0xcad703e9
+ 0x5df65ee2 0x947b7c2c 0x7cac7cfb 0x3282a0b5
+ 0x5c67da3b 0x71459bfd 0x91b055db 0xc951eeed
+ 0xde06eeda 0xaaea5aca 0x08d9226d 0x1e0c0b50
+ 0x44ae07b8 0xf037265d 0x823100f8 0xa642e2e5
+ 0x7f54061d 0xa0026339 0xbd969e25 0x51eb6051
+ 0xb7b2b522 0x7e3a0bd7 0xd8116971 0x3e973442
+ 0x8cdc35f3 0x0d108320 0x7a2f92dc 0x2c94b7a4
+ 0x6ab06326 0x50b9b16c 0x9bb91308 0xacd38150
+ 0x05922ec7 0x9f48a633 0x8e72317b 0x41b59d8c
+ 0xc6cdfe4c 0x2f628aac 0x3874bd08 0xb4e572ad
+ 0x7649260e 0x71b6aaf9 0x39dab510 0x858f965e
+ 0x322ba132 0x58c33983 0x25f5a5c5 0x45131737
+ 0xc9efed2a 0x43dcdc7a 0xb8176559 0x62a26ac4
+ 0x1ee7c5b1 0xc0f02a9b 0x26dd7616 0x8d0c377c
+ 0x9c5c57c6 0x06edf20c 0x22ad4eaf 0x5bddddc4
+ 0x7e221c25 0xbbec97e9 0xf82338e3 0xbb5c5916
+ 0x65885430 0x962077de 0xe52142ec 0x4c10a5a6
+ 0xcbf19d91 0x825cb043 0x21b49df1 0x1407f2c4
+ 0xa3cc17b2 0x796ed4ad 0x1859e928 0xeb9f55d2
+ 0x2f5fb606 0x4ef1bf74 0xa00279f9 0xc9fa2517
+ 0x925d9a77 0x164beb20 0xc4c52a47 0x3cd6b3f3
+ 0x607d07d0 0x1791803c 0xe82123a4 0xe2409ff9
+ 0xbcafaa43 0xd4809fe4 0x0ff22683 0x7ef4d5f9
+ 0xf67098f2 0x215173e0 0xe84b651d 0xfff97430
+ 0x9117caa5 0x9701e965 0xfb41af2b 0x2de0b345
+ 0x863219cd 0x57dbfb08 0x5ed9878f 0xda9848c8
+ 0xbd6a3e2a 0x78cee879 0x65a9ae31 0xd265ab5d
+ 0x4d8d0a94 0x53fe3477 0x163a9807 0xe6ee333d
+ 0x230ec18a 0x805befb4 0x28c735f3 0xfcea12a8
+ 0xdfb36088 0x6d71eeda 0x526509a0 0x97c07aa7
+ 0x505217dd 0x471bddf6 0x861c2251 0x1d4de90c
+ 0xe9b9c550 0x4741fb3f 0x67d594e5 0x0f134eea
+ 0x122daaee 0xab9a4171 0xf3675a04 0x68226f18
+ 0xdfeb2219 0x2d558e8d 0x3520077b 0xbd89e17e
+ 0x55ee30f2 0xe89bb5dd 0x5cd339a2 0x23671683
+ 0x6ae7fef5 0xff85343c 0x24592a20 0xaf79aa20
+ 0xa32c6711 0x2fe7d13a 0x3f582a56 0x575b9049
+ 0xd117d4a2 0xfe150bcd 0xd3598397 0x3df2fab3
+ 0x1259b6fe 0x7f9137d9 0x6911f18d 0xafeeeb77
+ 0x1c9c05ec 0xef1c1316 0xdc90bc14 0x3f084ebb
+ 0x197022a5 0xc723baef 0x8d956a3a 0x98b49ce9
+ 0x368f3198 0xa9542710 0x0d9b0fc8 0xe8940414
+ 0x0e4a345f 0x93d03091 0xb91a177c 0x166de3e9
+ 0x0497a17f 0x3b179d21 0x145bb508 0x59dcefdc
+ 0x6c00b488 0x48c5b25a 0x11ac5ff2 0x791caabe
+ 0x2a69fdb6 0xd4e828bb 0x495a2e26 0xafdbfbb9
+ 0x44a9c4de 0x203ebc65 0x41783cd5 0x5eec8a1a
+ 0x1b0107a4 0x8ee93772 0xa5342616 0xd1aeb1a2
+ 0xeb11eea0 0xa2db8d0e 0xd887bf86 0x2328668b
+ 0x6f047abb 0x1a016056 0x02792c95 0x743580e9
+ 0xf597f3d6 0x48169911 0x0fe7e92a 0x0d7bdd58
+ 0xf7a6dc2b 0xa928427c 0x52ad1483 0xaf181b83
+ 0x129dc832 0xf771c658 0x9fb4882e 0x491bfd60
+ 0x756e61cd 0xad7191fe 0x1ba10ed9 0x3cf91d75
+ 0xe635f99b 0x8182d8bf 0x2567117a 0x7a9c16c6
+ 0x79f4ec31 0xa0422381 0x75a6ee79 0x17fcc09c
+ 0x093dac9f 0x5d86884a 0x47294d64 0x9bbbbbb7
+ 0x8188504d 0x499bde9d 0xac5f4d4b 0x230012a6
+ 0x06e74e6b 0x9a2af42f 0x28786631 0xd9db3613
+ 0x6212a02b 0xff9c9169 0x0f7d0549 0x32cb119a
+ 0xdd8d4303 0x9798bff1 0xd72ff905 0xca5365a3
+ 0x3cb9f375 0xfe61bc4b 0xccd0f915 0x94151776
+ 0x64166df4 0xeefd90a6 0x3a0089cb 0xc4efaca4
+ 0xa64cbd96 0xbc4b834c 0x4b8be091 0x72f322fe
+ 0x35e67029 0x4030ed4c 0xe0cd63a3 0xda35976a
+ 0x94fbc08c 0xd6d3429b 0x6ac3087d 0x57e3eb54
+ 0xeba813a4 0x9bd06f05 0x2d2f860f 0x4901e70c
+ 0x226802f5 0xcc8d0940 0xa8825eb5 0x1ab23757
+ 0xe842caff 0x77123976 0x647068e2 0xc75de8be
+ 0x0bf388a2 0x4f501ebe 0xc64118fc 0xc1cbaabb
+ 0x98c9810d 0x0b4f63e4 0x641e2360 0x168bb3c8
+ 0xa1cede7b 0x5fe0d436 0xa93a4cf8 0xf7b75424
+ 0xf4725a08 0xe0532c1e 0xfe83bc98 0x3a43d6e0
+ 0xbebecec8 0x81bd1a51 0x5525ecd7 0x384d8d37
+ 0xed6ef639 0x5efe6032 0x6937ce1f 0xb3ee8dbd
+ 0xa0aa97df 0xd62d6fd7 0x5acc6d6f 0xef19f5b1
+ 0x3ad0d109 0x3660bbd1 0xfbf8d7e7 0x210ab474
+ 0xd9cde94d 0x4cb35844 0xb287c427 0x6087b156
+ 0xc04b25c1 0x78722325 0xe5937d3b 0x2477d2bf
+ 0x859237aa 0xd29b1567 0xc4b6c1ec 0xb325f9d3
+ 0xb59d3b11 0x54449fb8 0xba28f795 0xc72e0157
+ 0xa306042a 0x974e4bf8 0x835a665c 0x4b54f87b
+ 0x25b9f700 0x2176126c 0x868ad962 0xf5478e50
+ 0xa82f2f84 0x1ef6e4af 0xbfaf0c9b 0xea6acebe
+ 0x55965550 0x0d1a325d 0x9b786f43 0xa3a55c13
+ 0x758e4290 0x0e156cd6 0xec3fa531 0x73464f29
+ 0x1639e8bf 0x051d786b 0x303c214a 0x80c09001
+ 0x71f5ec60 0xb5322364 0x91ea1fc2 0xb461fe47
+ 0x596fbd60 0x73671c45 0x7301b951 0xb9c9605c
+ 0x1b04f497 0xfbef823b 0xc621a97b 0xe55e1d29
+ 0x6984e8b5 0xefce9254 0x544f7540 0xdcd81ef6
+ 0xa20e4ad6 0xc80fb804 0xb96d8a3b 0x3d04128e
+ 0xdcbd0f39 0xb5d4bca3 0x7720d158 0x6da9a045
+ 0x273c430e 0xece0eb38 0x672e817a 0xc0d79da7
+ 0x75c37954 0x58c753de 0xcbcbad35 0x786e6c7e
+ 0xe260b5d1 0xc404468d 0x57cfae75 0x39b497a8
+ 0x1bae57a2 0x52c7508e 0x89b127b9 0x03736bf1
+ 0xd0af6722 0x10b7cad0 0xb2fec538 0xae1bee3b
+ 0xb4fcc9f5 0xc7a89d3b 0xdde3aa84 0xef24259d
+ 0x5adacacb 0xd7f953d6 0x0be41a0c 0x83d6fbb0
+ 0x6967528e 0xb46394d6 0xf63ebf82 0xd2b3f03e
+ 0x7b86862f 0x57786dba 0xeb06cbba 0x7e989a81
+ 0xb9ebccbc 0xb74fffd4 0xbec943d2 0xb9a375c3
+ 0xd3344f7a 0x26c60798 0x49016082 0x551f17e0
+ 0x0f4bee9d 0x614303cd 0xcad6bd8c 0x5c3bbeaf
+ 0x86f4d83d 0xfc4445db 0x0f1a79e5 0xb9f0ce8c
+ 0xdc4152af 0x6e8fc82f 0xf2ccad51 0x8b0b7cc3
+ 0xa2aa307b 0xa520ea29 0x0292bc09 0x534ffc75
+ 0x1b398c80 0x5eca089e 0xc7aff269 0x0059f0b9
+ 0x541aa484 0x99943f2a 0xfc1f579e 0x85da714d
+ 0xd7092c5f 0x0a167a5d 0x898726b8 0x47ffe115
+ 0x8990821e 0xc08ff8a0 0x0e1a2986 0x339ff1d0
+ 0xedd4aaeb 0x9350e602 0x6569e126 0x5859aafd
+ 0x5b0cb2c6 0x147cfa35 0x0d905917 0xf2233208
+ 0xb36ef680 0x841b48d9 0x1c6a0f0d 0x8227247e
+ 0xac9bbb04 0xff8bbb90 0x6fcea1ea 0x7dfbb3aa
+ 0xa464bac7 0x88633a36 0x674b0362 0x74223977
+ 0x139a8d87 0x1d8a5826 0xaa254054 0xeff8db68
+ 0x664d29b7 0x5f1ac3eb 0xddcba2bf 0x0e73df53
+ 0x08ffe947 0xbf3f1da8 0x46f1d718 0x5ab11692
+ 0xf190a0b8 0x9d0e9717 0x86757018 0x97827999
+ 0x573d0b1d 0x7bf3969b 0x3172eab5 0xc5dd90bd
+ 0x413d1445 0xc9612206 0x43ecc87c 0x4d0af8fb
+ 0xad744b83 0x8f007f86 0x44551cd7 0xaf820402
+ 0x6b9a3cd7 0xed4a0a59 0xd4eb0493 0x1bde6215
+ 0xa693b3fc 0x22e4fe0d 0x057a211e 0x9973169c
+ 0x086516f4 0xe1e6ba26 0xb4ad5a0e 0xbf3cf264
+ 0xa40e61f0 0x12eef468 0x7be11464 0x6acb81cf
+ 0xa04787f7 0xdbe5ac75 0xcad096a8 0x185cf673
+ 0x6e0ea343 0xe84a1467 0xef3f00eb 0xef177b01
+ 0x46dd87bc 0x34309420 0x0821d1d1 0x39000215
+ 0x685f4c0e 0xb80c1c87 0x9756d5ff 0xbbcaf5b0
+ 0xde2d1453 0x4c9f69d1 0x56196e6b 0xef81e9a5
+ 0xfc22f7ce 0xca61a7a6 0x4bf15020 0xfa080406
+ 0xd0b837a6 0x7bcb8577 0xfedf367c 0xfcf81696
+ 0x014ed3e6 0xf3353212 0xc062d44a 0xd813a68f
+ 0xd5d7a1db 0x8c45c94e 0xc5b90467 0x6f74385b
+ 0x7130a2d3 0x708b9489 0xdbbb7ce7 0xfc90865c
+ 0x653c5bd4 0xac3cd1e2 0xe27bb6d9 0xd41e4d6a
+ 0xae016134 0x87b7b2c9 0xd994b3e9 0x71e42004
+ 0xb845d3af 0x592dbebb 0x620899c0 0x8d3b090d
+ 0x9d0e6a42 0xce95d950 0x4b7117d0 0x4e32208e
+ 0x379df4c7 0x73c8403d 0x9c035976 0x9fa4ab3f
+ 0x0e4abd10 0xea5abdc0 0xc74b08f5 0x8ad84f2f
+ 0xe6ea941f 0xedd37fd7 0x8800959d 0x4eaf1dd9
+ 0xc03f8601 0x3f05cec7 0xa7dc9585 0xfc497aa7
+ 0x5ab6ec8d 0xf920b15a 0x0528a3a0 0xb03478f9
+ 0xf58d945c 0xf6d56911 0x9d6b8f61 0x62eced7e
+ 0x8c387967 0xb9c3664c 0x703321a1 0xb0779fb6
+ 0x0a5ca536 0x216262ca 0x8471e2dc 0x456035c2
+ 0x1f9a3f80 0x62f7b45b 0xe0fb6e10 0xd817b0a1
+ 0xb04007a7 0x8a2a3997 0xc13b2ff7 0xac042c3c
+ 0x0af1158f 0xb080446d 0x22561f86 0x3c449de0
+ 0xbe156e20 0x7745c38a 0x19cadbff 0xcf505afc
+ 0xc2f94af9 0x720e8b00 0x1d740186 0xc411e6a7
+ 0x16f99b0a 0x0b949e35 0xbc306cf9 0x67f417b4
+ 0xce3e2635 0xd8f3a3fa 0x4b6fd9e6 0x63cfad21
+ 0xaaf1456d 0x6c520541 0xca2dcac8 0xab62863d
+ 0x150a0ae3 0xa9e92a07 0x85e51d1f 0x327253e7
+ 0xa0d5d35e 0x331b43ce 0x207a336a 0x3407a0b3
+ 0x975a2429 0x95d42c04 0x9ff5ef17 0xfefb14c7
+ 0xa3d8f8ac 0x6a112cd8 0x2d276889 0x5f2f6ef9
+ 0x611636e3 0xecc81a74 0x4d482888 0xa46a478d
+ 0x7de65d9d 0x921e2a1f 0x48cca90f 0x64013e1f
+ 0x45aa6b87 0x5da46878 0x39a21b74 0xa72250de
+ 0xebbaa970 0xef8d31f9 0x59a9e1e2 0xd3403b97
+ 0x1780ddca 0x731fa40f 0x6c2ba0fe 0x4f053afb
+ 0x2cf0e873 0xb6a733a8 0xc2a2e53e 0xd2241962
+ 0xcb981a05 0x4af04278 0x053d4e34 0x63d071b8
+ 0x731b063a 0xeed8b331 0x05221e90 0x6705a444
+ 0x2c504d6d 0x231c42ec 0x8debbfaa 0x07829ed7
+ 0x50ee8337 0x17ed0270 0x4a04c200 0xf5e650bd
+ 0x5bbe5f66 0x72d412d3 0x40253020 0xa949f29d
+ >;
pos = <CONFIG_VGA_BIOS_ADDR>;
};
#endif
+#ifdef CONFIG_HAVE_VBT
+ intel-vbt {
+ filename = CONFIG_VBT_FILE;
+ pos = <CONFIG_VBT_ADDR>;
+ };
+#endif
#ifdef CONFIG_HAVE_REFCODE
intel-refcode {
pos = <CONFIG_X86_REFCODE_ADDR>;
--- /dev/null
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+#ifndef __ASSEMBLY__
+struct fsp_config_data {
+ struct fsp_cfg_common common;
+ struct upd_region fsp_upd;
+};
+
+struct fspinit_rtbuf {
+ struct common_buf common; /* FSP common runtime data structure */
+};
+#endif
+
+/* FSP user configuration settings */
+
+#define MRC_INIT_TSEG_SIZE_1MB 1
+#define MRC_INIT_TSEG_SIZE_2MB 2
+#define MRC_INIT_TSEG_SIZE_4MB 4
+#define MRC_INIT_TSEG_SIZE_8MB 8
+
+#define MRC_INIT_MMIO_SIZE_1024MB 0x400
+#define MRC_INIT_MMIO_SIZE_1536MB 0x600
+#define MRC_INIT_MMIO_SIZE_2048MB 0x800
+
+#define IGD_DVMT50_PRE_ALLOC_32MB 0x01
+#define IGD_DVMT50_PRE_ALLOC_64MB 0x02
+#define IGD_DVMT50_PRE_ALLOC_96MB 0x03
+#define IGD_DVMT50_PRE_ALLOC_128MB 0x04
+#define IGD_DVMT50_PRE_ALLOC_160MB 0x05
+#define IGD_DVMT50_PRE_ALLOC_192MB 0x06
+#define IGD_DVMT50_PRE_ALLOC_224MB 0x07
+#define IGD_DVMT50_PRE_ALLOC_256MB 0x08
+#define IGD_DVMT50_PRE_ALLOC_288MB 0x09
+#define IGD_DVMT50_PRE_ALLOC_320MB 0x0a
+#define IGD_DVMT50_PRE_ALLOC_352MB 0x0b
+#define IGD_DVMT50_PRE_ALLOC_384MB 0x0c
+#define IGD_DVMT50_PRE_ALLOC_416MB 0x0d
+#define IGD_DVMT50_PRE_ALLOC_448MB 0x0e
+#define IGD_DVMT50_PRE_ALLOC_480MB 0x0f
+#define IGD_DVMT50_PRE_ALLOC_512MB 0x10
+
+#define APERTURE_SIZE_128MB 1
+#define APERTURE_SIZE_256MB 2
+#define APERTURE_SIZE_512MB 3
+
+#define GTT_SIZE_1MB 1
+#define GTT_SIZE_2MB 2
+
+#define DRAM_TYPE_DDR3 0
+#define DRAM_TYPE_LPDDR3 1
+
+#define SDCARD_MODE_DISABLED 0
+#define SDCARD_MODE_PCI 1
+#define SDCARD_MODE_ACPI 2
+
+#define LPE_MODE_DISABLED 0
+#define LPE_MODE_PCI 1
+#define LPE_MODE_ACPI 2
+
+#define CHV_SVID_CONFIG_0 0
+#define CHV_SVID_CONFIG_1 1
+#define CHV_SVID_CONFIG_2 2
+#define CHV_SVID_CONFIG_3 3
+
+#define EMMC_MODE_DISABLED 0
+#define EMMC_MODE_PCI 1
+#define EMMC_MODE_ACPI 2
+
+#define SATA_SPEED_GEN1 1
+#define SATA_SPEED_GEN2 2
+#define SATA_SPEED_GEN3 3
+
+#define ISP_PCI_DEV_CONFIG_1 1
+#define ISP_PCI_DEV_CONFIG_2 2
+#define ISP_PCI_DEV_CONFIG_3 3
+
+#define PNP_SETTING_DISABLED 0
+#define PNP_SETTING_POWER 1
+#define PNP_SETTING_PERF 2
+#define PNP_SETTING_POWER_AND_PERF 3
+
+#endif /* __FSP_CONFIGS_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2015, Intel Corporation
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_VPD_H__
+#define __FSP_VPD_H__
+
+struct __packed memory_upd {
+ u64 signature; /* Offset 0x0020 */
+ u8 revision; /* Offset 0x0028 */
+ u8 unused2[7]; /* Offset 0x0029 */
+ u16 mrc_init_tseg_size; /* Offset 0x0030 */
+ u16 mrc_init_mmio_size; /* Offset 0x0032 */
+ u8 mrc_init_spd_addr1; /* Offset 0x0034 */
+ u8 mrc_init_spd_addr2; /* Offset 0x0035 */
+ u8 mem_ch0_config; /* Offset 0x0036 */
+ u8 mem_ch1_config; /* Offset 0x0037 */
+ u32 memory_spd_ptr; /* Offset 0x0038 */
+ u8 igd_dvmt50_pre_alloc; /* Offset 0x003c */
+ u8 aperture_size; /* Offset 0x003d */
+ u8 gtt_size; /* Offset 0x003e */
+ u8 legacy_seg_decode; /* Offset 0x003f */
+ u8 enable_dvfs; /* Offset 0x0040 */
+ u8 memory_type; /* Offset 0x0041 */
+ u8 enable_ca_mirror; /* Offset 0x0042 */
+ u8 reserved[189]; /* Offset 0x0043 */
+};
+
+struct __packed azalia_verb_table_header {
+ u32 vendor_device_id;
+ u16 sub_system_id;
+ u8 revision_id;
+ u8 front_panel_support;
+ u16 number_of_rear_jacks;
+ u16 number_of_front_jacks;
+};
+
+struct __packed azalia_verb_table {
+ struct azalia_verb_table_header header;
+ u32 *data;
+};
+
+struct __packed azalia_config {
+ u8 pme_enable:1;
+ u8 docking_supported:1;
+ u8 docking_attached:1;
+ u8 hdmi_codec_enable:1;
+ u8 azalia_v_ci_enable:1;
+ u8 reserved:3;
+ u8 verb_table_num;
+ struct azalia_verb_table *verb_table;
+ u16 reset_wait_timer_ms;
+};
+
+struct gpio_family {
+ u32 confg;
+ u32 confg_changes;
+ u32 misc;
+ u32 mmio_addr;
+ wchar_t *name;
+};
+
+struct gpio_pad {
+ u32 confg0;
+ u32 confg0_changes;
+ u32 confg1;
+ u32 confg1_changes;
+ u32 community;
+ u32 mmio_addr;
+ wchar_t *name;
+ u32 misc;
+};
+
+struct __packed silicon_upd {
+ u64 signature; /* Offset 0x0100 */
+ u8 revision; /* Offset 0x0108 */
+ u8 unused3[7]; /* Offset 0x0109 */
+ u8 sdcard_mode; /* Offset 0x0110 */
+ u8 enable_hsuart0; /* Offset 0x0111 */
+ u8 enable_hsuart1; /* Offset 0x0112 */
+ u8 enable_azalia; /* Offset 0x0113 */
+ struct azalia_config *azalia_cfg_ptr; /* Offset 0x0114 */
+ u8 enable_sata; /* Offset 0x0118 */
+ u8 enable_xhci; /* Offset 0x0119 */
+ u8 lpe_mode; /* Offset 0x011a */
+ u8 enable_dma0; /* Offset 0x011b */
+ u8 enable_dma1; /* Offset 0x011c */
+ u8 enable_i2c0; /* Offset 0x011d */
+ u8 enable_i2c1; /* Offset 0x011e */
+ u8 enable_i2c2; /* Offset 0x011f */
+ u8 enable_i2c3; /* Offset 0x0120 */
+ u8 enable_i2c4; /* Offset 0x0121 */
+ u8 enable_i2c5; /* Offset 0x0122 */
+ u8 enable_i2c6; /* Offset 0x0123 */
+ u32 graphics_config_ptr; /* Offset 0x0124 */
+ struct gpio_family *gpio_familiy_ptr; /* Offset 0x0128 */
+ struct gpio_pad *gpio_pad_ptr; /* Offset 0x012c */
+ u8 disable_punit_pwr_config; /* Offset 0x0130 */
+ u8 chv_svid_config; /* Offset 0x0131 */
+ u8 disable_dptf; /* Offset 0x0132 */
+ u8 emmc_mode; /* Offset 0x0133 */
+ u8 usb3_clk_ssc; /* Offset 0x0134 */
+ u8 disp_clk_ssc; /* Offset 0x0135 */
+ u8 sata_clk_ssc; /* Offset 0x0136 */
+ u8 usb2_port0_pe_txi_set; /* Offset 0x0137 */
+ u8 usb2_port0_txi_set; /* Offset 0x0138 */
+ u8 usb2_port0_tx_emphasis_en; /* Offset 0x0139 */
+ u8 usb2_port0_tx_pe_half; /* Offset 0x013a */
+ u8 usb2_port1_pe_txi_set; /* Offset 0x013b */
+ u8 usb2_port1_txi_set; /* Offset 0x013c */
+ u8 usb2_port1_tx_emphasis_en; /* Offset 0x013d */
+ u8 usb2_port1_tx_pe_half; /* Offset 0x013e */
+ u8 usb2_port2_pe_txi_set; /* Offset 0x013f */
+ u8 usb2_port2_txi_set; /* Offset 0x0140 */
+ u8 usb2_port2_tx_emphasis_en; /* Offset 0x0141 */
+ u8 usb2_port2_tx_pe_half; /* Offset 0x0142 */
+ u8 usb2_port3_pe_txi_set; /* Offset 0x0143 */
+ u8 usb2_port3_txi_set; /* Offset 0x0144 */
+ u8 usb2_port3_tx_emphasis_en; /* Offset 0x0145 */
+ u8 usb2_port3_tx_pe_half; /* Offset 0x0146 */
+ u8 usb2_port4_pe_txi_set; /* Offset 0x0147 */
+ u8 usb2_port4_txi_set; /* Offset 0x0148 */
+ u8 usb2_port4_tx_emphasis_en; /* Offset 0x0149 */
+ u8 usb2_port4_tx_pe_half; /* Offset 0x014a */
+ u8 usb3_lane0_ow2tap_gen2_deemph3p5; /* Offset 0x014b */
+ u8 usb3_lane1_ow2tap_gen2_deemph3p5; /* Offset 0x014c */
+ u8 usb3_lane2_ow2tap_gen2_deemph3p5; /* Offset 0x014d */
+ u8 usb3_lane3_ow2tap_gen2_deemph3p5; /* Offset 0x014e */
+ u8 sata_speed; /* Offset 0x014f */
+ u8 usb_ssic_port; /* Offset 0x0150 */
+ u8 usb_hsic_port; /* Offset 0x0151 */
+ u8 pcie_rootport_speed; /* Offset 0x0152 */
+ u8 enable_ssic; /* Offset 0x0153 */
+ u32 logo_ptr; /* Offset 0x0154 */
+ u32 logo_size; /* Offset 0x0158 */
+ u8 rtc_lock; /* Offset 0x015c */
+ u8 pmic_i2c_bus; /* Offset 0x015d */
+ u8 enable_isp; /* Offset 0x015e */
+ u8 isp_pci_dev_config; /* Offset 0x015f */
+ u8 turbo_mode; /* Offset 0x0160 */
+ u8 pnp_settings; /* Offset 0x0161 */
+ u8 sd_detect_chk; /* Offset 0x0162 */
+ u8 reserved[411]; /* Offset 0x0163 */
+};
+
+#define MEMORY_UPD_ID 0x244450554d454d24 /* '$MEMUPD$' */
+#define SILICON_UPD_ID 0x244450555f495324 /* '$SI_UPD$' */
+
+struct __packed upd_region {
+ u64 signature; /* Offset 0x0000 */
+ u8 revision; /* Offset 0x0008 */
+ u8 unused0[7]; /* Offset 0x0009 */
+ u32 memory_upd_offset; /* Offset 0x0010 */
+ u32 silicon_upd_offset; /* Offset 0x0014 */
+ u64 unused1; /* Offset 0x0018 */
+ struct memory_upd memory_upd; /* Offset 0x0020 */
+ struct silicon_upd silicon_upd; /* Offset 0x0100 */
+ u16 terminator; /* Offset 0x02fe */
+};
+
+#define VPD_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */
+
+struct __packed vpd_region {
+ u64 sign; /* Offset 0x0000 */
+ u32 img_rev; /* Offset 0x0008 */
+ u32 upd_offset; /* Offset 0x000c */
+};
+
+#endif /* __FSP_VPD_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * From coreboot src/soc/intel/braswell/include/soc/gpio.h
+ */
+
+#ifndef _BRASWELL_GPIO_H_
+#define _BRASWELL_GPIO_H_
+
+#include <asm/arch/iomap.h>
+
+enum mode_list {
+ M0,
+ M1,
+ M2,
+ M3,
+ M4,
+ M5,
+ M6,
+ M7,
+ M8,
+ M9,
+ M10,
+ M11,
+ M12,
+ M13,
+};
+
+enum int_select {
+ L0,
+ L1,
+ L2,
+ L3,
+ L4,
+ L5,
+ L6,
+ L7,
+ L8,
+ L9,
+ L10,
+ L11,
+ L12,
+ L13,
+ L14,
+ L15,
+};
+
+enum gpio_en {
+ NATIVE = 0xff,
+ GPIO = 0, /* Native, no need to set PAD_VALUE */
+ GPO = 1, /* GPO, output only in PAD_VALUE */
+ GPI = 2, /* GPI, input only in PAD_VALUE */
+ HI_Z = 3,
+ NA_GPO = 0,
+};
+
+enum gpio_state {
+ LOW,
+ HIGH,
+};
+
+enum en_dis {
+ DISABLE, /* Disable */
+ ENABLE, /* Enable */
+};
+
+enum int_type {
+ INT_DIS,
+ TRIG_EDGE_LOW,
+ TRIG_EDGE_HIGH,
+ TRIG_EDGE_BOTH,
+ TRIG_LEVEL,
+};
+
+enum mask {
+ MASKABLE,
+ NON_MASKABLE,
+};
+
+enum glitch_cfg {
+ GLITCH_DISABLE,
+ EN_EDGE_DETECT,
+ EN_RX_DATA,
+ EN_EDGE_RX_DATA,
+};
+
+enum inv_rx_tx {
+ NO_INVERSION = 0,
+ INV_RX_ENABLE = 1,
+ INV_TX_ENABLE = 2,
+ INV_RX_TX_ENABLE = 3,
+ INV_RX_DATA = 4,
+ INV_TX_DATA = 8,
+};
+
+enum voltage {
+ VOLT_3_3, /* Working on 3.3 Volts */
+ VOLT_1_8, /* Working on 1.8 Volts */
+};
+
+enum hs_mode {
+ DISABLE_HS, /* Disable high speed mode */
+ ENABLE_HS, /* Enable high speed mode */
+};
+
+enum odt_up_dn {
+ PULL_UP, /* On Die Termination Up */
+ PULL_DOWN, /* On Die Termination Down */
+};
+
+enum odt_en {
+ DISABLE_OD, /* On Die Termination Disable */
+ ENABLE_OD, /* On Die Termination Enable */
+};
+
+enum pull_type {
+ P_NONE = 0, /* Pull None */
+ P_20K_L = 1, /* Pull Down 20K */
+ P_5K_L = 2, /* Pull Down 5K */
+ P_1K_L = 4, /* Pull Down 1K */
+ P_20K_H = 9, /* Pull Up 20K */
+ P_5K_H = 10, /* Pull Up 5K */
+ P_1K_H = 12 /* Pull Up 1K */
+};
+
+enum bit {
+ ONE_BIT = 1,
+ TWO_BIT = 3,
+ THREE_BIT = 7,
+ FOUR_BIT = 15,
+ FIVE_BIT = 31,
+ SIX_BIT = 63,
+ SEVEN_BIT = 127,
+ EIGHT_BIT = 255
+};
+
+enum gpe_config {
+ GPE,
+ SMI,
+ SCI,
+};
+
+enum community {
+ SOUTHWEST = 0x0000,
+ NORTH = 0x8000,
+ EAST = 0x10000,
+ SOUTHEAST = 0x18000,
+ VIRTUAL = 0x20000,
+};
+
+#define NA 0xff
+#define TERMINATOR 0xffffffff
+
+#define GPIO_FAMILY_CONF(family_name, park_mode, hysctl, vp18_mode, hs_mode, \
+ odt_up_dn, odt_en, curr_src_str, rcomp, family_no, community_offset) { \
+ .confg = ((((park_mode) != NA) ? park_mode << 26 : 0) | \
+ (((hysctl) != NA) ? hysctl << 24 : 0) | \
+ (((vp18_mode) != NA) ? vp18_mode << 21 : 0) | \
+ (((hs_mode) != NA) ? hs_mode << 19 : 0) | \
+ (((odt_up_dn) != NA) ? odt_up_dn << 18 : 0) | \
+ (((odt_en) != NA) ? odt_en << 17 : 0) | \
+ (curr_src_str)), \
+ .confg_changes = ((((park_mode) != NA) ? ONE_BIT << 26 : 0) | \
+ (((hysctl) != NA) ? TWO_BIT << 24 : 0) | \
+ (((vp18_mode) != NA) ? ONE_BIT << 21 : 0) | \
+ (((hs_mode) != NA) ? ONE_BIT << 19 : 0) | \
+ (((odt_up_dn) != NA) ? ONE_BIT << 18 : 0) | \
+ (((odt_en) != NA) ? ONE_BIT << 17 : 0) | \
+ (THREE_BIT)), \
+ .misc = ((rcomp == ENABLE) ? 1 : 0) , \
+ .mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
+ ((family_no != NA) ? (IO_BASE_ADDRESS + community_offset +\
+ (0x80 * family_no) + 0x1080) : 0) , \
+ .name = 0 \
+}
+
+#define GPIO_PAD_CONF(pad_name, mode_select, mode, gpio_config, gpio_state, \
+ gpio_light_mode, int_type, int_sel, term, open_drain, current_source,\
+ int_mask, glitch, inv_rx_tx, wake_mask, wake_mask_bit, gpe, \
+ mmio_offset, community_offset) { \
+ .confg0 = ((((int_sel) != NA) ? (int_sel << 28) : 0) | \
+ (((glitch) != NA) ? (glitch << 26) : 0) | \
+ (((term) != NA) ? (term << 20) : 0) | \
+ (((mode_select) == GPIO) ? ((mode << 16) | (1 << 15)) : \
+ ((mode << 16))) | \
+ (((gpio_config) != NA) ? (gpio_config << 8) : 0) | \
+ (((gpio_light_mode) != NA) ? (gpio_light_mode << 7) : 0) | \
+ (((gpio_state) == HIGH) ? 2 : 0)), \
+ .confg0_changes = ((((int_sel) != NA) ? (FOUR_BIT << 28) : 0) | \
+ (((glitch) != NA) ? (TWO_BIT << 26) : 0) | \
+ (((term) != NA) ? (FOUR_BIT << 20) : 0) | \
+ (FIVE_BIT << 15) | \
+ (((gpio_config) != NA) ? (THREE_BIT << 8) : 0) | \
+ (((gpio_light_mode) != NA) ? (ONE_BIT << 7) : 0) | \
+ (((gpio_state) != NA) ? ONE_BIT << 1 : 0)), \
+ .confg1 = ((((current_source) != NA) ? (current_source << 27) : 0) | \
+ (((inv_rx_tx) != NA) ? inv_rx_tx << 4 : 0) | \
+ (((open_drain) != NA) ? open_drain << 3 : 0) | \
+ (((int_type) != NA) ? int_type : 0)), \
+ .confg1_changes = ((((current_source) != NA) ? (ONE_BIT << 27) : 0) | \
+ (((inv_rx_tx) != NA) ? FOUR_BIT << 4 : 0) | \
+ (((open_drain) != NA) ? ONE_BIT << 3 : 0) | \
+ (((int_type) != NA) ? THREE_BIT : 0)), \
+ .community = community_offset, \
+ .mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
+ ((mmio_offset != NA) ? (IO_BASE_ADDRESS + \
+ community_offset + mmio_offset) : 0), \
+ .name = 0, \
+ .misc = ((((gpe) != NA) ? (gpe << 0) : 0) | \
+ (((wake_mask) != NA) ? (wake_mask << 2) : 0) | \
+ (((int_mask) != NA) ? (int_mask << 3) : 0)) | \
+ (((wake_mask_bit) != NA) ? (wake_mask_bit << 4) : (NA << 4)) \
+}
+
+#endif /* _BRASWELL_GPIO_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BRASWELL_IOMAP_H_
+#define _BRASWELL_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* Power Management Controller */
+#define PMC_BASE_ADDRESS 0xfed03000
+#define PMC_BASE_SIZE 0x400
+
+/* Power Management Unit */
+#define PUNIT_BASE_ADDRESS 0xfed05000
+#define PUNIT_BASE_SIZE 0x800
+
+/* Intel Legacy Block */
+#define ILB_BASE_ADDRESS 0xfed08000
+#define ILB_BASE_SIZE 0x400
+
+/* SPI Bus */
+#define SPI_BASE_ADDRESS 0xfed01000
+#define SPI_BASE_SIZE 0x400
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS 0xfed1c000
+#define RCBA_BASE_SIZE 0x400
+
+/* IO Memory */
+#define IO_BASE_ADDRESS 0xfed80000
+#define IO_BASE_SIZE 0x4000
+
+/* MODPHY */
+#define MPHY_BASE_ADDRESS 0xfef00000
+#define MPHY_BASE_SIZE 0x100000
+
+/* IO Port bases */
+
+#define ACPI_BASE_ADDRESS 0x400
+#define ACPI_BASE_SIZE 0x80
+
+#define GPIO_BASE_ADDRESS 0x500
+#define GPIO_BASE_SIZE 0x100
+
+#define SMBUS_BASE_ADDRESS 0xefa0
+
+#endif /* _BRASWELL_IOMAP_H_ */
#ifndef __ASM_X86_DMA_MAPPING_H
#define __ASM_X86_DMA_MAPPING_H
-#define dma_mapping_error(x, y) 0
+#include <linux/dma-direction.h>
-enum dma_data_direction {
- DMA_BIDIRECTIONAL = 0,
- DMA_TO_DEVICE = 1,
- DMA_FROM_DEVICE = 2,
-};
+#define dma_mapping_error(x, y) 0
static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
{
u32 stack_top;
u32 boot_mode; /* Current system boot mode */
void *upd_data; /* User platform configuraiton data region */
- u32 reserved[7]; /* Reserved */
+ u32 tolum_size; /* Top of low usable memory size (FSP 1.1) */
+ u32 reserved[6]; /* Reserved */
};
enum fsp_phase {
/* GUID specific data goes here */
};
+enum pixel_format {
+ pixel_rgbx_8bpc, /* RGB 8 bit per color */
+ pixel_bgrx_8bpc, /* BGR 8 bit per color */
+ pixel_bitmask,
+};
+
+struct __packed hob_graphics_info {
+ phys_addr_t fb_base; /* framebuffer base address */
+ u32 fb_size; /* framebuffer size */
+ u32 version;
+ u32 width;
+ u32 height;
+ enum pixel_format pixel_format;
+ u32 red_mask;
+ u32 green_mask;
+ u32 blue_mask;
+ u32 reserved_mask;
+ u32 pixels_per_scanline;
+};
+
/**
* get_next_hob() - return a pointer to the next HOB in the HOB list
*
{ 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \
}
+/* The following GUIDs are newly introduced in FSP spec 1.1 */
+
+#define FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID \
+ { \
+ 0x73ff4f56, 0xaa8e, 0x4451, \
+ { 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } \
+ }
+
+#define FSP_GRAPHICS_INFO_HOB_GUID \
+ { \
+ 0x39f62cce, 0x6825, 0x4669, \
+ { 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 } \
+ }
+
#endif
u32 fsp_tempram_init; /* tempram_init offset */
u32 fsp_init; /* fsp_init offset */
u32 fsp_notify; /* fsp_notify offset */
- u32 reserved2;
+ u32 fsp_mem_init; /* fsp_mem_init offset */
+ u32 fsp_tempram_exit; /* fsp_tempram_exit offset */
+ u32 fsp_silicon_init; /* fsp_silicon_init offset */
};
+#define FSP_HEADER_REVISION_1 1
+#define FSP_HEADER_REVISION_2 2
+
+#define FSP_ATTR_GRAPHICS_SUPPORT (1 << 0)
+
#endif
*/
void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);
+/**
+ * This function retrieves graphics information.
+ *
+ * @hob_list: A HOB list pointer.
+ * @len: A pointer to the graphics info HOB length.
+ * If the HOB is located, the length will be updated.
+ *
+ * @retval NULL: Failed to find the graphics info HOB.
+ * @retval others: A pointer to struct hob_graphics_info.
+ */
+void *fsp_get_graphics_info(const void *hob_list, u32 *len);
+
/**
* This function overrides the default configurations of FSP.
*
uint8_t x86_mask;
uint32_t x86_device;
uint64_t tsc_base; /* Initial value returned by rdtsc() */
+ unsigned long clock_rate; /* Clock rate of timer in Hz */
void *new_fdt; /* Relocated FDT */
uint32_t bist; /* Built-in self test value */
enum pei_boot_mode_t pei_boot_mode;
obj-y += fsp_car.o
obj-y += fsp_common.o
obj-y += fsp_dram.o
+obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o
obj-y += fsp_support.o
for (i = 0; i < sizeof(hdr->sign); i++)
printf("%c", *sign++);
printf(", size %d, rev %d\n", hdr->hdr_len, hdr->hdr_rev);
- printf("Image : rev %d.%d, id ",
- (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff);
+ printf("Image : rev ");
+ if (hdr->hdr_rev == FSP_HEADER_REVISION_1) {
+ printf("%d.%d",
+ (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff);
+ } else {
+ printf("%d.%d.%d.%d",
+ (hdr->img_rev >> 24) & 0xff, (hdr->img_rev >> 16) & 0xff,
+ (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff);
+ }
+ printf(", id ");
for (i = 0; i < ARRAY_SIZE(hdr->img_id); i++)
printf("%c", hdr->img_id[i]);
printf(", addr 0x%08x, size %d\n", img_addr, hdr->img_size);
+ if (hdr->hdr_rev == FSP_HEADER_REVISION_2) {
+ printf("GFX :%ssupported\n",
+ hdr->img_attr & FSP_ATTR_GRAPHICS_SUPPORT ? " " : " un");
+ }
printf("VPD : addr 0x%08x, size %d\n",
hdr->cfg_region_off + img_addr, hdr->cfg_region_size);
printf("\nNumber of APIs Supported : %d\n", hdr->api_num);
printf("\tTempRamInit : 0x%08x\n", hdr->fsp_tempram_init + img_addr);
printf("\tFspInit : 0x%08x\n", hdr->fsp_init + img_addr);
printf("\tFspNotify : 0x%08x\n", hdr->fsp_notify + img_addr);
+ if (hdr->hdr_rev == FSP_HEADER_REVISION_2) {
+ printf("\tMemoryInit : 0x%08x\n",
+ hdr->fsp_mem_init + img_addr);
+ printf("\tTempRamExit : 0x%08x\n",
+ hdr->fsp_tempram_exit + img_addr);
+ printf("\tSiliconInit : 0x%08x\n",
+ hdr->fsp_silicon_init + img_addr);
+ }
return 0;
}
--- /dev/null
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <vbe.h>
+#include <video.h>
+#include <asm/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pixel {
+ u8 pos;
+ u8 size;
+};
+
+static const struct fsp_framebuffer {
+ struct pixel red;
+ struct pixel green;
+ struct pixel blue;
+ struct pixel rsvd;
+} fsp_framebuffer_format_map[] = {
+ [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} },
+ [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
+};
+
+static int save_vesa_mode(struct vesa_mode_info *vesa)
+{
+ const struct hob_graphics_info *ginfo;
+ const struct fsp_framebuffer *fbinfo;
+
+ ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL);
+
+ /*
+ * If there is no graphics info structure, bail out and keep
+ * running on the serial console.
+ */
+ if (!ginfo) {
+ debug("FSP graphics hand-off block not found\n");
+ return -ENXIO;
+ }
+
+ vesa->x_resolution = ginfo->width;
+ vesa->y_resolution = ginfo->height;
+ vesa->bits_per_pixel = 32;
+ vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4;
+ vesa->phys_base_ptr = ginfo->fb_base;
+
+ if (ginfo->pixel_format >= pixel_bitmask) {
+ debug("FSP set unknown framebuffer format: %d\n",
+ ginfo->pixel_format);
+ return -EINVAL;
+ }
+ fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format];
+ vesa->red_mask_size = fbinfo->red.size;
+ vesa->red_mask_pos = fbinfo->red.pos;
+ vesa->green_mask_size = fbinfo->green.size;
+ vesa->green_mask_pos = fbinfo->green.pos;
+ vesa->blue_mask_size = fbinfo->blue.size;
+ vesa->blue_mask_pos = fbinfo->blue.pos;
+ vesa->reserved_mask_size = fbinfo->rsvd.size;
+ vesa->reserved_mask_pos = fbinfo->rsvd.pos;
+
+ return 0;
+}
+
+static int fsp_video_probe(struct udevice *dev)
+{
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct vesa_mode_info *vesa = &mode_info.vesa;
+ int ret;
+
+ printf("Video: ");
+
+ /* Initialize vesa_mode_info structure */
+ ret = save_vesa_mode(vesa);
+ if (ret)
+ goto err;
+
+ /*
+ * The framebuffer base address in the FSP graphics info HOB reflects
+ * the value assigned by the FSP. After PCI enumeration the framebuffer
+ * base address may be relocated. Let's get the updated one from device.
+ *
+ * For IGD, it seems to be always on BAR2.
+ */
+ vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
+
+ ret = vbe_setup_video_priv(vesa, uc_priv, plat);
+ if (ret)
+ goto err;
+
+ printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
+ vesa->bits_per_pixel);
+
+ return 0;
+
+err:
+ printf("No video mode configured in FSP!\n");
+ return ret;
+}
+
+static const struct udevice_id fsp_video_ids[] = {
+ { .compatible = "fsp-fb" },
+ { }
+};
+
+U_BOOT_DRIVER(fsp_video) = {
+ .name = "fsp_video",
+ .id = UCLASS_VIDEO,
+ .of_match = fsp_video_ids,
+ .probe = fsp_video_probe,
+};
+
+static struct pci_device_id fsp_video_supported[] = {
+ { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) },
+ { },
+};
+
+U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported);
return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
}
+
+void *fsp_get_graphics_info(const void *hob_list, u32 *len)
+{
+ const struct efi_guid guid = FSP_GRAPHICS_INFO_HOB_GUID;
+
+ return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
+}
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <asm/mach-types.h>
#include <common.h>
#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
#include <netdev.h>
--- /dev/null
+if TARGET_VYASA_RK3288
+
+config SYS_BOARD
+ default "vyasa-rk3288"
+
+config SYS_VENDOR
+ default "amarula"
+
+config SYS_CONFIG_NAME
+ default "vyasa-rk3288"
+
+endif
--- /dev/null
+VYASA RK3288
+M: Jagan Teki <jagan@amarulasolutions.com>
+S: Maintained
+F: board/amarula/vyasa-rk3288
+F: include/configs/vyasa-rk3288.h
+F: configs/vyasa-rk3288_defconfig
--- /dev/null
+#
+# Copyright (C) 2017 Amarula Solutions
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += vyasa-rk3288.o
--- /dev/null
+/*
+ * Copyright (C) 2017 Amarula Solutions
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
-#ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_SD_BOOT
at91_mci_hw_init();
-#elif CONFIG_SYS_USE_NANDFLASH
+#elif CONFIG_NAND_BOOT
at91sam9m10g45ek_nand_hw_init();
#endif
}
void at91_spl_board_init(void)
{
-#ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_SD_BOOT
at91_mci_hw_init();
-#elif CONFIG_SYS_USE_NANDFLASH
+#elif CONFIG_NAND_BOOT
at91sam9n12ek_nand_hw_init();
-#elif CONFIG_SYS_USE_SPIFLASH
+#elif CONFIG_SPI_BOOT
at91_spi0_hw_init(1 << 4);
#endif
}
void at91_spl_board_init(void)
{
-#ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_SD_BOOT
at91_mci_hw_init();
-#elif CONFIG_SYS_USE_NANDFLASH
+#elif CONFIG_NAND_BOOT
at91sam9x5ek_nand_hw_init();
#endif
}
--- /dev/null
+#
+# Copyright (C) 2017 Microchip
+# Wenyou Yang <wenyou.yang@microchip.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_I2C_EEPROM) += mac_eeprom.o
+obj-$(CONFIG_DM_VIDEO) += video_display.o
+endif
--- /dev/null
+/*
+ * Copyright (C) 2017 Microchip
+ * Wenyou Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+void dummy(void)
+{
+}
--- /dev/null
+/*
+ * Copyright (C) 2017 Microchip
+ * Wenyou Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c_eeprom.h>
+#include <netdev.h>
+
+int at91_set_ethaddr(int offset)
+{
+ const int ETH_ADDR_LEN = 6;
+ unsigned char ethaddr[ETH_ADDR_LEN];
+ const char *ETHADDR_NAME = "ethaddr";
+ struct udevice *dev;
+ int ret;
+
+ if (env_get(ETHADDR_NAME))
+ return 0;
+
+ ret = uclass_first_device_err(UCLASS_I2C_EEPROM, &dev);
+ if (ret)
+ return ret;
+
+ ret = i2c_eeprom_read(dev, offset, ethaddr, 6);
+ if (ret)
+ return ret;
+
+ if (is_valid_ethaddr(ethaddr))
+ eth_env_set_enetaddr(ETHADDR_NAME, ethaddr);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2017 Microchip
+ * Wenyou Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <atmel_lcd.h>
+#include <dm.h>
+#include <nand.h>
+#include <version.h>
+#include <video.h>
+#include <video_console.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int at91_video_show_board_info(void)
+{
+ ulong dram_size, nand_size;
+ int i;
+ u32 len = 0;
+ char buf[255];
+ char *corp = "2017 Microchip Technology Inc.\n";
+ char temp[32];
+ struct udevice *dev, *con;
+ const char *s;
+ vidinfo_t logo_info;
+ int ret;
+
+ len += sprintf(&buf[len], "%s\n", U_BOOT_VERSION);
+ memcpy(&buf[len], corp, strlen(corp));
+ len += strlen(corp);
+ len += sprintf(&buf[len], "%s CPU at %s MHz\n", get_cpu_name(),
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+
+ nand_size = 0;
+#ifdef CONFIG_NAND_ATMEL
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i]->size;
+#endif
+
+ len += sprintf(&buf[len], "%ld MB SDRAM, %ld MB NAND\n",
+ dram_size >> 20, nand_size >> 20);
+
+ ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
+ if (ret)
+ return ret;
+
+ microchip_logo_info(&logo_info);
+ ret = video_bmp_display(dev, logo_info.logo_addr,
+ logo_info.logo_x_offset,
+ logo_info.logo_y_offset, false);
+ if (ret)
+ return ret;
+
+ ret = uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con);
+ if (ret)
+ return ret;
+
+ vidconsole_position_cursor(con, 0, logo_info.logo_height);
+ for (s = buf, i = 0; i < len; s++, i++)
+ vidconsole_put_char(con, *s);
+
+ return 0;
+}
--- /dev/null
+if TARGET_SAMA5D27_SOM1_EK
+
+config SYS_BOARD
+ default "sama5d27_som1_ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sama5d27_som1_ek"
+
+endif
--- /dev/null
+SAMA5D27 SOM1 EK BOARD
+M: Wenyou Yang <wenyou.yang@microchip.com>
+S: Maintained
+F: board/atmel/sama5d27_som1_ek/
+F: include/configs/sama5d27_som1_ek.h
+F: configs/sama5d27_som1_ek_mmc_defconfig
--- /dev/null
+#
+# Copyright (C) 2017 Microchip Corporation
+# Wenyou Yang <wenyou.yang@microchip.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sama5d27_som1_ek.o
--- /dev/null
+/*
+ * Copyright (C) 2017 Microchip Corporation
+ * Wenyou.Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void board_usb_hw_init(void)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_DM_VIDEO
+ at91_video_show_board_info();
+#endif
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void board_uart1_hw_init(void)
+{
+ atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */
+
+ at91_periph_clk_enable(ATMEL_ID_UART1);
+}
+
+void board_debug_uart_init(void)
+{
+ board_uart1_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_USB
+ board_usb_hw_init();
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#define MAC24AA_MAC_OFFSET 0xfa
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_I2C_EEPROM
+ at91_set_ethaddr(MAC24AA_MAC_OFFSET);
+#endif
+ return 0;
+}
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+ ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_13 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_DIC_DS |
+ ATMEL_MPDDRC_CR_ZQ_LONG |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+ ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+ ddrc->rtr = 0x511;
+
+ ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
+ (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
+ (2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
+
+ ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
+ (23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
+ (200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
+
+ ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
+ (8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
+ (8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+ struct atmel_mpddrc_config ddrc_config;
+ u32 reg;
+
+ ddrc_conf(&ddrc_config);
+
+ at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+ writel(AT91_PMC_DDR, &pmc->scer);
+
+ reg = readl(&mpddrc->io_calibr);
+ reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+ reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
+ reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+ reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101);
+ writel(reg, &mpddrc->io_calibr);
+
+ writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
+ &mpddrc->rd_data_path);
+
+ ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+
+ writel(0x3, &mpddrc->cal_mr4);
+ writel(64, &mpddrc->tim_cal);
+}
+
+void at91_pmc_init(void)
+{
+ u32 tmp;
+
+ /*
+ * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
+ * so we need to slow down and configure MCKR accordingly.
+ * This is why we have a special flavor of the switching function.
+ */
+ tmp = AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_MAIN;
+ at91_mck_init_down(tmp);
+
+ tmp = AT91_PMC_PLLAR_29 |
+ AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+ AT91_PMC_PLLXR_MUL(40) |
+ AT91_PMC_PLLXR_DIV(1);
+ at91_plla_init(tmp);
+
+ tmp = AT91_PMC_MCKR_H32MXDIV |
+ AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_PLLA;
+ at91_mck_init(tmp);
+}
+#endif
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
-#ifdef CONFIG_SYS_USE_SERIALFLASH
+#ifdef CONFIG_SPI_BOOT
board_spi0_hw_init();
#endif
-#ifdef CONFIG_SYS_USE_NANDFLASH
+#ifdef CONFIG_NAND_BOOT
board_nand_hw_init();
#endif
}
#include <common.h>
#include <atmel_hlcdc.h>
#include <debug_uart.h>
-#include <dm.h>
-#include <i2c.h>
#include <lcd.h>
#include <version.h>
#include <asm/io.h>
return 0;
}
-#ifdef CONFIG_CMD_I2C
-static int set_ethaddr_from_eeprom(void)
-{
- const int ETH_ADDR_LEN = 6;
- unsigned char ethaddr[ETH_ADDR_LEN];
- const char *ETHADDR_NAME = "ethaddr";
- struct udevice *bus, *dev;
-
- if (env_get(ETHADDR_NAME))
- return 0;
-
- if (uclass_get_device_by_seq(UCLASS_I2C, 1, &bus)) {
- printf("Cannot find I2C bus 1\n");
- return -1;
- }
-
- if (dm_i2c_probe(bus, AT24MAC_ADDR, 0, &dev)) {
- printf("Failed to probe I2C chip\n");
- return -1;
- }
-
- if (dm_i2c_read(dev, AT24MAC_REG, ethaddr, ETH_ADDR_LEN)) {
- printf("Failed to read ethernet address from EEPROM\n");
- return -1;
- }
-
- if (!is_valid_ethaddr(ethaddr)) {
- printf("The ethernet address read from EEPROM is not valid!\n");
- return -1;
- }
-
- return eth_env_set_enetaddr(ETHADDR_NAME, ethaddr);
-}
-#else
-static int set_ethaddr_from_eeprom(void)
-{
- return 0;
-}
-#endif
+#define AT24MAC_MAC_OFFSET 0x9a
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
- set_ethaddr_from_eeprom();
+#ifdef CONFIG_I2C_EEPROM
+ at91_set_ethaddr(AT24MAC_MAC_OFFSET);
+#endif
return 0;
}
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
u32 tmp;
+ /*
+ * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
+ * so we need to slow down and configure MCKR accordingly.
+ * This is why we have a special flavor of the switching function.
+ */
+ tmp = AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_MAIN;
+ at91_mck_init_down(tmp);
+
tmp = AT91_PMC_PLLAR_29 |
AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
AT91_PMC_PLLXR_MUL(82) |
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
-#ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_GENERIC_ATMEL_MCI
sama5d3_xplained_mci0_hw_init();
#endif
-#elif CONFIG_SYS_USE_NANDFLASH
+#elif CONFIG_NAND_BOOT
sama5d3_xplained_nand_hw_init();
#endif
}
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
-#if CONFIG_SYS_USE_NANDFLASH
+#if CONFIG_NAND_BOOT
sama5d3xek_nand_hw_init();
#endif
}
}
#endif
+#define AT24MAC_MAC_OFFSET 0x9a
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_I2C_EEPROM
+ at91_set_ethaddr(AT24MAC_MAC_OFFSET);
+#endif
+ return 0;
+}
+#endif
+
int board_init(void)
{
/* adress of boot parameters */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
-#if CONFIG_SYS_USE_NANDFLASH
+#if CONFIG_NAND_BOOT
sama5d4_xplained_nand_hw_init();
#endif
}
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
-#if CONFIG_SYS_USE_NANDFLASH
+#if CONFIG_NAND_BOOT
sama5d4ek_nand_hw_init();
#endif
}
/* configure MMDC for SDRAM width/size and per-model calibration */
ot1200_spl_dram_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
}
/* Serial console */
static const struct pad_conf_entry cl_som_am57x_padconf_console[] = {
- {UART3_RXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_RXD */
- {UART3_TXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_TXD */
+ {UART3_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_RXD */
+ {UART3_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_TXD */
};
/* PMIC I2C */
static const struct pad_conf_entry cl_som_am57x_padconf_pmic[] = {
- {MCASP1_ACLKR, (IEN | PEN | M10)}, /* MCASP1_ACLKR.I2C4_SDA */
- {MCASP1_FSR, (IEN | PEN | M10)}, /* MCASP1_FSR.I2C4_SCL */
+ {MCASP1_ACLKR, (M10 | PIN_INPUT)}, /* MCASP1_ACLKR.I2C4_SDA */
+ {MCASP1_FSR, (M10 | PIN_INPUT)}, /* MCASP1_FSR.I2C4_SCL */
};
/* Green GPIO led */
static const struct pad_conf_entry cl_som_am57x_padconf_green_led[] = {
- {GPMC_A15, (IDIS | PDIS | PTD | M14)}, /* GPMC_A15.GPIO2_5 */
+ {GPMC_A15, (M14 | PIN_OUTPUT_PULLDOWN)}, /* GPMC_A15.GPIO2_5 */
};
/* MMC/SD Card */
static const struct pad_conf_entry cl_som_am57x_padconf_sd_card[] = {
- {MMC1_CLK, (IEN | PDIS | PTU | M0) }, /* MMC1_CLK */
- {MMC1_CMD, (IEN | PDIS | PTU | M0) }, /* MMC1_CMD */
- {MMC1_DAT0, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT0 */
- {MMC1_DAT1, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT1 */
- {MMC1_DAT2, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT2 */
- {MMC1_DAT3, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT3 */
- {MMC1_SDCD, (IEN | PEN | M14)}, /* MMC1_SDCD */
- {MMC1_SDWP, (IEN | PEN | M14)}, /* MMC1_SDWP */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_CLK */
+ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_CMD */
+ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT3 */
+ {MMC1_SDCD, (M14 | PIN_INPUT) }, /* MMC1_SDCD */
+ {MMC1_SDWP, (M14 | PIN_INPUT) }, /* MMC1_SDWP */
};
/* WiFi - must be in the safe mode on boot */
static const struct pad_conf_entry cl_som_am57x_padconf_wifi[] = {
- {UART1_CTSN, (IEN | M15)}, /* UART1_CTSN */
- {UART1_RTSN, (IEN | M15)}, /* UART1_RTSN */
- {UART2_RXD, (IEN | M15)}, /* UART2_RXD */
- {UART2_TXD, (IEN | M15)}, /* UART2_TXD */
- {UART2_CTSN, (IEN | M15)}, /* UART2_CTSN */
- {UART2_RTSN, (IEN | M15)}, /* UART2_RTSN */
+ {UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_CTSN */
+ {UART1_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_RTSN */
+ {UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RXD */
+ {UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_TXD */
+ {UART2_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_CTSN */
+ {UART2_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RTSN */
};
/* QSPI */
static const struct pad_conf_entry cl_som_am57x_padconf_qspi[] = {
- {GPMC_A13, (IEN | PEN | M1)}, /* GPMC_A13.QSPI1_RTCLK */
- {GPMC_A18, (IEN | PEN | M1)}, /* GPMC_A18.QSPI1_SCLK */
- {GPMC_A16, (IEN | PEN | M1)}, /* GPMC_A16.QSPI1_D0 */
- {GPMC_A17, (IEN | PEN | M1)}, /* GPMC_A17.QSPI1_D1 */
- {GPMC_CS2, (IEN | PDIS | PTU | M1)}, /* GPMC_CS2.QSPI1_CS0 */
+ {GPMC_A13, (M1 | PIN_INPUT) }, /* GPMC_A13.QSPI1_RTCLK */
+ {GPMC_A18, (M1 | PIN_INPUT) }, /* GPMC_A18.QSPI1_SCLK */
+ {GPMC_A16, (M1 | PIN_INPUT) }, /* GPMC_A16.QSPI1_D0 */
+ {GPMC_A17, (M1 | PIN_INPUT) }, /* GPMC_A17.QSPI1_D1 */
+ {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS2.QSPI1_CS0 */
};
/* GPIO Expander I2C */
static const struct pad_conf_entry cl_som_am57x_padconf_i2c_gpio[] = {
- {MCASP1_AXR0, (IEN | PEN | M10)}, /* MCASP1_AXR0.I2C5_SDA */
- {MCASP1_AXR1, (IEN | PEN | M10)}, /* MCASP1_AXR1.I2C5_SCL */
+ {MCASP1_AXR0, (M10 | PIN_INPUT)}, /* MCASP1_AXR0.I2C5_SDA */
+ {MCASP1_AXR1, (M10 | PIN_INPUT)}, /* MCASP1_AXR1.I2C5_SCL */
};
/* eMMC internal storage */
static const struct pad_conf_entry cl_som_am57x_padconf_emmc[] = {
- {GPMC_A19, (IEN | PDIS | PTU | M1)}, /* GPMC_A19.MMC2_DAT4 */
- {GPMC_A20, (IEN | PDIS | PTU | M1)}, /* GPMC_A20.MMC2_DAT5 */
- {GPMC_A21, (IEN | PDIS | PTU | M1)}, /* GPMC_A21.MMC2_DAT6 */
- {GPMC_A22, (IEN | PDIS | PTU | M1)}, /* GPMC_A22.MMC2_DAT7 */
- {GPMC_A23, (IEN | PDIS | PTU | M1)}, /* GPMC_A23.MMC2_CLK */
- {GPMC_A24, (IEN | PDIS | PTU | M1)}, /* GPMC_A24.MMC2_DAT0 */
- {GPMC_A25, (IEN | PDIS | PTU | M1)}, /* GPMC_A25.MMC2_DAT1 */
- {GPMC_A26, (IEN | PDIS | PTU | M1)}, /* GPMC_A26.MMC2_DAT2 */
- {GPMC_A27, (IEN | PDIS | PTU | M1)}, /* GPMC_A27.MMC2_DAT3 */
- {GPMC_CS1, (IEN | PDIS | PTU | M1)}, /* GPMC_CS1.MMC2_CMD */
+ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A19.MMC2_DAT4 */
+ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A20.MMC2_DAT5 */
+ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A21.MMC2_DAT6 */
+ {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A22.MMC2_DAT7 */
+ {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A23.MMC2_CLK */
+ {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A24.MMC2_DAT0 */
+ {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A25.MMC2_DAT1 */
+ {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A26.MMC2_DAT2 */
+ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A27.MMC2_DAT3 */
+ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS1.MMC2_CMD */
};
/* usb1_drvvbus */
static const struct pad_conf_entry cl_som_am57x_padconf_usb[] = {
- {USB1_DRVVBUS, (M0 | FSC) }, /* USB1_DRVVBUS.USB1_DRVVBUS */
+ /* USB1_DRVVBUS.USB1_DRVVBUS */
+ {USB1_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL) },
};
/* Ethernet */
static const struct pad_conf_entry cl_som_am57x_padconf_ethernet[] = {
/* MDIO bus */
- {VIN2A_D10, (PDIS | PTU | M3) }, /* VIN2A_D10.MDIO_MCLK */
- {VIN2A_D11, (IEN | PDIS | PTU | M3) }, /* VIN2A_D11.MDIO_D */
+ {VIN2A_D10, (M3 | PIN_OUTPUT_PULLUP) }, /* VIN2A_D10.MDIO_MCLK */
+ {VIN2A_D11, (M3 | PIN_INPUT_PULLUP) }, /* VIN2A_D11.MDIO_D */
/* EMAC Slave 1 at addr 0x1 - Default interface */
- {VIN2A_D12, (IDIS | PEN | M3) }, /* VIN2A_D12.RGMII1_TXC */
- {VIN2A_D13, (IDIS | PEN | M3) }, /* VIN2A_D13.RGMII1_TXCTL */
- {VIN2A_D14, (IDIS | PEN | M3) }, /* VIN2A_D14.RGMII1_TXD3 */
- {VIN2A_D15, (IDIS | PEN | M3) }, /* VIN2A_D15.RGMII1_TXD2 */
- {VIN2A_D16, (IDIS | PEN | M3) }, /* VIN2A_D16.RGMII1_TXD1 */
- {VIN2A_D17, (IDIS | PEN | M3) }, /* VIN2A_D17.RGMII1_TXD0 */
- {VIN2A_D18, (IEN | PDIS | PTD | M3) }, /* VIN2A_D18.RGMII1_RXC */
- {VIN2A_D19, (IEN | PDIS | PTD | M3) }, /* VIN2A_D19.RGMII1_RXCTL */
- {VIN2A_D20, (IEN | PDIS | PTD | M3) }, /* VIN2A_D20.RGMII1_RXD3 */
- {VIN2A_D21, (IEN | PDIS | PTD | M3) }, /* VIN2A_D21.RGMII1_RXD2 */
- {VIN2A_D22, (IEN | PDIS | PTD | M3) }, /* VIN2A_D22.RGMII1_RXD1 */
- {VIN2A_D23, (IEN | PDIS | PTD | M3) }, /* VIN2A_D23.RGMII1_RXD0 */
+ {VIN2A_D12, (M3 | PIN_OUTPUT) }, /* VIN2A_D12.RGMII1_TXC */
+ {VIN2A_D13, (M3 | PIN_OUTPUT) }, /* VIN2A_D13.RGMII1_TXCTL */
+ {VIN2A_D14, (M3 | PIN_OUTPUT) }, /* VIN2A_D14.RGMII1_TXD3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT) }, /* VIN2A_D15.RGMII1_TXD2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT) }, /* VIN2A_D16.RGMII1_TXD1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT) }, /* VIN2A_D17.RGMII1_TXD0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D18.RGMII1_RXC */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D19.RGMII1_RXCTL */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D20.RGMII1_RXD3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D21.RGMII1_RXD2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D22.RGMII1_RXD1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D23.RGMII1_RXD0 */
/* Eth PHY1 reset GPIOs*/
- {VIN2A_CLK0, (IDIS | PDIS | PTD | M14)}, /* VIN2A_CLK0.GPIO3_28 */
+ {VIN2A_CLK0, (M14 | PIN_OUTPUT_PULLDOWN)}, /* VIN2A_CLK0.GPIO3_28 */
};
#define SET_MUX(mux_array) do_set_mux32((*ctrl)->control_padconf_core_base, \
puts("!!!ERROR!!! DRAM detection failed!!!\n");
hang();
}
-
- memset(__bss_start, 0, __bss_end - __bss_start);
- board_init_r(NULL, 0);
}
void board_boot_order(u32 *spl_boot_list)
config SYS_CONFIG_NAME
default "da850evm"
+menuconfig DA850_MAC
+ bool "Use MAC Address"
+ default y
+
+if DA850_MAC
+config MAC_ADDR_IN_SPIFLASH
+ bool "MAC address in SPI Flash"
+ default y
+ help
+ The OMAP-L138 and AM1808 SoM are programmed with
+ their MAC address in SPI Flash from the factory
+ Enable this option to read the MAC from SPI Flash
+
+config MAC_ADDR_IN_EEPROM
+ bool "MAC address in EEPROM"
+ help
+ The DA850 EVM comes with SoM are programmed with
+ their MAC address in SPI Flash from the factory,
+ but the kit has an optional expansion board with
+ EEPROM available. Enable this option to read the
+ MAC from the EEPROM
+
+endif
+
endif
if TARGET_OMAPL138_LCDK
config SYS_CONFIG_NAME
default "omapl138_lcdk"
-source "board/ti/common/Kconfig"
-
endif
+
+source "board/ti/common/Kconfig"
-DA8XXEVM BOARD
-M: Nick Thompson <nick.thompson@gefanuc.com>
-S: Maintained
-F: board/davinci/da8xxevm/
-F: include/configs/da830evm.h
-F: configs/da830evm_defconfig
-
DA850_AM18XXEVM BOARD
-M: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+M: Adam Ford <aford173@gmail.com>
S: Maintained
+F: board/davinci/da8xxevm/
F: include/configs/da850evm.h
F: configs/da850_am18xxevm_defconfig
F: configs/da850evm_defconfig
enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr);
+#endif
+
#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
int spi_mac_read;
uchar buff[6];
"with the MAC address in the environment\n");
printf("Default using MAC address from environment\n");
}
-#endif
+
+#elif defined(CONFIG_MAC_ADDR_IN_EEPROM)
uint8_t enetaddr[8];
int eeprom_mac_read;
/* DDR initialization */
spl_dram_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
}
int board_init(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
+
/*
* Set CCI-400 control override register to enable barrier
* transaction
int board_init(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
- CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
/* Set CCI-400 control override register to enable barrier
* transaction */
int board_init(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
/*
* Set CCI-400 control override register to enable barrier
* transaction
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
#ifdef CONFIG_NAND_BOOT
int board_init(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
#if defined(CONFIG_DEEP_SLEEP)
void board_sleep_prepare(void)
{
- struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
major = get_soc_major_rev();
--- /dev/null
+if TARGET_LS1088AQDS
+
+config SYS_BOARD
+ default "ls1088a"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1088aqds"
+
+endif
+
+if TARGET_LS1088ARDB
+
+config SYS_BOARD
+ default "ls1088a"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1088ardb"
+
+endif
--- /dev/null
+LS1088ARDB BOARD
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Ashish Kumar <Ashish.Kumar@nxp.com>
+S: Maintained
+F: board/freescale/ls1088a/
+F: include/configs/ls1088ardb.h
+F: configs/ls1088ardb_qspi_defconfig
+
+LS1088AQDS BOARD
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Ashish Kumar <Ashish.Kumar@nxp.com>
+S: Maintained
+F: board/freescale/ls1088a/
+F: include/configs/ls1088aqds.h
+F: configs/ls1088aqds_qspi_defconfig
--- /dev/null
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1088a.o
+obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o
+obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o
+obj-y += ddr.o
--- /dev/null
+Overview
+--------
+The LS1088A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports ARM SoC LS1088A and its
+derivatives.
+
+
+LS1088A SoC Overview
+--------------------------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+
+RDB Default Switch Settings (1: ON; 0: OFF)
+-------------------------------------------
+
+For QSPI Boot
+SW1 0011 0001
+SW2 x100 0000
+SW3 1111 0010
+SW4 1001 0011
+SW5 1111 0000
+
+For SD Boot
+SW1 0010 0000
+SW2 0100 0000
+SW3 1111 0010
+SW4 1001 0011
+SW5 1111 0000
+
+For eMMC Boot
+SW1 0010 0000
+SW2 1100 0000
+SW3 1111 0010
+SW4 1001 0011
+SW5 1111 0000
+
+Alternately you can use this command to switch from QSPI to SD
+
+=> i2c mw 66 0x60 0x20; i2c mw 66 10 10;i2c mw 66 10 21
+
+ LS1088ARDB board Overview
+ -------------------------
+ - SERDES Connections, 16 lanes supporting:
+ - PCI Express - 3.0
+ - SATA 3.0
+ - XFI
+ - QSGMII
+ - DDR Controller
+ - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
+ chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
+ with FSL refernce software is 2100MT/s
+ - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB
+ - IFC/Local Bus
+ - One 2 GB NAND flash with ECC support, not as boot source
+ - CPLD of size 2K
+ - USB 3.0
+ - Two high speed USB 3.0 ports
+ - First USB 3.0 port configured as Host with Type-A connector
+ - Second USB 3.0 port configured as OTG with micro-AB connector
+ - SDHC/eMMC
+ - SDHC slot and onboard eMMC are muxed together
+ - 4 I2C controllers
+ - Two SATA onboard connectors
+ - 2 UART
+ - JTAG support
+ - QSPI emulator support
+ - TDM riser support
+
+QDS Default Switch Settings (1: ON; 0: OFF)
+-------------------------------------------
+
+For 16b IFC-NOR
+SW1 0001 0010
+SW2 x110 1111
+
+For QSPI Boot
+SW1 0011 0001
+SW2 0110 1111
+
+For SD Boot
+SW1 0010 0000
+SW2 0110 1111
+
+For eMMC Boot
+SW1 0010 0000
+SW2 1110 1111
+
+For I2C (ext. addr.)
+SW1 0010 0100
+SW2 1110 1111
+
+SW3 to SW12 are identical for all boot source
+
+SW3 0010 0100
+SW4 0010 0000
+SW5 1110 0111
+SW6 1110 1000
+SW7 0001 1101
+SW8 0000 1101
+SW9 1100 1010
+SW10 1110 1000
+SW11 1111 0100
+SW12 1111 1111
+
+ LS1088AQDS board Overview
+ -------------------------
+ - SERDES Connections, 16 lanes supporting:
+ - PCI Express - 3.0
+ - SATA 3.0
+ - 2 XFI
+ - QSGMII, SGMII with help for Riser card
+ - 2 RGMII
+ - 5 slot for Riser card or PCIe NIC
+ - DDR Controller
+ - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
+ chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
+ with FSL refernce software is 2100MT/s
+ - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB
+ - IFC/Local Bus
+ - One 2 GB NAND flash with ECC support, not as boot source
+ - CPLD of size 2K
+ - USB 3.0
+ - Two high speed USB 3.0 ports
+ - First USB 3.0 port configured as Host with Type-A connector
+ - Second USB 3.0 port configured as OTG with micro-AB connector
+ - SDHC/eMMC
+ - SDHC/eMMC slot via adaptor
+ - 4 I2C controllers
+ - Two SATA onboard connectors
+ - 2 UART
+ - JTAG support
+ - DSPI
+ - PROMJET support
+ - QSPI emulator support
+ - TDM riser support
+
+QSPI flash memory map valid for both QDS and RDB
+ Image Flash Offset
+ RCW+PBI 0x00000000
+ Boot firmware (U-Boot) 0x00100000
+ Boot firmware Environment 0x00300000
+ PPA firmware 0x00400000
+ DPAA2 MC 0x00A00000
+ DPAA2 DPL 0x00D00000
+ DPAA2 DPC 0x00E00000
+ Kernel.itb 0x01000000
--- /dev/null
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/clock.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * we use identical timing for all slots. If needed, change the code
+ * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+ */
+ pbsp = udimms[0];
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for %lu MT/s\n",
+ ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+
+
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* Enable DDR hashing */
+ popts->addr_hash = 1;
+
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
+ DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
+}
+
+
+int fsl_initdram(void)
+{
+ puts("Initializing DDR....using SPD\n");
+
+ gd->ram_size = fsl_ddr_sdram();
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1088A_DDR_H__
+#define __LS1088A_DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+#if defined(CONFIG_TARGET_LS1088ARDB)
+
+ {2, 1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,},
+ {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,},
+ {}
+#elif defined(CONFIG_TARGET_LS1088AQDS)
+ {2, 1666, 0, 8, 8, 0x0A0A0C0E, 0x0F10110C,},
+ {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2300, 0, 4, 9, 0x0A0C0D11, 0x1214150E,},
+ {}
+
+#endif
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+#endif
--- /dev/null
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+#include <hwconfig.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+#include "../common/qixis.h"
+
+#include "ls1088a_qixis.h"
+
+#define MC_BOOT_ENV_VAR "mcinitcmd"
+
+#ifdef CONFIG_FSL_MC_ENET
+
+#define SFP_TX 0
+
+ /* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
+ * Bank 1 -> Lanes A, B, C, D,
+ * Bank 2 -> Lanes A,B, C, D,
+ */
+
+ /* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
+ * means that the mapping must be determined dynamically, or that the lane
+ * maps to something other than a board slot.
+ */
+
+static u8 lane_to_slot_fsm1[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
+ * housed.
+ */
+
+static int xqsgii_riser_phy_addr[] = {
+ XQSGMII_CARD_PHY1_PORT0_ADDR,
+ XQSGMII_CARD_PHY2_PORT0_ADDR,
+ XQSGMII_CARD_PHY3_PORT0_ADDR,
+ XQSGMII_CARD_PHY4_PORT0_ADDR,
+ XQSGMII_CARD_PHY3_PORT2_ADDR,
+ XQSGMII_CARD_PHY1_PORT2_ADDR,
+ XQSGMII_CARD_PHY4_PORT2_ADDR,
+ XQSGMII_CARD_PHY2_PORT2_ADDR,
+};
+
+static int sgmii_riser_phy_addr[] = {
+ SGMII_CARD_PORT1_PHY_ADDR,
+ SGMII_CARD_PORT2_PHY_ADDR,
+ SGMII_CARD_PORT3_PHY_ADDR,
+ SGMII_CARD_PORT4_PHY_ADDR,
+};
+
+/* Slot2 does not have EMI connections */
+#define EMI_NONE 0xFF
+#define EMI1_RGMII1 0
+#define EMI1_RGMII2 1
+#define EMI1_SLOT1 2
+
+static const char * const mdio_names[] = {
+ "LS1088A_QDS_MDIO0",
+ "LS1088A_QDS_MDIO1",
+ "LS1088A_QDS_MDIO2",
+ DEFAULT_WRIOP_MDIO2_NAME,
+};
+
+struct ls1088a_qds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static void sgmii_configure_repeater(int dpmac)
+{
+ struct mii_dev *bus;
+ uint8_t a = 0xf;
+ int i, j, ret;
+ unsigned short value;
+ const char *dev = "LS1088A_QDS_MDIO2";
+ int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
+ int i2c_phy_addr = 0;
+ int phy_addr = 0;
+
+ uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
+ uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+ uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
+ uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+
+ /* Set I2c to Slot 1 */
+ i2c_write(0x77, 0, 0, &a, 1);
+
+ switch (dpmac) {
+ case 1:
+ i2c_phy_addr = i2c_addr[1];
+ phy_addr = 4;
+ break;
+ case 2:
+ i2c_phy_addr = i2c_addr[0];
+ phy_addr = 0;
+ break;
+ case 3:
+ i2c_phy_addr = i2c_addr[3];
+ phy_addr = 0xc;
+ break;
+ case 7:
+ i2c_phy_addr = i2c_addr[2];
+ phy_addr = 8;
+ break;
+ }
+
+ /* Check the PHY status */
+ ret = miiphy_set_current_dev(dev);
+ if (ret > 0)
+ goto error;
+
+ bus = mdio_get_current_dev();
+ debug("Reading from bus %s\n", bus->name);
+
+ ret = miiphy_write(dev, phy_addr, 0x1f, 3);
+ if (ret > 0)
+ goto error;
+
+ mdelay(10);
+ ret = miiphy_read(dev, phy_addr, 0x11, &value);
+ if (ret > 0)
+ goto error;
+
+ mdelay(10);
+
+ if ((value & 0xfff) == 0x401) {
+ miiphy_write(dev, phy_addr, 0x1f, 0);
+ printf("DPMAC %d:PHY is ..... Configured\n", dpmac);
+ return;
+ }
+
+ for (i = 0; i < 4; i++) {
+ for (j = 0; j < 4; j++) {
+ a = 0x18;
+ i2c_write(i2c_phy_addr, 6, 1, &a, 1);
+ a = 0x38;
+ i2c_write(i2c_phy_addr, 4, 1, &a, 1);
+ a = 0x4;
+ i2c_write(i2c_phy_addr, 8, 1, &a, 1);
+
+ i2c_write(i2c_phy_addr, 0xf, 1,
+ &ch_a_eq[i], 1);
+ i2c_write(i2c_phy_addr, 0x11, 1,
+ &ch_a_ctl2[j], 1);
+
+ i2c_write(i2c_phy_addr, 0x16, 1,
+ &ch_b_eq[i], 1);
+ i2c_write(i2c_phy_addr, 0x18, 1,
+ &ch_b_ctl2[j], 1);
+
+ a = 0x14;
+ i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
+ a = 0xb5;
+ i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
+ a = 0x20;
+ i2c_write(i2c_phy_addr, 4, 1, &a, 1);
+ mdelay(100);
+ ret = miiphy_read(dev, phy_addr, 0x11, &value);
+ if (ret > 0)
+ goto error;
+
+ mdelay(100);
+ ret = miiphy_read(dev, phy_addr, 0x11, &value);
+ if (ret > 0)
+ goto error;
+
+ if ((value & 0xfff) == 0x401) {
+ printf("DPMAC %d :PHY is configured ",
+ dpmac);
+ printf("after setting repeater 0x%x\n",
+ value);
+ i = 5;
+ j = 5;
+ } else {
+ printf("DPMAC %d :PHY is failed to ",
+ dpmac);
+ printf("configure the repeater 0x%x\n", value);
+ }
+ }
+ }
+ miiphy_write(dev, phy_addr, 0x1f, 0);
+error:
+ if (ret)
+ printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac);
+ return;
+}
+
+static void qsgmii_configure_repeater(int dpmac)
+{
+ uint8_t a = 0xf;
+ int i, j;
+ int i2c_phy_addr = 0;
+ int phy_addr = 0;
+ int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
+
+ uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
+ uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+ uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
+ uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+
+ const char *dev = mdio_names[EMI1_SLOT1];
+ int ret = 0;
+ unsigned short value;
+
+ /* Set I2c to Slot 1 */
+ i2c_write(0x77, 0, 0, &a, 1);
+
+ switch (dpmac) {
+ case 7:
+ case 8:
+ case 9:
+ case 10:
+ i2c_phy_addr = i2c_addr[2];
+ phy_addr = 8;
+ break;
+
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ i2c_phy_addr = i2c_addr[3];
+ phy_addr = 0xc;
+ break;
+ }
+
+ /* Check the PHY status */
+ ret = miiphy_set_current_dev(dev);
+ ret = miiphy_write(dev, phy_addr, 0x1f, 3);
+ mdelay(10);
+ ret = miiphy_read(dev, phy_addr, 0x11, &value);
+ mdelay(10);
+ ret = miiphy_read(dev, phy_addr, 0x11, &value);
+ mdelay(10);
+ if ((value & 0xf) == 0xf) {
+ miiphy_write(dev, phy_addr, 0x1f, 0);
+ printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
+ return;
+ }
+
+ for (i = 0; i < 4; i++) {
+ for (j = 0; j < 4; j++) {
+ a = 0x18;
+ i2c_write(i2c_phy_addr, 6, 1, &a, 1);
+ a = 0x38;
+ i2c_write(i2c_phy_addr, 4, 1, &a, 1);
+ a = 0x4;
+ i2c_write(i2c_phy_addr, 8, 1, &a, 1);
+
+ i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
+ i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
+
+ i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
+ i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
+
+ a = 0x14;
+ i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
+ a = 0xb5;
+ i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
+ a = 0x20;
+ i2c_write(i2c_phy_addr, 4, 1, &a, 1);
+ mdelay(100);
+ ret = miiphy_read(dev, phy_addr, 0x11, &value);
+ if (ret > 0)
+ goto error;
+ mdelay(1);
+ ret = miiphy_read(dev, phy_addr, 0x11, &value);
+ if (ret > 0)
+ goto error;
+ mdelay(10);
+ if ((value & 0xf) == 0xf) {
+ miiphy_write(dev, phy_addr, 0x1f, 0);
+ printf("DPMAC %d :PHY is ..... Configured\n",
+ dpmac);
+ return;
+ }
+ }
+ }
+error:
+ printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
+ return;
+}
+
+static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name = ls1088a_qds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+static void ls1088a_qds_enable_SFP_TX(u8 muxval)
+{
+ u8 brdcfg9;
+
+ brdcfg9 = QIXIS_READ(brdcfg[9]);
+ brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
+ brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
+ QIXIS_WRITE(brdcfg[9], brdcfg9);
+}
+
+static void ls1088a_qds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+
+ if (muxval <= 5) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr,
+ int devad, int regnum)
+{
+ struct ls1088a_qds_mdio *priv = bus->priv;
+
+ ls1088a_qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct ls1088a_qds_mdio *priv = bus->priv;
+
+ ls1088a_qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int ls1088a_qds_mdio_reset(struct mii_dev *bus)
+{
+ struct ls1088a_qds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct ls1088a_qds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate ls1088a_qds MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate ls1088a_qds private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = ls1088a_qds_mdio_read;
+ bus->write = ls1088a_qds_mdio_write;
+ bus->reset = ls1088a_qds_mdio_reset;
+ sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+
+ return mdio_register(bus);
+}
+
+/*
+ * Initialize the dpmac_info array.
+ *
+ */
+static void initialize_dpmac_to_slot(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 serdes1_prtcl, cfg;
+
+ cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
+ FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
+ serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
+
+ switch (serdes1_prtcl) {
+ case 0x12:
+ printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+ serdes1_prtcl);
+ lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
+ lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
+ lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
+ lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
+ break;
+ case 0x15:
+ case 0x1D:
+ printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+ serdes1_prtcl);
+ lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
+ lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
+ lane_to_slot_fsm1[2] = EMI_NONE;
+ lane_to_slot_fsm1[3] = EMI_NONE;
+ break;
+ case 0x1E:
+ printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+ serdes1_prtcl);
+ lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
+ lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
+ lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
+ lane_to_slot_fsm1[3] = EMI_NONE;
+ break;
+ case 0x3A:
+ printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+ serdes1_prtcl);
+ lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
+ lane_to_slot_fsm1[1] = EMI_NONE;
+ lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
+ lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
+ break;
+
+ default:
+ printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
+ __func__, serdes1_prtcl);
+ break;
+ }
+}
+
+void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
+{
+ struct mii_dev *bus;
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 serdes1_prtcl, cfg;
+
+ cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
+ FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
+ serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
+
+ int *riser_phy_addr;
+ char *env_hwconfig = env_get("hwconfig");
+
+ if (hwconfig_f("xqsgmii", env_hwconfig))
+ riser_phy_addr = &xqsgii_riser_phy_addr[0];
+ else
+ riser_phy_addr = &sgmii_riser_phy_addr[0];
+
+ switch (serdes1_prtcl) {
+ case 0x12:
+ case 0x15:
+ case 0x1E:
+ case 0x3A:
+ switch (dpmac_id) {
+ case 1:
+ wriop_set_phy_address(dpmac_id, riser_phy_addr[1]);
+ break;
+ case 2:
+ wriop_set_phy_address(dpmac_id, riser_phy_addr[0]);
+ break;
+ case 3:
+ wriop_set_phy_address(dpmac_id, riser_phy_addr[3]);
+ break;
+ case 7:
+ wriop_set_phy_address(dpmac_id, riser_phy_addr[2]);
+ break;
+ default:
+ printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
+ break;
+ }
+ break;
+ default:
+ printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
+ __func__, serdes1_prtcl);
+ return;
+ }
+ dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
+ bus = mii_dev_for_muxval(EMI1_SLOT1);
+ wriop_set_mdio(dpmac_id, bus);
+}
+
+void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
+{
+ struct mii_dev *bus;
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 serdes1_prtcl, cfg;
+
+ cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
+ FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
+ serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
+
+ switch (serdes1_prtcl) {
+ case 0x1D:
+ case 0x1E:
+ switch (dpmac_id) {
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ wriop_set_phy_address(dpmac_id, dpmac_id + 9);
+ break;
+ case 7:
+ case 8:
+ case 9:
+ case 10:
+ wriop_set_phy_address(dpmac_id, dpmac_id + 1);
+ break;
+ }
+
+ dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
+ bus = mii_dev_for_muxval(EMI1_SLOT1);
+ wriop_set_mdio(dpmac_id, bus);
+ break;
+ default:
+ printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+ serdes1_prtcl);
+ break;
+ }
+}
+
+void ls1088a_handle_phy_interface_xsgmii(int i)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 serdes1_prtcl, cfg;
+
+ cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
+ FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
+ serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
+
+ switch (serdes1_prtcl) {
+ case 0x15:
+ case 0x1D:
+ case 0x1E:
+ wriop_set_phy_address(i, i + 26);
+ ls1088a_qds_enable_SFP_TX(SFP_TX);
+ break;
+ default:
+ printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+ serdes1_prtcl);
+ break;
+ }
+}
+
+static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 serdes1_prtcl, cfg;
+ struct mii_dev *bus;
+
+ cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
+ FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
+ serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
+
+ switch (dpmac_id) {
+ case 4:
+ wriop_set_phy_address(dpmac_id, RGMII_PHY1_ADDR);
+ dpmac_info[dpmac_id].board_mux = EMI1_RGMII1;
+ bus = mii_dev_for_muxval(EMI1_RGMII1);
+ wriop_set_mdio(dpmac_id, bus);
+ break;
+ case 5:
+ wriop_set_phy_address(dpmac_id, RGMII_PHY2_ADDR);
+ dpmac_info[dpmac_id].board_mux = EMI1_RGMII2;
+ bus = mii_dev_for_muxval(EMI1_RGMII2);
+ wriop_set_mdio(dpmac_id, bus);
+ break;
+ default:
+ printf("qds: WRIOP: Unsupported RGMII SerDes Protocol 0x%02x\n",
+ serdes1_prtcl);
+ break;
+ }
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int error = 0, i;
+ char *mc_boot_env_var;
+#ifdef CONFIG_FSL_MC_ENET
+ struct memac_mdio_info *memac_mdio0_info;
+ char *env_hwconfig = env_get("hwconfig");
+
+ initialize_dpmac_to_slot();
+
+ memac_mdio0_info = (struct memac_mdio_info *)malloc(
+ sizeof(struct memac_mdio_info));
+ memac_mdio0_info->regs =
+ (struct memac_mdio_controller *)
+ CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
+
+ /* Register the real MDIO1 bus */
+ fm_memac_mdio_init(bis, memac_mdio0_info);
+ /* Register the muxing front-ends to the MDIO buses */
+ ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
+ ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);
+ ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
+
+ for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+ switch (wriop_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_RGMII:
+ ls1088a_handle_phy_interface_rgmii(i);
+ break;
+ case PHY_INTERFACE_MODE_QSGMII:
+ ls1088a_handle_phy_interface_qsgmii(i);
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+ ls1088a_handle_phy_interface_sgmii(i);
+ break;
+ case PHY_INTERFACE_MODE_XGMII:
+ ls1088a_handle_phy_interface_xsgmii(i);
+ break;
+ default:
+ break;
+
+ if (i == 16)
+ i = NUM_WRIOP_PORTS;
+ }
+ }
+
+ mc_boot_env_var = env_get(MC_BOOT_ENV_VAR);
+ if (mc_boot_env_var)
+ run_command_list(mc_boot_env_var, -1, 0);
+ error = cpu_eth_init(bis);
+
+ if (hwconfig_f("xqsgmii", env_hwconfig)) {
+ for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+ switch (wriop_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_QSGMII:
+ qsgmii_configure_repeater(i);
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+ sgmii_configure_repeater(i);
+ break;
+ default:
+ break;
+ }
+
+ if (i == 16)
+ i = NUM_WRIOP_PORTS;
+ }
+ }
+#endif
+ error = pci_eth_init(bis);
+ return error;
+}
--- /dev/null
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <exports.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MC_BOOT_ENV_VAR "mcinitcmd"
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+ char *mc_boot_env_var;
+ int i, interface;
+ struct memac_mdio_info mdio_info;
+ struct mii_dev *dev;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct memac_mdio_controller *reg;
+ u32 srds_s1, cfg;
+
+ cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
+ FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
+
+ srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
+
+ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ mdio_info.regs = reg;
+ mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+ /* Register the EMI 1 */
+ fm_memac_mdio_init(bis, &mdio_info);
+
+ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ mdio_info.regs = reg;
+ mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
+
+ /* Register the EMI 2 */
+ fm_memac_mdio_init(bis, &mdio_info);
+
+ switch (srds_s1) {
+ case 0x1D:
+ /*
+ * XFI does not need a PHY to work, but to avoid U-boot use
+ * default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to XFI
+ * MAC error.
+ */
+ wriop_set_phy_address(WRIOP1_DPMAC1, 0x0a);
+ wriop_set_phy_address(WRIOP1_DPMAC2, AQ_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC3, QSGMII1_PORT1_PHY_ADDR);
+ wriop_set_phy_address(WRIOP1_DPMAC4, QSGMII1_PORT2_PHY_ADDR);
+ wriop_set_phy_address(WRIOP1_DPMAC5, QSGMII1_PORT3_PHY_ADDR);
+ wriop_set_phy_address(WRIOP1_DPMAC6, QSGMII1_PORT4_PHY_ADDR);
+ wriop_set_phy_address(WRIOP1_DPMAC7, QSGMII2_PORT1_PHY_ADDR);
+ wriop_set_phy_address(WRIOP1_DPMAC8, QSGMII2_PORT2_PHY_ADDR);
+ wriop_set_phy_address(WRIOP1_DPMAC9, QSGMII2_PORT3_PHY_ADDR);
+ wriop_set_phy_address(WRIOP1_DPMAC10, QSGMII2_PORT4_PHY_ADDR);
+
+ break;
+ default:
+ printf("SerDes1 protocol 0x%x is not supported on LS1088ARDB\n",
+ srds_s1);
+ break;
+ }
+
+ for (i = WRIOP1_DPMAC3; i <= WRIOP1_DPMAC10; i++) {
+ interface = wriop_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_QSGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+ wriop_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+ wriop_set_mdio(WRIOP1_DPMAC2, dev);
+
+ mc_boot_env_var = env_get(MC_BOOT_ENV_VAR);
+ if (mc_boot_env_var)
+ run_command_list(mc_boot_env_var, -1, 0);
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
--- /dev/null
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fsl_ddr.h>
+#include <fsl_sec.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <fsl-mc/fsl_mc.h>
+#include <environment.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+#include <asm/arch/ppa.h>
+
+#include "../common/qixis.h"
+#include "ls1088a_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned long long get_qixis_addr(void)
+{
+ unsigned long long addr;
+
+ if (gd->flags & GD_FLG_RELOC)
+ addr = QIXIS_BASE_PHYS;
+ else
+ addr = QIXIS_BASE_PHYS_EARLY;
+
+ /*
+ * IFC address under 256MB is mapped to 0x30000000, any address above
+ * is mapped to 0x5_10000000 up to 4GB.
+ */
+ addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
+
+ return addr;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ u8 sw;
+ static const char *const freq[] = {"100", "125", "156.25",
+ "100 separate SSCG"};
+ int clock;
+
+#ifdef CONFIG_TARGET_LS1088AQDS
+ printf("Board: LS1088A-QDS, ");
+#else
+ printf("Board: LS1088A-RDB, ");
+#endif
+
+ sw = QIXIS_READ(arch);
+ printf("Board Arch: V%d, ", sw >> 4);
+
+#ifdef CONFIG_TARGET_LS1088AQDS
+ printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+#else
+ printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
+#endif
+
+ memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+#ifdef CONFIG_SD_BOOT
+ puts("SD card\n");
+#endif
+ switch (sw) {
+#ifdef CONFIG_TARGET_LS1088AQDS
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ printf("vBank: %d\n", sw);
+ break;
+ case 8:
+ puts("PromJet\n");
+ break;
+ case 15:
+ puts("IFCCard\n");
+ break;
+ case 14:
+#else
+ case 0:
+#endif
+ puts("QSPI:");
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
+ if (sw == 0 || sw == 4)
+ puts("0\n");
+ else if (sw == 1)
+ puts("1\n");
+ else
+ puts("EMU\n");
+ break;
+
+ default:
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+ break;
+ }
+
+#ifdef CONFIG_TARGET_LS1088AQDS
+ printf("FPGA: v%d (%s), build %d",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+#else
+ printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
+#endif
+
+ /*
+ * Display the actual SERDES reference clocks as configured by the
+ * dip switches on the board. Note that the SWx registers could
+ * technically be set to force the reference clocks to match the
+ * values that the SERDES expects (or vice versa). For now, however,
+ * we just display both values and hope the user notices when they
+ * don't match.
+ */
+ puts("SERDES1 Reference : ");
+ sw = QIXIS_READ(brdcfg[2]);
+ clock = (sw >> 6) & 3;
+ printf("Clock1 = %sMHz ", freq[clock]);
+ clock = (sw >> 4) & 3;
+ printf("Clock2 = %sMHz", freq[clock]);
+
+ puts("\nSERDES2 Reference : ");
+ clock = (sw >> 2) & 3;
+ printf("Clock1 = %sMHz ", freq[clock]);
+ clock = (sw >> 0) & 3;
+ printf("Clock2 = %sMHz\n", freq[clock]);
+
+ return 0;
+}
+
+bool if_board_diff_clk(void)
+{
+#ifdef CONFIG_TARGET_LS1088AQDS
+ u8 diff_conf = QIXIS_READ(brdcfg[11]);
+ return diff_conf & 0x40;
+#else
+ u8 diff_conf = QIXIS_READ(dutcfg[11]);
+ return diff_conf & 0x80;
+#endif
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0f) {
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ if (if_board_diff_clk())
+ return get_board_sys_clk();
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+
+ return 66666666;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+void board_retimer_init(void)
+{
+ u8 reg;
+
+ /* Retimer is connected to I2C1_CH5 */
+ select_i2c_ch_pca9547(I2C_MUX_CH5);
+
+ /* Access to Control/Shared register */
+ reg = 0x0;
+ i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
+
+ /* Read device revision and ID */
+ i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
+ debug("Retimer version id = 0x%x\n", reg);
+
+ /* Enable Broadcast. All writes target all channel register sets */
+ reg = 0x0c;
+ i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
+
+ /* Reset Channel Registers */
+ i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
+ reg |= 0x4;
+ i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
+
+ /* Set data rate as 10.3125 Gbps */
+ reg = 0x90;
+ i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
+ reg = 0xb3;
+ i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
+ reg = 0x90;
+ i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
+ reg = 0xb3;
+ i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
+ reg = 0xcd;
+ i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
+
+ /* Select VCO Divider to full rate (000) */
+ i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
+ reg &= 0x0f;
+ reg |= 0x70;
+ i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
+
+#ifdef CONFIG_TARGET_LS1088AQDS
+ /* Retimer is connected to I2C1_CH5 */
+ select_i2c_ch_pca9547(I2C_MUX_CH5);
+
+ /* Access to Control/Shared register */
+ reg = 0x0;
+ i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
+
+ /* Read device revision and ID */
+ i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
+ debug("Retimer version id = 0x%x\n", reg);
+
+ /* Enable Broadcast. All writes target all channel register sets */
+ reg = 0x0c;
+ i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
+
+ /* Reset Channel Registers */
+ i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
+ reg |= 0x4;
+ i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
+
+ /* Set data rate as 10.3125 Gbps */
+ reg = 0x90;
+ i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
+ reg = 0xb3;
+ i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
+ reg = 0x90;
+ i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
+ reg = 0xb3;
+ i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
+ reg = 0xcd;
+ i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
+
+ /* Select VCO Divider to full rate (000) */
+ i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
+ reg &= 0x0f;
+ reg |= 0x70;
+ i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
+#endif
+ /*return the default channel*/
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+}
+
+int board_init(void)
+{
+ init_final_memctl_regs();
+#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
+ u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
+
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ board_retimer_init();
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
+ /* invert AQR105 IRQ pins polarity */
+ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+ ppa_init();
+#endif
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch3_early_init_f();
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ puts("\nDDR ");
+ print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+ print_ddr_info(0);
+}
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+#ifdef CONFIG_FSL_CAAM
+ sec_init();
+#endif
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+void fdt_fixup_board_enet(void *fdt)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/fsl-mc");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/fsl,dprc@0");
+
+ if (offset < 0) {
+ printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
+ __func__, offset);
+ return;
+ }
+
+ if (get_mc_boot_status() == 0)
+ fdt_status_okay(fdt, offset);
+ else
+ fdt_status_fail(fdt, offset);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int err, i;
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ ft_cpu_setup(blob, bd);
+
+ /* fixup DT for the two GPP DDR banks */
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ base[i] = gd->bd->bi_dram[i].start;
+ size[i] = gd->bd->bi_dram[i].size;
+ }
+
+#ifdef CONFIG_RESV_RAM
+ /* reduce size if reserved memory is within this bank */
+ if (gd->arch.resv_ram >= base[0] &&
+ gd->arch.resv_ram < base[0] + size[0])
+ size[0] = gd->arch.resv_ram - base[0];
+ else if (gd->arch.resv_ram >= base[1] &&
+ gd->arch.resv_ram < base[1] + size[1])
+ size[1] = gd->arch.resv_ram - base[1];
+#endif
+
+ fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+
+#ifdef CONFIG_FSL_MC_ENET
+ fdt_fixup_board_enet(blob);
+ err = fsl_mc_ldpaa_exit(bd);
+ if (err)
+ return err;
+#endif
+
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1088AQDS_QIXIS_H__
+#define __LS1088AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1088AQDS */
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+#define QIXIS_SYSCLK_150 0x5
+#define QIXIS_SYSCLK_160 0x6
+#define QIXIS_SYSCLK_166 0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100 0x0
+#define QIXIS_SDCLK1_125 0x1
+#define QIXIS_SDCLK1_165 0x2
+#define QIXIS_SDCLK1_100_SP 0x3
+
+#define BRDCFG4_EMISEL_MASK 0xE0
+#define BRDCFG4_EMISEL_SHIFT 5
+#define BRDCFG9_SFPTX_MASK 0x10
+#define BRDCFG9_SFPTX_SHIFT 4
+
+#endif
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
rtc_enable_32khz_output();
+#ifdef CONFIG_FSL_CAAM
+ sec_init();
+#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
return 0;
}
M: Saksham Jain <saksham.jain@nxp.freescale.com>
S: Maintained
F: configs/ls2080ardb_SECURE_BOOT_defconfig
+
+LS2088A_QSPI_SECURE_BOOT BOARD
+M: Udit Agarwal <udit.agarwal@nxp.com>
+S: Maintained
+F: configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
#ifdef CONFIG_FSL_QIXIS
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
#endif
+
+#ifdef CONFIG_FSL_CAAM
+ sec_init();
+#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
- return set_clk_enet(ENET_125MHz);
+ return set_clk_enet(ENET_125MHZ);
}
spl_dram_init(8 << ventana_info.sdram_width,
16 << ventana_info.sdram_size,
board_model);
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
}
void board_boot_order(u32 *spl_boot_list)
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := bx50v3.o
+obj-y := bx50v3.o vpd_reader.o
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <pwm.h>
+#include <stdlib.h>
+#include "vpd_reader.h"
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_SYS_I2C_EEPROM_ADDR
+# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#endif
+
+#ifndef CONFIG_SYS_I2C_EEPROM_BUS
+#define CONFIG_SYS_I2C_EEPROM_BUS 2
+#endif
+
#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS)
return 1;
}
+#define VPD_TYPE_INVALID 0x00
+#define VPD_BLOCK_NETWORK 0x20
+#define VPD_BLOCK_HWID 0x44
+#define VPD_PRODUCT_B850 1
+#define VPD_PRODUCT_B650 2
+#define VPD_PRODUCT_B450 3
+
+struct vpd_cache {
+ uint8_t product_id;
+ uint8_t macbits;
+ unsigned char mac1[6];
+};
+
+/*
+ * Extracts MAC and product information from the VPD.
+ */
+static int vpd_callback(
+ void *userdata,
+ uint8_t id,
+ uint8_t version,
+ uint8_t type,
+ size_t size,
+ uint8_t const *data)
+{
+ struct vpd_cache *vpd = (struct vpd_cache *)userdata;
+
+ if ( id == VPD_BLOCK_HWID
+ && version == 1
+ && type != VPD_TYPE_INVALID
+ && size >= 1) {
+ vpd->product_id = data[0];
+
+ } else if ( id == VPD_BLOCK_NETWORK
+ && version == 1
+ && type != VPD_TYPE_INVALID
+ && size >= 6) {
+ vpd->macbits |= 1;
+ memcpy(vpd->mac1, data, 6);
+ }
+
+ return 0;
+}
+
+static void set_eth0_mac_address(unsigned char * mac)
+{
+ uint32_t *ENET_TCR = (uint32_t*)0x21880c4;
+ uint32_t *ENET_PALR = (uint32_t*)0x21880e4;
+ uint32_t *ENET_PAUR = (uint32_t*)0x21880e8;
+
+ *ENET_TCR |= 0x100; /* ADDINS */
+ *ENET_PALR |= (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+ *ENET_PAUR |= (mac[4] << 24) | (mac[5] << 16);
+}
+
+static void process_vpd(struct vpd_cache *vpd)
+{
+ if ( vpd->product_id == VPD_PRODUCT_B850
+ || vpd->product_id == VPD_PRODUCT_B650
+ || vpd->product_id == VPD_PRODUCT_B450) {
+ if (vpd->macbits & 1) {
+ set_eth0_mac_address(vpd->mac1);
+ }
+ }
+}
+
+static int read_vpd(uint eeprom_bus)
+{
+ struct vpd_cache vpd;
+ int res;
+ int size = 1024;
+ uint8_t *data;
+ unsigned int current_i2c_bus = i2c_get_bus_num();
+
+ res = i2c_set_bus_num(eeprom_bus);
+ if (res < 0)
+ return res;
+
+ data = (uint8_t *)malloc(size);
+ if (!data)
+ return -ENOMEM;
+
+ res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, data, size);
+
+ if (res == 0) {
+ memset(&vpd, 0, sizeof(vpd));
+ vpd_reader(size, data, &vpd, vpd_callback);
+ process_vpd(&vpd);
+ }
+
+ free(data);
+
+ i2c_set_bus_num(current_i2c_bus);
+ return res;
+}
+
int board_eth_init(bd_t *bis)
{
setup_iomux_enet();
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+ read_vpd(CONFIG_SYS_I2C_EEPROM_BUS);
+
return 0;
}
--- /dev/null
+/*
+ * Copyright 2016 General Electric Company
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "vpd_reader.h"
+
+#include <linux/bch.h>
+#include <stdlib.h>
+
+
+/* BCH configuration */
+
+const struct {
+ int header_ecc_capability_bits;
+ int data_ecc_capability_bits;
+ unsigned int prim_poly;
+ struct {
+ int min;
+ int max;
+ } galois_field_order;
+} bch_configuration = {
+ .header_ecc_capability_bits = 4,
+ .data_ecc_capability_bits = 16,
+ .prim_poly = 0,
+ .galois_field_order = {
+ .min = 5,
+ .max = 15,
+ },
+};
+
+static int calculate_galois_field_order(size_t source_length)
+{
+ int gfo = bch_configuration.galois_field_order.min;
+
+ for (; gfo < bch_configuration.galois_field_order.max &&
+ ((((1 << gfo) - 1) - ((int)source_length * 8)) < 0);
+ gfo++) {
+ }
+
+ if (gfo == bch_configuration.galois_field_order.max) {
+ return -1;
+ }
+
+ return gfo + 1;
+}
+
+static int verify_bch(int ecc_bits, unsigned int prim_poly,
+ uint8_t * data, size_t data_length,
+ const uint8_t * ecc, size_t ecc_length)
+{
+ int gfo = calculate_galois_field_order(data_length);
+ if (gfo < 0) {
+ return -1;
+ }
+
+ struct bch_control * bch = init_bch(gfo, ecc_bits, prim_poly);
+ if (!bch) {
+ return -1;
+ }
+
+ if (bch->ecc_bytes != ecc_length) {
+ free_bch(bch);
+ return -1;
+ }
+
+ unsigned * errloc = (unsigned *)calloc(data_length, sizeof(unsigned));
+ int errors = decode_bch(
+ bch, data, data_length, ecc, NULL, NULL, errloc);
+ free_bch(bch);
+ if (errors < 0) {
+ free(errloc);
+ return -1;
+ }
+
+ if (errors > 0) {
+ for (int n = 0; n < errors; n++) {
+ if (errloc[n] >= 8 * data_length) {
+ /* n-th error located in ecc (no need for data correction) */
+ } else {
+ /* n-th error located in data */
+ data[errloc[n] / 8] ^= 1 << (errloc[n] % 8);
+ }
+ }
+ }
+
+ free(errloc);
+ return 0;
+}
+
+
+static const int ID = 0;
+static const int LEN = 1;
+static const int VER = 2;
+static const int TYP = 3;
+static const int BLOCK_SIZE = 4;
+
+static const uint8_t HEADER_BLOCK_ID = 0x00;
+static const uint8_t HEADER_BLOCK_LEN = 18;
+static const uint32_t HEADER_BLOCK_MAGIC = 0xca53ca53;
+static const size_t HEADER_BLOCK_VERIFY_LEN = 14;
+static const size_t HEADER_BLOCK_ECC_OFF = 14;
+static const size_t HEADER_BLOCK_ECC_LEN = 4;
+
+static const uint8_t ECC_BLOCK_ID = 0xFF;
+
+int vpd_reader(
+ size_t size,
+ uint8_t * data,
+ void * userdata,
+ int (*fn)(
+ void * userdata,
+ uint8_t id,
+ uint8_t version,
+ uint8_t type,
+ size_t size,
+ uint8_t const * data))
+{
+ if ( size < HEADER_BLOCK_LEN
+ || data == NULL
+ || fn == NULL) {
+ return -EINVAL;
+ }
+
+ /*
+ * +--------------------+--------------------+--//--+--------------------+
+ * | header block | data block | ... | ecc block |
+ * +--------------------+--------------------+--//--+--------------------+
+ * : : :
+ * +------+-------+-----+ +------+-------------+
+ * | id | magic | ecc | | ... | ecc |
+ * | len | off | | +------+-------------+
+ * | ver | size | | :
+ * | type | | | :
+ * +------+-------+-----+ :
+ * : : : :
+ * <----- [1] ----> <----------- [2] ----------->
+ *
+ * Repair (if necessary) the contents of header block [1] by using a
+ * 4 byte ECC located at the end of the header block. A successful
+ * return value means that we can trust the header.
+ */
+ int ret = verify_bch(
+ bch_configuration.header_ecc_capability_bits,
+ bch_configuration.prim_poly,
+ data,
+ HEADER_BLOCK_VERIFY_LEN,
+ &data[HEADER_BLOCK_ECC_OFF],
+ HEADER_BLOCK_ECC_LEN);
+ if (ret < 0) {
+ return ret;
+ }
+
+ /* Validate header block { id, length, version, type }. */
+ if ( data[ID] != HEADER_BLOCK_ID
+ || data[LEN] != HEADER_BLOCK_LEN
+ || data[VER] != 0
+ || data[TYP] != 0
+ || ntohl(*(uint32_t *)(&data[4])) != HEADER_BLOCK_MAGIC) {
+ return -EINVAL;
+ }
+
+ uint32_t offset = ntohl(*(uint32_t *)(&data[8]));
+ uint16_t size_bits = ntohs(*(uint16_t *)(&data[12]));
+
+ /* Check that ECC header fits. */
+ if (offset + 3 >= size) {
+ return -EINVAL;
+ }
+
+ /* Validate ECC block. */
+ uint8_t * ecc = &data[offset];
+ if ( ecc[ID] != ECC_BLOCK_ID
+ || ecc[LEN] < BLOCK_SIZE
+ || ecc[LEN] + offset > size
+ || ecc[LEN] - BLOCK_SIZE != size_bits / 8
+ || ecc[VER] != 1
+ || ecc[TYP] != 1) {
+ return -EINVAL;
+ }
+
+ /*
+ * Use the header block to locate the ECC block and verify the data
+ * blocks [2] against the ecc block ECC.
+ */
+ ret = verify_bch(
+ bch_configuration.data_ecc_capability_bits,
+ bch_configuration.prim_poly,
+ &data[data[LEN]],
+ offset - data[LEN],
+ &data[offset + BLOCK_SIZE],
+ ecc[LEN] - BLOCK_SIZE);
+ if (ret < 0) {
+ return ret;
+ }
+
+ /* Stop after ECC. Ignore possible zero padding. */
+ size = offset;
+
+ for (;;) {
+ /* Move to next block. */
+ size -= data[LEN];
+ data += data[LEN];
+
+ if (size == 0) {
+ /* Finished iterating through blocks. */
+ return 0;
+ }
+
+ if ( size < BLOCK_SIZE
+ || data[LEN] < BLOCK_SIZE) {
+ /* Not enough data for a header, or short header. */
+ return -EINVAL;
+ }
+
+ ret = fn(
+ userdata,
+ data[ID],
+ data[VER],
+ data[TYP],
+ data[LEN] - BLOCK_SIZE,
+ &data[BLOCK_SIZE]);
+ if (ret) {
+ return ret;
+ }
+ }
+}
--- /dev/null
+/*
+ * Copyright 2016 General Electric Company
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "common.h"
+
+/*
+ * Read VPD from given data, verify content, and call callback
+ * for each vital product data block.
+ *
+ * Returns Non-zero on error. Negative numbers encode errno.
+ */
+int vpd_reader(
+ size_t size,
+ uint8_t * data,
+ void * userdata,
+ int (*fn)(
+ void * userdata,
+ uint8_t id,
+ uint8_t version,
+ uint8_t type,
+ size_t size,
+ uint8_t const * data));
4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC,
PCIe and some other sensor interfaces.
+config TARGET_CHERRYHILL
+ bool "Cherry Hill"
+ help
+ This is the Intel Cherry Hill Customer Reference Board. It is in a
+ mini-ITX form factor containing the Intel Braswell SoC, which has
+ a 64-bit quad-core, single-thread, Intel Atom processor, along with
+ serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe,
+ some GPIOs, one HDMI and two DP video out.
+
config TARGET_COUGARCANYON2
bool "Cougar Canyon 2"
help
endchoice
source "board/intel/bayleybay/Kconfig"
+source "board/intel/cherryhill/Kconfig"
source "board/intel/cougarcanyon2/Kconfig"
source "board/intel/crownbay/Kconfig"
source "board/intel/edison/Kconfig"
--- /dev/null
+if TARGET_CHERRYHILL
+
+config SYS_BOARD
+ default "cherryhill"
+
+config SYS_VENDOR
+ default "intel"
+
+config SYS_SOC
+ default "braswell"
+
+config SYS_CONFIG_NAME
+ default "cherryhill"
+
+config SYS_TEXT_BASE
+ default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select X86_RESET_VECTOR
+ select INTEL_BRASWELL
+ select BOARD_ROMSIZE_KB_8192
+ select SPI_FLASH_MACRONIX
+
+endif
--- /dev/null
+INTEL CHERRYHILL BOARD
+M: Bin Meng <bmeng.cn@gmail.com>
+S: Maintained
+F: board/intel/cherryhill/
+F: include/configs/cherryhill.h
+F: configs/cherryhill_defconfig
--- /dev/null
+#
+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cherryhill.o start.o
--- /dev/null
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/fsp/fsp_support.h>
+
+static const struct gpio_family gpio_family[] = {
+ GPIO_FAMILY_CONF("SOUTHEAST_2_hshvfamily_2x3_rcomp_7_0", NA, 0,
+ VOLT_1_8, NA, NA, NA, 0, ENABLE, 2, SOUTHEAST),
+
+ /* end of the table */
+ GPIO_FAMILY_CONF("GPIO FAMILY TABLE END", NA, 0,
+ VOLT_1_8, NA, NA, NA, 0, DISABLE, 0, TERMINATOR),
+};
+
+static const struct gpio_pad gpio_pad[] = {
+ GPIO_PAD_CONF("N37: CX_PRDY_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 29, NA, 0x4c38, NORTH),
+ GPIO_PAD_CONF("N35: CX_PRDY_B_2", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 27, NA, 0x4c28, NORTH),
+ GPIO_PAD_CONF("N39: CX_PREQ_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 20, NA, 0x4858, NORTH),
+ GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW,
+ NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 37, NA, 0x5018, NORTH),
+ GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW,
+ NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 42, NA, 0x5040, NORTH),
+ GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW,
+ NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 35, NA, 0x5008, NORTH),
+ GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW,
+ NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 40, NA, 0x5030, NORTH),
+ GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW,
+ NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 45, NA, 0x5058, NORTH),
+ GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW,
+ NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 34, NA, 0x5000, NORTH),
+ GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GPO, LOW,
+ NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 38, NA, 0x5020, NORTH),
+ GPIO_PAD_CONF("N54: GP_CAMERASB07", GPIO, M1, GPO, LOW,
+ NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 43, NA, 0x5048, NORTH),
+ GPIO_PAD_CONF("N47: GP_CAMERASB08", GPIO, M1, GPO, LOW,
+ NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 36, NA, 0x5010, NORTH),
+ GPIO_PAD_CONF("N52: GP_CAMERASB09", GPIO, M1, GPO, LOW,
+ NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 41, NA, 0x5038, NORTH),
+ GPIO_PAD_CONF("N50: GP_CAMERASB10", GPIO, M1, GPO, LOW,
+ NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 39, NA, 0x5028, NORTH),
+ GPIO_PAD_CONF("N55: GP_CAMERASB11", GPIO, M1, GPO, LOW,
+ NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 44, NA, 0x5050, NORTH),
+ GPIO_PAD_CONF("N00: GPIO_DFX0", NATIVE, M5, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 0, NA, 0x4400, NORTH),
+ GPIO_PAD_CONF("N03: GPIO_DFX1", NATIVE, M5, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 3, NA, 0x4418, NORTH),
+ GPIO_PAD_CONF("N07: GPIO_DFX2", NATIVE, M5, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 2, NA, 0x4438, NORTH),
+ GPIO_PAD_CONF("N01: GPIO_DFX3", NATIVE, M5, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+ NA, 1, NA, 0x4408, NORTH),
+ GPIO_PAD_CONF("N05: GPIO_DFX4", GPIO, M1, GPO, HIGH, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 5, NA, 0x4428, NORTH),
+ GPIO_PAD_CONF("N04: GPIO_DFX5", GPIO, M1, GPO, HIGH, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 4, NA, 0x4420, NORTH),
+ GPIO_PAD_CONF("N08: GPIO_DFX6", NATIVE, M8, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 8, NA, 0x4440, NORTH),
+ GPIO_PAD_CONF("N02: GPIO_DFX7", GPIO, M1, GPO, LOW, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 2, NA, 0x4410, NORTH),
+ GPIO_PAD_CONF("N15: GPIO_SUS0", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 9 , NA, 0x4800, NORTH),
+ GPIO_PAD_CONF("N19: GPIO_SUS1", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 13, NA, 0x4820, NORTH),
+ GPIO_PAD_CONF("N24: GPIO_SUS2", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 18, NA, 0x4848, NORTH),
+ GPIO_PAD_CONF("N17: GPIO_SUS3", NATIVE, M6, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 11, NA, 0x4810, NORTH),
+ GPIO_PAD_CONF("N22: GPIO_SUS4", GPIO, M1, GPO, HIGH, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 16, NA, 0x4838, NORTH),
+ GPIO_PAD_CONF("N20: GPIO_SUS5", GPIO, M1, GPO, HIGH, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 14, NA, 0x4828, NORTH),
+ GPIO_PAD_CONF("N25: GPIO_SUS6", GPIO, M1, GPI, NA, NA,
+ TRIG_EDGE_LOW, L9, NA, NA, NA, NON_MASKABLE,
+ EN_EDGE_RX_DATA, NO_INVERSION,
+ NA, 19, SCI, 0x4850, NORTH),
+ GPIO_PAD_CONF("N18: GPIO_SUS7", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 12, SMI, 0x4818, NORTH),
+ GPIO_PAD_CONF("N71: HV_DDI0_DDC_SCL", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 57, NA, 0x5458, NORTH),
+ GPIO_PAD_CONF("N66: HV_DDI0_DDC_SDA", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 52, NA, 0x5430, NORTH),
+ GPIO_PAD_CONF("N61: HV_DDI0_HPD", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+ NA, 47, NA, 0x5408, NORTH),
+ GPIO_PAD_CONF("N64: HV_DDI1_HPD", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+ NA, 50, NA, 0x5420, NORTH),
+ GPIO_PAD_CONF("N67: HV_DDI2_DDC_SCL", NATIVE, M3, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 53, NA, 0x5438, NORTH),
+ GPIO_PAD_CONF("N62: HV_DDI2_DDC_SDA", NATIVE, M3, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 48, NA, 0x5410, NORTH),
+ GPIO_PAD_CONF("N68: HV_DDI2_HPD", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+ NA, 54, NA, 0x5440, NORTH),
+ GPIO_PAD_CONF("N65: PANEL0_BKLTCTL", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 51, NA, 0x5428, NORTH),
+ GPIO_PAD_CONF("N60: PANEL0_BKLTEN", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 46, NA, 0x5400, NORTH),
+ GPIO_PAD_CONF("N72: PANEL0_VDDEN", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 58, NA, 0x5460, NORTH),
+ GPIO_PAD_CONF("N63: PANEL1_BKLTCTL", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 49, NA, 0x5418, NORTH),
+ GPIO_PAD_CONF("N70: PANEL1_BKLTEN", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 56, NA, 0x5450, NORTH),
+ GPIO_PAD_CONF("N69: PANEL1_VDDEN", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 55, NA, 0x5448, NORTH),
+ GPIO_PAD_CONF("N32: PROCHOT_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 24, NA, 0x4c10, NORTH),
+ GPIO_PAD_CONF("N16: SEC_GPIO_SUS10", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 10, NA, 0x4808, NORTH),
+ GPIO_PAD_CONF("N21: SEC_GPIO_SUS11", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 15, NA, 0x4830, NORTH),
+ GPIO_PAD_CONF("N23: SEC_GPIO_SUS8", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 17, NA, 0x4840, NORTH),
+ GPIO_PAD_CONF("N27: SEC_GPIO_SUS9", GPIO, M1, GPI, LOW, NA,
+ TRIG_LEVEL, L15, NA, NA, NA, NON_MASKABLE,
+ EN_RX_DATA, INV_RX_DATA,
+ NA, 21, SCI, 0x4860, NORTH),
+ GPIO_PAD_CONF("N31: TCK", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 23, NA, 0x4c08, NORTH),
+ GPIO_PAD_CONF("N41: TDI", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 33, NA, 0x4c58, NORTH),
+ GPIO_PAD_CONF("N39: TDO", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 31, NA, 0x4c48, NORTH),
+ GPIO_PAD_CONF("N36: TDO_2", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 28, NA, 0x4c30, NORTH),
+ GPIO_PAD_CONF("N34: TMS", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 26, NA, 0x4c20, NORTH),
+ GPIO_PAD_CONF("N30: TRST_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 22, NA, 0x4c00, NORTH),
+
+ GPIO_PAD_CONF("E21: MF_ISH_GPIO_0", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 18, NA, 0x4830, EAST),
+ GPIO_PAD_CONF("E18: MF_ISH_GPIO_1", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 15, NA, 0x4818, EAST),
+ GPIO_PAD_CONF("E24: MF_ISH_GPIO_2", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 21, NA, 0x4848, EAST),
+ GPIO_PAD_CONF("E15: MF_ISH_GPIO_3", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 12, NA, 0x4800, EAST),
+ GPIO_PAD_CONF("E22: MF_ISH_GPIO_4", GPIO, M1, GPI, NA, NA,
+ NA, L0, NA, NA, NA, NON_MASKABLE, NA, NO_INVERSION,
+ NA, 19, NA, 0x4838, EAST),
+ GPIO_PAD_CONF("E19: MF_ISH_GPIO_5", GPIO, M1, GPO, HIGH, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 16, NA, 0x4820, EAST),
+ GPIO_PAD_CONF("E25: MF_ISH_GPIO_6", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 22, NA, 0x4850, EAST),
+ GPIO_PAD_CONF("E16: MF_ISH_GPIO_7", GPIO, M1, GPO, HIGH, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 13, NA, 0x4808, EAST),
+ GPIO_PAD_CONF("E23: MF_ISH_GPIO_8", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 20, NA, 0x4840, EAST),
+ GPIO_PAD_CONF("E20: MF_ISH_GPIO_9", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 17, NA, 0x4828, EAST),
+ GPIO_PAD_CONF("E26: MF_ISH_I2C1_SDA", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 23, NA, 0x4858, EAST),
+ GPIO_PAD_CONF("E17: MF_ISH_I2C1_SCL", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 14, NA, 0x4810, EAST),
+ GPIO_PAD_CONF("E04: PMU_AC_PRESENT", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 4, NA, 0x4420, EAST),
+ GPIO_PAD_CONF("E01: PMU_BATLOW_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 1, NA, 0x4408, EAST),
+ GPIO_PAD_CONF("E05: PMU_PLTRST_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 5, NA, 0x4428, EAST),
+ GPIO_PAD_CONF("E07: PMU_SLP_LAN_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 7, NA, 0x4438, EAST),
+ GPIO_PAD_CONF("E03: PMU_SLP_S0IX_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 3, NA, 0x4418, EAST),
+ GPIO_PAD_CONF("E00: PMU_SLP_S3_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 0, NA, 0x4400, EAST),
+ GPIO_PAD_CONF("E09: PMU_SLP_S4_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 9, NA, 0x4448, EAST),
+ GPIO_PAD_CONF("E06: PMU_SUSCLK", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 6, NA, 0x4430, EAST),
+ GPIO_PAD_CONF("E10: PMU_WAKE_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 10, NA, 0x4450, EAST),
+ GPIO_PAD_CONF("E11: PMU_WAKE_LAN_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 11, NA, 0x4458, EAST),
+ GPIO_PAD_CONF("E02: SUS_STAT_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 2, NA, 0x4410, EAST),
+
+ GPIO_PAD_CONF("SE16: SDMMC1_CLK", NATIVE, M1, NA, NA, HIGH,
+ NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,
+ NA, 9, NA, 0x4808, SOUTHEAST),
+ GPIO_PAD_CONF("SE23: SDMMC1_CMD", NATIVE, M1, NA, NA, HIGH,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 16, NA, 0x4840, SOUTHEAST),
+ GPIO_PAD_CONF("SE17: SDMMC1_D0", NATIVE, M1, NA, NA, HIGH,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 10, NA, 0x4810, SOUTHEAST),
+ GPIO_PAD_CONF("SE24: SDMMC1_D1", NATIVE, M1, NA, NA, HIGH,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 17, NA, 0x4848, SOUTHEAST),
+ GPIO_PAD_CONF("SE20: SDMMC1_D2", NATIVE, M1, NA, NA, HIGH,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 13, NA, 0x4828, SOUTHEAST),
+ GPIO_PAD_CONF("SE26: SDMMC1_D3_CD_B", NATIVE, M1, NA, NA, HIGH,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 19, NA, 0x4858, SOUTHEAST),
+ GPIO_PAD_CONF("SE67: MMC1_D4_SD_WE", NATIVE, M1, NA, NA, HIGH,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 41, NA, 0x5438, SOUTHEAST),
+ GPIO_PAD_CONF("SE65: MMC1_D5", NATIVE, M1, NA, NA, HIGH,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 39, NA, 0x5428, SOUTHEAST),
+ GPIO_PAD_CONF("SE63: MMC1_D6", NATIVE, M1, NA, NA, HIGH,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 37, NA, 0x5418, SOUTHEAST),
+ GPIO_PAD_CONF("SE68: MMC1_D7", NATIVE, M1, NA, NA, HIGH,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 42, NA, 0x5440, SOUTHEAST),
+ GPIO_PAD_CONF("SE69: MMC1_RCLK", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 43, NA, 0x5448, SOUTHEAST),
+ GPIO_PAD_CONF("SE77: GPIO_ALERT", GPIO, M1, GPI, NA, NA,
+ TRIG_LEVEL, L2, NA, NA, NA, NON_MASKABLE,
+ EN_RX_DATA, INV_RX_DATA,
+ NA, 46, NA, 0x5810, SOUTHEAST),
+ GPIO_PAD_CONF("SE79: ILB_SERIRQ", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 48, NA, 0x5820, SOUTHEAST),
+ GPIO_PAD_CONF("SE51: MF_LPC_CLKOUT0", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
+ NA, 32, NA, 0x5030, SOUTHEAST),
+ GPIO_PAD_CONF("SE49: MF_LPC_CLKOUT1", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 30, NA, 0x5020, SOUTHEAST),
+ GPIO_PAD_CONF("SE47: MF_LPC_AD0", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 28, NA, 0x5010, SOUTHEAST),
+ GPIO_PAD_CONF("SE52: MF_LPC_AD1", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 33, NA, 0x5038, SOUTHEAST),
+ GPIO_PAD_CONF("SE45: MF_LPC_AD2", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 26, NA, 0x5000, SOUTHEAST),
+ GPIO_PAD_CONF("SE50: MF_LPC_AD3", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 31, NA, 0x5028, SOUTHEAST),
+ GPIO_PAD_CONF("SE46: LPC_CLKRUNB", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 27, NA, 0x5008, SOUTHEAST),
+ GPIO_PAD_CONF("SE48: LPC_FRAMEB", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 29, NA, 0x5018, SOUTHEAST),
+ GPIO_PAD_CONF("SE00: MF_PLT_CLK0", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 0, NA, 0x4400, SOUTHEAST),
+ GPIO_PAD_CONF("SE02: MF_PLT_CLK1", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 1, NA, 0x4410, SOUTHEAST),
+ GPIO_PAD_CONF("SE07: MF_PLT_CLK2", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 7, NA, 0x4438, SOUTHEAST),
+ GPIO_PAD_CONF("SE04: MF_PLT_CLK3", GPIO, M1, GPI, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 4, NA, 0x4420, SOUTHEAST),
+ GPIO_PAD_CONF("SE03: MF_PLT_CLK4", GPIO, M1, GPO, LOW, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 3, NA, 0x4418, SOUTHEAST),
+ GPIO_PAD_CONF("SE06: MF_PLT_CLK5", GPIO, M3, GPO, LOW, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 6, NA, 0x4430, SOUTHEAST),
+ GPIO_PAD_CONF("SE83: SUSPWRDNACK", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 52, NA, 0x5840, SOUTHEAST),
+ GPIO_PAD_CONF("SE05: PWM0", GPIO, M1, GPO, LOW, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 5, NA, 0x4428, SOUTHEAST),
+ GPIO_PAD_CONF("SE01: PWM1", GPIO, M1, GPO, HIGH, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 1, NA, 0x4408, SOUTHEAST),
+ GPIO_PAD_CONF("SE85: SDMMC3_1P8_EN", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 54, NA, 0x5850, SOUTHEAST),
+ GPIO_PAD_CONF("SE81: SDMMC3_CD_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 50, NA, 0x5830, SOUTHEAST),
+ GPIO_PAD_CONF("SE31: SDMMC3_CLK", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 21, NA, 0x4c08, SOUTHEAST),
+ GPIO_PAD_CONF("SE34: SDMMC3_CMD", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 24, NA, 0x4c20, SOUTHEAST),
+ GPIO_PAD_CONF("SE35: SDMMC3_D0", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 25, NA, 0x4c28, SOUTHEAST),
+ GPIO_PAD_CONF("SE30: SDMMC3_D1", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 20, NA, 0x4c00, SOUTHEAST),
+ GPIO_PAD_CONF("SE33: SDMMC3_D2", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 23, NA, 0x4c18, SOUTHEAST),
+ GPIO_PAD_CONF("SE32: SDMMC3_D3", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 22, NA, 0x4c10, SOUTHEAST),
+ GPIO_PAD_CONF("SE78: SDMMC3_PWR_EN_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,
+ NA, 47, NA, 0x5818, SOUTHEAST),
+ GPIO_PAD_CONF("SE19: SDMMC2_CLK", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 12, NA, 0x4820, SOUTHEAST),
+ GPIO_PAD_CONF("SE22: SDMMC2_CMD", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 15, NA, 0x4838, SOUTHEAST),
+ GPIO_PAD_CONF("SE25: SDMMC2_D0", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 18, NA, 0x4850, SOUTHEAST),
+ GPIO_PAD_CONF("SE18: SDMMC2_D1", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 11, NA, 0x4818, SOUTHEAST),
+ GPIO_PAD_CONF("SE21: SDMMC2_D2", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 14, NA, 0x4830, SOUTHEAST),
+ GPIO_PAD_CONF("SE15: SDMMC2_D3_CD_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 8, NA, 0x4800, SOUTHEAST),
+ GPIO_PAD_CONF("SE62: SPI1_CLK", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 36, NA, 0x5410, SOUTHEAST),
+ GPIO_PAD_CONF("SE61: SPI1_CS0_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 35, NA, 0x5408, SOUTHEAST),
+ GPIO_PAD_CONF("SE66: SPI1_CS1_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 40, NA, 0x5430, SOUTHEAST),
+ GPIO_PAD_CONF("SE60: SPI1_MISO", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 34, NA, 0x5400, SOUTHEAST),
+ GPIO_PAD_CONF("SE64: SPI1_MOSI", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 38, NA, 0x5420, SOUTHEAST),
+ GPIO_PAD_CONF("SE80: USB_OC0_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 49, NA, 0x5828, SOUTHEAST),
+ GPIO_PAD_CONF("SE75: USB_OC1_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 44, NA, 0x5800, SOUTHEAST),
+ GPIO_PAD_CONF("SW02: FST_SPI_CLK", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 2, NA, 0x4410, SOUTHWEST),
+ GPIO_PAD_CONF("SW06: FST_SPI_CS0_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 6, NA, 0x4430, SOUTHWEST),
+ GPIO_PAD_CONF("SW04: FST_SPI_CS1_B", GPIO, M1, GPO, HIGH, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 4, NA, 0x4420, SOUTHWEST),
+ GPIO_PAD_CONF("SW07: FST_SPI_CS2_B", GPIO, M1, GPO, LOW, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 7, NA, 0x4438, SOUTHWEST),
+ GPIO_PAD_CONF("SW01: FST_SPI_D0", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 1, NA, 0x4408, SOUTHWEST),
+ GPIO_PAD_CONF("SW05: FST_SPI_D1", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 5, NA, 0x4428, SOUTHWEST),
+ GPIO_PAD_CONF("SW00: FST_SPI_D2", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 0, NA, 0x4400, SOUTHWEST),
+ GPIO_PAD_CONF("SW03: FST_SPI_D3", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 3, NA, 0x4418, SOUTHWEST),
+ GPIO_PAD_CONF("SW30: MF_HDA_CLK", NATIVE, M2, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 16, NA, 0x4c00, SOUTHWEST),
+ GPIO_PAD_CONF("SW37: MF_HDA_DOCKENB", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 23, NA, 0x4c38, SOUTHWEST),
+ GPIO_PAD_CONF("SW34: MF_HDA_DOCKRSTB", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 20, NA, 0x4c20, SOUTHWEST),
+ GPIO_PAD_CONF("SW31: MF_HDA_RSTB", NATIVE, M2, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 17, NA, 0x4c08, SOUTHWEST),
+ GPIO_PAD_CONF("SW32: MF_HDA_SDI0", NATIVE, M2, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 18, NA, 0x4c10, SOUTHWEST),
+ GPIO_PAD_CONF("SW36: MF_HDA_SDI1", NATIVE, M2, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 22, NA, 0x4c30, SOUTHWEST),
+ GPIO_PAD_CONF("SW33: MF_HDA_SDO", NATIVE, M2, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 19, NA, 0x4c18, SOUTHWEST),
+ GPIO_PAD_CONF("SW35: MF_HDA_SYNC", NATIVE, M2, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 21, NA, 0x4c28, SOUTHWEST),
+ GPIO_PAD_CONF("SW18: UART1_CTS_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 11, NA, 0x4818, SOUTHWEST),
+ GPIO_PAD_CONF("SW15: UART1_RTS_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 8, NA, 0x4800, SOUTHWEST),
+ GPIO_PAD_CONF("SW16: UART1_RXD", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 9, NA, 0x4808, SOUTHWEST),
+ GPIO_PAD_CONF("SW20: UART1_TXD", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 13, NA, 0x4828, SOUTHWEST),
+ GPIO_PAD_CONF("SW22: UART2_CTS_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
+ NA, 15, NA, 0x4838, SOUTHWEST),
+ GPIO_PAD_CONF("SW19: UART2_RTS_B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 12, NA, 0x4820, SOUTHWEST),
+ GPIO_PAD_CONF("SW17: UART2_RXD", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
+ NA, 10, NA, 0x4810, SOUTHWEST),
+ GPIO_PAD_CONF("SW21: UART2_TXD", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 14, NA, 0x4830, SOUTHWEST),
+ GPIO_PAD_CONF("SW50: I2C4_SCL", NATIVE, M3, NA, NA, NA,
+ NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 29, NA, 0x5028, SOUTHWEST),
+ GPIO_PAD_CONF("SW46: I2C4_SDA", NATIVE, M3, NA, NA, NA,
+ NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 25, NA, 0x5008, SOUTHWEST),
+ GPIO_PAD_CONF("SW49: I2C_NFC_SDA", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,
+ NA, 28, NA, 0x5020, SOUTHWEST),
+ GPIO_PAD_CONF("SW52: I2C_NFC_SCL", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,
+ NA, 31, NA, 0x5038, SOUTHWEST),
+ GPIO_PAD_CONF("SW77: GP_SSP_2_CLK", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 50, NA, 0x5c10, SOUTHWEST),
+ GPIO_PAD_CONF("SW81: GP_SSP_2_FS", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 54, NA, 0x5c30, SOUTHWEST),
+ GPIO_PAD_CONF("SW79: GP_SSP_2_RXD", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 52, NA, 0x5c20, SOUTHWEST),
+ GPIO_PAD_CONF("SW82: GP_SSP_2_TXD", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+ NA, 55, NA, 0x5C38, SOUTHWEST),
+ GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 48, NA, 0x5c00, SOUTHWEST),
+ GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 49, NA, 0x5c08, SOUTHWEST),
+ GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 51, NA, 0x5c18, SOUTHWEST),
+ GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 53, NA, 0x5c28, SOUTHWEST),
+ GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 40, NA, 0x5800, SOUTHWEST),
+ GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 41, NA, 0x5808, SOUTHWEST),
+ GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,
+ NA, 43, NA, 0x5818, SOUTHWEST),
+ GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 45, NA, 0x5828, SOUTHWEST),
+ GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,
+ NA, 42, NA, 0x5810, SOUTHWEST),
+ GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA,
+ NA, NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 44, NA, 0x5820, SOUTHWEST),
+ GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 46, NA, 0x5830, SOUTHWEST),
+ GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+ NA, 47, NA, 0x5838, SOUTHWEST),
+ GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, 48, NA, 0x5c00, SOUTHWEST),
+ GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, 49, NA, 0x5c08, SOUTHWEST),
+ GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, 51, NA, 0x5c18, SOUTHWEST),
+ GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, 53, NA, 0x5c28, SOUTHWEST),
+ GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA,
+ NA, 40, NA, 0x5800, SOUTHWEST),
+ GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA,
+ NA, 41, NA, 0x5808, SOUTHWEST),
+ GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, ENABLE, NA, NA, NA, NA,
+ NA, 43, NA, 0x5818, SOUTHWEST),
+ GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA,
+ NA, NA, NA, NA, NA, NA, NA, NA,
+ NA, 45, NA, 0x5828, SOUTHWEST),
+ GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, ENABLE, NA, NA, NA, NA,
+ NA, 42, NA, 0x5810, SOUTHWEST),
+ GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA,
+ NA, NA, NA, P_20K_H, NA, NA, NA, NA, NA,
+ NA, 44, NA, 0x5820, SOUTHWEST),
+ GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NA,
+ NA, 46, NA, 0x5830, SOUTHWEST),
+ GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA,
+ NA, NA, P_20K_H, NA, NA, NA, NA, NA,
+ NA, 47, NA, 0x5838, SOUTHWEST),
+
+ /* end of the table */
+ GPIO_PAD_CONF("GPIO PAD TABLE END", NATIVE, M1, NA, NA, NA,
+ NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+ NA, 0, NA, 0, TERMINATOR),
+};
+
+void update_fsp_gpio_configs(const struct gpio_family **family,
+ const struct gpio_pad **pad)
+{
+ *family = gpio_family;
+ *pad = gpio_pad;
+}
--- /dev/null
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+ jmp early_board_init_ret
udelay(100);
mmdc_do_write_level_calibration(&novena_ddr_info);
mmdc_do_dqs_calibration(&novena_ddr_info);
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
}
/* DDR initialization */
spl_dram_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
}
#endif
config SYS_CONFIG_NAME
default "am3517_evm"
+source "board/ti/common/Kconfig"
+
endif
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
#include "omap3logic.h"
+#ifdef CONFIG_USB_EHCI_HCD
+#include <usb.h>
+#include <asm/ehci-omap.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
};
#endif
+#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
+/* Call usb_stop() before starting the kernel */
+void show_boot_progress(int val)
+{
+ if (val == BOOTSTAGE_ID_RUN_OS)
+ usb_stop();
+}
+
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
+};
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(int index)
+{
+ return omap_ehci_hcd_stop();
+}
+
+#endif /* CONFIG_USB_EHCI_HCD */
+
/*
* Routine: misc_init_r
CONFIG_SANDBOX_BIG_ENDIAN should be defined when running on big-endian
machines.
+By default sandbox builds and runs on 64-bit hosts. If you are going to build
+and run sandbox on a 32-bit host, select CONFIG_SANDBOX_32BIT.
+
Note that standalone/API support is not available at present.
make sandbox_defconfig all NO_SDL=1
./u-boot
- If you are building on a 32-bit machine you may get errors from __ffs.h
- about shifting more than the machine word size. Edit the config file
- include/configs/sandbox.h and change CONFIG_SANDBOX_BITS_PER_LONG to 32.
-
U-Boot will start on your computer, showing a sandbox emulation of the serial
console:
$> sudo mkfs.vfat -n EFI -v ${lodev}p1
$> sudo mkfs.ext4 -L ROOT -v ${lodev}p2
+or utilize the device described in test/py/make_test_disk.py:
+
+ #!/usr/bin/python
+ import make_test_disk
+ make_test_disk.makeDisk()
Writing Sandbox Drivers
-----------------------
* Machine selection -
* Machine val1, val2
* -------------------------
+ * HB2 x x
* HB rev 3.x x 0
* CBi 0 1
* HB 1 1
return true;
}
+static bool is_hummingboard2(void)
+{
+ int val1;
+
+ SETUP_IOMUX_PADS(hb_cbi_sense);
+
+ gpio_direction_input(IMX_GPIO_NR(2, 8));
+
+ val1 = gpio_get_value(IMX_GPIO_NR(2, 8));
+
+ /*
+ * Machine selection -
+ * Machine val1
+ * -------------------
+ * HB2 0
+ * HB rev 3.x x
+ * CBi x
+ * HB x
+ */
+
+ if (val1 == 0)
+ return true;
+ else
+ return false;
+}
+
int checkboard(void)
{
- if (is_hummingboard())
+ if (is_hummingboard2())
+ puts("Board: MX6 Hummingboard2\n");
+ else if (is_hummingboard())
puts("Board: MX6 Hummingboard\n");
else
puts("Board: MX6 Cubox-i\n");
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- if (is_hummingboard())
+ if (is_hummingboard2())
+ env_set("board_name", "HUMMINGBOARD2");
+ else if (is_hummingboard())
env_set("board_name", "HUMMINGBOARD");
else
env_set("board_name", "CUBOXI");
Put pico board into normal boot mode.
Power up the board and the new updated U-Boot should boot from eMMC.
+
+Building U-Boot to boot with NXP 4.1 kernel:
+
+The NXP 4.1 kernel boots only in secure boot mode on mx7.
+
+Follow the next steps to enable secure boot:
+
+$ make mrproper
+$ make pico-imx7d_defconfig
+$ make menuconfig
+ -> ARM architecture
+ -> [*] Enable support for booting in non-secure mode
+ -> [*] Boot in secure mode by default
+ -> Exit
+$ make
+
+Flash u-boot.imx using the imx_usb_loader tool.
(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
- return set_clk_enet(ENET_125MHz);
+ return set_clk_enet(ENET_125MHZ);
}
int board_phy_config(struct phy_device *phydev)
> make CROSS_COMPILE=aarch64-unknown-elf- ARCH=arm u-boot.itb
-Write to a SD-card
-==================
+Flash the image
+===============
+
+Copy the SPL to offset 32k and the FIT image containing the payloads
+(U-Boot proper, ATF, devicetree) to offset 256k card.
+
+SD-Card
+-------
> dd if=spl-3368.img of=/dev/sdb seek=64
> dd if=u-boot.itb of=/dev/sdb seek=512
+eMMC
+----
+
+rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with
+help of the Rockchip loader binary.
+
+ > git clone https://github.com/rockchip-linux/rkdeveloptool
+ > cd rkdeveloptool
+ > autoreconf -i && && ./configure && make
+ > git clone https://github.com/rockchip-linux/rkbin.git
+ > ./rkdeveloptool db rkbin/rk33/rk3368_loader_v2.00.256.bin
+ > ./rkdeveloptool wl 64 ../spl.img
+ > ./rkdeveloptool wl 512 ../u-boot.itb
+
If everything went according to plan, you should see the following
output on UART0:
Package the image
=================
- > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin spl.img
- > make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb
+Creating a SPL image for SD-Card/eMMC
+ > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin spl_mmc.img
+Creating a SPL image for SPI-NOR
+ > tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin spl_nor.img
+Create the FIT image containing U-Boot proper, ATF, M0 Firmware, devicetree
+ > make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb
Flash the image
===============
-Copy the SPL to offset 32k and the FIT image containing the payloads
-(U-Boot proper, ATF, M0 Firmware, devicetree) to offset 256k on a SD
-card.
+Copy the SPL to offset 32k for SD/eMMC, offset 0 for NOR-Flash and the FIT
+image to offset 256k card.
- > dd if=spl.img of=/dev/sdb seek=64
+SD-Card
+-------
+
+ > dd if=spl_mmc.img of=/dev/sdb seek=64
> dd if=u-boot.itb of=/dev/sdb seek=512
-After powering up the board (with the inserted SD card), you should see
-a U-Boot console on UART0 (115200n8).
+eMMC
+----
+
+rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with
+help of the Rockchip loader binary.
+
+ > git clone https://github.com/rockchip-linux/rkdeveloptool
+ > cd rkdeveloptool
+ > autoreconf -i && ./configure && make
+ > git clone https://github.com/rockchip-linux/rkbin.git
+ > ./rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
+ > ./rkdeveloptool wl 64 ../spl_mmc.img
+ > ./rkdeveloptool wl 512 ../u-boot.itb
+
+NOR-Flash
+---------
+
+Writing the SPI NOR Flash requires a running U-Boot. For the sake of simplicity
+we assume you have a SD-Card with a partition containing the required files
+ready.
+
+ > load mmc 1:1 ${kernel_addr_r} spl_nor.img
+ > sf probe
+ > sf erase 0 +$filesize
+ > sf write $kernel_addr_r 0 ${filesize}
+ > load mmc 1:1 ${kernel_addr_r} u-boot.itb
+ > sf erase 0x40000 +$filesize
+ > sf write $kernel_addr_r 0x40000 ${filesize}
+
+
+Reboot the system and you should see a U-Boot console on UART0 (115200n8).
u8 low[cpuid_length/2], high[cpuid_length/2];
char cpuid_str[cpuid_length * 2 + 1];
u64 serialno;
- char serialno_str[16];
+ char serialno_str[17];
/* retrieve the device */
ret = uclass_get_device_by_driver(UCLASS_MISC,
0x0
};
+static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
+ .sdram_config_init = 0x61863332,
+ .sdram_config = 0x61863332,
+ .sdram_config2 = 0x08000000,
+ .ref_ctrl = 0x0000514d,
+ .ref_ctrl_final = 0x0000144a,
+ .sdram_tim1 = 0xd333887c,
+ .sdram_tim2 = 0x40b37fe3,
+ .sdram_tim3 = 0x409f8ada,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x5007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400f,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400f,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
switch (emif_nr) {
case 1:
- *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
+ if (board_is_am571x_idk())
+ *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
+ else
+ *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
break;
case 2:
*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
void hw_data_init(void)
{
*prcm = &dra7xx_prcm;
- *dplls_data = &dra7xx_dplls;
+ if (is_dra72x())
+ *dplls_data = &dra72x_dplls;
+ else
+ *dplls_data = &dra7xx_dplls;
*ctrl = &dra7xx_ctrl;
}
if (board_is_x15_revb1()) {
if (!strcmp(name, "am57xx-beagle-x15-revb1"))
return 0;
+ } else if (board_is_x15_revc()) {
+ if (!strcmp(name, "am57xx-beagle-x15-revc"))
+ return 0;
} else if (!strcmp(name, "am57xx-beagle-x15")) {
return 0;
}
#include "mux_data.h"
#include "../common/board_detect.h"
+#define board_is_dra76x_evm() board_ti_is("DRA76/7x")
#define board_is_dra74x_evm() board_ti_is("5777xCPU")
#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
#define board_is_dra71x_evm() board_ti_is("DRA79x,D")
.emif_rd_wr_exec_thresh = 0x00000305
};
+const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
+ .sdram_config_init = 0x61862B32,
+ .sdram_config = 0x61862B32,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x0000514C,
+ .ref_ctrl_final = 0x0000144A,
+ .sdram_tim1 = 0xD113783C,
+ .sdram_tim2 = 0x30B47FE3,
+ .sdram_tim3 = 0x409F8AD8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x5007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0824400D,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400D,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
+ .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
+ .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
+ .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
+const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
+ .sdram_config_init = 0x61862B32,
+ .sdram_config = 0x61862B32,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x0000514C,
+ .ref_ctrl_final = 0x0000144A,
+ .sdram_tim1 = 0xD113781C,
+ .sdram_tim2 = 0x30B47FE3,
+ .sdram_tim3 = 0x409F8AD8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x5007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0824400D,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400D,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
+ .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
+ .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
+ .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
u64 ram_size;
break;
}
break;
+ case DRA762_ES1_0:
+ if (emif_nr == 1)
+ *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
+ else
+ *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
+ break;
case DRA722_ES1_0:
case DRA722_ES2_0:
+ case DRA722_ES2_1:
if (ram_size < CONFIG_MAX_MEM_MAPPED)
*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
else
ram_size = board_ti_get_emif_size();
switch (omap_revision()) {
+ case DRA762_ES1_0:
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
break;
case DRA722_ES1_0:
case DRA722_ES2_0:
+ case DRA722_ES2_1:
default:
if (ram_size < CONFIG_MAX_MEM_MAPPED)
*dmm_lisa_regs = &lisa_map_2G_x_2;
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
+struct vcores_data dra76x_volts = {
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = LP87565_REG_ADDR_BUCK01,
+ .mpu.pmic = &lp87565,
+ .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
+ .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
+ .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS65917_REG_ADDR_SMPS1,
+ .eve.pmic = &tps659038,
+ .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
+ .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
+ .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = LP87565_REG_ADDR_BUCK23,
+ .gpu.pmic = &lp87565,
+ .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS65917_REG_ADDR_SMPS3,
+ .core.pmic = &tps659038,
+
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
+ .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
+ .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS65917_REG_ADDR_SMPS4,
+ .iva.pmic = &tps659038,
+ .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
struct vcores_data dra722_volts = {
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
name = "dra71x";
else
name = "dra72x";
+ } else if (is_dra76x()) {
+ name = "dra76x";
} else {
name = "dra7xx";
}
bname = "DRA72x EVM";
} else if (board_is_dra71x_evm()) {
bname = "DRA71x EVM";
+ } else if (board_is_dra76x_evm()) {
+ bname = "DRA76x EVM";
} else {
/* If EEPROM is not populated */
if (is_dra72x())
*omap_vcores = &dra722_volts;
} else if (board_is_dra71x_evm()) {
*omap_vcores = &dra718_volts;
+ } else if (board_is_dra76x_evm()) {
+ *omap_vcores = &dra76x_volts;
} else {
/* If EEPROM is not populated */
if (is_dra72x())
switch (omap_revision()) {
case DRA722_ES1_0:
case DRA722_ES2_0:
+ case DRA722_ES2_1:
pads = dra72x_core_padconf_array_common;
npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
if (board_is_dra71x_evm()) {
iodelay = dra742_es1_1_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
break;
+ case DRA762_ES1_0:
+ pads = dra76x_core_padconf_array;
+ npads = ARRAY_SIZE(dra76x_core_padconf_array);
+ iodelay = dra76x_es1_0_iodelay_cfg_array;
+ niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
+ break;
default:
case DRA752_ES2_0:
pads = dra74x_core_padconf_array;
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
+
+void board_mmc_poweron_ldo(uint voltage)
+{
+ if (board_is_dra71x_evm()) {
+ if (voltage == LDO_VOLT_3V0)
+ voltage = 0x19;
+ else if (voltage == LDO_VOLT_1V8)
+ voltage = 0xa;
+ lp873x_mmc1_poweron_ldo(voltage);
+ } else if (board_is_dra76x_evm()) {
+ palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
+ } else {
+ palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
+ }
+}
#endif
#ifdef CONFIG_USB_DWC3
if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
return;
- /* Do not enable VTT for DRA722 */
- if (is_dra72x())
+ /* Do not enable VTT for DRA722 or DRA76x */
+ if (is_dra72x() || is_dra76x())
return;
/*
} else if (!strcmp(name, "dra72-evm")) {
return 0;
}
- } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) {
+ } else if (is_dra76x() && !strcmp(name, "dra76-evm")) {
+ return 0;
+ } else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) {
return 0;
}
{WAKEUP2, (M14)}, /* Wakeup2.gpio1_2 */
};
+const struct pad_conf_entry dra76x_core_padconf_array[] = {
+ {GPMC_AD0, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad0.vout3_d0 */
+ {GPMC_AD1, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad1.vout3_d1 */
+ {GPMC_AD2, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad2.vout3_d2 */
+ {GPMC_AD3, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad3.vout3_d3 */
+ {GPMC_AD4, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad4.vout3_d4 */
+ {GPMC_AD5, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad5.vout3_d5 */
+ {GPMC_AD6, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad6.vout3_d6 */
+ {GPMC_AD7, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad7.vout3_d7 */
+ {GPMC_AD8, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad8.vout3_d8 */
+ {GPMC_AD9, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad9.vout3_d9 */
+ {GPMC_AD10, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad10.vout3_d10 */
+ {GPMC_AD11, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad11.vout3_d11 */
+ {GPMC_AD12, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad12.vout3_d12 */
+ {GPMC_AD13, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad13.vout3_d13 */
+ {GPMC_AD14, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad14.vout3_d14 */
+ {GPMC_AD15, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad15.vout3_d15 */
+ {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vout3_d16 */
+ {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vout3_d17 */
+ {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vout3_d18 */
+ {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vout3_d19 */
+ {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vout3_d20 */
+ {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vout3_d21 */
+ {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vout3_d22 */
+ {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vout3_d23 */
+ {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vout3_hsync */
+ {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vout3_vsync */
+ {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vout3_de */
+ {GPMC_A11, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a11.gpio2_1 */
+ {GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */
+ {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
+ {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
+ {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
+ {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
+ {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
+ {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
+ {GPMC_A19, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a19.mmc2_dat4 */
+ {GPMC_A20, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a20.mmc2_dat5 */
+ {GPMC_A21, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a21.mmc2_dat6 */
+ {GPMC_A22, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a22.mmc2_dat7 */
+ {GPMC_A23, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a23.mmc2_clk */
+ {GPMC_A24, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a24.mmc2_dat0 */
+ {GPMC_A25, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a25.mmc2_dat1 */
+ {GPMC_A26, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a26.mmc2_dat2 */
+ {GPMC_A27, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a27.mmc2_dat3 */
+ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
+ {GPMC_CS0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_cs0.gpmc_cs0 */
+ {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
+ {GPMC_CS3, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs3.vout3_clk */
+ {GPMC_ADVN_ALE, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpmc_advn_ale */
+ {GPMC_OEN_REN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpmc_oen_ren */
+ {GPMC_WEN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpmc_wen */
+ {GPMC_BEN0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_ben0.gpmc_ben0 */
+ {GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpmc_wait0 */
+ {VIN1A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin1a_fld0.gpio3_1 */
+ {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_clk0.vin2a_clk0 */
+ {VIN2A_DE0, (M15 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_de0.Driveroff */
+ {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */
+ {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_hsync0.vin2a_hsync0 */
+ {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_vsync0.vin2a_vsync0 */
+ {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d0.vin2a_d0 */
+ {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d1.vin2a_d1 */
+ {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d2.vin2a_d2 */
+ {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d3.vin2a_d3 */
+ {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d4.vin2a_d4 */
+ {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.vin2a_d5 */
+ {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d6.vin2a_d6 */
+ {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d7.vin2a_d7 */
+ {VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d8.vin2a_d8 */
+ {VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d9.vin2a_d9 */
+ {VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d10.vin2a_d10 */
+ {VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d11.vin2a_d11 */
+ {VIN2A_D12, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
+ {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_de.vout1_de */
+ {VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)}, /* vout1_fld.gpio4_21 */
+ {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
+ {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
+ {RGMII0_TXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
+ {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
+ {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
+ {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
+ {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
+ {MCASP1_ACLKX, (M14 | 0x00070000)}, /* mcasp1_aclkx.gpio7_31 */
+ {MCASP1_FSX, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.gpio7_30 */
+ {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
+ {MCASP1_AXR1, (M10 | 0x000f0000)}, /* mcasp1_axr1.i2c5_scl */
+ {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
+ {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
+ {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
+ {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
+ {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
+ {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
+ {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
+ {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
+ {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
+ {MCASP2_ACLKR, (M15 | PIN_INPUT_PULLUP)}, /* mcasp2_aclkr.Driveroff */
+ {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
+ {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
+ {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
+ {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.mmc1_sdcd */
+ {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
+ {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
+ {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
+ {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
+ {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
+ {SPI1_CS2, (M6 | 0x000f0000)}, /* spi1_cs2.hdmi1_hpd */
+ {SPI1_CS3, (M6 | 0x000f0000)}, /* spi1_cs3.hdmi1_cec */
+ {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
+ {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
+ {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
+ {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
+ {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
+ {DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */
+ {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
+ {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
+ {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
+ {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
+ {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */
+ {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
+ {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
+ {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
+ {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
+ {WAKEUP0, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_0 */
+ {WAKEUP1, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_1 */
+ {WAKEUP2, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq2 */
+ {WAKEUP3, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq1 */
+};
+
#ifdef CONFIG_IODELAY_RECALIBRATION
const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = {
{0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
{0x0188, 590, 0}, /* CFG_GPMC_A18_OUT */
{0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
};
+
+const struct iodelay_cfg_entry dra76x_es1_0_iodelay_cfg_array[] = {
+ {0x011C, 787, 0}, /* CFG_GPMC_A0_OUT */
+ {0x0128, 1181, 0}, /* CFG_GPMC_A10_OUT */
+ {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
+ {0x0150, 2149, 1052}, /* CFG_GPMC_A14_IN */
+ {0x015C, 2121, 997}, /* CFG_GPMC_A15_IN */
+ {0x0168, 2159, 1134}, /* CFG_GPMC_A16_IN */
+ {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
+ {0x0174, 2135, 1085}, /* CFG_GPMC_A17_IN */
+ {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
+ {0x01A0, 592, 0}, /* CFG_GPMC_A1_OUT */
+ {0x020C, 641, 0}, /* CFG_GPMC_A2_OUT */
+ {0x0218, 1481, 0}, /* CFG_GPMC_A3_OUT */
+ {0x0224, 1775, 0}, /* CFG_GPMC_A4_OUT */
+ {0x0230, 785, 0}, /* CFG_GPMC_A5_OUT */
+ {0x023C, 848, 0}, /* CFG_GPMC_A6_OUT */
+ {0x0248, 851, 0}, /* CFG_GPMC_A7_OUT */
+ {0x0254, 1783, 0}, /* CFG_GPMC_A8_OUT */
+ {0x0260, 951, 0}, /* CFG_GPMC_A9_OUT */
+ {0x026C, 1091, 0}, /* CFG_GPMC_AD0_OUT */
+ {0x0278, 1027, 0}, /* CFG_GPMC_AD10_OUT */
+ {0x0284, 824, 0}, /* CFG_GPMC_AD11_OUT */
+ {0x0290, 1196, 0}, /* CFG_GPMC_AD12_OUT */
+ {0x029C, 754, 0}, /* CFG_GPMC_AD13_OUT */
+ {0x02A8, 665, 0}, /* CFG_GPMC_AD14_OUT */
+ {0x02B4, 1027, 0}, /* CFG_GPMC_AD15_OUT */
+ {0x02C0, 937, 0}, /* CFG_GPMC_AD1_OUT */
+ {0x02CC, 1168, 0}, /* CFG_GPMC_AD2_OUT */
+ {0x02D8, 872, 0}, /* CFG_GPMC_AD3_OUT */
+ {0x02E4, 1092, 0}, /* CFG_GPMC_AD4_OUT */
+ {0x02F0, 576, 0}, /* CFG_GPMC_AD5_OUT */
+ {0x02FC, 1113, 0}, /* CFG_GPMC_AD6_OUT */
+ {0x0308, 943, 0}, /* CFG_GPMC_AD7_OUT */
+ {0x0314, 0, 0}, /* CFG_GPMC_AD8_OUT */
+ {0x0320, 0, 0}, /* CFG_GPMC_AD9_OUT */
+ {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
+ {0x0380, 1801, 948}, /* CFG_GPMC_CS3_OUT */
+ {0x06F0, 451, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 127, 1571}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 165, 1178}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 136, 1302}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 0, 1520}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 28, 1690}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 121, 0}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 60, 0}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 153, 0}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 35, 0}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 172, 0}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A38, 0, 0}, /* CFG_VIN2A_CLK0_IN */
+ {0x0A44, 2180, 0}, /* CFG_VIN2A_D0_IN */
+ {0x0A50, 2297, 110}, /* CFG_VIN2A_D10_IN */
+ {0x0A5C, 1938, 0}, /* CFG_VIN2A_D11_IN */
+ {0x0A70, 147, 0}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 110, 0}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 18, 0}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 82, 0}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 33, 0}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 417, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 156, 843}, /* CFG_VIN2A_D19_IN */
+ {0x0AC8, 2326, 309}, /* CFG_VIN2A_D1_IN */
+ {0x0AD4, 223, 1413}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 169, 1415}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 43, 1150}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 0, 1210}, /* CFG_VIN2A_D23_IN */
+ {0x0B04, 2057, 0}, /* CFG_VIN2A_D2_IN */
+ {0x0B10, 2440, 257}, /* CFG_VIN2A_D3_IN */
+ {0x0B1C, 2142, 0}, /* CFG_VIN2A_D4_IN */
+ {0x0B28, 2455, 252}, /* CFG_VIN2A_D5_IN */
+ {0x0B34, 1883, 0}, /* CFG_VIN2A_D6_IN */
+ {0x0B40, 2229, 0}, /* CFG_VIN2A_D7_IN */
+ {0x0B4C, 2250, 151}, /* CFG_VIN2A_D8_IN */
+ {0x0B58, 2279, 27}, /* CFG_VIN2A_D9_IN */
+ {0x0B7C, 2233, 0}, /* CFG_VIN2A_HSYNC0_IN */
+ {0x0B88, 1936, 0}, /* CFG_VIN2A_VSYNC0_IN */
+ {0x0B9C, 1281, 497}, /* CFG_VOUT1_CLK_OUT */
+ {0x0BA8, 379, 0}, /* CFG_VOUT1_D0_OUT */
+ {0x0BB4, 441, 0}, /* CFG_VOUT1_D10_OUT */
+ {0x0BC0, 461, 0}, /* CFG_VOUT1_D11_OUT */
+ {0x0BCC, 1189, 0}, /* CFG_VOUT1_D12_OUT */
+ {0x0BD8, 312, 0}, /* CFG_VOUT1_D13_OUT */
+ {0x0BE4, 298, 0}, /* CFG_VOUT1_D14_OUT */
+ {0x0BF0, 284, 0}, /* CFG_VOUT1_D15_OUT */
+ {0x0BFC, 152, 0}, /* CFG_VOUT1_D16_OUT */
+ {0x0C08, 216, 0}, /* CFG_VOUT1_D17_OUT */
+ {0x0C14, 408, 0}, /* CFG_VOUT1_D18_OUT */
+ {0x0C20, 519, 0}, /* CFG_VOUT1_D19_OUT */
+ {0x0C2C, 475, 0}, /* CFG_VOUT1_D1_OUT */
+ {0x0C38, 316, 0}, /* CFG_VOUT1_D20_OUT */
+ {0x0C44, 59, 0}, /* CFG_VOUT1_D21_OUT */
+ {0x0C50, 221, 0}, /* CFG_VOUT1_D22_OUT */
+ {0x0C5C, 96, 0}, /* CFG_VOUT1_D23_OUT */
+ {0x0C68, 264, 0}, /* CFG_VOUT1_D2_OUT */
+ {0x0C74, 421, 0}, /* CFG_VOUT1_D3_OUT */
+ {0x0C80, 1257, 0}, /* CFG_VOUT1_D4_OUT */
+ {0x0C8C, 432, 0}, /* CFG_VOUT1_D5_OUT */
+ {0x0C98, 436, 0}, /* CFG_VOUT1_D6_OUT */
+ {0x0CA4, 440, 0}, /* CFG_VOUT1_D7_OUT */
+ {0x0CB0, 81, 100}, /* CFG_VOUT1_D8_OUT */
+ {0x0CBC, 471, 0}, /* CFG_VOUT1_D9_OUT */
+ {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */
+ {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */
+ {0x0CEC, 815, 0}, /* CFG_VOUT1_VSYNC_OUT */
+};
#endif
#endif /* _MUX_DATA_DRA7XX_H_ */
#include <asm/arch/mmc_host_def.h>
#include <fdtdec.h>
#include <i2c.h>
+#include <remoteproc.h>
#include "mux-k2g.h"
#include "../common/board_detect.h"
return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
}
#endif
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
+{
+ int id = getenv_ulong("dev_pmmc", 10, 0);
+ int ret;
+
+ if (!rproc_is_initialized())
+ rproc_init();
+
+ ret = rproc_load(id, pmmc_image, pmmc_size);
+ printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
+ id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
+
+ if (!ret)
+ rproc_start(id);
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
+#endif
#include <dm/platform_data/serial_mxc.h>
#include <dm/platdata.h>
#include <fsl_esdhc.h>
-#include <g_dnl.h>
#include <i2c.h>
#include <imx_thermal.h>
#include <linux/errno.h>
{
}
-#ifdef CONFIG_SPL_USB_GADGET_SUPPORT
-int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
-{
- unsigned short usb_pid;
-
- usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + 0xfff;
- put_unaligned(usb_pid, &dev->idProduct);
-
- return 0;
-}
-#endif
-
#endif
static struct mxc_serial_platdata mxc_serial_plat = {
#include <dm/platform_data/serial_mxc.h>
#include <dm/platdata.h>
#include <fsl_esdhc.h>
-#include <g_dnl.h>
#include <i2c.h>
#include <imx_thermal.h>
#include <linux/errno.h>
{
}
-#ifdef CONFIG_SPL_USB_GADGET_SUPPORT
-int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
-{
- unsigned short usb_pid;
-
- usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + 0xfff;
- put_unaligned(usb_pid, &dev->idProduct);
-
- return 0;
-}
-#endif
-
#endif
static struct mxc_serial_platdata mxc_serial_plat = {
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
#endif
- return set_clk_enet(ENET_50MHz);
+ return set_clk_enet(ENET_50MHZ);
}
int board_phy_config(struct phy_device *phydev)
ret = -EIO;
goto out;
}
- /* Flush cache after read */
- flush_cache((ulong)(unsigned char *)config_block, 512);
} else {
/* Just writing one 512 byte block */
if (blk_dwrite(mmc_get_blk_desc(mmc), blk_start, 1,
/* DDR initialization */
spl_dram_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
}
#endif
/* DDR initialization */
spl_dram_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
}
#endif
ulong cnt = simple_strtoul(argv[4], NULL, 16);
ulong n;
- printf("\n%s read: device %d block # %lld, count %ld ... ",
- if_name, *cur_devnump, (unsigned long long)blk,
- cnt);
+ printf("\n%s read: device %d block # "LBAFU", count %lu ... ",
+ if_name, *cur_devnump, blk, cnt);
n = blk_read_devnum(if_type, *cur_devnump, blk, cnt,
(ulong *)addr);
ulong cnt = simple_strtoul(argv[4], NULL, 16);
ulong n;
- printf("\n%s write: device %d block # %lld, count %ld ... ",
- if_name, *cur_devnump, (unsigned long long)blk,
- cnt);
+ printf("\n%s write: device %d block # "LBAFU", count %lu ... ",
+ if_name, *cur_devnump, blk, cnt);
n = blk_write_devnum(if_type, *cur_devnump, blk, cnt,
(ulong *)addr);
if (!fdt_valid(&blob))
return CMD_RET_FAILURE;
- ret = fdt_overlay_apply(working_fdt, blob);
- if (ret) {
- printf("fdt_overlay_apply(): %s\n", fdt_strerror(ret));
+ /* apply method prints messages on error */
+ ret = fdt_overlay_apply_verbose(working_fdt, blob);
+ if (ret)
return CMD_RET_FAILURE;
- }
}
#endif
/* resize the fdt */
curr_device, blk, cnt);
n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
- /* flush cache after read */
- flush_cache((ulong)addr, cnt * 512); /* FIXME */
printf("%d blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR");
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
c = find_cmd_tbl(argv[1], &cmd_spl_export_sub[0],
ARRAY_SIZE(cmd_spl_export_sub));
- if ((c) && ((int)c->cmd <= SPL_EXPORT_LAST)) {
+ if ((c) && ((long)c->cmd <= SPL_EXPORT_LAST)) {
argc -= 2;
argv += 2;
- if (call_bootm(argc, argv, subcmd_list[(int)c->cmd]))
+ if (call_bootm(argc, argv, subcmd_list[(long)c->cmd]))
return -1;
- switch ((int)c->cmd) {
+ switch ((long)c->cmd) {
#ifdef CONFIG_OF_LIBFDT
case SPL_EXPORT_FDT:
printf("Argument image is now in RAM: 0x%p\n",
c = find_cmd_tbl(argv[1], &cmd_spl_sub[0], ARRAY_SIZE(cmd_spl_sub));
if (c) {
- cmd = (int)c->cmd;
+ cmd = (long)c->cmd;
switch (cmd) {
case SPL_EXPORT:
argc--;
unsigned long long tmp;
struct ubi_volume *vol;
loff_t offp = 0;
+ size_t len_read;
vol = ubi_find_volume(volume);
if (vol == NULL)
tmp = offp;
off = do_div(tmp, vol->usable_leb_size);
lnum = tmp;
+ len_read = size;
do {
if (off + len >= vol->usable_leb_size)
len = vol->usable_leb_size - off;
len = size > tbuf_size ? tbuf_size : size;
} while (size);
+ if (!size)
+ env_set_hex("filesize", len_read);
+
free(tbuf);
return err;
}
29,916,167 26,005,792 bootm_start
30,361,327 445,160 start_kernel
-config BOOTSTAGE_USER_COUNT
- int "Number of boot ID numbers available for user use"
- default 20
- help
- This is the number of available user bootstage records.
- Each time you call bootstage_mark(BOOTSTAGE_ID_ALLOC, ...)
- a new ID will be allocated from this stash. If you exceed
- the limit, recording will stop.
-
config BOOTSTAGE_RECORD_COUNT
int "Number of boot stage records to store"
default 30
This is the size of the bootstage record list and is the maximum
number of bootstage records that can be recorded.
+config SPL_BOOTSTAGE_RECORD_COUNT
+ int "Number of boot stage records to store for SPL"
+ default 5
+ help
+ This is the size of the bootstage record list and is the maximum
+ number of bootstage records that can be recorded.
+
config BOOTSTAGE_FDT
bool "Store boot timing information in the OS device tree"
depends on BOOTSTAGE
endif # !CONFIG_SPL_BUILD
-obj-$(CONFIG_$(SPL_)BOOTSTAGE) += bootstage.o
+obj-$(CONFIG_$(SPL_TPL_)BOOTSTAGE) += bootstage.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_DFU_SUPPORT) += dfu.o
* UART if available.
*/
gd->flags &= ~GD_FLG_SERIAL_READY;
+#ifdef CONFIG_TIMER
+ gd->timer = NULL;
+#endif
/*
* U-Boot has been copied into SDRAM, the BSS has been cleared etc.
DECLARE_GLOBAL_DATA_PTR;
enum {
- RECORD_COUNT = CONFIG_BOOTSTAGE_RECORD_COUNT,
+ RECORD_COUNT = CONFIG_VAL(BOOTSTAGE_RECORD_COUNT),
};
struct bootstage_record {
}
if (data->rec_count > RECORD_COUNT)
printf("Overflowed internal boot id table by %d entries\n"
- "- please increase CONFIG_BOOTSTAGE_RECORD_COUNT\n",
+ "Please increase CONFIG_(SPL_)BOOTSTAGE_RECORD_COUNT\n",
data->rec_count - RECORD_COUNT);
puts("\nAccumulated time:\n");
if (data->rec_count + hdr->count > RECORD_COUNT) {
debug("%s: Bootstage has %d records, we have space for %d\n"
- "- please increase CONFIG_BOOTSTAGE_USER_COUNT\n",
+ "Please increase CONFIG_(SPL_)BOOTSTAGE_RECORD_COUNT\n",
__func__, hdr->count, RECORD_COUNT - data->rec_count);
return -ENOSPC;
}
}
return toff;
}
+
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+/**
+ * fdt_overlay_apply_verbose - Apply an overlay with verbose error reporting
+ *
+ * @fdt: ptr to device tree
+ * @fdto: ptr to device tree overlay
+ *
+ * Convenience function to apply an overlay and display helpful messages
+ * in the case of an error
+ */
+int fdt_overlay_apply_verbose(void *fdt, void *fdto)
+{
+ int err;
+ bool has_symbols;
+
+ err = fdt_path_offset(fdt, "/__symbols__");
+ has_symbols = err >= 0;
+
+ err = fdt_overlay_apply(fdt, fdto);
+ if (err < 0) {
+ printf("failed on fdt_overlay_apply(): %s\n",
+ fdt_strerror(err));
+ if (!has_symbols) {
+ printf("base fdt does did not have a /__symbols__ node\n");
+ printf("make sure you've compiled with -@\n");
+ }
+ }
+ return err;
+}
+#endif
if (fit_check_format(buf)) {
ulong load, len;
- fdt_noffset = fit_image_load(images,
+ fdt_noffset = boot_get_fdt_fit(images,
fdt_addr, &fit_uname_fdt,
&fit_uname_config,
- arch, IH_TYPE_FLATDT,
- BOOTSTAGE_ID_FIT_FDT_START,
- FIT_LOAD_OPTIONAL, &load, &len);
+ arch, &load, &len);
images->fit_hdr_fdt = map_sysmem(fdt_addr, 0);
images->fit_uname_fdt = fit_uname_fdt;
images->fit_noffset_fdt = fdt_noffset;
fdt_addr = load;
+
break;
} else
#endif
#include <errno.h>
#include <mapmem.h>
#include <asm/io.h>
+#include <malloc.h>
DECLARE_GLOBAL_DATA_PTR;
#endif /* !USE_HOSTCC*/
printf("0x%08lx\n", load);
}
+ /* optional load address for FDT */
+ if (type == IH_TYPE_FLATDT && !fit_image_get_load(fit, image_noffset, &load))
+ printf("%s Load Address: 0x%08lx\n", p, load);
+
if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
(type == IH_TYPE_RAMDISK)) {
ret = fit_image_get_entry(fit, image_noffset, &entry);
{
int noffset, confs_noffset;
int len;
+ const char *s;
+ char *conf_uname_copy = NULL;
confs_noffset = fdt_path_offset(fit, FIT_CONFS_PATH);
if (confs_noffset < 0) {
debug("Found default configuration: '%s'\n", conf_uname);
}
+ s = strchr(conf_uname, '#');
+ if (s) {
+ len = s - conf_uname;
+ conf_uname_copy = malloc(len + 1);
+ if (!conf_uname_copy) {
+ debug("Can't allocate uname copy: '%s'\n",
+ conf_uname);
+ return -ENOMEM;
+ }
+ memcpy(conf_uname_copy, conf_uname, len);
+ conf_uname_copy[len] = '\0';
+ conf_uname = conf_uname_copy;
+ }
+
noffset = fdt_subnode_offset(fit, confs_noffset, conf_uname);
if (noffset < 0) {
debug("Can't get node offset for configuration unit name: '%s' (%s)\n",
conf_uname, fdt_strerror(noffset));
}
+ if (conf_uname_copy)
+ free(conf_uname_copy);
+
return noffset;
}
-int fit_conf_get_prop_node(const void *fit, int noffset,
+int fit_conf_get_prop_node_count(const void *fit, int noffset,
const char *prop_name)
{
- char *uname;
+ return fdt_stringlist_count(fit, noffset, prop_name);
+}
+
+int fit_conf_get_prop_node_index(const void *fit, int noffset,
+ const char *prop_name, int index)
+{
+ const char *uname;
int len;
/* get kernel image unit name from configuration kernel property */
- uname = (char *)fdt_getprop(fit, noffset, prop_name, &len);
+ uname = fdt_stringlist_get(fit, noffset, prop_name, index, &len);
if (uname == NULL)
return len;
return fit_image_get_node(fit, uname);
}
+int fit_conf_get_prop_node(const void *fit, int noffset,
+ const char *prop_name)
+{
+ return fit_conf_get_prop_node_index(fit, noffset, prop_name, 0);
+}
+
/**
* fit_conf_print - prints out the FIT configuration details
* @fit: pointer to the FIT format image header
char *desc;
const char *uname;
int ret;
- int loadables_index;
+ int fdt_index, loadables_index;
/* Mandatory properties */
ret = fit_get_desc(fit, noffset, &desc);
if (uname)
printf("%s Init Ramdisk: %s\n", p, uname);
- uname = fdt_getprop(fit, noffset, FIT_FDT_PROP, NULL);
- if (uname)
- printf("%s FDT: %s\n", p, uname);
+ for (fdt_index = 0;
+ uname = fdt_stringlist_get(fit, noffset, FIT_FDT_PROP,
+ fdt_index, NULL), uname;
+ fdt_index++) {
+
+ if (fdt_index == 0)
+ printf("%s FDT: ", p);
+ else
+ printf("%s ", p);
+ printf("%s\n", uname);
+ }
uname = fdt_getprop(fit, noffset, FIT_FPGA_PROP, NULL);
if (uname)
int cfg_noffset, noffset;
const char *fit_uname;
const char *fit_uname_config;
+ const char *fit_base_uname_config;
const void *fit;
const void *buf;
size_t size;
fit = map_sysmem(addr, 0);
fit_uname = fit_unamep ? *fit_unamep : NULL;
fit_uname_config = fit_uname_configp ? *fit_uname_configp : NULL;
+ fit_base_uname_config = NULL;
prop_name = fit_get_image_type_property(image_type);
printf("## Loading %s from FIT Image at %08lx ...\n", prop_name, addr);
BOOTSTAGE_SUB_NO_UNIT_NAME);
return -ENOENT;
}
- fit_uname_config = fdt_get_name(fit, cfg_noffset, NULL);
- printf(" Using '%s' configuration\n", fit_uname_config);
+ fit_base_uname_config = fdt_get_name(fit, cfg_noffset, NULL);
+ printf(" Using '%s' configuration\n", fit_base_uname_config);
if (image_type == IH_TYPE_KERNEL) {
/* Remember (and possibly verify) this config */
- images->fit_uname_cfg = fit_uname_config;
+ images->fit_uname_cfg = fit_base_uname_config;
if (IMAGE_ENABLE_VERIFY && images->verify) {
puts(" Verifying Hash Integrity ... ");
if (fit_config_verify(fit, cfg_noffset)) {
if (fit_unamep)
*fit_unamep = (char *)fit_uname;
if (fit_uname_configp)
- *fit_uname_configp = (char *)fit_uname_config;
+ *fit_uname_configp = (char *)(fit_uname_config ? :
+ fit_base_uname_config);
return noffset;
}
return ret;
}
+
+#ifndef USE_HOSTCC
+int boot_get_fdt_fit(bootm_headers_t *images, ulong addr,
+ const char **fit_unamep, const char **fit_uname_configp,
+ int arch, ulong *datap, ulong *lenp)
+{
+ int fdt_noffset, cfg_noffset, count;
+ const void *fit;
+ const char *fit_uname = NULL;
+ const char *fit_uname_config = NULL;
+ char *fit_uname_config_copy = NULL;
+ char *next_config = NULL;
+ ulong load, len;
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+ ulong image_start, image_end;
+ ulong ovload, ovlen;
+ const char *uconfig;
+ const char *uname;
+ void *base, *ov;
+ int i, err, noffset, ov_noffset;
+#endif
+
+ fit_uname = fit_unamep ? *fit_unamep : NULL;
+
+ if (fit_uname_configp && *fit_uname_configp) {
+ fit_uname_config_copy = strdup(*fit_uname_configp);
+ if (!fit_uname_config_copy)
+ return -ENOMEM;
+
+ next_config = strchr(fit_uname_config_copy, '#');
+ if (next_config)
+ *next_config++ = '\0';
+ if (next_config - 1 > fit_uname_config_copy)
+ fit_uname_config = fit_uname_config_copy;
+ }
+
+ fdt_noffset = fit_image_load(images,
+ addr, &fit_uname, &fit_uname_config,
+ arch, IH_TYPE_FLATDT,
+ BOOTSTAGE_ID_FIT_FDT_START,
+ FIT_LOAD_OPTIONAL, &load, &len);
+
+ if (fdt_noffset < 0)
+ goto out;
+
+ debug("fit_uname=%s, fit_uname_config=%s\n",
+ fit_uname ? fit_uname : "<NULL>",
+ fit_uname_config ? fit_uname_config : "<NULL>");
+
+ fit = map_sysmem(addr, 0);
+
+ cfg_noffset = fit_conf_get_node(fit, fit_uname_config);
+
+ /* single blob, or error just return as well */
+ count = fit_conf_get_prop_node_count(fit, cfg_noffset, FIT_FDT_PROP);
+ if (count <= 1 && !next_config)
+ goto out;
+
+ /* we need to apply overlays */
+
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+ image_start = addr;
+ image_end = addr + fit_get_size(fit);
+ /* verify that relocation took place by load address not being in fit */
+ if (load >= image_start && load < image_end) {
+ /* check is simplified; fit load checks for overlaps */
+ printf("Overlayed FDT requires relocation\n");
+ fdt_noffset = -EBADF;
+ goto out;
+ }
+
+ base = map_sysmem(load, len);
+
+ /* apply extra configs in FIT first, followed by args */
+ for (i = 1; ; i++) {
+ if (i < count) {
+ noffset = fit_conf_get_prop_node_index(fit, cfg_noffset,
+ FIT_FDT_PROP, i);
+ uname = fit_get_name(fit, noffset, NULL);
+ uconfig = NULL;
+ } else {
+ if (!next_config)
+ break;
+ uconfig = next_config;
+ next_config = strchr(next_config, '#');
+ if (next_config)
+ *next_config++ = '\0';
+ uname = NULL;
+ }
+
+ debug("%d: using uname=%s uconfig=%s\n", i, uname, uconfig);
+
+ ov_noffset = fit_image_load(images,
+ addr, &uname, &uconfig,
+ arch, IH_TYPE_FLATDT,
+ BOOTSTAGE_ID_FIT_FDT_START,
+ FIT_LOAD_REQUIRED, &ovload, &ovlen);
+ if (ov_noffset < 0) {
+ printf("load of %s failed\n", uname);
+ continue;
+ }
+ debug("%s loaded at 0x%08lx len=0x%08lx\n",
+ uname, ovload, ovlen);
+ ov = map_sysmem(ovload, ovlen);
+
+ base = map_sysmem(load, len + ovlen);
+ err = fdt_open_into(base, base, len + ovlen);
+ if (err < 0) {
+ printf("failed on fdt_open_into\n");
+ fdt_noffset = err;
+ goto out;
+ }
+ /* the verbose method prints out messages on error */
+ err = fdt_overlay_apply_verbose(base, ov);
+ if (err < 0) {
+ fdt_noffset = err;
+ goto out;
+ }
+ fdt_pack(base);
+ len = fdt_totalsize(base);
+ }
+#else
+ printf("config with overlays but CONFIG_OF_LIBFDT_OVERLAY not set\n");
+ fdt_noffset = -EBADF;
+#endif
+
+out:
+ if (datap)
+ *datap = load;
+ if (lenp)
+ *lenp = len;
+ if (fit_unamep)
+ *fit_unamep = fit_uname;
+ if (fit_uname_configp)
+ *fit_uname_configp = fit_uname_config;
+
+ if (fit_uname_config_copy)
+ free(fit_uname_config_copy);
+ return fdt_noffset;
+}
+#endif
{ IH_TYPE_FPGA, "fpga", "FPGA Image" },
{ IH_TYPE_TEE, "tee", "Trusted Execution Environment Image",},
{ IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT" },
+ { IH_TYPE_PMMC, "pmmc", "TI Power Management Micro-Controller Firmware",},
{ -1, "", "", },
};
spl_image->load_addr, spl_image->size);
#else
/* LEGACY image not supported */
- debug("Legacy boot image support not enabled, proceeding to other boot methods");
+ debug("Legacy boot image support not enabled, proceeding to other boot methods\n");
return -EINVAL;
#endif
} else {
spl_set_header_raw_uboot(spl_image);
#else
/* RAW image not supported, proceed to other boot methods. */
- debug("Raw boot image support not enabled, proceeding to other boot methods");
+ debug("Raw boot image support not enabled, proceeding to other boot methods\n");
return -EINVAL;
#endif
}
#include <libfdt.h>
#include <spl.h>
+#ifndef CONFIG_SYS_BOOTM_LEN
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+#endif
+
/**
* spl_fit_get_image_node(): By using the matching configuration subnode,
* retrieve the name of an image, specified by a property name and an index
void *fit, ulong base_offset, int node,
struct spl_image_info *image_info)
{
- ulong offset;
+ int offset;
size_t length;
+ int len;
ulong load_addr, load_ptr;
void *src;
ulong overhead;
int nr_sectors;
int align_len = ARCH_DMA_MINALIGN - 1;
+ uint8_t image_comp = -1, type = -1;
+ const void *data;
+
+ if (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP)) {
+ if (fit_image_get_comp(fit, node, &image_comp))
+ puts("Cannot get image compression format.\n");
+ else
+ debug("%s ", genimg_get_comp_name(image_comp));
+
+ if (fit_image_get_type(fit, node, &type))
+ puts("Cannot get image type.\n");
+ else
+ debug("%s ", genimg_get_type_name(type));
+ }
- offset = fdt_getprop_u32(fit, node, "data-offset");
- if (offset == FDT_ERROR)
- return -ENOENT;
- offset += base_offset;
- length = fdt_getprop_u32(fit, node, "data-size");
- if (length == FDT_ERROR)
- return -ENOENT;
- load_addr = fdt_getprop_u32(fit, node, "load");
- if (load_addr == FDT_ERROR && image_info)
+ if (fit_image_get_load(fit, node, &load_addr))
load_addr = image_info->load_addr;
- load_ptr = (load_addr + align_len) & ~align_len;
-
- overhead = get_aligned_image_overhead(info, offset);
- nr_sectors = get_aligned_image_size(info, length, offset);
- if (info->read(info, sector + get_aligned_image_offset(info, offset),
- nr_sectors, (void*)load_ptr) != nr_sectors)
- return -EIO;
- debug("image: dst=%lx, offset=%lx, size=%lx\n", load_ptr, offset,
- (unsigned long)length);
+ if (!fit_image_get_data_offset(fit, node, &offset)) {
+ /* External data */
+ offset += base_offset;
+ if (fit_image_get_data_size(fit, node, &len))
+ return -ENOENT;
+
+ load_ptr = (load_addr + align_len) & ~align_len;
+ length = len;
+
+ overhead = get_aligned_image_overhead(info, offset);
+ nr_sectors = get_aligned_image_size(info, length, offset);
+
+ if (info->read(info,
+ sector + get_aligned_image_offset(info, offset),
+ nr_sectors, (void *)load_ptr) != nr_sectors)
+ return -EIO;
+
+ debug("External data: dst=%lx, offset=%x, size=%lx\n",
+ load_ptr, offset, (unsigned long)length);
+ src = (void *)load_ptr + overhead;
+ } else {
+ /* Embedded data */
+ if (fit_image_get_data(fit, node, &data, &length)) {
+ puts("Cannot get image data/size\n");
+ return -ENOENT;
+ }
+ debug("Embedded data: dst=%lx, size=%lx\n", load_addr,
+ (unsigned long)length);
+ src = (void *)data;
+ }
- src = (void *)load_ptr + overhead;
#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
board_fit_image_post_process(&src, &length);
#endif
- memcpy((void*)load_addr, src, length);
+ if (IS_ENABLED(CONFIG_SPL_OS_BOOT) &&
+ IS_ENABLED(CONFIG_SPL_GZIP) &&
+ image_comp == IH_COMP_GZIP &&
+ type == IH_TYPE_KERNEL) {
+ if (gunzip((void *)load_addr, CONFIG_SYS_BOOTM_LEN,
+ src, &length)) {
+ puts("Uncompressing error\n");
+ return -EIO;
+ }
+ } else {
+ memcpy((void *)load_addr, src, length);
+ }
if (image_info) {
image_info->load_addr = load_addr;
ulong size;
unsigned long count;
struct spl_image_info image_info;
- int node, images, ret;
+ bool boot_os = false;
+ int node = -1;
+ int images, ret;
int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
int index = 0;
/*
- * Figure out where the external images start. This is the base for the
- * data-offset properties in each image.
+ * For FIT with external data, figure out where the external images
+ * start. This is the base for the data-offset properties in each
+ * image.
*/
size = fdt_totalsize(fit);
size = (size + 3) & ~3;
*
* In fact the FIT has its own load address, but we assume it cannot
* be before CONFIG_SYS_TEXT_BASE.
+ *
+ * For FIT with data embedded, data is loaded as part of FIT image.
+ * For FIT with external data, data is not loaded in this step.
*/
fit = (void *)((CONFIG_SYS_TEXT_BASE - size - info->bl_len -
align_len) & ~align_len);
return -1;
}
+#ifdef CONFIG_SPL_OS_BOOT
+ /* Find OS image first */
+ node = spl_fit_get_image_node(fit, images, FIT_KERNEL_PROP, 0);
+ if (node < 0)
+ debug("No kernel image.\n");
+ else
+ boot_os = true;
+#endif
/* find the U-Boot image */
- node = spl_fit_get_image_node(fit, images, "firmware", 0);
+ if (node < 0)
+ node = spl_fit_get_image_node(fit, images, "firmware", 0);
if (node < 0) {
debug("could not find firmware image, trying loadables...\n");
node = spl_fit_get_image_node(fit, images, "loadables", 0);
if (ret)
return ret;
+#ifdef CONFIG_SPL_OS_BOOT
+ if (!fit_image_get_os(fit, node, &spl_image->os))
+ debug("Image OS is %s\n", genimg_get_os_name(spl_image->os));
+#else
spl_image->os = IH_OS_U_BOOT;
+#endif
- /* Figure out which device tree the board wants to use */
- node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
- if (node < 0) {
- debug("%s: cannot find FDT node\n", __func__);
- return node;
- }
+ if (!boot_os) {
+ /* Figure out which device tree the board wants to use */
+ node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
+ if (node < 0) {
+ debug("%s: cannot find FDT node\n", __func__);
+ return node;
+ }
- /*
- * Read the device tree and place it after the image.
- * Align the destination address to ARCH_DMA_MINALIGN.
- */
- image_info.load_addr = spl_image->load_addr + spl_image->size;
- ret = spl_load_fit_image(info, sector, fit, base_offset, node,
- &image_info);
- if (ret < 0)
- return ret;
+ /*
+ * Read the device tree and place it after the image.
+ * Align the destination address to ARCH_DMA_MINALIGN.
+ */
+ image_info.load_addr = spl_image->load_addr + spl_image->size;
+ ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+ &image_info);
+ if (ret < 0)
+ return ret;
+ }
/* Now check if there are more images for us to load */
for (; ; index++) {
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="NDS32 # "
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
-CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_CLK=y
CONFIG_MMC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_ETH=y
CONFIG_FTMAC100=y
CONFIG_BAUDRATE=38400
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_NDS_AE3XX_SPI=y
CONFIG_TIMER=y
CONFIG_AE3XX_TIMER=y
CONFIG_SYS_TEXT_BASE=0x80100000
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_TARGET_AM3517_CRANE=y
+CONFIG_EMIF4=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_TARGET_AM3517_EVM=y
+CONFIG_EMIF4=y
CONFIG_BOOTDELAY=10
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="AM3517_EVM # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EEPROM is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
+# CONFIG_CMD_GPT is not set
CONFIG_CMD_NAND=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_USB=y
+# CONFIG_CMD_SPI is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
+# CONFIG_CMD_MII is not set
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+# CONFIG_CMD_TIME is not set
CONFIG_CMD_UBI=y
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_STORAGE=y
+# CONFIG_FAT_WRITE is not set
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am572x-idk am571x-idk"
+CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am572x-idk am571x-idk"
+CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
CONFIG_DEBUG_UART=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mmcblk0p2 rw rootwait"
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
CONFIG_DEBUG_UART=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
+CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2"
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek"
CONFIG_DEBUG_UART=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek"
CONFIG_DEBUG_UART=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
+CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek"
CONFIG_DEBUG_UART=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
+CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw"
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="mem=128M console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
+CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw"
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_DEBUG_UART=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
+CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw"
--- /dev/null
+CONFIG_X86=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_DEFAULT_DEVICE_TREE="cherryhill"
+CONFIG_TARGET_CHERRYHILL=y
+CONFIG_DEBUG_UART=y
+CONFIG_SMP=y
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_RTL8169=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_NS16550=y
CONFIG_SPL_TIMER=y
+CONFIG_TIMER_EARLY=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_NS16550=y
+CONFIG_TIMER_EARLY=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_CM_T3517=y
+CONFIG_EMIF4=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DA850EVM=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_MAC_ADDR_IN_EEPROM=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50"
+CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BOOTZ is not set
# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
+# CONFIG_CMD_EEPROM is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_GPT is not set
+# CONFIG_CMD_I2C is not set
+# CONFIG_CMD_PART is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
+# CONFIG_CMD_TIME is not set
+# CONFIG_CMD_EXT4 is not set
+# CONFIG_CMD_FS_GENERIC is not set
CONFIG_CMD_DIAG=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+# CONFIG_FAT_WRITE is not set
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DA850EVM=y
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
+# CONFIG_CMD_EEPROM is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_GPT is not set
+# CONFIG_CMD_I2C is not set
+# CONFIG_CMD_PART is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
+# CONFIG_CMD_TIME is not set
+# CONFIG_CMD_EXT4 is not set
+# CONFIG_CMD_FS_GENERIC is not set
CONFIG_CMD_DIAG=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+# CONFIG_FAT_WRITE is not set
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DA850EVM=y
-CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT"
+CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_SYS_EXTRA_OPTIONS="USE_NOR,DIRECT_NOR_BOOT"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_BOOTZ is not set
CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_SF=y
+# CONFIG_CMD_EEPROM is not set
+# CONFIG_CMD_GPIO is not set
+# CONFIG_CMD_GPT is not set
+# CONFIG_CMD_I2C is not set
+# CONFIG_CMD_MMC is not set
+# CONFIG_CMD_PART is not set
+# CONFIG_CMD_SPI is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+# CONFIG_CMD_TIME is not set
+# CONFIG_CMD_EXT2 is not set
+# CONFIG_CMD_EXT4 is not set
+# CONFIG_CMD_FAT is not set
+# CONFIG_CMD_FS_GENERIC is not set
CONFIG_CMD_DIAG=y
CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_MMC is not set
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
+CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
+CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_ECO5PK=y
+CONFIG_EMIF4=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb"
CONFIG_DEBUG_UART=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x62000000
+CONFIG_FASTBOOT_BUF_SIZE=0x08000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RV1108=y
+CONFIG_DM_REGULATOR_FIXED=y
CONFIG_BAUDRATE=1500000
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DEBUG_UART_BASE=0x10210000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x110a
CONFIG_ERRNO_STR=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/lion_rk3368/fit_spl_atf.its"
+CONFIG_BOOTSTAGE=y
+CONFIG_SPL_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_BOOTSTAGE_FDT=y
+CONFIG_ENV_IS_IN_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_SPL=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
+CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_MTDPARTS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088AQDS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_FSL_LS_PPA=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088ARDB=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_FSL_LS_PPA=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080ARDB=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_BOOTDELAY=10
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SECURE_BOOT=y
+CONFIG_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4"
+CONFIG_SYS_EXTRA_OPTIONS=""
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS3,115200"
CONFIG_SYS_TEXT_BASE=0x80008000
# CONFIG_SPL_GPIO_SUPPORT is not set
CONFIG_TARGET_MCX=y
+CONFIG_EMIF4=y
CONFIG_VIDEO=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_MT_VENTOUX=y
+CONFIG_EMIF4=y
CONFIG_VIDEO=y
CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_PCI=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
-# CONFIG_CMD_USB is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="TI"
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D27_SOM1_EK=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xf8020000
+CONFIG_DEBUG_UART_CLOCK=82000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH"
+CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,57600 earlyprintk mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs"
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
+CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,57600 earlyprintk mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait"
CONFIG_ATMEL_PIO4=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
+CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
CONFIG_ATMEL_PIO4=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
+CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d3_xplained"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
+CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_AT91_H32MX=y
CONFIG_DM_GPIO=y
CONFIG_AT91_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
+CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
CONFIG_AT91_H32MX=y
CONFIG_DM_GPIO=y
CONFIG_AT91_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
CONFIG_AT91_H32MX=y
CONFIG_DM_GPIO=y
CONFIG_AT91_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
+CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_BOOTSTAGE_USER_COUNT=32
CONFIG_BOOTSTAGE_FDT=y
CONFIG_BOOTSTAGE_STASH=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_CMD_DEMO=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_TPM=y
CONFIG_LZ4=y
CONFIG_ERRNO_STR=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
CONFIG_UT_ENV=y
+CONFIG_UT_OVERLAY=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_BOOTSTAGE_USER_COUNT=32
CONFIG_BOOTSTAGE_FDT=y
CONFIG_BOOTSTAGE_STASH=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_BOOTSTAGE_USER_COUNT=32
CONFIG_BOOTSTAGE_FDT=y
CONFIG_BOOTSTAGE_STASH=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_BOOTSTAGE_USER_COUNT=32
CONFIG_BOOTSTAGE_FDT=y
CONFIG_BOOTSTAGE_STASH=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_ROCKCHIP_RK3368=y
+CONFIG_TARGET_SHEEP=y
CONFIG_DEFAULT_DEVICE_TREE="rk3368-sheep"
CONFIG_DEBUG_UART=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ROCKCHIP_RK3368=y
CONFIG_RAM=y
CONFIG_DEBUG_UART_BASE=0xFF1b0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_TARGET_TWISTER=y
+CONFIG_EMIF4=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
# CONFIG_SPL_EXT_SUPPORT is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-pro4-ref"
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_SPL=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_CONFIG=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_GPIO_UNIPHIER=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
-CONFIG_MMC_UNIPHIER=y
-CONFIG_NAND=y
-CONFIG_NAND_DENALI=y
-CONFIG_NAND_DENALI_DT=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
-CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_SPL_NAND_DENALI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_STORAGE=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y
-CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka"
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_SPL=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_CONFIG=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_GPIO_UNIPHIER=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
-CONFIG_MMC_UNIPHIER=y
-CONFIG_NAND=y
-CONFIG_NAND_DENALI=y
-CONFIG_NAND_DENALI_DT=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
-CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_SPL_NAND_DENALI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_STORAGE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_ARCH_UNIPHIER_V7_MULTI=y
+CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka"
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SPL=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CONFIG=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_GPIO_UNIPHIER=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
+CONFIG_MMC_UNIPHIER=y
+CONFIG_NAND=y
+CONFIG_NAND_DENALI=y
+CONFIG_NAND_DENALI_DT=y
+CONFIG_SYS_NAND_DENALI_64BIT=y
+CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_SPL_NAND_DENALI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_VINCO=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk rw root=/dev/mmcblk0p2 rootfstype=ext4 rootwait quiet lpj=1990656"
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3288=y
+CONFIG_TARGET_VYASA_RK3288=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-vyasa"
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SILENT_CONSOLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_PINCTRL_ROCKCHIP_RK3288=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_DEBUG_UART_BASE=0xff690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
return -1;
}
+int part_get_info_whole_disk(struct blk_desc *dev_desc, disk_partition_t *info)
+{
+ info->start = 0;
+ info->size = dev_desc->lba;
+ info->blksz = dev_desc->blksz;
+ info->bootable = 0;
+ strcpy((char *)info->type, BOOT_PART_TYPE);
+ strcpy((char *)info->name, "Whole Disk");
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
+ info->uuid[0] = 0;
+#endif
+#ifdef CONFIG_PARTITION_TYPE_GUID
+ info->type_guid[0] = 0;
+#endif
+
+ return 0;
+}
+
int blk_get_device_by_str(const char *ifname, const char *dev_hwpart_str,
struct blk_desc **dev_desc)
{
(*dev_desc)->log2blksz = LOG2((*dev_desc)->blksz);
- info->start = 0;
- info->size = (*dev_desc)->lba;
- info->blksz = (*dev_desc)->blksz;
- info->bootable = 0;
- strcpy((char *)info->type, BOOT_PART_TYPE);
- strcpy((char *)info->name, "Whole Disk");
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- info->uuid[0] = 0;
-#endif
-#ifdef CONFIG_PARTITION_TYPE_GUID
- info->type_guid[0] = 0;
-#endif
+ part_get_info_whole_disk(*dev_desc, info);
ret = 0;
goto cleanup;
--- /dev/null
+U-Boot FDT Overlay usage
+=============================================
+
+Overlays Syntax
+---------------
+
+Overlays require slightly different syntax compared to traditional overlays.
+Please refer to dt-object-internal.txt in the dtc sources for information
+regarding the internal format of overlays:
+https://git.kernel.org/pub/scm/utils/dtc/dtc.git/tree/Documentation/dt-object-internal.txt
+
+Building Overlays
+-----------------
+
+In a nutshell overlays provides a means to manipulate a symbol a previous dtb
+or overlay has defined. It requires both the base and all the overlays
+to be compiled with the -@ command line switch so that symbol information is
+included.
+
+Note support for -@ option can only be found in dtc version 1.4.4 or newer.
+Only version 4.14 or higher of the Linux kernel includes a built in version
+of dtc that meets this requirement.
+
+Building an overlay follows the same process as building a traditional dtb.
+
+For example:
+
+base.dts
+--------
+
+ /dts-v1/;
+ / {
+ foo: foonode {
+ foo-property;
+ };
+ };
+
+ $ dtc -@ -I dts -O dtb -o base.dtb base.dts
+
+bar.dts
+-------
+
+ /dts-v1/;
+ /plugin/;
+ / {
+ fragment@1 {
+ target = <&foo>;
+ __overlay__ {
+ overlay-1-property;
+ bar: barnode {
+ bar-property;
+ };
+ };
+ };
+ };
+
+ $ dtc -@ -I dts -O dtb -o bar.dtb bar.dts
+
+Ways to Utilize Overlays in U-boot
+----------------------------------
+
+There are two ways to apply overlays in U-boot.
+1. Include and define overlays within a FIT image and have overlays
+ automatically applied.
+
+2. Manually load and apply overlays
+
+The remainder of this document will discuss using overlays via the manual
+approach. For information on using overlays as part of a FIT image please see:
+doc/uImage.FIT/overlay-fdt-boot.txt
+
+Manually Loading and Applying Overlays
+--------------------------------------
+
+1. Figure out where to place both the base device tree blob and the
+overlay. Make sure you have enough space to grow the base tree without
+overlapping anything.
+
+=> setenv fdtaddr 0x87f00000
+=> setenv fdtovaddr 0x87fc0000
+
+2. Load the base blob and overlay blobs
+
+=> load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/base.dtb
+=> load ${devtype} ${bootpart} ${fdtovaddr} ${bootdir}/overlay.dtb
+
+3. Set it as the working fdt tree.
+
+=> fdtaddr $fdtaddr
+
+4. Grow it enough so it can 'fit' all the applied overlays
+
+=> fdt resize 8192
+
+5. You are now ready to apply the overlay.
+
+=> fdt apply $fdtovaddr
+
+6. Boot system like you would do with a traditional dtb.
+
+For bootm:
+
+=> bootm ${kerneladdr} - ${fdtaddr}
+
+For bootz:
+
+=> bootz ${kerneladdr} - ${fdtaddr}
+
+Please note that in case of an error, both the base and overlays are going
+to be invalidated, so keep copies to avoid reloading.
+
+Pantelis Antoniou
+pantelis.antoniou@konsulko.com
+11/7/2017
32bit SoC boards:
- Board | <defconfig> | <device-tree>
----------------|------------------------------|------------------------------
-LD4 reference | uniphier_ld4_sld8_defconfig | uniphier-ld4-ref (default)
-sld8 reference | uniphier_ld4_sld8_defconfig | uniphier-sld8-def
-Pro4 reference | uniphier_pro4_defconfig | uniphier-pro4-ref (default)
-Pro4 Ace | uniphier_pro4_defconfig | uniphier-pro4-ace
-Pro4 Sanji | uniphier_pro4_defconfig | uniphier-pro4-sanji
-Pro5 4KBOX | uniphier_pxs2_ld6b_defconfig | uniphier-pro5-4kbox
-PXs2 Gentil | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-gentil
-PXs2 Vodka | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-vodka (default)
-LD6b reference | uniphier_pxs2_ld6b_defconfig | uniphier-ld6b-ref
+ Board | <defconfig> | <device-tree>
+---------------|-----------------------------|------------------------------
+LD4 reference | uniphier_ld4_sld8_defconfig | uniphier-ld4-ref (default)
+sld8 reference | uniphier_ld4_sld8_defconfig | uniphier-sld8-def
+Pro4 reference | uniphier_v7_defconfig | uniphier-pro4-ref
+Pro4 Ace | uniphier_v7_defconfig | uniphier-pro4-ace
+Pro4 Sanji | uniphier_v7_defconfig | uniphier-pro4-sanji
+Pro5 4KBOX | uniphier_v7_defconfig | uniphier-pro5-4kbox
+PXs2 Gentil | uniphier_v7_defconfig | uniphier-pxs2-gentil
+PXs2 Vodka | uniphier_v7_defconfig | uniphier-pxs2-vodka (default)
+LD6b reference | uniphier_v7_defconfig | uniphier-ld6b-ref
64bit SoC boards:
LD11 Global | uniphier_v8_defconfig | uniphier-ld11-global
LD20 reference | uniphier_v8_defconfig | uniphier-ld20-ref (default)
LD20 Global | uniphier_v8_defconfig | uniphier-ld20-global
+PXs3 reference | uniphier_v8_defconfig | uniphier-pxs3-ref
For example, to compile the source for PXs2 Vodka board, run the following:
- $ make uniphier_pxs2_ld6b_defconfig
+ $ make uniphier_v7_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-vodka
The device tree marked as (default) can be omitted. `uniphier-pxs2-vodka` is
-the default device tree for the configuration `uniphier_pxs2_ld6b_defconfig`,
-so the following gives the same result.
+the default device tree for the configuration `uniphier_v7_defconfig`, so the
+following gives the same result.
- $ make uniphier_pxs2_ld6b_defconfig
+ $ make uniphier_v7_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabihf-
--
Masahiro Yamada <yamada.masahiro@socionext.com>
-Jul. 2017
+Sep. 2017
are supported:
- Bayley Bay CRB
+ - Cherry Hill CRB
- Congatec QEVAL 2.0 & conga-QA3/E3845
- Cougar Canyon 2 CRB
- Crown Bay CRB
---
+Intel Cherry Hill specific instructions for bare mode:
+
+This uses Intel FSP for Braswell platform. Download it from Intel FSP website,
+put the .fd file to the board directory and rename it to fsp.bin.
+
+Extract descriptor.bin and me.bin from the original BIOS on the board using
+ifdtool and put them to the board directory as well.
+
+Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS
+image for the integrated graphics device. Instead a new binary called Video
+BIOS Table (VBT) is shipped. Put it to the board directory and rename it to
+vbt.bin if you want graphics support in U-Boot.
+
+Now you can build U-Boot and obtain u-boot.rom
+
+$ make cherryhill_defconfig
+$ make all
+
+An important note for programming u-boot.rom to the on-board SPI flash is that
+you need make sure the SPI flash's 'quad enable' bit in its status register
+matches the settings in the descriptor.bin, otherwise the board won't boot.
+
+For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the
+status register by DediProg in: Config > Modify Status Register > Write Status
+Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it
+persists in SPI flash part regardless of the u-boot.rom image burned.
+
+---
+
Intel Galileo instructions for bare mode:
Only one binary blob is needed for Remote Management Unit (RMU) within Intel
--- /dev/null
+# List of addresses picked up by patman/get_maintainer.pl that are known to
+# bounce. Addresses are listed one per line and need to match the author
+# information recorded in git.
bool cap_sd_highspeed;
fdt32_t card_detect_delay;
fdt32_t clock_freq_min_max[2];
- struct phandle_2_cell clocks[4];
+ struct phandle_1_arg clocks[4];
bool disable_wp;
fdt32_t fifo_depth;
fdt32_t interrupts[3];
New uImage:
8. bootm <addr1>
9. bootm [<addr1>]:<subimg1>
-10. bootm [<addr1>]#<conf>
+10. bootm [<addr1>]#<conf>[#<extra-conf[#...]]
11. bootm [<addr1>]:<subimg1> [<addr2>]:<subimg2>
12. bootm [<addr1>]:<subimg1> [<addr2>]:<subimg2> [<addr3>]:<subimg3>
13. bootm [<addr1>]:<subimg1> [<addr2>]:<subimg2> <addr3>
- new uImage configuration specification
<addr>#<configuration unit_name>
+- new uImage configuration specification with extra configuration components
+<addr>#<configuration unit_name>[#<extra configuration unit_name>[#..]]
+
+The extra configuration currently is supported only for additional device tree
+overlays to apply on the base device tree supplied by the first configuration
+unit.
Examples:
- boot configuration "cfg@1" from a new uImage located at 200000:
bootm 200000#cfg@1
+- boot configuration "cfg@1" with extra "cfg@2" from a new uImage located
+ at 200000:
+bootm 200000#cfg@1#cfg@2
+
- boot "kernel@1" from a new uImage at 200000 with initrd "ramdisk@2" found in
some other new uImage stored at address 800000:
bootm 200000:kernel@1 800000:ramdisk@2
* (Bogus) example FIT image description file demonstrating the usage
* of multiple images loaded by the SPL.
* Several binaries will be loaded at their respective load addresses.
+ *
+ * For booting U-Boot, "firmware" is searched first. If not found, "loadables"
+ * is used to identify images to be loaded into memory. If falcon boot is
+ * enabled, "kernel" is searched first. If not found, it falls back to the
+ * same flow as booting U-Boot. Changing image type will result skipping
+ * specific image.
+ *
* Finally the one image specifying an entry point will be entered by the SPL.
*/
--- /dev/null
+U-Boot FDT Overlay FIT usage
+============================
+
+Introduction
+------------
+In many cases it is desirable to have a single FIT image support a multitude
+of similar boards and their expansion options. The same kernel on DT enabled
+platforms can support this easily enough by providing a DT blob upon boot
+that matches the desired configuration.
+
+This document focuses on specifically using overlays as part of a FIT image.
+General information regarding overlays including its syntax and building it
+can be found in doc/README.fdt-overlays
+
+Configuration without overlays
+------------------------------
+
+Take a hypothetical board named 'foo' where there are different supported
+revisions, reva and revb. Assume that both board revisions can use add a bar
+add-on board, while only the revb board can use a baz add-on board.
+
+Without using overlays the configuration would be as follows for every case.
+
+ /dts-v1/;
+ / {
+ images {
+ kernel@1 {
+ data = /incbin/("./zImage");
+ type = "kernel";
+ arch = "arm";
+ os = "linux";
+ load = <0x82000000>;
+ entry = <0x82000000>;
+ };
+ fdt@1 {
+ data = /incbin/("./foo-reva.dtb");
+ type = "flat_dt";
+ arch = "arm";
+ };
+ fdt@2 {
+ data = /incbin/("./foo-revb.dtb");
+ type = "flat_dt";
+ arch = "arm";
+ };
+ fdt@3 {
+ data = /incbin/("./foo-reva-bar.dtb");
+ type = "flat_dt";
+ arch = "arm";
+ };
+ fdt@4 {
+ data = /incbin/("./foo-revb-bar.dtb");
+ type = "flat_dt";
+ arch = "arm";
+ };
+ fdt@5 {
+ data = /incbin/("./foo-revb-baz.dtb");
+ type = "flat_dt";
+ arch = "arm";
+ };
+ fdt@6 {
+ data = /incbin/("./foo-revb-bar-baz.dtb");
+ type = "flat_dt";
+ arch = "arm";
+ };
+ };
+
+ configurations {
+ default = "foo-reva.dtb;
+ foo-reva.dtb {
+ kernel = "kernel@1";
+ fdt = "fdt@1";
+ };
+ foo-revb.dtb {
+ kernel = "kernel@1";
+ fdt = "fdt@2";
+ };
+ foo-reva-bar.dtb {
+ kernel = "kernel@1";
+ fdt = "fdt@3";
+ };
+ foo-revb-bar.dtb {
+ kernel = "kernel@1";
+ fdt = "fdt@4";
+ };
+ foo-revb-baz.dtb {
+ kernel = "kernel@1";
+ fdt = "fdt@5";
+ };
+ foo-revb-bar-baz.dtb {
+ kernel = "kernel@1";
+ fdt = "fdt@6";
+ };
+ };
+ };
+
+Note the blob needs to be compiled for each case and the combinatorial explosion of
+configurations. A typical device tree blob is in the low hunderds of kbytes so a
+multitude of configuration grows the image quite a bit.
+
+Booting this image is done by using
+
+ # bootm <addr>#<config>
+
+Where config is one of:
+ foo-reva.dtb, foo-revb.dtb, foo-reva-bar.dtb, foo-revb-bar.dtb,
+ foo-revb-baz.dtb, foo-revb-bar-baz.dtb
+
+This selects the DTB to use when booting.
+
+Configuration using overlays
+----------------------------
+
+Device tree overlays can be applied to a base DT and result in the same blob
+being passed to the booting kernel. This saves on space and avoid the combinatorial
+explosion problem.
+
+ /dts-v1/;
+ / {
+ images {
+ kernel@1 {
+ data = /incbin/("./zImage");
+ type = "kernel";
+ arch = "arm";
+ os = "linux";
+ load = <0x82000000>;
+ entry = <0x82000000>;
+ };
+ fdt@1 {
+ data = /incbin/("./foo.dtb");
+ type = "flat_dt";
+ arch = "arm";
+ load = <0x87f00000>;
+ };
+ fdt@2 {
+ data = /incbin/("./reva.dtbo");
+ type = "flat_dt";
+ arch = "arm";
+ load = <0x87fc0000>;
+ };
+ fdt@3 {
+ data = /incbin/("./revb.dtbo");
+ type = "flat_dt";
+ arch = "arm";
+ load = <0x87fc0000>;
+ };
+ fdt@4 {
+ data = /incbin/("./bar.dtbo");
+ type = "flat_dt";
+ arch = "arm";
+ load = <0x87fc0000>;
+ };
+ fdt@5 {
+ data = /incbin/("./baz.dtbo");
+ type = "flat_dt";
+ arch = "arm";
+ load = <0x87fc0000>;
+ };
+ };
+
+ configurations {
+ default = "foo-reva.dtb;
+ foo-reva.dtb {
+ kernel = "kernel@1";
+ fdt = "fdt@1", "fdt@2";
+ };
+ foo-revb.dtb {
+ kernel = "kernel@1";
+ fdt = "fdt@1", "fdt@3";
+ };
+ foo-reva-bar.dtb {
+ kernel = "kernel@1";
+ fdt = "fdt@1", "fdt@2", "fdt@4";
+ };
+ foo-revb-bar.dtb {
+ kernel = "kernel@1";
+ fdt = "fdt@1", "fdt@3", "fdt@4";
+ };
+ foo-revb-baz.dtb {
+ kernel = "kernel@1";
+ fdt = "fdt@1", "fdt@3", "fdt@5";
+ };
+ foo-revb-bar-baz.dtb {
+ kernel = "kernel@1";
+ fdt = "fdt@1", "fdt@3", "fdt@4", "fdt@5";
+ };
+ bar {
+ fdt = "fdt@4";
+ };
+ baz {
+ fdt = "fdt@5";
+ };
+ };
+ };
+
+Booting this image is exactly the same as the non-overlay example.
+u-boot will retrieve the base blob and apply the overlays in sequence as
+they are declared in the configuration.
+
+Note the minimum amount of different DT blobs, as well as the requirement for
+the DT blobs to have a load address; the overlay application requires the blobs
+to be writeable.
+
+Configuration using overlays and feature selection
+--------------------------------------------------
+
+Although the configuration in the previous section works is a bit inflexible
+since it requires all possible configuration options to be laid out before
+hand in the FIT image. For the add-on boards the extra config selection method
+might make sense.
+
+Note the two bar & baz configuration nodes. To boot a reva board with
+the bar add-on board enabled simply use:
+
+ # bootm <addr>#foo-reva.dtb#bar
+
+While booting a revb with bar and baz is as follows:
+
+ # bootm <addr>#foo-revb.dtb#bar#baz
+
+The limitation for a feature selection configuration node is that a single
+fdt option is currently supported.
+
+Pantelis Antoniou
+pantelis.antoniou@konsulko.com
+12/6/2017
|- description = "configuration description"
|- kernel = "kernel sub-node unit name"
|- ramdisk = "ramdisk sub-node unit name"
- |- fdt = "fdt sub-node unit-name"
+ |- fdt = "fdt sub-node unit-name" [, "fdt overlay sub-node unit-name", ...]
|- fpga = "fpga sub-node unit-name"
|- loadables = "loadables sub-node unit-name"
- ramdisk : Unit name of the corresponding ramdisk image (component image
node of a "ramdisk" type).
- fdt : Unit name of the corresponding fdt blob (component image node of a
- "fdt type").
+ "fdt type"). Additional fdt overlay nodes can be supplied which signify
+ that the resulting device tree blob is generated by the first base fdt
+ blob with all subsequent overlays applied.
- setup : Unit name of the corresponding setup binary (used for booting
an x86 kernel). This contains the setup.bin file built by the kernel.
- fpga : Unit name of the corresponding fpga bitstream blob
defines an absolute position or address as the offset. This is helpful when
booting U-Boot proper before performing relocation.
+Normal kernel FIT image has data embedded within FIT structure. U-Boot image
+for SPL boot has external data. Existence of 'data-offset' can be used to
+identify which format is used.
+
9) Examples
-----------
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
+#include <linux/dma-direction.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <malloc.h>
#endif
};
-enum dma_data_direction {
- DMA_BIDIRECTIONAL = 0,
- DMA_TO_DEVICE = 1,
- DMA_FROM_DEVICE = 2,
- DMA_NONE = 3,
-};
-
struct ata_link {
struct ata_port *ap;
int pmp;
if (IS_ERR_VALUE(n))
return n;
- /* flush cache after read */
- flush_cache((ulong)buffer, blkcnt * desc->blksz);
-
return n;
}
int blk_create_device(struct udevice *parent, const char *drv_name,
const char *name, int if_type, int devnum, int blksz,
- lbaint_t size, struct udevice **devp)
+ lbaint_t lba, struct udevice **devp)
{
struct blk_desc *desc;
struct udevice *dev;
desc = dev_get_uclass_platdata(dev);
desc->if_type = if_type;
desc->blksz = blksz;
- desc->lba = size / blksz;
+ desc->lba = lba;
desc->part_type = PART_TYPE_UNKNOWN;
desc->bdev = dev;
desc->devnum = devnum;
int blk_create_devicef(struct udevice *parent, const char *drv_name,
const char *name, int if_type, int devnum, int blksz,
- lbaint_t size, struct udevice **devp)
+ lbaint_t lba, struct udevice **devp)
{
char dev_name[30], *str;
int ret;
return -ENOMEM;
ret = blk_create_device(parent, drv_name, str, if_type, devnum,
- blksz, size, devp);
+ blksz, lba, devp);
if (ret) {
free(str);
return ret;
if (IS_ERR_VALUE(n))
return n;
- /* flush cache after read */
- flush_cache((ulong)buffer, blkcnt * desc->blksz);
-
return n;
}
}
ret = blk_create_device(gd->dm_root, "sandbox_host_blk", str,
IF_TYPE_HOST, devnum, 512,
- os_lseek(fd, 0, OS_SEEK_END), &dev);
+ os_lseek(fd, 0, OS_SEEK_END) / 512, &dev);
if (ret)
goto err_file;
ret = device_probe(dev);
(struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR;
/*
- * write RTC kick register to enable write
- * for RTC Scratch registers. Scratch0 and 1 are
- * used for bootcount values.
+ * write RTC kick registers to enable write
+ * for RTC Scratch registers. Scratch register 2 is
+ * used for bootcount value.
*/
writel(RTC_KICK0R_WE, ®->kick0r);
writel(RTC_KICK1R_WE, ®->kick1r);
config SPL_CLK
bool "Enable clock support in SPL"
- depends on CLK && SPL_DM
+ depends on CLK && SPL && SPL_DM
help
The clock subsystem adds a small amount of overhead to the image.
If this is acceptable and you have a need to use clock drivers in
config AT91_UTMI
bool "Support UTMI PLL Clock"
- depends on CLK_AT91
+ depends on CLK_AT91 && SPL_DM
+ select REGMAP
+ select SPL_REGMAP
+ select SYSCON
+ select SPL_SYSCON
help
This option is used to enable the AT91 UTMI PLL clock
driver. It is the clock provider of USB, and UPLLCK is the
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
+#include <syscon.h>
#include <linux/io.h>
#include <mach/at91_pmc.h>
+#include <mach/sama5_sfr.h>
#include "pmc.h"
DECLARE_GLOBAL_DATA_PTR;
-#define UTMI_FIXED_MUL 40
+/*
+ * The purpose of this clock is to generate a 480 MHz signal. A different
+ * rate can't be configured.
+ */
+#define UTMI_RATE 480000000
static int utmi_clk_enable(struct clk *clk)
{
struct pmc_platdata *plat = dev_get_platdata(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
+ struct clk clk_dev;
+ ulong clk_rate;
+ u32 utmi_ref_clk_freq;
u32 tmp;
+ int err;
if (readl(&pmc->sr) & AT91_PMC_LOCKU)
return 0;
+ /*
+ * If mainck rate is different from 12 MHz, we have to configure the
+ * FREQ field of the SFR_UTMICKTRIM register to generate properly
+ * the utmi clock.
+ */
+ err = clk_get_by_index(clk->dev, 0, &clk_dev);
+ if (err)
+ return -EINVAL;
+
+ clk_rate = clk_get_rate(&clk_dev);
+ switch (clk_rate) {
+ case 12000000:
+ utmi_ref_clk_freq = 0;
+ break;
+ case 16000000:
+ utmi_ref_clk_freq = 1;
+ break;
+ case 24000000:
+ utmi_ref_clk_freq = 2;
+ break;
+ /*
+ * Not supported on SAMA5D2 but it's not an issue since MAINCK
+ * maximum value is 24 MHz.
+ */
+ case 48000000:
+ utmi_ref_clk_freq = 3;
+ break;
+ default:
+ printf("UTMICK: unsupported mainck rate\n");
+ return -EINVAL;
+ }
+
+ if (plat->regmap_sfr) {
+ err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp);
+ if (err)
+ return -EINVAL;
+
+ tmp &= ~AT91_UTMICKTRIM_FREQ;
+ tmp |= utmi_ref_clk_freq;
+ err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp);
+ if (err)
+ return -EINVAL;
+ } else if (utmi_ref_clk_freq) {
+ printf("UTMICK: sfr node required\n");
+ return -EINVAL;
+ }
+
tmp = readl(&pmc->uckr);
tmp |= AT91_PMC_UPLLEN |
AT91_PMC_UPLLCOUNT |
static ulong utmi_clk_get_rate(struct clk *clk)
{
- return gd->arch.main_clk_rate_hz * UTMI_FIXED_MUL;
+ /* UTMI clk rate is fixed. */
+ return UTMI_RATE;
}
static struct clk_ops utmi_clk_ops = {
.get_rate = utmi_clk_get_rate,
};
+static int utmi_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct pmc_platdata *plat = dev_get_platdata(dev);
+ struct udevice *syscon;
+
+ uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+ "regmap-sfr", &syscon);
+
+ if (syscon)
+ plat->regmap_sfr = syscon_get_regmap(syscon);
+
+ return 0;
+}
+
static int utmi_clk_probe(struct udevice *dev)
{
return at91_pmc_core_probe(dev);
.id = UCLASS_CLK,
.of_match = utmi_clk_match,
.probe = utmi_clk_probe,
+ .ofdata_to_platdata = utmi_clk_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
.ops = &utmi_clk_ops,
};
#ifndef __AT91_PMC_H__
#define __AT91_PMC_H__
+#include <regmap.h>
+
struct pmc_platdata {
struct at91_pmc *reg_base;
+ struct regmap *regmap_sfr;
};
int at91_pmc_core_probe(struct udevice *dev);
#if CONFIG_IS_ENABLED(OF_CONTROL)
# if CONFIG_IS_ENABLED(OF_PLATDATA)
int clk_get_by_index_platdata(struct udevice *dev, int index,
- struct phandle_2_cell *cells, struct clk *clk)
+ struct phandle_1_arg *cells, struct clk *clk)
{
int ret;
ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
if (ret)
return ret;
- clk->id = cells[0].id;
+ clk->id = cells[0].arg[0];
return 0;
}
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3368_clk_plat *plat = dev_get_platdata(dev);
- priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
+ priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
rkclk_init(priv->cru);
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3368_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rk3368_cru *)devfdt_get_addr(dev);
+ priv->cru = dev_read_addr_ptr(dev);
#endif
return 0;
return ret;
}
+static int rk3399_clk_enable(struct clk *clk)
+{
+ switch (clk->id) {
+ case HCLK_HOST0:
+ case HCLK_HOST0_ARB:
+ case HCLK_HOST1:
+ case HCLK_HOST1_ARB:
+ return 0;
+ }
+
+ debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+}
+
static struct clk_ops rk3399_clk_ops = {
.get_rate = rk3399_clk_get_rate,
.set_rate = rk3399_clk_set_rate,
+ .enable = rk3399_clk_enable,
};
static int rk3399_clk_probe(struct udevice *dev)
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3399_clk_plat *plat = dev_get_platdata(dev);
- priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
+ priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
rkclk_init(priv->cru);
#endif
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3399_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rk3399_cru *)devfdt_get_addr(dev);
+ priv->cru = dev_read_addr_ptr(dev);
#endif
return 0;
}
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
- priv->pmucru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
+ priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
#ifndef CONFIG_SPL_BUILD
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
- priv->pmucru = (struct rk3399_pmucru *)devfdt_get_addr(dev);
+ priv->pmucru = dev_read_addr_ptr(dev);
#endif
return 0;
}
{
int i, is_last;
struct udevice *child;
- char class_name[12];
/* print the first 11 characters to not break the tree-format. */
- strlcpy(class_name, dev->uclass->uc_drv->name, sizeof(class_name));
- printf(" %-11s [ %c ] ", class_name,
- dev->flags & DM_FLAG_ACTIVATED ? '+' : ' ');
+ printf(" %-10.10s [ %c ] %-10.10s ", dev->uclass->uc_drv->name,
+ dev->flags & DM_FLAG_ACTIVATED ? '+' : ' ', dev->driver->name);
for (i = depth; i >= 0; i--) {
is_last = (last_flag >> i) & 1;
root = dm_root();
if (root) {
- printf(" Class Probed Name\n");
+ printf(" Class Probed Driver Name\n");
printf("----------------------------------------\n");
show_devices(root, -1, 0);
}
if (!ofnode_valid(timings))
return -EINVAL;
- for (i = 0, node = ofnode_first_subnode(timings);
- ofnode_valid(node) && i != index;
- node = ofnode_first_subnode(node))
- i++;
+ i = 0;
+ ofnode_for_each_subnode(node, timings) {
+ if (i++ == index)
+ break;
+ }
if (!ofnode_valid(node))
return -EINVAL;
return dev_read_addr_index(dev, 0);
}
+void *dev_read_addr_ptr(struct udevice *dev)
+{
+ fdt_addr_t addr = dev_read_addr(dev);
+
+ return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr;
+}
+
fdt_addr_t dev_read_addr_size(struct udevice *dev, const char *property,
fdt_size_t *sizep)
{
}
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-int regmap_init_mem_platdata(struct udevice *dev, u32 *reg, int count,
+int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count,
struct regmap **mapp)
{
struct regmap_range *range;
#endif
return dm_scan_fdt_node(gd->dm_root, blob, 0, pre_reloc_only);
}
+#else
+static int dm_scan_fdt_node(struct udevice *parent, const void *blob,
+ int offset, bool pre_reloc_only)
+{
+ return 0;
+}
#endif
+int dm_extended_scan_fdt(const void *blob, bool pre_reloc_only)
+{
+ int node, ret;
+
+ ret = dm_scan_fdt(gd->fdt_blob, pre_reloc_only);
+ if (ret) {
+ debug("dm_scan_fdt() failed: %d\n", ret);
+ return ret;
+ }
+
+ /* bind fixed-clock */
+ node = ofnode_to_offset(ofnode_path("/clocks"));
+ /* if no DT "clocks" node, no need to go further */
+ if (node < 0)
+ return ret;
+
+ ret = dm_scan_fdt_node(gd->dm_root, gd->fdt_blob, node,
+ pre_reloc_only);
+ if (ret)
+ debug("dm_scan_fdt_node() failed: %d\n", ret);
+
+ return ret;
+}
+
__weak int dm_scan_other(bool pre_reloc_only)
{
return 0;
}
if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) {
- ret = dm_scan_fdt(gd->fdt_blob, pre_reloc_only);
+ ret = dm_extended_scan_fdt(gd->fdt_blob, pre_reloc_only);
if (ret) {
- debug("dm_scan_fdt() failed: %d\n", ret);
+ debug("dm_extended_scan_dt() failed: %d\n", ret);
return ret;
}
}
void remove_unused_controllers(fsl_ddr_info_t *info)
{
-#ifdef CONFIG_FSL_LSCH3
+#ifdef CONFIG_SYS_FSL_HAS_CCN504
int i;
u64 nodeid;
void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
char *end;
int ret;
- /* This only supports RK3288 at present */
- priv->regs = (struct rockchip_gpio_regs *)devfdt_get_addr(dev);
+ priv->regs = dev_read_addr_ptr(dev);
ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
if (ret)
return ret;
/*
* Copyright (C) 2015 - 2016 Xilinx, Inc.
+ * Copyright (C) 2017 National Instruments Corp
* Written by Michal Simek
*
* SPDX-License-Identifier: GPL-2.0+
#include <dm.h>
#include <errno.h>
#include <i2c.h>
-#include <asm/gpio.h>
+
+#include <asm-generic/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
struct pca954x_priv {
u32 addr; /* I2C mux address */
u32 width; /* I2C mux width - number of busses */
+ struct gpio_desc gpio_mux_reset;
};
static const struct chip_desc chips[] = {
return 0;
}
+static int pca954x_probe(struct udevice *dev)
+{
+ if (IS_ENABLED(CONFIG_DM_GPIO)) {
+ struct pca954x_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = gpio_request_by_name(dev, "reset-gpios", 0,
+ &priv->gpio_mux_reset, GPIOD_IS_OUT);
+
+ /* it's optional so only bail if we get a real error */
+ if (err && (err != -ENOENT))
+ return err;
+
+ /* dm will take care of polarity */
+ if (dm_gpio_is_valid(&priv->gpio_mux_reset))
+ dm_gpio_set_value(&priv->gpio_mux_reset, 0);
+ }
+
+ return 0;
+}
+
+static int pca954x_remove(struct udevice *dev)
+{
+ if (IS_ENABLED(CONFIG_DM_GPIO)) {
+ struct pca954x_priv *priv = dev_get_priv(dev);
+
+ if (dm_gpio_is_valid(&priv->gpio_mux_reset))
+ dm_gpio_free(dev, &priv->gpio_mux_reset);
+ }
+
+ return 0;
+}
+
U_BOOT_DRIVER(pca954x) = {
.name = "pca954x",
.id = UCLASS_I2C_MUX,
.of_match = pca954x_ids,
+ .probe = pca954x_probe,
+ .remove = pca954x_remove,
.ops = &pca954x_ops,
.ofdata_to_platdata = pca954x_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct pca954x_priv),
{
struct rk_i2c *priv = dev_get_priv(bus);
- priv->regs = (void *)devfdt_get_addr(bus);
+ priv->regs = dev_read_addr_ptr(bus);
return 0;
}
help
Enable a generic driver for EEPROMs attached via I2C.
+
+config SPL_I2C_EEPROM
+ bool "Enable driver for generic I2C-attached EEPROMs for SPL"
+ depends on MISC && SPL && SPL_DM
+ help
+ This option is an SPL-variant of the I2C_EEPROM option.
+ See the help of I2C_EEPROM for details.
+
if I2C_EEPROM
config SYS_I2C_EEPROM_ADDR
endif
obj-$(CONFIG_FSL_IIM) += fsl_iim.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
-obj-$(CONFIG_I2C_EEPROM) += i2c_eeprom.o
+obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
config->flash_erase_value = ofnode_read_s32_default(flash_node,
"erase-value", -1);
- for (node = ofnode_first_subnode(flash_node); ofnode_valid(node);
- node = ofnode_next_subnode(node)) {
+ ofnode_for_each_subnode(node, flash_node) {
const char *name = ofnode_get_name(node);
enum ec_flash_region region;
static const struct udevice_id i2c_eeprom_std_ids[] = {
{ .compatible = "i2c-eeprom", .data = 0 },
+ { .compatible = "microchip,24aa02e48", .data = 3 },
{ .compatible = "atmel,24c01a", .data = 3 },
{ .compatible = "atmel,24c02", .data = 3 },
{ .compatible = "atmel,24c04", .data = 4 },
{ .compatible = "atmel,24c08a", .data = 4 },
{ .compatible = "atmel,24c16a", .data = 4 },
+ { .compatible = "atmel,24mac402", .data = 4 },
{ .compatible = "atmel,24c32", .data = 5 },
{ .compatible = "atmel,24c64", .data = 5 },
{ .compatible = "atmel,24c128", .data = 6 },
{
struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
- plat->base = (void *)dev_read_addr(dev);
+ plat->base = dev_read_addr_ptr(dev);
return 0;
}
struct dwmci_host *host = &priv->host;
host->name = dev->name;
- host->ioaddr = (void *)devfdt_get_addr(dev);
+ host->ioaddr = dev_read_addr_ptr(dev);
host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
host->priv = dev;
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
-#include <fdtdec.h>
#include <libfdt.h>
#include <malloc.h>
#include <mapmem.h>
struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat;
host->name = dev->name;
- host->ioaddr = map_sysmem(dtplat->reg[1], dtplat->reg[3]);
+ host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
max_frequency = dtplat->max_frequency;
ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk);
#else
struct sdhci_host *host = dev_get_priv(dev);
host->name = dev->name;
- host->ioaddr = devfdt_get_addr_ptr(dev);
+ host->ioaddr = dev_read_addr_ptr(dev);
#endif
return 0;
#include <mmc.h>
#include <dm.h>
#include <linux/compat.h>
+#include <linux/dma-direction.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <asm/unaligned.h>
-#include <asm/dma-mapping.h>
DECLARE_GLOBAL_DATA_PTR;
#include <malloc.h>
#include <nand.h>
#include <linux/errno.h>
-#include <asm/io.h>
+#include <linux/io.h>
#include "denali.h"
*/
static void detect_max_banks(struct denali_nand_info *denali)
{
- uint32_t features = readl(denali->flash_reg + FEATURES);
- /*
- * Read the revision register, so we can calculate the max_banks
- * properly: the encoding changed from rev 5.0 to 5.1
- */
- u32 revision = MAKE_COMPARABLE_REVISION(
- readl(denali->flash_reg + REVISION));
- if (revision < REVISION_5_1)
- denali->max_banks = 2 << (features & FEATURES__N_BANKS);
- else
- denali->max_banks = 1 << (features & FEATURES__N_BANKS);
+ uint32_t features = ioread32(denali->flash_reg + FEATURES);
+
+ denali->max_banks = 1 << (features & FEATURES__N_BANKS);
+
+ /* the encoding changed from rev 5.0 to 5.1 */
+ if (denali->revision < 0x0501)
+ denali->max_banks <<= 1;
}
static void detect_partition_feature(struct denali_nand_info *denali)
/* Initialization code to bring the device up to a known good state */
static void denali_hw_init(struct denali_nand_info *denali)
{
+ /*
+ * The REVISION register may not be reliable. Platforms are allowed to
+ * override it.
+ */
+ if (!denali->revision)
+ denali->revision = swab16(ioread32(denali->flash_reg + REVISION));
+
/*
* tell driver how many bit controller will skip before writing
* ECC code in OOB. This is normally used for bad block marker
#define REVISION 0x370
#define REVISION__VALUE 0xffff
-#define MAKE_COMPARABLE_REVISION(x) swab16((x) & REVISION__VALUE)
-#define REVISION_5_1 0x00000501
#define ONFI_DEVICE_FEATURES 0x380
#define ONFI_DEVICE_FEATURES__VALUE 0x003f
uint32_t blksperchip;
uint32_t bbtskipbytes;
uint32_t max_banks;
+ unsigned int revision;
+ unsigned int caps;
};
+#define DENALI_CAP_HW_ECC_FIXUP BIT(0)
+#define DENALI_CAP_DMA_64BIT BIT(1)
+
int denali_init(struct denali_nand_info *denali);
#endif /* __DENALI_H__ */
#include "denali.h"
+struct denali_dt_data {
+ unsigned int revision;
+ unsigned int caps;
+};
+
+static const struct denali_dt_data denali_socfpga_data = {
+ .caps = DENALI_CAP_HW_ECC_FIXUP,
+};
+
+static const struct denali_dt_data denali_uniphier_v5a_data = {
+ .caps = DENALI_CAP_HW_ECC_FIXUP |
+ DENALI_CAP_DMA_64BIT,
+};
+
+static const struct denali_dt_data denali_uniphier_v5b_data = {
+ .revision = 0x0501,
+ .caps = DENALI_CAP_HW_ECC_FIXUP |
+ DENALI_CAP_DMA_64BIT,
+};
+
static const struct udevice_id denali_nand_dt_ids[] = {
{
.compatible = "altr,socfpga-denali-nand",
+ .data = (unsigned long)&denali_socfpga_data,
},
{
.compatible = "socionext,uniphier-denali-nand-v5a",
+ .data = (unsigned long)&denali_uniphier_v5a_data,
},
{
.compatible = "socionext,uniphier-denali-nand-v5b",
+ .data = (unsigned long)&denali_uniphier_v5b_data,
},
{ /* sentinel */ }
};
static int denali_dt_probe(struct udevice *dev)
{
struct denali_nand_info *denali = dev_get_priv(dev);
+ const struct denali_dt_data *data;
struct resource res;
int ret;
+ data = (void *)dev_get_driver_data(dev);
+ if (data) {
+ denali->revision = data->revision;
+ denali->caps = data->caps;
+ }
+
ret = dev_read_resource_byname(dev, "denali_reg", &res);
if (ret)
return ret;
{"mx25l51235f", INFO(0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) },
{"mx25u6435f", INFO(0xc22537, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP) },
{"mx25l12855e", INFO(0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) },
+ {"mx25u1635e", INFO(0xc22535, 0x0, 64 * 1024, 32, SECT_4K) },
{"mx66u51235f", INFO(0xc2253a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) },
{"mx66l1g45g", INFO(0xc2201b, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP) },
#endif
#endif
struct eth_pdata *pdata = &dw_pdata->eth_pdata;
const char *phy_mode;
- const fdt32_t *cell;
#ifdef CONFIG_DM_GPIO
int reset_flags = GPIOD_IS_OUT;
#endif
int ret = 0;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
- NULL);
+ phy_mode = dev_read_string(dev, "phy-mode");
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
return -EINVAL;
}
- pdata->max_speed = 0;
- cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
- if (cell)
- pdata->max_speed = fdt32_to_cpu(*cell);
+ pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
#ifdef CONFIG_DM_GPIO
if (dev_read_bool(dev, "snps,reset-active-low"))
mmc_init(mmc);
(void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
addr);
- /* flush cache after read */
- flush_cache((ulong)addr, cnt * 512);
}
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
return mc_dpl_applied;
}
-/**
+/*
* Return the MC address of private DRAM block.
+ * As per MC design document, MC initial base address
+ * should be least significant 512MB address of MC private
+ * memory, i.e. address should point to end address masked
+ * with 512MB offset in private DRAM block.
*/
u64 mc_get_dram_addr(void)
{
- return gd->arch.resv_ram;
+ size_t mc_ram_size = mc_get_dram_block_size();
+
+ return (gd->arch.resv_ram + mc_ram_size - 1) &
+ MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
}
/**
writel (FTMAC100_MACCR_SW_RST, &ftmac100->maccr);
while (readl (&ftmac100->maccr) & FTMAC100_MACCR_SW_RST)
- ;
+ mdelay(1);
+ /*
+ * When soft reset complete, write mac address immediately maybe fail somehow
+ * Wait for a while can avoid this problem
+ */
+ mdelay(1);
}
/*
struct ftmac100_rxdes *rxdes = priv->rxdes;
unsigned int maccr;
int i;
-
debug ("%s()\n", __func__);
ftmac100_reset(priv);
unsigned short rxlen;
curr_des = &priv->rxdes[priv->rx_index];
-
if (curr_des->rxdes0 & FTMAC100_RXDES0_RXDMA_OWN)
return 0;
}
rxlen = FTMAC100_RXDES0_RFL (curr_des->rxdes0);
-
+ invalidate_dcache_range(curr_des->rxdes2,curr_des->rxdes2+rxlen);
debug ("%s(): RX buffer %d, %x received\n",
__func__, priv->rx_index, rxlen);
/* initiate a transmit sequence */
+ flush_dcache_range((u32)packet,(u32)packet+length);
curr_des->txdes2 = (unsigned int)packet; /* TXBUF_BADR */
curr_des->txdes1 &= FTMAC100_TXDES1_EDOTR;
obj-y += ldpaa_wriop.o
obj-y += ldpaa_eth.o
obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o
+obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o
}
}
+void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if)
+{
+ dpmac_info[dpmac_id].enabled = 1;
+ dpmac_info[dpmac_id].id = dpmac_id;
+ dpmac_info[dpmac_id].phy_addr = -1;
+ dpmac_info[dpmac_id].enet_if = enet_if;
+}
+
+
/*TODO what it do */
static int wriop_dpmac_to_index(int dpmac_id)
{
--- /dev/null
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <phy.h>
+#include <fsl-mc/ldpaa_wriop.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+
+u32 dpmac_to_devdisr[] = {
+ [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
+ [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
+ [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
+ [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
+ [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
+ [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
+ [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
+ [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
+ [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
+ [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
+};
+
+static int is_device_disabled(int dpmac_id)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 devdisr2 = in_le32(&gur->devdisr2);
+
+ return dpmac_to_devdisr[dpmac_id] & devdisr2;
+}
+
+void wriop_dpmac_disable(int dpmac_id)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
+}
+
+void wriop_dpmac_enable(int dpmac_id)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
+}
+
+phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
+{
+ enum srds_prtcl;
+
+ if (is_device_disabled(dpmac_id + 1))
+ return PHY_INTERFACE_MODE_NONE;
+
+ switch (lane_prtcl) {
+ case SGMII1:
+ case SGMII2:
+ case SGMII3:
+ case SGMII7:
+ return PHY_INTERFACE_MODE_SGMII;
+ }
+
+ if (lane_prtcl >= XFI1 && lane_prtcl <= XFI2)
+ return PHY_INTERFACE_MODE_XGMII;
+
+ if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_B)
+ return PHY_INTERFACE_MODE_QSGMII;
+
+ return PHY_INTERFACE_MODE_NONE;
+}
+
+void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
+{
+ switch (lane_prtcl) {
+ case QSGMII_A:
+ wriop_init_dpmac(sd, 3, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 4, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 5, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 6, (int)lane_prtcl);
+ break;
+ case QSGMII_B:
+ wriop_init_dpmac(sd, 7, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 8, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 9, (int)lane_prtcl);
+ wriop_init_dpmac(sd, 10, (int)lane_prtcl);
+ break;
+ }
+}
+
+#ifdef CONFIG_SYS_FSL_HAS_RGMII
+void fsl_rgmii_init(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 ec;
+
+#ifdef CONFIG_SYS_FSL_EC1
+ ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
+ & FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK;
+ ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
+
+ if (!ec)
+ wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII);
+#endif
+
+#ifdef CONFIG_SYS_FSL_EC2
+ ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
+ & FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK;
+ ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;
+
+ if (!ec)
+ wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII);
+#endif
+}
+#endif
mmc_init(mmc);
(void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
addr);
- /* flush cache after read */
- flush_cache((ulong)addr, cnt * 512);
}
#endif
* (C) Copyright 2017 Adaptrum, Inc.
* Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
*/
+
#include <config.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <fdtdec.h>
#include <micrel.h>
#include <phy.h>
return -EOPNOTSUPP;
for (i = 0; i < ofcfg->grpsz; i++) {
- val[i] = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
- ofcfg->grp[i].name, -1);
+ val[i] = dev_read_u32_default(dev, ofcfg->grp[i].name, ~0);
offset = ofcfg->grp[i].off;
if (val[i] == -1) {
/* Default register value for KSZ9021 */
#include <common.h>
#include <dm.h>
#include <dm/pinctrl.h>
+#include <asm/hardware.h>
#include <linux/io.h>
#include <linux/err.h>
#include <mach/at91_pio.h>
u32 cell[3];
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
- "interrupts", cell, ARRAY_SIZE(cell));
+ ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
if (ret < 0)
return -EINVAL;
}
#endif
-int palmas_mmc1_poweron_ldo(uint voltage)
+int palmas_mmc1_poweron_ldo(uint ldo_volt, uint ldo_ctrl, uint voltage)
{
u8 val = 0;
#if defined(CONFIG_DRA7XX)
int ret;
- /*
- * Currently valid for the dra7xx_evm board:
- * Set TPS659038 LDO1 to 3.0 V or 1.8V
- */
- ret = palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_VOLTAGE, voltage);
+
+ ret = palmas_i2c_write_u8(TPS65903X_CHIP_P1, ldo_volt, voltage);
if (ret) {
printf("tps65903x: could not set LDO1 voltage.\n");
return ret;
}
/* TURN ON LDO1 */
val = RSC_MODE_SLEEP | RSC_MODE_ACTIVE;
- ret = palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_CTRL, val);
+ ret = palmas_i2c_write_u8(TPS65903X_CHIP_P1, ldo_ctrl, val);
if (ret) {
printf("tps65903x: could not turn on LDO1.\n");
return ret;
debug("%s for '%s' at node offset: %d\n", __func__, pmic->name,
dev_of_offset(pmic));
- for (node = ofnode_first_subnode(parent);
- ofnode_valid(node);
- node = ofnode_next_subnode(node)) {
+ ofnode_for_each_subnode(node, parent) {
node_name = ofnode_get_name(node);
debug("* Found child node: '%s'\n", node_name);
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <fdtdec.h>
-#include <libfdt.h>
#include <power/rk8xx_pmic.h>
#include <power/pmic.h>
mmc_init(mmc);
(void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
addr);
- /* flush cache after read */
- flush_cache((ulong)addr, cnt * 512);
}
#endif
- u_qe_upload_firmware(addr);
- out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+ if (!u_qe_upload_firmware(addr))
+ out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
free(addr);
#endif
{
struct rk3368_sdram_params *plat = dev_get_platdata(dev);
struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
- int ret;
plat->ddr_freq = of_plat->rockchip_ddr_frequency;
plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
plat->memory_schedule = of_plat->rockchip_memory_schedule;
- ret = regmap_init_mem_platdata(dev, of_plat->reg,
- ARRAY_SIZE(of_plat->reg) / 2,
- &plat->map);
- if (ret)
- return ret;
-
return 0;
}
#endif
debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
#ifdef CONFIG_TPL_BUILD
- pctl = regmap_get_range(plat->map, 0);
- ddrphy = regmap_get_range(plat->map, 1);
+ pctl = (struct rk3368_ddr_pctl *)plat->of_plat.reg[0];
+ ddrphy = (struct rk3368_ddrphy *)plat->of_plat.reg[2];
msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
*/
snprintf(str, sizeof(str), "id%dlun%d", id, lun);
ret = blk_create_devicef(dev, "scsi_blk", str, IF_TYPE_SCSI, -1,
- bd.blksz, bd.blksz * bd.lba, &bdev);
+ bd.blksz, bd.lba, &bdev);
if (ret) {
debug("Can't create device\n");
return ret;
If you have a machine based on a Motorola IMX CPU you
can enable its onboard serial port by enabling this option.
+config NULLDEV_SERIAL
+ bool "Null serial device"
+ help
+ Select this to enable null serial device support. A null serial
+ device merely acts as a placeholder for a serial device and does
+ nothing for all it's operation.
+
config PIC32_SERIAL
bool "Support for Microchip PIC32 on-chip UART"
depends on DM_SERIAL && MACH_PIC32
obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
+obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
--- /dev/null
+/*
+ * Copyright (c) 2015 National Instruments
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <serial.h>
+
+static int nulldev_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ return 0;
+}
+
+static int nulldev_serial_getc(struct udevice *dev)
+{
+ return -EAGAIN;
+}
+
+static int nulldev_serial_input(struct udevice *dev)
+{
+ return 0;
+}
+
+static int nulldev_serial_putc(struct udevice *dev, const char ch)
+{
+ return 0;
+}
+
+static const struct udevice_id nulldev_serial_ids[] = {
+ { .compatible = "nulldev-serial" },
+ { }
+};
+
+
+const struct dm_serial_ops nulldev_serial_ops = {
+ .putc = nulldev_serial_putc,
+ .getc = nulldev_serial_getc,
+ .setbrg = nulldev_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_nulldev) = {
+ .name = "serial_nulldev",
+ .id = UCLASS_SERIAL,
+ .of_match = nulldev_serial_ids,
+ .ops = &nulldev_serial_ops,
+};
used to access the SPI NOR flash on platforms embedding this
Freescale IP core.
+config NDS_AE3XX_SPI
+ bool "Andestech AE3XX SPI driver"
+ help
+ Enable the Andestech AE3XX SPI driver. This driver can be
+ used to access the SPI flash on platforms embedding this
+ Andestech IP core.
+
config TI_QSPI
bool "TI QSPI driver"
help
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
+obj-$(CONFIG_NDS_AE3XX_SPI) += nds_ae3xx_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
--- /dev/null
+/*
+ * NDS SPI controller driver.
+ *
+ * Copyright 2017 Andes Technology, Inc.
+ * Author: Rick Chen (rick@andestech.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <dm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_TRANSFER_LEN 512
+#define CHUNK_SIZE 1
+#define SPI_TIMEOUT 0x100000
+#define SPI0_BUS 0
+#define SPI1_BUS 1
+#define SPI0_BASE 0xf0b00000
+#define SPI1_BASE 0xf0f00000
+#define NSPI_MAX_CS_NUM 1
+
+struct ae3xx_spi_regs {
+ u32 rev;
+ u32 reserve1[3];
+ u32 format; /* 0x10 */
+#define DATA_LENGTH(x) ((x-1)<<8)
+ u32 pio;
+ u32 reserve2[2];
+ u32 tctrl; /* 0x20 */
+#define TRAMODE_OFFSET 24
+#define TRAMODE_MASK (0x0F<<TRAMODE_OFFSET)
+#define TRAMODE_WR_SYNC (0<<TRAMODE_OFFSET)
+#define TRAMODE_WO (1<<TRAMODE_OFFSET)
+#define TRAMODE_RO (2<<TRAMODE_OFFSET)
+#define TRAMODE_WR (3<<TRAMODE_OFFSET)
+#define TRAMODE_RW (4<<TRAMODE_OFFSET)
+#define TRAMODE_WDR (5<<TRAMODE_OFFSET)
+#define TRAMODE_RDW (6<<TRAMODE_OFFSET)
+#define TRAMODE_NONE (7<<TRAMODE_OFFSET)
+#define TRAMODE_DW (8<<TRAMODE_OFFSET)
+#define TRAMODE_DR (9<<TRAMODE_OFFSET)
+#define WCNT_OFFSET 12
+#define WCNT_MASK (0x1FF<<WCNT_OFFSET)
+#define RCNT_OFFSET 0
+#define RCNT_MASK (0x1FF<<RCNT_OFFSET)
+ u32 cmd;
+ u32 addr;
+ u32 data;
+ u32 ctrl; /* 0x30 */
+#define TXFTH_OFFSET 16
+#define RXFTH_OFFSET 8
+#define TXDMAEN (1<<4)
+#define RXDMAEN (1<<3)
+#define TXFRST (1<<2)
+#define RXFRST (1<<1)
+#define SPIRST (1<<0)
+ u32 status;
+#define TXFFL (1<<23)
+#define TXEPTY (1<<22)
+#define TXFVE_MASK (0x1F<<16)
+#define RXFEM (1<<14)
+#define RXFVE_OFFSET (8)
+#define RXFVE_MASK (0x1F<<RXFVE_OFFSET)
+#define SPIBSY (1<<0)
+ u32 inten;
+ u32 intsta;
+ u32 timing; /* 0x40 */
+#define SCLK_DIV_MASK 0xFF
+};
+
+struct nds_spi_slave {
+#ifndef CONFIG_DM_SPI
+ struct spi_slave slave;
+#endif
+ volatile struct ae3xx_spi_regs *regs;
+ int to;
+ unsigned int freq;
+ ulong clock;
+ unsigned int mode;
+ u8 num_cs;
+ unsigned int mtiming;
+ size_t cmd_len;
+ u8 cmd_buf[16];
+ size_t data_len;
+ size_t tran_len;
+ u8 *din;
+ u8 *dout;
+ unsigned int max_transfer_length;
+};
+
+static int __ae3xx_spi_set_speed(struct nds_spi_slave *ns)
+{
+ u32 tm;
+ u8 div;
+ tm = ns->regs->timing;
+ tm &= ~SCLK_DIV_MASK;
+
+ if(ns->freq >= ns->clock)
+ div =0xff;
+ else{
+ for (div = 0; div < 0xff; div++) {
+ if (ns->freq >= ns->clock / (2 * (div + 1)))
+ break;
+ }
+ }
+
+ tm |= div;
+ ns->regs->timing = tm;
+
+ return 0;
+
+}
+
+static int __ae3xx_spi_claim_bus(struct nds_spi_slave *ns)
+{
+ unsigned int format=0;
+ ns->regs->ctrl |= (TXFRST|RXFRST|SPIRST);
+ while((ns->regs->ctrl &(TXFRST|RXFRST|SPIRST))&&(ns->to--))
+ if(!ns->to)
+ return -EINVAL;
+
+ ns->cmd_len = 0;
+ format = ns->mode|DATA_LENGTH(8);
+ ns->regs->format = format;
+ __ae3xx_spi_set_speed(ns);
+
+ return 0;
+}
+
+static int __ae3xx_spi_release_bus(struct nds_spi_slave *ns)
+{
+ /* do nothing */
+ return 0;
+}
+
+static int __ae3xx_spi_start(struct nds_spi_slave *ns)
+{
+ int i,olen=0;
+ int tc = ns->regs->tctrl;
+
+ tc &= ~(WCNT_MASK|RCNT_MASK|TRAMODE_MASK);
+ if ((ns->din)&&(ns->cmd_len))
+ tc |= TRAMODE_WR;
+ else if (ns->din)
+ tc |= TRAMODE_RO;
+ else
+ tc |= TRAMODE_WO;
+
+ if(ns->dout)
+ olen = ns->tran_len;
+ tc |= (ns->cmd_len+olen-1) << WCNT_OFFSET;
+
+ if(ns->din)
+ tc |= (ns->tran_len-1) << RCNT_OFFSET;
+
+ ns->regs->tctrl = tc;
+ ns->regs->cmd = 1;
+
+ for (i=0;i<ns->cmd_len;i++)
+ ns->regs->data = ns->cmd_buf[i];
+
+ return 0;
+}
+
+static int __ae3xx_spi_stop(struct nds_spi_slave *ns)
+{
+ ns->regs->timing = ns->mtiming;
+ while ((ns->regs->status & SPIBSY)&&(ns->to--))
+ if (!ns->to)
+ return -EINVAL;
+
+ return 0;
+}
+
+static void __nspi_espi_tx(struct nds_spi_slave *ns, const void *dout)
+{
+ ns->regs->data = *(u8 *)dout;
+}
+
+static int __nspi_espi_rx(struct nds_spi_slave *ns, void *din, unsigned int bytes)
+{
+ *(u8 *)din = ns->regs->data;
+ return bytes;
+}
+
+
+static int __ae3xx_spi_xfer(struct nds_spi_slave *ns,
+ unsigned int bitlen, const void *data_out, void *data_in,
+ unsigned long flags)
+{
+ unsigned int event, rx_bytes;
+ const void *dout = NULL;
+ void *din = NULL;
+ int num_blks, num_chunks, max_tran_len, tran_len;
+ int num_bytes;
+ u8 *cmd_buf = ns->cmd_buf;
+ size_t cmd_len = ns->cmd_len;
+ size_t data_len = bitlen / 8;
+ int rf_cnt;
+ int ret = 0;
+
+ max_tran_len = ns->max_transfer_length;
+ switch (flags) {
+ case SPI_XFER_BEGIN:
+ cmd_len = ns->cmd_len = data_len;
+ memcpy(cmd_buf, data_out, cmd_len);
+ return 0;
+
+ case 0:
+ case SPI_XFER_END:
+ if (bitlen == 0) {
+ return 0;
+ }
+ ns->data_len = data_len;
+ ns->din = (u8 *)data_in;
+ ns->dout = (u8 *)data_out;
+ break;
+
+ case SPI_XFER_BEGIN | SPI_XFER_END:
+ ns->data_len = 0;
+ ns->din = 0;
+ ns->dout = 0;
+ cmd_len = ns->cmd_len = data_len;
+ memcpy(cmd_buf, data_out, cmd_len);
+ data_out = 0;
+ data_len = 0;
+ __ae3xx_spi_start(ns);
+ break;
+ }
+ debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) data_len %u\n",
+ *(uint *)data_out, data_out, *(uint *)data_in, data_in, data_len);
+ num_chunks = DIV_ROUND_UP(data_len, max_tran_len);
+ din = data_in;
+ dout = data_out;
+ while (num_chunks--) {
+ tran_len = min(data_len, (size_t)max_tran_len);
+ ns->tran_len = tran_len;
+ num_blks = DIV_ROUND_UP(tran_len , CHUNK_SIZE);
+ num_bytes = (tran_len) % CHUNK_SIZE;
+ if(num_bytes == 0)
+ num_bytes = CHUNK_SIZE;
+ __ae3xx_spi_start(ns);
+
+ while (num_blks) {
+ event = in_le32(&ns->regs->status);
+ if ((event & TXEPTY) && (data_out)) {
+ __nspi_espi_tx(ns, dout);
+ num_blks -= CHUNK_SIZE;
+ dout += CHUNK_SIZE;
+ }
+
+ if ((event & RXFVE_MASK) && (data_in)) {
+ rf_cnt = ((event & RXFVE_MASK)>> RXFVE_OFFSET);
+ if (rf_cnt >= CHUNK_SIZE)
+ rx_bytes = CHUNK_SIZE;
+ else if (num_blks == 1 && rf_cnt == num_bytes)
+ rx_bytes = num_bytes;
+ else
+ continue;
+
+ if (__nspi_espi_rx(ns, din, rx_bytes) == rx_bytes) {
+ num_blks -= CHUNK_SIZE;
+ din = (unsigned char *)din + rx_bytes;
+ }
+ }
+ }
+
+ data_len -= tran_len;
+ if(data_len)
+ {
+ ns->cmd_buf[1] += ((tran_len>>16)&0xff);
+ ns->cmd_buf[2] += ((tran_len>>8)&0xff);
+ ns->cmd_buf[3] += ((tran_len)&0xff);
+ ns->data_len = data_len;
+ }
+ ret = __ae3xx_spi_stop(ns);
+ }
+ ret = __ae3xx_spi_stop(ns);
+
+ return ret;
+}
+
+#ifndef CONFIG_DM_SPI
+#define to_nds_spi_slave(s) container_of(s, struct nds_spi_slave, slave)
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct nds_spi_slave *ns;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ ns = spi_alloc_slave(struct nds_spi_slave, bus, cs);
+
+ switch (bus) {
+ case SPI0_BUS:
+ ns->regs = (struct ae3xx_spi_regs *)SPI0_BASE;
+ break;
+
+ case SPI1_BUS:
+ ns->regs = (struct ae3xx_spi_regs *)SPI1_BASE;
+ break;
+
+ default:
+ return NULL;
+ }
+
+ ns->freq= max_hz;
+ ns->mode = mode;
+ ns->to = SPI_TIMEOUT;
+ ns->max_transfer_length = MAX_TRANSFER_LEN;
+ ns->slave.max_write_size = MAX_TRANSFER_LEN;
+ if (!ns)
+ return NULL;
+
+ return &ns->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct nds_spi_slave *ns = to_nds_spi_slave(slave);
+ free(ns);
+}
+
+void spi_init(void)
+{
+ /* do nothing */
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct nds_spi_slave *ns = to_nds_spi_slave(slave);
+ return __ae3xx_spi_claim_bus(ns);
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct nds_spi_slave *ns = to_nds_spi_slave(slave);
+ __ae3xx_spi_release_bus(ns);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
+ void *data_in, unsigned long flags)
+{
+ struct nds_spi_slave *ns = to_nds_spi_slave(slave);
+ return __ae3xx_spi_xfer(ns, bitlen, data_out, data_in, flags);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs < NSPI_MAX_CS_NUM;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct nds_spi_slave *ns = to_nds_spi_slave(slave);
+ __ae3xx_spi_start(ns);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct nds_spi_slave *ns = to_nds_spi_slave(slave);
+ __ae3xx_spi_stop(ns);
+}
+#else
+static int ae3xx_spi_set_speed(struct udevice *bus, uint max_hz)
+{
+ struct nds_spi_slave *ns = dev_get_priv(bus);
+
+ debug("%s speed %u\n", __func__, max_hz);
+
+ ns->freq = max_hz;
+ __ae3xx_spi_set_speed(ns);
+
+ return 0;
+}
+
+static int ae3xx_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct nds_spi_slave *ns = dev_get_priv(bus);
+
+ debug("%s mode %u\n", __func__, mode);
+ ns->mode = mode;
+
+ return 0;
+}
+
+static int ae3xx_spi_claim_bus(struct udevice *dev)
+{
+ struct dm_spi_slave_platdata *slave_plat =
+ dev_get_parent_platdata(dev);
+ struct udevice *bus = dev->parent;
+ struct nds_spi_slave *ns = dev_get_priv(bus);
+
+ if (slave_plat->cs >= ns->num_cs) {
+ printf("Invalid SPI chipselect\n");
+ return -EINVAL;
+ }
+
+ return __ae3xx_spi_claim_bus(ns);
+}
+
+static int ae3xx_spi_release_bus(struct udevice *dev)
+{
+ struct nds_spi_slave *ns = dev_get_priv(dev->parent);
+
+ return __ae3xx_spi_release_bus(ns);
+}
+
+static int ae3xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din,
+ unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct nds_spi_slave *ns = dev_get_priv(bus);
+
+ return __ae3xx_spi_xfer(ns, bitlen, dout, din, flags);
+}
+
+static int ae3xx_spi_get_clk(struct udevice *bus)
+{
+ struct nds_spi_slave *ns = dev_get_priv(bus);
+ struct clk clk;
+ ulong clk_rate;
+ int ret;
+
+ ret = clk_get_by_index(bus, 0, &clk);
+ if (ret)
+ return -EINVAL;
+
+ clk_rate = clk_get_rate(&clk);
+ if (!clk_rate)
+ return -EINVAL;
+
+ ns->clock = clk_rate;
+ clk_free(&clk);
+
+ return 0;
+}
+
+static int ae3xx_spi_probe(struct udevice *bus)
+{
+ struct nds_spi_slave *ns = dev_get_priv(bus);
+
+ ns->to = SPI_TIMEOUT;
+ ns->max_transfer_length = MAX_TRANSFER_LEN;
+ ns->mtiming = ns->regs->timing;
+ ae3xx_spi_get_clk(bus);
+
+ return 0;
+}
+
+static int ae3xx_ofdata_to_platadata(struct udevice *bus)
+{
+ struct nds_spi_slave *ns = dev_get_priv(bus);
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(bus);
+
+ ns->regs = map_physmem(devfdt_get_addr(bus),
+ sizeof(struct ae3xx_spi_regs),
+ MAP_NOCACHE);
+ if (!ns->regs) {
+ printf("%s: could not map device address\n", __func__);
+ return -EINVAL;
+ }
+ ns->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
+
+ return 0;
+}
+
+static const struct dm_spi_ops ae3xx_spi_ops = {
+ .claim_bus = ae3xx_spi_claim_bus,
+ .release_bus = ae3xx_spi_release_bus,
+ .xfer = ae3xx_spi_xfer,
+ .set_speed = ae3xx_spi_set_speed,
+ .set_mode = ae3xx_spi_set_mode,
+};
+
+static const struct udevice_id ae3xx_spi_ids[] = {
+ { .compatible = "andestech,atcspi200" },
+ { }
+};
+
+U_BOOT_DRIVER(ae3xx_spi) = {
+ .name = "ae3xx_spi",
+ .id = UCLASS_SPI,
+ .of_match = ae3xx_spi_ids,
+ .ops = &ae3xx_spi_ops,
+ .ofdata_to_platdata = ae3xx_ofdata_to_platadata,
+ .priv_auto_alloc_size = sizeof(struct nds_spi_slave),
+ .probe = ae3xx_spi_probe,
+};
+#endif
struct rockchip_spi_priv *priv = dev_get_priv(bus);
int ret;
- plat->base = devfdt_get_addr(bus);
+ plat->base = dev_read_addr(bus);
ret = clk_get_by_index(bus, 0, &priv->clk);
if (ret < 0) {
obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o
endif
obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o
+obj-$(CONFIG_ROCKCHIP_RK322X) += sysreset_rk322x.o
obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += sysreset_rk3368.o
#include <common.h>
#include <dm.h>
+#include <dm/ofnode.h>
#include <mapmem.h>
#include <asm/arch/timer.h>
#include <dt-structs.h>
struct rk_timer *timer;
};
-static int rockchip_timer_get_count(struct udevice *dev, u64 *count)
+static inline int64_t rockchip_timer_get_curr_value(struct rk_timer *timer)
{
- struct rockchip_timer_priv *priv = dev_get_priv(dev);
uint64_t timebase_h, timebase_l;
uint64_t cntr;
- timebase_l = readl(&priv->timer->timer_curr_value0);
- timebase_h = readl(&priv->timer->timer_curr_value1);
+ timebase_l = readl(&timer->timer_curr_value0);
+ timebase_h = readl(&timer->timer_curr_value1);
- /* timers are down-counting */
cntr = timebase_h << 32 | timebase_l;
+ return cntr;
+}
+
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
+ulong timer_get_boot_us(void)
+{
+ uint64_t ticks = 0;
+ uint32_t rate;
+ uint64_t us;
+ int ret;
+
+ ret = dm_timer_init();
+
+ if (!ret) {
+ /* The timer is available */
+ rate = timer_get_rate(gd->timer);
+ timer_get_count(gd->timer, &ticks);
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ } else if (ret == -EAGAIN) {
+ /* We have been called so early that the DM is not ready,... */
+ ofnode node = offset_to_ofnode(-1);
+ struct rk_timer *timer = NULL;
+
+ /*
+ * ... so we try to access the raw timer, if it is specified
+ * via the tick-timer property in /chosen.
+ */
+ node = ofnode_get_chosen_node("tick-timer");
+ if (!ofnode_valid(node)) {
+ debug("%s: no /chosen/tick-timer\n", __func__);
+ return 0;
+ }
+
+ timer = (struct rk_timer *)ofnode_get_addr(node);
+
+ /* This timer is down-counting */
+ ticks = ~0uLL - rockchip_timer_get_curr_value(timer);
+ if (ofnode_read_u32(node, "clock-frequency", &rate)) {
+ debug("%s: could not read clock-frequency\n", __func__);
+ return 0;
+ }
+#endif
+ } else {
+ return 0;
+ }
+
+ us = (ticks * 1000) / rate;
+ return us;
+}
+#endif
+
+static int rockchip_timer_get_count(struct udevice *dev, u64 *count)
+{
+ struct rockchip_timer_priv *priv = dev_get_priv(dev);
+ uint64_t cntr = rockchip_timer_get_curr_value(priv->timer);
+
+ /* timers are down-counting */
*count = ~0ull - cntr;
return 0;
}
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rockchip_timer_priv *priv = dev_get_priv(dev);
- priv->timer = (struct rk_timer *)devfdt_get_addr(dev);
+ priv->timer = dev_read_addr_ptr(dev);
+ if (!priv->timer)
+ return -ENOENT;
#endif
return 0;
const uint32_t reload_val_l = reload_val & 0xffffffff;
const uint32_t reload_val_h = reload_val >> 32;
+ /* don't reinit, if the timer is already running and set up */
+ if ((readl(&priv->timer->timer_ctrl_reg) & 1) == 1 &&
+ (readl(&priv->timer->timer_load_count0) == reload_val_l) &&
+ (readl(&priv->timer->timer_load_count1) == reload_val_h))
+ return 0;
+
/* disable timer and reset all control */
writel(0, &priv->timer->timer_ctrl_reg);
/* write reload value */
struct rockchip_timer_priv *priv = dev_get_priv(dev);
struct rockchip_timer_plat *plat = dev_get_platdata(dev);
- priv->timer = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
+ priv->timer = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
uc_priv->clock_rate = plat->dtd.clock_frequency;
#endif
#include <dm.h>
#include <dm/lists.h>
#include <dm/device-internal.h>
+#include <dm/root.h>
#include <clk.h>
#include <errno.h>
#include <timer.h>
if (IS_ERR_VALUE(ret))
return ret;
uc_priv->clock_rate = ret;
- } else
- uc_priv->clock_rate = fdtdec_get_int(gd->fdt_blob,
- dev_of_offset(dev), "clock-frequency", 0);
+ } else {
+ uc_priv->clock_rate =
+ dev_read_u32_default(dev, "clock-frequency", 0);
+ }
#endif
return 0;
int notrace dm_timer_init(void)
{
- __maybe_unused const void *blob = gd->fdt_blob;
struct udevice *dev = NULL;
- int node = -ENOENT;
+ __maybe_unused ofnode node;
int ret;
if (gd->timer)
return 0;
+ /*
+ * Directly access gd->dm_root to suppress error messages, if the
+ * virtual root driver does not yet exist.
+ */
+ if (gd->dm_root == NULL)
+ return -EAGAIN;
+
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
/* Check for a chosen timer to be used for tick */
- node = fdtdec_get_chosen_node(blob, "tick-timer");
+ node = ofnode_get_chosen_node("tick-timer");
+
+ if (ofnode_valid(node) &&
+ uclass_get_device_by_ofnode(UCLASS_TIMER, node, &dev)) {
+ /*
+ * If the timer is not marked to be bound before
+ * relocation, bind it anyway.
+ */
+ if (!lists_bind_fdt(dm_root(), node, &dev)) {
+ ret = device_probe(dev);
+ if (ret)
+ return ret;
+ }
+ }
#endif
- if (node < 0) {
- /* No chosen timer, trying first available timer */
+
+ if (!dev) {
+ /* Fall back to the first available timer */
ret = uclass_first_device_err(UCLASS_TIMER, &dev);
if (ret)
return ret;
- } else {
- if (uclass_get_device_by_of_offset(UCLASS_TIMER, node, &dev)) {
- /*
- * If the timer is not marked to be bound before
- * relocation, bind it anyway.
- */
- if (node > 0 &&
- !lists_bind_fdt(gd->dm_root, offset_to_ofnode(node),
- &dev)) {
- ret = device_probe(dev);
- if (ret)
- return ret;
- }
- }
}
if (dev) {
#include <asm/msr.h>
#include <asm/u-boot-x86.h>
-#define MAX_NUM_FREQS 8
+#define MAX_NUM_FREQS 9
DECLARE_GLOBAL_DATA_PTR;
static struct freq_desc freq_desc_tables[] = {
/* PNW */
- { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 } },
+ { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
/* CLV+ */
- { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },
+ { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
/* TNG - Intel Atom processor Z3400 series */
- { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },
+ { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
- { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },
+ { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
/* ANN - Intel Atom processor Z3500 series */
- { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } },
+ { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
+ /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
+ { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
+ 80000, 93300, 90000, 88900, 87500 } },
/* Ivybridge */
- { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
};
static int match_cpu(u8 family, u8 model)
return 0;
}
-static int tsc_timer_probe(struct udevice *dev)
+static void tsc_timer_ensure_setup(void)
{
- struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-
+ if (gd->arch.tsc_base)
+ return;
gd->arch.tsc_base = rdtsc();
/*
* If there is no clock frequency specified in the device tree,
* calibrate it by ourselves.
*/
- if (!uc_priv->clock_rate) {
+ if (!gd->arch.clock_rate) {
unsigned long fast_calibrate;
fast_calibrate = cpu_mhz_from_msr();
panic("TSC frequency is ZERO");
}
- uc_priv->clock_rate = fast_calibrate * 1000000;
+ gd->arch.clock_rate = fast_calibrate * 1000000;
}
+}
+
+static int tsc_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ tsc_timer_ensure_setup();
+ uc_priv->clock_rate = gd->arch.clock_rate;
return 0;
}
+unsigned long notrace timer_early_get_rate(void)
+{
+ tsc_timer_ensure_setup();
+
+ return gd->arch.clock_rate;
+}
+
+u64 notrace timer_early_get_count(void)
+{
+ return rdtsc() - gd->arch.tsc_base;
+}
+
static const struct timer_ops tsc_timer_ops = {
.get_count = tsc_timer_get_count,
};
#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
#include <div64.h>
#include "ipu.h"
#include "ipu_regs.h"
#define IPU_SW_RST_TOUT_USEC (10000)
+#define IPUV3_CLK_MX51 133000000
+#define IPUV3_CLK_MX53 200000000
+#define IPUV3_CLK_MX6Q 264000000
+#define IPUV3_CLK_MX6DL 198000000
+
void clk_enable(struct clk *clk)
{
if (clk) {
static struct clk ipu_clk = {
.name = "ipu_clk",
- .rate = CONFIG_IPUV3_CLK,
#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
.enable_reg = (u32 *)(CCM_BASE_ADDR +
offsetof(struct mxc_ccm_reg, CCGR5)),
g_pixel_clk[1] = &pixel_clk[1];
g_ipu_clk = &ipu_clk;
+#if defined(CONFIG_MX51)
+ g_ipu_clk->rate = IPUV3_CLK_MX51;
+#elif defined(CONFIG_MX53)
+ g_ipu_clk->rate = IPUV3_CLK_MX53;
+#else
+ g_ipu_clk->rate = is_mx6sdl() ? IPUV3_CLK_MX6DL : IPUV3_CLK_MX6Q;
+#endif
debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
g_ldb_clk = &ldb_clk;
debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
EXT_COBJ-y += lib/string.o
EXT_COBJ-y += lib/time.o
EXT_COBJ-y += lib/vsprintf.o
+EXT_COBJ-y += lib/charset.o
+EXT_COBJ-$(CONFIG_LIB_UUID) += lib/uuid.o
EXT_SOBJ-$(CONFIG_PPC) += arch/powerpc/lib/ppcstring.o
ifeq ($(ARCH),arm)
EXT_SOBJ-$(CONFIG_USE_ARCH_MEMSET) += arch/arm/lib/memset.o
{
syscall(API_DISPLAY_CLEAR, NULL);
}
+
+__weak void *memcpy(void *dest, const void *src, size_t size)
+{
+ unsigned char *dptr = dest;
+ const unsigned char *ptr = src;
+ const unsigned char *end = src + size;
+
+ while (ptr < end)
+ *dptr++ = *ptr++;
+
+ return dest;
+}
obj-$(CONFIG_FS_FAT) := fat.o
obj-$(CONFIG_FAT_WRITE):= fat_write.o
-
-ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_FS_FAT) += file.o
-endif
#include <config.h>
#include <exports.h>
#include <fat.h>
+#include <fs.h>
#include <asm/byteorder.h>
#include <part.h>
#include <malloc.h>
#endif
/*
- * Convert a string to lowercase.
+ * Convert a string to lowercase. Converts at most 'len' characters,
+ * 'len' may be larger than the length of 'str' if 'str' is NULL
+ * terminated.
*/
-static void downcase(char *str)
+static void downcase(char *str, size_t len)
{
- while (*str != '\0') {
+ while (*str != '\0' && len--) {
*str = tolower(*str);
str++;
}
return fat_set_blk_dev(dev_desc, &info);
}
-/*
- * Get the first occurence of a directory delimiter ('/' or '\') in a string.
- * Return index into string if found, -1 otherwise.
- */
-static int dirdelim(char *str)
-{
- char *start = str;
-
- while (*str != '\0') {
- if (ISDIRDELIM(*str))
- return str - start;
- str++;
- }
- return -1;
-}
-
/*
* Extract zero terminated short name from a directory entry.
*/
ptr = s_name;
while (*ptr && *ptr != ' ')
ptr++;
+ if (dirent->lcase & CASE_LOWER_BASE)
+ downcase(s_name, (unsigned)(ptr - s_name));
if (dirent->ext[0] && dirent->ext[0] != ' ') {
- *ptr = '.';
- ptr++;
+ *ptr++ = '.';
memcpy(ptr, dirent->ext, 3);
+ if (dirent->lcase & CASE_LOWER_EXT)
+ downcase(ptr, 3);
ptr[3] = '\0';
while (*ptr && *ptr != ' ')
ptr++;
*s_name = '\0';
else if (*s_name == aRING)
*s_name = DELETED_FLAG;
- downcase(s_name);
}
static int flush_dirty_fat_buffer(fsdata *mydata);
int ret;
if (clustnum > 0) {
- startsect = mydata->data_begin +
- clustnum * mydata->clust_size;
+ startsect = clust_to_sect(mydata, clustnum);
} else {
startsect = mydata->rootdir_sect;
}
return 0;
}
-/*
- * Extract the full long filename starting at 'retdent' (which is really
- * a slot) into 'l_name'. If successful also copy the real directory entry
- * into 'retdent'
- * Return 0 on success, -1 otherwise.
- */
-static int
-get_vfatname(fsdata *mydata, int curclust, __u8 *cluster,
- dir_entry *retdent, char *l_name)
-{
- dir_entry *realdent;
- dir_slot *slotptr = (dir_slot *)retdent;
- __u8 *buflimit = cluster + mydata->sect_size * ((curclust == 0) ?
- PREFETCH_BLOCKS :
- mydata->clust_size);
- __u8 counter = (slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff;
- int idx = 0;
-
- if (counter > VFAT_MAXSEQ) {
- debug("Error: VFAT name is too long\n");
- return -1;
- }
-
- while ((__u8 *)slotptr < buflimit) {
- if (counter == 0)
- break;
- if (((slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff) != counter)
- return -1;
- slotptr++;
- counter--;
- }
-
- if ((__u8 *)slotptr >= buflimit) {
- dir_slot *slotptr2;
-
- if (curclust == 0)
- return -1;
- curclust = get_fatent(mydata, curclust);
- if (CHECK_CLUST(curclust, mydata->fatsize)) {
- debug("curclust: 0x%x\n", curclust);
- printf("Invalid FAT entry\n");
- return -1;
- }
-
- if (get_cluster(mydata, curclust, get_contents_vfatname_block,
- mydata->clust_size * mydata->sect_size) != 0) {
- debug("Error: reading directory block\n");
- return -1;
- }
-
- slotptr2 = (dir_slot *)get_contents_vfatname_block;
- while (counter > 0) {
- if (((slotptr2->id & ~LAST_LONG_ENTRY_MASK)
- & 0xff) != counter)
- return -1;
- slotptr2++;
- counter--;
- }
-
- /* Save the real directory entry */
- realdent = (dir_entry *)slotptr2;
- while ((__u8 *)slotptr2 > get_contents_vfatname_block) {
- slotptr2--;
- slot2str(slotptr2, l_name, &idx);
- }
- } else {
- /* Save the real directory entry */
- realdent = (dir_entry *)slotptr;
- }
-
- do {
- slotptr--;
- if (slot2str(slotptr, l_name, &idx))
- break;
- } while (!(slotptr->id & LAST_LONG_ENTRY_MASK));
-
- l_name[idx] = '\0';
- if (*l_name == DELETED_FLAG)
- *l_name = '\0';
- else if (*l_name == aRING)
- *l_name = DELETED_FLAG;
- downcase(l_name);
-
- /* Return the real directory entry */
- memcpy(retdent, realdent, sizeof(dir_entry));
-
- return 0;
-}
-
/* Calculate short name checksum */
static __u8 mkcksum(const char name[8], const char ext[3])
{
}
/*
- * Get the directory entry associated with 'filename' from the directory
- * starting at 'startsect'
+ * TODO these should go away once fat_write is reworked to use the
+ * directory iterator
*/
__u8 get_dentfromdir_block[MAX_CLUSTSIZE]
__aligned(ARCH_DMA_MINALIGN);
-
-static dir_entry *get_dentfromdir(fsdata *mydata, int startsect,
- char *filename, dir_entry *retdent,
- int dols)
-{
- __u16 prevcksum = 0xffff;
- __u32 curclust = START(retdent);
- int files = 0, dirs = 0;
-
- debug("get_dentfromdir: %s\n", filename);
-
- while (1) {
- dir_entry *dentptr;
-
- int i;
-
- if (get_cluster(mydata, curclust, get_dentfromdir_block,
- mydata->clust_size * mydata->sect_size) != 0) {
- debug("Error: reading directory block\n");
- return NULL;
- }
-
- dentptr = (dir_entry *)get_dentfromdir_block;
-
- for (i = 0; i < DIRENTSPERCLUST; i++) {
- char s_name[14], l_name[VFAT_MAXLEN_BYTES];
-
- l_name[0] = '\0';
- if (dentptr->name[0] == DELETED_FLAG) {
- dentptr++;
- continue;
- }
- if ((dentptr->attr & ATTR_VOLUME)) {
- if (vfat_enabled &&
- (dentptr->attr & ATTR_VFAT) == ATTR_VFAT &&
- (dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
- prevcksum = ((dir_slot *)dentptr)->alias_checksum;
- get_vfatname(mydata, curclust,
- get_dentfromdir_block,
- dentptr, l_name);
- if (dols) {
- int isdir;
- char dirc;
- int doit = 0;
-
- isdir = (dentptr->attr & ATTR_DIR);
-
- if (isdir) {
- dirs++;
- dirc = '/';
- doit = 1;
- } else {
- dirc = ' ';
- if (l_name[0] != 0) {
- files++;
- doit = 1;
- }
- }
- if (doit) {
- if (dirc == ' ') {
- printf(" %8u %s%c\n",
- FAT2CPU32(dentptr->size),
- l_name,
- dirc);
- } else {
- printf(" %s%c\n",
- l_name,
- dirc);
- }
- }
- dentptr++;
- continue;
- }
- debug("vfatname: |%s|\n", l_name);
- } else {
- /* Volume label or VFAT entry */
- dentptr++;
- continue;
- }
- }
- if (dentptr->name[0] == 0) {
- if (dols) {
- printf("\n%d file(s), %d dir(s)\n\n",
- files, dirs);
- }
- debug("Dentname == NULL - %d\n", i);
- return NULL;
- }
- if (vfat_enabled) {
- __u8 csum = mkcksum(dentptr->name, dentptr->ext);
- if (dols && csum == prevcksum) {
- prevcksum = 0xffff;
- dentptr++;
- continue;
- }
- }
-
- get_name(dentptr, s_name);
- if (dols) {
- int isdir = (dentptr->attr & ATTR_DIR);
- char dirc;
- int doit = 0;
-
- if (isdir) {
- dirs++;
- dirc = '/';
- doit = 1;
- } else {
- dirc = ' ';
- if (s_name[0] != 0) {
- files++;
- doit = 1;
- }
- }
-
- if (doit) {
- if (dirc == ' ') {
- printf(" %8u %s%c\n",
- FAT2CPU32(dentptr->size),
- s_name, dirc);
- } else {
- printf(" %s%c\n",
- s_name, dirc);
- }
- }
-
- dentptr++;
- continue;
- }
-
- if (strcmp(filename, s_name)
- && strcmp(filename, l_name)) {
- debug("Mismatch: |%s|%s|\n", s_name, l_name);
- dentptr++;
- continue;
- }
-
- memcpy(retdent, dentptr, sizeof(dir_entry));
-
- debug("DentName: %s", s_name);
- debug(", start: 0x%x", START(dentptr));
- debug(", size: 0x%x %s\n",
- FAT2CPU32(dentptr->size),
- (dentptr->attr & ATTR_DIR) ? "(DIR)" : "");
-
- return retdent;
- }
-
- curclust = get_fatent(mydata, curclust);
- if (CHECK_CLUST(curclust, mydata->fatsize)) {
- debug("curclust: 0x%x\n", curclust);
- printf("Invalid FAT entry\n");
- return NULL;
- }
- }
-
- return NULL;
-}
+__u8 do_fat_read_at_block[MAX_CLUSTSIZE]
+ __aligned(ARCH_DMA_MINALIGN);
/*
* Read boot sector and volume info from a FAT filesystem
return ret;
}
-__u8 do_fat_read_at_block[MAX_CLUSTSIZE]
- __aligned(ARCH_DMA_MINALIGN);
-
-int do_fat_read_at(const char *filename, loff_t pos, void *buffer,
- loff_t maxsize, int dols, int dogetsize, loff_t *size)
+static int get_fs_info(fsdata *mydata)
{
- char fnamecopy[2048];
boot_sector bs;
volume_info volinfo;
- fsdata datablock;
- fsdata *mydata = &datablock;
- dir_entry *dentptr = NULL;
- __u16 prevcksum = 0xffff;
- char *subname = "";
- __u32 cursect;
- int idx, isdir = 0;
- int files = 0, dirs = 0;
- int ret = -1;
- int firsttime;
- __u32 root_cluster = 0;
- __u32 read_blk;
- int rootdir_size = 0;
- int buffer_blk_cnt;
- int do_read;
- __u8 *dir_ptr;
-
- if (read_bootsectandvi(&bs, &volinfo, &mydata->fatsize)) {
+ int ret;
+
+ ret = read_bootsectandvi(&bs, &volinfo, &mydata->fatsize);
+ if (ret) {
debug("Error: reading boot sector\n");
- return -1;
+ return ret;
}
if (mydata->fatsize == 32) {
- root_cluster = bs.root_cluster;
mydata->fatlength = bs.fat32_length;
} else {
mydata->fatlength = bs.fat_length;
mydata->fat_sect = bs.reserved;
- cursect = mydata->rootdir_sect
- = mydata->fat_sect + mydata->fatlength * bs.fats;
+ mydata->rootdir_sect = mydata->fat_sect + mydata->fatlength * bs.fats;
mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0];
mydata->clust_size = bs.cluster_size;
if (mydata->fatsize == 32) {
mydata->data_begin = mydata->rootdir_sect -
(mydata->clust_size * 2);
+ mydata->root_cluster = bs.root_cluster;
} else {
- rootdir_size = ((bs.dir_entries[1] * (int)256 +
- bs.dir_entries[0]) *
- sizeof(dir_entry)) /
- mydata->sect_size;
+ mydata->rootdir_size = ((bs.dir_entries[1] * (int)256 +
+ bs.dir_entries[0]) *
+ sizeof(dir_entry)) /
+ mydata->sect_size;
mydata->data_begin = mydata->rootdir_sect +
- rootdir_size -
+ mydata->rootdir_size -
(mydata->clust_size * 2);
+ mydata->root_cluster =
+ sect_to_clust(mydata, mydata->rootdir_sect);
}
mydata->fatbufnum = -1;
mydata->fatsize, mydata->fat_sect, mydata->fatlength);
debug("Rootdir begins at cluster: %d, sector: %d, offset: %x\n"
"Data begins at: %d\n",
- root_cluster,
+ mydata->root_cluster,
mydata->rootdir_sect,
mydata->rootdir_sect * mydata->sect_size, mydata->data_begin);
debug("Sector size: %d, cluster size: %d\n", mydata->sect_size,
mydata->clust_size);
- /* "cwd" is always the root... */
- while (ISDIRDELIM(*filename))
- filename++;
+ return 0;
+}
- /* Make a copy of the filename and convert it to lowercase */
- strcpy(fnamecopy, filename);
- downcase(fnamecopy);
-root_reparse:
- if (*fnamecopy == '\0') {
- if (!dols)
- goto exit;
+/*
+ * Directory iterator, to simplify filesystem traversal
+ *
+ * Implements an iterator pattern to traverse directory tables,
+ * transparently handling directory tables split across multiple
+ * clusters, and the difference between FAT12/FAT16 root directory
+ * (contiguous) and subdirectories + FAT32 root (chained).
+ *
+ * Rough usage:
+ *
+ * for (fat_itr_root(&itr, fsdata); fat_itr_next(&itr); ) {
+ * // to traverse down to a subdirectory pointed to by
+ * // current iterator position:
+ * fat_itr_child(&itr, &itr);
+ * }
+ *
+ * For more complete example, see fat_itr_resolve()
+ */
- dols = LS_ROOT;
- } else if ((idx = dirdelim(fnamecopy)) >= 0) {
- isdir = 1;
- fnamecopy[idx] = '\0';
- subname = fnamecopy + idx + 1;
-
- /* Handle multiple delimiters */
- while (ISDIRDELIM(*subname))
- subname++;
- } else if (dols) {
- isdir = 1;
- }
+typedef struct {
+ fsdata *fsdata; /* filesystem parameters */
+ unsigned clust; /* current cluster */
+ int last_cluster; /* set once we've read last cluster */
+ int is_root; /* is iterator at root directory */
+ int remaining; /* remaining dent's in current cluster */
- buffer_blk_cnt = 0;
- firsttime = 1;
- while (1) {
- int i;
+ /* current iterator position values: */
+ dir_entry *dent; /* current directory entry */
+ char l_name[VFAT_MAXLEN_BYTES]; /* long (vfat) name */
+ char s_name[14]; /* short 8.3 name */
+ char *name; /* l_name if there is one, else s_name */
- if (mydata->fatsize == 32 || firsttime) {
- dir_ptr = do_fat_read_at_block;
- firsttime = 0;
- } else {
- /**
- * FAT16 sector buffer modification:
- * Each loop, the second buffered block is moved to
- * the buffer begin, and two next sectors are read
- * next to the previously moved one. So the sector
- * buffer keeps always 3 sectors for fat16.
- * And the current sector is the buffer second sector
- * beside the "firsttime" read, when it is the first one.
- *
- * PREFETCH_BLOCKS is 2 for FAT16 == loop[0:1]
- * n = computed root dir sector
- * loop | cursect-1 | cursect | cursect+1 |
- * 0 | sector n+0 | sector n+1 | none |
- * 1 | none | sector n+0 | sector n+1 |
- * 0 | sector n+1 | sector n+2 | sector n+3 |
- * 1 | sector n+3 | ...
- */
- dir_ptr = (do_fat_read_at_block + mydata->sect_size);
- memcpy(do_fat_read_at_block, dir_ptr, mydata->sect_size);
- }
+ /* storage for current cluster in memory: */
+ u8 block[MAX_CLUSTSIZE] __aligned(ARCH_DMA_MINALIGN);
+} fat_itr;
- do_read = 1;
+static int fat_itr_isdir(fat_itr *itr);
- if (mydata->fatsize == 32 && buffer_blk_cnt)
- do_read = 0;
+/**
+ * fat_itr_root() - initialize an iterator to start at the root
+ * directory
+ *
+ * @itr: iterator to initialize
+ * @fsdata: filesystem data for the partition
+ * @return 0 on success, else -errno
+ */
+static int fat_itr_root(fat_itr *itr, fsdata *fsdata)
+{
+ if (get_fs_info(fsdata))
+ return -ENXIO;
- if (do_read) {
- read_blk = (mydata->fatsize == 32) ?
- mydata->clust_size : PREFETCH_BLOCKS;
+ itr->fsdata = fsdata;
+ itr->clust = fsdata->root_cluster;
+ itr->dent = NULL;
+ itr->remaining = 0;
+ itr->last_cluster = 0;
+ itr->is_root = 1;
- debug("FAT read(sect=%d, cnt:%d), clust_size=%d, DIRENTSPERBLOCK=%zd\n",
- cursect, read_blk, mydata->clust_size, DIRENTSPERBLOCK);
+ return 0;
+}
- if (disk_read(cursect, read_blk, dir_ptr) < 0) {
- debug("Error: reading rootdir block\n");
- goto exit;
- }
+/**
+ * fat_itr_child() - initialize an iterator to descend into a sub-
+ * directory
+ *
+ * Initializes 'itr' to iterate the contents of the directory at
+ * the current cursor position of 'parent'. It is an error to
+ * call this if the current cursor of 'parent' is pointing at a
+ * regular file.
+ *
+ * Note that 'itr' and 'parent' can be the same pointer if you do
+ * not need to preserve 'parent' after this call, which is useful
+ * for traversing directory structure to resolve a file/directory.
+ *
+ * @itr: iterator to initialize
+ * @parent: the iterator pointing at a directory entry in the
+ * parent directory of the directory to iterate
+ */
+static void fat_itr_child(fat_itr *itr, fat_itr *parent)
+{
+ fsdata *mydata = parent->fsdata; /* for silly macros */
+ unsigned clustnum = START(parent->dent);
- dentptr = (dir_entry *)dir_ptr;
- }
+ assert(fat_itr_isdir(parent));
- for (i = 0; i < DIRENTSPERBLOCK; i++) {
- char s_name[14], l_name[VFAT_MAXLEN_BYTES];
- __u8 csum;
+ itr->fsdata = parent->fsdata;
+ if (clustnum > 0) {
+ itr->clust = clustnum;
+ } else {
+ itr->clust = parent->fsdata->root_cluster;
+ }
+ itr->dent = NULL;
+ itr->remaining = 0;
+ itr->last_cluster = 0;
+ itr->is_root = 0;
+}
- l_name[0] = '\0';
- if (dentptr->name[0] == DELETED_FLAG) {
- dentptr++;
- continue;
- }
+static void *next_cluster(fat_itr *itr)
+{
+ fsdata *mydata = itr->fsdata; /* for silly macros */
+ int ret;
+ u32 sect;
+
+ /* have we reached the end? */
+ if (itr->last_cluster)
+ return NULL;
+
+ sect = clust_to_sect(itr->fsdata, itr->clust);
+
+ debug("FAT read(sect=%d), clust_size=%d, DIRENTSPERBLOCK=%zd\n",
+ sect, itr->fsdata->clust_size, DIRENTSPERBLOCK);
+
+ /*
+ * NOTE: do_fat_read_at() had complicated logic to deal w/
+ * vfat names that span multiple clusters in the fat16 case,
+ * which get_dentfromdir() probably also needed (and was
+ * missing). And not entirely sure what fat32 didn't have
+ * the same issue.. We solve that by only caring about one
+ * dent at a time and iteratively constructing the vfat long
+ * name.
+ */
+ ret = disk_read(sect, itr->fsdata->clust_size,
+ itr->block);
+ if (ret < 0) {
+ debug("Error: reading block\n");
+ return NULL;
+ }
- if (vfat_enabled)
- csum = mkcksum(dentptr->name, dentptr->ext);
-
- if (dentptr->attr & ATTR_VOLUME) {
- if (vfat_enabled &&
- (dentptr->attr & ATTR_VFAT) == ATTR_VFAT &&
- (dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
- prevcksum =
- ((dir_slot *)dentptr)->alias_checksum;
-
- get_vfatname(mydata,
- root_cluster,
- dir_ptr,
- dentptr, l_name);
-
- if (dols == LS_ROOT) {
- char dirc;
- int doit = 0;
- int isdir =
- (dentptr->attr & ATTR_DIR);
-
- if (isdir) {
- dirs++;
- dirc = '/';
- doit = 1;
- } else {
- dirc = ' ';
- if (l_name[0] != 0) {
- files++;
- doit = 1;
- }
- }
- if (doit) {
- if (dirc == ' ') {
- printf(" %8u %s%c\n",
- FAT2CPU32(dentptr->size),
- l_name,
- dirc);
- } else {
- printf(" %s%c\n",
- l_name,
- dirc);
- }
- }
- dentptr++;
- continue;
- }
- debug("Rootvfatname: |%s|\n",
- l_name);
- } else {
- /* Volume label or VFAT entry */
- dentptr++;
- continue;
- }
- } else if (dentptr->name[0] == 0) {
- debug("RootDentname == NULL - %d\n", i);
- if (dols == LS_ROOT) {
- printf("\n%d file(s), %d dir(s)\n\n",
- files, dirs);
- ret = 0;
- }
- goto exit;
- }
- else if (vfat_enabled &&
- dols == LS_ROOT && csum == prevcksum) {
- prevcksum = 0xffff;
- dentptr++;
- continue;
- }
+ if (itr->is_root && itr->fsdata->fatsize != 32) {
+ itr->clust++;
+ sect = clust_to_sect(itr->fsdata, itr->clust);
+ if (sect - itr->fsdata->rootdir_sect >=
+ itr->fsdata->rootdir_size) {
+ debug("cursect: 0x%x\n", itr->clust);
+ itr->last_cluster = 1;
+ }
+ } else {
+ itr->clust = get_fatent(itr->fsdata, itr->clust);
+ if (CHECK_CLUST(itr->clust, itr->fsdata->fatsize)) {
+ debug("cursect: 0x%x\n", itr->clust);
+ itr->last_cluster = 1;
+ }
+ }
- get_name(dentptr, s_name);
-
- if (dols == LS_ROOT) {
- int isdir = (dentptr->attr & ATTR_DIR);
- char dirc;
- int doit = 0;
-
- if (isdir) {
- dirc = '/';
- if (s_name[0] != 0) {
- dirs++;
- doit = 1;
- }
- } else {
- dirc = ' ';
- if (s_name[0] != 0) {
- files++;
- doit = 1;
- }
- }
- if (doit) {
- if (dirc == ' ') {
- printf(" %8u %s%c\n",
- FAT2CPU32(dentptr->size),
- s_name, dirc);
- } else {
- printf(" %s%c\n",
- s_name, dirc);
- }
- }
- dentptr++;
- continue;
- }
+ return itr->block;
+}
- if (strcmp(fnamecopy, s_name)
- && strcmp(fnamecopy, l_name)) {
- debug("RootMismatch: |%s|%s|\n", s_name,
- l_name);
- dentptr++;
- continue;
- }
+static dir_entry *next_dent(fat_itr *itr)
+{
+ if (itr->remaining == 0) {
+ struct dir_entry *dent = next_cluster(itr);
+ unsigned nbytes = itr->fsdata->sect_size *
+ itr->fsdata->clust_size;
- if (isdir && !(dentptr->attr & ATTR_DIR))
- goto exit;
+ /* have we reached the last cluster? */
+ if (!dent)
+ return NULL;
- debug("RootName: %s", s_name);
- debug(", start: 0x%x", START(dentptr));
- debug(", size: 0x%x %s\n",
- FAT2CPU32(dentptr->size),
- isdir ? "(DIR)" : "");
+ itr->remaining = nbytes / sizeof(dir_entry) - 1;
+ itr->dent = dent;
+ } else {
+ itr->remaining--;
+ itr->dent++;
+ }
- goto rootdir_done; /* We got a match */
- }
- debug("END LOOP: buffer_blk_cnt=%d clust_size=%d\n", buffer_blk_cnt,
- mydata->clust_size);
+ /* have we reached the last valid entry? */
+ if (itr->dent->name[0] == 0)
+ return NULL;
- /*
- * On FAT32 we must fetch the FAT entries for the next
- * root directory clusters when a cluster has been
- * completely processed.
- */
- ++buffer_blk_cnt;
- int rootdir_end = 0;
- if (mydata->fatsize == 32) {
- if (buffer_blk_cnt == mydata->clust_size) {
- int nxtsect = 0;
- int nxt_clust = 0;
+ return itr->dent;
+}
+
+static dir_entry *extract_vfat_name(fat_itr *itr)
+{
+ struct dir_entry *dent = itr->dent;
+ int seqn = itr->dent->name[0] & ~LAST_LONG_ENTRY_MASK;
+ u8 chksum, alias_checksum = ((dir_slot *)dent)->alias_checksum;
+ int n = 0;
- nxt_clust = get_fatent(mydata, root_cluster);
- rootdir_end = CHECK_CLUST(nxt_clust, 32);
+ while (seqn--) {
+ char buf[13];
+ int idx = 0;
- nxtsect = mydata->data_begin +
- (nxt_clust * mydata->clust_size);
+ slot2str((dir_slot *)dent, buf, &idx);
- root_cluster = nxt_clust;
+ /* shift accumulated long-name up and copy new part in: */
+ memmove(itr->l_name + idx, itr->l_name, n);
+ memcpy(itr->l_name, buf, idx);
+ n += idx;
- cursect = nxtsect;
- buffer_blk_cnt = 0;
- }
- } else {
- if (buffer_blk_cnt == PREFETCH_BLOCKS)
- buffer_blk_cnt = 0;
+ dent = next_dent(itr);
+ if (!dent)
+ return NULL;
+ }
- rootdir_end = (++cursect - mydata->rootdir_sect >=
- rootdir_size);
- }
+ itr->l_name[n] = '\0';
- /* If end of rootdir reached */
- if (rootdir_end) {
- if (dols == LS_ROOT) {
- printf("\n%d file(s), %d dir(s)\n\n",
- files, dirs);
- *size = 0;
- }
- goto exit;
- }
+ chksum = mkcksum(dent->name, dent->ext);
+
+ /* checksum mismatch could mean deleted file, etc.. skip it: */
+ if (chksum != alias_checksum) {
+ debug("** chksum=%x, alias_checksum=%x, l_name=%s, s_name=%8s.%3s\n",
+ chksum, alias_checksum, itr->l_name, dent->name, dent->ext);
+ return NULL;
}
-rootdir_done:
- firsttime = 1;
+ return dent;
+}
+
+/**
+ * fat_itr_next() - step to the next entry in a directory
+ *
+ * Must be called once on a new iterator before the cursor is valid.
+ *
+ * @itr: the iterator to iterate
+ * @return boolean, 1 if success or 0 if no more entries in the
+ * current directory
+ */
+static int fat_itr_next(fat_itr *itr)
+{
+ dir_entry *dent;
- while (isdir) {
- int startsect = mydata->data_begin
- + START(dentptr) * mydata->clust_size;
- dir_entry dent;
- char *nextname = NULL;
+ itr->name = NULL;
- dent = *dentptr;
- dentptr = &dent;
+ while (1) {
+ dent = next_dent(itr);
+ if (!dent)
+ return 0;
- idx = dirdelim(subname);
+ if (dent->name[0] == DELETED_FLAG ||
+ dent->name[0] == aRING)
+ continue;
- if (idx >= 0) {
- subname[idx] = '\0';
- nextname = subname + idx + 1;
- /* Handle multiple delimiters */
- while (ISDIRDELIM(*nextname))
- nextname++;
- if (dols && *nextname == '\0')
- firsttime = 0;
- } else {
- if (dols && firsttime) {
- firsttime = 0;
+ if (dent->attr & ATTR_VOLUME) {
+ if (vfat_enabled &&
+ (dent->attr & ATTR_VFAT) == ATTR_VFAT &&
+ (dent->name[0] & LAST_LONG_ENTRY_MASK)) {
+ dent = extract_vfat_name(itr);
+ if (!dent)
+ continue;
+ itr->name = itr->l_name;
+ break;
} else {
- isdir = 0;
+ /* Volume label or VFAT entry, skip */
+ continue;
}
}
- if (get_dentfromdir(mydata, startsect, subname, dentptr,
- isdir ? 0 : dols) == NULL) {
- if (dols && !isdir)
- *size = 0;
- goto exit;
- }
+ break;
+ }
- if (isdir && !(dentptr->attr & ATTR_DIR))
- goto exit;
+ get_name(dent, itr->s_name);
+ if (!itr->name)
+ itr->name = itr->s_name;
- /*
- * If we are looking for a directory, and found a directory
- * type entry, and the entry is for the root directory (as
- * denoted by a cluster number of 0), jump back to the start
- * of the function, since at least on FAT12/16, the root dir
- * lives in a hard-coded location and needs special handling
- * to parse, rather than simply following the cluster linked
- * list in the FAT, like other directories.
- */
- if (isdir && (dentptr->attr & ATTR_DIR) && !START(dentptr)) {
- /*
- * Modify the filename to remove the prefix that gets
- * back to the root directory, so the initial root dir
- * parsing code can continue from where we are without
- * confusion.
- */
- strcpy(fnamecopy, nextname ?: "");
- /*
- * Set up state the same way as the function does when
- * first started. This is required for the root dir
- * parsing code operates in its expected environment.
- */
- subname = "";
- cursect = mydata->rootdir_sect;
- isdir = 0;
- goto root_reparse;
- }
+ return 1;
+}
- if (idx >= 0)
- subname = nextname;
- }
+/**
+ * fat_itr_isdir() - is current cursor position pointing to a directory
+ *
+ * @itr: the iterator
+ * @return true if cursor is at a directory
+ */
+static int fat_itr_isdir(fat_itr *itr)
+{
+ return !!(itr->dent->attr & ATTR_DIR);
+}
- if (dogetsize) {
- *size = FAT2CPU32(dentptr->size);
- ret = 0;
- } else {
- ret = get_contents(mydata, dentptr, pos, buffer, maxsize, size);
- }
- debug("Size: %u, got: %llu\n", FAT2CPU32(dentptr->size), *size);
+/*
+ * Helpers:
+ */
-exit:
- free(mydata->fatbuf);
- return ret;
-}
+#define TYPE_FILE 0x1
+#define TYPE_DIR 0x2
+#define TYPE_ANY (TYPE_FILE | TYPE_DIR)
-int do_fat_read(const char *filename, void *buffer, loff_t maxsize, int dols,
- loff_t *actread)
+/**
+ * fat_itr_resolve() - traverse directory structure to resolve the
+ * requested path.
+ *
+ * Traverse directory structure to the requested path. If the specified
+ * path is to a directory, this will descend into the directory and
+ * leave it iterator at the start of the directory. If the path is to a
+ * file, it will leave the iterator in the parent directory with current
+ * cursor at file's entry in the directory.
+ *
+ * @itr: iterator initialized to root
+ * @path: the requested path
+ * @type: bitmask of allowable file types
+ * @return 0 on success or -errno
+ */
+static int fat_itr_resolve(fat_itr *itr, const char *path, unsigned type)
{
- return do_fat_read_at(filename, 0, buffer, maxsize, dols, 0, actread);
+ const char *next;
+
+ /* chomp any extra leading slashes: */
+ while (path[0] && ISDIRDELIM(path[0]))
+ path++;
+
+ /* are we at the end? */
+ if (strlen(path) == 0) {
+ if (!(type & TYPE_DIR))
+ return -ENOENT;
+ return 0;
+ }
+
+ /* find length of next path entry: */
+ next = path;
+ while (next[0] && !ISDIRDELIM(next[0]))
+ next++;
+
+ while (fat_itr_next(itr)) {
+ int match = 0;
+ unsigned n = max(strlen(itr->name), (size_t)(next - path));
+
+ /* check both long and short name: */
+ if (!strncasecmp(path, itr->name, n))
+ match = 1;
+ else if (itr->name != itr->s_name &&
+ !strncasecmp(path, itr->s_name, n))
+ match = 1;
+
+ if (!match)
+ continue;
+
+ if (fat_itr_isdir(itr)) {
+ /* recurse into directory: */
+ fat_itr_child(itr, itr);
+ return fat_itr_resolve(itr, next, type);
+ } else if (next[0]) {
+ /*
+ * If next is not empty then we have a case
+ * like: /path/to/realfile/nonsense
+ */
+ debug("bad trailing path: %s\n", next);
+ return -ENOENT;
+ } else if (!(type & TYPE_FILE)) {
+ return -ENOTDIR;
+ } else {
+ return 0;
+ }
+ }
+
+ return -ENOENT;
}
int file_fat_detectfs(void)
return 0;
}
-int file_fat_ls(const char *dir)
-{
- loff_t size;
-
- return do_fat_read(dir, NULL, 0, LS_YES, &size);
-}
-
int fat_exists(const char *filename)
{
+ fsdata fsdata;
+ fat_itr itrblock, *itr = &itrblock;
int ret;
- loff_t size;
- ret = do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1, &size);
+ ret = fat_itr_root(itr, &fsdata);
+ if (ret)
+ return 0;
+
+ ret = fat_itr_resolve(itr, filename, TYPE_ANY);
+ free(fsdata.fatbuf);
return ret == 0;
}
int fat_size(const char *filename, loff_t *size)
{
- return do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1, size);
+ fsdata fsdata;
+ fat_itr itrblock, *itr = &itrblock;
+ int ret;
+
+ ret = fat_itr_root(itr, &fsdata);
+ if (ret)
+ return ret;
+
+ ret = fat_itr_resolve(itr, filename, TYPE_FILE);
+ if (ret) {
+ /*
+ * Directories don't have size, but fs_size() is not
+ * expected to fail if passed a directory path:
+ */
+ free(fsdata.fatbuf);
+ fat_itr_root(itr, &fsdata);
+ if (!fat_itr_resolve(itr, filename, TYPE_DIR)) {
+ *size = 0;
+ ret = 0;
+ }
+ goto out;
+ }
+
+ *size = FAT2CPU32(itr->dent->size);
+out:
+ free(fsdata.fatbuf);
+ return ret;
}
int file_fat_read_at(const char *filename, loff_t pos, void *buffer,
loff_t maxsize, loff_t *actread)
{
+ fsdata fsdata;
+ fat_itr itrblock, *itr = &itrblock;
+ int ret;
+
+ ret = fat_itr_root(itr, &fsdata);
+ if (ret)
+ return ret;
+
+ ret = fat_itr_resolve(itr, filename, TYPE_FILE);
+ if (ret)
+ goto out;
+
printf("reading %s\n", filename);
- return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO, 0,
- actread);
+ ret = get_contents(&fsdata, itr->dent, pos, buffer, maxsize, actread);
+
+out:
+ free(fsdata.fatbuf);
+ return ret;
}
int file_fat_read(const char *filename, void *buffer, int maxsize)
return ret;
}
+typedef struct {
+ struct fs_dir_stream parent;
+ struct fs_dirent dirent;
+ fsdata fsdata;
+ fat_itr itr;
+} fat_dir;
+
+int fat_opendir(const char *filename, struct fs_dir_stream **dirsp)
+{
+ fat_dir *dir = calloc(1, sizeof(*dir));
+ int ret;
+
+ if (!dir)
+ return -ENOMEM;
+
+ ret = fat_itr_root(&dir->itr, &dir->fsdata);
+ if (ret)
+ goto fail;
+
+ ret = fat_itr_resolve(&dir->itr, filename, TYPE_DIR);
+ if (ret)
+ goto fail;
+
+ *dirsp = (struct fs_dir_stream *)dir;
+ return 0;
+
+fail:
+ free(dir->fsdata.fatbuf);
+ free(dir);
+ return ret;
+}
+
+int fat_readdir(struct fs_dir_stream *dirs, struct fs_dirent **dentp)
+{
+ fat_dir *dir = (fat_dir *)dirs;
+ struct fs_dirent *dent = &dir->dirent;
+
+ if (!fat_itr_next(&dir->itr))
+ return -ENOENT;
+
+ memset(dent, 0, sizeof(*dent));
+ strcpy(dent->name, dir->itr.name);
+
+ if (fat_itr_isdir(&dir->itr)) {
+ dent->type = FS_DT_DIR;
+ } else {
+ dent->type = FS_DT_REG;
+ dent->size = FAT2CPU32(dir->itr.dent->size);
+ }
+
+ *dentp = dent;
+
+ return 0;
+}
+
+void fat_closedir(struct fs_dir_stream *dirs)
+{
+ fat_dir *dir = (fat_dir *)dirs;
+ free(dir->fsdata.fatbuf);
+ free(dir);
+}
+
void fat_close(void)
{
}
*l_name = '\0';
else if (*l_name == aRING)
*l_name = DELETED_FLAG;
- downcase(l_name);
+ downcase(l_name, INT_MAX);
/* Return the real directory entry */
*retdent = realdent;
int ret;
if (clustnum > 0)
- startsect = mydata->data_begin +
- clustnum * mydata->clust_size;
+ startsect = clust_to_sect(mydata, clustnum);
else
startsect = mydata->rootdir_sect;
__u32 startsect, sect_num, offset;
if (clustnum > 0) {
- startsect = mydata->data_begin +
- clustnum * mydata->clust_size;
+ startsect = clust_to_sect(mydata, clustnum);
} else {
startsect = mydata->rootdir_sect;
}
static dir_entry *find_directory_entry(fsdata *mydata, int startsect,
char *filename, dir_entry *retdent, __u32 start)
{
- __u32 curclust = (startsect - mydata->data_begin) / mydata->clust_size;
+ __u32 curclust = sect_to_clust(mydata, startsect);
debug("get_dentfromdir: %s\n", filename);
memcpy(l_filename, filename, name_len);
l_filename[name_len] = 0; /* terminate the string */
- downcase(l_filename);
+ downcase(l_filename, INT_MAX);
startsect = mydata->rootdir_sect;
retdent = find_directory_entry(mydata, startsect,
+++ /dev/null
-/*
- * file.c
- *
- * Mini "VFS" by Marcus Sundberg
- *
- * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6
- * 2003-03-10 - kharris@nexus-tech.net - ported to uboot
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-#include <fat.h>
-#include <linux/stat.h>
-#include <linux/time.h>
-
-/* Supported filesystems */
-static const struct filesystem filesystems[] = {
- { file_fat_detectfs, file_fat_ls, file_fat_read, "FAT" },
-};
-#define NUM_FILESYS (sizeof(filesystems)/sizeof(struct filesystem))
-
-/* The filesystem which was last detected */
-static int current_filesystem = FSTYPE_NONE;
-
-/* The current working directory */
-#define CWD_LEN 511
-char file_cwd[CWD_LEN+1] = "/";
-
-const char *
-file_getfsname(int idx)
-{
- if (idx < 0 || idx >= NUM_FILESYS)
- return NULL;
-
- return filesystems[idx].name;
-}
-
-static void
-pathcpy(char *dest, const char *src)
-{
- char *origdest = dest;
-
- do {
- if (dest-file_cwd >= CWD_LEN) {
- *dest = '\0';
- return;
- }
- *(dest) = *(src);
- if (*src == '\0') {
- if (dest-- != origdest && ISDIRDELIM(*dest)) {
- *dest = '\0';
- }
- return;
- }
- ++dest;
-
- if (ISDIRDELIM(*src))
- while (ISDIRDELIM(*src)) src++;
- else
- src++;
- } while (1);
-}
-
-int
-file_cd(const char *path)
-{
- if (ISDIRDELIM(*path)) {
- while (ISDIRDELIM(*path)) path++;
- strncpy(file_cwd+1, path, CWD_LEN-1);
- } else {
- const char *origpath = path;
- char *tmpstr = file_cwd;
- int back = 0;
-
- while (*tmpstr != '\0') tmpstr++;
- do {
- tmpstr--;
- } while (ISDIRDELIM(*tmpstr));
-
- while (*path == '.') {
- path++;
- while (*path == '.') {
- path++;
- back++;
- }
- if (*path != '\0' && !ISDIRDELIM(*path)) {
- path = origpath;
- back = 0;
- break;
- }
- while (ISDIRDELIM(*path)) path++;
- origpath = path;
- }
-
- while (back--) {
- /* Strip off path component */
- while (!ISDIRDELIM(*tmpstr)) {
- tmpstr--;
- }
- if (tmpstr == file_cwd) {
- /* Incremented again right after the loop. */
- tmpstr--;
- break;
- }
- /* Skip delimiters */
- while (ISDIRDELIM(*tmpstr)) tmpstr--;
- }
- tmpstr++;
- if (*path == '\0') {
- if (tmpstr == file_cwd) {
- *tmpstr = '/';
- tmpstr++;
- }
- *tmpstr = '\0';
- return 0;
- }
- *tmpstr = '/';
- pathcpy(tmpstr+1, path);
- }
-
- return 0;
-}
-
-int
-file_detectfs(void)
-{
- int i;
-
- current_filesystem = FSTYPE_NONE;
-
- for (i = 0; i < NUM_FILESYS; i++) {
- if (filesystems[i].detect() == 0) {
- strcpy(file_cwd, "/");
- current_filesystem = i;
- break;
- }
- }
-
- return current_filesystem;
-}
-
-int
-file_ls(const char *dir)
-{
- char fullpath[1024];
- const char *arg;
-
- if (current_filesystem == FSTYPE_NONE) {
- printf("Can't list files without a filesystem!\n");
- return -1;
- }
-
- if (ISDIRDELIM(*dir)) {
- arg = dir;
- } else {
- sprintf(fullpath, "%s/%s", file_cwd, dir);
- arg = fullpath;
- }
- return filesystems[current_filesystem].ls(arg);
-}
-
-int file_read(const char *filename, void *buffer, int maxsize)
-{
- char fullpath[1024];
- const char *arg;
-
- if (current_filesystem == FSTYPE_NONE) {
- printf("Can't load file without a filesystem!\n");
- return -1;
- }
-
- if (ISDIRDELIM(*filename)) {
- arg = filename;
- } else {
- sprintf(fullpath, "%s/%s", file_cwd, filename);
- arg = fullpath;
- }
-
- return filesystems[current_filesystem].read(arg, buffer, maxsize);
-}
DECLARE_GLOBAL_DATA_PTR;
static struct blk_desc *fs_dev_desc;
+static int fs_dev_part;
static disk_partition_t fs_partition;
static int fs_type = FS_TYPE_ANY;
return -1;
}
+/* generic implementation of ls in terms of opendir/readdir/closedir */
+__maybe_unused
+static int fs_ls_generic(const char *dirname)
+{
+ struct fs_dir_stream *dirs;
+ struct fs_dirent *dent;
+ int nfiles = 0, ndirs = 0;
+
+ dirs = fs_opendir(dirname);
+ if (!dirs)
+ return -errno;
+
+ while ((dent = fs_readdir(dirs))) {
+ if (dent->type == FS_DT_DIR) {
+ printf(" %s/\n", dent->name);
+ ndirs++;
+ } else {
+ printf(" %8lld %s\n", dent->size, dent->name);
+ nfiles++;
+ }
+ }
+
+ fs_closedir(dirs);
+
+ printf("\n%d file(s), %d dir(s)\n\n", nfiles, ndirs);
+
+ return 0;
+}
+
static inline int fs_exists_unsupported(const char *filename)
{
return 0;
return -1;
}
+static inline int fs_opendir_unsupported(const char *filename,
+ struct fs_dir_stream **dirs)
+{
+ return -EACCES;
+}
+
struct fstype_info {
int fstype;
char *name;
loff_t len, loff_t *actwrite);
void (*close)(void);
int (*uuid)(char *uuid_str);
+ /*
+ * Open a directory stream. On success return 0 and directory
+ * stream pointer via 'dirsp'. On error, return -errno. See
+ * fs_opendir().
+ */
+ int (*opendir)(const char *filename, struct fs_dir_stream **dirsp);
+ /*
+ * Read next entry from directory stream. On success return 0
+ * and directory entry pointer via 'dentp'. On error return
+ * -errno. See fs_readdir().
+ */
+ int (*readdir)(struct fs_dir_stream *dirs, struct fs_dirent **dentp);
+ /* see fs_closedir() */
+ void (*closedir)(struct fs_dir_stream *dirs);
};
static struct fstype_info fstypes[] = {
.null_dev_desc_ok = false,
.probe = fat_set_blk_dev,
.close = fat_close,
- .ls = file_fat_ls,
+ .ls = fs_ls_generic,
.exists = fat_exists,
.size = fat_size,
.read = fat_read_file,
.write = fs_write_unsupported,
#endif
.uuid = fs_uuid_unsupported,
+ .opendir = fat_opendir,
+ .readdir = fat_readdir,
+ .closedir = fat_closedir,
},
#endif
#ifdef CONFIG_FS_EXT4
.write = fs_write_unsupported,
#endif
.uuid = ext4fs_uuid,
+ .opendir = fs_opendir_unsupported,
},
#endif
#ifdef CONFIG_SANDBOX
.read = fs_read_sandbox,
.write = fs_write_sandbox,
.uuid = fs_uuid_unsupported,
+ .opendir = fs_opendir_unsupported,
},
#endif
#ifdef CONFIG_CMD_UBIFS
.read = ubifs_read,
.write = fs_write_unsupported,
.uuid = fs_uuid_unsupported,
+ .opendir = fs_opendir_unsupported,
},
#endif
{
.read = fs_read_unsupported,
.write = fs_write_unsupported,
.uuid = fs_uuid_unsupported,
+ .opendir = fs_opendir_unsupported,
},
};
if (!fs_dev_desc && !info->null_dev_desc_ok)
continue;
+ if (!info->probe(fs_dev_desc, &fs_partition)) {
+ fs_type = info->fstype;
+ fs_dev_part = part;
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+/* set current blk device w/ blk_desc + partition # */
+int fs_set_blk_dev_with_part(struct blk_desc *desc, int part)
+{
+ struct fstype_info *info;
+ int ret, i;
+
+ if (part >= 1)
+ ret = part_get_info(desc, part, &fs_partition);
+ else
+ ret = part_get_info_whole_disk(desc, &fs_partition);
+ if (ret)
+ return ret;
+ fs_dev_desc = desc;
+
+ for (i = 0, info = fstypes; i < ARRAY_SIZE(fstypes); i++, info++) {
if (!info->probe(fs_dev_desc, &fs_partition)) {
fs_type = info->fstype;
return 0;
return ret;
}
+struct fs_dir_stream *fs_opendir(const char *filename)
+{
+ struct fstype_info *info = fs_get_info(fs_type);
+ struct fs_dir_stream *dirs = NULL;
+ int ret;
+
+ ret = info->opendir(filename, &dirs);
+ fs_close();
+ if (ret) {
+ errno = -ret;
+ return NULL;
+ }
+
+ dirs->desc = fs_dev_desc;
+ dirs->part = fs_dev_part;
+
+ return dirs;
+}
+
+struct fs_dirent *fs_readdir(struct fs_dir_stream *dirs)
+{
+ struct fstype_info *info;
+ struct fs_dirent *dirent;
+ int ret;
+
+ fs_set_blk_dev_with_part(dirs->desc, dirs->part);
+ info = fs_get_info(fs_type);
+
+ ret = info->readdir(dirs, &dirent);
+ fs_close();
+ if (ret) {
+ errno = -ret;
+ return NULL;
+ }
+
+ return dirent;
+}
+
+void fs_closedir(struct fs_dir_stream *dirs)
+{
+ struct fstype_info *info;
+
+ if (!dirs)
+ return;
+
+ fs_set_blk_dev_with_part(dirs->desc, dirs->part);
+ info = fs_get_info(fs_type);
+
+ info->closedir(dirs);
+ fs_close();
+}
+
+
int do_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int fstype)
{
u_long vl_lower_margin; /* Time from picture to sync */
u_long mmio; /* Memory mapped registers */
+
+ u_int logo_width;
+ u_int logo_height;
+ int logo_x_offset;
+ int logo_y_offset;
+ u_long logo_addr;
} vidinfo_t;
+void atmel_logo_info(vidinfo_t *info);
+void microchip_logo_info(vidinfo_t *info);
+
#endif
* @devnum: Device number, specific to the interface type, or -1 to
* allocate the next available number
* @blksz: Block size of the device in bytes (typically 512)
- * @size: Total size of the device in bytes
+ * @lba: Total number of blocks of the device
* @devp: the new device (which has not been probed)
*/
int blk_create_device(struct udevice *parent, const char *drv_name,
const char *name, int if_type, int devnum, int blksz,
- lbaint_t size, struct udevice **devp);
+ lbaint_t lba, struct udevice **devp);
/**
* blk_create_devicef() - Create a new named block device
* @devnum: Device number, specific to the interface type, or -1 to
* allocate the next available number
* @blksz: Block size of the device in bytes (typically 512)
- * @size: Total size of the device in bytes
+ * @lba: Total number of blocks of the device
* @devp: the new device (which has not been probed)
*/
int blk_create_devicef(struct udevice *parent, const char *drv_name,
const char *name, int if_type, int devnum, int blksz,
- lbaint_t size, struct udevice **devp);
+ lbaint_t lba, struct udevice **devp);
/**
* blk_prepare_device() - Prepare a block device for use
#ifndef _BOOTSTAGE_H
#define _BOOTSTAGE_H
-/* Define this for host tools */
-#ifndef CONFIG_BOOTSTAGE_USER_COUNT
-#define CONFIG_BOOTSTAGE_USER_COUNT 20
-#endif
-
/* Flags for each bootstage record */
enum bootstage_flags {
BOOTSTAGEF_ERROR = 1 << 0, /* Error record */
/* a few spare for the user, from here */
BOOTSTAGE_ID_USER,
- BOOTSTAGE_ID_COUNT = BOOTSTAGE_ID_USER + CONFIG_BOOTSTAGE_USER_COUNT,
BOOTSTAGE_ID_ALLOC,
};
--- /dev/null
+/*
+ * charset conversion utils
+ *
+ * Copyright (c) 2017 Rob Clark
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CHARSET_H_
+#define __CHARSET_H_
+
+#define MAX_UTF8_PER_UTF16 4
+
+/**
+ * utf16_strlen() - Get the length of an utf16 string
+ *
+ * Returns the number of 16 bit characters in an utf16 string, not
+ * including the terminating NULL character.
+ *
+ * @in the string to measure
+ * @return the string length
+ */
+size_t utf16_strlen(const uint16_t *in);
+
+/**
+ * utf16_strnlen() - Get the length of a fixed-size utf16 string.
+ *
+ * Returns the number of 16 bit characters in an utf16 string,
+ * not including the terminating NULL character, but at most
+ * 'count' number of characters. In doing this, utf16_strnlen()
+ * looks at only the first 'count' characters.
+ *
+ * @in the string to measure
+ * @count the maximum number of characters to count
+ * @return the string length, up to a maximum of 'count'
+ */
+size_t utf16_strnlen(const uint16_t *in, size_t count);
+
+/**
+ * utf16_strcpy() - UTF16 equivalent of strcpy()
+ */
+uint16_t *utf16_strcpy(uint16_t *dest, const uint16_t *src);
+
+/**
+ * utf16_strdup() - UTF16 equivalent of strdup()
+ */
+uint16_t *utf16_strdup(const uint16_t *s);
+
+/**
+ * utf16_to_utf8() - Convert an utf16 string to utf8
+ *
+ * Converts 'size' characters of the utf16 string 'src' to utf8
+ * written to the 'dest' buffer.
+ *
+ * NOTE that a single utf16 character can generate up to 4 utf8
+ * characters. See MAX_UTF8_PER_UTF16.
+ *
+ * @dest the destination buffer to write the utf8 characters
+ * @src the source utf16 string
+ * @size the number of utf16 characters to convert
+ * @return the pointer to the first unwritten byte in 'dest'
+ */
+uint8_t *utf16_to_utf8(uint8_t *dest, const uint16_t *src, size_t size);
+
+#endif /* __CHARSET_H_ */
};
#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)
-struct phandle_2_cell;
+struct phandle_1_arg;
int clk_get_by_index_platdata(struct udevice *dev, int index,
- struct phandle_2_cell *cells, struct clk *clk);
+ struct phandle_1_arg *cells, struct clk *clk);
/**
* clock_get_by_index - Get/request a clock by integer index.
#if (CONFIG_IS_ENABLED(PARTITION_UUIDS) || \
CONFIG_IS_ENABLED(EFI_PARTITION) || \
+ CONFIG_IS_ENABLED(EFI_LOADER) || \
defined(CONFIG_RANDOM_UUID) || \
defined(CONFIG_CMD_UUID) || \
defined(CONFIG_BOOTP_PXE)) && \
#define CONFIG_CMDLINE_EDITING
#define CONFIG_PANIC_HANG
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_ARCH_MAP_SYSMEM
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_SERVERIP
/* max number of sectors on one chip */
#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
-#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
#define CONFIG_SYS_MAX_FLASH_SECT 512
/* environments */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 50000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SECT_SIZE 0x1000
+#define CONFIG_ENV_OFFSET 0x140000
#define CONFIG_ENV_SIZE 8192
#define CONFIG_ENV_OVERWRITE
+
+/* SPI FLASH */
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
/*
* For booting Linux, the board info and command line data
* have to be in the first 16 MB of memory, since this is
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_ARCH_MAP_SYSMEM
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#endif
/*
* High Level Configuration Options
*/
-#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_NAND_OMAP_GPMC
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x260000
+#define CONFIG_ENV_ADDR 0x260000
/*-----------------------------------------------------------------------
* CFI FLASH driver setup
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
-
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
-#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap.h>
+#include <configs/ti_omap3_common.h>
+#undef CONFIG_SDRC /* Disable SDRC since we have EMIF4 */
#define CONFIG_MISC_INIT_R
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (16 << 20)
-
/* Hardware drivers */
/* NS16550 Configuration */
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/* select serial console configuration */
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
/*
* USB configuration
/* Board NAND Info. */
#ifdef CONFIG_NAND
-#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_GPMC_PREFETCH
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
-#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
- /* to access */
- /* nand at CS0 */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
- /* NAND devices */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
/* We set the max number of command args high to avoid HUSH bugs. */
#define CONFIG_SYS_MAXARGS 64
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE 512
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ + sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
- /* address */
-
-/*
- * AM3517 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
/* Physical Memory Map */
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
/* FLASH and environment organization */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_SIZE CONFIG_SYS_ENV_SECT_SIZE
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x260000
+#define CONFIG_ENV_ADDR 0x260000
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_NAND_SIMPLE
+#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
+#undef CONFIG_SPL_BSS_START_ADDR
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_CONSOLE_MUX
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 198000000
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_PWM_IMX
#ifndef __AT91_SAMA5_COMMON_H
#define __AT91_SAMA5_COMMON_H
-#include <asm/hardware.h>
-
#define CONFIG_SYS_TEXT_BASE 0x26f00000
/* ARM asynchronous clock */
* Command line configuration.
*/
-#ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_ENV_IS_IN_MMC
/* Use raw reserved sectors to save environment */
#else
-#ifdef CONFIG_SYS_USE_NANDFLASH
+#ifdef CONFIG_NAND_BOOT
/* u-boot env in nand flash */
#define CONFIG_ENV_OFFSET 0xc0000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \
"nand read 0x22000000 0x200000 0x600000;" \
"bootz 0x22000000 - 0x21000000"
-#elif CONFIG_SYS_USE_SERIALFLASH
+#elif CONFIG_SPI_BOOT
/* u-boot env in serial flash, by default is bus 0 and cs 0 */
#define CONFIG_ENV_OFFSET 0x6000
#define CONFIG_ENV_SIZE 0x2000
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/hardware.h>
-
#define CONFIG_SYS_TEXT_BASE 0x73f00000
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
+#define CONFIG_SYS_SDRAM_BASE 0x70000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_SYS_INIT_SP_ADDR \
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END 0x23e00000
-#ifdef CONFIG_SYS_USE_NANDFLASH
+#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env in nandflash */
#define CONFIG_ENV_OFFSET 0x120000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_BOOTCOMMAND \
"nand read 0x70000000 0x200000 0x300000;" \
"bootm 0x70000000"
-#elif CONFIG_SYS_USE_MMC
+#elif CONFIG_SD_BOOT
/* bootstrap + u-boot + env + linux in mmc */
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_SYS_MONITOR_LEN 0x80000
-#ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_BSS_START_ADDR 0x70000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#elif CONFIG_SYS_USE_NANDFLASH
+#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_ECC
#ifndef __AT91SAM9N12_CONFIG_H_
#define __AT91SAM9N12_CONFIG_H_
-/*
- * SoC must be defined first, before hardware.h is included.
- * In this case SoC is defined in boards.cfg.
- */
-#include <asm/hardware.h>
-
#define CONFIG_SYS_TEXT_BASE 0x26f00000
/* ARM asynchronous clock */
* that address while providing maximum stack area below.
*/
# define CONFIG_SYS_INIT_SP_ADDR \
- (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+ (0x00300000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
/* DataFlash */
#ifdef CONFIG_CMD_SF
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
#endif
-#ifdef CONFIG_SYS_USE_SPIFLASH
+#ifdef CONFIG_SPI_BOOT
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_ENV_OFFSET 0x5000
"sf probe 0; sf read 0x22000000 0x100000 0x300000; " \
"bootm 0x22000000"
-#elif defined(CONFIG_SYS_USE_NANDFLASH)
+#elif defined(CONFIG_NAND_BOOT)
/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_OFFSET 0x120000
"nand read 0x22000000 0x200000 0x400000;" \
"bootm 0x22000000 - 0x21000000"
-#else /* CONFIG_SYS_USE_MMC */
+#else /* CONFIG_SD_BOOT */
/* bootstrap + u-boot + env + linux in mmc */
#define CONFIG_SYS_MCKR 0x1301
#define CONFIG_SYS_MCKR_CSS 0x1302
-#ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#elif CONFIG_SYS_USE_NANDFLASH
+#elif CONFIG_SPI_BOOT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
+
+#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
+#endif
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
-#elif CONFIG_SYS_USE_SPIFLASH
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
-
-#endif
-
#endif
#ifndef __CONFIG_H__
#define __CONFIG_H__
-#include <asm/hardware.h>
-
#define CONFIG_SYS_TEXT_BASE 0x26f00000
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
-#define CONFIG_AT91SAM9X5EK
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END 0x26e00000
-#ifdef CONFIG_SYS_USE_NANDFLASH
+#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_OFFSET 0x120000
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_BOOTCOMMAND "nand read " \
"0x22000000 0x200000 0x300000; " \
"bootm 0x22000000"
-#elif defined(CONFIG_SYS_USE_SPIFLASH)
+#elif defined(CONFIG_SPI_BOOT)
/* bootstrap + u-boot + env + linux in spi flash */
#define CONFIG_ENV_OFFSET 0x5000
#define CONFIG_ENV_SIZE 0x3000
#define CONFIG_BOOTCOMMAND "sf probe 0; " \
"sf read 0x22000000 0x84000 0x294000; " \
"bootm 0x22000000"
-#else /* CONFIG_SYS_USE_MMC */
+#else /* CONFIG_SD_BOOT */
/* bootstrap + u-boot + env + linux in mmc */
#define CONFIG_ENV_SIZE 0x4000
#endif
#define CONFIG_SYS_MCKR 0x1301
#define CONFIG_SYS_MCKR_CSS 0x1302
-#ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#elif CONFIG_SYS_USE_NANDFLASH
+#elif CONFIG_SPI_BOOT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
+
+#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
+#endif
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
-#elif CONFIG_SYS_USE_SPIFLASH
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
-
-#endif
-
#endif
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#ifdef CONFIG_MX6DL
-#define CONFIG_IPUV3_CLK 198000000
-#else
-#define CONFIG_IPUV3_CLK 264000000
-#endif
#define CONFIG_IMX_HDMI
/* SATA */
--- /dev/null
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN (2 << 20)
+
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \
+ "stdout=vidconsole,serial\0" \
+ "stderr=vidconsole,serial\0"
+
+/* Environment configuration */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_OFFSET 0x005f0000
+
+#endif /* __CONFIG_H */
/* Display */
#define CONFIG_VIDEO_IPUV3
-#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#define CONFIG_SPLASH_SCREEN
*/
#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
-#define CONFIG_SDRC /* The chip has SDRC controller */
-
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x260000
+#define CONFIG_ENV_ADDR 0x260000
#if defined(CONFIG_CMD_NET)
#define CONFIG_SMC911X
* to be on the safe side once the default is changed.
*/
-#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
-
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x260000
+#define CONFIG_ENV_ADDR 0x260000
#if defined(CONFIG_CMD_NET)
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_CONSOLE_MUX
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
0x01000000) /* 16MB */
/* NAND and environment organization */
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x260000
/* SRAM config */
#define CONFIG_SYS_SRAM_START 0x40200000
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#endif
#define CONFIG_SYS_I2C_MXC_I2C2
#define CONFIG_SYS_I2C_MXC_I2C3
+#define CONFIG_SYS_NUM_I2C_BUSES 9
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
+ }
+
+#define CONFIG_BCH
+
#endif /* __GE_BX50V3_CONFIG_H */
/* Framebuffer and LCD */
#define CONFIG_VIDEO_IPUV3
#define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_VIDEO_BMP_LOGO
/* Framebuffer */
#ifdef CONFIG_VIDEO_IPUV3
-# define CONFIG_IPUV3_CLK 260000000
# define CONFIG_IMX_VIDEO_SKIP
# define CONFIG_SPLASH_SCREEN
"run envboot; " \
"run run_mon_hs; " \
"run init_${boot}; " \
- "run set_name_pmmc get_pmmc_${boot} run_pmmc; " \
"run get_fit_${boot}; " \
"bootm ${fit_loadaddr}#${name_fdt}"
#endif
--- /dev/null
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1088_COMMON_H
+#define __LS1088_COMMON_H
+
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_MP
+
+#include <asm/arch/stream_id_lsch3.h>
+#include <asm/arch/config.h>
+#include <asm/arch/soc.h>
+
+/* Link Definitions */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+
+/* Link Definitions */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_TEXT_BASE 0x20100000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x30100000
+#endif
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
+/*
+ * SMP Definitinos
+ */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* IFC */
+#define CONFIG_FSL_IFC
+
+/*
+ * During booting, IFC is mapped at the region of 0x30000000.
+ * But this region is limited to 256MB. To accommodate NOR, promjet
+ * and FPGA. This region is divided as below:
+ * 0x30000000 - 0x37ffffff : 128MB : NOR flash
+ * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
+ * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
+ *
+ * To accommodate bigger NOR flash and other devices, we will map IFC
+ * chip selects to as below:
+ * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
+ * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
+ * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
+ * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
+ * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
+ *
+ * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
+ * CONFIG_SYS_FLASH_BASE has the final address (core view)
+ * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
+ */
+
+#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
+#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
+#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
+
+#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
+#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
+
+#ifndef __ASSEMBLY__
+unsigned long long get_qixis_addr(void);
+#endif
+
+#define QIXIS_BASE get_qixis_addr()
+#define QIXIS_BASE_PHYS 0x20000000
+#define QIXIS_BASE_PHYS_EARLY 0xC000000
+
+
+#define CONFIG_SYS_NAND_BASE 0x530000000ULL
+#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
+
+
+/* MC firmware */
+/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
+#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
+#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
+#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
+#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
+/*
+ * Carve out a DDR region which will not be used by u-boot/Linux
+ *
+ * It will be used by MC and Debug Server. The MC region must be
+ * 512MB aligned, so the min size to hide is 512MB.
+ */
+
+#if defined(CONFIG_FSL_MC_ENET)
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
+#endif
+
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
+
+/* Command line configuration */
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_CACHE
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+
+#define CONFIG_NR_DRAM_BANKS 2
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE 128
+
+/* #define CONFIG_DISPLAY_CPUINFO */
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x80100000\0" \
+ "kernel_addr=0x100000\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x581000000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "console=ttyAMA0,38400n8\0" \
+ "mcinitcmd=fsl_mc start mc 0x580a00000" \
+ " 0x580e00000 \0"
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
+ "earlycon=uart8250,mmio,0x21c0500 " \
+ "ramdisk_size=0x3000000 default_hugepagesz=2m" \
+ " hugepagesz=2m hugepages=256"
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
+ "sf read 0x80200000 0xd00000 0x100000;"\
+ " fsl_mc apply dpl 0x80200000 &&" \
+ " sf read $kernel_load $kernel_start" \
+ " $kernel_size && bootm $kernel_load"
+#else /* NOR BOOT*/
+#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
+ " cp.b $kernel_start $kernel_load" \
+ " $kernel_size && bootm $kernel_load"
+#endif
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#endif /* __LS1088_COMMON_H */
--- /dev/null
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1088A_QDS_H
+#define __LS1088A_QDS_H
+
+#include "ls1088a_common.h"
+
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE 0x20000
+#endif
+
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_QIXIS_I2C_ACCESS
+#define SYS_NO_FLASH
+
+#undef CONFIG_CMD_IMLS
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 100000000
+#else
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
+#endif
+
+#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
+#define COUNTER_FREQUENCY 25000000 /* 25MHz */
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#define SPD_EEPROM_ADDRESS 0x51
+#define CONFIG_SYS_SPD_BUS_NUM 0
+
+
+/*
+ * IFC Definitions
+ */
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
+
+#define CONFIG_SYS_NOR0_CSPR \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1a) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x04000000
+#define CONFIG_SYS_IFC_CCR 0x01000000
+
+#ifndef SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
+ CONFIG_SYS_FLASH_BASE + 0x40000000}
+#endif
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS 256
+#define CONFIG_SYS_NAND_MAX_OOBFREE 2
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+#define CONFIG_FSL_QIXIS
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define QIXIS_LBMAP_SWITCH 6
+#define QIXIS_QMAP_MASK 0xe0
+#define QIXIS_QMAP_SHIFT 5
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x0e
+#define QIXIS_LBMAP_ALTBANK 0x2e
+#define QIXIS_LBMAP_SD 0x00
+#define QIXIS_LBMAP_SD_QSPI 0x0e
+#define QIXIS_LBMAP_QSPI 0x0e
+#define QIXIS_RCW_SRC_SD 0x40
+#define QIXIS_RCW_SRC_QSPI 0x62
+#define QIXIS_RST_CTL_RESET 0x41
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_RST_FORCE_MEM 0x01
+#define QIXIS_STAT_PRES1 0xb
+#define QIXIS_SDID_MASK 0x07
+#define QIXIS_ESDHC_NO_ADAPTER 0x7
+
+#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
+#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+
+#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
+#else
+#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
+#endif
+/* QIXIS Timing parameters*/
+#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+ FTIM1_GPCM_TRAD(0x3f))
+#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+ FTIM2_GPCM_TCH(0xf) | \
+ FTIM2_GPCM_TWP(0x3E))
+#define SYS_FPGA_CS_FTIM3 0x0
+
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
+#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
+#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_CSPR3_FINAL CONFIG_SYS_FPGA_CSPR_FINAL
+#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_CS_FTIM0
+#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_CS_FTIM1
+#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_CS_FTIM2
+#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_CS_FTIM3
+#endif
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI 0x77
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR 0x18
+#define I2C_RETIMER_ADDR2 0x19
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH5 0xD
+
+/*
+* RTC configuration
+*/
+#define RTC
+#define CONFIG_RTC_PCF8563 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
+#define CONFIG_CMD_DATE
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* QSPI device */
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE (1 << 26)
+#define FSL_QSPI_FLASH_NUM 2
+
+#endif
+
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SF_DEFAULT_BUS 1
+#define CONFIG_SF_DEFAULT_CS 0
+#endif
+#endif
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_FSL_MEMAC
+
+/* MMC */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
+ QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
+
+/* Initial environment variables */
+#if defined(CONFIG_QSPI_BOOT)
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x90100000\0" \
+ "kernel_addr=0x100000\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x1000000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
+ "sf read 0x80100000 0xE00000 0x100000;" \
+ "fsl_mc start mc 0x80000000 0x80100000\0" \
+ "mcmemsize=0x70000000 \0"
+#else /* NOR BOOT */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x90100000\0" \
+ "kernel_addr=0x100000\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x1000000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
+ "mcmemsize=0x70000000 \0"
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_FSL_MEMAC
+#define CONFIG_PHYLIB
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define RGMII_PHY1_ADDR 0x1
+#define RGMII_PHY2_ADDR 0x2
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+
+#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
+#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
+#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
+#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
+#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
+#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
+#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
+#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
+#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
+#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
+#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
+#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
+#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
+#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
+#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
+#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
+
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "DPMAC1@xgmii"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+
+#endif
+
+#undef CONFIG_CMDLINE_EDITING
+#include <config_distro_defaults.h>
+#define BOOT_TARGET_DEVICES(func) \
+ func(USB, usb, 0) \
+ func(MMC, mmc, 0) \
+ func(SCSI, scsi, 0) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1088A_QDS_H */
--- /dev/null
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1088A_RDB_H
+#define __LS1088A_RDB_H
+
+#include "ls1088a_common.h"
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE 0x20000
+#endif
+
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_QIXIS_I2C_ACCESS
+#define SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 100000000
+#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
+#define COUNTER_FREQUENCY 25000000 /* 25MHz */
+
+#define CONFIG_DDR_SPD
+#ifdef CONFIG_EMU
+#define CONFIG_SYS_FSL_DDR_EMU
+#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
+#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
+#else
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+#define SPD_EEPROM_ADDRESS 0x51
+#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+
+
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
+#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
+
+#define CONFIG_SYS_NOR0_CSPR \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
+ FTIM0_NOR_TEADC(0x1) | \
+ FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
+ FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
+ FTIM2_NOR_TCH(0x0) | \
+ FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3 0x04000000
+#define CONFIG_SYS_IFC_CCR 0x01000000
+
+#ifndef SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#endif
+#endif
+#define CONFIG_SYS_NAND_MAX_ECCPOS 256
+#define CONFIG_SYS_NAND_MAX_OOBFREE 2
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+#define CONFIG_FSL_QIXIS
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define QIXIS_LBMAP_SWITCH 2
+#define QIXIS_QMAP_MASK 0xe0
+#define QIXIS_QMAP_SHIFT 5
+#define QIXIS_LBMAP_MASK 0x1f
+#define QIXIS_LBMAP_SHIFT 5
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x20
+#define QIXIS_LBMAP_SD 0x00
+#define QIXIS_LBMAP_SD_QSPI 0x00
+#define QIXIS_LBMAP_QSPI 0x00
+#define QIXIS_RCW_SRC_SD 0x40
+#define QIXIS_RCW_SRC_QSPI 0x62
+#define QIXIS_RST_CTL_RESET 0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_RST_FORCE_MEM 0x01
+
+#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
+#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+
+#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
+#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
+/* QIXIS Timing parameters*/
+#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+ FTIM1_GPCM_TRAD(0x3f))
+#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+ FTIM2_GPCM_TCH(0xf) | \
+ FTIM2_GPCM_TWP(0x3E))
+#define SYS_FPGA_CS_FTIM3 0x0
+
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#endif
+
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI 0x77
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR 0x18
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH5 0xD
+/*
+* RTC configuration
+*/
+#define RTC
+#define CONFIG_RTC_PCF8563 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
+#define CONFIG_CMD_DATE
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* QSPI device */
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE (1 << 26)
+#define FSL_QSPI_FLASH_NUM 2
+#endif
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_FSL_MEMAC
+
+/* Initial environment variables */
+#if defined(CONFIG_QSPI_BOOT)
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x90100000\0" \
+ "kernel_addr=0x100000\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x1000000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
+ "sf read 0x80100000 0xE00000 0x100000;" \
+ "fsl_mc start mc 0x80000000 0x80100000\0" \
+ "mcmemsize=0x70000000 \0"
+
+#endif
+
+/* MAC/PHY configuration */
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_AQUANTIA
+#define AQ_PHY_ADDR1 0x00
+#define AQR105_IRQ_MASK 0x00000004
+
+#define QSGMII1_PORT1_PHY_ADDR 0x0c
+#define QSGMII1_PORT2_PHY_ADDR 0x0d
+#define QSGMII1_PORT3_PHY_ADDR 0x0e
+#define QSGMII1_PORT4_PHY_ADDR 0x0f
+#define QSGMII2_PORT1_PHY_ADDR 0x1c
+#define QSGMII2_PORT2_PHY_ADDR 0x1d
+#define QSGMII2_PORT3_PHY_ADDR 0x1e
+#define QSGMII2_PORT4_PHY_ADDR 0x1f
+
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "DPMAC1@xgmii"
+#define CONFIG_PHY_GIGE
+#endif
+
+/* MMC */
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+#undef CONFIG_CMDLINE_EDITING
+#include <config_distro_defaults.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(USB, usb, 0) \
+ func(MMC, mmc, 0) \
+ func(SCSI, scsi, 0) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1088A_RDB_H */
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
-#define CONFIG_IPUV3_CLK 200000000
#endif
/*
#define CONFIG_SYS_USE_SERIALFLASH 1
#define CONFIG_BOARD_LATE_INIT
+/* Timer */
+#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
+
/*
* Memory configurations
*/
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x10000000
#ifdef CONFIG_SPL_BUILD
* Serial Driver
*/
#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_USART0
-#define CONFIG_USART_ID ATMEL_ID_USART0
+#define CONFIG_USART_BASE 0xf802c000
+#define CONFIG_USART_ID 6
/*
* Ethernet
#define CONFIG_MACH_TYPE MACH_TYPE_MCX
-#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
-
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_GPMC_PREFETCH
-#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
/* Redundant Environment */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x180000
+#define CONFIG_ENV_ADDR 0x180000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
2 * CONFIG_SYS_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK 133000000
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK 200000000
#endif /* __CONFIG_H */
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK 200000000
#endif /* __CONFIG_H */
/* Framebuffer */
#define CONFIG_VIDEO_IPUV3
-#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
"fi; " \
"fi\0" \
"findfdt="\
+ "if test $board_name = HUMMINGBOARD2 && test $board_rev = MX6Q ; then " \
+ "setenv fdtfile imx6q-hummingboard2.dtb; fi; " \
+ "if test $board_name = HUMMINGBOARD2 && test $board_rev = MX6DL ; then " \
+ "setenv fdtfile imx6dl-hummingboard2.dtb; fi; " \
"if test $board_name = HUMMINGBOARD && test $board_rev = MX6Q ; then " \
"setenv fdtfile imx6q-hummingboard.dtb; fi; " \
"if test $board_name = HUMMINGBOARD && test $board_rev = MX6DL ; then " \
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#ifdef CONFIG_MX6DL
-#define CONFIG_IPUV3_CLK 198000000
-#else
-#define CONFIG_IPUV3_CLK 264000000
-#endif
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024)
#define CONFIG_BMP_16BPP
-#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
*/
#define CONFIG_SYS_TEXT_BASE 0x80008000
-#define CONFIG_SDRC /* The chip has SDRC controller */
-
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
#include <asm/arch/mem.h>
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#endif
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x260000
+#define CONFIG_ENV_ADDR 0x260000
/* Defines for SPL */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x260000
+#define CONFIG_ENV_ADDR 0x260000
/* Defines for SPL */
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x260000
+#define CONFIG_ENV_ADDR 0x260000
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
/* NAND: SPL falcon mode configs */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x260000
+#define CONFIG_ENV_ADDR 0x260000
/* SMSC922x Ethernet */
#if defined(CONFIG_CMD_NET)
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
-#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
-
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x240000
+#define CONFIG_ENV_ADDR 0x240000
/* Configure SMSC9211 ethernet */
#if defined(CONFIG_CMD_NET)
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x260000
+#define CONFIG_ENV_ADDR 0x260000
#endif /* __CONFIG_H */
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x260000
+#define CONFIG_ENV_ADDR 0x260000
#ifdef CONFIG_CMD_NET
/* Ethernet (LAN9211 from SMSC9118 family) */
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
BOOTENV
#endif
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000)
+/* rockchip ohci host driver */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
#endif
--- /dev/null
+/*
+ * Configuration file for the SAMA5D27 SOM1 EK Board.
+ *
+ * Copyright (C) 2017 Microchip Corporation
+ * Wenyou Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+#undef CONFIG_SYS_TEXT_BASE
+#undef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_TEXT_BASE 0x23f00000
+#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
+
+#define CONFIG_MISC_INIT_R
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE 0x8000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR 0x218000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+/* NAND flash */
+#undef CONFIG_CMD_NAND
+
+/* SPI flash */
+#define CONFIG_SF_DEFAULT_SPEED 66000000
+
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_SD_BOOT
+/* u-boot env in sd/mmc card */
+#define FAT_ENV_INTERFACE "mmc"
+#define FAT_ENV_DEVICE_AND_PART "0"
+#define FAT_ENV_FILE "uboot.env"
+#define CONFIG_ENV_SIZE 0x4000
+/* bootstrap + u-boot + env in sd card */
+#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d27_som1_ek.dtb; " \
+ "fatload mmc 0:1 0x22000000 zImage; " \
+ "bootz 0x22000000 - 0x21000000"
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+#endif
+
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_ENV_OFFSET 0xb0000
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_BOOTCOMMAND "sf probe 0; " \
+ "sf read 0x21000000 0xc0000 0x20000; " \
+ "sf read 0x22000000 0xe0000 0x400000; " \
+ "bootz 0x22000000 - 0x21000000"
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+#endif
+
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x200000
+#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#endif
+
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
+#endif
+
+#endif
/* serial console */
#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_UART0
-#define CONFIG_USART_ID ATMEL_ID_UART0
+#define CONFIG_USART_BASE 0xf801c000
+#define CONFIG_USART_ID 24
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CONFIG_SYS_TIMER_COUNTER 0xf804803c
+
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x210000
#else
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_BASE 0x80000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_MACB_SEARCH_PHY
-#ifdef CONFIG_SYS_USE_NANDFLASH
+#ifdef CONFIG_NAND_BOOT
#undef CONFIG_ENV_OFFSET
#undef CONFIG_ENV_OFFSET_REDUND
#undef CONFIG_BOOTCOMMAND
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-#ifdef CONFIG_SYS_USE_SERIALFLASH
+#ifdef CONFIG_SPI_BOOT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
-#elif CONFIG_SYS_USE_NANDFLASH
+#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
+#endif
#define CONFIG_PMECC_CAP 8
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
-#endif
#endif
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SF_DEFAULT_SPEED 30000000
#endif
-/* I2C */
-#define AT24MAC_ADDR 0x5c
-#define AT24MAC_REG 0x9a
-
/* LCD */
#ifdef CONFIG_LCD
#define CONFIG_ATMEL_LCD_RGB565
#endif
-#ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_SD_BOOT
/* bootstrap + u-boot + env in sd card */
#undef CONFIG_BOOTCOMMAND
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
-#define CONFIG_SPL_MAX_SIZE 0x18000
+#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-#ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#elif CONFIG_SYS_USE_SERIALFLASH
+#elif CONFIG_SPI_BOOT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
* This needs to be defined for the OHCI code to work but it is defined as
* ATMEL_ID_UHPHS in the CPU specific header files.
*/
-#define ATMEL_ID_UHP ATMEL_ID_UHPHS
+#define ATMEL_ID_UHP 32
/*
* Specify the clock enable bit in the PMC_SCER register.
*/
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
+#define ATMEL_PMC_UHP (1 << 6)
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x10000000
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_BASE 0x60000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-#if CONFIG_SYS_USE_NANDFLASH
-/* override the bootcmd, bootargs and other configuration for nandflash env */
-#elif CONFIG_SYS_USE_MMC
-/* override the bootcmd, bootargs and other configuration for sd/mmc env */
-#endif
-
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x300000
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-#ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#elif CONFIG_SYS_USE_NANDFLASH
+#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
+#endif
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
#endif
-
-#endif
* This needs to be defined for the OHCI code to work but it is defined as
* ATMEL_ID_UHPHS in the CPU specific header files.
*/
-#define ATMEL_ID_UHP ATMEL_ID_UHPHS
+#define ATMEL_ID_UHP 32
/*
* Specify the clock enable bit in the PMC_SCER register.
*/
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
+#define ATMEL_PMC_UHP (1 << 6)
/* LCD */
#define LCD_BPP LCD_COLOR16
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_BASE 0x60000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-#ifdef CONFIG_SYS_USE_SERIALFLASH
-/* override the bootcmd, bootargs and other configuration for spi flash env*/
-#elif CONFIG_SYS_USE_NANDFLASH
-/* override the bootcmd, bootargs and other configuration nandflash env */
-#elif CONFIG_SYS_USE_MMC
-/* override the bootcmd, bootargs and other configuration for sd/mmc env */
-#endif
-
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x300000
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-#ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#elif CONFIG_SYS_USE_NANDFLASH
+#elif CONFIG_SPI_BOOT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
+
+#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
+#endif
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
-#elif CONFIG_SYS_USE_SERIALFLASH
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
-
-#endif
-
#endif
#include "at91-sama5_common.h"
+#define CONFIG_MISC_INIT_R
+
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_BASE 0x80000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_ATMEL_LCD_RGB565
#endif
-#ifdef CONFIG_SYS_USE_SERIALFLASH
-/* override the bootcmd, bootargs and other configuration for spi flash env */
-#elif CONFIG_SYS_USE_NANDFLASH
-/* override the bootcmd, bootargs and other configuration for nandflash env */
-#elif CONFIG_SYS_USE_MMC
-/* override the bootcmd, bootargs and other configuration for sd/mmc env */
-#endif
-
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-#ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#elif CONFIG_SYS_USE_NANDFLASH
+#elif CONFIG_SPI_BOOT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
+
+#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
+#endif
#define CONFIG_PMECC_CAP 8
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
-#elif CONFIG_SYS_USE_SERIALFLASH
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
-
-#endif
#endif
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_BASE 0x80000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_ATMEL_HLCD
#define CONFIG_ATMEL_LCD_RGB565
-#ifdef CONFIG_SYS_USE_SERIALFLASH
-/* override the bootcmd, bootargs and other configuration for spi flash env*/
-#elif CONFIG_SYS_USE_NANDFLASH
-/* override the bootcmd, bootargs and other configuration for nandflash env*/
-#elif CONFIG_SYS_USE_MMC
-/* override the bootcmd, bootargs and other configuration for sd/mmc env */
-#endif
-
/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-#ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#elif CONFIG_SYS_USE_NANDFLASH
+#elif CONFIG_SPI_BOOT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
+
+#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
+#endif
#define CONFIG_PMECC_CAP 8
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
-#elif CONFIG_SYS_USE_SERIALFLASH
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
-
-#endif
#endif
* DRAM
*/
-#define CONFIG_SDRC
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
#define CONFIG_SYS_TEXT_BASE 0x80008000
-#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
-
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
/* **** PISMO SUPPORT *** */
#define CONFIG_NAND_OMAP_GPMC
-#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
/* Redundant Environment */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x180000
+#define CONFIG_ENV_ADDR 0x180000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
2 * CONFIG_SYS_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
* High Level Configuration Options
*/
-#define CONFIG_SDRC /* Has an SDRC controller */
-
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Framebuffer */
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
-#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>
-/* The chip has SDRC controller */
-#define CONFIG_SDRC
-
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
*/
#define CONFIG_SYS_TEXT_BASE 0x80100000
-#define CONFIG_SDRC /* The chip has SDRC controller */
-
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
/* serial console */
#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_USART3
-#define CONFIG_USART_ID ATMEL_ID_USART3
+#define CONFIG_USART_BASE 0xfc00c000
+#define CONFIG_USART_ID 30
+
+/* Timer */
+#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x4000000
#define CONFIG_SYS_INIT_SP_ADDR \
#ifdef CONFIG_CMD_MMC
#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_GENERIC_ATMEL_MCI
-#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1
+#define ATMEL_BASE_MMCI 0xfc000000
#define CONFIG_SYS_MMC_CLK_OD 500000
/* For generating MMC partitions */
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_MACB_SEARCH_PHY
-#ifdef CONFIG_SYS_USE_SERIALFLASH
+#ifdef CONFIG_SPI_BOOT
/* bootstrap + u-boot + env + linux in serial flash */
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
--- /dev/null
+/*
+ * Copyright (C) 2017 Amarula Solutions
+ *
+ * Configuration settings for Amarula Vyasa RK3288.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3288_common.h>
+
+#undef BOOT_TARGET_DEVICES
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#undef CONFIG_CMD_USB_MASS_STORAGE
+
+#endif
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#endif
int ofnode_read_resource_byname(ofnode node, const char *name,
struct resource *res);
+/**
+ * ofnode_for_each_subnode() - iterate over all subnodes of a parent
+ *
+ * @node: child node (ofnode, lvalue)
+ * @parent: parent node (ofnode)
+ *
+ * This is a wrapper around a for loop and is used like so:
+ *
+ * ofnode node;
+ *
+ * ofnode_for_each_subnode(node, parent) {
+ * Use node
+ * ...
+ * }
+ *
+ * Note that this is implemented as a macro and @node is used as
+ * iterator in the loop. The parent variable can be a constant or even a
+ * literal.
+ */
+#define ofnode_for_each_subnode(node, parent) \
+ for (node = ofnode_first_subnode(parent); \
+ ofnode_valid(node); \
+ node = ofnode_next_subnode(node))
+
#endif
*/
fdt_addr_t dev_read_addr(struct udevice *dev);
+/**
+ * dev_read_addr_ptr() - Get the reg property of a device
+ * as a pointer
+ *
+ * @dev: Device to read from
+ *
+ * @return pointer or NULL if not found
+ */
+void *dev_read_addr_ptr(struct udevice *dev);
+
/**
* dev_read_addr_size() - get address and size from a device property
*
return devfdt_get_addr(dev);
}
+static inline void *dev_read_addr_ptr(struct udevice *dev)
+{
+ return devfdt_get_addr_ptr(dev);
+}
+
static inline fdt_addr_t dev_read_addr_size(struct udevice *dev,
const char *propname,
fdt_size_t *sizep)
*/
int dm_scan_fdt(const void *blob, bool pre_reloc_only);
+/**
+ * dm_extended_scan_fdt() - Scan the device tree and bind drivers
+ *
+ * This calls dm_scna_dft() which scans the device tree and creates a driver
+ * for each node. the top-level subnodes are examined and also all sub-nodes
+ * of "clocks" node.
+ *
+ * @blob: Pointer to device tree blob
+ * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
+ * flag. If false bind all drivers.
+ * @return 0 if OK, -ve on error
+ */
+int dm_extended_scan_fdt(const void *blob, bool pre_reloc_only);
+
/**
* dm_scan_other() - Scan for other devices
*
*/
#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val)
+/* DRA7 IODELAY configuration parameters */
+#define A_DELAY_PS(val) ((val) & 0xffff)
+#define G_DELAY_PS(val) ((val) & 0xffff)
#endif
/* These structures may only be used in SPL */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
-struct phandle_2_cell {
+struct phandle_0_arg {
const void *node;
- int id;
+ int arg[0];
};
-#include <generated/dt-structs.h>
+
+struct phandle_1_arg {
+ const void *node;
+ int arg[1];
+};
+
+struct phandle_2_arg {
+ const void *node;
+ int arg[2];
+};
+#include <generated/dt-structs-gen.h>
#endif
#endif
"setenv fdtfile dra72-evm.dtb; fi;" \
"if test $board_name = dra71x; then " \
"setenv fdtfile dra71-evm.dtb; fi;" \
+ "if test $board_name = dra76x; then " \
+ "setenv fdtfile dra76-evm.dtb; fi;" \
"if test $board_name = beagle_x15; then " \
"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
"if test $board_name = beagle_x15_revb1; then " \
"setenv fdtfile am57xx-beagle-x15-revb1.dtb; fi;" \
+ "if test $board_name = beagle_x15_revc; then " \
+ "setenv fdtfile am57xx-beagle-x15-revc.dtb; fi;" \
"if test $board_name = am572x_idk; then " \
"setenv fdtfile am572x-idk.dtb; fi;" \
"if test $board_name = am57xx_evm; then " \
#define _FAT_H_
#include <asm/byteorder.h>
+#include <fs.h>
#define CONFIG_SUPPORT_VFAT
/* Maximum Long File Name length supported here is 128 UTF-16 code units */
*/
#define LAST_LONG_ENTRY_MASK 0x40
-/* Flags telling whether we should read a file or list a directory */
-#define LS_NO 0
-#define LS_YES 1
-#define LS_DIR 1
-#define LS_ROOT 2
-
#define ISDIRDELIM(c) ((c) == '/' || (c) == '\\')
#define FSTYPE_NONE (-1)
/* Boot sign comes last, 2 bytes */
} volume_info;
+/* see dir_entry::lcase: */
+#define CASE_LOWER_BASE 8 /* base (name) is lower case */
+#define CASE_LOWER_EXT 16 /* extension is lower case */
+
typedef struct dir_entry {
char name[8],ext[3]; /* Name and extension */
__u8 attr; /* Attribute bits */
- __u8 lcase; /* Case for base and extension */
+ __u8 lcase; /* Case for name and ext (CASE_LOWER_x) */
__u8 ctime_ms; /* Creation time, milliseconds */
__u16 ctime; /* Creation time */
__u16 cdate; /* Creation date */
__u16 clust_size; /* Size of clusters in sectors */
int data_begin; /* The sector of the first cluster, can be negative */
int fatbufnum; /* Used by get_fatent, init to -1 */
+ int rootdir_size; /* Size of root dir for non-FAT32 */
+ __u32 root_cluster; /* First cluster of root dir for FAT32 */
} fsdata;
-typedef int (file_detectfs_func)(void);
-typedef int (file_ls_func)(const char *dir);
-typedef int (file_read_func)(const char *filename, void *buffer,
- int maxsize);
-
-struct filesystem {
- file_detectfs_func *detect;
- file_ls_func *ls;
- file_read_func *read;
- const char name[12];
-};
-
-/* FAT tables */
-file_detectfs_func file_fat_detectfs;
-file_ls_func file_fat_ls;
-file_read_func file_fat_read;
-
-/* Currently this doesn't check if the dir exists or is valid... */
-int file_cd(const char *path);
+static inline u32 clust_to_sect(fsdata *fsdata, u32 clust)
+{
+ return fsdata->data_begin + clust * fsdata->clust_size;
+}
+
+static inline u32 sect_to_clust(fsdata *fsdata, u32 sect)
+{
+ return (sect - fsdata->data_begin) / fsdata->clust_size;
+}
+
int file_fat_detectfs(void);
-int file_fat_ls(const char *dir);
int fat_exists(const char *filename);
int fat_size(const char *filename, loff_t *size);
int file_fat_read_at(const char *filename, loff_t pos, void *buffer,
loff_t maxsize, loff_t *actread);
int file_fat_read(const char *filename, void *buffer, int maxsize);
-const char *file_getfsname(int idx);
int fat_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info);
int fat_register_device(struct blk_desc *dev_desc, int part_no);
loff_t *actwrite);
int fat_read_file(const char *filename, void *buf, loff_t offset, loff_t len,
loff_t *actread);
+int fat_opendir(const char *filename, struct fs_dir_stream **dirsp);
+int fat_readdir(struct fs_dir_stream *dirs, struct fs_dirent **dentp);
+void fat_closedir(struct fs_dir_stream *dirs);
void fat_close(void);
#endif /* _FAT_H_ */
int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width,
u32 height, u32 stride, const char *format);
+int fdt_overlay_apply_verbose(void *fdt, void *fdto);
+
#endif /* ifdef CONFIG_OF_LIBFDT */
#ifdef USE_HOSTCC
#define FDT_ADDR_T_NONE (-1ULL)
#define fdt_addr_to_cpu(reg) be64_to_cpu(reg)
#define fdt_size_to_cpu(reg) be64_to_cpu(reg)
+typedef fdt64_t fdt_val_t;
#else
#define FDT_ADDR_T_NONE (-1U)
#define fdt_addr_to_cpu(reg) be32_to_cpu(reg)
#define fdt_size_to_cpu(reg) be32_to_cpu(reg)
+typedef fdt32_t fdt_val_t;
#endif
/* Information obtained about memory from the FDT */
*/
int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype);
+/*
+ * fs_set_blk_dev_with_part - Set current block device + partition
+ *
+ * Similar to fs_set_blk_dev(), but useful for cases where you already
+ * know the blk_desc and part number.
+ *
+ * Returns 0 on success.
+ * Returns non-zero if invalid partition or error accessing the disk.
+ */
+int fs_set_blk_dev_with_part(struct blk_desc *desc, int part);
+
/*
* Print the list of files on the partition previously set by fs_set_blk_dev(),
* in directory "dirname".
int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len,
loff_t *actwrite);
+/*
+ * Directory entry types, matches the subset of DT_x in posix readdir()
+ * which apply to u-boot.
+ */
+#define FS_DT_DIR 4 /* directory */
+#define FS_DT_REG 8 /* regular file */
+#define FS_DT_LNK 10 /* symbolic link */
+
+/*
+ * A directory entry, returned by fs_readdir(). Returns information
+ * about the file/directory at the current directory entry position.
+ */
+struct fs_dirent {
+ unsigned type; /* one of FS_DT_x (not a mask) */
+ loff_t size; /* size in bytes */
+ char name[256];
+};
+
+/* Note: fs_dir_stream should be treated as opaque to the user of fs layer */
+struct fs_dir_stream {
+ /* private to fs. layer: */
+ struct blk_desc *desc;
+ int part;
+};
+
+/*
+ * fs_opendir - Open a directory
+ *
+ * @filename: the path to directory to open
+ * @return a pointer to the directory stream or NULL on error and errno
+ * set appropriately
+ */
+struct fs_dir_stream *fs_opendir(const char *filename);
+
+/*
+ * fs_readdir - Read the next directory entry in the directory stream.
+ *
+ * Works in an analogous way to posix readdir(). The previously returned
+ * directory entry is no longer valid after calling fs_readdir() again.
+ * After fs_closedir() is called, the returned directory entry is no
+ * longer valid.
+ *
+ * @dirs: the directory stream
+ * @return the next directory entry (only valid until next fs_readdir() or
+ * fs_closedir() call, do not attempt to free()) or NULL if the end of
+ * the directory is reached.
+ */
+struct fs_dirent *fs_readdir(struct fs_dir_stream *dirs);
+
+/*
+ * fs_closedir - close a directory stream
+ *
+ * @dirs: the directory stream
+ */
+void fs_closedir(struct fs_dir_stream *dirs);
+
/*
* Common implementation for various filesystem commands, optionally limited
* to a specific filesystem type via the fstype parameter.
void wriop_dpmac_enable(int);
phy_interface_t wriop_dpmac_enet_if(int, int);
void wriop_init_dpmac_qsgmii(int, int);
+void wriop_init_rgmii(void);
+void wriop_init_dpmac_enet_if(int , phy_interface_t);
#endif /* __LDPAA_WRIOP_H */
u8 res_e5c[164];
u32 debug[64]; /* debug_1 to debug_64 */
};
+
+#ifdef CONFIG_SYS_FSL_HAS_CCI400
+#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
+#define CCI400_CTRLORD_EN_BARRIER 0
+#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
+#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
+#define CCI400_SNOOP_REQ_EN 0x00000001
+
+/* CCI-400 registers */
+struct ccsr_cci400 {
+ u32 ctrl_ord; /* Control Override */
+ u32 spec_ctrl; /* Speculation Control */
+ u32 secure_access; /* Secure Access */
+ u32 status; /* Status */
+ u32 impr_err; /* Imprecise Error */
+ u8 res_14[0x100 - 0x14];
+ u32 pmcr; /* Performance Monitor Control */
+ u8 res_104[0xfd0 - 0x104];
+ u32 pid[8]; /* Peripheral ID */
+ u32 cid[4]; /* Component ID */
+ struct {
+ u32 snoop_ctrl; /* Snoop Control */
+ u32 sha_ord; /* Shareable Override */
+ u8 res_1008[0x1100 - 0x1008];
+ u32 rc_qos_ord; /* read channel QoS Value Override */
+ u32 wc_qos_ord; /* read channel QoS Value Override */
+ u8 res_1108[0x110c - 0x1108];
+ u32 qos_ctrl; /* QoS Control */
+ u32 max_ot; /* Max OT */
+ u8 res_1114[0x1130 - 0x1114];
+ u32 target_lat; /* Target Latency */
+ u32 latency_regu; /* Latency Regulation */
+ u32 qos_range; /* QoS Range */
+ u8 res_113c[0x2000 - 0x113c];
+ } slave[5]; /* Slave Interface */
+ u8 res_6000[0x9004 - 0x6000];
+ u32 cycle_counter; /* Cycle counter */
+ u32 count_ctrl; /* Count Control */
+ u32 overflow_status; /* Overflow Flag Status */
+ u8 res_9010[0xa000 - 0x9010];
+ struct {
+ u32 event_select; /* Event Select */
+ u32 event_count; /* Event Count */
+ u32 counter_ctrl; /* Counter Control */
+ u32 overflow_status; /* Overflow Flag Status */
+ u8 res_a010[0xb000 - 0xa010];
+ } pcounter[4]; /* Performance Counter */
+ u8 res_e004[0x10000 - 0xe004];
+};
+#endif
+
#endif /* __FSL_IMMAP_H */
IH_TYPE_VYBRIDIMAGE, /* VYBRID .vyb Image */
IH_TYPE_TEE, /* Trusted Execution Environment OS Image */
IH_TYPE_FIRMWARE_IVT, /* Firmware Image with HABv4 IVT */
+ IH_TYPE_PMMC, /* TI Power Management Micro-Controller Firmware */
IH_TYPE_COUNT, /* Number of image types */
};
int boot_get_setup_fit(bootm_headers_t *images, uint8_t arch,
ulong *setup_start, ulong *setup_len);
+/**
+ * boot_get_fdt_fit() - load a DTB from a FIT file (applying overlays)
+ *
+ * This deals with all aspects of loading an DTB from a FIT.
+ * The correct base image based on configuration will be selected, and
+ * then any overlays specified will be applied (as present in fit_uname_configp).
+ *
+ * @param images Boot images structure
+ * @param addr Address of FIT in memory
+ * @param fit_unamep On entry this is the requested image name
+ * (e.g. "kernel@1") or NULL to use the default. On exit
+ * points to the selected image name
+ * @param fit_uname_configp On entry this is the requested configuration
+ * name (e.g. "conf@1") or NULL to use the default. On
+ * exit points to the selected configuration name.
+ * @param arch Expected architecture (IH_ARCH_...)
+ * @param datap Returns address of loaded image
+ * @param lenp Returns length of loaded image
+ *
+ * @return node offset of base image, or -ve error code on error
+ */
+int boot_get_fdt_fit(bootm_headers_t *images, ulong addr,
+ const char **fit_unamep, const char **fit_uname_configp,
+ int arch, ulong *datap, ulong *lenp);
+
/**
* fit_image_load() - load an image from a FIT
*
--- /dev/null
+#ifndef _LINUX_DMA_DIRECTION_H
+#define _LINUX_DMA_DIRECTION_H
+/*
+ * These definitions mirror those in pci.h, so they can be used
+ * interchangeably with their PCI_ counterparts.
+ */
+enum dma_data_direction {
+ DMA_BIDIRECTIONAL = 0,
+ DMA_TO_DEVICE = 1,
+ DMA_FROM_DEVICE = 2,
+ DMA_NONE = 3,
+};
+#endif
#include <linux/types.h>
#include <asm/io.h>
+static inline u8 ioread8(const volatile void __iomem *addr)
+{
+ return readb(addr);
+}
+
+static inline u16 ioread16(const volatile void __iomem *addr)
+{
+ return readw(addr);
+}
+
+static inline u32 ioread32(const volatile void __iomem *addr)
+{
+ return readl(addr);
+}
+
+#ifdef CONFIG_64BIT
+static inline u64 ioread64(const volatile void __iomem *addr)
+{
+ return readq(addr);
+}
+#endif /* CONFIG_64BIT */
+
+static inline void iowrite8(u8 value, volatile void __iomem *addr)
+{
+ writeb(value, addr);
+}
+
+static inline void iowrite16(u16 value, volatile void __iomem *addr)
+{
+ writew(value, addr);
+}
+
+static inline void iowrite32(u32 value, volatile void __iomem *addr)
+{
+ writel(value, addr);
+}
+
+#ifdef CONFIG_64BIT
+static inline void iowrite64(u64 value, volatile void __iomem *addr)
+{
+ writeq(value, addr);
+}
+#endif /* CONFIG_64BIT */
+
#ifndef CONFIG_HAVE_ARCH_IOREMAP
static inline void __iomem *ioremap(resource_size_t offset,
resource_size_t size)
#define LDO2_CTRL 0x52
#define LDO2_VOLTAGE 0x53
+/* LDO2 control/voltage */
+#define LDO4_CTRL 0x5e
+#define LDO4_VOLTAGE 0x5f
+
/* LDO9 control/voltage */
#define LDO9_CTRL 0x60
#define LDO9_VOLTAGE 0x61
}
void palmas_init_settings(void);
-int palmas_mmc1_poweron_ldo(uint voltage);
+int palmas_mmc1_poweron_ldo(uint ldo_volt, uint ldo_ctrl, uint voltage);
int lp873x_mmc1_poweron_ldo(uint voltage);
int twl603x_mmc1_set_ldo9(u8 vsel);
int twl603x_audio_power(u8 on);
/* disk/part.c */
int part_get_info(struct blk_desc *dev_desc, int part, disk_partition_t *info);
+/**
+ * part_get_info_whole_disk() - get partition info for the special case of
+ * a partition occupying the entire disk.
+ */
+int part_get_info_whole_disk(struct blk_desc *dev_desc, disk_partition_t *info);
+
void part_print(struct blk_desc *dev_desc);
void part_init(struct blk_desc *dev_desc);
void dev_print(struct blk_desc *dev_desc);
static inline int part_get_info(struct blk_desc *dev_desc, int part,
disk_partition_t *info) { return -1; }
+static inline int part_get_info_whole_disk(struct blk_desc *dev_desc,
+ disk_partition_t *info)
+{ return -1; }
static inline void part_print(struct blk_desc *dev_desc) {}
static inline void part_init(struct blk_desc *dev_desc) {}
static inline void dev_print(struct blk_desc *dev_desc) {}
* @count: Number of pairs (e.g. 1 if the regmap has a single entry)
* @mapp: Returns allocated map
*/
-int regmap_init_mem_platdata(struct udevice *dev, u32 *reg, int count,
+int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count,
struct regmap **mapp);
/**
#ifndef __SYSCON_H
#define __SYSCON_H
+#include <fdtdec.h>
+
/**
* struct syscon_uc_info - Information stored by the syscon UCLASS_UCLASS
*
* We don't support 64-bit machines. If they are so resource-contrained that
* they need to use OF_PLATDATA, something is horribly wrong with the
* education of our hardware engineers.
+ *
+ * Update: 64-bit is now supported and we have an education crisis.
*/
struct syscon_base_platdata {
- u32 reg[2];
+ fdt_val_t reg[2];
};
#endif
bool "Enable LZO decompression support"
help
This enables support for LZO compression algorithm.r
+
+config SPL_GZIP
+ bool "Enable gzip decompression support for SPL build"
+ select SPL_ZLIB
+ help
+ This enables support for GZIP compression altorithm for SPL boot.
+
+config SPL_ZLIB
+ bool
+ help
+ This enables compression lib for SPL boot.
+
endmenu
config ERRNO_STR
obj-$(CONFIG_EFI_LOADER) += efi_loader/
obj-$(CONFIG_LZMA) += lzma/
obj-$(CONFIG_LZO) += lzo/
-obj-$(CONFIG_ZLIB) += zlib/
obj-$(CONFIG_BZIP2) += bzip2/
obj-$(CONFIG_TIZEN) += tizen/
obj-$(CONFIG_FIT) += libfdt/
obj-$(CONFIG_OF_LIVE) += of_live.o
obj-$(CONFIG_CMD_DHRYSTONE) += dhry/
+obj-$(CONFIG_ARCH_AT91) += at91/
obj-$(CONFIG_AES) += aes.o
+obj-y += charset.o
obj-$(CONFIG_USB_TTY) += circbuf.o
obj-y += crc7.o
obj-y += crc8.o
obj-$(CONFIG_ERRNO_STR) += errno_str.o
obj-$(CONFIG_FIT) += fdtdec_common.o
obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o
-obj-$(CONFIG_GZIP) += gunzip.o
obj-$(CONFIG_GZIP_COMPRESSED) += gzip.o
obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o
obj-y += initcall.o
obj-$(CONFIG_SHA1) += sha1.o
obj-$(CONFIG_SHA256) += sha256.o
+obj-$(CONFIG_$(SPL_)ZLIB) += zlib/
+obj-$(CONFIG_$(SPL_)GZIP) += gunzip.o
+
obj-$(CONFIG_$(SPL_TPL_)SAVEENV) += qsort.o
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
ifneq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy)
--- /dev/null
+#
+# Copyright (C) 2017 Microchip
+# Wenyou.Yang <wenyou.yang@microchip.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_ARCH_AT91) += at91.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Microchip
+ * Wenyou.Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <atmel_lcd.h>
+
+#include "atmel_logo_8bpp.h"
+#include "microchip_logo_8bpp.h"
+
+void atmel_logo_info(vidinfo_t *info)
+{
+ info->logo_width = ATMEL_LOGO_8BPP_WIDTH;
+ info->logo_height = ATMEL_LOGO_8BPP_HEIGHT;
+ info->logo_x_offset = ATMEL_LOGO_8BPP_X_OFFSET;
+ info->logo_y_offset = ATMEL_LOGO_8BPP_X_OFFSET;
+ info->logo_addr = (u_long)atmel_logo_8bpp;
+}
+
+void microchip_logo_info(vidinfo_t *info)
+{
+ info->logo_width = MICROCHIP_LOGO_8BPP_WIDTH;
+ info->logo_height = MICROCHIP_LOGO_8BPP_HEIGHT;
+ info->logo_x_offset = MICROCHIP_LOGO_8BPP_X_OFFSET;
+ info->logo_y_offset = MICROCHIP_LOGO_8BPP_X_OFFSET;
+ info->logo_addr = (u_long)microchip_logo_8bpp;
+}
--- /dev/null
+/*
+ * Copyright (C) 2017 Microchip
+ * Wenyou.Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ATMEL_LOGO_8BPP_H__
+#define __ATMEL_LOGO_8BPP_H__
+
+#define ATMEL_LOGO_8BPP_WIDTH 240
+#define ATMEL_LOGO_8BPP_HEIGHT 60
+
+#define ATMEL_LOGO_8BPP_X_OFFSET 0
+#define ATMEL_LOGO_8BPP_Y_OFFSET 0
+
+/* Format: BMP 8BPP 240*60 */
+unsigned char atmel_logo_8bpp[] = {
+ 0x42, 0x4d, 0x76, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x36, 0x04,
+ 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x3c, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xc4, 0x0e, 0x00, 0x00, 0xc4, 0x0e, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xc1, 0x79, 0x00, 0xff, 0xc1, 0x7a,
+ 0x01, 0xff, 0xc2, 0x7a, 0x02, 0xff, 0xc2, 0x7b, 0x04, 0xff, 0xc2, 0x7c,
+ 0x05, 0xff, 0xc3, 0x7c, 0x06, 0xff, 0xc3, 0x7d, 0x08, 0xff, 0xc3, 0x7e,
+ 0x09, 0xff, 0xc4, 0x7e, 0x0a, 0xff, 0xc4, 0x7f, 0x0c, 0xff, 0xc4, 0x80,
+ 0x0d, 0xff, 0xc5, 0x81, 0x0f, 0xff, 0xc5, 0x81, 0x10, 0xff, 0xc5, 0x82,
+ 0x11, 0xff, 0xc6, 0x82, 0x12, 0xff, 0xc6, 0x83, 0x14, 0xff, 0xc6, 0x84,
+ 0x15, 0xff, 0xc7, 0x85, 0x17, 0xff, 0xc7, 0x85, 0x18, 0xff, 0xc7, 0x86,
+ 0x1a, 0xff, 0xc8, 0x87, 0x1b, 0xff, 0xc8, 0x87, 0x1c, 0xff, 0xc8, 0x88,
+ 0x1d, 0xff, 0xc9, 0x89, 0x1f, 0xff, 0xc9, 0x8a, 0x1f, 0xff, 0xc8, 0x89,
+ 0x20, 0xff, 0xc9, 0x8a, 0x21, 0xff, 0xca, 0x8b, 0x23, 0xff, 0xca, 0x8c,
+ 0x23, 0xff, 0xc9, 0x8c, 0x24, 0xff, 0xca, 0x8c, 0x25, 0xff, 0xca, 0x8e,
+ 0x28, 0xff, 0xcb, 0x8e, 0x29, 0xff, 0xcb, 0x90, 0x2b, 0xff, 0xcc, 0x90,
+ 0x2b, 0xff, 0xcb, 0x90, 0x2c, 0xff, 0xcc, 0x90, 0x2e, 0xff, 0xcc, 0x91,
+ 0x30, 0xff, 0xcc, 0x92, 0x30, 0xff, 0xcd, 0x92, 0x31, 0xff, 0xcd, 0x94,
+ 0x33, 0xff, 0xcd, 0x93, 0x34, 0xff, 0xcd, 0x94, 0x34, 0xff, 0xce, 0x94,
+ 0x35, 0xff, 0xce, 0x96, 0x37, 0xff, 0xce, 0x96, 0x38, 0xff, 0xcf, 0x97,
+ 0x39, 0xff, 0xcf, 0x98, 0x3d, 0xff, 0xd0, 0x99, 0x3d, 0xff, 0xd0, 0x9a,
+ 0x40, 0xff, 0xd1, 0x9b, 0x41, 0xff, 0xd1, 0x9c, 0x42, 0xff, 0xd1, 0x9c,
+ 0x44, 0xff, 0xd2, 0x9d, 0x46, 0xff, 0xd2, 0x9e, 0x47, 0xff, 0xd2, 0x9e,
+ 0x48, 0xff, 0xd3, 0x9f, 0x49, 0xff, 0xd3, 0xa0, 0x4a, 0xff, 0xd3, 0xa0,
+ 0x4c, 0xff, 0xd4, 0xa2, 0x4e, 0xff, 0xd4, 0xa2, 0x50, 0xff, 0xd5, 0xa4,
+ 0x52, 0xff, 0xd5, 0xa4, 0x55, 0xff, 0xd5, 0xa6, 0x56, 0xff, 0xd6, 0xa6,
+ 0x57, 0xff, 0xd6, 0xa6, 0x58, 0xff, 0xd7, 0xa8, 0x5a, 0xff, 0xd7, 0xa8,
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+ 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba,
+ 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba,
+ 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba,
+ 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba,
+ 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba,
+ 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba,
+ 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xba, 0xb2, 0x2f,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0xa8, 0xba, 0xba, 0xba,
+ 0xba, 0xba, 0xb6, 0x8f, 0x3f, 0x31, 0x34, 0x4c, 0xa0, 0xba
+};
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2017 Microchip
+ * Wenyou.Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MICROCHIP_LOGO_8BPP_H__
+#define __MICROCHIP_LOGO_8BPP_H__
+
+#define MICROCHIP_LOGO_8BPP_WIDTH 208
+#define MICROCHIP_LOGO_8BPP_HEIGHT 56
+
+#define MICROCHIP_LOGO_8BPP_X_OFFSET 0
+#define MCIROCHIP_LOGO_8BPP_Y_OFFSET 0
+
+/* Format: BMP 8BPP 240*60 */
+unsigned char microchip_logo_8bpp[] = {
+ 0x42, 0x4d, 0xb6, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x36, 0x04,
+ 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0xd0, 0x00, 0x00, 0x00, 0x38, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2d,
+ 0x00, 0x00, 0x74, 0x12, 0x00, 0x00, 0x74, 0x12, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x80, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x80, 0x00, 0x80, 0x00,
+ 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x80, 0x00, 0x00, 0xc0, 0xc0,
+ 0xc0, 0x00, 0xc0, 0xdc, 0xc0, 0x00, 0xf0, 0xca, 0xa6, 0x00, 0x00, 0x20,
+ 0x40, 0x00, 0x00, 0x20, 0x60, 0x00, 0x00, 0x20, 0x80, 0x00, 0x00, 0x20,
+ 0xa0, 0x00, 0x00, 0x20, 0xc0, 0x00, 0x00, 0x20, 0xe0, 0x00, 0x00, 0x40,
+ 0x00, 0x00, 0x00, 0x40, 0x20, 0x00, 0x00, 0x40, 0x40, 0x00, 0x00, 0x40,
+ 0x60, 0x00, 0x00, 0x40, 0x80, 0x00, 0x00, 0x40, 0xa0, 0x00, 0x00, 0x40,
+ 0xc0, 0x00, 0x00, 0x40, 0xe0, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x60,
+ 0x20, 0x00, 0x00, 0x60, 0x40, 0x00, 0x00, 0x60, 0x60, 0x00, 0x00, 0x60,
+ 0x80, 0x00, 0x00, 0x60, 0xa0, 0x00, 0x00, 0x60, 0xc0, 0x00, 0x00, 0x60,
+ 0xe0, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x20, 0x00, 0x00, 0x80,
+ 0x40, 0x00, 0x00, 0x80, 0x60, 0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x80,
+ 0xa0, 0x00, 0x00, 0x80, 0xc0, 0x00, 0x00, 0x80, 0xe0, 0x00, 0x00, 0xa0,
+ 0x00, 0x00, 0x00, 0xa0, 0x20, 0x00, 0x00, 0xa0, 0x40, 0x00, 0x00, 0xa0,
+ 0x60, 0x00, 0x00, 0xa0, 0x80, 0x00, 0x00, 0xa0, 0xa0, 0x00, 0x00, 0xa0,
+ 0xc0, 0x00, 0x00, 0xa0, 0xe0, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0xc0,
+ 0x20, 0x00, 0x00, 0xc0, 0x40, 0x00, 0x00, 0xc0, 0x60, 0x00, 0x00, 0xc0,
+ 0x80, 0x00, 0x00, 0xc0, 0xa0, 0x00, 0x00, 0xc0, 0xc0, 0x00, 0x00, 0xc0,
+ 0xe0, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0xe0, 0x20, 0x00, 0x00, 0xe0,
+ 0x40, 0x00, 0x00, 0xe0, 0x60, 0x00, 0x00, 0xe0, 0x80, 0x00, 0x00, 0xe0,
+ 0xa0, 0x00, 0x00, 0xe0, 0xc0, 0x00, 0x00, 0xe0, 0xe0, 0x00, 0x40, 0x00,
+ 0x00, 0x00, 0x40, 0x00, 0x20, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00,
+ 0x60, 0x00, 0x40, 0x00, 0x80, 0x00, 0x40, 0x00, 0xa0, 0x00, 0x40, 0x00,
+ 0xc0, 0x00, 0x40, 0x00, 0xe0, 0x00, 0x40, 0x20, 0x00, 0x00, 0x40, 0x20,
+ 0x20, 0x00, 0x40, 0x20, 0x40, 0x00, 0x40, 0x20, 0x60, 0x00, 0x40, 0x20,
+ 0x80, 0x00, 0x40, 0x20, 0xa0, 0x00, 0x40, 0x20, 0xc0, 0x00, 0x40, 0x20,
+ 0xe0, 0x00, 0x40, 0x40, 0x00, 0x00, 0x40, 0x40, 0x20, 0x00, 0x40, 0x40,
+ 0x40, 0x00, 0x40, 0x40, 0x60, 0x00, 0x40, 0x40, 0x80, 0x00, 0x40, 0x40,
+ 0xa0, 0x00, 0x40, 0x40, 0xc0, 0x00, 0x40, 0x40, 0xe0, 0x00, 0x40, 0x60,
+ 0x00, 0x00, 0x40, 0x60, 0x20, 0x00, 0x40, 0x60, 0x40, 0x00, 0x40, 0x60,
+ 0x60, 0x00, 0x40, 0x60, 0x80, 0x00, 0x40, 0x60, 0xa0, 0x00, 0x40, 0x60,
+ 0xc0, 0x00, 0x40, 0x60, 0xe0, 0x00, 0x40, 0x80, 0x00, 0x00, 0x40, 0x80,
+ 0x20, 0x00, 0x40, 0x80, 0x40, 0x00, 0x40, 0x80, 0x60, 0x00, 0x40, 0x80,
+ 0x80, 0x00, 0x40, 0x80, 0xa0, 0x00, 0x40, 0x80, 0xc0, 0x00, 0x40, 0x80,
+ 0xe0, 0x00, 0x40, 0xa0, 0x00, 0x00, 0x40, 0xa0, 0x20, 0x00, 0x40, 0xa0,
+ 0x40, 0x00, 0x40, 0xa0, 0x60, 0x00, 0x40, 0xa0, 0x80, 0x00, 0x40, 0xa0,
+ 0xa0, 0x00, 0x40, 0xa0, 0xc0, 0x00, 0x40, 0xa0, 0xe0, 0x00, 0x40, 0xc0,
+ 0x00, 0x00, 0x40, 0xc0, 0x20, 0x00, 0x40, 0xc0, 0x40, 0x00, 0x40, 0xc0,
+ 0x60, 0x00, 0x40, 0xc0, 0x80, 0x00, 0x40, 0xc0, 0xa0, 0x00, 0x40, 0xc0,
+ 0xc0, 0x00, 0x40, 0xc0, 0xe0, 0x00, 0x40, 0xe0, 0x00, 0x00, 0x40, 0xe0,
+ 0x20, 0x00, 0x40, 0xe0, 0x40, 0x00, 0x40, 0xe0, 0x60, 0x00, 0x40, 0xe0,
+ 0x80, 0x00, 0x40, 0xe0, 0xa0, 0x00, 0x40, 0xe0, 0xc0, 0x00, 0x40, 0xe0,
+ 0xe0, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x20, 0x00, 0x80, 0x00,
+ 0x40, 0x00, 0x80, 0x00, 0x60, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
+ 0xa0, 0x00, 0x80, 0x00, 0xc0, 0x00, 0x80, 0x00, 0xe0, 0x00, 0x80, 0x20,
+ 0x00, 0x00, 0x80, 0x20, 0x20, 0x00, 0x80, 0x20, 0x40, 0x00, 0x80, 0x20,
+ 0x60, 0x00, 0x80, 0x20, 0x80, 0x00, 0x80, 0x20, 0xa0, 0x00, 0x80, 0x20,
+ 0xc0, 0x00, 0x80, 0x20, 0xe0, 0x00, 0x80, 0x40, 0x00, 0x00, 0x80, 0x40,
+ 0x20, 0x00, 0x80, 0x40, 0x40, 0x00, 0x80, 0x40, 0x60, 0x00, 0x80, 0x40,
+ 0x80, 0x00, 0x80, 0x40, 0xa0, 0x00, 0x80, 0x40, 0xc0, 0x00, 0x80, 0x40,
+ 0xe0, 0x00, 0x80, 0x60, 0x00, 0x00, 0x80, 0x60, 0x20, 0x00, 0x80, 0x60,
+ 0x40, 0x00, 0x80, 0x60, 0x60, 0x00, 0x80, 0x60, 0x80, 0x00, 0x80, 0x60,
+ 0xa0, 0x00, 0x80, 0x60, 0xc0, 0x00, 0x80, 0x60, 0xe0, 0x00, 0x80, 0x80,
+ 0x00, 0x00, 0x80, 0x80, 0x20, 0x00, 0x80, 0x80, 0x40, 0x00, 0x80, 0x80,
+ 0x60, 0x00, 0x80, 0x80, 0x80, 0x00, 0x80, 0x80, 0xa0, 0x00, 0x80, 0x80,
+ 0xc0, 0x00, 0x80, 0x80, 0xe0, 0x00, 0x80, 0xa0, 0x00, 0x00, 0x80, 0xa0,
+ 0x20, 0x00, 0x80, 0xa0, 0x40, 0x00, 0x80, 0xa0, 0x60, 0x00, 0x80, 0xa0,
+ 0x80, 0x00, 0x80, 0xa0, 0xa0, 0x00, 0x80, 0xa0, 0xc0, 0x00, 0x80, 0xa0,
+ 0xe0, 0x00, 0x80, 0xc0, 0x00, 0x00, 0x80, 0xc0, 0x20, 0x00, 0x80, 0xc0,
+ 0x40, 0x00, 0x80, 0xc0, 0x60, 0x00, 0x80, 0xc0, 0x80, 0x00, 0x80, 0xc0,
+ 0xa0, 0x00, 0x80, 0xc0, 0xc0, 0x00, 0x80, 0xc0, 0xe0, 0x00, 0x80, 0xe0,
+ 0x00, 0x00, 0x80, 0xe0, 0x20, 0x00, 0x80, 0xe0, 0x40, 0x00, 0x80, 0xe0,
+ 0x60, 0x00, 0x80, 0xe0, 0x80, 0x00, 0x80, 0xe0, 0xa0, 0x00, 0x80, 0xe0,
+ 0xc0, 0x00, 0x80, 0xe0, 0xe0, 0x00, 0xc0, 0x00, 0x00, 0x00, 0xc0, 0x00,
+ 0x20, 0x00, 0xc0, 0x00, 0x40, 0x00, 0xc0, 0x00, 0x60, 0x00, 0xc0, 0x00,
+ 0x80, 0x00, 0xc0, 0x00, 0xa0, 0x00, 0xc0, 0x00, 0xc0, 0x00, 0xc0, 0x00,
+ 0xe0, 0x00, 0xc0, 0x20, 0x00, 0x00, 0xc0, 0x20, 0x20, 0x00, 0xc0, 0x20,
+ 0x40, 0x00, 0xc0, 0x20, 0x60, 0x00, 0xc0, 0x20, 0x80, 0x00, 0xc0, 0x20,
+ 0xa0, 0x00, 0xc0, 0x20, 0xc0, 0x00, 0xc0, 0x20, 0xe0, 0x00, 0xc0, 0x40,
+ 0x00, 0x00, 0xc0, 0x40, 0x20, 0x00, 0xc0, 0x40, 0x40, 0x00, 0xc0, 0x40,
+ 0x60, 0x00, 0xc0, 0x40, 0x80, 0x00, 0xc0, 0x40, 0xa0, 0x00, 0xc0, 0x40,
+ 0xc0, 0x00, 0xc0, 0x40, 0xe0, 0x00, 0xc0, 0x60, 0x00, 0x00, 0xc0, 0x60,
+ 0x20, 0x00, 0xc0, 0x60, 0x40, 0x00, 0xc0, 0x60, 0x60, 0x00, 0xc0, 0x60,
+ 0x80, 0x00, 0xc0, 0x60, 0xa0, 0x00, 0xc0, 0x60, 0xc0, 0x00, 0xc0, 0x60,
+ 0xe0, 0x00, 0xc0, 0x80, 0x00, 0x00, 0xc0, 0x80, 0x20, 0x00, 0xc0, 0x80,
+ 0x40, 0x00, 0xc0, 0x80, 0x60, 0x00, 0xc0, 0x80, 0x80, 0x00, 0xc0, 0x80,
+ 0xa0, 0x00, 0xc0, 0x80, 0xc0, 0x00, 0xc0, 0x80, 0xe0, 0x00, 0xc0, 0xa0,
+ 0x00, 0x00, 0xc0, 0xa0, 0x20, 0x00, 0xc0, 0xa0, 0x40, 0x00, 0xc0, 0xa0,
+ 0x60, 0x00, 0xc0, 0xa0, 0x80, 0x00, 0xc0, 0xa0, 0xa0, 0x00, 0xc0, 0xa0,
+ 0xc0, 0x00, 0xc0, 0xa0, 0xe0, 0x00, 0xc0, 0xc0, 0x00, 0x00, 0xc0, 0xc0,
+ 0x20, 0x00, 0xc0, 0xc0, 0x40, 0x00, 0xc0, 0xc0, 0x60, 0x00, 0xc0, 0xc0,
+ 0x80, 0x00, 0xc0, 0xc0, 0xa0, 0x00, 0xf0, 0xfb, 0xff, 0x00, 0xa4, 0xa0,
+ 0xa0, 0x00, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0xff,
+ 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00,
+ 0xff, 0x00, 0xff, 0xff, 0x00, 0x00, 0xff, 0xff, 0xff, 0x00, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xef, 0xef,
+ 0xa7, 0x9f, 0x57, 0x57, 0x4f, 0x4f, 0x57, 0x57, 0x5f, 0xa7, 0xef, 0xef,
+ 0xf6, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xf6,
+ 0xa7, 0x5f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x57, 0xa7, 0xef, 0xf6, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xf6, 0xef, 0xa7, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x5f,
+ 0xef, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf6, 0xa7, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x9f, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x57, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x57, 0xaf,
+ 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xaf, 0x57, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x9f, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xa7, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0xef, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf6, 0x57, 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x0f, 0x0f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f,
+ 0x57, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0x0f, 0x0f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f,
+ 0xa7, 0xef, 0x9f, 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x0f, 0x0f, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xf6, 0x9f, 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x0f, 0x9f, 0xf6, 0xff, 0xf6, 0x9f, 0x0f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0xa7, 0xf6, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x57, 0x0f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x57, 0xef, 0xff, 0xff, 0xff, 0xf6,
+ 0x57, 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x57, 0xef,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x4f,
+ 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x4f, 0xaf, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xef, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x0f, 0x0f, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xa7, 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x0f, 0x5f, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa7, 0x0f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x9f, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x5f, 0x0f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x0f, 0x57, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xf6, 0x57, 0x0f, 0x4f, 0x4f, 0x4f, 0x0f, 0x57, 0xef, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6,
+ 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xf6, 0xf6, 0xf6,
+ 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0x57, 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0xa7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xa4, 0x5b, 0x5b, 0x5b, 0x07,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf7, 0x5b, 0x5b, 0x5b, 0xa4, 0xff, 0xf6, 0x9b, 0x5b,
+ 0x5b, 0xa4, 0xf6, 0xff, 0xff, 0xf6, 0xf7, 0x5b, 0x52, 0x52, 0x52, 0x52,
+ 0x52, 0x52, 0x52, 0x52, 0x52, 0xa4, 0x08, 0xff, 0xf6, 0xa4, 0x5b, 0x5b,
+ 0xa4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xf7, 0x5b, 0x5b, 0x9b,
+ 0x08, 0xff, 0xff, 0xf6, 0xf7, 0x5b, 0x52, 0x52, 0x52, 0x52, 0x52, 0x52,
+ 0x52, 0x52, 0x5b, 0xa4, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xa4, 0x5b,
+ 0x52, 0x52, 0x52, 0x52, 0x52, 0x52, 0x52, 0x52, 0x52, 0x9b, 0x08, 0xff,
+ 0xf6, 0xa4, 0x5b, 0x5b, 0xa4, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6,
+ 0xa4, 0x5b, 0x5b, 0x9b, 0xff, 0xf6, 0xa4, 0x5b, 0x5b, 0x5b, 0x07, 0xff,
+ 0xf7, 0x5b, 0x5b, 0x9b, 0x08, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x57,
+ 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9f,
+ 0x0f, 0x4f, 0x0f, 0x5f, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x08, 0x52,
+ 0x00, 0x00, 0x00, 0xa4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xa4, 0x5b,
+ 0xa4, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x52,
+ 0xff, 0x08, 0x00, 0x00, 0x00, 0x49, 0x08, 0xff, 0xf6, 0x5b, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5b, 0xf6,
+ 0xf6, 0x52, 0x00, 0x00, 0x52, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6,
+ 0x52, 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0x9b, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0xf6, 0xff, 0xff,
+ 0xf6, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x52, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x52, 0xf6, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf6, 0x49, 0x00, 0x00, 0x49, 0xff, 0xf6, 0x52, 0x00,
+ 0x00, 0x00, 0xf7, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xf6, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5f, 0x0f,
+ 0x4f, 0x0f, 0x4f, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0x57, 0x4f, 0x0f, 0x4f, 0xef, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x57, 0xef, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xff, 0xff, 0xff,
+ 0xf6, 0x52, 0x00, 0x00, 0x00, 0x9b, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5b,
+ 0x00, 0x00, 0x00, 0x9b, 0xff, 0x08, 0x00, 0x00, 0x00, 0x52, 0x08, 0xff,
+ 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x49, 0x07, 0xff, 0x52, 0x00, 0x00, 0x52, 0xf6, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf6, 0x5b, 0x00, 0x00, 0x00, 0x07, 0xff, 0x07, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xa4, 0xff, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0xf6, 0x52, 0x00, 0x00,
+ 0x52, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x49,
+ 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0xf7, 0xff, 0xa4, 0x00, 0x00, 0x00,
+ 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xf6, 0x57, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0x5f, 0x0f, 0x4f, 0x0f, 0xa7, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x5f, 0x0f, 0x4f, 0x0f, 0xa7, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x5f, 0x0f,
+ 0xa7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x9b,
+ 0xf6, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x49, 0x07, 0xff,
+ 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0xa4, 0xff, 0x08, 0x00, 0x00,
+ 0x00, 0x52, 0x08, 0xff, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xff, 0x52, 0x00, 0x00,
+ 0x52, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x5b, 0x00, 0x00, 0x00,
+ 0x07, 0xff, 0x9b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0xf6, 0xff, 0x52, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+ 0xf6, 0x52, 0x00, 0x00, 0x52, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6,
+ 0x52, 0x00, 0x00, 0x49, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0xf7, 0xff,
+ 0xa4, 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x0f, 0x5f, 0xf6, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x57, 0x4f, 0x0f, 0x57, 0xf6, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0x0f, 0x4f,
+ 0x0f, 0x57, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xaf, 0x0f, 0x4f, 0x5f, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9b,
+ 0x00, 0x00, 0x00, 0x5b, 0xf6, 0xff, 0xff, 0xf6, 0x5b, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xa4, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0xf7,
+ 0xff, 0x08, 0x00, 0x00, 0x00, 0x52, 0x08, 0xf6, 0x52, 0x00, 0x00, 0x00,
+ 0x49, 0x5b, 0x5b, 0x5b, 0x5b, 0x5b, 0x5b, 0x5b, 0x5b, 0x52, 0x5b, 0x08,
+ 0xf6, 0x52, 0x00, 0x00, 0x52, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0xf7,
+ 0x49, 0x00, 0x00, 0x49, 0x08, 0xff, 0x52, 0x00, 0x00, 0x00, 0x00, 0x52,
+ 0x5b, 0x5b, 0x5b, 0x5b, 0x5b, 0x49, 0x00, 0x00, 0x00, 0x49, 0x08, 0xf6,
+ 0x49, 0x00, 0x00, 0x00, 0x49, 0x5b, 0x5b, 0x5b, 0x5b, 0x5b, 0x5b, 0x5b,
+ 0x5b, 0x5b, 0x52, 0xf6, 0xf6, 0x52, 0x00, 0x00, 0x52, 0xf6, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x49, 0xff, 0xf6, 0x52, 0x00,
+ 0x00, 0x00, 0xf7, 0xff, 0xa4, 0x00, 0x00, 0x00, 0xa4, 0x07, 0xf7, 0xf7,
+ 0xf7, 0xf7, 0xf7, 0xf7, 0xf7, 0x07, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x4f, 0x0f,
+ 0xa7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x5f, 0x0f, 0x4f,
+ 0x4f, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xf6, 0x57, 0x0f, 0x4f, 0x4f, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xf6, 0x57, 0x0f, 0x4f, 0x57, 0xf6, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x52, 0xf6, 0xff, 0xff, 0x07,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0x08, 0xff, 0xff, 0xf6, 0x49,
+ 0x00, 0x00, 0x00, 0x07, 0xff, 0x08, 0x00, 0x00, 0x00, 0x52, 0xf6, 0x07,
+ 0x49, 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0xf6, 0xf6, 0x52, 0x00,
+ 0x00, 0x00, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x49, 0x00,
+ 0x00, 0x00, 0x07, 0xf6, 0x49, 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00,
+ 0x52, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x49,
+ 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0xf7, 0xff, 0xa4, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xf6,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xaf, 0x4f, 0x0f, 0x4f, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xa7, 0x0f, 0x4f, 0x0f, 0x9f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf6, 0x9f, 0x0f, 0x4f, 0x0f, 0xa7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x9f, 0x0f, 0x4f, 0x4f,
+ 0x57, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x52,
+ 0xf6, 0xff, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf7,
+ 0xff, 0xff, 0xf6, 0x49, 0x00, 0x00, 0x00, 0x08, 0xff, 0x08, 0x00, 0x00,
+ 0x00, 0x52, 0xf6, 0x07, 0x49, 0x00, 0x00, 0x52, 0xf6, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, 0x07,
+ 0xff, 0x08, 0x49, 0x00, 0x00, 0x49, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0x52, 0x00, 0x00, 0x00, 0x07, 0xf6, 0x49, 0x00, 0x00, 0x52,
+ 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xf6, 0x52, 0x00, 0x00, 0x49, 0xf7, 0xf7, 0xf7, 0xf7, 0xf7, 0xf7, 0xf7,
+ 0x49, 0x00, 0x00, 0x49, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0xf7, 0xff,
+ 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0x4f, 0x4f, 0x0f, 0x57, 0xf6, 0xff,
+ 0xff, 0xff, 0xff, 0xef, 0x57, 0x0f, 0x0f, 0x57, 0xf6, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x4f, 0x4f, 0x0f, 0x57,
+ 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef,
+ 0x4f, 0x0f, 0x4f, 0x4f, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7,
+ 0x00, 0x00, 0x00, 0x49, 0x08, 0xff, 0xf6, 0x49, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x5b, 0xf6, 0xff, 0x08, 0x49, 0x00, 0x00, 0x00, 0xf6,
+ 0xff, 0x08, 0x00, 0x00, 0x00, 0x52, 0xf6, 0x07, 0x49, 0x00, 0x00, 0x5b,
+ 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xf6, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x49, 0x07, 0xff, 0xf6, 0x49, 0x00, 0x00, 0x49, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9b, 0x00, 0x00, 0x00, 0x07, 0xf6,
+ 0x49, 0x00, 0x00, 0x52, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, 0xff, 0xf6, 0x52, 0x00,
+ 0x00, 0x00, 0xf7, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0x4f, 0x4f,
+ 0x4f, 0x0f, 0x9f, 0xf6, 0xff, 0xff, 0xf6, 0x5f, 0x0f, 0x4f, 0x0f, 0xaf,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x57,
+ 0x0f, 0x4f, 0x0f, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xf6, 0x57, 0x0f, 0x4f, 0x4f, 0x5f, 0xf6, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0x07, 0x49, 0x00, 0x00, 0x00, 0x08, 0xff, 0x07, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xff, 0x07, 0x00,
+ 0x00, 0x00, 0x49, 0xf6, 0xff, 0x08, 0x00, 0x00, 0x00, 0x52, 0xf6, 0x07,
+ 0x49, 0x00, 0x00, 0x5b, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0x49, 0x49, 0x49,
+ 0x49, 0x49, 0x49, 0x00, 0x00, 0x00, 0x00, 0x5b, 0xf6, 0xf6, 0x49, 0x00,
+ 0x00, 0x49, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9b, 0x00,
+ 0x00, 0x00, 0x07, 0xf6, 0x49, 0x00, 0x00, 0x9b, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49,
+ 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0xf7, 0xff, 0xa4, 0x00, 0x00, 0x00,
+ 0x49, 0x52, 0x52, 0x52, 0x52, 0x52, 0x52, 0x00, 0x00, 0x00, 0x00, 0x9b,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xaf, 0x4f, 0x4f, 0x4f, 0x0f, 0x0f, 0xaf, 0xff, 0xff, 0xaf, 0x0f,
+ 0x4f, 0x0f, 0x5f, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xa7, 0x0f, 0x4f, 0x0f, 0x5f, 0xf6, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa7, 0x0f, 0x4f, 0x4f, 0x4f, 0xef,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x49, 0x00, 0x00, 0x00,
+ 0x07, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x49, 0xa4, 0x49, 0x00, 0x00, 0x00,
+ 0xa4, 0xff, 0x07, 0x00, 0x00, 0x00, 0x52, 0xf6, 0xff, 0x08, 0x00, 0x00,
+ 0x00, 0x52, 0xf6, 0x07, 0x49, 0x00, 0x00, 0x5b, 0xf6, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00,
+ 0x52, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x52, 0x00, 0x00, 0x49,
+ 0x08, 0xf6, 0x49, 0x00, 0x00, 0x49, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0x9b, 0x00, 0x00, 0x00, 0x07, 0xf6, 0x49, 0x00, 0x00, 0x5b,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xf6, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x49, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0xf7, 0xff,
+ 0xa4, 0x00, 0x00, 0x00, 0xf7, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0xa4,
+ 0x00, 0x00, 0x00, 0x5b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x57,
+ 0xf6, 0xf6, 0x57, 0x0f, 0x0f, 0x4f, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x4f, 0x0f, 0x0f, 0x57, 0xef, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x4f, 0x0f,
+ 0x4f, 0x4f, 0xa7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x08,
+ 0x52, 0x00, 0x00, 0x00, 0x07, 0xf6, 0x49, 0x00, 0x00, 0x00, 0x5b, 0xf6,
+ 0x52, 0x00, 0x00, 0x00, 0x52, 0xf6, 0xf7, 0x00, 0x00, 0x00, 0x5b, 0xff,
+ 0xff, 0x08, 0x00, 0x00, 0x00, 0x52, 0xf6, 0x07, 0x49, 0x00, 0x00, 0x5b,
+ 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xf6, 0x52, 0x00, 0x00, 0x52, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xa4, 0x00, 0x00, 0x00, 0x08, 0xf6, 0x49, 0x00, 0x00, 0x49, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x07, 0xf6,
+ 0x49, 0x00, 0x00, 0x52, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, 0xff, 0xf6, 0x52, 0x00,
+ 0x00, 0x00, 0xf7, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0x08, 0x49, 0x00, 0x00, 0x52, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x0f, 0x5f, 0x5f, 0x0f, 0x4f, 0x0f, 0xa7, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x5f, 0x0f, 0x4f,
+ 0x0f, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xf6, 0x5f, 0x0f, 0x4f, 0x4f, 0x57, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0x07, 0xf7, 0x00, 0x00,
+ 0x00, 0x00, 0xf7, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x07, 0xf7, 0x00,
+ 0x00, 0x00, 0x9b, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x52, 0xf6, 0x07,
+ 0x49, 0x00, 0x00, 0x52, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x52, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x08, 0xf6, 0x49, 0x00,
+ 0x00, 0x00, 0x08, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x52, 0x00,
+ 0x00, 0x00, 0x07, 0xf6, 0x49, 0x00, 0x00, 0x49, 0xf6, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00,
+ 0x49, 0xa4, 0xf7, 0xf7, 0xf7, 0xf7, 0xf7, 0xa4, 0x49, 0x00, 0x00, 0x49,
+ 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0xf7, 0xff, 0xa4, 0x00, 0x00, 0x00,
+ 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x08, 0x49, 0x00, 0x00, 0x52,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x4f, 0x0f,
+ 0x5f, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xa7, 0x0f, 0x4f, 0x0f, 0x5f, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xa7, 0x0f, 0x0f, 0x4f, 0x4f, 0xef, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00,
+ 0xf7, 0x52, 0x00, 0x00, 0x00, 0x52, 0xf6, 0xff, 0x07, 0x49, 0x00, 0x00,
+ 0x00, 0xa4, 0x9b, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xff, 0x08, 0x00, 0x00,
+ 0x00, 0x52, 0xf6, 0x08, 0x49, 0x00, 0x00, 0x00, 0xa4, 0xf6, 0xf6, 0xf6,
+ 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xff, 0xf6, 0x52, 0x00, 0x00,
+ 0x52, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xff, 0x08, 0x52, 0x00, 0x00, 0x00,
+ 0x08, 0xff, 0x52, 0x00, 0x00, 0x00, 0x9b, 0xf6, 0xff, 0xf6, 0xf6, 0xf6,
+ 0xff, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x08, 0xf6, 0x49, 0x00, 0x00, 0x00,
+ 0xa4, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xff,
+ 0xf6, 0x52, 0x00, 0x00, 0x52, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6,
+ 0x52, 0x00, 0x00, 0x49, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0xf7, 0xff,
+ 0xa4, 0x00, 0x00, 0x00, 0x07, 0xff, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, 0xa4,
+ 0x00, 0x00, 0x00, 0x5b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x57, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x0f, 0x4f, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef, 0x57, 0x0f, 0x0f, 0x4f, 0xef, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x57, 0x0f, 0x4f, 0x4f,
+ 0xa7, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0x9b, 0x00, 0x00, 0x00, 0x52, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xff, 0xff,
+ 0xf6, 0x5b, 0x00, 0x00, 0x00, 0x49, 0x52, 0x00, 0x00, 0x00, 0xf7, 0xff,
+ 0xff, 0x08, 0x00, 0x00, 0x00, 0x52, 0x08, 0xf6, 0x52, 0x00, 0x00, 0x00,
+ 0x00, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x52, 0x08,
+ 0xf6, 0x52, 0x00, 0x00, 0x00, 0x52, 0x52, 0x52, 0x52, 0x52, 0x52, 0x49,
+ 0x00, 0x00, 0x00, 0x00, 0x07, 0xff, 0x52, 0x00, 0x00, 0x00, 0x00, 0x49,
+ 0x52, 0x52, 0x52, 0x52, 0x49, 0x00, 0x00, 0x00, 0x00, 0x49, 0x08, 0xf6,
+ 0x49, 0x00, 0x00, 0x00, 0x00, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+ 0x49, 0x49, 0x49, 0xf6, 0xf6, 0x52, 0x00, 0x00, 0x52, 0xf6, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x49, 0xff, 0xf6, 0x52, 0x00,
+ 0x00, 0x00, 0xf7, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x49, 0x52, 0x52, 0x52,
+ 0x52, 0x52, 0x49, 0x00, 0x00, 0x00, 0x00, 0x9b, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa7, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0xa7, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x9f, 0x0f, 0x4f, 0x0f, 0xa7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x5f,
+ 0x0f, 0x4f, 0x4f, 0x57, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x07, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xf7, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x52, 0x08, 0xff,
+ 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x49, 0x08, 0xff, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, 0x08, 0xff, 0x9b, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x52, 0xf6, 0xff, 0x5b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf6, 0xf6, 0x52, 0x00, 0x00,
+ 0x52, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x49,
+ 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0xf7, 0xff, 0xa4, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa4,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xef, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x9f,
+ 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0x0f,
+ 0x0f, 0x4f, 0x0f, 0x9f, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xaf, 0x0f, 0x0f, 0x4f, 0x4f, 0xef, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x5b, 0xff, 0xff, 0xff, 0xff, 0x08, 0x52, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0x08, 0x00, 0x00,
+ 0x00, 0x52, 0x08, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0xf6, 0xf6, 0x52, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9b,
+ 0xf6, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0xf7, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, 0xf6,
+ 0xf6, 0x52, 0x00, 0x00, 0x52, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6,
+ 0x52, 0x00, 0x00, 0x49, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0xf7, 0xff,
+ 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x49, 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x57, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x0f, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xf6, 0x57, 0x0f, 0x4f, 0x4f, 0x4f, 0x0f, 0xa7, 0xf6, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x57, 0x0f, 0x4f, 0x4f, 0x9f, 0xf6,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf7, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, 0x07, 0xff,
+ 0xff, 0x08, 0x00, 0x00, 0x00, 0x52, 0x08, 0xff, 0xff, 0xa4, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9b, 0xf6,
+ 0xf6, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x49, 0x07, 0xff, 0xff, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5b, 0xf6, 0xff, 0xff,
+ 0xf6, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xa4, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x52, 0xf6, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x49, 0xff, 0xf6, 0x52, 0x00,
+ 0x00, 0x00, 0xf7, 0xff, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa7,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x4f, 0xef, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xf6, 0x9f, 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f,
+ 0x4f, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x9f, 0x0f, 0x4f,
+ 0x4f, 0x57, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0x07, 0x49, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49,
+ 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x49, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x49, 0xf6, 0xff, 0xff, 0xf6, 0xa4, 0xa4, 0xa4, 0xf7, 0xf6, 0xff,
+ 0xff, 0xff, 0x07, 0xa4, 0x5b, 0x5b, 0x5b, 0x5b, 0x5b, 0x5b, 0x5b, 0x5b,
+ 0x5b, 0xf7, 0xf6, 0xff, 0xf6, 0xf7, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
+ 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xf7, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0x08, 0xa4, 0x9b, 0x5b, 0x5b, 0x5b, 0x5b, 0x5b, 0x5b, 0x5b, 0xa4, 0x07,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0xa4, 0x9b, 0x5b, 0x5b, 0x5b,
+ 0x5b, 0x5b, 0x5b, 0x5b, 0x9b, 0xf7, 0xf6, 0xff, 0xf6, 0xf7, 0xa4, 0xa4,
+ 0xf7, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xf7, 0xa4, 0xa4, 0xa4,
+ 0xff, 0xf6, 0xf7, 0xa4, 0xa4, 0xa4, 0x07, 0xff, 0x07, 0xa4, 0xa4, 0xa4,
+ 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xf7, 0xf6, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf6, 0x57, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x0f, 0x57, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x0f, 0x0f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x57, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xef, 0x0f, 0x0f, 0x4f, 0x4f, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07, 0x49, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xa4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9b,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0xa7, 0xff, 0xff, 0xff, 0xff, 0xf6,
+ 0x57, 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0xa7, 0xf6,
+ 0xff, 0xff, 0xff, 0xf6, 0x57, 0x0f, 0x4f, 0x4f, 0x5f, 0xf6, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0x08, 0x49, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xf6, 0x9f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x0f, 0xef,
+ 0xff, 0xff, 0xf6, 0xa7, 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x0f, 0xaf, 0xff, 0xff, 0xf6, 0xa7, 0x0f, 0x4f, 0x4f, 0x57,
+ 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00, 0x00, 0x5b, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0x52, 0x00, 0x00, 0x00,
+ 0x00, 0x5b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x57, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x0f, 0x57, 0xef, 0xef, 0xa7, 0x0f, 0x0f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x4f, 0xaf, 0xef, 0xa7, 0x0f,
+ 0x0f, 0x4f, 0x4f, 0xa7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa4, 0x00, 0x00,
+ 0x00, 0x49, 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xf7, 0x00, 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x57,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x4f, 0x57, 0x0f, 0x0f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x0f,
+ 0x4f, 0x57, 0x0f, 0x0f, 0x4f, 0x4f, 0x5f, 0xf6, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xf6, 0xa4, 0x52, 0x5b, 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x52, 0x52, 0xa4, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xef, 0x57, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x0f, 0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x0f, 0x0f, 0x4f, 0x4f, 0x4f, 0x57, 0xef, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xf6,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x57, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0xa7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xef, 0x57, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x57, 0xf6, 0xff, 0x07, 0xa4, 0xf7, 0xf6, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xa7, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0xef, 0xff, 0x07, 0x5b,
+ 0x52, 0x52, 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6,
+ 0xef, 0x5f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x9f,
+ 0xf6, 0xff, 0xf7, 0x52, 0x52, 0x52, 0xf7, 0xf6, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xef, 0x5f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x5f, 0xf6, 0xff, 0xff, 0x08, 0x5b, 0x52, 0x5b, 0x07, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6,
+ 0xef, 0xa7, 0x5f, 0x57, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
+ 0x4f, 0x4f, 0x4f, 0x5f, 0xa7, 0xef, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xf6,
+ 0x08, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6, 0xf6, 0xef, 0xaf, 0xa7, 0xa7,
+ 0xa7, 0xa7, 0xa7, 0xa7, 0xaf, 0xef, 0xef, 0xf6, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+};
+
+#endif
--- /dev/null
+/*
+ * charset conversion utils
+ *
+ * Copyright (c) 2017 Rob Clark
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <charset.h>
+#include <malloc.h>
+
+/*
+ * utf8/utf16 conversion mostly lifted from grub
+ */
+
+size_t utf16_strlen(const uint16_t *in)
+{
+ size_t i;
+ for (i = 0; in[i]; i++);
+ return i;
+}
+
+size_t utf16_strnlen(const uint16_t *in, size_t count)
+{
+ size_t i;
+ for (i = 0; count-- && in[i]; i++);
+ return i;
+}
+
+uint16_t *utf16_strcpy(uint16_t *dest, const uint16_t *src)
+{
+ uint16_t *tmp = dest;
+
+ while ((*dest++ = *src++) != '\0')
+ /* nothing */;
+ return tmp;
+
+}
+
+uint16_t *utf16_strdup(const uint16_t *s)
+{
+ uint16_t *new;
+ if (!s || !(new = malloc((utf16_strlen(s) + 1) * 2)))
+ return NULL;
+ utf16_strcpy(new, s);
+ return new;
+}
+
+/* Convert UTF-16 to UTF-8. */
+uint8_t *utf16_to_utf8(uint8_t *dest, const uint16_t *src, size_t size)
+{
+ uint32_t code_high = 0;
+
+ while (size--) {
+ uint32_t code = *src++;
+
+ if (code_high) {
+ if (code >= 0xDC00 && code <= 0xDFFF) {
+ /* Surrogate pair. */
+ code = ((code_high - 0xD800) << 10) + (code - 0xDC00) + 0x10000;
+
+ *dest++ = (code >> 18) | 0xF0;
+ *dest++ = ((code >> 12) & 0x3F) | 0x80;
+ *dest++ = ((code >> 6) & 0x3F) | 0x80;
+ *dest++ = (code & 0x3F) | 0x80;
+ } else {
+ /* Error... */
+ *dest++ = '?';
+ /* *src may be valid. Don't eat it. */
+ src--;
+ }
+
+ code_high = 0;
+ } else {
+ if (code <= 0x007F) {
+ *dest++ = code;
+ } else if (code <= 0x07FF) {
+ *dest++ = (code >> 6) | 0xC0;
+ *dest++ = (code & 0x3F) | 0x80;
+ } else if (code >= 0xD800 && code <= 0xDBFF) {
+ code_high = code;
+ continue;
+ } else if (code >= 0xDC00 && code <= 0xDFFF) {
+ /* Error... */
+ *dest++ = '?';
+ } else if (code < 0x10000) {
+ *dest++ = (code >> 12) | 0xE0;
+ *dest++ = ((code >> 6) & 0x3F) | 0x80;
+ *dest++ = (code & 0x3F) | 0x80;
+ } else {
+ *dest++ = (code >> 18) | 0xF0;
+ *dest++ = ((code >> 12) & 0x3F) | 0x80;
+ *dest++ = ((code >> 6) & 0x3F) | 0x80;
+ *dest++ = (code & 0x3F) | 0x80;
+ }
+ }
+ }
+
+ return dest;
+}
*/
#include <common.h>
+#include <charset.h>
#include <efi_loader.h>
static bool console_size_queried;
static void print_unicode_in_utf8(u16 c)
{
- char utf8[4] = { 0 };
- char *b = utf8;
-
- if (c < 0x80) {
- *(b++) = c;
- } else if (c < 0x800) {
- *(b++) = 192 + c / 64;
- *(b++) = 128 + c % 64;
- } else {
- *(b++) = 224 + c / 4096;
- *(b++) = 128 + c / 64 % 64;
- *(b++) = 128 + c % 64;
- }
-
+ char utf8[MAX_UTF8_PER_UTF16] = { 0 };
+ utf16_to_utf8((u8 *)utf8, &c, 1);
puts(utf8);
}
* @fdt: Base device tree blob
* @fdto: Device tree overlay blob
* @fragment: node offset of the fragment in the overlay
+ * @pathp: pointer which receives the path of the target (or NULL)
*
* overlay_get_target() retrieves the target offset in the base
* device tree of a fragment, no matter how the actual targetting is
* Negative error code on error
*/
static int overlay_get_target(const void *fdt, const void *fdto,
- int fragment)
+ int fragment, char const **pathp)
{
uint32_t phandle;
- const char *path;
- int path_len;
+ const char *path = NULL;
+ int path_len = 0, ret;
/* Try first to do a phandle based lookup */
phandle = overlay_get_target_phandle(fdto, fragment);
if (phandle == (uint32_t)-1)
return -FDT_ERR_BADPHANDLE;
- if (phandle)
- return fdt_node_offset_by_phandle(fdt, phandle);
+ /* no phandle, try path */
+ if (!phandle) {
+ /* And then a path based lookup */
+ path = fdt_getprop(fdto, fragment, "target-path", &path_len);
+ if (path)
+ ret = fdt_path_offset(fdt, path);
+ else
+ ret = path_len;
+ } else
+ ret = fdt_node_offset_by_phandle(fdt, phandle);
- /* And then a path based lookup */
- path = fdt_getprop(fdto, fragment, "target-path", &path_len);
- if (!path) {
- /*
- * If we haven't found either a target or a
- * target-path property in a node that contains a
- * __overlay__ subnode (we wouldn't be called
- * otherwise), consider it a improperly written
- * overlay
- */
- if (path_len == -FDT_ERR_NOTFOUND)
- return -FDT_ERR_BADOVERLAY;
+ /*
+ * If we haven't found either a target or a
+ * target-path property in a node that contains a
+ * __overlay__ subnode (we wouldn't be called
+ * otherwise), consider it a improperly written
+ * overlay
+ */
+ if (ret < 0 && path_len == -FDT_ERR_NOTFOUND)
+ ret = -FDT_ERR_BADOVERLAY;
+
+ /* return on error */
+ if (ret < 0)
+ return ret;
- return path_len;
- }
+ /* return pointer to path (if available) */
+ if (pathp)
+ *pathp = path ? path : NULL;
- return fdt_path_offset(fdt, path);
+ return ret;
}
/**
*
* overlay_merge() merges an overlay into its base device tree.
*
- * This is the final step in the device tree overlay application
+ * This is the next to last step in the device tree overlay application
* process, when all the phandles have been adjusted and resolved and
* you just have to merge overlay into the base device tree.
*
if (overlay < 0)
return overlay;
- target = overlay_get_target(fdt, fdto, fragment);
+ target = overlay_get_target(fdt, fdto, fragment, NULL);
if (target < 0)
return target;
return 0;
}
+static int get_path_len(const void *fdt, int nodeoffset)
+{
+ int len = 0, namelen;
+ const char *name;
+
+ FDT_CHECK_HEADER(fdt);
+
+ for (;;) {
+ name = fdt_get_name(fdt, nodeoffset, &namelen);
+ if (!name)
+ return namelen;
+
+ /* root? we're done */
+ if (namelen == 0)
+ break;
+
+ nodeoffset = fdt_parent_offset(fdt, nodeoffset);
+ if (nodeoffset < 0)
+ return nodeoffset;
+ len += namelen + 1;
+ }
+
+ /* in case of root pretend it's "/" */
+ if (len == 0)
+ len++;
+ return len;
+}
+
+/**
+ * overlay_symbol_update - Update the symbols of base tree after a merge
+ * @fdt: Base Device Tree blob
+ * @fdto: Device tree overlay blob
+ *
+ * overlay_symbol_update() updates the symbols of the base tree with the
+ * symbols of the applied overlay
+ *
+ * This is the last step in the device tree overlay application
+ * process, allowing the reference of overlay symbols by subsequent
+ * overlay operations.
+ *
+ * returns:
+ * 0 on success
+ * Negative error code on failure
+ */
+static int overlay_symbol_update(void *fdt, void *fdto)
+{
+ int root_sym, ov_sym, prop, path_len, fragment, target;
+ int len, frag_name_len, ret, rel_path_len;
+ const char *s, *e;
+ const char *path;
+ const char *name;
+ const char *frag_name;
+ const char *rel_path;
+ const char *target_path;
+ char *buf;
+ void *p;
+
+ ov_sym = fdt_subnode_offset(fdto, 0, "__symbols__");
+
+ /* if no overlay symbols exist no problem */
+ if (ov_sym < 0)
+ return 0;
+
+ root_sym = fdt_subnode_offset(fdt, 0, "__symbols__");
+
+ /* it no root symbols exist we should create them */
+ if (root_sym == -FDT_ERR_NOTFOUND)
+ root_sym = fdt_add_subnode(fdt, 0, "__symbols__");
+
+ /* any error is fatal now */
+ if (root_sym < 0)
+ return root_sym;
+
+ /* iterate over each overlay symbol */
+ fdt_for_each_property_offset(prop, fdto, ov_sym) {
+ path = fdt_getprop_by_offset(fdto, prop, &name, &path_len);
+ if (!path)
+ return path_len;
+
+ /* verify it's a string property (terminated by a single \0) */
+ if (path_len < 1 || memchr(path, '\0', path_len) != &path[path_len - 1])
+ return -FDT_ERR_BADVALUE;
+
+ /* keep end marker to avoid strlen() */
+ e = path + path_len;
+
+ /* format: /<fragment-name>/__overlay__/<relative-subnode-path> */
+
+ if (*path != '/')
+ return -FDT_ERR_BADVALUE;
+
+ /* get fragment name first */
+ s = strchr(path + 1, '/');
+ if (!s)
+ return -FDT_ERR_BADOVERLAY;
+
+ frag_name = path + 1;
+ frag_name_len = s - path - 1;
+
+ /* verify format; safe since "s" lies in \0 terminated prop */
+ len = sizeof("/__overlay__/") - 1;
+ if ((e - s) < len || memcmp(s, "/__overlay__/", len))
+ return -FDT_ERR_BADOVERLAY;
+
+ rel_path = s + len;
+ rel_path_len = e - rel_path;
+
+ /* find the fragment index in which the symbol lies */
+ ret = fdt_subnode_offset_namelen(fdto, 0, frag_name,
+ frag_name_len);
+ /* not found? */
+ if (ret < 0)
+ return -FDT_ERR_BADOVERLAY;
+ fragment = ret;
+
+ /* an __overlay__ subnode must exist */
+ ret = fdt_subnode_offset(fdto, fragment, "__overlay__");
+ if (ret < 0)
+ return -FDT_ERR_BADOVERLAY;
+
+ /* get the target of the fragment */
+ ret = overlay_get_target(fdt, fdto, fragment, &target_path);
+ if (ret < 0)
+ return ret;
+ target = ret;
+
+ /* if we have a target path use */
+ if (!target_path) {
+ ret = get_path_len(fdt, target);
+ if (ret < 0)
+ return ret;
+ len = ret;
+ } else {
+ len = strlen(target_path);
+ }
+
+ ret = fdt_setprop_placeholder(fdt, root_sym, name,
+ len + (len > 1) + rel_path_len + 1, &p);
+ if (ret < 0)
+ return ret;
+
+ if (!target_path) {
+ /* again in case setprop_placeholder changed it */
+ ret = overlay_get_target(fdt, fdto, fragment, &target_path);
+ if (ret < 0)
+ return ret;
+ target = ret;
+ }
+
+ buf = p;
+ if (len > 1) { /* target is not root */
+ if (!target_path) {
+ ret = fdt_get_path(fdt, target, buf, len + 1);
+ if (ret < 0)
+ return ret;
+ } else
+ memcpy(buf, target_path, len + 1);
+
+ } else
+ len--;
+
+ buf[len] = '/';
+ memcpy(buf + len + 1, rel_path, rel_path_len);
+ buf[len + 1 + rel_path_len] = '\0';
+ }
+
+ return 0;
+}
+
int fdt_overlay_apply(void *fdt, void *fdto)
{
uint32_t delta = fdt_get_max_phandle(fdt);
if (ret)
goto err;
+ ret = overlay_symbol_update(fdt, fdto);
+ if (ret)
+ goto err;
+
/*
* The overlay has been damaged, erase its magic.
*/
return 0;
}
-int fdt_setprop(void *fdt, int nodeoffset, const char *name,
- const void *val, int len)
+int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name,
+ int len, void **prop_data)
{
struct fdt_property *prop;
int err;
if (err)
return err;
+ *prop_data = prop->data;
+ return 0;
+}
+
+int fdt_setprop(void *fdt, int nodeoffset, const char *name,
+ const void *val, int len)
+{
+ void *prop_data;
+ int err;
+
+ err = fdt_setprop_placeholder(fdt, nodeoffset, name, len, &prop_data);
+ if (err)
+ return err;
+
if (len)
- memcpy(prop->data, val, len);
+ memcpy(prop_data, val, len);
return 0;
}
struct fdt_region region[], int max_regions,
char *path, int path_len, int add_string_tab)
{
- int stack[FDT_MAX_DEPTH];
+ int stack[FDT_MAX_DEPTH] = { 0 };
char *end;
int nextoffset = 0;
uint32_t tag;
int fdt_setprop(void *fdt, int nodeoffset, const char *name,
const void *val, int len);
+/**
+ * fdt_setprop _placeholder - allocate space for a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @len: length of the property value
+ * @prop_data: return pointer to property data
+ *
+ * fdt_setprop_placeholer() allocates the named property in the given node.
+ * If the property exists it is resized. In either case a pointer to the
+ * property data is returned.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ * 0, on success
+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ * contain the new property value
+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ * -FDT_ERR_BADLAYOUT,
+ * -FDT_ERR_BADMAGIC,
+ * -FDT_ERR_BADVERSION,
+ * -FDT_ERR_BADSTATE,
+ * -FDT_ERR_BADSTRUCTURE,
+ * -FDT_ERR_BADLAYOUT,
+ * -FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name,
+ int len, void **prop_data);
+
/**
* fdt_setprop_u32 - set a property to a 32-bit integer
* @fdt: pointer to the device tree blob
%module libfdt
+%include <stdint.i>
+
%{
#define SWIG_FILE_WITH_INIT
#include "libfdt.h"
self._fdt = bytearray(data)
check_err(fdt_check_header(self._fdt));
+ def subnode_offset(self, parentoffset, name, quiet=()):
+ """Get the offset of a named subnode
+
+ Args:
+ parentoffset: Offset of the parent node to check
+ name: Name of the required subnode, e.g. 'subnode@1'
+ quiet: Errors to ignore (empty to raise on all errors)
+
+ Returns:
+ The node offset of the found node, if any
+
+ Raises
+ FdtException if there is no node with that name, or other error
+ """
+ return check_err(fdt_subnode_offset(self._fdt, parentoffset, name),
+ quiet)
+
def path_offset(self, path, quiet=()):
"""Get the offset for a given path
return pdata
return bytearray(pdata[0])
+ def get_phandle(self, nodeoffset):
+ """Get the phandle of a node
+
+ Args:
+ nodeoffset: Node offset to check
+
+ Returns:
+ phandle of node, or 0 if the node has no phandle or another error
+ occurs
+ """
+ return fdt_get_phandle(self._fdt, nodeoffset)
+
+ def parent_offset(self, nodeoffset, quiet=()):
+ """Get the offset of a node's parent
+
+ Args:
+ nodeoffset: Node offset to check
+ quiet: Errors to ignore (empty to raise on all errors)
+
+ Returns:
+ The offset of the parent node, if any
+
+ Raises:
+ FdtException if no parent found or other error occurs
+ """
+ return check_err(fdt_parent_offset(self._fdt, nodeoffset), quiet)
+
+ def node_offset_by_phandle(self, phandle, quiet=()):
+ """Get the offset of a node with the given phandle
+
+ Args:
+ phandle: Phandle to search for
+ quiet: Errors to ignore (empty to raise on all errors)
+
+ Returns:
+ The offset of node with that phandle, if any
+
+ Raises:
+ FdtException if no node found or other error occurs
+ """
+ return check_err(fdt_node_offset_by_phandle(self._fdt, phandle), quiet)
class Property:
"""Holds a device tree property name and value.
#include <errno.h>
#include <linux/ctype.h>
+/* from lib/kstrtox.c */
+static const char *_parse_integer_fixup_radix(const char *s, unsigned int *base)
+{
+ if (*base == 0) {
+ if (s[0] == '0') {
+ if (tolower(s[1]) == 'x' && isxdigit(s[2]))
+ *base = 16;
+ else
+ *base = 8;
+ } else
+ *base = 10;
+ }
+ if (*base == 16 && s[0] == '0' && tolower(s[1]) == 'x')
+ s += 2;
+ return s;
+}
+
unsigned long simple_strtoul(const char *cp, char **endp,
unsigned int base)
{
unsigned long result = 0;
unsigned long value;
- if (*cp == '0') {
- cp++;
- if ((*cp == 'x') && isxdigit(cp[1])) {
- base = 16;
- cp++;
- }
-
- if (!base)
- base = 8;
- }
-
- if (!base)
- base = 10;
+ cp = _parse_integer_fixup_radix(cp, &base);
while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp)
? toupper(*cp) : *cp)-'A'+10) < base) {
{
unsigned long long result = 0, value;
- if (*cp == '0') {
- cp++;
- if ((*cp == 'x') && isxdigit(cp[1])) {
- base = 16;
- cp++;
- }
-
- if (!base)
- base = 8;
- }
-
- if (!base)
- base = 10;
+ cp = _parse_integer_fixup_radix(cp, &base);
while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp - '0'
: (islower(*cp) ? toupper(*cp) : *cp) - 'A' + 10) < base) {
#include <linux/ctype.h>
#include <common.h>
+#include <charset.h>
+#include <uuid.h>
#include <div64.h>
#define noinline __attribute__((noinline))
return buf;
}
+static char *string16(char *buf, char *end, u16 *s, int field_width,
+ int precision, int flags)
+{
+ u16 *str = s ? s : L"<NULL>";
+ int utf16_len = utf16_strnlen(str, precision);
+ u8 utf8[utf16_len * MAX_UTF8_PER_UTF16];
+ int utf8_len, i;
+
+ utf8_len = utf16_to_utf8(utf8, str, utf16_len) - utf8;
+
+ if (!(flags & LEFT))
+ while (utf8_len < field_width--)
+ ADDCH(buf, ' ');
+ for (i = 0; i < utf8_len; ++i)
+ ADDCH(buf, utf8[i]);
+ while (utf8_len < field_width--)
+ ADDCH(buf, ' ');
+ return buf;
+}
+
#ifdef CONFIG_CMD_NET
static const char hex_asc[] = "0123456789abcdef";
#define hex_asc_lo(x) hex_asc[((x) & 0x0f)]
}
#endif
+#ifdef CONFIG_LIB_UUID
+/*
+ * This works (roughly) the same way as linux's, but we currently always
+ * print lower-case (ie. we just keep %pUB and %pUL for compat with linux),
+ * mostly just because that is what uuid_bin_to_str() supports.
+ *
+ * %pUb: 01020304-0506-0708-090a-0b0c0d0e0f10
+ * %pUl: 04030201-0605-0807-090a-0b0c0d0e0f10
+ */
+static char *uuid_string(char *buf, char *end, u8 *addr, int field_width,
+ int precision, int flags, const char *fmt)
+{
+ char uuid[UUID_STR_LEN + 1];
+ int str_format = UUID_STR_FORMAT_STD;
+
+ switch (*(++fmt)) {
+ case 'L':
+ case 'l':
+ str_format = UUID_STR_FORMAT_GUID;
+ break;
+ case 'B':
+ case 'b':
+ /* this is the default */
+ break;
+ default:
+ break;
+ }
+
+ uuid_bin_to_str(addr, uuid, str_format);
+
+ return string(buf, end, uuid, field_width, precision, flags);
+}
+#endif
+
/*
* Show a '%p' thing. A kernel extension is that the '%p' is followed
* by an extra set of alphanumeric characters that are extended format
flags);
#endif
-#ifdef CONFIG_CMD_NET
switch (*fmt) {
+#ifdef CONFIG_CMD_NET
case 'a':
flags |= SPECIAL | ZEROPAD;
precision, flags);
flags &= ~SPECIAL;
break;
- }
#endif
+#ifdef CONFIG_LIB_UUID
+ case 'U':
+ return uuid_string(buf, end, ptr, field_width, precision,
+ flags, fmt);
+#endif
+ default:
+ break;
+ }
flags |= SMALL;
if (field_width == -1) {
field_width = 2*sizeof(void *);
continue;
case 's':
- str = string(str, end, va_arg(args, char *),
- field_width, precision, flags);
+ if (qualifier == 'l' && !IS_ENABLED(CONFIG_SPL_BUILD)) {
+ str = string16(str, end, va_arg(args, u16 *),
+ field_width, precision, flags);
+ } else {
+ str = string(str, end, va_arg(args, char *),
+ field_width, precision, flags);
+ }
continue;
case 'p':
dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
+# DTCO
+# ---------------------------------------------------------------------------
+
+quiet_cmd_dtco = DTCO $@
+# Rule for objects only; does not put specific u-boot include at the end
+# No generation of assembly file either
+# Modified for U-Boot
+cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \
+ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) - ; \
+ $(DTC) -@ -O dtb -o $@ -b 0 \
+ -i $(dir $<) $(DTC_FLAGS) \
+ -d $(depfile).dtc.tmp $(dtc-tmp) ; \
+ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
+
+$(obj)/%.dtbo: $(src)/%.dts FORCE
+ $(call if_changed_dep,dtco)
+
# Fonts
# ---------------------------------------------------------------------------
quiet_cmd_plat = PLAT $@
cmd_plat = $(CC) $(c_flags) -c $< -o $@
-$(obj)/dts/dt-platdata.o: $(obj)/dts/dt-platdata.c include/generated/dt-structs.h
+$(obj)/dts/dt-platdata.o: $(obj)/dts/dt-platdata.c \
+ include/generated/dt-structs-gen.h
$(call if_changed,plat)
PHONY += dts_dir
dts_dir:
$(shell [ -d $(obj)/dts ] || mkdir -p $(obj)/dts)
-include/generated/dt-structs.h: $(obj)/$(SPL_BIN).dtb dts_dir checkdtoc
+include/generated/dt-structs-gen.h: $(obj)/$(SPL_BIN).dtb dts_dir checkdtoc
$(call if_changed,dtoch)
$(obj)/dts/dt-platdata.c: $(obj)/$(SPL_BIN).dtb dts_dir checkdtoc
-#!/usr/bin/perl -w
+#!/usr/bin/env perl
# (c) 2001, Dave Jones. (the file handling bit)
# (c) 2005, Joel Schopp <jschopp@austin.ibm.com> (the ugly bit)
# (c) 2007,2008, Andy Whitcroft <apw@uk.ibm.com> (new conditions, test suite)
# Licensed under the terms of the GNU GPL License version 2
use strict;
+use warnings;
use POSIX;
use File::Basename;
use Cwd 'abs_path';
+use Term::ANSIColor qw(:constants);
my $P = $0;
-$P =~ s@.*/@@g;
my $D = dirname(abs_path($P));
my $V = '0.32';
my $tst_only;
my $emacs = 0;
my $terse = 0;
+my $showfile = 0;
my $file = 0;
+my $git = 0;
+my %git_commits = ();
my $check = 0;
+my $check_orig = 0;
my $summary = 1;
my $mailback = 0;
my $summary_file = 0;
my $show_types = 0;
+my $list_types = 0;
my $fix = 0;
my $fix_inplace = 0;
my $root;
my $max_line_length = 80;
my $ignore_perl_version = 0;
my $minimum_perl_version = 5.10.0;
+my $min_conf_desc_length = 4;
my $spelling_file = "$D/spelling.txt";
my $codespell = 0;
my $codespellfile = "/usr/share/codespell/dictionary.txt";
+my $conststructsfile = "$D/const_structs.checkpatch";
+my $typedefsfile = "";
+my $color = "auto";
+my $allow_c99_comments = 1;
sub help {
my ($exitcode) = @_;
--patch treat FILE as patchfile (default)
--emacs emacs compile window format
--terse one line per report
+ --showfile emit diffed file position, not input file position
+ -g, --git treat FILE as a single commit or git revision range
+ single git commit with:
+ <rev>
+ <rev>^
+ <rev>~n
+ multiple git commits with:
+ <rev1>..<rev2>
+ <rev1>...<rev2>
+ <rev>-<count>
+ git merges are ignored
-f, --file treat FILE as regular source file
--subjective, --strict enable more subjective tests
+ --list-types list the possible message types
--types TYPE(,TYPE2...) show only these comma separated message types
--ignore TYPE(,TYPE2...) ignore various comma separated message types
+ --show-types show the specific message type in the output
--max-line-length=n set the maximum line length, if exceeded, warn
- --show-types show the message "types" in the output
+ --min-conf-desc-length=n set the min description length, if shorter, warn
--root=PATH PATH to the kernel tree root
--no-summary suppress the per-file summary
--mailback only produce a report in case of warnings/errors
--ignore-perl-version override checking of perl version. expect
runtime errors.
--codespell Use the codespell dictionary for spelling/typos
- (default:/usr/local/share/codespell/dictionary.txt)
+ (default:/usr/share/codespell/dictionary.txt)
--codespellfile Use this codespell dictionary
+ --typedefsfile Read additional types from this file
+ --color[=WHEN] Use colors 'always', 'never', or only when output
+ is a terminal ('auto'). Default is 'auto'.
-h, --help, --version display this help and exit
When FILE is - read standard input.
exit($exitcode);
}
+sub uniq {
+ my %seen;
+ return grep { !$seen{$_}++ } @_;
+}
+
+sub list_types {
+ my ($exitcode) = @_;
+
+ my $count = 0;
+
+ local $/ = undef;
+
+ open(my $script, '<', abs_path($P)) or
+ die "$P: Can't read '$P' $!\n";
+
+ my $text = <$script>;
+ close($script);
+
+ my @types = ();
+ for ($text =~ /\b(?:(?:CHK|WARN|ERROR)\s*\(\s*"([^"]+)")/g) {
+ push (@types, $_);
+ }
+ @types = sort(uniq(@types));
+ print("#\tMessage type\n\n");
+ foreach my $type (@types) {
+ print(++$count . "\t" . $type . "\n");
+ }
+
+ exit($exitcode);
+}
+
my $conf = which_conf($configuration_file);
if (-f $conf) {
my @conf_args;
unshift(@ARGV, @conf_args) if @conf_args;
}
+# Perl's Getopt::Long allows options to take optional arguments after a space.
+# Prevent --color by itself from consuming other arguments
+foreach (@ARGV) {
+ if ($_ eq "--color" || $_ eq "-color") {
+ $_ = "--color=$color";
+ }
+}
+
GetOptions(
'q|quiet+' => \$quiet,
'tree!' => \$tree,
'patch!' => \$chk_patch,
'emacs!' => \$emacs,
'terse!' => \$terse,
+ 'showfile!' => \$showfile,
'f|file!' => \$file,
+ 'g|git!' => \$git,
'subjective!' => \$check,
'strict!' => \$check,
'ignore=s' => \@ignore,
'types=s' => \@use,
'show-types!' => \$show_types,
+ 'list-types!' => \$list_types,
'max-line-length=i' => \$max_line_length,
+ 'min-conf-desc-length=i' => \$min_conf_desc_length,
'root=s' => \$root,
'summary!' => \$summary,
'mailback!' => \$mailback,
'ignore-perl-version!' => \$ignore_perl_version,
'debug=s' => \%debug,
'test-only=s' => \$tst_only,
- 'codespell!' => \$codespell,
- 'codespellfile=s' => \$codespellfile,
+ 'codespell!' => \$codespell,
+ 'codespellfile=s' => \$codespellfile,
+ 'typedefsfile=s' => \$typedefsfile,
+ 'color=s' => \$color,
+ 'no-color' => \$color, #keep old behaviors of -nocolor
+ 'nocolor' => \$color, #keep old behaviors of -nocolor
'h|help' => \$help,
'version' => \$help
) or help(1);
help(0) if ($help);
+list_types(0) if ($list_types);
+
$fix = 1 if ($fix_inplace);
+$check_orig = $check;
my $exit = 0;
}
}
+#if no filenames are given, push '-' to read patch from stdin
if ($#ARGV < 0) {
- print "$P: no input files\n";
- exit(1);
+ push(@ARGV, '-');
+}
+
+if ($color =~ /^[01]$/) {
+ $color = !$color;
+} elsif ($color =~ /^always$/i) {
+ $color = 1;
+} elsif ($color =~ /^never$/i) {
+ $color = 0;
+} elsif ($color =~ /^auto$/i) {
+ $color = (-t STDOUT);
+} else {
+ die "Invalid color mode: $color\n";
}
sub hash_save_array_words {
sub hash_show_words {
my ($hashRef, $prefix) = @_;
- if ($quiet == 0 && keys %$hashRef) {
- print "NOTE: $prefix message types:";
+ if (keys %$hashRef) {
+ print "\nNOTE: $prefix message types:";
foreach my $word (sort keys %$hashRef) {
print " $word";
}
- print "\n\n";
+ print "\n";
}
}
__init_refok|
__kprobes|
__ref|
- __rcu
+ __rcu|
+ __private
}x;
our $InitAttributePrefix = qr{__(?:mem|cpu|dev|net_|)};
our $InitAttributeData = qr{$InitAttributePrefix(?:initdata\b)};
__percpu|
__nocast|
__safe|
- __bitwise__|
+ __bitwise|
__packed__|
__packed2__|
__naked|
__noreturn|
__used|
__cold|
+ __pure|
__noclone|
__deprecated|
__read_mostly|
__weak
}x;
our $Modifier;
-our $Inline = qr{inline|__always_inline|noinline};
+our $Inline = qr{inline|__always_inline|noinline|__inline|__inline__};
our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]};
our $Lval = qr{$Ident(?:$Member)*};
our $Binary = qr{(?i)0b[01]+$Int_type?};
our $Hex = qr{(?i)0x[0-9a-f]+$Int_type?};
our $Int = qr{[0-9]+$Int_type?};
+our $Octal = qr{0[0-7]+$Int_type?};
+our $String = qr{"[X\t]*"};
our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?};
our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?};
our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?};
our $Float = qr{$Float_hex|$Float_dec|$Float_int};
-our $Constant = qr{$Float|$Binary|$Hex|$Int};
+our $Constant = qr{$Float|$Binary|$Octal|$Hex|$Int};
our $Assignment = qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=};
-our $Compare = qr{<=|>=|==|!=|<|>};
+our $Compare = qr{<=|>=|==|!=|<|(?<!-)>};
our $Arithmetic = qr{\+|-|\*|\/|%};
our $Operators = qr{
<=|>=|==|!=|
&&|\|\||,|\^|\+\+|--|&|\||$Arithmetic
}x;
+our $c90_Keywords = qr{do|for|while|if|else|return|goto|continue|switch|default|case|break}x;
+
+our $BasicType;
our $NonptrType;
+our $NonptrTypeMisordered;
our $NonptrTypeWithAttr;
our $Type;
+our $TypeMisordered;
our $Declare;
+our $DeclareMisordered;
our $NON_ASCII_UTF8 = qr{
[\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte
| $NON_ASCII_UTF8
}x;
-our $typeTypedefs = qr{(?x:
+our $typeC99Typedefs = qr{(?:__)?(?:[us]_?)?int_?(?:8|16|32|64)_t};
+our $typeOtherOSTypedefs = qr{(?x:
+ u_(?:char|short|int|long) | # bsd
+ u(?:nchar|short|int|long) # sysv
+)};
+our $typeKernelTypedefs = qr{(?x:
(?:__)?(?:u|s|be|le)(?:8|16|32|64)|
atomic_t
)};
+our $typeTypedefs = qr{(?x:
+ $typeC99Typedefs\b|
+ $typeOtherOSTypedefs\b|
+ $typeKernelTypedefs\b
+)};
+
+our $zero_initializer = qr{(?:(?:0[xX])?0+$Int_type?|NULL|false)\b};
our $logFunctions = qr{(?x:
- printk(?:_ratelimited|_once|)|
+ printk(?:_ratelimited|_once|_deferred_once|_deferred|)|
(?:[a-z0-9]+_){1,2}(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)|
WARN(?:_RATELIMIT|_ONCE|)|
panic|
- debug|
- printf|
- puts|
MODULE_[A-Z_]+|
seq_vprintf|seq_printf|seq_puts
)};
Cc:
)};
+our @typeListMisordered = (
+ qr{char\s+(?:un)?signed},
+ qr{int\s+(?:(?:un)?signed\s+)?short\s},
+ qr{int\s+short(?:\s+(?:un)?signed)},
+ qr{short\s+int(?:\s+(?:un)?signed)},
+ qr{(?:un)?signed\s+int\s+short},
+ qr{short\s+(?:un)?signed},
+ qr{long\s+int\s+(?:un)?signed},
+ qr{int\s+long\s+(?:un)?signed},
+ qr{long\s+(?:un)?signed\s+int},
+ qr{int\s+(?:un)?signed\s+long},
+ qr{int\s+(?:un)?signed},
+ qr{int\s+long\s+long\s+(?:un)?signed},
+ qr{long\s+long\s+int\s+(?:un)?signed},
+ qr{long\s+long\s+(?:un)?signed\s+int},
+ qr{long\s+long\s+(?:un)?signed},
+ qr{long\s+(?:un)?signed},
+);
+
our @typeList = (
qr{void},
- qr{(?:unsigned\s+)?char},
- qr{(?:unsigned\s+)?short},
- qr{(?:unsigned\s+)?int},
- qr{(?:unsigned\s+)?long},
- qr{(?:unsigned\s+)?long\s+int},
- qr{(?:unsigned\s+)?long\s+long},
- qr{(?:unsigned\s+)?long\s+long\s+int},
- qr{unsigned},
+ qr{(?:(?:un)?signed\s+)?char},
+ qr{(?:(?:un)?signed\s+)?short\s+int},
+ qr{(?:(?:un)?signed\s+)?short},
+ qr{(?:(?:un)?signed\s+)?int},
+ qr{(?:(?:un)?signed\s+)?long\s+int},
+ qr{(?:(?:un)?signed\s+)?long\s+long\s+int},
+ qr{(?:(?:un)?signed\s+)?long\s+long},
+ qr{(?:(?:un)?signed\s+)?long},
+ qr{(?:un)?signed},
qr{float},
qr{double},
qr{bool},
qr{${Ident}_t},
qr{${Ident}_handler},
qr{${Ident}_handler_fn},
+ @typeListMisordered,
);
+
+our $C90_int_types = qr{(?x:
+ long\s+long\s+int\s+(?:un)?signed|
+ long\s+long\s+(?:un)?signed\s+int|
+ long\s+long\s+(?:un)?signed|
+ (?:(?:un)?signed\s+)?long\s+long\s+int|
+ (?:(?:un)?signed\s+)?long\s+long|
+ int\s+long\s+long\s+(?:un)?signed|
+ int\s+(?:(?:un)?signed\s+)?long\s+long|
+
+ long\s+int\s+(?:un)?signed|
+ long\s+(?:un)?signed\s+int|
+ long\s+(?:un)?signed|
+ (?:(?:un)?signed\s+)?long\s+int|
+ (?:(?:un)?signed\s+)?long|
+ int\s+long\s+(?:un)?signed|
+ int\s+(?:(?:un)?signed\s+)?long|
+
+ int\s+(?:un)?signed|
+ (?:(?:un)?signed\s+)?int
+)};
+
+our @typeListFile = ();
our @typeListWithAttr = (
@typeList,
qr{struct\s+$InitAttribute\s+$Ident},
our @modifierList = (
qr{fastcall},
);
+our @modifierListFile = ();
+
+our @mode_permission_funcs = (
+ ["module_param", 3],
+ ["module_param_(?:array|named|string)", 4],
+ ["module_param_array_named", 5],
+ ["debugfs_create_(?:file|u8|u16|u32|u64|x8|x16|x32|x64|size_t|atomic_t|bool|blob|regset32|u32_array)", 2],
+ ["proc_create(?:_data|)", 2],
+ ["(?:CLASS|DEVICE|SENSOR|SENSOR_DEVICE|IIO_DEVICE)_ATTR", 2],
+ ["IIO_DEV_ATTR_[A-Z_]+", 1],
+ ["SENSOR_(?:DEVICE_|)ATTR_2", 2],
+ ["SENSOR_TEMPLATE(?:_2|)", 3],
+ ["__ATTR", 2],
+);
+
+#Create a search pattern for all these functions to speed up a loop below
+our $mode_perms_search = "";
+foreach my $entry (@mode_permission_funcs) {
+ $mode_perms_search .= '|' if ($mode_perms_search ne "");
+ $mode_perms_search .= $entry->[0];
+}
+
+our $mode_perms_world_writable = qr{
+ S_IWUGO |
+ S_IWOTH |
+ S_IRWXUGO |
+ S_IALLUGO |
+ 0[0-7][0-7][2367]
+}x;
+
+our %mode_permission_string_types = (
+ "S_IRWXU" => 0700,
+ "S_IRUSR" => 0400,
+ "S_IWUSR" => 0200,
+ "S_IXUSR" => 0100,
+ "S_IRWXG" => 0070,
+ "S_IRGRP" => 0040,
+ "S_IWGRP" => 0020,
+ "S_IXGRP" => 0010,
+ "S_IRWXO" => 0007,
+ "S_IROTH" => 0004,
+ "S_IWOTH" => 0002,
+ "S_IXOTH" => 0001,
+ "S_IRWXUGO" => 0777,
+ "S_IRUGO" => 0444,
+ "S_IWUGO" => 0222,
+ "S_IXUGO" => 0111,
+);
+
+#Create a search pattern for all these strings to speed up a loop below
+our $mode_perms_string_search = "";
+foreach my $entry (keys %mode_permission_string_types) {
+ $mode_perms_string_search .= '|' if ($mode_perms_string_search ne "");
+ $mode_perms_string_search .= $entry;
+}
our $allowed_asm_includes = qr{(?x:
irq|
- memory
+ memory|
+ time|
+ reboot
)};
# memory.h: ARM has a custom one
$misspellings = join("|", sort keys %spelling_fix) if keys %spelling_fix;
+sub read_words {
+ my ($wordsRef, $file) = @_;
+
+ if (open(my $words, '<', $file)) {
+ while (<$words>) {
+ my $line = $_;
+
+ $line =~ s/\s*\n?$//g;
+ $line =~ s/^\s*//g;
+
+ next if ($line =~ m/^\s*#/);
+ next if ($line =~ m/^\s*$/);
+ if ($line =~ /\s/) {
+ print("$file: '$line' invalid - ignored\n");
+ next;
+ }
+
+ $$wordsRef .= '|' if ($$wordsRef ne "");
+ $$wordsRef .= $line;
+ }
+ close($file);
+ return 1;
+ }
+
+ return 0;
+}
+
+my $const_structs = "";
+read_words(\$const_structs, $conststructsfile)
+ or warn "No structs that should be const will be found - file '$conststructsfile': $!\n";
+
+my $typeOtherTypedefs = "";
+if (length($typedefsfile)) {
+ read_words(\$typeOtherTypedefs, $typedefsfile)
+ or warn "No additional types will be considered - file '$typedefsfile': $!\n";
+}
+$typeTypedefs .= '|' . $typeOtherTypedefs if ($typeOtherTypedefs ne "");
sub build_types {
- my $mods = "(?x: \n" . join("|\n ", @modifierList) . "\n)";
- my $all = "(?x: \n" . join("|\n ", @typeList) . "\n)";
+ my $mods = "(?x: \n" . join("|\n ", (@modifierList, @modifierListFile)) . "\n)";
+ my $all = "(?x: \n" . join("|\n ", (@typeList, @typeListFile)) . "\n)";
+ my $Misordered = "(?x: \n" . join("|\n ", @typeListMisordered) . "\n)";
my $allWithAttr = "(?x: \n" . join("|\n ", @typeListWithAttr) . "\n)";
$Modifier = qr{(?:$Attribute|$Sparse|$mods)};
+ $BasicType = qr{
+ (?:$typeTypedefs\b)|
+ (?:${all}\b)
+ }x;
$NonptrType = qr{
(?:$Modifier\s+|const\s+)*
(?:
)
(?:\s+$Modifier|\s+const)*
}x;
+ $NonptrTypeMisordered = qr{
+ (?:$Modifier\s+|const\s+)*
+ (?:
+ (?:${Misordered}\b)
+ )
+ (?:\s+$Modifier|\s+const)*
+ }x;
$NonptrTypeWithAttr = qr{
(?:$Modifier\s+|const\s+)*
(?:
}x;
$Type = qr{
$NonptrType
- (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*|\[\])+|(?:\s*\[\s*\])+)?
+ (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*\s*(?:const\s*)?|\[\])+|(?:\s*\[\s*\])+)?
+ (?:\s+$Inline|\s+$Modifier)*
+ }x;
+ $TypeMisordered = qr{
+ $NonptrTypeMisordered
+ (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*\s*(?:const\s*)?|\[\])+|(?:\s*\[\s*\])+)?
(?:\s+$Inline|\s+$Modifier)*
}x;
- $Declare = qr{(?:$Storage\s+)?$Type};
+ $Declare = qr{(?:$Storage\s+(?:$Inline\s+)?)?$Type};
+ $DeclareMisordered = qr{(?:$Storage\s+(?:$Inline\s+)?)?$TypeMisordered};
}
build_types();
# Any use must be runtime checked with $^V
our $balanced_parens = qr/(\((?:[^\(\)]++|(?-1))*\))/;
-our $LvalOrFunc = qr{($Lval)\s*($balanced_parens{0,1})\s*};
-our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant)};
+our $LvalOrFunc = qr{((?:[\&\*]\s*)?$Lval)\s*($balanced_parens{0,1})\s*};
+our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant|$String)};
+
+our $declaration_macros = qr{(?x:
+ (?:$Storage\s+)?(?:[A-Z_][A-Z0-9]*_){0,2}(?:DEFINE|DECLARE)(?:_[A-Z0-9]+){1,6}\s*\(|
+ (?:$Storage\s+)?[HLP]?LIST_HEAD\s*\(|
+ (?:$Storage\s+)?${Type}\s+uninitialized_var\s*\(
+)};
sub deparenthesize {
my ($string) = @_;
return "" if (!defined($string));
- $string =~ s@^\s*\(\s*@@g;
- $string =~ s@\s*\)\s*$@@g;
+
+ while ($string =~ /^\s*\(.*\)\s*$/) {
+ $string =~ s@^\s*\(\s*@@;
+ $string =~ s@\s*\)\s*$@@;
+ }
+
$string =~ s@\s+@ @g;
+
return $string;
}
}
}
+sub is_maintained_obsolete {
+ my ($filename) = @_;
+
+ return 0 if (!$tree || !(-e "$root/scripts/get_maintainer.pl"));
+
+ my $status = `perl $root/scripts/get_maintainer.pl --status --nom --nol --nogit --nogit-fallback -f $filename 2>&1`;
+
+ return $status =~ /obsolete/i;
+}
+
my $camelcase_seeded = 0;
sub seed_camelcase_includes {
return if ($camelcase_seeded);
}
}
+sub git_commit_info {
+ my ($commit, $id, $desc) = @_;
+
+ return ($id, $desc) if ((which("git") eq "") || !(-e ".git"));
+
+ my $output = `git log --no-color --format='%H %s' -1 $commit 2>&1`;
+ $output =~ s/^\s*//gm;
+ my @lines = split("\n", $output);
+
+ return ($id, $desc) if ($#lines < 0);
+
+ if ($lines[0] =~ /^error: short SHA1 $commit is ambiguous\./) {
+# Maybe one day convert this block of bash into something that returns
+# all matching commit ids, but it's very slow...
+#
+# echo "checking commits $1..."
+# git rev-list --remotes | grep -i "^$1" |
+# while read line ; do
+# git log --format='%H %s' -1 $line |
+# echo "commit $(cut -c 1-12,41-)"
+# done
+ } elsif ($lines[0] =~ /^fatal: ambiguous argument '$commit': unknown revision or path not in the working tree\./) {
+ $id = undef;
+ } else {
+ $id = substr($lines[0], 0, 12);
+ $desc = substr($lines[0], 41);
+ }
+
+ return ($id, $desc);
+}
+
$chk_signoff = 0 if ($file);
my @rawlines = ();
my @lines = ();
my @fixed = ();
-my $vname;
+my @fixed_inserted = ();
+my @fixed_deleted = ();
my $fixlinenr = -1;
+# If input is git commits, extract all commits from the commit expressions.
+# For example, HEAD-3 means we need check 'HEAD, HEAD~1, HEAD~2'.
+die "$P: No git repository found\n" if ($git && !-e ".git");
+
+if ($git) {
+ my @commits = ();
+ foreach my $commit_expr (@ARGV) {
+ my $git_range;
+ if ($commit_expr =~ m/^(.*)-(\d+)$/) {
+ $git_range = "-$2 $1";
+ } elsif ($commit_expr =~ m/\.\./) {
+ $git_range = "$commit_expr";
+ } else {
+ $git_range = "-1 $commit_expr";
+ }
+ my $lines = `git log --no-color --no-merges --pretty=format:'%H %s' $git_range`;
+ foreach my $line (split(/\n/, $lines)) {
+ $line =~ /^([0-9a-fA-F]{40,40}) (.*)$/;
+ next if (!defined($1) || !defined($2));
+ my $sha1 = $1;
+ my $subject = $2;
+ unshift(@commits, $sha1);
+ $git_commits{$sha1} = $subject;
+ }
+ }
+ die "$P: no git commits after extraction!\n" if (@commits == 0);
+ @ARGV = @commits;
+}
+
+my $vname;
for my $filename (@ARGV) {
my $FILE;
- if ($file) {
+ if ($git) {
+ open($FILE, '-|', "git format-patch -M --stdout -1 $filename") ||
+ die "$P: $filename: git format-patch failed - $!\n";
+ } elsif ($file) {
open($FILE, '-|', "diff -u /dev/null $filename") ||
die "$P: $filename: diff failed - $!\n";
} elsif ($filename eq '-') {
}
if ($filename eq '-') {
$vname = 'Your patch';
+ } elsif ($git) {
+ $vname = "Commit " . substr($filename, 0, 12) . ' ("' . $git_commits{$filename} . '")';
} else {
$vname = $filename;
}
push(@rawlines, $_);
}
close($FILE);
+
+ if ($#ARGV > 0 && $quiet == 0) {
+ print '-' x length($vname) . "\n";
+ print "$vname\n";
+ print '-' x length($vname) . "\n";
+ }
+
if (!process($filename)) {
$exit = 1;
}
@rawlines = ();
@lines = ();
@fixed = ();
+ @fixed_inserted = ();
+ @fixed_deleted = ();
+ $fixlinenr = -1;
+ @modifierListFile = ();
+ @typeListFile = ();
+ build_types();
+}
+
+if (!$quiet) {
+ hash_show_words(\%use_type, "Used");
+ hash_show_words(\%ignore_type, "Ignored");
+
+ if ($^V lt 5.10.0) {
+ print << "EOM"
+
+NOTE: perl $^V is not modern enough to detect all possible issues.
+ An upgrade to at least perl v5.10.0 is suggested.
+EOM
+ }
+ if ($exit) {
+ print << "EOM"
+
+NOTE: If any of the errors are false positives, please report
+ them to the maintainer, see CHECKPATCH in MAINTAINERS.
+EOM
+ }
}
exit($exit);
return $formatted_email;
}
+sub which {
+ my ($bin) = @_;
+
+ foreach my $path (split(/:/, $ENV{PATH})) {
+ if (-e "$path/$bin") {
+ return "$path/$bin";
+ }
+ }
+
+ return "";
+}
+
sub which_conf {
my ($conf) = @_;
$res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@;
}
+ if ($allow_c99_comments && $res =~ m@(//.*$)@) {
+ my $match = $1;
+ $res =~ s/\Q$match\E/"$;" x length($match)/e;
+ }
+
return $res;
}
sub get_quoted_string {
my ($line, $rawline) = @_;
- return "" if ($line !~ m/(\"[X]+\")/g);
+ return "" if ($line !~ m/($String)/g);
return substr($rawline, $-[0], $+[0] - $-[0]);
}
for my $modifier (split(' ', $possible)) {
if ($modifier !~ $notPermitted) {
warn "MODIFIER: $modifier ($possible) ($line)\n" if ($dbg_possible);
- push(@modifierList, $modifier);
+ push(@modifierListFile, $modifier);
}
}
} else {
warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible);
- push(@typeList, $possible);
+ push(@typeListFile, $possible);
}
build_types();
} else {
my $prefix = '';
sub show_type {
- return defined $use_type{$_[0]} if (scalar keys %use_type > 0);
+ my ($type) = @_;
+
+ $type =~ tr/[a-z]/[A-Z]/;
- return !defined $ignore_type{$_[0]};
+ return defined $use_type{$type} if (scalar keys %use_type > 0);
+
+ return !defined $ignore_type{$type};
}
sub report {
- if (!show_type($_[1]) ||
- (defined $tst_only && $_[2] !~ /\Q$tst_only\E/)) {
+ my ($level, $type, $msg) = @_;
+
+ if (!show_type($type) ||
+ (defined $tst_only && $msg !~ /\Q$tst_only\E/)) {
return 0;
}
- my $line;
+ my $output = '';
+ if ($color) {
+ if ($level eq 'ERROR') {
+ $output .= RED;
+ } elsif ($level eq 'WARNING') {
+ $output .= YELLOW;
+ } else {
+ $output .= GREEN;
+ }
+ }
+ $output .= $prefix . $level . ':';
if ($show_types) {
- $line = "$prefix$_[0]:$_[1]: $_[2]\n";
- } else {
- $line = "$prefix$_[0]: $_[2]\n";
+ $output .= BLUE if ($color);
+ $output .= "$type:";
+ }
+ $output .= RESET if ($color);
+ $output .= ' ' . $msg . "\n";
+
+ if ($showfile) {
+ my @lines = split("\n", $output, -1);
+ splice(@lines, 1, 1);
+ $output = join("\n", @lines);
}
- $line = (split('\n', $line))[0] . "\n" if ($terse);
+ $output = (split('\n', $output))[0] . "\n" if ($terse);
- push(our @report, $line);
+ push(our @report, $output);
return 1;
}
+
sub report_dump {
our @report;
}
+sub fixup_current_range {
+ my ($lineRef, $offset, $length) = @_;
+
+ if ($$lineRef =~ /^\@\@ -\d+,\d+ \+(\d+),(\d+) \@\@/) {
+ my $o = $1;
+ my $l = $2;
+ my $no = $o + $offset;
+ my $nl = $l + $length;
+ $$lineRef =~ s/\+$o,$l \@\@/\+$no,$nl \@\@/;
+ }
+}
+
+sub fix_inserted_deleted_lines {
+ my ($linesRef, $insertedRef, $deletedRef) = @_;
+
+ my $range_last_linenr = 0;
+ my $delta_offset = 0;
+
+ my $old_linenr = 0;
+ my $new_linenr = 0;
+
+ my $next_insert = 0;
+ my $next_delete = 0;
+
+ my @lines = ();
+
+ my $inserted = @{$insertedRef}[$next_insert++];
+ my $deleted = @{$deletedRef}[$next_delete++];
+
+ foreach my $old_line (@{$linesRef}) {
+ my $save_line = 1;
+ my $line = $old_line; #don't modify the array
+ if ($line =~ /^(?:\+\+\+|\-\-\-)\s+\S+/) { #new filename
+ $delta_offset = 0;
+ } elsif ($line =~ /^\@\@ -\d+,\d+ \+\d+,\d+ \@\@/) { #new hunk
+ $range_last_linenr = $new_linenr;
+ fixup_current_range(\$line, $delta_offset, 0);
+ }
+
+ while (defined($deleted) && ${$deleted}{'LINENR'} == $old_linenr) {
+ $deleted = @{$deletedRef}[$next_delete++];
+ $save_line = 0;
+ fixup_current_range(\$lines[$range_last_linenr], $delta_offset--, -1);
+ }
+
+ while (defined($inserted) && ${$inserted}{'LINENR'} == $old_linenr) {
+ push(@lines, ${$inserted}{'LINE'});
+ $inserted = @{$insertedRef}[$next_insert++];
+ $new_linenr++;
+ fixup_current_range(\$lines[$range_last_linenr], $delta_offset++, 1);
+ }
+
+ if ($save_line) {
+ push(@lines, $line);
+ $new_linenr++;
+ }
+
+ $old_linenr++;
+ }
+
+ return @lines;
+}
+
+sub fix_insert_line {
+ my ($linenr, $line) = @_;
+
+ my $inserted = {
+ LINENR => $linenr,
+ LINE => $line,
+ };
+ push(@fixed_inserted, $inserted);
+}
+
+sub fix_delete_line {
+ my ($linenr, $line) = @_;
+
+ my $deleted = {
+ LINENR => $linenr,
+ LINE => $line,
+ };
+
+ push(@fixed_deleted, $deleted);
+}
+
sub ERROR {
- if (report("ERROR", $_[0], $_[1])) {
+ my ($type, $msg) = @_;
+
+ if (report("ERROR", $type, $msg)) {
our $clean = 0;
our $cnt_error++;
return 1;
return 0;
}
sub WARN {
- if (report("WARNING", $_[0], $_[1])) {
+ my ($type, $msg) = @_;
+
+ if (report("WARNING", $type, $msg)) {
our $clean = 0;
our $cnt_warn++;
return 1;
return 0;
}
sub CHK {
- if ($check && report("CHECK", $_[0], $_[1])) {
+ my ($type, $msg) = @_;
+
+ if ($check && report("CHECK", $type, $msg)) {
our $clean = 0;
our $cnt_chk++;
return 1;
}
}
- return $last_openparen + 1;
+ return length(expand_tabs(substr($line, 0, $last_openparen))) + 1;
}
sub process {
our $clean = 1;
my $signoff = 0;
my $is_patch = 0;
-
- my $in_header_lines = 1;
+ my $in_header_lines = $file ? 0 : 1;
my $in_commit_log = 0; #Scanning lines before patch
-
+ my $has_commit_log = 0; #Encountered lines before patch
+ my $commit_log_possible_stack_dump = 0;
+ my $commit_log_long_line = 0;
+ my $commit_log_has_diff = 0;
+ my $reported_maintainer_file = 0;
my $non_utf8_charset = 0;
+ my $last_blank_line = 0;
+ my $last_coalesced_string_linenr = -1;
+
our @report = ();
our $cnt_lines = 0;
our $cnt_error = 0;
my $realline = 0;
my $realcnt = 0;
my $here = '';
+ my $context_function; #undef'd unless there's a known function
my $in_comment = 0;
my $comment_edge = 0;
my $first_line = 0;
if ($rawline=~/^\+\+\+\s+(\S+)/) {
$setup_docs = 0;
- if ($1 =~ m@Documentation/kernel-parameters.txt$@) {
+ if ($1 =~ m@Documentation/admin-guide/kernel-parameters.rst$@) {
$setup_docs = 1;
}
#next;
}
- if ($rawline=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) {
+ if ($rawline =~ /^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) {
$realline=$1-1;
if (defined $2) {
$realcnt=$3+1;
$realcnt = 0;
$linenr = 0;
+ $fixlinenr = -1;
foreach my $line (@lines) {
$linenr++;
+ $fixlinenr++;
my $sline = $line; #copy of $line
$sline =~ s/$;/ /g; #with comments as spaces
my $rawline = $rawlines[$linenr - 1];
#extract the line range in the file after the patch is applied
- if ($line=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) {
+ if (!$in_commit_log &&
+ $line =~ /^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@(.*)/) {
+ my $context = $4;
$is_patch = 1;
$first_line = $linenr + 1;
$realline=$1-1;
%suppress_whiletrailers = ();
%suppress_export = ();
$suppress_statement = 0;
+ if ($context =~ /\b(\w+)\s*\(/) {
+ $context_function = $1;
+ } else {
+ undef $context_function;
+ }
next;
# track the line number as we move through the hunk, note that
my $hunk_line = ($realcnt != 0);
-#make up the handle for any error we report on this line
- $prefix = "$filename:$realline: " if ($emacs && $file);
- $prefix = "$filename:$linenr: " if ($emacs && !$file);
-
$here = "#$linenr: " if (!$file);
$here = "#$realline: " if ($file);
+ my $found_file = 0;
# extract the filename as it passes
if ($line =~ /^diff --git.*?(\S+)$/) {
$realfile = $1;
$realfile =~ s@^([^/]*)/@@ if (!$file);
$in_commit_log = 0;
+ $found_file = 1;
} elsif ($line =~ /^\+\+\+\s+(\S+)/) {
$realfile = $1;
$realfile =~ s@^([^/]*)/@@ if (!$file);
ERROR("MODIFIED_INCLUDE_ASM",
"do not modify files in include/asm, change architecture specific files in include/asm-<architecture>\n" . "$here$rawline\n");
}
+ $found_file = 1;
+ }
+
+#make up the handle for any error we report on this line
+ if ($showfile) {
+ $prefix = "$realfile:$realline: "
+ } elsif ($emacs) {
+ if ($file) {
+ $prefix = "$filename:$realline: ";
+ } else {
+ $prefix = "$filename:$linenr: ";
+ }
+ }
+
+ if ($found_file) {
+ if (is_maintained_obsolete($realfile)) {
+ WARN("OBSOLETE",
+ "$realfile is marked as 'obsolete' in the MAINTAINERS hierarchy. No unnecessary modifications please.\n");
+ }
+ if ($realfile =~ m@^(?:drivers/net/|net/|drivers/staging/)@) {
+ $check = 1;
+ } else {
+ $check = $check_orig;
+ }
next;
}
$cnt_lines++ if ($realcnt != 0);
+# Check if the commit log has what seems like a diff which can confuse patch
+ if ($in_commit_log && !$commit_log_has_diff &&
+ (($line =~ m@^\s+diff\b.*a/[\w/]+@ &&
+ $line =~ m@^\s+diff\b.*a/([\w/]+)\s+b/$1\b@) ||
+ $line =~ m@^\s*(?:\-\-\-\s+a/|\+\+\+\s+b/)@ ||
+ $line =~ m/^\s*\@\@ \-\d+,\d+ \+\d+,\d+ \@\@/)) {
+ ERROR("DIFF_IN_COMMIT_MSG",
+ "Avoid using diff content in the commit message - patch(1) might not work\n" . $herecurr);
+ $commit_log_has_diff = 1;
+ }
+
# Check for incorrect file permissions
if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) {
my $permhere = $here . "FILE: $realfile\n";
$in_commit_log = 0;
}
+# Check if MAINTAINERS is being updated. If so, there's probably no need to
+# emit the "does MAINTAINERS need updating?" message on file add/move/delete
+ if ($line =~ /^\s*MAINTAINERS\s*\|/) {
+ $reported_maintainer_file = 1;
+ }
+
# Check signature styles
if (!$in_header_lines &&
$line =~ /^(\s*)([a-z0-9_-]+by:|$signature_tags)(\s*)(.*)/i) {
if (WARN("BAD_SIGN_OFF",
"Do not use whitespace before $ucfirst_sign_off\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =
+ $fixed[$fixlinenr] =
"$ucfirst_sign_off $email";
}
}
if (WARN("BAD_SIGN_OFF",
"'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =
+ $fixed[$fixlinenr] =
"$ucfirst_sign_off $email";
}
if (WARN("BAD_SIGN_OFF",
"Use a single space after $ucfirst_sign_off\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =
+ $fixed[$fixlinenr] =
"$ucfirst_sign_off $email";
}
}
}
}
+# Check email subject for common tools that don't need to be mentioned
+ if ($in_header_lines &&
+ $line =~ /^Subject:.*\b(?:checkpatch|sparse|smatch)\b[^:]/i) {
+ WARN("EMAIL_SUBJECT",
+ "A patch subject line should describe the change not the tool that found it\n" . $herecurr);
+ }
+
+# Check for old stable address
+ if ($line =~ /^\s*cc:\s*.*<?\bstable\@kernel\.org\b>?.*$/i) {
+ ERROR("STABLE_ADDRESS",
+ "The 'stable' address should be 'stable\@vger.kernel.org'\n" . $herecurr);
+ }
+
+# Check for unwanted Gerrit info
+ if ($in_commit_log && $line =~ /^\s*change-id:/i) {
+ ERROR("GERRIT_CHANGE_ID",
+ "Remove Gerrit Change-Id's before submitting upstream.\n" . $herecurr);
+ }
+
+# Check if the commit log is in a possible stack dump
+ if ($in_commit_log && !$commit_log_possible_stack_dump &&
+ ($line =~ /^\s*(?:WARNING:|BUG:)/ ||
+ $line =~ /^\s*\[\s*\d+\.\d{6,6}\s*\]/ ||
+ # timestamp
+ $line =~ /^\s*\[\<[0-9a-fA-F]{8,}\>\]/)) {
+ # stack dump address
+ $commit_log_possible_stack_dump = 1;
+ }
+
+# Check for line lengths > 75 in commit log, warn once
+ if ($in_commit_log && !$commit_log_long_line &&
+ length($line) > 75 &&
+ !($line =~ /^\s*[a-zA-Z0-9_\/\.]+\s+\|\s+\d+/ ||
+ # file delta changes
+ $line =~ /^\s*(?:[\w\.\-]+\/)++[\w\.\-]+:/ ||
+ # filename then :
+ $line =~ /^\s*(?:Fixes:|Link:)/i ||
+ # A Fixes: or Link: line
+ $commit_log_possible_stack_dump)) {
+ WARN("COMMIT_LOG_LONG_LINE",
+ "Possible unwrapped commit description (prefer a maximum 75 chars per line)\n" . $herecurr);
+ $commit_log_long_line = 1;
+ }
+
+# Reset possible stack dump if a blank line is found
+ if ($in_commit_log && $commit_log_possible_stack_dump &&
+ $line =~ /^\s*$/) {
+ $commit_log_possible_stack_dump = 0;
+ }
+
+# Check for git id commit length and improperly formed commit descriptions
+ if ($in_commit_log && !$commit_log_possible_stack_dump &&
+ $line !~ /^\s*(?:Link|Patchwork|http|https|BugLink):/i &&
+ $line !~ /^This reverts commit [0-9a-f]{7,40}/ &&
+ ($line =~ /\bcommit\s+[0-9a-f]{5,}\b/i ||
+ ($line =~ /(?:\s|^)[0-9a-f]{12,40}(?:[\s"'\(\[]|$)/i &&
+ $line !~ /[\<\[][0-9a-f]{12,40}[\>\]]/i &&
+ $line !~ /\bfixes:\s*[0-9a-f]{12,40}/i))) {
+ my $init_char = "c";
+ my $orig_commit = "";
+ my $short = 1;
+ my $long = 0;
+ my $case = 1;
+ my $space = 1;
+ my $hasdesc = 0;
+ my $hasparens = 0;
+ my $id = '0123456789ab';
+ my $orig_desc = "commit description";
+ my $description = "";
+
+ if ($line =~ /\b(c)ommit\s+([0-9a-f]{5,})\b/i) {
+ $init_char = $1;
+ $orig_commit = lc($2);
+ } elsif ($line =~ /\b([0-9a-f]{12,40})\b/i) {
+ $orig_commit = lc($1);
+ }
+
+ $short = 0 if ($line =~ /\bcommit\s+[0-9a-f]{12,40}/i);
+ $long = 1 if ($line =~ /\bcommit\s+[0-9a-f]{41,}/i);
+ $space = 0 if ($line =~ /\bcommit [0-9a-f]/i);
+ $case = 0 if ($line =~ /\b[Cc]ommit\s+[0-9a-f]{5,40}[^A-F]/);
+ if ($line =~ /\bcommit\s+[0-9a-f]{5,}\s+\("([^"]+)"\)/i) {
+ $orig_desc = $1;
+ $hasparens = 1;
+ } elsif ($line =~ /\bcommit\s+[0-9a-f]{5,}\s*$/i &&
+ defined $rawlines[$linenr] &&
+ $rawlines[$linenr] =~ /^\s*\("([^"]+)"\)/) {
+ $orig_desc = $1;
+ $hasparens = 1;
+ } elsif ($line =~ /\bcommit\s+[0-9a-f]{5,}\s+\("[^"]+$/i &&
+ defined $rawlines[$linenr] &&
+ $rawlines[$linenr] =~ /^\s*[^"]+"\)/) {
+ $line =~ /\bcommit\s+[0-9a-f]{5,}\s+\("([^"]+)$/i;
+ $orig_desc = $1;
+ $rawlines[$linenr] =~ /^\s*([^"]+)"\)/;
+ $orig_desc .= " " . $1;
+ $hasparens = 1;
+ }
+
+ ($id, $description) = git_commit_info($orig_commit,
+ $id, $orig_desc);
+
+ if (defined($id) &&
+ ($short || $long || $space || $case || ($orig_desc ne $description) || !$hasparens)) {
+ ERROR("GIT_COMMIT_ID",
+ "Please use git commit description style 'commit <12+ chars of sha1> (\"<title line>\")' - ie: '${init_char}ommit $id (\"$description\")'\n" . $herecurr);
+ }
+ }
+
+# Check for added, moved or deleted files
+ if (!$reported_maintainer_file && !$in_commit_log &&
+ ($line =~ /^(?:new|deleted) file mode\s*\d+\s*$/ ||
+ $line =~ /^rename (?:from|to) [\w\/\.\-]+\s*$/ ||
+ ($line =~ /\{\s*([\w\/\.\-]*)\s*\=\>\s*([\w\/\.\-]*)\s*\}/ &&
+ (defined($1) || defined($2))))) {
+ $is_patch = 1;
+ $reported_maintainer_file = 1;
+ WARN("FILE_PATH_CHANGES",
+ "added, moved or deleted file(s), does MAINTAINERS need updating?\n" . $herecurr);
+ }
+
# Check for wrappage within a valid hunk of the file
if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) {
ERROR("CORRUPTED_PATCH",
$herecurr) if (!$emitted_corrupt++);
}
-# Check for absolute kernel paths.
- if ($tree) {
- while ($line =~ m{(?:^|\s)(/\S*)}g) {
- my $file = $1;
-
- if ($file =~ m{^(.*?)(?::\d+)+:?$} &&
- check_absolute_file($1, $herecurr)) {
- #
- } else {
- check_absolute_file($file, $herecurr);
- }
- }
- }
-
# UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php
if (($realfile =~ /^$/ || $line =~ /^\+/) &&
$rawline !~ m/^$UTF8*$/) {
# Check if it's the start of a commit log
# (not a header line and we haven't seen the patch filename)
if ($in_header_lines && $realfile =~ /^$/ &&
- $rawline !~ /^(commit\b|from\b|[\w-]+:).+$/i) {
+ !($rawline =~ /^\s+(?:\S|$)/ ||
+ $rawline =~ /^(?:commit\b|from\b|[\w-]+:)/i)) {
$in_header_lines = 0;
$in_commit_log = 1;
+ $has_commit_log = 1;
}
# Check if there is UTF-8 in a commit log when a mail header has explicitly
"8-bit UTF-8 used in possible commit log\n" . $herecurr);
}
+# Check for absolute kernel paths in commit message
+ if ($tree && $in_commit_log) {
+ while ($line =~ m{(?:^|\s)(/\S*)}g) {
+ my $file = $1;
+
+ if ($file =~ m{^(.*?)(?::\d+)+:?$} &&
+ check_absolute_file($1, $herecurr)) {
+ #
+ } else {
+ check_absolute_file($file, $herecurr);
+ }
+ }
+ }
+
# Check for various typo / spelling mistakes
if (defined($misspellings) &&
($in_commit_log || $line =~ /^(?:\+|Subject:)/i)) {
if (ERROR("DOS_LINE_ENDINGS",
"DOS line endings\n" . $herevet) &&
$fix) {
- $fixed[$linenr - 1] =~ s/[\s\015]+$//;
+ $fixed[$fixlinenr] =~ s/[\s\015]+$//;
}
} elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) {
my $herevet = "$here\n" . cat_vet($rawline) . "\n";
if (ERROR("TRAILING_WHITESPACE",
"trailing whitespace\n" . $herevet) &&
$fix) {
- $fixed[$linenr - 1] =~ s/\s+$//;
+ $fixed[$fixlinenr] =~ s/\s+$//;
}
$rpt_cleaners = 1;
# Check for FSF mailing addresses.
if ($rawline =~ /\bwrite to the Free/i ||
+ $rawline =~ /\b675\s+Mass\s+Ave/i ||
$rawline =~ /\b59\s+Temple\s+Pl/i ||
$rawline =~ /\b51\s+Franklin\s+St/i) {
my $herevet = "$here\n" . cat_vet($rawline) . "\n";
# Only applies when adding the entry originally, after that we do not have
# sufficient context to determine whether it is indeed long enough.
if ($realfile =~ /Kconfig/ &&
- $line =~ /.\s*config\s+/) {
+ $line =~ /^\+\s*config\s+/) {
my $length = 0;
my $cnt = $realcnt;
my $ln = $linenr + 1;
$is_end = $lines[$ln - 1] =~ /^\+/;
next if ($f =~ /^-/);
+ last if (!$file && $f =~ /^\@\@/);
- if ($lines[$ln - 1] =~ /.\s*(?:bool|tristate)\s*\"/) {
+ if ($lines[$ln - 1] =~ /^\+\s*(?:bool|tristate)\s*\"/) {
$is_start = 1;
- } elsif ($lines[$ln - 1] =~ /.\s*(?:---)?help(?:---)?$/) {
+ } elsif ($lines[$ln - 1] =~ /^\+\s*(?:---)?help(?:---)?$/) {
$length = -1;
}
}
$length++;
}
- WARN("CONFIG_DESCRIPTION",
- "please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_start && $is_end && $length < 4);
+ if ($is_start && $is_end && $length < $min_conf_desc_length) {
+ WARN("CONFIG_DESCRIPTION",
+ "please write a paragraph that describes the config symbol fully\n" . $herecurr);
+ }
#print "is_start<$is_start> is_end<$is_end> length<$length>\n";
}
-# discourage the addition of CONFIG_EXPERIMENTAL in Kconfig.
+# check for MAINTAINERS entries that don't have the right form
+ if ($realfile =~ /^MAINTAINERS$/ &&
+ $rawline =~ /^\+[A-Z]:/ &&
+ $rawline !~ /^\+[A-Z]:\t\S/) {
+ if (WARN("MAINTAINERS_STYLE",
+ "MAINTAINERS entries use one tab after TYPE:\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/^(\+[A-Z]):\s*/$1:\t/;
+ }
+ }
+
+# discourage the use of boolean for type definition attributes of Kconfig options
if ($realfile =~ /Kconfig/ &&
- $line =~ /.\s*depends on\s+.*\bEXPERIMENTAL\b/) {
- WARN("CONFIG_EXPERIMENTAL",
- "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n");
+ $line =~ /^\+\s*\bboolean\b/) {
+ WARN("CONFIG_TYPE_BOOLEAN",
+ "Use of boolean is deprecated, please use bool instead.\n" . $herecurr);
}
if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) &&
}
# check for DT compatible documentation
- if (defined $root && $realfile =~ /\.dts/ &&
- $rawline =~ /^\+\s*compatible\s*=/) {
+ if (defined $root &&
+ (($realfile =~ /\.dtsi?$/ && $line =~ /^\+\s*compatible\s*=\s*\"/) ||
+ ($realfile =~ /\.[ch]$/ && $line =~ /^\+.*\.compatible\s*=\s*\"/))) {
+
my @compats = $rawline =~ /\"([a-zA-Z0-9\-\,\.\+_]+)\"/g;
+ my $dt_path = $root . "/Documentation/devicetree/bindings/";
+ my $vp_file = $dt_path . "vendor-prefixes.txt";
+
foreach my $compat (@compats) {
my $compat2 = $compat;
- my $dt_path = $root . "/Documentation/devicetree/bindings/";
- $compat2 =~ s/\,[a-z]*\-/\,<\.\*>\-/;
- `grep -Erq "$compat|$compat2" $dt_path`;
+ $compat2 =~ s/\,[a-zA-Z0-9]*\-/\,<\.\*>\-/;
+ my $compat3 = $compat;
+ $compat3 =~ s/\,([a-z]*)[0-9]*\-/\,$1<\.\*>\-/;
+ `grep -Erq "$compat|$compat2|$compat3" $dt_path`;
if ( $? >> 8 ) {
WARN("UNDOCUMENTED_DT_STRING",
"DT compatible string \"$compat\" appears un-documented -- check $dt_path\n" . $herecurr);
}
- my $vendor = $compat;
- my $vendor_path = $dt_path . "vendor-prefixes.txt";
- next if (! -f $vendor_path);
- $vendor =~ s/^([a-zA-Z0-9]+)\,.*/$1/;
- `grep -Eq "$vendor" $vendor_path`;
+ next if $compat !~ /^([a-zA-Z0-9\-]+)\,/;
+ my $vendor = $1;
+ `grep -Eq "^$vendor\\b" $vp_file`;
if ( $? >> 8 ) {
WARN("UNDOCUMENTED_DT_STRING",
- "DT compatible string vendor \"$vendor\" appears un-documented -- check $vendor_path\n" . $herecurr);
+ "DT compatible string vendor \"$vendor\" appears un-documented -- check $vp_file\n" . $herecurr);
}
}
}
# check we are in a valid source file if not then ignore this hunk
- next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/);
-
-#line length limit
- if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ &&
- $rawline !~ /^.\s*\*\s*\@$Ident\s/ &&
- !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:|,|\)\s*;)\s*$/ ||
- $line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) &&
- $length > $max_line_length)
- {
- WARN("LONG_LINE",
- "line over $max_line_length characters\n" . $herecurr);
- }
+ next if ($realfile !~ /\.(h|c|s|S|sh|dtsi|dts)$/);
-# Check for user-visible strings broken across lines, which breaks the ability
-# to grep for the string. Make exceptions when the previous string ends in a
-# newline (multiple lines in one string constant) or '\t', '\r', ';', or '{'
-# (common in inline assembly) or is a octal \123 or hexadecimal \xaf value
- if ($line =~ /^\+\s*"/ &&
- $prevline =~ /"\s*$/ &&
- $prevrawline !~ /(?:\\(?:[ntr]|[0-7]{1,3}|x[0-9a-fA-F]{1,2})|;\s*|\{\s*)"\s*$/) {
- WARN("SPLIT_STRING",
- "quoted string split across lines\n" . $hereprev);
- }
+# line length limit (with some exclusions)
+#
+# There are a few types of lines that may extend beyond $max_line_length:
+# logging functions like pr_info that end in a string
+# lines with a single string
+# #defines that are a single string
+#
+# There are 3 different line length message types:
+# LONG_LINE_COMMENT a comment starts before but extends beyond $max_linelength
+# LONG_LINE_STRING a string starts before but extends beyond $max_line_length
+# LONG_LINE all other lines longer than $max_line_length
+#
+# if LONG_LINE is ignored, the other 2 types are also ignored
+#
-# check for spaces before a quoted newline
- if ($rawline =~ /^.*\".*\s\\n/) {
- if (WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE",
- "unnecessary whitespace before a quoted newline\n" . $herecurr) &&
- $fix) {
- $fixed[$linenr - 1] =~ s/^(\+.*\".*)\s+\\n/$1\\n/;
+ if ($line =~ /^\+/ && $length > $max_line_length) {
+ my $msg_type = "LONG_LINE";
+
+ # Check the allowed long line types first
+
+ # logging functions that end in a string that starts
+ # before $max_line_length
+ if ($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(?:KERN_\S+\s*|[^"]*))?($String\s*(?:|,|\)\s*;)\s*)$/ &&
+ length(expand_tabs(substr($line, 1, length($line) - length($1) - 1))) <= $max_line_length) {
+ $msg_type = "";
+
+ # lines with only strings (w/ possible termination)
+ # #defines with only strings
+ } elsif ($line =~ /^\+\s*$String\s*(?:\s*|,|\)\s*;)\s*$/ ||
+ $line =~ /^\+\s*#\s*define\s+\w+\s+$String$/) {
+ $msg_type = "";
+
+ # EFI_GUID is another special case
+ } elsif ($line =~ /^\+.*\bEFI_GUID\s*\(/) {
+ $msg_type = "";
+
+ # Otherwise set the alternate message types
+
+ # a comment starts before $max_line_length
+ } elsif ($line =~ /($;[\s$;]*)$/ &&
+ length(expand_tabs(substr($line, 1, length($line) - length($1) - 1))) <= $max_line_length) {
+ $msg_type = "LONG_LINE_COMMENT"
+
+ # a quoted string starts before $max_line_length
+ } elsif ($sline =~ /\s*($String(?:\s*(?:\\|,\s*|\)\s*;\s*))?)$/ &&
+ length(expand_tabs(substr($line, 1, length($line) - length($1) - 1))) <= $max_line_length) {
+ $msg_type = "LONG_LINE_STRING"
}
+ if ($msg_type ne "" &&
+ (show_type("LONG_LINE") || show_type($msg_type))) {
+ WARN($msg_type,
+ "line over $max_line_length characters\n" . $herecurr);
+ }
}
# check for adding lines without a newline.
}
# check we are in a valid source file C or perl if not then ignore this hunk
- next if ($realfile !~ /\.(h|c|pl)$/);
+ next if ($realfile !~ /\.(h|c|pl|dtsi|dts)$/);
# at the beginning of a line any tabs must come first and anything
# more than 8 must use tabs.
if (ERROR("CODE_INDENT",
"code indent should use tabs where possible\n" . $herevet) &&
$fix) {
- $fixed[$linenr - 1] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e;
+ $fixed[$fixlinenr] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e;
}
}
if (WARN("SPACE_BEFORE_TAB",
"please, no space before tabs\n" . $herevet) &&
$fix) {
- while ($fixed[$linenr - 1] =~
+ while ($fixed[$fixlinenr] =~
s/(^\+.*) {8,8}\t/$1\t\t/) {}
- while ($fixed[$linenr - 1] =~
+ while ($fixed[$fixlinenr] =~
s/(^\+.*) +\t/$1\t/) {}
}
}
"Logical continuations should be on the previous line\n" . $hereprev);
}
+# check indentation starts on a tab stop
+ if ($^V && $^V ge 5.10.0 &&
+ $sline =~ /^\+\t+( +)(?:$c90_Keywords\b|\{\s*$|\}\s*(?:else\b|while\b|\s*$))/) {
+ my $indent = length($1);
+ if ($indent % 8) {
+ if (WARN("TABSTOP",
+ "Statements should start on a tabstop\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s@(^\+\t+) +@$1 . "\t" x ($indent/8)@e;
+ }
+ }
+ }
+
# check multi-line statement indentation matches previous line
if ($^V && $^V ge 5.10.0 &&
- $prevline =~ /^\+(\t*)(if \(|$Ident\().*(\&\&|\|\||,)\s*$/) {
+ $prevline =~ /^\+([ \t]*)((?:$c90_Keywords(?:\s+if)\s*)|(?:$Declare\s*)?(?:$Ident|\(\s*\*\s*$Ident\s*\))\s*|(?:\*\s*)*$Lval\s*=\s*$Ident\s*)\(.*(\&\&|\|\||,)\s*$/) {
$prevline =~ /^\+(\t*)(.*)$/;
my $oldindent = $1;
my $rest = $2;
if (CHK("PARENTHESIS_ALIGNMENT",
"Alignment should match open parenthesis\n" . $hereprev) &&
$fix && $line =~ /^\+/) {
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s/^\+[ \t]*/\+$goodtabindent/;
}
}
}
}
- if ($line =~ /^\+.*\*[ \t]*\)[ \t]+(?!$Assignment|$Arithmetic)/) {
+# check for space after cast like "(int) foo" or "(struct foo) bar"
+# avoid checking a few false positives:
+# "sizeof(<type>)" or "__alignof__(<type>)"
+# function pointer declarations like "(*foo)(int) = bar;"
+# structure definitions like "(struct foo) { 0 };"
+# multiline macros that define functions
+# known attributes or the __attribute__ keyword
+ if ($line =~ /^\+(.*)\(\s*$Type\s*\)([ \t]++)((?![={]|\\$|$Attribute|__attribute__))/ &&
+ (!defined($1) || $1 !~ /\b(?:sizeof|__alignof__)\s*$/)) {
if (CHK("SPACING",
- "No space is necessary after a cast\n" . $hereprev) &&
+ "No space is necessary after a cast\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~
- s/^(\+.*\*[ \t]*\))[ \t]+/$1/;
+ $fixed[$fixlinenr] =~
+ s/(\(\s*$Type\s*\))[ \t]+/$1/;
}
}
+# Block comment styles
+# Networking with an initial /*
if ($realfile =~ m@^(drivers/net/|net/)@ &&
$prevrawline =~ /^\+[ \t]*\/\*[ \t]*$/ &&
- $rawline =~ /^\+[ \t]*\*/) {
+ $rawline =~ /^\+[ \t]*\*/ &&
+ $realline > 2) {
WARN("NETWORKING_BLOCK_COMMENT_STYLE",
"networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev);
}
- if ($realfile =~ m@^(drivers/net/|net/)@ &&
- $prevrawline =~ /^\+[ \t]*\/\*/ && #starting /*
+# Block comments use * on subsequent lines
+ if ($prevline =~ /$;[ \t]*$/ && #ends in comment
+ $prevrawline =~ /^\+.*?\/\*/ && #starting /*
$prevrawline !~ /\*\/[ \t]*$/ && #no trailing */
$rawline =~ /^\+/ && #line is new
$rawline !~ /^\+[ \t]*\*/) { #no leading *
- WARN("NETWORKING_BLOCK_COMMENT_STYLE",
- "networking block comments start with * on subsequent lines\n" . $hereprev);
+ WARN("BLOCK_COMMENT_STYLE",
+ "Block comments use * on subsequent lines\n" . $hereprev);
}
- if ($realfile =~ m@^(drivers/net/|net/)@ &&
- $rawline !~ m@^\+[ \t]*\*/[ \t]*$@ && #trailing */
+# Block comments use */ on trailing lines
+ if ($rawline !~ m@^\+[ \t]*\*/[ \t]*$@ && #trailing */
$rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ && #inline /*...*/
$rawline !~ m@^\+.*\*{2,}/[ \t]*$@ && #trailing **/
$rawline =~ m@^\+[ \t]*.+\*\/[ \t]*$@) { #non blank */
- WARN("NETWORKING_BLOCK_COMMENT_STYLE",
- "networking block comments put the trailing */ on a separate line\n" . $herecurr);
+ WARN("BLOCK_COMMENT_STYLE",
+ "Block comments use a trailing */ on a separate line\n" . $herecurr);
+ }
+
+# Block comment * alignment
+ if ($prevline =~ /$;[ \t]*$/ && #ends in comment
+ $line =~ /^\+[ \t]*$;/ && #leading comment
+ $rawline =~ /^\+[ \t]*\*/ && #leading *
+ (($prevrawline =~ /^\+.*?\/\*/ && #leading /*
+ $prevrawline !~ /\*\/[ \t]*$/) || #no trailing */
+ $prevrawline =~ /^\+[ \t]*\*/)) { #leading *
+ my $oldindent;
+ $prevrawline =~ m@^\+([ \t]*/?)\*@;
+ if (defined($1)) {
+ $oldindent = expand_tabs($1);
+ } else {
+ $prevrawline =~ m@^\+(.*/?)\*@;
+ $oldindent = expand_tabs($1);
+ }
+ $rawline =~ m@^\+([ \t]*)\*@;
+ my $newindent = $1;
+ $newindent = expand_tabs($newindent);
+ if (length($oldindent) ne length($newindent)) {
+ WARN("BLOCK_COMMENT_STYLE",
+ "Block comments should align the * on each line\n" . $hereprev);
+ }
+ }
+
+# check for missing blank lines after struct/union declarations
+# with exceptions for various attributes and macros
+ if ($prevline =~ /^[\+ ]};?\s*$/ &&
+ $line =~ /^\+/ &&
+ !($line =~ /^\+\s*$/ ||
+ $line =~ /^\+\s*EXPORT_SYMBOL/ ||
+ $line =~ /^\+\s*MODULE_/i ||
+ $line =~ /^\+\s*\#\s*(?:end|elif|else)/ ||
+ $line =~ /^\+[a-z_]*init/ ||
+ $line =~ /^\+\s*(?:static\s+)?[A-Z_]*ATTR/ ||
+ $line =~ /^\+\s*DECLARE/ ||
+ $line =~ /^\+\s*__setup/)) {
+ if (CHK("LINE_SPACING",
+ "Please use a blank line after function/struct/union/enum declarations\n" . $hereprev) &&
+ $fix) {
+ fix_insert_line($fixlinenr, "\+");
+ }
+ }
+
+# check for multiple consecutive blank lines
+ if ($prevline =~ /^[\+ ]\s*$/ &&
+ $line =~ /^\+\s*$/ &&
+ $last_blank_line != ($linenr - 1)) {
+ if (CHK("LINE_SPACING",
+ "Please don't use multiple blank lines\n" . $hereprev) &&
+ $fix) {
+ fix_delete_line($fixlinenr, $rawline);
+ }
+
+ $last_blank_line = $linenr;
+ }
+
+# check for missing blank lines after declarations
+ if ($sline =~ /^\+\s+\S/ && #Not at char 1
+ # actual declarations
+ ($prevline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ ||
+ # function pointer declarations
+ $prevline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ ||
+ # foo bar; where foo is some local typedef or #define
+ $prevline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ ||
+ # known declaration macros
+ $prevline =~ /^\+\s+$declaration_macros/) &&
+ # for "else if" which can look like "$Ident $Ident"
+ !($prevline =~ /^\+\s+$c90_Keywords\b/ ||
+ # other possible extensions of declaration lines
+ $prevline =~ /(?:$Compare|$Assignment|$Operators)\s*$/ ||
+ # not starting a section or a macro "\" extended line
+ $prevline =~ /(?:\{\s*|\\)$/) &&
+ # looks like a declaration
+ !($sline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ ||
+ # function pointer declarations
+ $sline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ ||
+ # foo bar; where foo is some local typedef or #define
+ $sline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ ||
+ # known declaration macros
+ $sline =~ /^\+\s+$declaration_macros/ ||
+ # start of struct or union or enum
+ $sline =~ /^\+\s+(?:union|struct|enum|typedef)\b/ ||
+ # start or end of block or continuation of declaration
+ $sline =~ /^\+\s+(?:$|[\{\}\.\#\"\?\:\(\[])/ ||
+ # bitfield continuation
+ $sline =~ /^\+\s+$Ident\s*:\s*\d+\s*[,;]/ ||
+ # other possible extensions of declaration lines
+ $sline =~ /^\+\s+\(?\s*(?:$Compare|$Assignment|$Operators)/) &&
+ # indentation of previous and current line are the same
+ (($prevline =~ /\+(\s+)\S/) && $sline =~ /^\+$1\S/)) {
+ if (WARN("LINE_SPACING",
+ "Missing a blank line after declarations\n" . $hereprev) &&
+ $fix) {
+ fix_insert_line($fixlinenr, "\+");
+ }
}
# check for spaces at the beginning of a line.
if (WARN("LEADING_SPACE",
"please, no spaces at the start of a line\n" . $herevet) &&
$fix) {
- $fixed[$linenr - 1] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e;
+ $fixed[$fixlinenr] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e;
}
}
# check we are in a valid C source file if not then ignore this hunk
next if ($realfile !~ /\.(h|c)$/);
-# discourage the addition of CONFIG_EXPERIMENTAL in #if(def).
- if ($line =~ /^\+\s*\#\s*if.*\bCONFIG_EXPERIMENTAL\b/) {
- WARN("CONFIG_EXPERIMENTAL",
- "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n");
+# check if this appears to be the start function declaration, save the name
+ if ($sline =~ /^\+\{\s*$/ &&
+ $prevline =~ /^\+(?:(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*)?($Ident)\(/) {
+ $context_function = $1;
+ }
+
+# check if this appears to be the end of function declaration
+ if ($sline =~ /^\+\}\s*$/) {
+ undef $context_function;
+ }
+
+# check indentation of any line with a bare else
+# (but not if it is a multiple line "if (foo) return bar; else return baz;")
+# if the previous line is a break or return and is indented 1 tab more...
+ if ($sline =~ /^\+([\t]+)(?:}[ \t]*)?else(?:[ \t]*{)?\s*$/) {
+ my $tabs = length($1) + 1;
+ if ($prevline =~ /^\+\t{$tabs,$tabs}break\b/ ||
+ ($prevline =~ /^\+\t{$tabs,$tabs}return\b/ &&
+ defined $lines[$linenr] &&
+ $lines[$linenr] !~ /^[ \+]\t{$tabs,$tabs}return/)) {
+ WARN("UNNECESSARY_ELSE",
+ "else is not generally useful after a break or return\n" . $hereprev);
+ }
+ }
+
+# check indentation of a line with a break;
+# if the previous line is a goto or return and is indented the same # of tabs
+ if ($sline =~ /^\+([\t]+)break\s*;\s*$/) {
+ my $tabs = $1;
+ if ($prevline =~ /^\+$tabs(?:goto|return)\b/) {
+ WARN("UNNECESSARY_BREAK",
+ "break is not useful after a goto or return\n" . $hereprev);
+ }
}
# check for RCS/CVS revision markers
my ($stat, $cond, $line_nr_next, $remain_next, $off_next,
$realline_next);
#print "LINE<$line>\n";
- if ($linenr >= $suppress_statement &&
+ if ($linenr > $suppress_statement &&
$realcnt && $sline =~ /.\s*\S/) {
($stat, $cond, $line_nr_next, $remain_next, $off_next) =
ctx_statement_block($linenr, $realcnt, 0);
# if/while/etc brace do not go on next line, unless defining a do while loop,
# or if that brace on the next line is for something else
- if ($line =~ /(.*)\b((?:if|while|for|switch)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) {
+ if ($line =~ /(.*)\b((?:if|while|for|switch|(?:[a-z_]+|)for_each[a-z_]+)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) {
my $pre_ctx = "$1$2";
my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0);
#print "realcnt<$realcnt> ctx_cnt<$ctx_cnt>\n";
#print "pre<$pre_ctx>\nline<$line>\nctx<$ctx>\nnext<$lines[$ctx_ln - 1]>\n";
- if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln -1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) {
+ if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln - 1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) {
ERROR("OPEN_BRACE",
"that open brace { should be on the previous line\n" .
"$here\n$ctx\n$rawlines[$ctx_ln - 1]\n");
}
# Check relative indent for conditionals and blocks.
- if ($line =~ /\b(?:(?:if|while|for)\s*\(|do\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) {
+ if ($line =~ /\b(?:(?:if|while|for|(?:[a-z_]+|)for_each[a-z_]+)\s*\(|(?:do|else)\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) {
($stat, $cond, $line_nr_next, $remain_next, $off_next) =
ctx_statement_block($linenr, $realcnt, 0)
if (!defined $stat);
substr($s, 0, length($c), '');
- # Make sure we remove the line prefixes as we have
- # none on the first line, and are going to readd them
- # where necessary.
- $s =~ s/\n./\n/gs;
+ # remove inline comments
+ $s =~ s/$;/ /g;
+ $c =~ s/$;/ /g;
# Find out how long the conditional actually is.
my @newlines = ($c =~ /\n/gs);
my $cond_lines = 1 + $#newlines;
+ # Make sure we remove the line prefixes as we have
+ # none on the first line, and are going to readd them
+ # where necessary.
+ $s =~ s/\n./\n/gs;
+ while ($s =~ /\n\s+\\\n/) {
+ $cond_lines += $s =~ s/\n\s+\\\n/\n/g;
+ }
+
# We want to check the first line inside the block
# starting at the end of the conditional, so remove:
# 1) any blank line termination
#print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n";
- if ($check && (($sindent % 8) != 0 ||
- ($sindent <= $indent && $s ne ''))) {
+ if ($check && $s ne '' &&
+ (($sindent % 8) != 0 ||
+ ($sindent < $indent) ||
+ ($sindent == $indent &&
+ ($s !~ /^\s*(?:\}|\{|else\b)/)) ||
+ ($sindent > $indent + 8))) {
WARN("SUSPECT_CODE_INDENT",
"suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n");
}
#ignore lines not being added
next if ($line =~ /^[^\+]/);
+# check for dereferences that span multiple lines
+ if ($prevline =~ /^\+.*$Lval\s*(?:\.|->)\s*$/ &&
+ $line =~ /^\+\s*(?!\#\s*(?!define\s+|if))\s*$Lval/) {
+ $prevline =~ /($Lval\s*(?:\.|->))\s*$/;
+ my $ref = $1;
+ $line =~ /^.\s*($Lval)/;
+ $ref .= $1;
+ $ref =~ s/\s//g;
+ WARN("MULTILINE_DEREFERENCE",
+ "Avoid multiple line dereference - prefer '$ref'\n" . $hereprev);
+ }
+
+# check for declarations of signed or unsigned without int
+ while ($line =~ m{\b($Declare)\s*(?!char\b|short\b|int\b|long\b)\s*($Ident)?\s*[=,;\[\)\(]}g) {
+ my $type = $1;
+ my $var = $2;
+ $var = "" if (!defined $var);
+ if ($type =~ /^(?:(?:$Storage|$Inline|$Attribute)\s+)*((?:un)?signed)((?:\s*\*)*)\s*$/) {
+ my $sign = $1;
+ my $pointer = $2;
+
+ $pointer = "" if (!defined $pointer);
+
+ if (WARN("UNSPECIFIED_INT",
+ "Prefer '" . trim($sign) . " int" . rtrim($pointer) . "' to bare use of '$sign" . rtrim($pointer) . "'\n" . $herecurr) &&
+ $fix) {
+ my $decl = trim($sign) . " int ";
+ my $comp_pointer = $pointer;
+ $comp_pointer =~ s/\s//g;
+ $decl .= $comp_pointer;
+ $decl = rtrim($decl) if ($var eq "");
+ $fixed[$fixlinenr] =~ s@\b$sign\s*\Q$pointer\E\s*$var\b@$decl$var@;
+ }
+ }
+ }
+
# TEST: allow direct testing of the type matcher.
if ($dbg_type) {
if ($line =~ /^.\s*$Declare\s*$/) {
# check for initialisation to aggregates open brace on the next line
if ($line =~ /^.\s*{/ &&
$prevline =~ /(?:^|[^=])=\s*$/) {
- ERROR("OPEN_BRACE",
- "that open brace { should be on the previous line\n" . $hereprev);
+ if (ERROR("OPEN_BRACE",
+ "that open brace { should be on the previous line\n" . $hereprev) &&
+ $fix && $prevline =~ /^\+/ && $line =~ /^\+/) {
+ fix_delete_line($fixlinenr - 1, $prevrawline);
+ fix_delete_line($fixlinenr, $rawline);
+ my $fixedline = $prevrawline;
+ $fixedline =~ s/\s*=\s*$/ = {/;
+ fix_insert_line($fixlinenr, $fixedline);
+ $fixedline = $line;
+ $fixedline =~ s/^(.\s*)\{\s*/$1/;
+ fix_insert_line($fixlinenr, $fixedline);
+ }
}
#
if (ERROR("C99_COMMENTS",
"do not use C99 // comments\n" . $herecurr) &&
$fix) {
- my $line = $fixed[$linenr - 1];
+ my $line = $fixed[$fixlinenr];
if ($line =~ /\/\/(.*)$/) {
my $comment = trim($1);
- $fixed[$linenr - 1] =~ s@\/\/(.*)$@/\* $comment \*/@;
+ $fixed[$fixlinenr] =~ s@\/\/(.*)$@/\* $comment \*/@;
}
}
}
}
# check for global initialisers.
- if ($line =~ /^\+(\s*$Type\s*$Ident\s*(?:\s+$Modifier))*\s*=\s*(0|NULL|false)\s*;/) {
+ if ($line =~ /^\+$Type\s*$Ident(?:\s+$Modifier)*\s*=\s*($zero_initializer)\s*;/) {
if (ERROR("GLOBAL_INITIALISERS",
- "do not initialise globals to 0 or NULL\n" .
- $herecurr) &&
+ "do not initialise globals to $1\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~ s/($Type\s*$Ident\s*(?:\s+$Modifier))*\s*=\s*(0|NULL|false)\s*;/$1;/;
+ $fixed[$fixlinenr] =~ s/(^.$Type\s*$Ident(?:\s+$Modifier)*)\s*=\s*$zero_initializer\s*;/$1;/;
}
}
# check for static initialisers.
- if ($line =~ /^\+.*\bstatic\s.*=\s*(0|NULL|false)\s*;/) {
+ if ($line =~ /^\+.*\bstatic\s.*=\s*($zero_initializer)\s*;/) {
if (ERROR("INITIALISED_STATIC",
- "do not initialise statics to 0 or NULL\n" .
+ "do not initialise statics to $1\n" .
$herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~ s/(\bstatic\s.*?)\s*=\s*(0|NULL|false)\s*;/$1;/;
+ $fixed[$fixlinenr] =~ s/(\bstatic\s.*?)\s*=\s*$zero_initializer\s*;/$1;/;
}
}
+# check for misordered declarations of char/short/int/long with signed/unsigned
+ while ($sline =~ m{(\b$TypeMisordered\b)}g) {
+ my $tmp = trim($1);
+ WARN("MISORDERED_TYPE",
+ "type '$tmp' should be specified in [[un]signed] [short|int|long|long long] order\n" . $herecurr);
+ }
+
# check for static const char * arrays.
if ($line =~ /\bstatic\s+const\s+char\s*\*\s*(\w+)\s*\[\s*\]\s*=\s*/) {
WARN("STATIC_CONST_CHAR_ARRAY",
$herecurr);
}
+# check for const <foo> const where <foo> is not a pointer or array type
+ if ($sline =~ /\bconst\s+($BasicType)\s+const\b/) {
+ my $found = $1;
+ if ($sline =~ /\bconst\s+\Q$found\E\s+const\b\s*\*/) {
+ WARN("CONST_CONST",
+ "'const $found const *' should probably be 'const $found * const'\n" . $herecurr);
+ } elsif ($sline !~ /\bconst\s+\Q$found\E\s+const\s+\w+\s*\[/) {
+ WARN("CONST_CONST",
+ "'const $found const' should probably be 'const $found'\n" . $herecurr);
+ }
+ }
+
+# check for non-global char *foo[] = {"bar", ...} declarations.
+ if ($line =~ /^.\s+(?:static\s+|const\s+)?char\s+\*\s*\w+\s*\[\s*\]\s*=\s*\{/) {
+ WARN("STATIC_CONST_CHAR_ARRAY",
+ "char * array declaration might be better as static const\n" .
+ $herecurr);
+ }
+
+# check for sizeof(foo)/sizeof(foo[0]) that could be ARRAY_SIZE(foo)
+ if ($line =~ m@\bsizeof\s*\(\s*($Lval)\s*\)@) {
+ my $array = $1;
+ if ($line =~ m@\b(sizeof\s*\(\s*\Q$array\E\s*\)\s*/\s*sizeof\s*\(\s*\Q$array\E\s*\[\s*0\s*\]\s*\))@) {
+ my $array_div = $1;
+ if (WARN("ARRAY_SIZE",
+ "Prefer ARRAY_SIZE($array)\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\Q$array_div\E/ARRAY_SIZE($array)/;
+ }
+ }
+ }
+
# check for function declarations without arguments like "int foo()"
if ($line =~ /(\b$Type\s+$Ident)\s*\(\s*\)/) {
if (ERROR("FUNCTION_WITHOUT_ARGS",
"Bad function definition - $1() should probably be $1(void)\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~ s/(\b($Type)\s+($Ident))\s*\(\s*\)/$2 $3(void)/;
- }
- }
-
-# check for uses of DEFINE_PCI_DEVICE_TABLE
- if ($line =~ /\bDEFINE_PCI_DEVICE_TABLE\s*\(\s*(\w+)\s*\)\s*=/) {
- if (WARN("DEFINE_PCI_DEVICE_TABLE",
- "Prefer struct pci_device_id over deprecated DEFINE_PCI_DEVICE_TABLE\n" . $herecurr) &&
- $fix) {
- $fixed[$linenr - 1] =~ s/\b(?:static\s+|)DEFINE_PCI_DEVICE_TABLE\s*\(\s*(\w+)\s*\)\s*=\s*/static const struct pci_device_id $1\[\] = /;
+ $fixed[$fixlinenr] =~ s/(\b($Type)\s+($Ident))\s*\(\s*\)/$2 $3(void)/;
}
}
$line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ &&
$line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ &&
$line !~ /\b$typeTypedefs\b/ &&
- $line !~ /\b__bitwise(?:__|)\b/) {
+ $line !~ /\b__bitwise\b/) {
WARN("NEW_TYPEDEFS",
"do not add new typedefs\n" . $herecurr);
}
my $sub_from = $ident;
my $sub_to = $ident;
$sub_to =~ s/\Q$from\E/$to/;
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s@\Q$sub_from\E@$sub_to@;
}
}
my $sub_from = $match;
my $sub_to = $match;
$sub_to =~ s/\Q$from\E/$to/;
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s@\Q$sub_from\E@$sub_to@;
}
}
}
-# # no BUG() or BUG_ON()
-# if ($line =~ /\b(BUG|BUG_ON)\b/) {
-# print "Try to use WARN_ON & Recovery code rather than BUG() or BUG_ON()\n";
-# print "$herecurr";
-# $clean = 0;
-# }
+# avoid BUG() or BUG_ON()
+ if ($line =~ /\b(?:BUG|BUG_ON)\b/) {
+ my $msg_type = \&WARN;
+ $msg_type = \&CHK if ($file);
+ &{$msg_type}("AVOID_BUG",
+ "Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()\n" . $herecurr);
+ }
+# avoid LINUX_VERSION_CODE
if ($line =~ /\bLINUX_VERSION_CODE\b/) {
WARN("LINUX_VERSION_CODE",
"LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr);
# check for uses of printk_ratelimit
if ($line =~ /\bprintk_ratelimit\s*\(/) {
WARN("PRINTK_RATELIMITED",
-"Prefer printk_ratelimited or pr_<level>_ratelimited to printk_ratelimit\n" . $herecurr);
+ "Prefer printk_ratelimited or pr_<level>_ratelimited to printk_ratelimit\n" . $herecurr);
}
# printk should use KERN_* levels. Note that follow on printk's on the
my $level2 = $level;
$level2 = "dbg" if ($level eq "debug");
WARN("PREFER_PR_LEVEL",
- "Prefer netdev_$level2(netdev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr);
+ "Prefer [subsystem eg: netdev]_$level2([subsystem]dev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr);
}
if ($line =~ /\bpr_warning\s*\(/) {
if (WARN("PREFER_PR_LEVEL",
"Prefer pr_warn(... to pr_warning(...\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s/\bpr_warning\b/pr_warn/;
}
}
"Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr);
}
+# ENOSYS means "bad syscall nr" and nothing else. This will have a small
+# number of false positives, but assembly files are not checked, so at
+# least the arch entry code will not trigger this warning.
+ if ($line =~ /\bENOSYS\b/) {
+ WARN("ENOSYS",
+ "ENOSYS means 'invalid syscall nr' and nothing else\n" . $herecurr);
+ }
+
# function brace can't be on same line, except for #defines of do while,
# or if closed on same line
- if (($line=~/$Type\s*$Ident\(.*\).*\s\{/) and
+ if (($line=~/$Type\s*$Ident\(.*\).*\s*{/) and
!($line=~/\#\s*define.*do\s\{/) and !($line=~/}/)) {
- ERROR("OPEN_BRACE",
- "open brace '{' following function declarations go on the next line\n" . $herecurr);
+ if (ERROR("OPEN_BRACE",
+ "open brace '{' following function declarations go on the next line\n" . $herecurr) &&
+ $fix) {
+ fix_delete_line($fixlinenr, $rawline);
+ my $fixed_line = $rawline;
+ $fixed_line =~ /(^..*$Type\s*$Ident\(.*\)\s*){(.*)$/;
+ my $line1 = $1;
+ my $line2 = $2;
+ fix_insert_line($fixlinenr, ltrim($line1));
+ fix_insert_line($fixlinenr, "\+{");
+ if ($line2 !~ /^\s*$/) {
+ fix_insert_line($fixlinenr, "\+\t" . trim($line2));
+ }
+ }
}
# open braces for enum, union and struct go on the same line.
if ($line =~ /^.\s*{/ &&
$prevline =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?\s*$/) {
- ERROR("OPEN_BRACE",
- "open brace '{' following $1 go on the same line\n" . $hereprev);
+ if (ERROR("OPEN_BRACE",
+ "open brace '{' following $1 go on the same line\n" . $hereprev) &&
+ $fix && $prevline =~ /^\+/ && $line =~ /^\+/) {
+ fix_delete_line($fixlinenr - 1, $prevrawline);
+ fix_delete_line($fixlinenr, $rawline);
+ my $fixedline = rtrim($prevrawline) . " {";
+ fix_insert_line($fixlinenr, $fixedline);
+ $fixedline = $rawline;
+ $fixedline =~ s/^(.\s*)\{\s*/$1\t/;
+ if ($fixedline !~ /^\+\s*$/) {
+ fix_insert_line($fixlinenr, $fixedline);
+ }
+ }
}
# missing space after union, struct or enum definition
if (WARN("SPACING",
"missing space after $1 definition\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s/^(.\s*(?:typedef\s+)?(?:enum|union|struct)(?:\s+$Ident){1,2})([=\{])/$1 $2/;
}
}
# Function pointer declarations
# check spacing between type, funcptr, and args
# canonical declaration is "type (*funcptr)(args...)"
-#
-# the $Declare variable will capture all spaces after the type
-# so check it for trailing missing spaces or multiple spaces
- if ($line =~ /^.\s*($Declare)\((\s*)\*(\s*)$Ident(\s*)\)(\s*)\(/) {
+ if ($line =~ /^.\s*($Declare)\((\s*)\*(\s*)($Ident)(\s*)\)(\s*)\(/) {
my $declare = $1;
my $pre_pointer_space = $2;
my $post_pointer_space = $3;
my $post_funcname_space = $5;
my $pre_args_space = $6;
- if ($declare !~ /\s$/) {
+# the $Declare variable will capture all spaces after the type
+# so check it for a missing trailing missing space but pointer return types
+# don't need a space so don't warn for those.
+ my $post_declare_space = "";
+ if ($declare =~ /(\s+)$/) {
+ $post_declare_space = $1;
+ $declare = rtrim($declare);
+ }
+ if ($declare !~ /\*$/ && $post_declare_space =~ /^$/) {
WARN("SPACING",
"missing space after return type\n" . $herecurr);
+ $post_declare_space = " ";
}
# unnecessary space "type (*funcptr)(args...)"
- elsif ($declare =~ /\s{2,}$/) {
- WARN("SPACING",
- "Multiple spaces after return type\n" . $herecurr);
- }
+# This test is not currently implemented because these declarations are
+# equivalent to
+# int foo(int bar, ...)
+# and this is form shouldn't/doesn't generate a checkpatch warning.
+#
+# elsif ($declare =~ /\s{2,}$/) {
+# WARN("SPACING",
+# "Multiple spaces after return type\n" . $herecurr);
+# }
# unnecessary space "type ( *funcptr)(args...)"
if (defined $pre_pointer_space &&
}
if (show_type("SPACING") && $fix) {
- $fixed[$linenr - 1] =~
- s/^(.\s*$Declare)\(\s*\*\s*($Ident)\s*\)\s*\(/rtrim($1) . " " . "\(\*$2\)\("/ex;
+ $fixed[$fixlinenr] =~
+ s/^(.\s*)$Declare\s*\(\s*\*\s*$Ident\s*\)\s*\(/$1 . $declare . $post_declare_space . '(*' . $funcname . ')('/ex;
}
}
if (ERROR("BRACKET_SPACE",
"space prohibited before open square bracket '['\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s/^(\+.*?)\s+\[/$1\[/;
}
}
if (WARN("SPACING",
"space prohibited between function name and open parenthesis '('\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s/\b$name\s+\(/$name\(/;
}
}
# Ignore operators passed as parameters.
if ($op_type ne 'V' &&
- $ca =~ /\s$/ && $cc =~ /^\s*,/) {
+ $ca =~ /\s$/ && $cc =~ /^\s*[,\)]/) {
# # Ignore comments
# } elsif ($op =~ /^$;+$/) {
# // is a comment
} elsif ($op eq '//') {
+ # : when part of a bitfield
+ } elsif ($opv eq ':B') {
+ # skip the bitfield test for now
+
# No spaces for:
# ->
- # : when part of a bitfield
- } elsif ($op eq '->' || $opv eq ':B') {
+ } elsif ($op eq '->') {
if ($ctx =~ /Wx.|.xW/) {
if (ERROR("SPACING",
"spaces prohibited around that '$op' $at\n" . $hereptr)) {
}
}
- # , must have a space on the right.
+ # , must not have a space before and must have a space on the right.
} elsif ($op eq ',') {
+ my $rtrim_before = 0;
+ my $space_after = 0;
+ if ($ctx =~ /Wx./) {
+ if (ERROR("SPACING",
+ "space prohibited before that '$op' $at\n" . $hereptr)) {
+ $line_fixed = 1;
+ $rtrim_before = 1;
+ }
+ }
if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) {
if (ERROR("SPACING",
"space required after that '$op' $at\n" . $hereptr)) {
- $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " ";
$line_fixed = 1;
$last_after = $n;
+ $space_after = 1;
+ }
+ }
+ if ($rtrim_before || $space_after) {
+ if ($rtrim_before) {
+ $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);
+ } else {
+ $good = $fix_elements[$n] . trim($fix_elements[$n + 1]);
+ }
+ if ($space_after) {
+ $good .= " ";
}
}
$op eq '*' or $op eq '/' or
$op eq '%')
{
- if ($ctx =~ /Wx[^WCE]|[^WCE]xW/) {
+ if ($check) {
+ if (defined $fix_elements[$n + 2] && $ctx !~ /[EW]x[EW]/) {
+ if (CHK("SPACING",
+ "spaces preferred around that '$op' $at\n" . $hereptr)) {
+ $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " ";
+ $fix_elements[$n + 2] =~ s/^\s+//;
+ $line_fixed = 1;
+ }
+ } elsif (!defined $fix_elements[$n + 2] && $ctx !~ /Wx[OE]/) {
+ if (CHK("SPACING",
+ "space preferred before that '$op' $at\n" . $hereptr)) {
+ $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]);
+ $line_fixed = 1;
+ }
+ }
+ } elsif ($ctx =~ /Wx[^WCE]|[^WCE]xW/) {
if (ERROR("SPACING",
"need consistent spacing around '$op' $at\n" . $hereptr)) {
$good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " ";
$ok = 1;
}
+ # for asm volatile statements
+ # ignore a colon with another
+ # colon immediately before or after
+ if (($op eq ':') &&
+ ($ca =~ /:$/ || $cc =~ /^:/)) {
+ $ok = 1;
+ }
+
# messages are ERROR, but ?: are CHK
if ($ok == 0) {
my $msg_type = \&ERROR;
$fixed_line = $fixed_line . $fix_elements[$#elements];
}
- if ($fix && $line_fixed && $fixed_line ne $fixed[$linenr - 1]) {
- $fixed[$linenr - 1] = $fixed_line;
+ if ($fix && $line_fixed && $fixed_line ne $fixed[$fixlinenr]) {
+ $fixed[$fixlinenr] = $fixed_line;
}
if (WARN("SPACING",
"space prohibited before semicolon\n" . $herecurr) &&
$fix) {
- 1 while $fixed[$linenr - 1] =~
+ 1 while $fixed[$fixlinenr] =~
s/^(\+.*\S)\s+;/$1;/;
}
}
## }
#need space before brace following if, while, etc
- if (($line =~ /\(.*\)\{/ && $line !~ /\($Type\){/) ||
+ if (($line =~ /\(.*\)\{/ && $line !~ /\($Type\)\{/) ||
$line =~ /do\{/) {
if (ERROR("SPACING",
"space required before the open brace '{'\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~ s/^(\+.*(?:do|\))){/$1 {/;
+ $fixed[$fixlinenr] =~ s/^(\+.*(?:do|\)))\{/$1 {/;
}
}
if (ERROR("SPACING",
"space required after that close brace '}'\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s/}((?!(?:,|;|\)))\S)/} $1/;
}
}
if (ERROR("SPACING",
"space prohibited after that open square bracket '['\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s/\[\s+/\[/;
}
}
if (ERROR("SPACING",
"space prohibited before that close square bracket ']'\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s/\s+\]/\]/;
}
}
if (ERROR("SPACING",
"space prohibited after that open parenthesis '('\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s/\(\s+/\(/;
}
}
if (ERROR("SPACING",
"space prohibited before that close parenthesis ')'\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s/\s+\)/\)/;
}
}
+# check unnecessary parentheses around addressof/dereference single $Lvals
+# ie: &(foo->bar) should be &foo->bar and *(foo->bar) should be *foo->bar
+
+ while ($line =~ /(?:[^&]&\s*|\*)\(\s*($Ident\s*(?:$Member\s*)+)\s*\)/g) {
+ my $var = $1;
+ if (CHK("UNNECESSARY_PARENTHESES",
+ "Unnecessary parentheses around $var\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\(\s*\Q$var\E\s*\)/$var/;
+ }
+ }
+
+# check for unnecessary parentheses around function pointer uses
+# ie: (foo->bar)(); should be foo->bar();
+# but not "if (foo->bar) (" to avoid some false positives
+ if ($line =~ /(\bif\s*|)(\(\s*$Ident\s*(?:$Member\s*)+\))[ \t]*\(/ && $1 !~ /^if/) {
+ my $var = $2;
+ if (CHK("UNNECESSARY_PARENTHESES",
+ "Unnecessary parentheses around function pointer $var\n" . $herecurr) &&
+ $fix) {
+ my $var2 = deparenthesize($var);
+ $var2 =~ s/\s//g;
+ $fixed[$fixlinenr] =~ s/\Q$var\E/$var2/;
+ }
+ }
+
#goto labels aren't indented, allow a single space however
if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and
!($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) {
if (WARN("INDENTED_LABEL",
"labels should not be indented\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s/^(.)\s+/$1/;
}
}
-# Return is not a function.
+# return is not a function
if (defined($stat) && $stat =~ /^.\s*return(\s*)\(/s) {
my $spacing = $1;
if ($^V && $^V ge 5.10.0 &&
- $stat =~ /^.\s*return\s*$balanced_parens\s*;\s*$/) {
- ERROR("RETURN_PARENTHESES",
- "return is not a function, parentheses are not required\n" . $herecurr);
-
+ $stat =~ /^.\s*return\s*($balanced_parens)\s*;\s*$/) {
+ my $value = $1;
+ $value = deparenthesize($value);
+ if ($value =~ m/^\s*$FuncArg\s*(?:\?|$)/) {
+ ERROR("RETURN_PARENTHESES",
+ "return is not a function, parentheses are not required\n" . $herecurr);
+ }
} elsif ($spacing !~ /\s+/) {
ERROR("SPACING",
"space required before the open parenthesis '('\n" . $herecurr);
}
}
+# unnecessary return in a void function
+# at end-of-function, with the previous line a single leading tab, then return;
+# and the line before that not a goto label target like "out:"
+ if ($sline =~ /^[ \+]}\s*$/ &&
+ $prevline =~ /^\+\treturn\s*;\s*$/ &&
+ $linenr >= 3 &&
+ $lines[$linenr - 3] =~ /^[ +]/ &&
+ $lines[$linenr - 3] !~ /^[ +]\s*$Ident\s*:/) {
+ WARN("RETURN_VOID",
+ "void function return statements are not generally useful\n" . $hereprev);
+ }
+
# if statements using unnecessary parentheses - ie: if ((foo == bar))
if ($^V && $^V ge 5.10.0 &&
$line =~ /\bif\s*((?:\(\s*){2,})/) {
}
}
-# Return of what appears to be an errno should normally be -'ve
- if ($line =~ /^.\s*return\s*(E[A-Z]*)\s*;/) {
+# comparisons with a constant or upper case identifier on the left
+# avoid cases like "foo + BAR < baz"
+# only fix matches surrounded by parentheses to avoid incorrect
+# conversions like "FOO < baz() + 5" being "misfixed" to "baz() > FOO + 5"
+ if ($^V && $^V ge 5.10.0 &&
+ $line =~ /^\+(.*)\b($Constant|[A-Z_][A-Z0-9_]*)\s*($Compare)\s*($LvalOrFunc)/) {
+ my $lead = $1;
+ my $const = $2;
+ my $comp = $3;
+ my $to = $4;
+ my $newcomp = $comp;
+ if ($lead !~ /(?:$Operators|\.)\s*$/ &&
+ $to !~ /^(?:Constant|[A-Z_][A-Z0-9_]*)$/ &&
+ WARN("CONSTANT_COMPARISON",
+ "Comparisons should place the constant on the right side of the test\n" . $herecurr) &&
+ $fix) {
+ if ($comp eq "<") {
+ $newcomp = ">";
+ } elsif ($comp eq "<=") {
+ $newcomp = ">=";
+ } elsif ($comp eq ">") {
+ $newcomp = "<";
+ } elsif ($comp eq ">=") {
+ $newcomp = "<=";
+ }
+ $fixed[$fixlinenr] =~ s/\(\s*\Q$const\E\s*$Compare\s*\Q$to\E\s*\)/($to $newcomp $const)/;
+ }
+ }
+
+# Return of what appears to be an errno should normally be negative
+ if ($sline =~ /\breturn(?:\s*\(+\s*|\s+)(E[A-Z]+)(?:\s*\)+\s*|\s*)[;:,]/) {
my $name = $1;
if ($name ne 'EOF' && $name ne 'ERROR') {
WARN("USE_NEGATIVE_ERRNO",
- "return of an errno should typically be -ve (return -$1)\n" . $herecurr);
+ "return of an errno should typically be negative (ie: return -$1)\n" . $herecurr);
}
}
if (ERROR("SPACING",
"space required before the open parenthesis '('\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s/\b(if|while|for|switch)\(/$1 \(/;
}
}
# if should not continue a brace
if ($line =~ /}\s*if\b/) {
ERROR("TRAILING_STATEMENTS",
- "trailing statements should be on next line\n" .
+ "trailing statements should be on next line (or did you mean 'else if'?)\n" .
$herecurr);
}
# case and default should not have general statements after them
# Check for }<nl>else {, these must be at the same
# indent level to be relevant to each other.
- if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ and
- $previndent == $indent) {
- ERROR("ELSE_AFTER_BRACE",
- "else should follow close brace '}'\n" . $hereprev);
+ if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ &&
+ $previndent == $indent) {
+ if (ERROR("ELSE_AFTER_BRACE",
+ "else should follow close brace '}'\n" . $hereprev) &&
+ $fix && $prevline =~ /^\+/ && $line =~ /^\+/) {
+ fix_delete_line($fixlinenr - 1, $prevrawline);
+ fix_delete_line($fixlinenr, $rawline);
+ my $fixedline = $prevrawline;
+ $fixedline =~ s/}\s*$//;
+ if ($fixedline !~ /^\+\s*$/) {
+ fix_insert_line($fixlinenr, $fixedline);
+ }
+ $fixedline = $rawline;
+ $fixedline =~ s/^(.\s*)else/$1} else/;
+ fix_insert_line($fixlinenr, $fixedline);
+ }
}
- if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ and
- $previndent == $indent) {
+ if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ &&
+ $previndent == $indent) {
my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0);
# Find out what is on the end of the line after the
$s =~ s/\n.*//g;
if ($s =~ /^\s*;/) {
- ERROR("WHILE_AFTER_BRACE",
- "while should follow close brace '}'\n" . $hereprev);
+ if (ERROR("WHILE_AFTER_BRACE",
+ "while should follow close brace '}'\n" . $hereprev) &&
+ $fix && $prevline =~ /^\+/ && $line =~ /^\+/) {
+ fix_delete_line($fixlinenr - 1, $prevrawline);
+ fix_delete_line($fixlinenr, $rawline);
+ my $fixedline = $prevrawline;
+ my $trailing = $rawline;
+ $trailing =~ s/^\+//;
+ $trailing = trim($trailing);
+ $fixedline =~ s/}\s*$/} $trailing/;
+ fix_insert_line($fixlinenr, $fixedline);
+ }
}
}
"Avoid gcc v4.3+ binary constant extension: <$var>\n" . $herecurr) &&
$fix) {
my $hexval = sprintf("0x%x", oct($var));
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s/\b$var\b/$hexval/;
}
}
#Ignore Page<foo> variants
$var !~ /^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ &&
#Ignore SI style variants like nS, mV and dB (ie: max_uV, regulator_min_uA_show)
- $var !~ /^(?:[a-z_]*?)_?[a-z][A-Z](?:_[a-z_]+)?$/) {
+ $var !~ /^(?:[a-z_]*?)_?[a-z][A-Z](?:_[a-z_]+)?$/ &&
+#Ignore some three character SI units explicitly, like MiB and KHz
+ $var !~ /^(?:[a-z_]*?)_?(?:[KMGT]iB|[KMGT]?Hz)(?:_[a-z_]+)?$/) {
while ($var =~ m{($Ident)}g) {
my $word = $1;
next if ($word !~ /[A-Z][a-z]|[a-z][A-Z]/);
if (WARN("WHITESPACE_AFTER_LINE_CONTINUATION",
"Whitespace after \\ makes next lines useless\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~ s/\s+$//;
+ $fixed[$fixlinenr] =~ s/\s+$//;
}
}
-#warn if <asm/foo.h> is #included and <linux/foo.h> is available (uses RAW line)
+# warn if <asm/foo.h> is #included and <linux/foo.h> is available and includes
+# itself <asm/foo.h> (uses RAW line)
if ($tree && $rawline =~ m{^.\s*\#\s*include\s*\<asm\/(.*)\.h\>}) {
my $file = "$1.h";
my $checkfile = "include/linux/$file";
$realfile ne $checkfile &&
$1 !~ /$allowed_asm_includes/)
{
- if ($realfile =~ m{^arch/}) {
- CHK("ARCH_INCLUDE_LINUX",
- "Consider using #include <linux/$file> instead of <asm/$file>\n" . $herecurr);
- } else {
- WARN("INCLUDE_LINUX",
- "Use #include <linux/$file> instead of <asm/$file>\n" . $herecurr);
+ my $asminclude = `grep -Ec "#include\\s+<asm/$file>" $root/$checkfile`;
+ if ($asminclude > 0) {
+ if ($realfile =~ m{^arch/}) {
+ CHK("ARCH_INCLUDE_LINUX",
+ "Consider using #include <linux/$file> instead of <asm/$file>\n" . $herecurr);
+ } else {
+ WARN("INCLUDE_LINUX",
+ "Use #include <linux/$file> instead of <asm/$file>\n" . $herecurr);
+ }
}
}
}
my $cnt = $realcnt;
my ($off, $dstat, $dcond, $rest);
my $ctx = '';
+ my $has_flow_statement = 0;
+ my $has_arg_concat = 0;
($dstat, $dcond, $ln, $cnt, $off) =
ctx_statement_block($linenr, $realcnt, 0);
$ctx = $dstat;
#print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n";
#print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n";
- $dstat =~ s/^.\s*\#\s*define\s+$Ident(?:\([^\)]*\))?\s*//;
+ $has_flow_statement = 1 if ($ctx =~ /\b(goto|return)\b/);
+ $has_arg_concat = 1 if ($ctx =~ /\#\#/ && $ctx !~ /\#\#\s*(?:__VA_ARGS__|args)\b/);
+
+ $dstat =~ s/^.\s*\#\s*define\s+$Ident(\([^\)]*\))?\s*//;
+ my $define_args = $1;
+ my $define_stmt = $dstat;
+ my @def_args = ();
+
+ if (defined $define_args && $define_args ne "") {
+ $define_args = substr($define_args, 1, length($define_args) - 2);
+ $define_args =~ s/\s*//g;
+ @def_args = split(",", $define_args);
+ }
+
$dstat =~ s/$;//g;
$dstat =~ s/\\\n.//g;
$dstat =~ s/^\s*//s;
# Flatten any parentheses and braces
while ($dstat =~ s/\([^\(\)]*\)/1/ ||
$dstat =~ s/\{[^\{\}]*\}/1/ ||
- $dstat =~ s/\[[^\[\]]*\]/1/)
+ $dstat =~ s/.\[[^\[\]]*\]/1/)
{
}
# Flatten any obvious string concatentation.
- while ($dstat =~ s/("X*")\s*$Ident/$1/ ||
- $dstat =~ s/$Ident\s*("X*")/$1/)
+ while ($dstat =~ s/($String)\s*$Ident/$1/ ||
+ $dstat =~ s/$Ident\s*($String)/$1/)
{
}
+ # Make asm volatile uses seem like a generic function
+ $dstat =~ s/\b_*asm_*\s+_*volatile_*\b/asm_volatile/g;
+
my $exceptions = qr{
$Declare|
module_param_named|
union|
struct|
\.$Ident\s*=\s*|
- ^\"|\"$
+ ^\"|\"$|
+ ^\[
}x;
#print "REST<$rest> dstat<$dstat> ctx<$ctx>\n";
+
+ $ctx =~ s/\n*$//;
+ my $herectx = $here . "\n";
+ my $stmt_cnt = statement_rawlines($ctx);
+
+ for (my $n = 0; $n < $stmt_cnt; $n++) {
+ $herectx .= raw_line($linenr, $n) . "\n";
+ }
+
if ($dstat ne '' &&
$dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(),
$dstat !~ /^(?:$Ident|-?$Constant);$/ && # foo();
$dstat !~ /^[!~-]?(?:$Lval|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo // foo->bar // foo.bar->baz
- $dstat !~ /^'X'$/ && # character constants
+ $dstat !~ /^'X'$/ && $dstat !~ /^'XX'$/ && # character constants
$dstat !~ /$exceptions/ &&
$dstat !~ /^\.$Ident\s*=/ && # .foo =
$dstat !~ /^(?:\#\s*$Ident|\#\s*$Constant)\s*$/ && # stringification #foo
$dstat !~ /^\(\{/ && # ({...
$ctx !~ /^.\s*#\s*define\s+TRACE_(?:SYSTEM|INCLUDE_FILE|INCLUDE_PATH)\b/)
{
- $ctx =~ s/\n*$//;
+ if ($dstat =~ /^\s*if\b/) {
+ ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE",
+ "Macros starting with if should be enclosed by a do - while loop to avoid possible if/else logic defects\n" . "$herectx");
+ } elsif ($dstat =~ /;/) {
+ ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE",
+ "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx");
+ } else {
+ ERROR("COMPLEX_MACRO",
+ "Macros with complex values should be enclosed in parentheses\n" . "$herectx");
+ }
+
+ }
+
+ # Make $define_stmt single line, comment-free, etc
+ my @stmt_array = split('\n', $define_stmt);
+ my $first = 1;
+ $define_stmt = "";
+ foreach my $l (@stmt_array) {
+ $l =~ s/\\$//;
+ if ($first) {
+ $define_stmt = $l;
+ $first = 0;
+ } elsif ($l =~ /^[\+ ]/) {
+ $define_stmt .= substr($l, 1);
+ }
+ }
+ $define_stmt =~ s/$;//g;
+ $define_stmt =~ s/\s+/ /g;
+ $define_stmt = trim($define_stmt);
+
+# check if any macro arguments are reused (ignore '...' and 'type')
+ foreach my $arg (@def_args) {
+ next if ($arg =~ /\.\.\./);
+ next if ($arg =~ /^type$/i);
+ my $tmp_stmt = $define_stmt;
+ $tmp_stmt =~ s/\b(typeof|__typeof__|__builtin\w+|typecheck\s*\(\s*$Type\s*,|\#+)\s*\(*\s*$arg\s*\)*\b//g;
+ $tmp_stmt =~ s/\#+\s*$arg\b//g;
+ $tmp_stmt =~ s/\b$arg\s*\#\#//g;
+ my $use_cnt = $tmp_stmt =~ s/\b$arg\b//g;
+ if ($use_cnt > 1) {
+ CHK("MACRO_ARG_REUSE",
+ "Macro argument reuse '$arg' - possible side-effects?\n" . "$herectx");
+ }
+# check if any macro arguments may have other precedence issues
+ if ($tmp_stmt =~ m/($Operators)?\s*\b$arg\b\s*($Operators)?/m &&
+ ((defined($1) && $1 ne ',') ||
+ (defined($2) && $2 ne ','))) {
+ CHK("MACRO_ARG_PRECEDENCE",
+ "Macro argument '$arg' may be better as '($arg)' to avoid precedence issues\n" . "$herectx");
+ }
+ }
+
+# check for macros with flow control, but without ## concatenation
+# ## concatenation is commonly a macro that defines a function so ignore those
+ if ($has_flow_statement && !$has_arg_concat) {
my $herectx = $here . "\n";
my $cnt = statement_rawlines($ctx);
for (my $n = 0; $n < $cnt; $n++) {
$herectx .= raw_line($linenr, $n) . "\n";
}
-
- if ($dstat =~ /;/) {
- ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE",
- "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx");
- } else {
- ERROR("COMPLEX_MACRO",
- "Macros with complex values should be enclosed in parenthesis\n" . "$herectx");
- }
+ WARN("MACRO_WITH_FLOW_CONTROL",
+ "Macros with flow control statements should be avoided\n" . "$herectx");
}
# check for line continuations outside of #defines, preprocessor #, and asm
$ctx = $dstat;
$dstat =~ s/\\\n.//g;
+ $dstat =~ s/$;/ /g;
if ($dstat =~ /^\+\s*#\s*define\s+$Ident\s*${balanced_parens}\s*do\s*{(.*)\s*}\s*while\s*\(\s*0\s*\)\s*([;\s]*)\s*$/) {
my $stmts = $2;
WARN("DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON",
"do {} while (0) macros should not be semicolon terminated\n" . "$herectx");
}
+ } elsif ($dstat =~ /^\+\s*#\s*define\s+$Ident.*;\s*$/) {
+ $ctx =~ s/\n*$//;
+ my $cnt = statement_rawlines($ctx);
+ my $herectx = $here . "\n";
+
+ for (my $n = 0; $n < $cnt; $n++) {
+ $herectx .= raw_line($linenr, $n) . "\n";
+ }
+
+ WARN("TRAILING_SEMICOLON",
+ "macros should not use a trailing semicolon\n" . "$herectx");
}
}
}
}
+# check for single line unbalanced braces
+ if ($sline =~ /^.\s*\}\s*else\s*$/ ||
+ $sline =~ /^.\s*else\s*\{\s*$/) {
+ CHK("BRACES", "Unbalanced braces around else statement\n" . $herecurr);
+ }
+
# check for unnecessary blank lines around braces
if (($line =~ /^.\s*}\s*$/ && $prevrawline =~ /^.\s*$/)) {
- CHK("BRACES",
- "Blank lines aren't necessary before a close brace '}'\n" . $hereprev);
+ if (CHK("BRACES",
+ "Blank lines aren't necessary before a close brace '}'\n" . $hereprev) &&
+ $fix && $prevrawline =~ /^\+/) {
+ fix_delete_line($fixlinenr - 1, $prevrawline);
+ }
}
if (($rawline =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) {
- CHK("BRACES",
- "Blank lines aren't necessary after an open brace '{'\n" . $hereprev);
+ if (CHK("BRACES",
+ "Blank lines aren't necessary after an open brace '{'\n" . $hereprev) &&
+ $fix) {
+ fix_delete_line($fixlinenr, $rawline);
+ }
}
# no volatiles please
my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b};
if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) {
WARN("VOLATILE",
- "Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt\n" . $herecurr);
+ "Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst\n" . $herecurr);
+ }
+
+# Check for user-visible strings broken across lines, which breaks the ability
+# to grep for the string. Make exceptions when the previous string ends in a
+# newline (multiple lines in one string constant) or '\t', '\r', ';', or '{'
+# (common in inline assembly) or is a octal \123 or hexadecimal \xaf value
+ if ($line =~ /^\+\s*$String/ &&
+ $prevline =~ /"\s*$/ &&
+ $prevrawline !~ /(?:\\(?:[ntr]|[0-7]{1,3}|x[0-9a-fA-F]{1,2})|;\s*|\{\s*)"\s*$/) {
+ if (WARN("SPLIT_STRING",
+ "quoted string split across lines\n" . $hereprev) &&
+ $fix &&
+ $prevrawline =~ /^\+.*"\s*$/ &&
+ $last_coalesced_string_linenr != $linenr - 1) {
+ my $extracted_string = get_quoted_string($line, $rawline);
+ my $comma_close = "";
+ if ($rawline =~ /\Q$extracted_string\E(\s*\)\s*;\s*$|\s*,\s*)/) {
+ $comma_close = $1;
+ }
+
+ fix_delete_line($fixlinenr - 1, $prevrawline);
+ fix_delete_line($fixlinenr, $rawline);
+ my $fixedline = $prevrawline;
+ $fixedline =~ s/"\s*$//;
+ $fixedline .= substr($extracted_string, 1) . trim($comma_close);
+ fix_insert_line($fixlinenr - 1, $fixedline);
+ $fixedline = $rawline;
+ $fixedline =~ s/\Q$extracted_string\E\Q$comma_close\E//;
+ if ($fixedline !~ /\+\s*$/) {
+ fix_insert_line($fixlinenr, $fixedline);
+ }
+ $last_coalesced_string_linenr = $linenr;
+ }
+ }
+
+# check for missing a space in a string concatenation
+ if ($prevrawline =~ /[^\\]\w"$/ && $rawline =~ /^\+[\t ]+"\w/) {
+ WARN('MISSING_SPACE',
+ "break quoted strings at a space character\n" . $hereprev);
+ }
+
+# check for an embedded function name in a string when the function is known
+# This does not work very well for -f --file checking as it depends on patch
+# context providing the function name or a single line form for in-file
+# function declarations
+ if ($line =~ /^\+.*$String/ &&
+ defined($context_function) &&
+ get_quoted_string($line, $rawline) =~ /\b$context_function\b/ &&
+ length(get_quoted_string($line, $rawline)) != (length($context_function) + 2)) {
+ WARN("EMBEDDED_FUNCTION_NAME",
+ "Prefer using '\"%s...\", __func__' to using '$context_function', this function's name, in a string\n" . $herecurr);
+ }
+
+# check for spaces before a quoted newline
+ if ($rawline =~ /^.*\".*\s\\n/) {
+ if (WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE",
+ "unnecessary whitespace before a quoted newline\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/^(\+.*\".*)\s+\\n/$1\\n/;
+ }
+
+ }
+
+# concatenated string without spaces between elements
+ if ($line =~ /$String[A-Z_]/ || $line =~ /[A-Za-z0-9_]$String/) {
+ CHK("CONCATENATED_STRING",
+ "Concatenated strings should use spaces between elements\n" . $herecurr);
+ }
+
+# uncoalesced string fragments
+ if ($line =~ /$String\s*"/) {
+ WARN("STRING_FRAGMENTS",
+ "Consecutive strings are generally better as a single string\n" . $herecurr);
+ }
+
+# check for non-standard and hex prefixed decimal printf formats
+ my $show_L = 1; #don't show the same defect twice
+ my $show_Z = 1;
+ while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) {
+ my $string = substr($rawline, $-[1], $+[1] - $-[1]);
+ $string =~ s/%%/__/g;
+ # check for %L
+ if ($show_L && $string =~ /%[\*\d\.\$]*L([diouxX])/) {
+ WARN("PRINTF_L",
+ "\%L$1 is non-standard C, use %ll$1\n" . $herecurr);
+ $show_L = 0;
+ }
+ # check for %Z
+ if ($show_Z && $string =~ /%[\*\d\.\$]*Z([diouxX])/) {
+ WARN("PRINTF_Z",
+ "%Z$1 is non-standard C, use %z$1\n" . $herecurr);
+ $show_Z = 0;
+ }
+ # check for 0x<decimal>
+ if ($string =~ /0x%[\*\d\.\$\Llzth]*[diou]/) {
+ ERROR("PRINTF_0XDECIMAL",
+ "Prefixing 0x with decimal output is defective\n" . $herecurr);
+ }
+ }
+
+# check for line continuations in quoted strings with odd counts of "
+ if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) {
+ WARN("LINE_CONTINUATIONS",
+ "Avoid line continuations in quoted strings\n" . $herecurr);
}
# warn about #if 0
# check for needless "if (<foo>) fn(<foo>)" uses
if ($prevline =~ /\bif\s*\(\s*($Lval)\s*\)/) {
- my $expr = '\s*\(\s*' . quotemeta($1) . '\s*\)\s*;';
- if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?)$expr/) {
- WARN('NEEDLESS_IF',
- "$1(NULL) is safe this check is probably not required\n" . $hereprev);
+ my $tested = quotemeta($1);
+ my $expr = '\s*\(\s*' . $tested . '\s*\)\s*;';
+ if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?|(?:kmem_cache|mempool|dma_pool)_destroy)$expr/) {
+ my $func = $1;
+ if (WARN('NEEDLESS_IF',
+ "$func(NULL) is safe and this check is probably not required\n" . $hereprev) &&
+ $fix) {
+ my $do_fix = 1;
+ my $leading_tabs = "";
+ my $new_leading_tabs = "";
+ if ($lines[$linenr - 2] =~ /^\+(\t*)if\s*\(\s*$tested\s*\)\s*$/) {
+ $leading_tabs = $1;
+ } else {
+ $do_fix = 0;
+ }
+ if ($lines[$linenr - 1] =~ /^\+(\t+)$func\s*\(\s*$tested\s*\)\s*;\s*$/) {
+ $new_leading_tabs = $1;
+ if (length($leading_tabs) + 1 ne length($new_leading_tabs)) {
+ $do_fix = 0;
+ }
+ } else {
+ $do_fix = 0;
+ }
+ if ($do_fix) {
+ fix_delete_line($fixlinenr - 1, $prevrawline);
+ $fixed[$fixlinenr] =~ s/^\+$new_leading_tabs/\+$leading_tabs/;
+ }
+ }
+ }
+ }
+
+# check for unnecessary "Out of Memory" messages
+ if ($line =~ /^\+.*\b$logFunctions\s*\(/ &&
+ $prevline =~ /^[ \+]\s*if\s*\(\s*(\!\s*|NULL\s*==\s*)?($Lval)(\s*==\s*NULL\s*)?\s*\)/ &&
+ (defined $1 || defined $3) &&
+ $linenr > 3) {
+ my $testval = $2;
+ my $testline = $lines[$linenr - 3];
+
+ my ($s, $c) = ctx_statement_block($linenr - 3, $realcnt, 0);
+# print("line: <$line>\nprevline: <$prevline>\ns: <$s>\nc: <$c>\n\n\n");
+
+ if ($s =~ /(?:^|\n)[ \+]\s*(?:$Type\s*)?\Q$testval\E\s*=\s*(?:\([^\)]*\)\s*)?\s*(?:devm_)?(?:[kv][czm]alloc(?:_node|_array)?\b|kstrdup|kmemdup|(?:dev_)?alloc_skb)/) {
+ WARN("OOM_MESSAGE",
+ "Possible unnecessary 'out of memory' message\n" . $hereprev);
+ }
+ }
+
+# check for logging functions with KERN_<LEVEL>
+ if ($line !~ /printk(?:_ratelimited|_once)?\s*\(/ &&
+ $line =~ /\b$logFunctions\s*\(.*\b(KERN_[A-Z]+)\b/) {
+ my $level = $1;
+ if (WARN("UNNECESSARY_KERN_LEVEL",
+ "Possible unnecessary $level\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\s*$level\s*//;
+ }
+ }
+
+# check for logging continuations
+ if ($line =~ /\bprintk\s*\(\s*KERN_CONT\b|\bpr_cont\s*\(/) {
+ WARN("LOGGING_CONTINUATION",
+ "Avoid logging continuation uses where feasible\n" . $herecurr);
+ }
+
+# check for mask then right shift without a parentheses
+ if ($^V && $^V ge 5.10.0 &&
+ $line =~ /$LvalOrFunc\s*\&\s*($LvalOrFunc)\s*>>/ &&
+ $4 !~ /^\&/) { # $LvalOrFunc may be &foo, ignore if so
+ WARN("MASK_THEN_SHIFT",
+ "Possible precedence defect with mask then right shift - may need parentheses\n" . $herecurr);
+ }
+
+# check for pointer comparisons to NULL
+ if ($^V && $^V ge 5.10.0) {
+ while ($line =~ /\b$LvalOrFunc\s*(==|\!=)\s*NULL\b/g) {
+ my $val = $1;
+ my $equal = "!";
+ $equal = "" if ($4 eq "!=");
+ if (CHK("COMPARISON_TO_NULL",
+ "Comparison to NULL could be written \"${equal}${val}\"\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\b\Q$val\E\s*(?:==|\!=)\s*NULL\b/$equal$val/;
+ }
}
}
WARN("MISPLACED_INIT",
"$attr should be placed after $var\n" . $herecurr))) &&
$fix) {
- $fixed[$linenr - 1] =~ s/(\bstatic\s+(?:const\s+)?)(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*([=;])\s*/"$1" . trim(string_find_replace($2, "\\s*$attr\\s*", " ")) . " " . trim(string_find_replace($3, "\\s*$attr\\s*", "")) . " $attr" . ("$4" eq ";" ? ";" : " = ")/e;
+ $fixed[$fixlinenr] =~ s/(\bstatic\s+(?:const\s+)?)(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*([=;])\s*/"$1" . trim(string_find_replace($2, "\\s*$attr\\s*", " ")) . " " . trim(string_find_replace($3, "\\s*$attr\\s*", "")) . " $attr" . ("$4" eq ";" ? ";" : " = ")/e;
}
}
}
if (ERROR("INIT_ATTRIBUTE",
"Use of const init definition must use ${attr_prefix}initconst\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s/$InitAttributeData/${attr_prefix}initconst/;
}
}
if (ERROR("INIT_ATTRIBUTE",
"Use of $attr requires a separate use of const\n" . $herecurr) &&
$fix) {
- my $lead = $fixed[$linenr - 1] =~
+ my $lead = $fixed[$fixlinenr] =~
/(^\+\s*(?:static\s+))/;
$lead = rtrim($1);
$lead = "$lead " if ($lead !~ /^\+$/);
$lead = "${lead}const ";
- $fixed[$linenr - 1] =~ s/(^\+\s*(?:static\s+))/$lead/;
+ $fixed[$fixlinenr] =~ s/(^\+\s*(?:static\s+))/$lead/;
+ }
+ }
+
+# check for __read_mostly with const non-pointer (should just be const)
+ if ($line =~ /\b__read_mostly\b/ &&
+ $line =~ /($Type)\s*$Ident/ && $1 !~ /\*\s*$/ && $1 =~ /\bconst\b/) {
+ if (ERROR("CONST_READ_MOSTLY",
+ "Invalid use of __read_mostly with const type\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\s+__read_mostly\b//;
+ }
+ }
+
+# don't use __constant_<foo> functions outside of include/uapi/
+ if ($realfile !~ m@^include/uapi/@ &&
+ $line =~ /(__constant_(?:htons|ntohs|[bl]e(?:16|32|64)_to_cpu|cpu_to_[bl]e(?:16|32|64)))\s*\(/) {
+ my $constant_func = $1;
+ my $func = $constant_func;
+ $func =~ s/^__constant_//;
+ if (WARN("CONSTANT_CONVERSION",
+ "$constant_func should be $func\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\b$constant_func\b/$func/g;
}
}
# prefer usleep_range over udelay
if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) {
+ my $delay = $1;
# ignore udelay's < 10, however
- if (! ($1 < 10) ) {
+ if (! ($delay < 10) ) {
CHK("USLEEP_RANGE",
- "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $line);
+ "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $herecurr);
+ }
+ if ($delay > 2000) {
+ WARN("LONG_UDELAY",
+ "long udelay - prefer mdelay; see arch/arm/include/asm/delay.h\n" . $herecurr);
}
}
if ($line =~ /\bmsleep\s*\((\d+)\);/) {
if ($1 < 20) {
WARN("MSLEEP",
- "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $line);
+ "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $herecurr);
}
}
if (ERROR("SPACING",
"exactly one space required after that #$1\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~
+ $fixed[$fixlinenr] =~
s/^(.\s*\#\s*(ifdef|ifndef|elif))\s{2,}/$1 /;
}
}
}
# check for memory barriers without a comment.
- if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) {
+
+ my $barriers = qr{
+ mb|
+ rmb|
+ wmb|
+ read_barrier_depends
+ }x;
+ my $barrier_stems = qr{
+ mb__before_atomic|
+ mb__after_atomic|
+ store_release|
+ load_acquire|
+ store_mb|
+ (?:$barriers)
+ }x;
+ my $all_barriers = qr{
+ (?:$barriers)|
+ smp_(?:$barrier_stems)|
+ virt_(?:$barrier_stems)
+ }x;
+
+ if ($line =~ /\b(?:$all_barriers)\s*\(/) {
if (!ctx_has_comment($first_line, $linenr)) {
WARN("MEMORY_BARRIER",
"memory barrier without comment\n" . $herecurr);
}
}
+
+ my $underscore_smp_barriers = qr{__smp_(?:$barrier_stems)}x;
+
+ if ($realfile !~ m@^include/asm-generic/@ &&
+ $realfile !~ m@/barrier\.h$@ &&
+ $line =~ m/\b(?:$underscore_smp_barriers)\s*\(/ &&
+ $line !~ m/^.\s*\#\s*define\s+(?:$underscore_smp_barriers)\s*\(/) {
+ WARN("MEMORY_BARRIER",
+ "__smp memory barriers shouldn't be used outside barrier.h and asm-generic\n" . $herecurr);
+ }
+
+# check for waitqueue_active without a comment.
+ if ($line =~ /\bwaitqueue_active\s*\(/) {
+ if (!ctx_has_comment($first_line, $linenr)) {
+ WARN("WAITQUEUE_ACTIVE",
+ "waitqueue_active without comment\n" . $herecurr);
+ }
+ }
+
# check of hardware specific defines
if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) {
CHK("ARCH_DEFINES",
"architecture specific defines should be avoided\n" . $herecurr);
}
+# check that the storage class is not after a type
+ if ($line =~ /\b($Type)\s+($Storage)\b/) {
+ WARN("STORAGE_CLASS",
+ "storage class '$2' should be located before type '$1'\n" . $herecurr);
+ }
# Check that the storage class is at the beginning of a declaration
- if ($line =~ /\b$Storage\b/ && $line !~ /^.\s*$Storage\b/) {
+ if ($line =~ /\b$Storage\b/ &&
+ $line !~ /^.\s*$Storage/ &&
+ $line =~ /^.\s*(.+?)\$Storage\s/ &&
+ $1 !~ /[\,\)]\s*$/) {
WARN("STORAGE_CLASS",
- "storage class should be at the beginning of the declaration\n" . $herecurr)
+ "storage class should be at the beginning of the declaration\n" . $herecurr);
}
# check the location of the inline attribute, that it is between
if (WARN("INLINE",
"plain inline is preferred over $1\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~ s/\b(__inline__|__inline)\b/inline/;
+ $fixed[$fixlinenr] =~ s/\b(__inline__|__inline)\b/inline/;
}
}
WARN("PREFER_PACKED",
"__packed is preferred over __attribute__((packed))\n" . $herecurr);
}
+
# Check for new packed members, warn to use care
- if ($line =~ /\b(__attribute__\s*\(\s*\(.*\bpacked|__packed)\b/) {
+ if ($realfile !~ m@\binclude/uapi/@ &&
+ $line =~ /\b(__attribute__\s*\(\s*\(.*\bpacked|__packed)\b/) {
WARN("NEW_PACKED",
"Adding new packed members is to be done with care\n" . $herecurr);
}
if (WARN("PREFER_PRINTF",
"__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf\s*,\s*(.*)\)\s*\)\s*\)/"__printf(" . trim($1) . ")"/ex;
+ $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf\s*,\s*(.*)\)\s*\)\s*\)/"__printf(" . trim($1) . ")"/ex;
}
}
if (WARN("PREFER_SCANF",
"__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\s*,\s*(.*)\)\s*\)\s*\)/"__scanf(" . trim($1) . ")"/ex;
+ $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\s*,\s*(.*)\)\s*\)\s*\)/"__scanf(" . trim($1) . ")"/ex;
+ }
+ }
+
+# Check for __attribute__ weak, or __weak declarations (may have link issues)
+ if ($^V && $^V ge 5.10.0 &&
+ $line =~ /(?:$Declare|$DeclareMisordered)\s*$Ident\s*$balanced_parens\s*(?:$Attribute)?\s*;/ &&
+ ($line =~ /\b__attribute__\s*\(\s*\(.*\bweak\b/ ||
+ $line =~ /\b__weak\b/)) {
+ ERROR("WEAK_DECLARATION",
+ "Using weak declarations can have unintended link defects\n" . $herecurr);
+ }
+
+# check for c99 types like uint8_t used outside of uapi/ and tools/
+ if ($realfile !~ m@\binclude/uapi/@ &&
+ $realfile !~ m@\btools/@ &&
+ $line =~ /\b($Declare)\s*$Ident\s*[=;,\[]/) {
+ my $type = $1;
+ if ($type =~ /\b($typeC99Typedefs)\b/) {
+ $type = $1;
+ my $kernel_type = 'u';
+ $kernel_type = 's' if ($type =~ /^_*[si]/);
+ $type =~ /(\d+)/;
+ $kernel_type .= $1;
+ if (CHK("PREFER_KERNEL_TYPES",
+ "Prefer kernel type '$kernel_type' over '$type'\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\b$type\b/$kernel_type/;
+ }
+ }
+ }
+
+# check for cast of C90 native int or longer types constants
+ if ($line =~ /(\(\s*$C90_int_types\s*\)\s*)($Constant)\b/) {
+ my $cast = $1;
+ my $const = $2;
+ if (WARN("TYPECAST_INT_CONSTANT",
+ "Unnecessary typecast of c90 int constant\n" . $herecurr) &&
+ $fix) {
+ my $suffix = "";
+ my $newconst = $const;
+ $newconst =~ s/${Int_type}$//;
+ $suffix .= 'U' if ($cast =~ /\bunsigned\b/);
+ if ($cast =~ /\blong\s+long\b/) {
+ $suffix .= 'LL';
+ } elsif ($cast =~ /\blong\b/) {
+ $suffix .= 'L';
+ }
+ $fixed[$fixlinenr] =~ s/\Q$cast\E$const\b/$newconst$suffix/;
}
}
if (WARN("SIZEOF_PARENTHESIS",
"sizeof $1 should be sizeof($1)\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~ s/\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/"sizeof(" . trim($1) . ")"/ex;
+ $fixed[$fixlinenr] =~ s/\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/"sizeof(" . trim($1) . ")"/ex;
}
}
-# check for line continuations in quoted strings with odd counts of "
- if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) {
- WARN("LINE_CONTINUATIONS",
- "Avoid line continuations in quoted strings\n" . $herecurr);
- }
-
# check for struct spinlock declarations
if ($line =~ /^.\s*\bstruct\s+spinlock\s+\w+\s*;/) {
WARN("USE_SPINLOCK_T",
# check for seq_printf uses that could be seq_puts
if ($sline =~ /\bseq_printf\s*\(.*"\s*\)\s*;\s*$/) {
my $fmt = get_quoted_string($line, $rawline);
- if ($fmt ne "" && $fmt !~ /[^\\]\%/) {
+ $fmt =~ s/%%//g;
+ if ($fmt !~ /%/) {
if (WARN("PREFER_SEQ_PUTS",
"Prefer seq_puts to seq_printf\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~ s/\bseq_printf\b/seq_puts/;
+ $fixed[$fixlinenr] =~ s/\bseq_printf\b/seq_puts/;
+ }
+ }
+ }
+
+ # check for vsprintf extension %p<foo> misuses
+ if ($^V && $^V ge 5.10.0 &&
+ defined $stat &&
+ $stat =~ /^\+(?![^\{]*\{\s*).*\b(\w+)\s*\(.*$String\s*,/s &&
+ $1 !~ /^_*volatile_*$/) {
+ my $bad_extension = "";
+ my $lc = $stat =~ tr@\n@@;
+ $lc = $lc + $linenr;
+ for (my $count = $linenr; $count <= $lc; $count++) {
+ my $fmt = get_quoted_string($lines[$count - 1], raw_line($count, 0));
+ $fmt =~ s/%%//g;
+ if ($fmt =~ /(\%[\*\d\.]*p(?![\WFfSsBKRraEhMmIiUDdgVCbGNO]).)/) {
+ $bad_extension = $1;
+ last;
}
}
+ if ($bad_extension ne "") {
+ my $stat_real = raw_line($linenr, 0);
+ for (my $count = $linenr + 1; $count <= $lc; $count++) {
+ $stat_real = $stat_real . "\n" . raw_line($count, 0);
+ }
+ WARN("VSPRINTF_POINTER_EXTENSION",
+ "Invalid vsprintf pointer extension '$bad_extension'\n" . "$here\n$stat_real\n");
+ }
}
# Check for misused memsets
if ($^V && $^V ge 5.10.0 &&
defined $stat &&
- $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/s) {
+ $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/) {
my $ms_addr = $2;
my $ms_val = $7;
}
# Check for memcpy(foo, bar, ETH_ALEN) that could be ether_addr_copy(foo, bar)
- if ($^V && $^V ge 5.10.0 &&
- $line =~ /^\+(?:.*?)\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/s) {
- if (WARN("PREFER_ETHER_ADDR_COPY",
- "Prefer ether_addr_copy() over memcpy() if the Ethernet addresses are __aligned(2)\n" . $herecurr) &&
- $fix) {
- $fixed[$linenr - 1] =~ s/\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/ether_addr_copy($2, $7)/;
- }
- }
+# if ($^V && $^V ge 5.10.0 &&
+# defined $stat &&
+# $stat =~ /^\+(?:.*?)\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/) {
+# if (WARN("PREFER_ETHER_ADDR_COPY",
+# "Prefer ether_addr_copy() over memcpy() if the Ethernet addresses are __aligned(2)\n" . "$here\n$stat\n") &&
+# $fix) {
+# $fixed[$fixlinenr] =~ s/\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/ether_addr_copy($2, $7)/;
+# }
+# }
+
+# Check for memcmp(foo, bar, ETH_ALEN) that could be ether_addr_equal*(foo, bar)
+# if ($^V && $^V ge 5.10.0 &&
+# defined $stat &&
+# $stat =~ /^\+(?:.*?)\bmemcmp\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/) {
+# WARN("PREFER_ETHER_ADDR_EQUAL",
+# "Prefer ether_addr_equal() or ether_addr_equal_unaligned() over memcmp()\n" . "$here\n$stat\n")
+# }
+
+# check for memset(foo, 0x0, ETH_ALEN) that could be eth_zero_addr
+# check for memset(foo, 0xFF, ETH_ALEN) that could be eth_broadcast_addr
+# if ($^V && $^V ge 5.10.0 &&
+# defined $stat &&
+# $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/) {
+#
+# my $ms_val = $7;
+#
+# if ($ms_val =~ /^(?:0x|)0+$/i) {
+# if (WARN("PREFER_ETH_ZERO_ADDR",
+# "Prefer eth_zero_addr over memset()\n" . "$here\n$stat\n") &&
+# $fix) {
+# $fixed[$fixlinenr] =~ s/\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*,\s*ETH_ALEN\s*\)/eth_zero_addr($2)/;
+# }
+# } elsif ($ms_val =~ /^(?:0xff|255)$/i) {
+# if (WARN("PREFER_ETH_BROADCAST_ADDR",
+# "Prefer eth_broadcast_addr() over memset()\n" . "$here\n$stat\n") &&
+# $fix) {
+# $fixed[$fixlinenr] =~ s/\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*,\s*ETH_ALEN\s*\)/eth_broadcast_addr($2)/;
+# }
+# }
+# }
# typecasts on min/max could be min_t/max_t
if ($^V && $^V ge 5.10.0 &&
# check for naked sscanf
if ($^V && $^V ge 5.10.0 &&
defined $stat &&
- $stat =~ /\bsscanf\b/ &&
+ $line =~ /\bsscanf\b/ &&
($stat !~ /$Ident\s*=\s*sscanf\s*$balanced_parens/ &&
$stat !~ /\bsscanf\s*$balanced_parens\s*(?:$Compare)/ &&
$stat !~ /(?:$Compare)\s*\bsscanf\s*$balanced_parens/)) {
"unchecked sscanf return value\n" . "$here\n$stat_real\n");
}
+# check for simple sscanf that should be kstrto<foo>
+ if ($^V && $^V ge 5.10.0 &&
+ defined $stat &&
+ $line =~ /\bsscanf\b/) {
+ my $lc = $stat =~ tr@\n@@;
+ $lc = $lc + $linenr;
+ my $stat_real = raw_line($linenr, 0);
+ for (my $count = $linenr + 1; $count <= $lc; $count++) {
+ $stat_real = $stat_real . "\n" . raw_line($count, 0);
+ }
+ if ($stat_real =~ /\bsscanf\b\s*\(\s*$FuncArg\s*,\s*("[^"]+")/) {
+ my $format = $6;
+ my $count = $format =~ tr@%@%@;
+ if ($count == 1 &&
+ $format =~ /^"\%(?i:ll[udxi]|[udxi]ll|ll|[hl]h?[udxi]|[udxi][hl]h?|[hl]h?|[udxi])"$/) {
+ WARN("SSCANF_TO_KSTRTO",
+ "Prefer kstrto<type> to single variable sscanf\n" . "$here\n$stat_real\n");
+ }
+ }
+ }
+
# check for new externs in .h files.
if ($realfile =~ /\.h$/ &&
$line =~ /^\+\s*(extern\s+)$Type\s*$Ident\s*\(/s) {
if (CHK("AVOID_EXTERNS",
"extern prototypes should be avoided in .h files\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~ s/(.*)\bextern\b\s*(.*)/$1$2/;
+ $fixed[$fixlinenr] =~ s/(.*)\bextern\b\s*(.*)/$1$2/;
}
}
"externs should be avoided in .c files\n" . $herecurr);
}
+# check for function declarations that have arguments without identifier names
+ if (defined $stat &&
+ $stat =~ /^.\s*(?:extern\s+)?$Type\s*$Ident\s*\(\s*([^{]+)\s*\)\s*;/s &&
+ $1 ne "void") {
+ my $args = trim($1);
+ while ($args =~ m/\s*($Type\s*(?:$Ident|\(\s*\*\s*$Ident?\s*\)\s*$balanced_parens)?)/g) {
+ my $arg = trim($1);
+ if ($arg =~ /^$Type$/ && $arg !~ /enum\s+$Ident$/) {
+ WARN("FUNCTION_ARGUMENTS",
+ "function definition argument '$arg' should also have an identifier name\n" . $herecurr);
+ }
+ }
+ }
+
+# check for function definitions
+ if ($^V && $^V ge 5.10.0 &&
+ defined $stat &&
+ $stat =~ /^.\s*(?:$Storage\s+)?$Type\s*($Ident)\s*$balanced_parens\s*{/s) {
+ $context_function = $1;
+
+# check for multiline function definition with misplaced open brace
+ my $ok = 0;
+ my $cnt = statement_rawlines($stat);
+ my $herectx = $here . "\n";
+ for (my $n = 0; $n < $cnt; $n++) {
+ my $rl = raw_line($linenr, $n);
+ $herectx .= $rl . "\n";
+ $ok = 1 if ($rl =~ /^[ \+]\{/);
+ $ok = 1 if ($rl =~ /\{/ && $n == 0);
+ last if $rl =~ /^[ \+].*\{/;
+ }
+ if (!$ok) {
+ ERROR("OPEN_BRACE",
+ "open brace '{' following function definitions go on the next line\n" . $herectx);
+ }
+ }
+
# checks for new __setup's
if ($rawline =~ /\b__setup\("([^"]*)"/) {
my $name = $1;
if (!grep(/$name/, @setup_docs)) {
CHK("UNDOCUMENTED_SETUP",
- "__setup appears un-documented -- check Documentation/kernel-parameters.txt\n" . $herecurr);
+ "__setup appears un-documented -- check Documentation/admin-guide/kernel-parameters.rst\n" . $herecurr);
}
}
"Prefer $3(sizeof(*$1)...) over $3($4...)\n" . $herecurr);
}
+# check for k[mz]alloc with multiplies that could be kmalloc_array/kcalloc
+ if ($^V && $^V ge 5.10.0 &&
+ defined $stat &&
+ $stat =~ /^\+\s*($Lval)\s*\=\s*(?:$balanced_parens)?\s*(k[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)\s*,/) {
+ my $oldfunc = $3;
+ my $a1 = $4;
+ my $a2 = $10;
+ my $newfunc = "kmalloc_array";
+ $newfunc = "kcalloc" if ($oldfunc eq "kzalloc");
+ my $r1 = $a1;
+ my $r2 = $a2;
+ if ($a1 =~ /^sizeof\s*\S/) {
+ $r1 = $a2;
+ $r2 = $a1;
+ }
+ if ($r1 !~ /^sizeof\b/ && $r2 =~ /^sizeof\s*\S/ &&
+ !($r1 =~ /^$Constant$/ || $r1 =~ /^[A-Z_][A-Z0-9_]*$/)) {
+ my $ctx = '';
+ my $herectx = $here . "\n";
+ my $cnt = statement_rawlines($stat);
+ for (my $n = 0; $n < $cnt; $n++) {
+ $herectx .= raw_line($linenr, $n) . "\n";
+ }
+ if (WARN("ALLOC_WITH_MULTIPLY",
+ "Prefer $newfunc over $oldfunc with multiply\n" . $herectx) &&
+ $cnt == 1 &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*(k[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)/$1 . ' = ' . "$newfunc(" . trim($r1) . ', ' . trim($r2)/e;
+ }
+ }
+ }
+
# check for krealloc arg reuse
if ($^V && $^V ge 5.10.0 &&
$line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*krealloc\s*\(\s*\1\s*,/) {
"$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr);
}
-# check for GFP_NOWAIT use
- if ($line =~ /\b__GFP_NOFAIL\b/) {
- WARN("__GFP_NOFAIL",
- "Use of __GFP_NOFAIL is deprecated, no new users should be added\n" . $herecurr);
- }
-
# check for multiple semicolons
if ($line =~ /;\s*;\s*$/) {
if (WARN("ONE_SEMICOLON",
"Statements terminations use 1 semicolon\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~ s/(\s*;\s*){2,}$/;/g;
+ $fixed[$fixlinenr] =~ s/(\s*;\s*){2,}$/;/g;
+ }
+ }
+
+# check for #defines like: 1 << <digit> that could be BIT(digit), it is not exported to uapi
+ if ($realfile !~ m@^include/uapi/@ &&
+ $line =~ /#\s*define\s+\w+\s+\(?\s*1\s*([ulUL]*)\s*\<\<\s*(?:\d+|$Ident)\s*\)?/) {
+ my $ull = "";
+ $ull = "_ULL" if (defined($1) && $1 =~ /ll/i);
+ if (CHK("BIT_MACRO",
+ "Prefer using the BIT$ull macro\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\(?\s*1\s*[ulUL]*\s*<<\s*(\d+|$Ident)\s*\)?/BIT${ull}($1)/;
+ }
+ }
+
+# check for #if defined CONFIG_<FOO> || defined CONFIG_<FOO>_MODULE
+ if ($line =~ /^\+\s*#\s*if\s+defined(?:\s*\(?\s*|\s+)(CONFIG_[A-Z_]+)\s*\)?\s*\|\|\s*defined(?:\s*\(?\s*|\s+)\1_MODULE\s*\)?\s*$/) {
+ my $config = $1;
+ if (WARN("PREFER_IS_ENABLED",
+ "Prefer IS_ENABLED(<FOO>) to CONFIG_<FOO> || CONFIG_<FOO>_MODULE\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] = "\+#if IS_ENABLED($config)";
}
}
my $has_statement = 0;
my $count = 0;
my $prevline = $linenr;
- while ($prevline > 1 && $count < 3 && !$has_break) {
+ while ($prevline > 1 && ($file || $count < 3) && !$has_break) {
$prevline--;
my $rline = $rawlines[$prevline - 1];
my $fline = $lines[$prevline - 1];
if (WARN("USE_FUNC",
"__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr) &&
$fix) {
- $fixed[$linenr - 1] =~ s/\b__FUNCTION__\b/__func__/g;
+ $fixed[$fixlinenr] =~ s/\b__FUNCTION__\b/__func__/g;
}
}
+# check for uses of __DATE__, __TIME__, __TIMESTAMP__
+ while ($line =~ /\b(__(?:DATE|TIME|TIMESTAMP)__)\b/g) {
+ ERROR("DATE_TIME",
+ "Use of the '$1' macro makes the build non-deterministic\n" . $herecurr);
+ }
+
# check for use of yield()
if ($line =~ /\byield\s*\(\s*\)/) {
WARN("YIELD",
"$1 is obsolete, use k$3 instead\n" . $herecurr);
}
-# check for __initcall(), use device_initcall() explicitly please
+# check for __initcall(), use device_initcall() explicitly or more appropriate function please
if ($line =~ /^.\s*__initcall\s*\(/) {
WARN("USE_DEVICE_INITCALL",
- "please use device_initcall() instead of __initcall()\n" . $herecurr);
- }
-
-# check for various ops structs, ensure they are const.
- my $struct_ops = qr{acpi_dock_ops|
- address_space_operations|
- backlight_ops|
- block_device_operations|
- dentry_operations|
- dev_pm_ops|
- dma_map_ops|
- extent_io_ops|
- file_lock_operations|
- file_operations|
- hv_ops|
- ide_dma_ops|
- intel_dvo_dev_ops|
- item_operations|
- iwl_ops|
- kgdb_arch|
- kgdb_io|
- kset_uevent_ops|
- lock_manager_operations|
- microcode_ops|
- mtrr_ops|
- neigh_ops|
- nlmsvc_binding|
- pci_raw_ops|
- pipe_buf_operations|
- platform_hibernation_ops|
- platform_suspend_ops|
- proto_ops|
- rpc_pipe_ops|
- seq_operations|
- snd_ac97_build_ops|
- soc_pcmcia_socket_ops|
- stacktrace_ops|
- sysfs_ops|
- tty_operations|
- usb_mon_operations|
- wd_ops}x;
+ "please use device_initcall() or more appropriate function instead of __initcall() (see include/linux/init.h)\n" . $herecurr);
+ }
+
+# check for various structs that are normally const (ops, kgdb, device_tree)
+# and avoid what seem like struct definitions 'struct foo {'
if ($line !~ /\bconst\b/ &&
- $line =~ /\bstruct\s+($struct_ops)\b/) {
+ $line =~ /\bstruct\s+($const_structs)\b(?!\s*\{)/) {
WARN("CONST_STRUCT",
- "struct $1 should normally be const\n" .
- $herecurr);
+ "struct $1 should normally be const\n" . $herecurr);
}
# use of NR_CPUS is usually wrong
"#define of '$1' is wrong - use Kconfig variables or standard guards instead\n" . $herecurr);
}
-# check for %L{u,d,i} in strings
- my $string;
- while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) {
- $string = substr($rawline, $-[1], $+[1] - $-[1]);
- $string =~ s/%%/__/g;
- if ($string =~ /(?<!%)%L[udi]/) {
- WARN("PRINTF_L",
- "\%Ld/%Lu are not-standard C, use %lld/%llu\n" . $herecurr);
- last;
- }
+# likely/unlikely comparisons similar to "(likely(foo) > 0)"
+ if ($^V && $^V ge 5.10.0 &&
+ $line =~ /\b((?:un)?likely)\s*\(\s*$FuncArg\s*\)\s*$Compare/) {
+ WARN("LIKELY_MISUSE",
+ "Using $1 should generally have parentheses around the comparison\n" . $herecurr);
}
# whine mightly about in_atomic
}
}
+# whine about ACCESS_ONCE
+ if ($^V && $^V ge 5.10.0 &&
+ $line =~ /\bACCESS_ONCE\s*$balanced_parens\s*(=(?!=))?\s*($FuncArg)?/) {
+ my $par = $1;
+ my $eq = $2;
+ my $fun = $3;
+ $par =~ s/^\(\s*(.*)\s*\)$/$1/;
+ if (defined($eq)) {
+ if (WARN("PREFER_WRITE_ONCE",
+ "Prefer WRITE_ONCE(<FOO>, <BAR>) over ACCESS_ONCE(<FOO>) = <BAR>\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\bACCESS_ONCE\s*\(\s*\Q$par\E\s*\)\s*$eq\s*\Q$fun\E/WRITE_ONCE($par, $fun)/;
+ }
+ } else {
+ if (WARN("PREFER_READ_ONCE",
+ "Prefer READ_ONCE(<FOO>) over ACCESS_ONCE(<FOO>)\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/\bACCESS_ONCE\s*\(\s*\Q$par\E\s*\)/READ_ONCE($par)/;
+ }
+ }
+ }
+
+# check for mutex_trylock_recursive usage
+ if ($line =~ /mutex_trylock_recursive/) {
+ ERROR("LOCKING",
+ "recursive locking is bad, do not use this ever.\n" . $herecurr);
+ }
+
# check for lockdep_set_novalidate_class
if ($line =~ /^.\s*lockdep_set_novalidate_class\s*\(/ ||
$line =~ /__lockdep_no_validate__\s*\)/ ) {
}
}
- if ($line =~ /debugfs_create_file.*S_IWUGO/ ||
- $line =~ /DEVICE_ATTR.*S_IWUGO/ ) {
+ if ($line =~ /debugfs_create_\w+.*\b$mode_perms_world_writable\b/ ||
+ $line =~ /DEVICE_ATTR.*\b$mode_perms_world_writable\b/) {
WARN("EXPORTED_WORLD_WRITABLE",
"Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr);
}
+
+# Mode permission misuses where it seems decimal should be octal
+# This uses a shortcut match to avoid unnecessary uses of a slow foreach loop
+ if ($^V && $^V ge 5.10.0 &&
+ defined $stat &&
+ $line =~ /$mode_perms_search/) {
+ foreach my $entry (@mode_permission_funcs) {
+ my $func = $entry->[0];
+ my $arg_pos = $entry->[1];
+
+ my $lc = $stat =~ tr@\n@@;
+ $lc = $lc + $linenr;
+ my $stat_real = raw_line($linenr, 0);
+ for (my $count = $linenr + 1; $count <= $lc; $count++) {
+ $stat_real = $stat_real . "\n" . raw_line($count, 0);
+ }
+
+ my $skip_args = "";
+ if ($arg_pos > 1) {
+ $arg_pos--;
+ $skip_args = "(?:\\s*$FuncArg\\s*,\\s*){$arg_pos,$arg_pos}";
+ }
+ my $test = "\\b$func\\s*\\(${skip_args}($FuncArg(?:\\|\\s*$FuncArg)*)\\s*[,\\)]";
+ if ($stat =~ /$test/) {
+ my $val = $1;
+ $val = $6 if ($skip_args ne "");
+ if (($val =~ /^$Int$/ && $val !~ /^$Octal$/) ||
+ ($val =~ /^$Octal$/ && length($val) ne 4)) {
+ ERROR("NON_OCTAL_PERMISSIONS",
+ "Use 4 digit octal (0777) not decimal permissions\n" . "$here\n" . $stat_real);
+ }
+ if ($val =~ /^$Octal$/ && (oct($val) & 02)) {
+ ERROR("EXPORTED_WORLD_WRITABLE",
+ "Exporting writable files is usually an error. Consider more restrictive permissions.\n" . "$here\n" . $stat_real);
+ }
+ }
+ }
+ }
+
+# check for uses of S_<PERMS> that could be octal for readability
+ if ($line =~ /\b$mode_perms_string_search\b/) {
+ my $val = "";
+ my $oval = "";
+ my $to = 0;
+ my $curpos = 0;
+ my $lastpos = 0;
+ while ($line =~ /\b(($mode_perms_string_search)\b(?:\s*\|\s*)?\s*)/g) {
+ $curpos = pos($line);
+ my $match = $2;
+ my $omatch = $1;
+ last if ($lastpos > 0 && ($curpos - length($omatch) != $lastpos));
+ $lastpos = $curpos;
+ $to |= $mode_permission_string_types{$match};
+ $val .= '\s*\|\s*' if ($val ne "");
+ $val .= $match;
+ $oval .= $omatch;
+ }
+ $oval =~ s/^\s*\|\s*//;
+ $oval =~ s/\s*\|\s*$//;
+ my $octal = sprintf("%04o", $to);
+ if (WARN("SYMBOLIC_PERMS",
+ "Symbolic permissions '$oval' are not preferred. Consider using octal permissions '$octal'.\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/$val/$octal/;
+ }
+ }
+
+# validate content of MODULE_LICENSE against list from include/linux/module.h
+ if ($line =~ /\bMODULE_LICENSE\s*\(\s*($String)\s*\)/) {
+ my $extracted_string = get_quoted_string($line, $rawline);
+ my $valid_licenses = qr{
+ GPL|
+ GPL\ v2|
+ GPL\ and\ additional\ rights|
+ Dual\ BSD/GPL|
+ Dual\ MIT/GPL|
+ Dual\ MPL/GPL|
+ Proprietary
+ }x;
+ if ($extracted_string !~ /^"(?:$valid_licenses)"$/x) {
+ WARN("MODULE_LICENSE",
+ "unknown module license " . $extracted_string . "\n" . $herecurr);
+ }
+ }
}
# If we have no input at all, then there is nothing to report on
exit(0);
}
- if (!$is_patch) {
+ if (!$is_patch && $file !~ /cover-letter\.patch$/) {
ERROR("NOT_UNIFIED_DIFF",
"Does not appear to be a unified-diff format patch\n");
}
- if ($is_patch && $chk_signoff && $signoff == 0) {
+ if ($is_patch && $has_commit_log && $chk_signoff && $signoff == 0) {
ERROR("MISSING_SIGN_OFF",
"Missing Signed-off-by: line(s)\n");
}
print "total: $cnt_error errors, $cnt_warn warnings, " .
(($check)? "$cnt_chk checks, " : "") .
"$cnt_lines lines checked\n";
- print "\n" if ($quiet == 0);
}
if ($quiet == 0) {
+ # If there were any defects found and not already fixing them
+ if (!$clean and !$fix) {
+ print << "EOM"
- if ($^V lt 5.10.0) {
- print("NOTE: perl $^V is not modern enough to detect all possible issues.\n");
- print("An upgrade to at least perl v5.10.0 is suggested.\n\n");
+NOTE: For some of the reported defects, checkpatch may be able to
+ mechanically convert to the typical style using --fix or --fix-inplace.
+EOM
}
-
# If there were whitespace errors which cleanpatch can fix
# then suggest that.
if ($rpt_cleaners) {
- print "NOTE: whitespace errors detected, you may wish to use scripts/cleanpatch or\n";
- print " scripts/cleanfile\n\n";
$rpt_cleaners = 0;
+ print << "EOM"
+
+NOTE: Whitespace errors detected.
+ You may wish to use scripts/cleanpatch or scripts/cleanfile
+EOM
}
}
- hash_show_words(\%use_type, "Used");
- hash_show_words(\%ignore_type, "Ignored");
-
- if ($clean == 0 && $fix && "@rawlines" ne "@fixed") {
+ if ($clean == 0 && $fix &&
+ ("@rawlines" ne "@fixed" ||
+ $#fixed_inserted >= 0 || $#fixed_deleted >= 0)) {
my $newfile = $filename;
$newfile .= ".EXPERIMENTAL-checkpatch-fixes" if (!$fix_inplace);
my $linecount = 0;
my $f;
+ @fixed = fix_inserted_deleted_lines(\@fixed, \@fixed_inserted, \@fixed_deleted);
+
open($f, '>', $newfile)
or die "$P: Can't open $newfile for write\n";
foreach my $fixed_line (@fixed) {
if ($file) {
if ($linecount > 3) {
$fixed_line =~ s/^\+//;
- print $f $fixed_line. "\n";
+ print $f $fixed_line . "\n";
}
} else {
print $f $fixed_line . "\n";
if (!$quiet) {
print << "EOM";
+
Wrote EXPERIMENTAL --fix correction(s) to '$newfile'
Do _NOT_ trust the results written to this file.
This EXPERIMENTAL file is simply a convenience to help rewrite patches.
No warranties, expressed or implied...
-
EOM
}
}
- if ($clean == 1 && $quiet == 0) {
- print "$vname has no obvious style problems and is ready for submission.\n"
- }
- if ($clean == 0 && $quiet == 0) {
- print << "EOM";
-$vname has style problems, please review.
-
-If any of these errors are false positives, please report
-them to the maintainer, see CHECKPATCH in MAINTAINERS.
-EOM
+ if ($quiet == 0) {
+ print "\n";
+ if ($clean == 1) {
+ print "$vname has no obvious style problems and is ready for submission.\n";
+ } else {
+ print "$vname has style problems, please review.\n";
+ }
}
-
return $clean;
}
CONFIG_EHCI_MXS_PORT0
CONFIG_EHCI_MXS_PORT1
CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
-CONFIG_EMIF4
CONFIG_EMMC_BOOT
CONFIG_EMU
CONFIG_ENABLE_36BIT_PHYS
CONFIG_IPAM390_GPIO_LED_GREEN
CONFIG_IPAM390_GPIO_LED_RED
CONFIG_IPROC
-CONFIG_IPUV3_CLK
CONFIG_IP_DEFRAG
CONFIG_IRAM_BASE
CONFIG_IRAM_END
CONFIG_MACH_TYPE
CONFIG_MACH_TYPE_COMPAT_REV
CONFIG_MACRESET_TIMEOUT
-CONFIG_MAC_ADDR_IN_EEPROM
-CONFIG_MAC_ADDR_IN_SPIFLASH
CONFIG_MALLOC_F_ADDR
CONFIG_MALTA
CONFIG_MARCO_MEMSET
CONFIG_SAMSUNG_ONENAND
CONFIG_SANDBOX_ARCH
CONFIG_SANDBOX_BIG_ENDIAN
-CONFIG_SANDBOX_BITS_PER_LONG
CONFIG_SANDBOX_SDL
CONFIG_SANDBOX_SPI_MAX_BUS
CONFIG_SANDBOX_SPI_MAX_CS
CONFIG_SC_TIMER_CLK
CONFIG_SDCARD
CONFIG_SDRAM_OFFSET_FOR_RT
-CONFIG_SDRC
CONFIG_SD_BOOT_QSPI
CONFIG_SECBOOT
CONFIG_SECURE_BL1_ONLY
CONFIG_SYS_CADMUS_BASE_REG
CONFIG_SYS_CBSIZE
CONFIG_SYS_CCCR
-CONFIG_SYS_CCI400_ADDR
CONFIG_SYS_CCSRBAR
CONFIG_SYS_CCSRBAR_PHYS
CONFIG_SYS_CCSRBAR_PHYS_HIGH
CONFIG_SYS_PSSR_VAL
CONFIG_SYS_PTCPAR
CONFIG_SYS_PTDPAR
-CONFIG_SYS_PTL2_BITS
CONFIG_SYS_PTV
CONFIG_SYS_PUAPAR
CONFIG_SYS_QE_FMAN_FW_IN_MMC
CONFIG_SYS_USE_SPIFLASH
CONFIG_SYS_USR_EXCEP
CONFIG_SYS_U_BOOT_OFFS
-CONFIG_SYS_VA_BITS
CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT
--- /dev/null
+# Put structs here that should be constant
+__dummy__
/* Create two, one the parent of the other */
ut_assertok(blk_create_device(gd->dm_root, "sandbox_host_blk", "test",
- IF_TYPE_HOST, 1, 512, 1024, &blk));
+ IF_TYPE_HOST, 1, 512, 2, &blk));
ut_assertok(blk_create_device(blk, "usb_storage_blk", "test",
- IF_TYPE_USB, 3, 512, 1024, &usb_blk));
+ IF_TYPE_USB, 3, 512, 2, &usb_blk));
/* Check we can find them */
ut_asserteq(-ENODEV, blk_get_device(IF_TYPE_HOST, 0, &dev));
struct udevice *blk, *dev;
ut_assertok(blk_create_device(gd->dm_root, "sandbox_host_blk", "test",
- IF_TYPE_HOST, 1, 512, 1024, &blk));
+ IF_TYPE_HOST, 1, 512, 2, &blk));
ut_asserteq(-ENODEV, blk_find_device(IF_TYPE_HOST, 0, &dev));
ut_assertok(blk_find_device(IF_TYPE_HOST, 1, &dev));
ut_asserteq_ptr(blk, dev);
if (test->flags & DM_TESTF_PROBE_TEST)
ut_assertok(do_autoprobe(uts));
if (test->flags & DM_TESTF_SCAN_FDT)
- ut_assertok(dm_scan_fdt(gd->fdt_blob, false));
+ ut_assertok(dm_extended_scan_fdt(gd->fdt_blob, false));
/*
* Silence the console and rely on console reocrding to get
# DT overlays
obj-y += test-fdt-base.dtb.o
obj-y += test-fdt-overlay.dtb.o
+obj-y += test-fdt-overlay-stacked.dtb.o
extern u32 __dtb_test_fdt_base_begin;
extern u32 __dtb_test_fdt_overlay_begin;
+extern u32 __dtb_test_fdt_overlay_stacked_begin;
-static int fdt_getprop_u32_by_index(void *fdt, const char *path,
+static int ut_fdt_getprop_u32_by_index(void *fdt, const char *path,
const char *name, int index,
u32 *out)
{
return 0;
}
-static int fdt_getprop_u32(void *fdt, const char *path, const char *name,
+static int ut_fdt_getprop_u32(void *fdt, const char *path, const char *name,
u32 *out)
{
- return fdt_getprop_u32_by_index(fdt, path, name, 0, out);
+ return ut_fdt_getprop_u32_by_index(fdt, path, name, 0, out);
}
static int fdt_getprop_str(void *fdt, const char *path, const char *name,
void *fdt = uts->priv;
u32 val = 0;
- ut_assertok(fdt_getprop_u32(fdt, "/test-node", "test-int-property",
+ ut_assertok(ut_fdt_getprop_u32(fdt, "/test-node", "test-int-property",
&val));
ut_asserteq(43, val);
local_phandle = fdt_get_phandle(fdt, off);
ut_assert(local_phandle);
- ut_assertok(fdt_getprop_u32_by_index(fdt, "/", "test-several-phandle",
+ ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", "test-several-phandle",
0, &val));
ut_asserteq(local_phandle, val);
- ut_assertok(fdt_getprop_u32_by_index(fdt, "/", "test-several-phandle",
+ ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", "test-several-phandle",
1, &val));
ut_asserteq(local_phandle, val);
test_phandle = fdt_get_phandle(fdt, off);
ut_assert(test_phandle);
- ut_assertok(fdt_getprop_u32_by_index(fdt, "/", "test-phandle", 0,
+ ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", "test-phandle", 0,
&val));
ut_asserteq(test_phandle, val);
- ut_assertok(fdt_getprop_u32_by_index(fdt, "/", "test-phandle", 1,
+ ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", "test-phandle", 1,
&val));
ut_asserteq(local_phandle, val);
}
OVERLAY_TEST(fdt_overlay_local_phandles, 0);
+static int fdt_overlay_stacked(struct unit_test_state *uts)
+{
+ void *fdt = uts->priv;
+ u32 val = 0;
+
+ ut_assertok(ut_fdt_getprop_u32(fdt, "/new-local-node",
+ "stacked-test-int-property", &val));
+ ut_asserteq(43, val);
+
+ return CMD_RET_SUCCESS;
+}
+OVERLAY_TEST(fdt_overlay_stacked, 0);
+
int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct unit_test *tests = ll_entry_start(struct unit_test,
struct unit_test *test;
void *fdt_base = &__dtb_test_fdt_base_begin;
void *fdt_overlay = &__dtb_test_fdt_overlay_begin;
- void *fdt_base_copy, *fdt_overlay_copy;
+ void *fdt_overlay_stacked = &__dtb_test_fdt_overlay_stacked_begin;
+ void *fdt_base_copy, *fdt_overlay_copy, *fdt_overlay_stacked_copy;
uts = calloc(1, sizeof(*uts));
if (!uts)
if (!fdt_overlay_copy)
return -ENOMEM;
+ fdt_overlay_stacked_copy = malloc(FDT_COPY_SIZE);
+ if (!fdt_overlay_stacked_copy)
+ return -ENOMEM;
+
/*
* Resize the FDT to 4k so that we have room to operate on
*
ut_assertok(fdt_open_into(fdt_overlay, fdt_overlay_copy,
FDT_COPY_SIZE));
+ /*
+ * Resize the stacked overlay to 4k so that we have room to operate on
+ *
+ * (and relocate it since the memory might be mapped
+ * read-only)
+ */
+ ut_assertok(fdt_open_into(fdt_overlay_stacked, fdt_overlay_stacked_copy,
+ FDT_COPY_SIZE));
+
/* Apply the overlay */
ut_assertok(fdt_overlay_apply(fdt_base_copy, fdt_overlay_copy));
+ /* Apply the stacked overlay */
+ ut_assertok(fdt_overlay_apply(fdt_base_copy, fdt_overlay_stacked_copy));
+
if (argc == 1)
printf("Running %d environment tests\n", n_ents);
printf("Failures: %d\n", uts->fail_count);
+ free(fdt_overlay_stacked_copy);
free(fdt_overlay_copy);
free(fdt_base_copy);
free(uts);
--- /dev/null
+/*
+ * Copyright (c) 2016 NextThing Co
+ * Copyright (c) 2016 Free Electrons
+ * Copyright (c) 2018 Konsulko Group
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ /* Test that we can reference an overlay symbol */
+ fragment@0 {
+ target = <&local>;
+
+ __overlay__ {
+ stacked-test-int-property = <43>;
+ };
+ };
+};
--- /dev/null
+# Copyright (c) 2017 Alison Chaiken
+# Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+# Test GPT manipulation commands.
+
+import os
+import pytest
+import u_boot_utils
+
+"""
+These tests rely on a 4 MB disk image, which is automatically created by
+the test.
+"""
+
+class GptTestDiskImage(object):
+ """Disk Image used by the GPT tests."""
+
+ def __init__(self, u_boot_console):
+ """Initialize a new GptTestDiskImage object.
+
+ Args:
+ u_boot_console: A U-Boot console.
+
+ Returns:
+ Nothing.
+ """
+
+ filename = 'test_gpt_disk_image.bin'
+ self.path = u_boot_console.config.persistent_data_dir + '/' + filename
+
+ if os.path.exists(self.path):
+ u_boot_console.log.action('Disk image file ' + self.path +
+ ' already exists')
+ else:
+ u_boot_console.log.action('Generating ' + self.path)
+ fd = os.open(self.path, os.O_RDWR | os.O_CREAT)
+ os.ftruncate(fd, 4194304)
+ os.close(fd)
+ sgdisk = '/sbin/sgdisk'
+ cmd = (sgdisk, '-U', '375a56f7-d6c9-4e81-b5f0-09d41ca89efe',
+ self.path)
+ u_boot_utils.run_and_log(u_boot_console, cmd)
+ cmd = (sgdisk, '--new=1:2048:2560', self.path)
+ u_boot_utils.run_and_log(u_boot_console, cmd)
+ cmd = (sgdisk, '--new=2:4096:4608', self.path)
+ u_boot_utils.run_and_log(u_boot_console, cmd)
+ cmd = (sgdisk, '-l', self.path)
+ u_boot_utils.run_and_log(u_boot_console, cmd)
+
+gtdi = None
+@pytest.fixture(scope='function')
+def state_disk_image(u_boot_console):
+ """pytest fixture to provide a GptTestDiskImage object to tests.
+ This is function-scoped because it uses u_boot_console, which is also
+ function-scoped. However, we don't need to actually do any function-scope
+ work, so this simply returns the same object over and over each time."""
+
+ global gtdi
+ if not gtdi:
+ gtdi = GptTestDiskImage(u_boot_console)
+ return gtdi
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('cmd_gpt')
+def test_gpt_guid(state_disk_image, u_boot_console):
+ """Test the gpt guid command."""
+
+ u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
+ output = u_boot_console.run_command('gpt guid host 0')
+ assert '375a56f7-d6c9-4e81-b5f0-09d41ca89efe' in output
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('cmd_gpt')
+def test_gpt_save_guid(state_disk_image, u_boot_console):
+ """Test the gpt guid command to save GUID into a string."""
+
+ if u_boot_console.config.buildconfig.get('config_cmd_gpt', 'n') != 'y':
+ pytest.skip('gpt command not supported')
+ u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
+ output = u_boot_console.run_command('gpt guid host 0 newguid')
+ output = u_boot_console.run_command('printenv newguid')
+ assert '375a56f7-d6c9-4e81-b5f0-09d41ca89efe' in output
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('cmd_gpt')
+@pytest.mark.buildconfigspec('cmd_gpt_rename')
+def test_gpt_rename_partition(state_disk_image, u_boot_console):
+ """Test the gpt rename command to write partition names."""
+
+ u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
+ u_boot_console.run_command('gpt rename host 0 1 first')
+ output = u_boot_console.run_command('gpt read host 0')
+ assert 'name first' in output
+ u_boot_console.run_command('gpt rename host 0 2 second')
+ output = u_boot_console.run_command('gpt read host 0')
+ assert 'name second' in output
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.buildconfigspec('cmd_gpt')
+@pytest.mark.buildconfigspec('cmd_gpt_rename')
+@pytest.mark.buildconfigspec('cmd_part')
+def test_gpt_swap_partitions(state_disk_image, u_boot_console):
+ """Test the gpt swap command to exchange two partition names."""
+
+ u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
+ output = u_boot_console.run_command('part list host 0')
+ assert '0x000007ff "first"' in output
+ assert '0x000017ff "second"' in output
+ u_boot_console.run_command('gpt swap host 0 first second')
+ output = u_boot_console.run_command('part list host 0')
+ assert '0x000007ff "second"' in output
+ assert '0x000017ff "first"' in output
Args:
cmd: The command to send.
- wait_for_each: Boolean indicating whether to wait for U-Boot to
+ wait_for_echo: Boolean indicating whether to wait for U-Boot to
echo the command text back to its output.
send_nl: Boolean indicating whether to send a newline character
after the command string.
--- /dev/null
+#
+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Entry-type module for Intel Video BIOS Table binary blob
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_intel_vbt(Entry_blob):
+ def __init__(self, image, etype, node):
+ Entry_blob.__init__(self, image, etype, node)
U_BOOT_NODTB_DATA = 'nodtb with microcode pointer somewhere in here'
FSP_DATA = 'fsp'
CMC_DATA = 'cmc'
+VBT_DATA = 'vbt'
class TestFunctional(unittest.TestCase):
"""Functional tests for binman
TestFunctional._MakeInputFile('u-boot-nodtb.bin', U_BOOT_NODTB_DATA)
TestFunctional._MakeInputFile('fsp.bin', FSP_DATA)
TestFunctional._MakeInputFile('cmc.bin', CMC_DATA)
+ TestFunctional._MakeInputFile('vbt.bin', VBT_DATA)
self._output_setup = False
# ELF file with a '_dt_ucode_base_size' symbol
self.assertEqual(FSP_DATA, data[:len(FSP_DATA)])
def testPackCmc(self):
- """Test that an image with a FSP binary can be created"""
+ """Test that an image with a CMC binary can be created"""
data = self._DoReadFile('43_intel-cmc.dts')
self.assertEqual(CMC_DATA, data[:len(CMC_DATA)])
+
+ def testPackVbt(self):
+ """Test that an image with a VBT binary can be created"""
+ data = self._DoReadFile('46_intel-vbt.dts')
+ self.assertEqual(VBT_DATA, data[:len(VBT_DATA)])
--- /dev/null
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ size = <16>;
+
+ intel-vbt {
+ filename = "vbt.bin";
+ };
+ };
+};
self.print_warnings = print_warnings
self.print_undef_assign = print_undef_assign
+ self._warnings = []
# For parsing routines that stop when finding a line belonging to a
# different construct, these holds that line and the tokenized version
need to refer to the top-level kernel directory with "$srctree".
replace (default: True): True if the configuration should replace the
- old configuration; False if it should add to it."""
+ old configuration; False if it should add to it.
+ Returns a list or warnings (hopefully empty)
+ """
+
+ self._warnings = []
# Put this first so that a missing file doesn't screw up our state
filename = os.path.expandvars(filename)
line_feeder = _FileFeed(filename)
while 1:
line = line_feeder.get_next()
if line is None:
- return
+ return self._warnings
line = line.rstrip()
def _warn(self, msg, filename=None, linenr=None):
"""For printing warnings to stderr."""
+ msg = _build_msg("warning: " + msg, filename, linenr)
if self.print_warnings:
- _stderr_msg("warning: " + msg, filename, linenr)
+ sys.stderr.write(msg + "\n")
+ self._warnings.append(msg)
class Item(object):
path = path[2:]
return path.rstrip("/")
-def _stderr_msg(msg, filename, linenr):
+def _build_msg(msg, filename, linenr):
if filename is not None:
- sys.stderr.write("{0}:{1}: ".format(_clean_up_path(filename), linenr))
- sys.stderr.write(msg + "\n")
+ msg = "{0}:{1}: ".format(_clean_up_path(filename), linenr) + msg
+ return msg
+
+def _stderr_msg(msg, filename, linenr):
+ sys.stderr.write(_build_msg(msg, filename, linenr) + "\n")
def _tokenization_error(s, filename, linenr):
loc = "" if filename is None else "{0}:{1}: ".format(filename, linenr)
static data.
"""
+import collections
import copy
import sys
fdt.TYPE_BYTE: 'unsigned char',
fdt.TYPE_STRING: 'const char *',
fdt.TYPE_BOOL: 'bool',
+ fdt.TYPE_INT64: 'fdt64_t',
}
STRUCT_PREFIX = 'dtd_'
VAL_PREFIX = 'dtv_'
+# This holds information about a property which includes phandles.
+#
+# max_args: integer: Maximum number or arguments that any phandle uses (int).
+# args: Number of args for each phandle in the property. The total number of
+# phandles is len(args). This is a list of integers.
+PhandleInfo = collections.namedtuple('PhandleInfo', ['max_args', 'args'])
+
+
def conv_name_to_c(name):
"""Convert a device-tree name to a C identifier
return '"%s"' % value
elif ftype == fdt.TYPE_BOOL:
return 'true'
+ elif ftype == fdt.TYPE_INT64:
+ return '%#x' % value
def get_compat_name(node):
"""Get a node's first compatible string as a C identifier
compat, aliases = compat[0], compat[1:]
return conv_name_to_c(compat), [conv_name_to_c(a) for a in aliases]
-def is_phandle(prop):
- """Check if a node contains phandles
-
- We have no reliable way of detecting whether a node uses a phandle
- or not. As an interim measure, use a list of known property names.
-
- Args:
- prop: Prop object to check
- Return:
- True if the object value contains phandles, else False
- """
- if prop.name in ['clocks']:
- return True
- return False
-
class DtbPlatdata(object):
"""Provide a means to convert device tree binary data to platform data
_dtb_fname: Filename of the input device tree binary file
_valid_nodes: A list of Node object with compatible strings
_include_disabled: true to include nodes marked status = "disabled"
- _phandle_nodes: A dict of nodes indexed by phandle number (1, 2...)
_outfile: The current output file (sys.stdout or a real file)
_lines: Stashed list of output lines for outputting in the future
- _phandle_nodes: A dict of Nodes indexed by phandle (an integer)
"""
def __init__(self, dtb_fname, include_disabled):
self._fdt = None
self._dtb_fname = dtb_fname
self._valid_nodes = None
self._include_disabled = include_disabled
- self._phandle_nodes = {}
self._outfile = None
self._lines = []
self._aliases = {}
self._lines = []
return lines
+ def out_header(self):
+ """Output a message indicating that this is an auto-generated file"""
+ self.out('''/*
+ * DO NOT MODIFY
+ *
+ * This file was generated by dtoc from a .dtb (device tree binary) file.
+ */
+
+''')
+
+ def get_phandle_argc(self, prop, node_name):
+ """Check if a node contains phandles
+
+ We have no reliable way of detecting whether a node uses a phandle
+ or not. As an interim measure, use a list of known property names.
+
+ Args:
+ prop: Prop object to check
+ Return:
+ Number of argument cells is this is a phandle, else None
+ """
+ if prop.name in ['clocks']:
+ val = prop.value
+ if not isinstance(val, list):
+ val = [val]
+ i = 0
+
+ max_args = 0
+ args = []
+ while i < len(val):
+ phandle = fdt_util.fdt32_to_cpu(val[i])
+ target = self._fdt.phandle_to_node.get(phandle)
+ if not target:
+ raise ValueError("Cannot parse '%s' in node '%s'" %
+ (prop.name, node_name))
+ prop_name = '#clock-cells'
+ cells = target.props.get(prop_name)
+ if not cells:
+ raise ValueError("Node '%s' has no '%s' property" %
+ (target.name, prop_name))
+ num_args = fdt_util.fdt32_to_cpu(cells.value)
+ max_args = max(max_args, num_args)
+ args.append(num_args)
+ i += 1 + num_args
+ return PhandleInfo(max_args, args)
+ return None
+
def scan_dtb(self):
"""Scan the device tree to obtain a tree of nodes and properties
def scan_node(self, root):
"""Scan a node and subnodes to build a tree of node and phandle info
- This adds each node to self._valid_nodes and each phandle to
- self._phandle_nodes.
+ This adds each node to self._valid_nodes.
Args:
root: Root node for scan
if (not self._include_disabled and not status or
status.value != 'disabled'):
self._valid_nodes.append(node)
- phandle_prop = node.props.get('phandle')
- if phandle_prop:
- phandle = phandle_prop.GetPhandle()
- self._phandle_nodes[phandle] = node
# recurse to handle any subnodes
self.scan_node(node)
"""Scan the device tree for useful information
This fills in the following properties:
- _phandle_nodes: A dict of Nodes indexed by phandle (an integer)
_valid_nodes: A list of nodes we wish to consider include in the
platform data
"""
- self._phandle_nodes = {}
self._valid_nodes = []
return self.scan_node(self._fdt.GetRoot())
+ @staticmethod
+ def get_num_cells(node):
+ """Get the number of cells in addresses and sizes for this node
+
+ Args:
+ node: Node to check
+
+ Returns:
+ Tuple:
+ Number of address cells for this node
+ Number of size cells for this node
+ """
+ parent = node.parent
+ na, ns = 2, 2
+ if parent:
+ na_prop = parent.props.get('#address-cells')
+ ns_prop = parent.props.get('#size-cells')
+ if na_prop:
+ na = fdt_util.fdt32_to_cpu(na_prop.value)
+ if ns_prop:
+ ns = fdt_util.fdt32_to_cpu(ns_prop.value)
+ return na, ns
+
+ def scan_reg_sizes(self):
+ """Scan for 64-bit 'reg' properties and update the values
+
+ This finds 'reg' properties with 64-bit data and converts the value to
+ an array of 64-values. This allows it to be output in a way that the
+ C code can read.
+ """
+ for node in self._valid_nodes:
+ reg = node.props.get('reg')
+ if not reg:
+ continue
+ na, ns = self.get_num_cells(node)
+ total = na + ns
+
+ if reg.type != fdt.TYPE_INT:
+ raise ValueError("Node '%s' reg property is not an int")
+ if len(reg.value) % total:
+ raise ValueError("Node '%s' reg property has %d cells "
+ 'which is not a multiple of na + ns = %d + %d)' %
+ (node.name, len(reg.value), na, ns))
+ reg.na = na
+ reg.ns = ns
+ if na != 1 or ns != 1:
+ reg.type = fdt.TYPE_INT64
+ i = 0
+ new_value = []
+ val = reg.value
+ if not isinstance(val, list):
+ val = [val]
+ while i < len(val):
+ addr = fdt_util.fdt_cells_to_cpu(val[i:], reg.na)
+ i += na
+ size = fdt_util.fdt_cells_to_cpu(val[i:], reg.ns)
+ i += ns
+ new_value += [addr, size]
+ reg.value = new_value
+
def scan_structs(self):
"""Scan the device tree building up the C structures we will use.
for pname, prop in node.props.items():
if pname in PROP_IGNORE_LIST or pname[0] == '#':
continue
- if isinstance(prop.value, list):
- if is_phandle(prop):
- # Process the list as pairs of (phandle, id)
- value_it = iter(prop.value)
- for phandle_cell, _ in zip(value_it, value_it):
- phandle = fdt_util.fdt32_to_cpu(phandle_cell)
- target_node = self._phandle_nodes[phandle]
- node.phandles.add(target_node)
+ info = self.get_phandle_argc(prop, node.name)
+ if info:
+ if not isinstance(prop.value, list):
+ prop.value = [prop.value]
+ # Process the list as pairs of (phandle, id)
+ pos = 0
+ for args in info.args:
+ phandle_cell = prop.value[pos]
+ phandle = fdt_util.fdt32_to_cpu(phandle_cell)
+ target_node = self._fdt.phandle_to_node[phandle]
+ node.phandles.add(target_node)
+ pos += 1 + args
def generate_structs(self, structs):
definitions for node in self._valid_nodes. See the documentation in
README.of-plat for more information.
"""
+ self.out_header()
self.out('#include <stdbool.h>\n')
self.out('#include <libfdt.h>\n')
self.out('struct %s%s {\n' % (STRUCT_PREFIX, name))
for pname in sorted(structs[name]):
prop = structs[name][pname]
- if is_phandle(prop):
+ info = self.get_phandle_argc(prop, structs[name])
+ if info:
# For phandles, include a reference to the target
- self.out('\t%s%s[%d]' % (tab_to(2, 'struct phandle_2_cell'),
+ struct_name = 'struct phandle_%d_arg' % info.max_args
+ self.out('\t%s%s[%d]' % (tab_to(2, struct_name),
conv_name_to_c(prop.name),
- len(prop.value) / 2))
+ len(info.args)))
else:
ptype = TYPE_NAMES[prop.type]
self.out('\t%s%s' % (tab_to(2, ptype),
vals = []
# For phandles, output a reference to the platform data
# of the target node.
- if is_phandle(prop):
+ info = self.get_phandle_argc(prop, node.name)
+ if info:
# Process the list as pairs of (phandle, id)
- value_it = iter(prop.value)
- for phandle_cell, id_cell in zip(value_it, value_it):
+ pos = 0
+ for args in info.args:
+ phandle_cell = prop.value[pos]
phandle = fdt_util.fdt32_to_cpu(phandle_cell)
- id_num = fdt_util.fdt32_to_cpu(id_cell)
- target_node = self._phandle_nodes[phandle]
+ target_node = self._fdt.phandle_to_node[phandle]
name = conv_name_to_c(target_node.name)
- vals.append('{&%s%s, %d}' % (VAL_PREFIX, name, id_num))
+ arg_values = []
+ for i in range(args):
+ arg_values.append(str(fdt_util.fdt32_to_cpu(prop.value[pos + 1 + i])))
+ pos += 1 + args
+ vals.append('\t{&%s%s, {%s}}' % (VAL_PREFIX, name,
+ ', '.join(arg_values)))
+ for val in vals:
+ self.buf('\n\t\t%s,' % val)
else:
for val in prop.value:
vals.append(get_value(prop.type, val))
- self.buf(', '.join(vals))
+
+ # Put 8 values per line to avoid very long lines.
+ for i in xrange(0, len(vals), 8):
+ if i:
+ self.buf(',\n\t\t')
+ self.buf(', '.join(vals[i:i + 8]))
self.buf('}')
else:
self.buf(get_value(prop.type, prop.value))
See the documentation in doc/driver-model/of-plat.txt for more
information.
"""
+ self.out_header()
self.out('#include <common.h>\n')
self.out('#include <dm.h>\n')
self.out('#include <dt-structs.h>\n')
plat = DtbPlatdata(dtb_file, include_disabled)
plat.scan_dtb()
plat.scan_tree()
+ plat.scan_reg_sizes()
plat.setup_output(output)
structs = plat.scan_structs()
plat.scan_phandles()
--- /dev/null
+/*
+ * Test device tree file for dtoc
+ *
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+ /dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ test1 {
+ u-boot,dm-pre-reloc;
+ compatible = "test1";
+ reg = <0x1234 0x5678>;
+ };
+
+ test2 {
+ u-boot,dm-pre-reloc;
+ compatible = "test2";
+ reg = <0x12345678 0x98765432 2 3>;
+ };
+
+};
--- /dev/null
+/*
+ * Test device tree file for dtoc
+ *
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+ /dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <2>;
+
+ test1 {
+ u-boot,dm-pre-reloc;
+ compatible = "test1";
+ reg = <0x1234 0x5678 0x0>;
+ };
+
+ test2 {
+ u-boot,dm-pre-reloc;
+ compatible = "test2";
+ reg = <0x12345678 0x98765432 0x10987654>;
+ };
+
+ test3 {
+ u-boot,dm-pre-reloc;
+ compatible = "test3";
+ reg = <0x12345678 0x98765432 0x10987654 2 0 3>;
+ };
+
+};
--- /dev/null
+/*
+ * Test device tree file for dtoc
+ *
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+ /dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ test1 {
+ u-boot,dm-pre-reloc;
+ compatible = "test1";
+ reg = /bits/ 64 <0x1234 0x5678>;
+ };
+
+ test2 {
+ u-boot,dm-pre-reloc;
+ compatible = "test2";
+ reg = /bits/ 64 <0x1234567890123456 0x9876543210987654>;
+ };
+
+ test3 {
+ u-boot,dm-pre-reloc;
+ compatible = "test3";
+ reg = /bits/ 64 <0x1234567890123456 0x9876543210987654 2 3>;
+ };
+
+};
--- /dev/null
+/*
+ * Test device tree file for dtoc
+ *
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+ /dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ test1 {
+ u-boot,dm-pre-reloc;
+ compatible = "test1";
+ reg = <0x1234 0x0 0x5678>;
+ };
+
+ test2 {
+ u-boot,dm-pre-reloc;
+ compatible = "test2";
+ reg = <0x12345678 0x90123456 0x98765432>;
+ };
+
+ test3 {
+ u-boot,dm-pre-reloc;
+ compatible = "test3";
+ reg = <0x12345678 0x90123456 0x98765432 0 2 3>;
+ };
+
+};
/ {
phandle: phandle-target {
+ u-boot,dm-pre-reloc;
+ compatible = "target";
+ intval = <0>;
+ #clock-cells = <0>;
+ };
+
+ phandle_1: phandle2-target {
u-boot,dm-pre-reloc;
compatible = "target";
intval = <1>;
+ #clock-cells = <1>;
+ };
+ phandle_2: phandle3-target {
+ u-boot,dm-pre-reloc;
+ compatible = "target";
+ intval = <2>;
+ #clock-cells = <2>;
};
phandle-source {
u-boot,dm-pre-reloc;
compatible = "source";
- clocks = <&phandle 1>;
+ clocks = <&phandle &phandle_1 11 &phandle_2 12 13 &phandle>;
};
};
/dts-v1/;
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
spl-test {
u-boot,dm-pre-reloc;
compatible = "sandbox,spl-test";
compatible = "sandbox,spl-test.2";
};
+ i2c@0 {
+ compatible = "sandbox,i2c-test";
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic@9 {
+ compatible = "sandbox,pmic-test";
+ u-boot,dm-pre-reloc;
+ reg = <9>;
+ low-power;
+ };
+ };
};
# so it is fairly efficient.
# A list of types we support
-(TYPE_BYTE, TYPE_INT, TYPE_STRING, TYPE_BOOL) = range(4)
+(TYPE_BYTE, TYPE_INT, TYPE_STRING, TYPE_BOOL, TYPE_INT64) = range(5)
def CheckErr(errnum, msg):
if errnum:
props: A dict of properties for this node, each a Prop object.
Keyed by property name
"""
- def __init__(self, fdt, offset, name, path):
+ def __init__(self, fdt, parent, offset, name, path):
self._fdt = fdt
+ self.parent = parent
self._offset = offset
self.name = name
self.path = path
searching into subnodes so that the entire tree is built.
"""
self.props = self._fdt.GetProps(self)
+ phandle = self.props.get('phandle')
+ if phandle:
+ val = fdt_util.fdt32_to_cpu(phandle.value)
+ self._fdt.phandle_to_node[val] = self
offset = libfdt.fdt_first_subnode(self._fdt.GetFdt(), self.Offset())
while offset >= 0:
sep = '' if self.path[-1] == '/' else '/'
name = self._fdt._fdt_obj.get_name(offset)
path = self.path + sep + name
- node = Node(self._fdt, offset, name, path)
+ node = Node(self._fdt, self, offset, name, path)
self.subnodes.append(node)
node.Scan()
def __init__(self, fname):
self._fname = fname
self._cached_offsets = False
+ self.phandle_to_node = {}
if self._fname:
self._fname = fdt_util.EnsureCompiled(self._fname)
TODO(sjg@chromium.org): Implement the 'root' parameter
"""
- self._root = self.Node(self, 0, '/', '/')
+ self._root = self.Node(self, None, 0, '/', '/')
self._root.Scan()
def GetRoot(self):
return libfdt.fdt_off_dt_struct(self._fdt) + offset
@classmethod
- def Node(self, fdt, offset, name, path):
+ def Node(self, fdt, parent, offset, name, path):
"""Create a new node
This is used by Fdt.Scan() to create a new node using the correct
Args:
fdt: Fdt object
+ parent: Parent node, or None if this is the root node
offset: Offset of node
name: Node name
path: Full path to node
"""
- node = Node(fdt, offset, name, path)
+ node = Node(fdt, parent, offset, name, path)
return node
def FdtScan(fname):
val = val.encode('raw_unicode_escape')
return struct.unpack('>I', val)[0]
+def fdt_cells_to_cpu(val, cells):
+ """Convert one or two cells to a long integer
+
+ Args:
+ Value to convert (array of one or more 4-character strings)
+
+ Return:
+ A native-endian long value
+ """
+ if not cells:
+ return 0
+ out = long(fdt32_to_cpu(val[0]))
+ if cells == 2:
+ out = out << 32 | fdt32_to_cpu(val[1])
+ return out
+
def EnsureCompiled(fname):
"""Compile an fdt .dts source file into a .dtb binary blob if needed.
data = infile.read()
self.assertEqual('''#include <stdbool.h>
#include <libfdt.h>
+struct dtd_sandbox_i2c_test {
+};
+struct dtd_sandbox_pmic_test {
+\tbool\t\tlow_power;
+\tfdt64_t\t\treg[2];
+};
struct dtd_sandbox_spl_test {
\tbool\t\tboolval;
\tunsigned char\tbytearray[3];
\t.bytearray\t\t= {0x6, 0x0, 0x0},
\t.byteval\t\t= 0x5,
\t.intval\t\t\t= 0x1,
-\t.longbytearray\t\t= {0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x10, 0x11},
+\t.longbytearray\t\t= {0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x10,
+\t\t0x11},
\t.stringval\t\t= "message",
\t.boolval\t\t= true,
\t.intarray\t\t= {0x2, 0x3, 0x4, 0x0},
\t.bytearray\t\t= {0x1, 0x23, 0x34},
\t.byteval\t\t= 0x8,
\t.intval\t\t\t= 0x3,
-\t.longbytearray\t\t= {0x9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
+\t.longbytearray\t\t= {0x9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+\t\t0x0},
\t.stringval\t\t= "message2",
\t.intarray\t\t= {0x5, 0x0, 0x0, 0x0},
\t.stringarray\t\t= {"another", "multi-word", "message"},
\t.platdata_size\t= sizeof(dtv_spl_test4),
};
+static struct dtd_sandbox_i2c_test dtv_i2c_at_0 = {
+};
+U_BOOT_DEVICE(i2c_at_0) = {
+\t.name\t\t= "sandbox_i2c_test",
+\t.platdata\t= &dtv_i2c_at_0,
+\t.platdata_size\t= sizeof(dtv_i2c_at_0),
+};
+
+static struct dtd_sandbox_pmic_test dtv_pmic_at_9 = {
+\t.low_power\t\t= true,
+\t.reg\t\t\t= {0x9, 0x0},
+};
+U_BOOT_DEVICE(pmic_at_9) = {
+\t.name\t\t= "sandbox_pmic_test",
+\t.platdata\t= &dtv_pmic_at_9,
+\t.platdata_size\t= sizeof(dtv_pmic_at_9),
+};
+
''', data)
def test_phandle(self):
self.assertEqual('''#include <stdbool.h>
#include <libfdt.h>
struct dtd_source {
-\tstruct phandle_2_cell clocks[1];
+\tstruct phandle_2_arg clocks[4];
};
struct dtd_target {
\tfdt32_t\t\tintval;
#include <dt-structs.h>
static struct dtd_target dtv_phandle_target = {
-\t.intval\t\t\t= 0x1,
+\t.intval\t\t\t= 0x0,
};
U_BOOT_DEVICE(phandle_target) = {
\t.name\t\t= "target",
\t.platdata_size\t= sizeof(dtv_phandle_target),
};
+static struct dtd_target dtv_phandle2_target = {
+\t.intval\t\t\t= 0x1,
+};
+U_BOOT_DEVICE(phandle2_target) = {
+\t.name\t\t= "target",
+\t.platdata\t= &dtv_phandle2_target,
+\t.platdata_size\t= sizeof(dtv_phandle2_target),
+};
+
+static struct dtd_target dtv_phandle3_target = {
+\t.intval\t\t\t= 0x2,
+};
+U_BOOT_DEVICE(phandle3_target) = {
+\t.name\t\t= "target",
+\t.platdata\t= &dtv_phandle3_target,
+\t.platdata_size\t= sizeof(dtv_phandle3_target),
+};
+
static struct dtd_source dtv_phandle_source = {
-\t.clocks\t\t\t= {{&dtv_phandle_target, 1}},
+\t.clocks\t\t\t= {
+\t\t\t{&dtv_phandle_target, {}},
+\t\t\t{&dtv_phandle2_target, {11}},
+\t\t\t{&dtv_phandle3_target, {12, 13}},
+\t\t\t{&dtv_phandle_target, {}},},
};
U_BOOT_DEVICE(phandle_source) = {
\t.name\t\t= "source",
\t.platdata_size\t= sizeof(dtv_spl_test),
};
+''', data)
+
+ def test_addresses64(self):
+ """Test output from a node with a 'reg' property with na=2, ns=2"""
+ dtb_file = get_dtb_file('dtoc_test_addr64.dts')
+ output = tools.GetOutputFilename('output')
+ dtb_platdata.run_steps(['struct'], dtb_file, False, output)
+ with open(output) as infile:
+ data = infile.read()
+ self.assertEqual('''#include <stdbool.h>
+#include <libfdt.h>
+struct dtd_test1 {
+\tfdt64_t\t\treg[2];
+};
+struct dtd_test2 {
+\tfdt64_t\t\treg[2];
+};
+struct dtd_test3 {
+\tfdt64_t\t\treg[4];
+};
+''', data)
+
+ dtb_platdata.run_steps(['platdata'], dtb_file, False, output)
+ with open(output) as infile:
+ data = infile.read()
+ self.assertEqual('''#include <common.h>
+#include <dm.h>
+#include <dt-structs.h>
+
+static struct dtd_test1 dtv_test1 = {
+\t.reg\t\t\t= {0x1234, 0x5678},
+};
+U_BOOT_DEVICE(test1) = {
+\t.name\t\t= "test1",
+\t.platdata\t= &dtv_test1,
+\t.platdata_size\t= sizeof(dtv_test1),
+};
+
+static struct dtd_test2 dtv_test2 = {
+\t.reg\t\t\t= {0x1234567890123456, 0x9876543210987654},
+};
+U_BOOT_DEVICE(test2) = {
+\t.name\t\t= "test2",
+\t.platdata\t= &dtv_test2,
+\t.platdata_size\t= sizeof(dtv_test2),
+};
+
+static struct dtd_test3 dtv_test3 = {
+\t.reg\t\t\t= {0x1234567890123456, 0x9876543210987654, 0x2, 0x3},
+};
+U_BOOT_DEVICE(test3) = {
+\t.name\t\t= "test3",
+\t.platdata\t= &dtv_test3,
+\t.platdata_size\t= sizeof(dtv_test3),
+};
+
+''', data)
+
+ def test_addresses32(self):
+ """Test output from a node with a 'reg' property with na=1, ns=1"""
+ dtb_file = get_dtb_file('dtoc_test_addr32.dts')
+ output = tools.GetOutputFilename('output')
+ dtb_platdata.run_steps(['struct'], dtb_file, False, output)
+ with open(output) as infile:
+ data = infile.read()
+ self.assertEqual('''#include <stdbool.h>
+#include <libfdt.h>
+struct dtd_test1 {
+\tfdt32_t\t\treg[2];
+};
+struct dtd_test2 {
+\tfdt32_t\t\treg[4];
+};
+''', data)
+
+ dtb_platdata.run_steps(['platdata'], dtb_file, False, output)
+ with open(output) as infile:
+ data = infile.read()
+ self.assertEqual('''#include <common.h>
+#include <dm.h>
+#include <dt-structs.h>
+
+static struct dtd_test1 dtv_test1 = {
+\t.reg\t\t\t= {0x1234, 0x5678},
+};
+U_BOOT_DEVICE(test1) = {
+\t.name\t\t= "test1",
+\t.platdata\t= &dtv_test1,
+\t.platdata_size\t= sizeof(dtv_test1),
+};
+
+static struct dtd_test2 dtv_test2 = {
+\t.reg\t\t\t= {0x12345678, 0x98765432, 0x2, 0x3},
+};
+U_BOOT_DEVICE(test2) = {
+\t.name\t\t= "test2",
+\t.platdata\t= &dtv_test2,
+\t.platdata_size\t= sizeof(dtv_test2),
+};
+
+''', data)
+
+ def test_addresses64_32(self):
+ """Test output from a node with a 'reg' property with na=2, ns=1"""
+ dtb_file = get_dtb_file('dtoc_test_addr64_32.dts')
+ output = tools.GetOutputFilename('output')
+ dtb_platdata.run_steps(['struct'], dtb_file, False, output)
+ with open(output) as infile:
+ data = infile.read()
+ self.assertEqual('''#include <stdbool.h>
+#include <libfdt.h>
+struct dtd_test1 {
+\tfdt64_t\t\treg[2];
+};
+struct dtd_test2 {
+\tfdt64_t\t\treg[2];
+};
+struct dtd_test3 {
+\tfdt64_t\t\treg[4];
+};
+''', data)
+
+ dtb_platdata.run_steps(['platdata'], dtb_file, False, output)
+ with open(output) as infile:
+ data = infile.read()
+ self.assertEqual('''#include <common.h>
+#include <dm.h>
+#include <dt-structs.h>
+
+static struct dtd_test1 dtv_test1 = {
+\t.reg\t\t\t= {0x123400000000, 0x5678},
+};
+U_BOOT_DEVICE(test1) = {
+\t.name\t\t= "test1",
+\t.platdata\t= &dtv_test1,
+\t.platdata_size\t= sizeof(dtv_test1),
+};
+
+static struct dtd_test2 dtv_test2 = {
+\t.reg\t\t\t= {0x1234567890123456, 0x98765432},
+};
+U_BOOT_DEVICE(test2) = {
+\t.name\t\t= "test2",
+\t.platdata\t= &dtv_test2,
+\t.platdata_size\t= sizeof(dtv_test2),
+};
+
+static struct dtd_test3 dtv_test3 = {
+\t.reg\t\t\t= {0x1234567890123456, 0x98765432, 0x2, 0x3},
+};
+U_BOOT_DEVICE(test3) = {
+\t.name\t\t= "test3",
+\t.platdata\t= &dtv_test3,
+\t.platdata_size\t= sizeof(dtv_test3),
+};
+
+''', data)
+
+ def test_addresses32_64(self):
+ """Test output from a node with a 'reg' property with na=1, ns=2"""
+ dtb_file = get_dtb_file('dtoc_test_addr32_64.dts')
+ output = tools.GetOutputFilename('output')
+ dtb_platdata.run_steps(['struct'], dtb_file, False, output)
+ with open(output) as infile:
+ data = infile.read()
+ self.assertEqual('''#include <stdbool.h>
+#include <libfdt.h>
+struct dtd_test1 {
+\tfdt64_t\t\treg[2];
+};
+struct dtd_test2 {
+\tfdt64_t\t\treg[2];
+};
+struct dtd_test3 {
+\tfdt64_t\t\treg[4];
+};
+''', data)
+
+ dtb_platdata.run_steps(['platdata'], dtb_file, False, output)
+ with open(output) as infile:
+ data = infile.read()
+ self.assertEqual('''#include <common.h>
+#include <dm.h>
+#include <dt-structs.h>
+
+static struct dtd_test1 dtv_test1 = {
+\t.reg\t\t\t= {0x1234, 0x567800000000},
+};
+U_BOOT_DEVICE(test1) = {
+\t.name\t\t= "test1",
+\t.platdata\t= &dtv_test1,
+\t.platdata_size\t= sizeof(dtv_test1),
+};
+
+static struct dtd_test2 dtv_test2 = {
+\t.reg\t\t\t= {0x12345678, 0x9876543210987654},
+};
+U_BOOT_DEVICE(test2) = {
+\t.name\t\t= "test2",
+\t.platdata\t= &dtv_test2,
+\t.platdata_size\t= sizeof(dtv_test2),
+};
+
+static struct dtd_test3 dtv_test3 = {
+\t.reg\t\t\t= {0x12345678, 0x9876543210987654, 0x2, 0x3},
+};
+U_BOOT_DEVICE(test3) = {
+\t.name\t\t= "test3",
+\t.platdata\t= &dtv_test3,
+\t.platdata_size\t= sizeof(dtv_test3),
+};
+
''', data)
os.environ['srctree'] = os.getcwd()
os.environ['UBOOTVERSION'] = 'dummy'
os.environ['KCONFIG_OBJDIR'] = ''
- self._conf = kconfiglib.Config()
+ self._conf = kconfiglib.Config(print_warnings=False)
def __del__(self):
"""Delete a leftover temporary file before exit.
else:
f.write(line[colon + 1:])
- self._conf.load_config(self._tmpfile)
+ warnings = self._conf.load_config(self._tmpfile)
+ if warnings:
+ for warning in warnings:
+ print '%s: %s' % (defconfig, warning)
try_remove(self._tmpfile)
self._tmpfile = None
if options.build_db:
with open(CONFIG_DATABASE, 'w') as fd:
for defconfig, configs in config_db.iteritems():
- print >>fd, '%s' % defconfig
+ fd.write('%s\n' % defconfig)
for config in sorted(configs.keys()):
- print >>fd, ' %s=%s' % (config, configs[config])
- print >>fd
+ fd.write(' %s=%s\n' % (config, configs[config]))
+ fd.write('\n')
if __name__ == '__main__':
main()
The checkpatch.pl in the U-Boot tools/ subdirectory will be located and
used. Failing that you can put it into your path or ~/bin/checkpatch.pl
+If you want to avoid sending patches to email addresses that are picked up
+by patman but are known to bounce you can add a [bounces] section to your
+.patman file. Unlike the [alias] section these are simple key: value pairs
+that are not recursive.
+
+>>>
+
+[bounces]
+gonefishing: Fred Bloggs <f.bloggs@napier.net>
+
+<<<
+
If you want to change the defaults for patman's command-line arguments,
you can add a [settings] section to your .patman file. This can be used
import get_maintainer
import gitutil
+import settings
import terminal
# Series-xxx tags that we understand
Return:
Filename of temp file created
"""
+ col = terminal.Color()
# Look for commit tags (of the form 'xxx:' at the start of the subject)
fname = '/tmp/patman.%d' % os.getpid()
fd = open(fname, 'w')
cc += add_maintainers
elif add_maintainers:
cc += get_maintainer.GetMaintainer(commit.patch)
+ for x in set(cc) & set(settings.bounces):
+ print(col.Color(col.YELLOW, 'Skipping "%s"' % x))
+ cc = set(cc) - set(settings.bounces)
cc = [m.encode('utf-8') if type(m) != str else m for m in cc]
all_ccs += cc
print(commit.patch, ', '.join(set(cc)), file=fd)
print("Couldn't create patman config file\n")
raise
- print("[alias]\nme: %s <%s>" % (name, email), file=f)
+ print('''[alias]
+me: %s <%s>
+
+[bounces]
+nxp = Zhikang Zhang <zhikang.zhang@nxp.com>
+''' % (name, email), file=f)
f.close();
def _UpdateDefaults(parser, config):
if bad_line:
print(bad_line)
+def _ReadBouncesFile(fname):
+ """Read in the bounces file if it exists
+
+ Args:
+ fname: Filename to read.
+ """
+ if os.path.exists(fname):
+ with open(fname) as fd:
+ for line in fd:
+ if line.startswith('#'):
+ continue
+ bounces.add(line.strip())
+
+def GetItems(config, section):
+ """Get the items from a section of the config.
+
+ Args:
+ config: _ProjectConfigParser object containing settings
+ section: name of section to retrieve
+
+ Returns:
+ List of (name, value) tuples for the section
+ """
+ try:
+ return config.items(section)
+ except ConfigParser.NoSectionError as e:
+ return []
+ except:
+ raise
+
def Setup(parser, project_name, config_fname=''):
"""Set up the settings module by reading config files.
config.read(config_fname)
- for name, value in config.items('alias'):
+ for name, value in GetItems(config, 'alias'):
alias[name] = value.split(',')
+ _ReadBouncesFile('doc/bounces')
+ for name, value in GetItems(config, 'bounces'):
+ bounces.add(value)
+
_UpdateDefaults(parser, config)
# These are the aliases we understand, indexed by alias. Each member is a list.
alias = {}
+bounces = set()
if __name__ == "__main__":
import doctest
pbi_crc_cmd2 = 0;
pbl_cmd_initaddr = params->addr & PBL_ADDR_24BIT_MASK;
pbl_cmd_initaddr |= PBL_ACS_CONT_CMD;
- pbl_cmd_initaddr |= uboot_size;
+ pbl_cmd_initaddr += uboot_size;
pbl_end_cmd[0] = 0x09610000;
pbl_end_cmd[1] = 0x00000000;
pbl_end_cmd[2] = 0x096100c0;
projects / u-boot / commitdiff
