--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm320518_eval.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides:\r
+ * - set of firmware functions to manage Leds, push-button and COM ports\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+ \r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm320518_eval.h"\r
+\r
+/** @addtogroup Utilities\r
+ * @{\r
+ */ \r
+\r
+/** @addtogroup STM32_EVAL\r
+ * @{\r
+ */ \r
+\r
+/** @addtogroup STM320518_EVAL\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup STM320518_EVAL_LOW_LEVEL \r
+ * @brief This file provides firmware functions to manage Leds, push-buttons, \r
+ * COM ports, SD card on SPI and temperature sensor (LM75) available on \r
+ * STM320518-EVAL evaluation board from STMicroelectronics.\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup STM320518_EVAL_LOW_LEVEL_Private_TypesDefinitions\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup STM320518_EVAL_LOW_LEVEL_Private_Defines\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup STM320518_EVAL_LOW_LEVEL_Private_Macros\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup STM320518_EVAL_LOW_LEVEL_Private_Variables\r
+ * @{\r
+ */ \r
+GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,\r
+ LED4_GPIO_PORT};\r
+const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,\r
+ LED4_PIN};\r
+const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,\r
+ LED4_GPIO_CLK};\r
+\r
+GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {TAMPER_BUTTON_GPIO_PORT, KEY_BUTTON_GPIO_PORT, \r
+ RIGHT_BUTTON_GPIO_PORT, LEFT_BUTTON_GPIO_PORT, \r
+ UP_BUTTON_GPIO_PORT, DOWN_BUTTON_GPIO_PORT, \r
+ SEL_BUTTON_GPIO_PORT}; \r
+\r
+const uint16_t BUTTON_PIN[BUTTONn] = {TAMPER_BUTTON_PIN, KEY_BUTTON_PIN, \r
+ RIGHT_BUTTON_PIN, LEFT_BUTTON_PIN, \r
+ UP_BUTTON_PIN, DOWN_BUTTON_PIN, \r
+ SEL_BUTTON_PIN}; \r
+\r
+const uint32_t BUTTON_CLK[BUTTONn] = {TAMPER_BUTTON_GPIO_CLK, KEY_BUTTON_GPIO_CLK, \r
+ RIGHT_BUTTON_GPIO_CLK, LEFT_BUTTON_GPIO_CLK, \r
+ UP_BUTTON_GPIO_CLK, DOWN_BUTTON_GPIO_CLK, \r
+ SEL_BUTTON_GPIO_CLK};\r
+\r
+const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {TAMPER_BUTTON_EXTI_LINE, \r
+ KEY_BUTTON_EXTI_LINE,\r
+ RIGHT_BUTTON_EXTI_LINE,\r
+ LEFT_BUTTON_EXTI_LINE,\r
+ UP_BUTTON_EXTI_LINE,\r
+ DOWN_BUTTON_EXTI_LINE,\r
+ SEL_BUTTON_EXTI_LINE};\r
+\r
+const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {TAMPER_BUTTON_EXTI_PORT_SOURCE, \r
+ KEY_BUTTON_EXTI_PORT_SOURCE,\r
+ RIGHT_BUTTON_EXTI_PORT_SOURCE,\r
+ LEFT_BUTTON_EXTI_PORT_SOURCE,\r
+ UP_BUTTON_EXTI_PORT_SOURCE,\r
+ DOWN_BUTTON_EXTI_PORT_SOURCE,\r
+ SEL_BUTTON_EXTI_PORT_SOURCE};\r
+ \r
+const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {TAMPER_BUTTON_EXTI_PIN_SOURCE, \r
+ KEY_BUTTON_EXTI_PIN_SOURCE,\r
+ RIGHT_BUTTON_EXTI_PIN_SOURCE,\r
+ LEFT_BUTTON_EXTI_PIN_SOURCE,\r
+ UP_BUTTON_EXTI_PIN_SOURCE,\r
+ DOWN_BUTTON_EXTI_PIN_SOURCE,\r
+ SEL_BUTTON_EXTI_PIN_SOURCE}; \r
+\r
+const uint16_t BUTTON_IRQn[BUTTONn] = {TAMPER_BUTTON_EXTI_IRQn, KEY_BUTTON_EXTI_IRQn, \r
+ RIGHT_BUTTON_EXTI_IRQn, LEFT_BUTTON_EXTI_IRQn, \r
+ UP_BUTTON_EXTI_IRQn, DOWN_BUTTON_EXTI_IRQn, \r
+ SEL_BUTTON_EXTI_IRQn};\r
+\r
+USART_TypeDef* COM_USART[COMn] = {EVAL_COM1}; \r
+\r
+GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT};\r
+ \r
+GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT};\r
+\r
+const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK};\r
+\r
+const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK};\r
+ \r
+const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK};\r
+\r
+const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN};\r
+\r
+const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN};\r
+ \r
+const uint16_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE};\r
+\r
+const uint16_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE};\r
+ \r
+const uint16_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF};\r
+ \r
+const uint16_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF};\r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup STM320518_EVAL_LOW_LEVEL_Private_FunctionPrototypes\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup STM320518_EVAL_LOW_LEVEL_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Configures LED GPIO.\r
+ * @param Led: Specifies the Led to be configured. \r
+ * This parameter can be one of following parameters:\r
+ * @arg LED1\r
+ * @arg LED2\r
+ * @arg LED3\r
+ * @arg LED4\r
+ * @retval None\r
+ */\r
+void STM_EVAL_LEDInit(Led_TypeDef Led)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+ \r
+ /* Enable the GPIO_LED Clock */\r
+ RCC_AHBPeriphClockCmd(GPIO_CLK[Led], ENABLE);\r
+\r
+ /* Configure the GPIO_LED pin */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r
+ GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);\r
+ GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];\r
+}\r
+\r
+/**\r
+ * @brief Turns selected LED On.\r
+ * @param Led: Specifies the Led to be set on. \r
+ * This parameter can be one of following parameters:\r
+ * @arg LED1\r
+ * @arg LED2\r
+ * @arg LED3\r
+ * @arg LED4 \r
+ * @retval None\r
+ */\r
+void STM_EVAL_LEDOn(Led_TypeDef Led)\r
+{\r
+ GPIO_PORT[Led]->BRR = GPIO_PIN[Led];\r
+}\r
+\r
+/**\r
+ * @brief Turns selected LED Off.\r
+ * @param Led: Specifies the Led to be set off. \r
+ * This parameter can be one of following parameters:\r
+ * @arg LED1\r
+ * @arg LED2\r
+ * @arg LED3\r
+ * @arg LED4 \r
+ * @retval None\r
+ */\r
+void STM_EVAL_LEDOff(Led_TypeDef Led)\r
+{\r
+ GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];\r
+}\r
+\r
+/**\r
+ * @brief Toggles the selected LED.\r
+ * @param Led: Specifies the Led to be toggled. \r
+ * This parameter can be one of following parameters:\r
+ * @arg LED1\r
+ * @arg LED2\r
+ * @arg LED3\r
+ * @arg LED4 \r
+ * @retval None\r
+ */\r
+void STM_EVAL_LEDToggle(Led_TypeDef Led)\r
+{\r
+ GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];\r
+}\r
+\r
+/**\r
+ * @brief Configures Button GPIO and EXTI Line.\r
+ * @param Button: Specifies the Button to be configured.\r
+ * This parameter can be one of following parameters:\r
+ * @arg BUTTON_TAMPER: Tamper Push Button \r
+ * @arg BUTTON_KEY: Key Push Button\r
+ * @arg BUTTON_RIGHT: Joystick Right Push Button \r
+ * @arg BUTTON_LEFT: Joystick Left Push Button \r
+ * @arg BUTTON_UP: Joystick Up Push Button \r
+ * @arg BUTTON_DOWN: Joystick Down Push Button\r
+ * @arg BUTTON_SEL: Joystick Sel Push Button \r
+ * @param Button_Mode: Specifies Button mode.\r
+ * This parameter can be one of following parameters: \r
+ * @arg BUTTON_MODE_GPIO: Button will be used as simple IO \r
+ * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt\r
+ * generation capability\r
+ * @retval None\r
+ */\r
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+ EXTI_InitTypeDef EXTI_InitStructure;\r
+ NVIC_InitTypeDef NVIC_InitStructure;\r
+\r
+ /* Enable the BUTTON Clock */\r
+ RCC_AHBPeriphClockCmd(BUTTON_CLK[Button], ENABLE);\r
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+\r
+ /* Configure Button pin as input */\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+ GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];\r
+ GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);\r
+\r
+ if (Button_Mode == BUTTON_MODE_EXTI)\r
+ {\r
+ /* Connect Button EXTI Line to Button GPIO Pin */\r
+ SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);\r
+\r
+ /* Configure Button EXTI line */\r
+ EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];\r
+ EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;\r
+ if ((Button != BUTTON_TAMPER) && (Button != BUTTON_KEY))\r
+ {\r
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;\r
+ }\r
+ else\r
+ {\r
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; \r
+ }\r
+ EXTI_InitStructure.EXTI_LineCmd = ENABLE;\r
+ EXTI_Init(&EXTI_InitStructure);\r
+\r
+ /* Enable and set Button EXTI Interrupt to the lowest priority */\r
+ NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];\r
+ NVIC_InitStructure.NVIC_IRQChannelPriority = 0x03;\r
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+\r
+ NVIC_Init(&NVIC_InitStructure); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the selected Button state.\r
+ * @param Button: Specifies the Button to be checked.\r
+ * This parameter can be one of following parameters:\r
+ * @arg BUTTON_TAMPER: Tamper Push Button \r
+ * @arg BUTTON_KEY: Key Push Button \r
+ * @arg BUTTON_RIGHT: Joystick Right Push Button \r
+ * @arg BUTTON_LEFT: Joystick Left Push Button \r
+ * @arg BUTTON_UP: Joystick Up Push Button \r
+ * @arg BUTTON_DOWN: Joystick Down Push Button\r
+ * @arg BUTTON_SEL: Joystick Sel Push Button \r
+ * @retval The Button GPIO pin value.\r
+ */\r
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)\r
+{\r
+ /* There is no Wakeup button on STM320518-EVAL. */\r
+ return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);\r
+}\r
+\r
+/**\r
+ * @brief Configures COM port.\r
+ * @param COM: Specifies the COM port to be configured.\r
+ * This parameter can be one of following parameters: \r
+ * @arg COM1\r
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that\r
+ * contains the configuration information for the specified USART peripheral.\r
+ * @retval None\r
+ */\r
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+ /* Enable GPIO clock */\r
+ RCC_AHBPeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM], ENABLE);\r
+\r
+ /* Enable USART clock */\r
+ RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE); \r
+\r
+ /* Connect PXx to USARTx_Tx */\r
+ GPIO_PinAFConfig(COM_TX_PORT[COM], COM_TX_PIN_SOURCE[COM], COM_TX_AF[COM]);\r
+\r
+ /* Connect PXx to USARTx_Rx */\r
+ GPIO_PinAFConfig(COM_RX_PORT[COM], COM_RX_PIN_SOURCE[COM], COM_RX_AF[COM]);\r
+ \r
+ /* Configure USART Tx as alternate function push-pull */\r
+ GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r
+ GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);\r
+ \r
+ /* Configure USART Rx as alternate function push-pull */\r
+ GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];\r
+ GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);\r
+\r
+ /* USART configuration */\r
+ USART_Init(COM_USART[COM], USART_InitStruct);\r
+ \r
+ /* Enable USART */\r
+ USART_Cmd(COM_USART[COM], ENABLE);\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the SPI interface.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SD_LowLevel_DeInit(void)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+ \r
+ SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */\r
+ SPI_I2S_DeInit(SD_SPI); /*!< DeInitializes the SD_SPI */\r
+ \r
+ /*!< SD_SPI Periph clock disable */\r
+ RCC_APB2PeriphClockCmd(SD_SPI_CLK, DISABLE); \r
+\r
+ /*!< Configure SD_SPI pins: SCK */\r
+ GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+ GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+ /*!< Configure SD_SPI pins: MISO */\r
+ GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;\r
+ GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+ /*!< Configure SD_SPI pins: MOSI */\r
+ GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;\r
+ GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+ /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */\r
+ GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;\r
+ GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+ /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */\r
+ GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;\r
+ GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SD Card and put it into StandBy State (Ready for \r
+ * data transfer).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SD_LowLevel_Init(void)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+ SPI_InitTypeDef SPI_InitStructure;\r
+\r
+ /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO \r
+ and SD_SPI_SCK_GPIO Periph clock enable */\r
+ RCC_AHBPeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |\r
+ SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);\r
+\r
+ /*!< SD_SPI Periph clock enable */\r
+ RCC_APB2PeriphClockCmd(SD_SPI_CLK, ENABLE); \r
+\r
+ /*!< Configure SD_SPI pins: SCK */\r
+ GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r
+ GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+ /*!< Configure SD_SPI pins: MISO */\r
+ GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;\r
+ GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+ /*!< Configure SD_SPI pins: MOSI */\r
+ GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;\r
+ GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+ /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */\r
+ GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r
+ GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+ /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */\r
+ GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r
+ GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+ /* Connect PXx to SD_SPI_SCK */\r
+ GPIO_PinAFConfig(SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_SOURCE, SD_SPI_SCK_AF);\r
+\r
+ /* Connect PXx to SD_SPI_MISO */\r
+ GPIO_PinAFConfig(SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_SOURCE, SD_SPI_MISO_AF); \r
+\r
+ /* Connect PXx to SD_SPI_MOSI */\r
+ GPIO_PinAFConfig(SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_SOURCE, SD_SPI_MOSI_AF); \r
+ \r
+ /*!< SD_SPI Config */\r
+ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+ SPI_InitStructure.SPI_Mode = SPI_Mode_Master;\r
+ SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;\r
+ SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;\r
+ SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;\r
+ SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;\r
+ SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+\r
+ SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;\r
+ SPI_InitStructure.SPI_CRCPolynomial = 7;\r
+ SPI_Init(SD_SPI, &SPI_InitStructure);\r
+ \r
+ SPI_RxFIFOThresholdConfig(SD_SPI, SPI_RxFIFOThreshold_QF);\r
+ \r
+ SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the LM75_I2C.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LM75_LowLevel_DeInit(void)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+ /*!< Disable LM75_I2C */\r
+ I2C_Cmd(LM75_I2C, DISABLE);\r
+ \r
+ /*!< DeInitializes the LM75_I2C */\r
+ I2C_DeInit(LM75_I2C);\r
+ \r
+ /*!< LM75_I2C Periph clock disable */\r
+ RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);\r
+ \r
+ /*!< Configure LM75_I2C pins: SCL */\r
+ GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+ GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+ /*!< Configure LM75_I2C pins: SDA */\r
+ GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;\r
+ GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+ /*!< Configure LM75_I2C pin: SMBUS ALERT */\r
+ GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;\r
+ GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the LM75_I2C..\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void LM75_LowLevel_Init(void)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+ /*!< LM75_I2C Periph clock enable */\r
+ RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);\r
+ \r
+ /* Configure the I2C clock source. The clock is derived from the HSI */\r
+ RCC_I2CCLKConfig(RCC_I2C1CLK_HSI);\r
+ \r
+ /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK \r
+ and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */\r
+ RCC_AHBPeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |\r
+ LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);\r
+ \r
+ /* Connect PXx to I2C_SCL */\r
+ GPIO_PinAFConfig(LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_SOURCE, LM75_I2C_SCL_AF);\r
+\r
+ /* Connect PXx to I2C_SDA */\r
+ GPIO_PinAFConfig(LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_SOURCE, LM75_I2C_SDA_AF); \r
+\r
+ /* Connect PXx to I2C_SMBUSALER */\r
+ GPIO_PinAFConfig(LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_SOURCE, LM75_I2C_SMBUSALERT_AF);\r
+ \r
+ /*!< Configure LM75_I2C pins: SCL */\r
+ GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+ GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+ /*!< Configure LM75_I2C pins: SDA */\r
+ GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;\r
+ GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+ /*!< Configure LM75_I2C pin: SMBUS ALERT */\r
+ GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;\r
+ GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes peripherals used by the I2C EEPROM driver.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void sEE_LowLevel_DeInit(void)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure; \r
+ \r
+ /* sEE_I2C Peripheral Disable */\r
+ I2C_Cmd(sEE_I2C, DISABLE);\r
+ \r
+ /* sEE_I2C DeInit */\r
+ I2C_DeInit(sEE_I2C);\r
+\r
+ /*!< sEE_I2C Periph clock disable */\r
+ RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE);\r
+ \r
+ /*!< GPIO configuration */ \r
+ /*!< Configure sEE_I2C pins: SCL */\r
+ GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+ GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+ GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+ /*!< Configure sEE_I2C pins: SDA */\r
+ GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;\r
+ GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);\r
+}\r
+\r
+/**\r
+ * @brief Initializes peripherals used by the I2C EEPROM driver.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void sEE_LowLevel_Init(void)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+ \r
+ /* Configure the I2C clock source. The clock is derived from the HSI */\r
+ RCC_I2CCLKConfig(RCC_I2C1CLK_HSI);\r
+ \r
+ /*!< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */\r
+ RCC_AHBPeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE);\r
+ \r
+ /*!< sEE_I2C Periph clock enable */\r
+ RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE);\r
+ \r
+ /* Connect PXx to I2C_SCL*/\r
+ GPIO_PinAFConfig(sEE_I2C_SCL_GPIO_PORT, sEE_I2C_SCL_SOURCE, sEE_I2C_SCL_AF);\r
+ \r
+ /* Connect PXx to I2C_SDA*/\r
+ GPIO_PinAFConfig(sEE_I2C_SDA_GPIO_PORT, sEE_I2C_SDA_SOURCE, sEE_I2C_SDA_AF);\r
+ \r
+ /*!< GPIO configuration */ \r
+ /*!< Configure sEE_I2C pins: SCL */\r
+ GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r
+ GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;\r
+ GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);\r
+ \r
+ /*!< Configure sEE_I2C pins: SDA */\r
+ GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;\r
+ GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm320518_eval.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains definitions for STM320518_EVAL's Leds, push-buttons\r
+ * and COM ports hardware resources.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+ \r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM320518_EVAL_H\r
+#define __STM320518_EVAL_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+#include "stm32_eval_legacy.h"\r
+\r
+/** @addtogroup Utilities\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM32_EVAL\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup STM320518_EVAL\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup STM320518_EVAL_LOW_LEVEL\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup STM320518_EVAL_LOW_LEVEL_Exported_Types\r
+ * @{\r
+ */\r
+typedef enum \r
+{\r
+ LED1 = 0,\r
+ LED2 = 1,\r
+ LED3 = 2,\r
+ LED4 = 3\r
+} Led_TypeDef;\r
+\r
+typedef enum \r
+{\r
+ BUTTON_TAMPER = 0,\r
+ BUTTON_KEY = 1,\r
+ BUTTON_RIGHT = 2,\r
+ BUTTON_LEFT = 3,\r
+ BUTTON_UP = 4,\r
+ BUTTON_DOWN = 5,\r
+ BUTTON_SEL = 6\r
+} Button_TypeDef;\r
+\r
+typedef enum \r
+{ \r
+ BUTTON_MODE_GPIO = 0,\r
+ BUTTON_MODE_EXTI = 1\r
+} ButtonMode_TypeDef;\r
+\r
+typedef enum \r
+{ \r
+ JOY_NONE = 0,\r
+ JOY_SEL = 1,\r
+ JOY_DOWN = 2,\r
+ JOY_LEFT = 3,\r
+ JOY_RIGHT = 4,\r
+ JOY_UP = 5\r
+} JOYState_TypeDef\r
+;\r
+\r
+typedef enum \r
+{\r
+ COM1 = 0,\r
+ COM2 = 1\r
+} COM_TypeDef; \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup STM320518_EVAL_LOW_LEVEL_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief Define for STM320518_EVAL board \r
+ */ \r
+#if !defined (USE_STM320518_EVAL)\r
+ #define USE_STM320518_EVAL\r
+#endif\r
+\r
+/** @addtogroup STM320518_EVAL_LOW_LEVEL_LED\r
+ * @{\r
+ */\r
+#define LEDn 4\r
+\r
+#define LED1_PIN GPIO_Pin_10\r
+#define LED1_GPIO_PORT GPIOC\r
+#define LED1_GPIO_CLK RCC_AHBPeriph_GPIOC\r
+ \r
+#define LED2_PIN GPIO_Pin_11\r
+#define LED2_GPIO_PORT GPIOC\r
+#define LED2_GPIO_CLK RCC_AHBPeriph_GPIOC\r
+ \r
+#define LED3_PIN GPIO_Pin_12\r
+#define LED3_GPIO_PORT GPIOC\r
+#define LED3_GPIO_CLK RCC_AHBPeriph_GPIOC\r
+ \r
+#define LED4_PIN GPIO_Pin_2\r
+#define LED4_GPIO_PORT GPIOD\r
+#define LED4_GPIO_CLK RCC_AHBPeriph_GPIOD\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @addtogroup STM320518_EVAL_LOW_LEVEL_BUTTON\r
+ * @{\r
+ */ \r
+#define BUTTONn 7\r
+\r
+/**\r
+ * @brief Tamper push-button\r
+ */\r
+#define TAMPER_BUTTON_PIN GPIO_Pin_13\r
+#define TAMPER_BUTTON_GPIO_PORT GPIOC\r
+#define TAMPER_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOC\r
+#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13\r
+#define TAMPER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC\r
+#define TAMPER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource13\r
+#define TAMPER_BUTTON_EXTI_IRQn EXTI4_15_IRQn \r
+\r
+/**\r
+ * @brief Key push-button\r
+ */\r
+#define KEY_BUTTON_PIN GPIO_Pin_8\r
+#define KEY_BUTTON_GPIO_PORT GPIOB\r
+#define KEY_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOB\r
+#define KEY_BUTTON_EXTI_LINE EXTI_Line8\r
+#define KEY_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOB\r
+#define KEY_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource8\r
+#define KEY_BUTTON_EXTI_IRQn EXTI4_15_IRQn\r
+\r
+/**\r
+ * @brief Joystick Right push-button\r
+ */\r
+#define RIGHT_BUTTON_PIN GPIO_Pin_8\r
+#define RIGHT_BUTTON_GPIO_PORT GPIOC\r
+#define RIGHT_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOC\r
+#define RIGHT_BUTTON_EXTI_LINE EXTI_Line8\r
+#define RIGHT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC\r
+#define RIGHT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource8\r
+#define RIGHT_BUTTON_EXTI_IRQn EXTI4_15_IRQn\r
+\r
+/**\r
+ * @brief Joystick Left push-button\r
+ */\r
+#define LEFT_BUTTON_PIN GPIO_Pin_9\r
+#define LEFT_BUTTON_GPIO_PORT GPIOC\r
+#define LEFT_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOC\r
+#define LEFT_BUTTON_EXTI_LINE EXTI_Line9\r
+#define LEFT_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC\r
+#define LEFT_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource9\r
+#define LEFT_BUTTON_EXTI_IRQn EXTI4_15_IRQn \r
+\r
+/**\r
+ * @brief Joystick Up push-button\r
+ */\r
+#define UP_BUTTON_PIN GPIO_Pin_6\r
+#define UP_BUTTON_GPIO_PORT GPIOC\r
+#define UP_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOC\r
+#define UP_BUTTON_EXTI_LINE EXTI_Line6\r
+#define UP_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC\r
+#define UP_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource6\r
+#define UP_BUTTON_EXTI_IRQn EXTI4_15_IRQn \r
+\r
+/**\r
+ * @brief Joystick Down push-button\r
+ */ \r
+#define DOWN_BUTTON_PIN GPIO_Pin_7\r
+#define DOWN_BUTTON_GPIO_PORT GPIOC\r
+#define DOWN_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOC\r
+#define DOWN_BUTTON_EXTI_LINE EXTI_Line7\r
+#define DOWN_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOC\r
+#define DOWN_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource7\r
+#define DOWN_BUTTON_EXTI_IRQn EXTI4_15_IRQn \r
+\r
+/**\r
+ * @brief Joystick Sel push-button\r
+ */\r
+#define SEL_BUTTON_PIN GPIO_Pin_0\r
+#define SEL_BUTTON_GPIO_PORT GPIOA\r
+#define SEL_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA\r
+#define SEL_BUTTON_EXTI_LINE EXTI_Line0\r
+#define SEL_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA\r
+#define SEL_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0\r
+#define SEL_BUTTON_EXTI_IRQn EXTI0_1_IRQn \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @addtogroup STM320518_EVAL_LOW_LEVEL_COM\r
+ * @{\r
+ */\r
+#define COMn 1\r
+\r
+/**\r
+ * @brief Definition for COM port1, connected to USART1\r
+ */ \r
+#define EVAL_COM1 USART1\r
+#define EVAL_COM1_CLK RCC_APB2Periph_USART1\r
+\r
+#define EVAL_COM1_TX_PIN GPIO_Pin_9\r
+#define EVAL_COM1_TX_GPIO_PORT GPIOA\r
+#define EVAL_COM1_TX_GPIO_CLK RCC_AHBPeriph_GPIOA\r
+#define EVAL_COM1_TX_SOURCE GPIO_PinSource9\r
+#define EVAL_COM1_TX_AF GPIO_AF_1\r
+\r
+#define EVAL_COM1_RX_PIN GPIO_Pin_10\r
+#define EVAL_COM1_RX_GPIO_PORT GPIOA\r
+#define EVAL_COM1_RX_GPIO_CLK RCC_AHBPeriph_GPIOA\r
+#define EVAL_COM1_RX_SOURCE GPIO_PinSource10\r
+#define EVAL_COM1_RX_AF GPIO_AF_1\r
+\r
+#define EVAL_COM1_CTS_PIN GPIO_Pin_11\r
+#define EVAL_COM1_CTS_GPIO_PORT GPIOA\r
+#define EVAL_COM1_CTS_GPIO_CLK RCC_AHBPeriph_GPIOA\r
+#define EVAL_COM1_CTS_SOURCE GPIO_PinSource11\r
+#define EVAL_COM1_CTS_AF GPIO_AF_1\r
+\r
+#define EVAL_COM1_RTS_PIN GPIO_Pin_12\r
+#define EVAL_COM1_RTS_GPIO_PORT GPIOA\r
+#define EVAL_COM1_RTS_GPIO_CLK RCC_AHBPeriph_GPIOA\r
+#define EVAL_COM1_RTS_SOURCE GPIO_PinSource12\r
+#define EVAL_COM1_RTS_AF GPIO_AF_1\r
+ \r
+#define EVAL_COM1_IRQn USART1_IRQn\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM320518_EVAL_LOW_LEVEL_SD_SPI\r
+ * @{\r
+ */\r
+/**\r
+ * @brief SD SPI Interface pins\r
+ */\r
+#define SD_SPI SPI1\r
+#define SD_SPI_CLK RCC_APB2Periph_SPI1\r
+\r
+#define SD_SPI_SCK_PIN GPIO_Pin_5 /* PA.05 */\r
+#define SD_SPI_SCK_GPIO_PORT GPIOA /* GPIOA */\r
+#define SD_SPI_SCK_GPIO_CLK RCC_AHBPeriph_GPIOA\r
+#define SD_SPI_SCK_SOURCE GPIO_PinSource5\r
+#define SD_SPI_SCK_AF GPIO_AF_0\r
+\r
+#define SD_SPI_MISO_PIN GPIO_Pin_6 /* PA.06 */\r
+#define SD_SPI_MISO_GPIO_PORT GPIOA /* GPIOA */\r
+#define SD_SPI_MISO_GPIO_CLK RCC_AHBPeriph_GPIOA\r
+#define SD_SPI_MISO_SOURCE GPIO_PinSource6\r
+#define SD_SPI_MISO_AF GPIO_AF_0\r
+\r
+#define SD_SPI_MOSI_PIN GPIO_Pin_7 /* PA.07 */\r
+#define SD_SPI_MOSI_GPIO_PORT GPIOA /* GPIOA */\r
+#define SD_SPI_MOSI_GPIO_CLK RCC_AHBPeriph_GPIOA\r
+#define SD_SPI_MOSI_SOURCE GPIO_PinSource7\r
+#define SD_SPI_MOSI_AF GPIO_AF_0\r
+\r
+#define SD_CS_PIN GPIO_Pin_5 /* PF.05 */\r
+#define SD_CS_GPIO_PORT GPIOF /* GPIOF */\r
+#define SD_CS_GPIO_CLK RCC_AHBPeriph_GPIOF\r
+\r
+ \r
+#define SD_DETECT_PIN GPIO_Pin_15 /* PB.15 */\r
+#define SD_DETECT_EXTI_LINE EXTI_Line15\r
+#define SD_DETECT_EXTI_PIN_SOURCE EXTI_PinSource15\r
+#define SD_DETECT_GPIO_PORT GPIOB /* GPIOB */\r
+#define SD_DETECT_GPIO_CLK RCC_AHBPeriph_GPIOB\r
+#define SD_DETECT_EXTI_PORT_SOURCE EXTI_PortSourceGPIOB\r
+#define SD_DETECT_EXTI_IRQn EXTI4_15_IRQn\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup STM320518_EVAL_LOW_LEVEL_TSENSOR_I2C\r
+ * @{\r
+ */\r
+/**\r
+ * @brief LM75 Temperature Sensor I2C Interface pins\r
+ */\r
+#define LM75_I2C I2C1\r
+#define LM75_I2C_CLK RCC_APB1Periph_I2C1\r
+\r
+#define LM75_I2C_SCL_PIN GPIO_Pin_6 /* PB.06 */\r
+#define LM75_I2C_SCL_GPIO_PORT GPIOB /* GPIOB */\r
+#define LM75_I2C_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB\r
+#define LM75_I2C_SCL_SOURCE GPIO_PinSource6\r
+#define LM75_I2C_SCL_AF GPIO_AF_1\r
+\r
+#define LM75_I2C_SDA_PIN GPIO_Pin_7 /* PB.07 */\r
+#define LM75_I2C_SDA_GPIO_PORT GPIOB /* GPIOB */\r
+#define LM75_I2C_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB\r
+#define LM75_I2C_SDA_SOURCE GPIO_PinSource7\r
+#define LM75_I2C_SDA_AF GPIO_AF_1\r
+\r
+#define LM75_I2C_SMBUSALERT_PIN GPIO_Pin_5 /* PB.05 */\r
+#define LM75_I2C_SMBUSALERT_GPIO_PORT GPIOB /* GPIOB */\r
+#define LM75_I2C_SMBUSALERT_GPIO_CLK RCC_AHBPeriph_GPIOB\r
+#define LM75_I2C_SMBUSALERT_SOURCE GPIO_PinSource5\r
+#define LM75_I2C_SMBUSALERT_AF GPIO_AF_3\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup STM320518_EVAL_LOW_LEVEL_I2C_EE\r
+ * @{\r
+ */\r
+/**\r
+ * @brief I2C EEPROM Interface pins\r
+ */ \r
+#define sEE_I2C I2C1\r
+#define sEE_I2C_CLK RCC_APB1Periph_I2C1\r
+ \r
+#define sEE_I2C_SCL_PIN GPIO_Pin_6 /* PB.06 */\r
+#define sEE_I2C_SCL_GPIO_PORT GPIOB /* GPIOB */\r
+#define sEE_I2C_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB\r
+#define sEE_I2C_SCL_SOURCE GPIO_PinSource6\r
+#define sEE_I2C_SCL_AF GPIO_AF_1\r
+\r
+#define sEE_I2C_SDA_PIN GPIO_Pin_7 /* PB.07 */\r
+#define sEE_I2C_SDA_GPIO_PORT GPIOB /* GPIOB */\r
+#define sEE_I2C_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB\r
+#define sEE_I2C_SDA_SOURCE GPIO_PinSource7\r
+#define sEE_I2C_SDA_AF GPIO_AF_1\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STM320518_EVAL_LOW_LEVEL_Exported_Functions\r
+ * @{\r
+ */\r
+void STM_EVAL_LEDInit(Led_TypeDef Led);\r
+void STM_EVAL_LEDOn(Led_TypeDef Led);\r
+void STM_EVAL_LEDOff(Led_TypeDef Led);\r
+void STM_EVAL_LEDToggle(Led_TypeDef Led);\r
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);\r
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);\r
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);\r
+void SD_LowLevel_DeInit(void);\r
+void SD_LowLevel_Init(void); \r
+void sFLASH_LowLevel_DeInit(void);\r
+void sFLASH_LowLevel_Init(void);\r
+void LM75_LowLevel_DeInit(void);\r
+void LM75_LowLevel_Init(void);\r
+void sEE_LowLevel_DeInit(void);\r
+void sEE_LowLevel_Init(void); \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM320518_EVAL_H */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32_eval_legacy.h\r
+ * @author MCD Application Team\r
+ * @version V5.0.1\r
+ * @date 28-December-2011\r
+ * @brief This file contains defines legacy for STM32 EVAL drivers.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */ \r
+ \r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32_EVAL_LEGACY_H\r
+#define __STM32_EVAL_LEGACY_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* STM322xG_EVAL Defines Legacy */ \r
+#ifdef USE_STM3220F_EVAL \r
+ #define USE_STM322xG_EVAL\r
+#endif\r
+#define STM3220F_LCD_Init STM322xG_LCD_Init\r
+\r
+/* Button Defines Legacy */ \r
+#define Button_WAKEUP BUTTON_WAKEUP\r
+#define Button_TAMPER BUTTON_TAMPER\r
+#define Button_KEY BUTTON_KEY\r
+#define Button_RIGHT BUTTON_RIGHT\r
+#define Button_LEFT BUTTON_LEFT\r
+#define Button_UP BUTTON_UP\r
+#define Button_DOWN BUTTON_DOWN\r
+#define Button_SEL BUTTON_SEL\r
+#define Mode_GPIO BUTTON_MODE_GPIO\r
+#define Mode_EXTI BUTTON_MODE_EXTI\r
+#define Button_Mode_TypeDef ButtonMode_TypeDef\r
+#define JOY_CENTER JOY_SEL\r
+#define JOY_State_TypeDef JOYState_TypeDef \r
+\r
+/* LCD Defines Legacy */ \r
+#define LCD_RSNWR_GPIO_CLK LCD_NWR_GPIO_CLK\r
+#define LCD_SPI_GPIO_PORT LCD_SPI_SCK_GPIO_PORT\r
+#define LCD_SPI_GPIO_CLK LCD_SPI_SCK_GPIO_CLK\r
+#define R0 LCD_REG_0\r
+#define R1 LCD_REG_1\r
+#define R2 LCD_REG_2\r
+#define R3 LCD_REG_3\r
+#define R4 LCD_REG_4\r
+#define R5 LCD_REG_5\r
+#define R6 LCD_REG_6\r
+#define R7 LCD_REG_7\r
+#define R8 LCD_REG_8\r
+#define R9 LCD_REG_9\r
+#define R10 LCD_REG_10\r
+#define R12 LCD_REG_12\r
+#define R13 LCD_REG_13\r
+#define R14 LCD_REG_14\r
+#define R15 LCD_REG_15\r
+#define R16 LCD_REG_16\r
+#define R17 LCD_REG_17\r
+#define R18 LCD_REG_18\r
+#define R19 LCD_REG_19\r
+#define R20 LCD_REG_20\r
+#define R21 LCD_REG_21\r
+#define R22 LCD_REG_22\r
+#define R23 LCD_REG_23\r
+#define R24 LCD_REG_24\r
+#define R25 LCD_REG_25\r
+#define R26 LCD_REG_26\r
+#define R27 LCD_REG_27\r
+#define R28 LCD_REG_28\r
+#define R29 LCD_REG_29\r
+#define R30 LCD_REG_30\r
+#define R31 LCD_REG_31\r
+#define R32 LCD_REG_32\r
+#define R33 LCD_REG_33\r
+#define R34 LCD_REG_34\r
+#define R36 LCD_REG_36\r
+#define R37 LCD_REG_37\r
+#define R40 LCD_REG_40\r
+#define R41 LCD_REG_41\r
+#define R43 LCD_REG_43\r
+#define R45 LCD_REG_45\r
+#define R48 LCD_REG_48\r
+#define R49 LCD_REG_49\r
+#define R50 LCD_REG_50\r
+#define R51 LCD_REG_51\r
+#define R52 LCD_REG_52\r
+#define R53 LCD_REG_53\r
+#define R54 LCD_REG_54\r
+#define R55 LCD_REG_55\r
+#define R56 LCD_REG_56\r
+#define R57 LCD_REG_57\r
+#define R59 LCD_REG_59\r
+#define R60 LCD_REG_60\r
+#define R61 LCD_REG_61\r
+#define R62 LCD_REG_62\r
+#define R63 LCD_REG_63\r
+#define R64 LCD_REG_64\r
+#define R65 LCD_REG_65\r
+#define R66 LCD_REG_66\r
+#define R67 LCD_REG_67\r
+#define R68 LCD_REG_68\r
+#define R69 LCD_REG_69\r
+#define R70 LCD_REG_70\r
+#define R71 LCD_REG_71\r
+#define R72 LCD_REG_72\r
+#define R73 LCD_REG_73\r
+#define R74 LCD_REG_74\r
+#define R75 LCD_REG_75\r
+#define R76 LCD_REG_76\r
+#define R77 LCD_REG_77\r
+#define R78 LCD_REG_78\r
+#define R79 LCD_REG_79\r
+#define R80 LCD_REG_80\r
+#define R81 LCD_REG_81\r
+#define R82 LCD_REG_82\r
+#define R83 LCD_REG_83\r
+#define R96 LCD_REG_96\r
+#define R97 LCD_REG_97\r
+#define R106 LCD_REG_106\r
+#define R118 LCD_REG_118\r
+#define R128 LCD_REG_128\r
+#define R129 LCD_REG_129\r
+#define R130 LCD_REG_130\r
+#define R131 LCD_REG_131\r
+#define R132 LCD_REG_132\r
+#define R133 LCD_REG_133\r
+#define R134 LCD_REG_134\r
+#define R135 LCD_REG_135\r
+#define R136 LCD_REG_136\r
+#define R137 LCD_REG_137\r
+#define R139 LCD_REG_139\r
+#define R140 LCD_REG_140\r
+#define R141 LCD_REG_141\r
+#define R143 LCD_REG_143\r
+#define R144 LCD_REG_144\r
+#define R145 LCD_REG_145\r
+#define R146 LCD_REG_146\r
+#define R147 LCD_REG_147\r
+#define R148 LCD_REG_148\r
+#define R149 LCD_REG_149\r
+#define R150 LCD_REG_150\r
+#define R151 LCD_REG_151\r
+#define R152 LCD_REG_152\r
+#define R153 LCD_REG_153\r
+#define R154 LCD_REG_154\r
+#define R157 LCD_REG_157\r
+#define R192 LCD_REG_192\r
+#define R193 LCD_REG_193\r
+#define R227 LCD_REG_227\r
+#define R229 LCD_REG_229\r
+#define R231 LCD_REG_231\r
+#define R239 LCD_REG_239\r
+#define White LCD_COLOR_WHITE\r
+#define Black LCD_COLOR_BLACK\r
+#define Grey LCD_COLOR_GREY\r
+#define Blue LCD_COLOR_BLUE\r
+#define Blue2 LCD_COLOR_BLUE2\r
+#define Red LCD_COLOR_RED\r
+#define Magenta LCD_COLOR_MAGENTA\r
+#define Green LCD_COLOR_GREEN\r
+#define Cyan LCD_COLOR_CYAN\r
+#define Yellow LCD_COLOR_YELLOW\r
+#define Line0 LCD_LINE_0\r
+#define Line1 LCD_LINE_1\r
+#define Line2 LCD_LINE_2\r
+#define Line3 LCD_LINE_3\r
+#define Line4 LCD_LINE_4\r
+#define Line5 LCD_LINE_5\r
+#define Line6 LCD_LINE_6\r
+#define Line7 LCD_LINE_7\r
+#define Line8 LCD_LINE_8\r
+#define Line9 LCD_LINE_9\r
+#define Horizontal LCD_DIR_HORIZONTAL\r
+#define Vertical LCD_DIR_VERTICAL\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/ \r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32_EVAL_LEGACY_H */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_conf.h \r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief Library configuration file.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_CONF_H\r
+#define __STM32F0XX_CONF_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Comment the line below to disable peripheral header file inclusion */\r
+#include "stm32f0xx_adc.h"\r
+#include "stm32f0xx_cec.h"\r
+#include "stm32f0xx_crc.h"\r
+#include "stm32f0xx_comp.h"\r
+#include "stm32f0xx_dac.h"\r
+#include "stm32f0xx_dbgmcu.h"\r
+#include "stm32f0xx_dma.h"\r
+#include "stm32f0xx_exti.h"\r
+#include "stm32f0xx_flash.h"\r
+#include "stm32f0xx_gpio.h"\r
+#include "stm32f0xx_syscfg.h"\r
+#include "stm32f0xx_i2c.h"\r
+#include "stm32f0xx_iwdg.h"\r
+#include "stm32f0xx_pwr.h"\r
+#include "stm32f0xx_rcc.h"\r
+#include "stm32f0xx_rtc.h"\r
+#include "stm32f0xx_spi.h"\r
+#include "stm32f0xx_tim.h"\r
+#include "stm32f0xx_usart.h"\r
+#include "stm32f0xx_wwdg.h"\r
+#include "stm32f0xx_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Uncomment the line below to expanse the "assert_param" macro in the \r
+ Standard Peripheral Library drivers code */\r
+/* #define USE_FULL_ASSERT 1 */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef USE_FULL_ASSERT\r
+\r
+/**\r
+ * @brief The assert_param macro is used for function's parameters check.\r
+ * @param expr: If expr is false, it calls assert_failed function which reports \r
+ * the name of the source file and the source line number of the call \r
+ * that failed. If expr is true, it returns no value.\r
+ * @retval None\r
+ */\r
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+ void assert_failed(uint8_t* file, uint32_t line);\r
+#else\r
+ #define assert_param(expr) ((void)0)\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+#endif /* __STM32F0XX_CONF_H */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Ensure stdint is only used by the compiler, and not the assembler. */\r
+#ifdef __ICCARM__\r
+ #include <stdint.h>\r
+ extern uint32_t SystemCoreClock;\r
+#endif\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 1\r
+#define configCPU_CLOCK_HZ ( SystemCoreClock )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 60 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 6500 ) )\r
+#define configMAX_TASK_NAME_LEN ( 5 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( 80 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names - or at least those used in the unmodified vector table. */\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. \r
+ * This file contains all the peripheral register's definitions, bits \r
+ * definitions and memory mapping for STM32F0xx devices. \r
+ * \r
+ * The file is the unique include file that the application programmer\r
+ * is using in the C source code, usually in main.c. This file contains:\r
+ * - Configuration section that allows to select:\r
+ * - The device used in the target application\r
+ * - To use or not the peripheral’s drivers in application code(i.e. \r
+ * code will be based on direct access to peripheral’s registers \r
+ * rather than drivers API), this option is controlled by \r
+ * "#define USE_STDPERIPH_DRIVER"\r
+ * - To change few application-specific parameters such as the HSE \r
+ * crystal frequency\r
+ * - Data structures and the address mapping for all peripherals\r
+ * - Peripheral's registers declarations and bits definition\r
+ * - Macros to access peripheral’s registers hardware\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f0xx\r
+ * @{\r
+ */\r
+ \r
+#ifndef __STM32F0XX_H\r
+#define __STM32F0XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+ \r
+/** @addtogroup Library_configuration_section\r
+ * @{\r
+ */\r
+ \r
+/* Uncomment the line below according to the target STM32F-0 device used in your \r
+ application \r
+ */\r
+\r
+#if !defined (STM32F0XX)\r
+ #define STM32F0XX /*!< STM32F0XX: STM32F0xx devices */\r
+#endif\r
+/* Tip: To avoid modifying this file each time you need to switch between these\r
+ devices, you can define the device in your toolchain compiler preprocessor.\r
+\r
+ - STM32F0xx devices are STM32F050xx microcontrollers where the Flash memory \r
+ density ranges between 32 and 64 Kbytes.\r
+ */\r
+\r
+#if !defined (STM32F0XX)\r
+ #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"\r
+#endif\r
+\r
+#if !defined USE_STDPERIPH_DRIVER\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+ In this case, these drivers will not be included and the application code will \r
+ be based on direct access to peripherals registers \r
+ */\r
+ /*#define USE_STDPERIPH_DRIVER*/\r
+#endif\r
+\r
+/**\r
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)\r
+ used in your application \r
+ \r
+ Tip: To avoid modifying this file each time you need to use different HSE, you\r
+ can define the HSE value in your toolchain compiler preprocessor.\r
+ */\r
+#if !defined (HSE_VALUE) \r
+#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/\r
+#endif\r
+\r
+/**\r
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup \r
+ Timeout value \r
+ */\r
+#if !defined (HSE_STARTUP_TIMEOUT)\r
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */\r
+#endif\r
+\r
+/**\r
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup \r
+ Timeout value \r
+ */\r
+#if !defined (HSI_STARTUP_TIMEOUT)\r
+#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */\r
+#endif\r
+\r
+#if !defined (HSI_VALUE) \r
+#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.\r
+ The real value may vary depending on the variations\r
+ in voltage and temperature. */\r
+#endif\r
+\r
+#if !defined (HSI14_VALUE) \r
+#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.\r
+ The real value may vary depending on the variations\r
+ in voltage and temperature. */\r
+#endif\r
+\r
+#if !defined (LSI_VALUE) \r
+#define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz\r
+ The real value may vary depending on the variations\r
+ in voltage and temperature. */\r
+#endif\r
+#if !defined (LSE_VALUE) \r
+#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */\r
+#endif\r
+\r
+/**\r
+ * @brief STM32F0xx Standard Peripheral Library version number V1.0.0RC1\r
+ */\r
+#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */\r
+#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */\r
+#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
+#define __STM32F0XX_STDPERIPH_VERSION_RC (0x01) /*!< [7:0] release candidate */ \r
+#define __STM32F0XX_STDPERIPH_VERSION ( (__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\\r
+ |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\\r
+ |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\\r
+ |(__STM32F0XX_STDPERIPH_VERSION_RC))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Configuration_section_for_CMSIS\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32F0xx Interrupt Number Definition, according to the selected device \r
+ * in @ref Library_configuration_section \r
+ */\r
+#define __CM0_REV 0 /*!< Core Revision r0p0 */\r
+#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */\r
+#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/*!< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */\r
+ SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */\r
+\r
+/****** STM32F-0 specific Interrupt Numbers *********************************************************/\r
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */\r
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */\r
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */\r
+ RCC_IRQn = 4, /*!< RCC Interrupt */\r
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */\r
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */\r
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */\r
+ TS_IRQn = 8, /*!< TS Interrupt */\r
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */\r
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */\r
+ DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */\r
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */\r
+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */\r
+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */\r
+ TIM3_IRQn = 16, /*!< TIM3 Interrupt */\r
+ TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */\r
+ TIM14_IRQn = 19, /*!< TIM14 Interrupt */\r
+ TIM15_IRQn = 20, /*!< TIM15 Interrupt */\r
+ TIM16_IRQn = 21, /*!< TIM16 Interrupt */\r
+ TIM17_IRQn = 22, /*!< TIM17 Interrupt */\r
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */\r
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */\r
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */\r
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */\r
+ USART1_IRQn = 27, /*!< USART1 Interrupt */\r
+ USART2_IRQn = 28, /*!< USART2 Interrupt */\r
+ CEC_IRQn = 30 /*!< CEC Interrupt */\r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#include "core_cm0.h"\r
+#include "system_stm32f0xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Exported_types\r
+ * @{\r
+ */ \r
+\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
+\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief Analog to Digital Converter \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */\r
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */\r
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */\r
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */\r
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */\r
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */\r
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */\r
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */\r
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */\r
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */\r
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */\r
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */\r
+} ADC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CCR;\r
+} ADC_Common_TypeDef;\r
+\r
+/** \r
+ * @brief HDMI-CEC \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */\r
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */\r
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */\r
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */\r
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */\r
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */\r
+}CEC_TypeDef;\r
+\r
+/**\r
+ * @brief Comparator \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */\r
+} COMP_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief CRC calculation unit \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\r
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\r
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */\r
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */\r
+} CRC_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Digital to Analog Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\r
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\r
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\r
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\r
+ uint32_t RESERVED[6]; /*!< Reserved, 0x14 */\r
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\r
+ uint32_t RESERVED1; /*!< Reserved, 0x30 */\r
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\r
+} DAC_TypeDef;\r
+\r
+/** \r
+ * @brief Debug MCU\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\r
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\r
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */\r
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */\r
+}DBGMCU_TypeDef;\r
+\r
+/** \r
+ * @brief DMA Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */\r
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */\r
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */\r
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */\r
+} DMA_Channel_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */\r
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */\r
+} DMA_TypeDef;\r
+\r
+/** \r
+ * @brief External Interrupt/Event Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */\r
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */\r
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */\r
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */\r
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */\r
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */\r
+}EXTI_TypeDef;\r
+\r
+/** \r
+ * @brief FLASH Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */\r
+ __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */\r
+ __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */\r
+ __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */\r
+ __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */\r
+ __IO uint32_t RESERVED; /*!< Reserved, 0x18 */\r
+ __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */\r
+ __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */\r
+} FLASH_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Option Bytes Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */\r
+ __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x04 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */\r
+ __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */\r
+} OB_TypeDef;\r
+ \r
+\r
+/** \r
+ * @brief General Purpose IO\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\r
+ __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x06 */\r
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\r
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\r
+ __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x12 */\r
+ __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x16 */\r
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */\r
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\r
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */\r
+ __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x2A */\r
+}GPIO_TypeDef;\r
+\r
+/** \r
+ * @brief SysTem Configuration\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */\r
+ uint32_t RESERVED; /*!< Reserved, 0x04 */\r
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */\r
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */\r
+} SYSCFG_TypeDef;\r
+\r
+/** \r
+ * @brief Inter-integrated Circuit Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */\r
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */\r
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */\r
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */\r
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */\r
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */\r
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */\r
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */\r
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */\r
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */\r
+}I2C_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Independent WATCHDOG\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */\r
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */\r
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */\r
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */\r
+} IWDG_TypeDef;\r
+\r
+/** \r
+ * @brief Power Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */\r
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */\r
+} PWR_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Reset and Clock Control\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\r
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */\r
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */\r
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */\r
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */\r
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */\r
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */\r
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */\r
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ \r
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */\r
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */\r
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */\r
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */\r
+ __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */\r
+} RCC_TypeDef;\r
+\r
+/** \r
+ * @brief Real-Time Clock\r
+ */\r
+\r
+typedef struct\r
+{ \r
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\r
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\r
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */\r
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */\r
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\r
+ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */\r
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */\r
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */\r
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */\r
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\r
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */\r
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\r
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\r
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\r
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\r
+ __IO uint32_t CAL; /*!< RTC calibration register, Address offset: 0x3C */\r
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\r
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */\r
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */\r
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */\r
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */\r
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */\r
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */\r
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */\r
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */\r
+} RTC_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Serial Peripheral Interface\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
+ __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
+ __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
+ __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\r
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
+ __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */\r
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
+ __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */\r
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */ \r
+ __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */\r
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */\r
+ __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */\r
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */ \r
+} SPI_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief TIM\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
+ __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint16_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
+ __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
+ __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */\r
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
+ __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\r
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
+ __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
+ __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */\r
+ __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\r
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */\r
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\r
+ __IO uint16_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */\r
+ uint16_t RESERVED10; /*!< Reserved, 0x2A */\r
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\r
+ __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\r
+ uint16_t RESERVED12; /*!< Reserved, 0x32 */\r
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\r
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\r
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\r
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\r
+ __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\r
+ uint16_t RESERVED17; /*!< Reserved, 0x26 */\r
+ __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */\r
+ uint16_t RESERVED18; /*!< Reserved, 0x4A */\r
+ __IO uint16_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */\r
+ uint16_t RESERVED19; /*!< Reserved, 0x4E */\r
+ __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */\r
+ uint16_t RESERVED20; /*!< Reserved, 0x52 */\r
+} TIM_TypeDef;\r
+\r
+/** \r
+ * @brief Touch Sensing Controller (TSC)\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */\r
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */\r
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ \r
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */\r
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */\r
+ __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */\r
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */\r
+ __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */\r
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */\r
+ __IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */\r
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */\r
+ __IO uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */\r
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */\r
+ __IO uint32_t IOGXCR[6]; /*!< TSC I/O group x counter register, Address offset: 0x34-48 */\r
+} TSC_TypeDef;\r
+\r
+/** \r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ \r
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ \r
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */\r
+ __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x0E */ \r
+ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x12 */\r
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ \r
+ __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x1A */\r
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */\r
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */\r
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */\r
+ uint16_t RESERVED4; /*!< Reserved, 0x26 */\r
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */\r
+ uint16_t RESERVED5; /*!< Reserved, 0x2A */\r
+} USART_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Window WATCHDOG\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\r
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\r
+} WWDG_TypeDef;\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_memory_map\r
+ * @{\r
+ */\r
+\r
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */\r
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */\r
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */\r
+\r
+/*!< Peripheral memory map */\r
+#define APBPERIPH_BASE PERIPH_BASE\r
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)\r
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)\r
+\r
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)\r
+#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)\r
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)\r
+#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)\r
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800)\r
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)\r
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)\r
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)\r
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400)\r
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)\r
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)\r
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000)\r
+#define DAC_BASE (APBPERIPH_BASE + 0x00007400)\r
+#define CEC_BASE (APBPERIPH_BASE + 0x00007800)\r
+\r
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)\r
+#define COMP_BASE (APBPERIPH_BASE + 0x0001001C)\r
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)\r
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)\r
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708)\r
+#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)\r
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)\r
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800)\r
+#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)\r
+#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)\r
+#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)\r
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)\r
+\r
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)\r
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)\r
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)\r
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)\r
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)\r
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)\r
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)\r
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */\r
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */\r
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)\r
+#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)\r
+\r
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)\r
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)\r
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)\r
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)\r
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_declaration\r
+ * @{\r
+ */ \r
+\r
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+#define PWR ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC ((DAC_TypeDef *) DAC_BASE)\r
+#define CEC ((CEC_TypeDef *) CEC_BASE)\r
+\r
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define COMP ((COMP_TypeDef *) COMP_BASE)\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)\r
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
+#define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)\r
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)\r
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)\r
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+\r
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\r
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\r
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\r
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\r
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\r
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define OB ((OB_TypeDef *) OB_BASE) \r
+#define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#define CRC ((CRC_TypeDef *) CRC_BASE)\r
+#define TSC ((TSC_TypeDef *) TSC_BASE)\r
+\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_constants\r
+ * @{\r
+ */\r
+ \r
+ /** @addtogroup Peripheral_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+ \r
+/******************************************************************************/\r
+/* Peripheral Registers Bits Definition */\r
+/******************************************************************************/\r
+/******************************************************************************/\r
+/* */\r
+/* Analog to Digital Converter (ADC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for ADC_ISR register ******************/\r
+#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */\r
+#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */\r
+#define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< End of Sequence flag */\r
+#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */\r
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */\r
+#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */\r
+\r
+/******************** Bits definition for ADC_IER register ******************/\r
+#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */\r
+#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */\r
+#define ADC_IER_EOSIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */\r
+#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */\r
+#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */\r
+#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */\r
+\r
+/******************** Bits definition for ADC_CR register *******************/\r
+#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */\r
+#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */\r
+#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */\r
+#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */\r
+#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */\r
+\r
+/******************* Bits definition for ADC_CFGR1 register *****************/\r
+#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */\r
+#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */\r
+#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */\r
+#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */\r
+#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */\r
+#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */\r
+#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */\r
+#define ADC_CFGR1_AUTDLY ((uint32_t)0x00004000) /*!< ADC delayed conversion mode */\r
+#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */\r
+#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */\r
+#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */\r
+#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */\r
+#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */\r
+#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */\r
+#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */\r
+#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */\r
+#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */\r
+#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */\r
+\r
+/******************* Bits definition for ADC_CFGR2 register *****************/\r
+#define ADC_CFGR2_JITOFFDIV4 ((uint32_t)0x80000000) /*!< Jitter Off when ADC clocked by PCLK div4 */\r
+#define ADC_CFGR2_JITOFFDIV2 ((uint32_t)0x40000000) /*!< Jitter Off when ADC clocked by PCLK div2 */\r
+\r
+/****************** Bit definition for ADC_SMPR register ********************/\r
+#define ADC_SMPR1_SMPR ((uint32_t)0x00000007) /*!< SMPR[2:0] bits (Sampling time selection) */\r
+#define ADC_SMPR1_SMPR_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define ADC_SMPR1_SMPR_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define ADC_SMPR1_SMPR_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+\r
+/******************* Bit definition for ADC_HTR register ********************/\r
+#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */\r
+\r
+/******************* Bit definition for ADC_LTR register ********************/\r
+#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */\r
+\r
+/****************** Bit definition for ADC_CHSELR register ******************/\r
+#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */\r
+#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */\r
+#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */\r
+#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */\r
+#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */\r
+#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */\r
+#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */\r
+#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */\r
+#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */\r
+#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */\r
+#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */\r
+#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */\r
+#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */\r
+#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */\r
+#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */\r
+#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */\r
+#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */\r
+#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */\r
+#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */\r
+\r
+/******************** Bit definition for ADC_DR register ********************/\r
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */\r
+\r
+/******************* Bit definition for ADC_CCR register ********************/\r
+#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */\r
+#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */\r
+#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* HDMI-CEC (CEC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for CEC_CR register *********************/\r
+#define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */\r
+#define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */\r
+#define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */\r
+\r
+/******************* Bit definition for CEC_CFGR register *******************/\r
+#define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */\r
+#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */\r
+#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */\r
+#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */\r
+#define CEC_CFGR_LREGEN ((uint32_t)0x00000040) /*!< CEC Long Period Error generation */\r
+#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast no Error generation */\r
+#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */\r
+#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */\r
+#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */\r
+\r
+/******************* Bit definition for CEC_TXDR register *******************/\r
+#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */\r
+\r
+/******************* Bit definition for CEC_RXDR register *******************/\r
+#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */\r
+\r
+/******************* Bit definition for CEC_ISR register ********************/\r
+#define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */\r
+#define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */\r
+#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */\r
+#define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */\r
+#define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */\r
+#define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */\r
+#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */\r
+#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */\r
+#define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */\r
+#define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */\r
+#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */\r
+#define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */\r
+#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */\r
+\r
+/******************* Bit definition for CEC_IER register ********************/\r
+#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */\r
+#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */\r
+#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */\r
+#define CEC_IER_BREIEIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */\r
+#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/\r
+#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */\r
+#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */\r
+#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */\r
+#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */\r
+#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */\r
+#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */\r
+#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */\r
+#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Analog Comparators (COMP) */\r
+/* */\r
+/******************************************************************************/\r
+/*********************** Bit definition for COMP_CSR register ***************/\r
+/* COMP1 bits definition */\r
+#define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */\r
+#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */\r
+#define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */\r
+#define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */\r
+#define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */\r
+#define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */\r
+#define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */\r
+#define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */\r
+#define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */\r
+#define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */\r
+#define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */\r
+#define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */\r
+#define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */\r
+#define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */\r
+#define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */\r
+#define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */\r
+#define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */\r
+#define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */\r
+#define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */\r
+/* COMP2 bits definition */\r
+#define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */\r
+#define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */\r
+#define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */\r
+#define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */\r
+#define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */\r
+#define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */\r
+#define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */\r
+#define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */\r
+#define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */\r
+#define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */\r
+#define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */\r
+#define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */\r
+#define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */\r
+#define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */\r
+#define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */\r
+#define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */\r
+#define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */\r
+#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */\r
+#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CRC calculation unit (CRC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for CRC_DR register *********************/\r
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\r
+\r
+/******************* Bit definition for CRC_IDR register ********************/\r
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */\r
+\r
+/******************** Bit definition for CRC_CR register ********************/\r
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */\r
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */\r
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */\r
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */\r
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */\r
+\r
+/******************* Bit definition for CRC_INIT register *******************/\r
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital to Analog Converter (DAC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DAC_CR register ********************/\r
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */\r
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */\r
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */\r
+\r
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+\r
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */\r
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA Underrun Interrupt enable */\r
+/***************** Bit definition for DAC_SWTRIGR register ******************/\r
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!<DAC channel1 software trigger */\r
+\r
+/***************** Bit definition for DAC_DHR12R1 register ******************/\r
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L1 register ******************/\r
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R1 register ******************/\r
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/******************* Bit definition for DAC_DOR1 register *******************/\r
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!<DAC channel1 data output */\r
+\r
+/******************** Bit definition for DAC_SR register ********************/\r
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Debug MCU (DBGMCU) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/**************** Bit definition for DBGMCU_IDCODE register *****************/\r
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */\r
+\r
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */\r
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */\r
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */\r
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */\r
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */\r
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */\r
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */\r
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */\r
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */\r
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */\r
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */\r
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */\r
+\r
+/****************** Bit definition for DBGMCU_CR register *******************/\r
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */\r
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */\r
+\r
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */\r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */\r
+\r
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/\r
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */\r
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */\r
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */\r
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DMA Controller (DMA) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for DMA_ISR register ********************/\r
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */\r
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */\r
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */\r
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */\r
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */\r
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */\r
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */\r
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */\r
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */\r
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */\r
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */\r
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */\r
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */\r
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */\r
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */\r
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */\r
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */\r
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */\r
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */\r
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */\r
+\r
+/******************* Bit definition for DMA_IFCR register *******************/\r
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */\r
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */\r
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */\r
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */\r
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */\r
+\r
+/******************* Bit definition for DMA_CCR register ********************/\r
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */\r
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */\r
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */\r
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */\r
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/\r
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */\r
+\r
+/****************** Bit definition for DMA_CNDTR register *******************/\r
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CPAR register ********************/\r
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CMAR register ********************/\r
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* External Interrupt/Event Controller (EXTI) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for EXTI_IMR register *******************/\r
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */\r
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */\r
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */\r
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */\r
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */\r
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */\r
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */\r
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */\r
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */\r
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */\r
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */\r
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */\r
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */\r
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */\r
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */\r
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */\r
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */\r
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */\r
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */\r
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */\r
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */\r
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */\r
+#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */\r
+#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */\r
+\r
+/****************** Bit definition for EXTI_EMR register ********************/\r
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */\r
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */\r
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */\r
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */\r
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */\r
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */\r
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */\r
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */\r
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */\r
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */\r
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */\r
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */\r
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */\r
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */\r
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */\r
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */\r
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */\r
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */\r
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */\r
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */\r
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */\r
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */\r
+#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */\r
+#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */\r
+\r
+/******************* Bit definition for EXTI_RTSR register ******************/\r
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */\r
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */\r
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */\r
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */\r
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */\r
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */\r
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */\r
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */\r
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */\r
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */\r
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */\r
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */\r
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */\r
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */\r
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */\r
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */\r
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */\r
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */\r
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */\r
+\r
+/******************* Bit definition for EXTI_FTSR register *******************/\r
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */\r
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */\r
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */\r
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */\r
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */\r
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */\r
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */\r
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */\r
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */\r
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */\r
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */\r
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */\r
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */\r
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */\r
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */\r
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */\r
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */\r
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */\r
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */\r
+\r
+/******************* Bit definition for EXTI_SWIER register *******************/\r
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */\r
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */\r
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */\r
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */\r
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */\r
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */\r
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */\r
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */\r
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */\r
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */\r
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */\r
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */\r
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */\r
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */\r
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */\r
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */\r
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */\r
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */\r
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */\r
+\r
+/****************** Bit definition for EXTI_PR register *********************/\r
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */\r
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */\r
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */\r
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */\r
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */\r
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */\r
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */\r
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */\r
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */\r
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */\r
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */\r
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */\r
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */\r
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */\r
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */\r
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */\r
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */\r
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */\r
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* FLASH and Option Bytes Registers */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for FLASH_ACR register ******************/\r
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */\r
+\r
+#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */\r
+#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */\r
+\r
+/****************** Bit definition for FLASH_KEYR register ******************/\r
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */\r
+\r
+/***************** Bit definition for FLASH_OPTKEYR register ****************/\r
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */\r
+\r
+/****************** Bit definition for FLASH_SR register *******************/\r
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */\r
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */\r
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */\r
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */\r
+\r
+/******************* Bit definition for FLASH_CR register *******************/\r
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */\r
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */\r
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */\r
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */\r
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */\r
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */\r
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */\r
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */\r
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */\r
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */\r
+#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */\r
+\r
+/******************* Bit definition for FLASH_AR register *******************/\r
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */\r
+\r
+/****************** Bit definition for FLASH_OBR register *******************/\r
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */\r
+#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */\r
+#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */\r
+\r
+#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */\r
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */\r
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */\r
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */\r
+#define FLASH_OBR_BOOT1 ((uint32_t)0x00001000) /*!< BOOT1 */\r
+#define FLASH_OBR_VDDA_ANALOG ((uint32_t)0x00002000) /*!< VDDA Analog Monitoring */\r
+\r
+/****************** Bit definition for FLASH_WRPR register ******************/\r
+#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/****************** Bit definition for OB_RDP register **********************/\r
+#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */\r
+#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */\r
+\r
+/****************** Bit definition for OB_USER register *********************/\r
+#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */\r
+#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */\r
+\r
+/****************** Bit definition for OB_WRP0 register *********************/\r
+#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */\r
+#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */\r
+\r
+/****************** Bit definition for OB_WRP1 register *********************/\r
+#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */\r
+#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* General Purpose IOs (GPIO) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for GPIO_MODER register *****************/\r
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)\r
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)\r
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)\r
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)\r
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)\r
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)\r
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)\r
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)\r
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)\r
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)\r
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)\r
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)\r
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)\r
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)\r
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)\r
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)\r
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)\r
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)\r
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)\r
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)\r
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)\r
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)\r
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)\r
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)\r
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)\r
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)\r
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)\r
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)\r
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)\r
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)\r
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)\r
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)\r
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)\r
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)\r
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)\r
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)\r
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)\r
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)\r
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)\r
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)\r
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)\r
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)\r
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)\r
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)\r
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)\r
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)\r
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)\r
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)\r
+\r
+/****************** Bit definition for GPIO_OTYPER register *****************/\r
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)\r
+\r
+/**************** Bit definition for GPIO_OSPEEDR register ******************/\r
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)\r
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)\r
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)\r
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)\r
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)\r
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)\r
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)\r
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)\r
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)\r
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)\r
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)\r
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)\r
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)\r
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)\r
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)\r
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)\r
+\r
+/******************* Bit definition for GPIO_PUPDR register ******************/\r
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)\r
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)\r
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)\r
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)\r
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)\r
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)\r
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)\r
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)\r
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)\r
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)\r
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)\r
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)\r
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)\r
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)\r
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)\r
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)\r
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)\r
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)\r
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)\r
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)\r
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)\r
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)\r
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)\r
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)\r
+\r
+/******************* Bit definition for GPIO_IDR register *******************/\r
+#define GPIO_IDR_0 ((uint32_t)0x00000001)\r
+#define GPIO_IDR_1 ((uint32_t)0x00000002)\r
+#define GPIO_IDR_2 ((uint32_t)0x00000004)\r
+#define GPIO_IDR_3 ((uint32_t)0x00000008)\r
+#define GPIO_IDR_4 ((uint32_t)0x00000010)\r
+#define GPIO_IDR_5 ((uint32_t)0x00000020)\r
+#define GPIO_IDR_6 ((uint32_t)0x00000040)\r
+#define GPIO_IDR_7 ((uint32_t)0x00000080)\r
+#define GPIO_IDR_8 ((uint32_t)0x00000100)\r
+#define GPIO_IDR_9 ((uint32_t)0x00000200)\r
+#define GPIO_IDR_10 ((uint32_t)0x00000400)\r
+#define GPIO_IDR_11 ((uint32_t)0x00000800)\r
+#define GPIO_IDR_12 ((uint32_t)0x00001000)\r
+#define GPIO_IDR_13 ((uint32_t)0x00002000)\r
+#define GPIO_IDR_14 ((uint32_t)0x00004000)\r
+#define GPIO_IDR_15 ((uint32_t)0x00008000)\r
+\r
+/****************** Bit definition for GPIO_ODR register ********************/\r
+#define GPIO_ODR_0 ((uint32_t)0x00000001)\r
+#define GPIO_ODR_1 ((uint32_t)0x00000002)\r
+#define GPIO_ODR_2 ((uint32_t)0x00000004)\r
+#define GPIO_ODR_3 ((uint32_t)0x00000008)\r
+#define GPIO_ODR_4 ((uint32_t)0x00000010)\r
+#define GPIO_ODR_5 ((uint32_t)0x00000020)\r
+#define GPIO_ODR_6 ((uint32_t)0x00000040)\r
+#define GPIO_ODR_7 ((uint32_t)0x00000080)\r
+#define GPIO_ODR_8 ((uint32_t)0x00000100)\r
+#define GPIO_ODR_9 ((uint32_t)0x00000200)\r
+#define GPIO_ODR_10 ((uint32_t)0x00000400)\r
+#define GPIO_ODR_11 ((uint32_t)0x00000800)\r
+#define GPIO_ODR_12 ((uint32_t)0x00001000)\r
+#define GPIO_ODR_13 ((uint32_t)0x00002000)\r
+#define GPIO_ODR_14 ((uint32_t)0x00004000)\r
+#define GPIO_ODR_15 ((uint32_t)0x00008000)\r
+\r
+/****************** Bit definition for GPIO_BSRR register ********************/\r
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)\r
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)\r
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)\r
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)\r
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)\r
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)\r
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)\r
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)\r
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)\r
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)\r
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)\r
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)\r
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)\r
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)\r
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)\r
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)\r
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)\r
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)\r
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)\r
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)\r
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)\r
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)\r
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)\r
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)\r
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)\r
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)\r
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)\r
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)\r
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)\r
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)\r
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)\r
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)\r
+\r
+/****************** Bit definition for GPIO_LCKR register ********************/\r
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)\r
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)\r
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)\r
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)\r
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)\r
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)\r
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)\r
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)\r
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)\r
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)\r
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)\r
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)\r
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)\r
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)\r
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)\r
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)\r
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)\r
+\r
+/****************** Bit definition for GPIO_AFRL register ********************/\r
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)\r
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)\r
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)\r
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)\r
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)\r
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)\r
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)\r
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)\r
+\r
+/****************** Bit definition for GPIO_AFRH register ********************/\r
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)\r
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)\r
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)\r
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)\r
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)\r
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)\r
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)\r
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)\r
+\r
+/****************** Bit definition for GPIO_BRR register *********************/\r
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)\r
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)\r
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)\r
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)\r
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)\r
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)\r
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)\r
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)\r
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)\r
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)\r
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)\r
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)\r
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)\r
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)\r
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)\r
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Inter-integrated Circuit Interface (I2C) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for I2C_CR1 register *******************/\r
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */\r
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */\r
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */\r
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */\r
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */\r
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */\r
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */\r
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */\r
+#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */\r
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */\r
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */\r
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */\r
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */\r
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */\r
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */\r
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */\r
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */\r
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */\r
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */\r
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */\r
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */\r
+\r
+/****************** Bit definition for I2C_CR2 register ********************/\r
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */\r
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */\r
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */\r
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */\r
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */\r
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */\r
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */\r
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */\r
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */\r
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */\r
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */\r
+\r
+/******************* Bit definition for I2C_OAR1 register ******************/\r
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */\r
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */\r
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */\r
+\r
+/******************* Bit definition for I2C_OAR2 register ******************/\r
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */\r
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */\r
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */\r
+\r
+/******************* Bit definition for I2C_TIMINGR register *******************/\r
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */\r
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */\r
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */\r
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */\r
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */\r
+\r
+/******************* Bit definition for I2C_TIMEOUTR register *******************/\r
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */\r
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */\r
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */\r
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/\r
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */\r
+\r
+/****************** Bit definition for I2C_ISR register *********************/\r
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */\r
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */\r
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */\r
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/\r
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */\r
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */\r
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */\r
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */\r
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */\r
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */\r
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */\r
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */\r
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */\r
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */\r
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */\r
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */\r
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */\r
+\r
+/****************** Bit definition for I2C_ICR register *********************/\r
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */\r
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */\r
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */\r
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */\r
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */\r
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */\r
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */\r
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */\r
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */\r
+\r
+/****************** Bit definition for I2C_PECR register *********************/\r
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */\r
+\r
+/****************** Bit definition for I2C_RXDR register *********************/\r
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */\r
+\r
+/****************** Bit definition for I2C_TXDR register *********************/\r
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Independent WATCHDOG (IWDG) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */\r
+\r
+/******************* Bit definition for IWDG_PR register ********************/\r
+#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */\r
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */\r
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */\r
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */\r
+\r
+/******************* Bit definition for IWDG_RLR register *******************/\r
+#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */\r
+\r
+/******************* Bit definition for IWDG_SR register ********************/\r
+#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */\r
+#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */\r
+#define IWDG_SR_WVU ((uint8_t)0x04) /*!< Watchdog counter window value update */\r
+\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_WINR_WIN ((uint16_t)0x0FFF) /*!< Watchdog counter window value */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Power Control (PWR) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for PWR_CR register ********************/\r
+#define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */\r
+#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */\r
+#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */\r
+#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */\r
+#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */\r
+\r
+#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */\r
+#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */\r
+#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */\r
+#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */\r
+\r
+/*!< PVD level configuration */\r
+#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */\r
+#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */\r
+#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */\r
+#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */\r
+#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */\r
+#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */\r
+#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */\r
+#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */\r
+\r
+#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */\r
+\r
+/******************* Bit definition for PWR_CSR register ********************/\r
+#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */\r
+#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */\r
+#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */\r
+#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */\r
+\r
+#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */\r
+#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Reset and Clock Control */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for RCC_CR register ********************/\r
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */\r
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */\r
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */\r
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */\r
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */\r
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */\r
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */\r
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */\r
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */\r
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */\r
+\r
+/******************* Bit definition for RCC_CFGR register *******************/\r
+/*!< SW configuration */\r
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */\r
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+\r
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */\r
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */\r
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */\r
+\r
+/*!< SWS configuration */\r
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
+\r
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */\r
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */\r
+\r
+/*!< HPRE configuration */\r
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */\r
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */\r
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */\r
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */\r
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */\r
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */\r
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */\r
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */\r
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */\r
+\r
+/*!< PPRE configuration */\r
+#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */\r
+#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+\r
+#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */\r
+\r
+/*!< ADCPPRE configuration */\r
+#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */\r
+\r
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */\r
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */\r
+\r
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */\r
+\r
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */\r
+\r
+/*!< PLLMUL configuration */\r
+#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\r
+#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */\r
+\r
+#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */\r
+#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */\r
+\r
+#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */\r
+#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */\r
+\r
+#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */\r
+#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */\r
+#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */\r
+#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */\r
+#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */\r
+#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */\r
+#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */\r
+#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */\r
+#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */\r
+#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */\r
+#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */\r
+#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */\r
+#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */\r
+#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */\r
+#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */\r
+\r
+/*!< MCO configuration */\r
+#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */\r
+#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+\r
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
+#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x03000000) /*!< HSI14 clock selected as MCO source */\r
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */\r
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */\r
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */\r
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */\r
+\r
+/*!<****************** Bit definition for RCC_CIR register ********************/\r
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */\r
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */\r
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */\r
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */\r
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */\r
+#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */\r
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */\r
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */\r
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */\r
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */\r
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */\r
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */\r
+#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */\r
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */\r
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */\r
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */\r
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */\r
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */\r
+#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */\r
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */\r
+\r
+/***************** Bit definition for RCC_APB2RSTR register *****************/\r
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */\r
+#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 clock reset */\r
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */\r
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */\r
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */\r
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */\r
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */\r
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */\r
+#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */\r
+\r
+/***************** Bit definition for RCC_APB1RSTR register *****************/\r
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */\r
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */\r
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */\r
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */\r
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */\r
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */\r
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */\r
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */\r
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */\r
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */\r
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */\r
+#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */\r
+\r
+/****************** Bit definition for RCC_AHBENR register ******************/\r
+#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */\r
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */\r
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */\r
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */\r
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */\r
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */\r
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */\r
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */\r
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */\r
+#define RCC_AHBENR_TSEN ((uint32_t)0x01000000) /*!< TS clock enable */\r
+\r
+/***************** Bit definition for RCC_APB2ENR register ******************/\r
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */\r
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */\r
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */\r
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */\r
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */\r
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */\r
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */\r
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */\r
+#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */\r
+\r
+/***************** Bit definition for RCC_APB1ENR register ******************/\r
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */\r
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */\r
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */\r
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */\r
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */\r
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */\r
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */\r
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */\r
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */\r
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */\r
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */\r
+#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */\r
+\r
+/******************* Bit definition for RCC_BDCR register *******************/\r
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */\r
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */\r
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */\r
+\r
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */\r
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */\r
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */\r
+\r
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */\r
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+\r
+/*!< RTC congiguration */\r
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */\r
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */\r
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */\r
+\r
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */\r
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */\r
+\r
+/******************* Bit definition for RCC_CSR register ********************/ \r
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */\r
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */\r
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */\r
+#define RCC_CSR_OBL ((uint32_t)0x02000000) /*!< OBL reset flag */\r
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */\r
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */\r
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */\r
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */\r
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */\r
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */\r
+\r
+/******************* Bit definition for RCC_AHBRSTR register ****************/\r
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */\r
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */\r
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */\r
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) /*!< GPIOD clock reset */\r
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) /*!< GPIOF clock reset */\r
+#define RCC_AHBRSTR_TSRST ((uint32_t)0x00100000) /*!< TS clock reset */\r
+\r
+/******************* Bit definition for RCC_CFGR2 register ******************/\r
+/*!< PREDIV1 configuration */\r
+#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */\r
+#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */\r
+#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */\r
+#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */\r
+#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */\r
+#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */\r
+#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */\r
+#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */\r
+#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */\r
+#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */\r
+#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */\r
+#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */\r
+#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */\r
+#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */\r
+#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */\r
+#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */\r
+#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */\r
+\r
+/******************* Bit definition for RCC_CFGR3 register ******************/\r
+/*!< USART1 Clock source selection */\r
+#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */\r
+#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+/*!< I2C1 Clock source selection */\r
+#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */ \r
+#define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */ \r
+#define RCC_CFGR3_ADCSW ((uint32_t)0x00000100) /*!< ADCSW bits */ \r
+\r
+/******************* Bit definition for RCC_CR2 register ********************/\r
+#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */\r
+#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */\r
+#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */\r
+#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */\r
+#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Real-Time Clock (RTC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RTC_TR register *******************/\r
+#define RTC_TR_PM ((uint32_t)0x00400000) /*!< */\r
+#define RTC_TR_HT ((uint32_t)0x00300000) /*!< */\r
+#define RTC_TR_HT_0 ((uint32_t)0x00100000) /*!< */\r
+#define RTC_TR_HT_1 ((uint32_t)0x00200000) /*!< */\r
+#define RTC_TR_HU ((uint32_t)0x000F0000) /*!< */\r
+#define RTC_TR_HU_0 ((uint32_t)0x00010000) /*!< */\r
+#define RTC_TR_HU_1 ((uint32_t)0x00020000) /*!< */\r
+#define RTC_TR_HU_2 ((uint32_t)0x00040000) /*!< */\r
+#define RTC_TR_HU_3 ((uint32_t)0x00080000) /*!< */\r
+#define RTC_TR_MNT ((uint32_t)0x00007000) /*!< */\r
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000) /*!< */\r
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000) /*!< */\r
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000) /*!< */\r
+#define RTC_TR_MNU ((uint32_t)0x00000F00) /*!< */\r
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100) /*!< */\r
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200) /*!< */\r
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400) /*!< */\r
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800) /*!< */\r
+#define RTC_TR_ST ((uint32_t)0x00000070) /*!< */\r
+#define RTC_TR_ST_0 ((uint32_t)0x00000010) /*!< */\r
+#define RTC_TR_ST_1 ((uint32_t)0x00000020) /*!< */\r
+#define RTC_TR_ST_2 ((uint32_t)0x00000040) /*!< */\r
+#define RTC_TR_SU ((uint32_t)0x0000000F) /*!< */\r
+#define RTC_TR_SU_0 ((uint32_t)0x00000001) /*!< */\r
+#define RTC_TR_SU_1 ((uint32_t)0x00000002) /*!< */\r
+#define RTC_TR_SU_2 ((uint32_t)0x00000004) /*!< */\r
+#define RTC_TR_SU_3 ((uint32_t)0x00000008) /*!< */\r
+\r
+/******************** Bits definition for RTC_DR register *******************/\r
+#define RTC_DR_YT ((uint32_t)0x00F00000) /*!< */\r
+#define RTC_DR_YT_0 ((uint32_t)0x00100000) /*!< */\r
+#define RTC_DR_YT_1 ((uint32_t)0x00200000) /*!< */\r
+#define RTC_DR_YT_2 ((uint32_t)0x00400000) /*!< */\r
+#define RTC_DR_YT_3 ((uint32_t)0x00800000) /*!< */\r
+#define RTC_DR_YU ((uint32_t)0x000F0000) /*!< */\r
+#define RTC_DR_YU_0 ((uint32_t)0x00010000) /*!< */\r
+#define RTC_DR_YU_1 ((uint32_t)0x00020000) /*!< */\r
+#define RTC_DR_YU_2 ((uint32_t)0x00040000) /*!< */\r
+#define RTC_DR_YU_3 ((uint32_t)0x00080000) /*!< */\r
+#define RTC_DR_WDU ((uint32_t)0x0000E000) /*!< */\r
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000) /*!< */\r
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000) /*!< */\r
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000) /*!< */\r
+#define RTC_DR_MT ((uint32_t)0x00001000) /*!< */\r
+#define RTC_DR_MU ((uint32_t)0x00000F00) /*!< */\r
+#define RTC_DR_MU_0 ((uint32_t)0x00000100) /*!< */\r
+#define RTC_DR_MU_1 ((uint32_t)0x00000200) /*!< */\r
+#define RTC_DR_MU_2 ((uint32_t)0x00000400) /*!< */\r
+#define RTC_DR_MU_3 ((uint32_t)0x00000800) /*!< */\r
+#define RTC_DR_DT ((uint32_t)0x00000030) /*!< */\r
+#define RTC_DR_DT_0 ((uint32_t)0x00000010) /*!< */\r
+#define RTC_DR_DT_1 ((uint32_t)0x00000020) /*!< */\r
+#define RTC_DR_DU ((uint32_t)0x0000000F) /*!< */\r
+#define RTC_DR_DU_0 ((uint32_t)0x00000001) /*!< */\r
+#define RTC_DR_DU_1 ((uint32_t)0x00000002) /*!< */\r
+#define RTC_DR_DU_2 ((uint32_t)0x00000004) /*!< */\r
+#define RTC_DR_DU_3 ((uint32_t)0x00000008) /*!< */\r
+\r
+/******************** Bits definition for RTC_CR register *******************/\r
+#define RTC_CR_COE ((uint32_t)0x00800000) /*!< */\r
+#define RTC_CR_OSEL ((uint32_t)0x00600000) /*!< */\r
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000) /*!< */\r
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000) /*!< */\r
+#define RTC_CR_POL ((uint32_t)0x00100000) /*!< */\r
+#define RTC_CR_CALSEL ((uint32_t)0x00080000) /*!< */\r
+#define RTC_CR_BCK ((uint32_t)0x00040000) /*!< */\r
+#define RTC_CR_SUB1H ((uint32_t)0x00020000) /*!< */\r
+#define RTC_CR_ADD1H ((uint32_t)0x00010000) /*!< */\r
+#define RTC_CR_TSIE ((uint32_t)0x00008000) /*!< */\r
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000) /*!< */\r
+#define RTC_CR_TSE ((uint32_t)0x00000800) /*!< */\r
+#define RTC_CR_ALRAE ((uint32_t)0x00000100) /*!< */\r
+#define RTC_CR_DCE ((uint32_t)0x00000080) /*!< */\r
+#define RTC_CR_FMT ((uint32_t)0x00000040) /*!< */\r
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020) /*!< */\r
+#define RTC_CR_REFCKON ((uint32_t)0x00000010) /*!< */\r
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008) /*!< */\r
+\r
+/******************** Bits definition for RTC_ISR register ******************/\r
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000) /*!< */\r
+#define RTC_ISR_TAMP3F ((uint32_t)0x00008000) /*!< */\r
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000) /*!< */\r
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000) /*!< */\r
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000) /*!< */\r
+#define RTC_ISR_TSF ((uint32_t)0x00000800) /*!< */\r
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100) /*!< */\r
+#define RTC_ISR_INIT ((uint32_t)0x00000080) /*!< */\r
+#define RTC_ISR_INITF ((uint32_t)0x00000040) /*!< */\r
+#define RTC_ISR_RSF ((uint32_t)0x00000020) /*!< */\r
+#define RTC_ISR_INITS ((uint32_t)0x00000010) /*!< */\r
+#define RTC_ISR_SHPF ((uint32_t)0x00000008) /*!< */\r
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001) /*!< */\r
+\r
+/******************** Bits definition for RTC_PRER register *****************/\r
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) /*!< */\r
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) /*!< */\r
+\r
+/******************** Bits definition for RTC_ALRMAR register ***************/\r
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) /*!< */\r
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) /*!< */\r
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000) /*!< */\r
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) /*!< */\r
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) /*!< */\r
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000) /*!< */\r
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) /*!< */\r
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) /*!< */\r
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) /*!< */\r
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) /*!< */\r
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) /*!< */\r
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000) /*!< */\r
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000) /*!< */\r
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) /*!< */\r
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) /*!< */\r
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000) /*!< */\r
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) /*!< */\r
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) /*!< */\r
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) /*!< */\r
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) /*!< */\r
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) /*!< */\r
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000) /*!< */\r
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) /*!< */\r
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) /*!< */\r
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) /*!< */\r
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) /*!< */\r
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) /*!< */\r
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) /*!< */\r
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) /*!< */\r
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) /*!< */\r
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) /*!< */\r
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070) /*!< */\r
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) /*!< */\r
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) /*!< */\r
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) /*!< */\r
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F) /*!< */\r
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) /*!< */\r
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) /*!< */\r
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) /*!< */\r
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) /*!< */\r
+\r
+/******************** Bits definition for RTC_WPR register ******************/\r
+#define RTC_WPR_KEY ((uint32_t)0x000000FF) /*!< */\r
+\r
+/******************** Bits definition for RTC_SSR register ******************/\r
+#define RTC_SSR_SS ((uint32_t)0x0003FFFF) /*!< */\r
+\r
+/******************** Bits definition for RTC_SHIFTR register ***************/\r
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) /*!< */\r
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) /*!< */\r
+\r
+/******************** Bits definition for RTC_TSTR register *****************/\r
+#define RTC_TSTR_PM ((uint32_t)0x00400000) /*!< */\r
+#define RTC_TSTR_HT ((uint32_t)0x00300000) /*!< */\r
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000) /*!< */\r
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000) /*!< */\r
+#define RTC_TSTR_HU ((uint32_t)0x000F0000) /*!< */\r
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000) /*!< */\r
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000) /*!< */\r
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000) /*!< */\r
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000) /*!< */\r
+#define RTC_TSTR_MNT ((uint32_t)0x00007000) /*!< */\r
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) /*!< */\r
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) /*!< */\r
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) /*!< */\r
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00) /*!< */\r
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) /*!< */\r
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) /*!< */\r
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) /*!< */\r
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) /*!< */\r
+#define RTC_TSTR_ST ((uint32_t)0x00000070) /*!< */\r
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010) /*!< */\r
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020) /*!< */\r
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040) /*!< */\r
+#define RTC_TSTR_SU ((uint32_t)0x0000000F) /*!< */\r
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001) /*!< */\r
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002) /*!< */\r
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004) /*!< */\r
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008) /*!< */\r
+\r
+/******************** Bits definition for RTC_TSDR register *****************/\r
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000) /*!< */\r
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) /*!< */\r
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) /*!< */\r
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) /*!< */\r
+#define RTC_TSDR_MT ((uint32_t)0x00001000) /*!< */\r
+#define RTC_TSDR_MU ((uint32_t)0x00000F00) /*!< */\r
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100) /*!< */\r
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200) /*!< */\r
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400) /*!< */\r
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800) /*!< */\r
+#define RTC_TSDR_DT ((uint32_t)0x00000030) /*!< */\r
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010) /*!< */\r
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020) /*!< */\r
+#define RTC_TSDR_DU ((uint32_t)0x0000000F) /*!< */\r
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001) /*!< */\r
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002) /*!< */\r
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004) /*!< */\r
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008) /*!< */\r
+\r
+/******************** Bits definition for RTC_TSSSR register ****************/\r
+#define RTC_TSSSR_SS ((uint32_t)0x0003FFFF)\r
+\r
+/******************** Bits definition for RTC_CAL register *****************/\r
+#define RTC_CAL_CALP ((uint32_t)0x00008000) /*!< */\r
+#define RTC_CAL_CALW8 ((uint32_t)0x00004000) /*!< */\r
+#define RTC_CAL_CALW16 ((uint32_t)0x00002000) /*!< */\r
+#define RTC_CAL_CALM ((uint32_t)0x000001FF) /*!< */\r
+#define RTC_CAL_CALM_0 ((uint32_t)0x00000001) /*!< */\r
+#define RTC_CAL_CALM_1 ((uint32_t)0x00000002) /*!< */\r
+#define RTC_CAL_CALM_2 ((uint32_t)0x00000004) /*!< */\r
+#define RTC_CAL_CALM_3 ((uint32_t)0x00000008) /*!< */\r
+#define RTC_CAL_CALM_4 ((uint32_t)0x00000010) /*!< */\r
+#define RTC_CAL_CALM_5 ((uint32_t)0x00000020) /*!< */\r
+#define RTC_CAL_CALM_6 ((uint32_t)0x00000040) /*!< */\r
+#define RTC_CAL_CALM_7 ((uint32_t)0x00000080) /*!< */\r
+#define RTC_CAL_CALM_8 ((uint32_t)0x00000100) /*!< */\r
+\r
+/******************** Bits definition for RTC_TAFCR register ****************/\r
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) /*!< */\r
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) /*!< */\r
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) /*!< */\r
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) /*!< */\r
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) /*!< */\r
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) /*!< */\r
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) /*!< */\r
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) /*!< */\r
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) /*!< */\r
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) /*!< */\r
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) /*!< */\r
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) /*!< */\r
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) /*!< */\r
+#define RTC_TAFCR_TAMP3EDGE ((uint32_t)0x00000040) /*!< */\r
+#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020) /*!< */\r
+#define RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010) /*!< */\r
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) /*!< */\r
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) /*!< */\r
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) /*!< */\r
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) /*!< */\r
+\r
+/******************** Bits definition for RTC_ALRMASSR register *************/\r
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) /*!< */\r
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) /*!< */\r
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) /*!< */\r
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) /*!< */\r
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) /*!< */\r
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) /*!< */\r
+\r
+/******************** Bits definition for RTC_BKP0R register ****************/\r
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF) /*!< */\r
+\r
+/******************** Bits definition for RTC_BKP1R register ****************/\r
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF) /*!< */\r
+\r
+/******************** Bits definition for RTC_BKP2R register ****************/\r
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF) /*!< */\r
+\r
+/******************** Bits definition for RTC_BKP3R register ****************/\r
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF) /*!< */\r
+\r
+/******************** Bits definition for RTC_BKP4R register ****************/\r
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF) /*!< */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Peripheral Interface (SPI) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for SPI_CR1 register ********************/\r
+#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */\r
+#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */\r
+#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */\r
+#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */\r
+#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */\r
+#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */\r
+#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */\r
+#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */\r
+#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */\r
+#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */\r
+#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */\r
+#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */\r
+#define SPI_CR1_CRCL ((uint16_t)0x0800) /*!< CRC Length */\r
+#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */\r
+#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */\r
+#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */\r
+#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */\r
+\r
+/******************* Bit definition for SPI_CR2 register ********************/\r
+#define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /*!< Rx Buffer DMA Enable */\r
+#define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /*!< Tx Buffer DMA Enable */\r
+#define SPI_CR2_SSOE ((uint16_t)0x0004) /*!< SS Output Enable */\r
+#define SPI_CR2_NSSP ((uint16_t)0x0008) /*!< NSS pulse management Enable */\r
+#define SPI_CR2_FRF ((uint16_t)0x0010) /*!< Frame Format Enable */\r
+#define SPI_CR2_ERRIE ((uint16_t)0x0020) /*!< Error Interrupt Enable */\r
+#define SPI_CR2_RXNEIE ((uint16_t)0x0040) /*!< RX buffer Not Empty Interrupt Enable */\r
+#define SPI_CR2_TXEIE ((uint16_t)0x0080) /*!< Tx buffer Empty Interrupt Enable */\r
+#define SPI_CR2_DS ((uint16_t)0x0F00) /*!< DS[3:0] Data Size */\r
+#define SPI_CR2_DS_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define SPI_CR2_DS_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+#define SPI_CR2_DS_2 ((uint16_t)0x0400) /*!< Bit 2 */\r
+#define SPI_CR2_DS_3 ((uint16_t)0x0800) /*!< Bit 3 */\r
+#define SPI_CR2_FRXTH ((uint16_t)0x1000) /*!< FIFO reception Threshold */\r
+#define SPI_CR2_LDMARX ((uint16_t)0x2000) /*!< Last DMA transfer for reception */\r
+#define SPI_CR2_LDMATX ((uint16_t)0x4000) /*!< Last DMA transfer for transmission */\r
+\r
+/******************** Bit definition for SPI_SR register ********************/\r
+#define SPI_SR_RXNE ((uint16_t)0x0001) /*!< Receive buffer Not Empty */\r
+#define SPI_SR_TXE ((uint16_t)0x0002) /*!< Transmit buffer Empty */\r
+#define SPI_SR_CHSIDE ((uint16_t)0x0004) /*!< Channel side */\r
+#define SPI_SR_UDR ((uint16_t)0x0008) /*!< Underrun flag */\r
+#define SPI_SR_CRCERR ((uint16_t)0x0010) /*!< CRC Error flag */\r
+#define SPI_SR_MODF ((uint16_t)0x0020) /*!< Mode fault */\r
+#define SPI_SR_OVR ((uint16_t)0x0040) /*!< Overrun flag */\r
+#define SPI_SR_BSY ((uint16_t)0x0080) /*!< Busy flag */\r
+#define SPI_SR_FRE ((uint16_t)0x0100) /*!< TI frame format error */\r
+#define SPI_SR_FRLVL ((uint16_t)0x0600) /*!< FIFO Reception Level */\r
+#define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /*!< Bit 0 */\r
+#define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /*!< Bit 1 */\r
+#define SPI_SR_FTLVL ((uint16_t)0x1800) /*!< FIFO Transmission Level */\r
+#define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /*!< Bit 0 */\r
+#define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /*!< Bit 1 */ \r
+\r
+/******************** Bit definition for SPI_DR register ********************/\r
+#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */\r
+\r
+/******************* Bit definition for SPI_CRCPR register ******************/\r
+#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */\r
+\r
+/****************** Bit definition for SPI_RXCRCR register ******************/\r
+#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */\r
+\r
+/****************** Bit definition for SPI_TXCRCR register ******************/\r
+#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */\r
+\r
+/****************** Bit definition for SPI_I2SCFGR register *****************/\r
+#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */\r
+#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */\r
+#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */\r
+#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */\r
+#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */\r
+#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */\r
+#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */\r
+#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */\r
+#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */\r
+\r
+/****************** Bit definition for SPI_I2SPR register *******************/\r
+#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */\r
+#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */\r
+#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* System Configuration (SYSCFG) */\r
+/* */\r
+/******************************************************************************/\r
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/\r
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */\r
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */\r
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */\r
+#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */\r
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */\r
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */\r
+#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */\r
+#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */\r
+#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */\r
+#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */\r
+#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */\r
+#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/\r
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */\r
+\r
+/** \r
+ * @brief EXTI0 configuration \r
+ */\r
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0003) /*!< PF[0] pin */\r
+\r
+/** \r
+ * @brief EXTI1 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0030) /*!< PF[1] pin */\r
+\r
+/** \r
+ * @brief EXTI2 configuration \r
+ */\r
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */\r
+\r
+/** \r
+ * @brief EXTI3 configuration \r
+ */\r
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/\r
+#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */\r
+\r
+/** \r
+ * @brief EXTI4 configuration \r
+ */\r
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0003) /*!< PF[4] pin */\r
+\r
+/** \r
+ * @brief EXTI5 configuration \r
+ */\r
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0030) /*!< PF[5] pin */\r
+\r
+/** \r
+ * @brief EXTI6 configuration \r
+ */\r
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0300) /*!< PF[6] pin */\r
+\r
+/** \r
+ * @brief EXTI7 configuration \r
+ */\r
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x3000) /*!< PF[7] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/\r
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */\r
+\r
+/** \r
+ * @brief EXTI8 configuration \r
+ */\r
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */\r
+\r
+/** \r
+ * @brief EXTI9 configuration \r
+ */\r
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */\r
+\r
+/** \r
+ * @brief EXTI10 configuration \r
+ */\r
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */\r
+\r
+/** \r
+ * @brief EXTI11 configuration \r
+ */\r
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/\r
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */\r
+\r
+/** \r
+ * @brief EXTI12 configuration \r
+ */\r
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */\r
+\r
+/** \r
+ * @brief EXTI13 configuration \r
+ */\r
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */\r
+\r
+/** \r
+ * @brief EXTI14 configuration \r
+ */\r
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */\r
+\r
+/** \r
+ * @brief EXTI15 configuration \r
+ */\r
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */\r
+\r
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/\r
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */\r
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */\r
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */\r
+#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Timers (TIM) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for TIM_CR1 register ********************/\r
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */\r
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */\r
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */\r
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */\r
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */\r
+\r
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */\r
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */\r
+\r
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */\r
+\r
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */\r
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for TIM_CR2 register ********************/\r
+#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */\r
+#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */\r
+#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */\r
+\r
+#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */\r
+#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */\r
+#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */\r
+#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */\r
+#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */\r
+#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */\r
+#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */\r
+#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */\r
+\r
+/******************* Bit definition for TIM_SMCR register *******************/\r
+#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!< OCREF clear selection */\r
+\r
+#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */\r
+#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */\r
+\r
+#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */\r
+#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
+#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
+\r
+#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */\r
+#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */\r
+\r
+/******************* Bit definition for TIM_DIER register *******************/\r
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */\r
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */\r
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */\r
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */\r
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */\r
+#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */\r
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */\r
+#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */\r
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */\r
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */\r
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */\r
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */\r
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */\r
+#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */\r
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */\r
+\r
+/******************** Bit definition for TIM_SR register ********************/\r
+#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */\r
+#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */\r
+#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */\r
+#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */\r
+#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */\r
+#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */\r
+#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */\r
+#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */\r
+#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */\r
+#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */\r
+#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */\r
+#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */\r
+\r
+/******************* Bit definition for TIM_EGR register ********************/\r
+#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */\r
+#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */\r
+#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */\r
+#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */\r
+#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */\r
+#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */\r
+#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */\r
+#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */\r
+\r
+/****************** Bit definition for TIM_CCMR1 register *******************/\r
+#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */\r
+#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */\r
+\r
+#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */\r
+\r
+#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */\r
+#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */\r
+\r
+#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
+\r
+/****************** Bit definition for TIM_CCMR2 register *******************/\r
+#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */\r
+#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */\r
+\r
+#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */\r
+\r
+#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for TIM_CCER register *******************/\r
+#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */\r
+#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */\r
+#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */\r
+#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */\r
+#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */\r
+#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */\r
+#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */\r
+#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */\r
+#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */\r
+#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */\r
+#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */\r
+\r
+/******************* Bit definition for TIM_CNT register ********************/\r
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */\r
+\r
+/******************* Bit definition for TIM_PSC register ********************/\r
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */\r
+\r
+/******************* Bit definition for TIM_ARR register ********************/\r
+#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */\r
+\r
+/******************* Bit definition for TIM_RCR register ********************/\r
+#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */\r
+\r
+/******************* Bit definition for TIM_CCR1 register *******************/\r
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */\r
+\r
+/******************* Bit definition for TIM_CCR2 register *******************/\r
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */\r
+\r
+/******************* Bit definition for TIM_CCR3 register *******************/\r
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */\r
+\r
+/******************* Bit definition for TIM_CCR4 register *******************/\r
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */\r
+\r
+/******************* Bit definition for TIM_BDTR register *******************/\r
+#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
+#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */\r
+#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */\r
+\r
+#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */\r
+#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */\r
+#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */\r
+#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */\r
+#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */\r
+#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */\r
+#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */\r
+\r
+/******************* Bit definition for TIM_DCR register ********************/\r
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+\r
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for TIM_DMAR register *******************/\r
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */\r
+\r
+/******************* Bit definition for TIM_OR register *********************/\r
+#define TIM14_OR_TI1_RMP ((uint16_t)0x00C0) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */\r
+#define TIM14_OR_TI1_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */\r
+#define TIM14_OR_TI1_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for USART_CR1 register *******************/\r
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */\r
+#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */\r
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */\r
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */\r
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */\r
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */\r
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */\r
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */\r
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */\r
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */\r
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */\r
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */\r
+#define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */\r
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */\r
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */\r
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */\r
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\r
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */\r
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */\r
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */\r
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */\r
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */\r
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */\r
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */\r
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */\r
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */\r
+\r
+/****************** Bit definition for USART_CR2 register *******************/\r
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */\r
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */\r
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */\r
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */\r
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */\r
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */\r
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */\r
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */\r
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */\r
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */\r
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */\r
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */\r
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */\r
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */\r
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/\r
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\r
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */\r
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */\r
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */\r
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */\r
+\r
+/****************** Bit definition for USART_CR3 register *******************/\r
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */\r
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */\r
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */\r
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */\r
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */\r
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */\r
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */\r
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */\r
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */\r
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */\r
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */\r
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */\r
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */\r
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */\r
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */\r
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\r
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */\r
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */\r
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */\r
+#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */\r
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */\r
+\r
+/****************** Bit definition for USART_BRR register *******************/\r
+#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */\r
+#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */\r
+\r
+/****************** Bit definition for USART_GTPR register ******************/\r
+#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */\r
+#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */\r
+\r
+\r
+/******************* Bit definition for USART_RTOR register *****************/\r
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */\r
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */\r
+\r
+/******************* Bit definition for USART_RQR register ******************/\r
+#define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */\r
+#define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */\r
+#define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */\r
+#define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */\r
+#define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */\r
+\r
+/******************* Bit definition for USART_ISR register ******************/\r
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */\r
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */\r
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */\r
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */\r
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */\r
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */\r
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */\r
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */\r
+#define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */\r
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */\r
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */\r
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */\r
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */\r
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */\r
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */\r
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */\r
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */\r
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */\r
+#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */\r
+#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */\r
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */\r
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */\r
+\r
+/******************* Bit definition for USART_ICR register ******************/\r
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */\r
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */\r
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */\r
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */\r
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */\r
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */\r
+#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */\r
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */\r
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */\r
+#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */\r
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */\r
+#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */\r
+\r
+/******************* Bit definition for USART_RDR register ******************/\r
+#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */\r
+\r
+/******************* Bit definition for USART_TDR register ******************/\r
+#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Window WATCHDOG (WWDG) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for WWDG_CR register ********************/\r
+#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */\r
+#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */\r
+#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */\r
+#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */\r
+#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */\r
+#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */\r
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */\r
+\r
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */\r
+\r
+/******************* Bit definition for WWDG_CFR register *******************/\r
+#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */\r
+#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */\r
+#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */\r
+#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */\r
+#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */\r
+#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */\r
+#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */\r
+#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */\r
+\r
+#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */\r
+#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */\r
+#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */\r
+\r
+#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */\r
+\r
+/******************* Bit definition for WWDG_SR register ********************/\r
+#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */ \r
+\r
+#ifdef USE_STDPERIPH_DRIVER\r
+ #include "stm32f0xx_conf.h"\r
+#endif\r
+\r
+/** @addtogroup Exported_macro\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F0XX_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f0xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Header File.\r
+ ****************************************************************************** \r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f0xx_system\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @brief Define to prevent recursive inclusion\r
+ */\r
+#ifndef __SYSTEM_STM32F0XX_H\r
+#define __SYSTEM_STM32F0XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/** @addtogroup STM32F0xx_System_Includes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup STM32F0xx_System_Exported_types\r
+ * @{\r
+ */\r
+\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F0xx_System_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F0xx_System_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F0xx_System_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+extern void SystemInit(void);\r
+extern void SystemCoreClockUpdate(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__SYSTEM_STM32F0XX_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
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+<td style="padding: 0cm;" valign="top">\r
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">\r
+<tbody>\r
+ <tr>\r
+ <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../../Release_Notes.html">Back to Release page</a></span></td>\r
+ </tr>\r
+<tr style="">\r
+<td style="padding: 1.5pt;">\r
+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release\r
+Notes for STM32F0xx CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>\r
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>\r
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>\r
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">\r
+<tbody>\r
+<tr>\r
+<td style="padding: 0cm;" valign="top">\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>\r
+<ol style="margin-top: 0cm;" start="1" type="1">\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F0xx CMSIS\r
+update History</a><o:p></o:p></span></li>\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>\r
+</ol>\r
+<span style="font-family: "Times New Roman";"></span>\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F0xx CMSIS\r
+update History</span></h2>\r
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC1 / 27-January-2012<o:p></o:p></span></h3>\r
+ <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+Changes<o:p></o:p></span></u></b></p>\r
+\r
+ <ul style="margin-top: 0cm;" type="square">\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Second release for </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32F0xx</span> devices</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">All source \r
+files: update disclaimer to add reference to the new license agreement</span></li>\r
+ <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update all peripherals bits definitions<br>\r
+</span></li>\r
+ </ul>\r
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V0.1.0 / 30-November-2011<o:p></o:p></span></h3>\r
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+Changes<o:p></o:p></span></u></b></p>\r
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First Alpha release for </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32F0xx</span> devices</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span><span style="font-weight: bold; font-style: italic;"></span></span>\r
+\r
+<ul style="margin-top: 0in;" type="disc">\r
+</ul>\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><small><span style="font-family: Verdana;">The use of this STM32\r
+Firmware is governed by the terms and conditions of the License\r
+Agreement available in the root of this package.</span></small>\r
+\r
+<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">\r
+<hr align="center" size="2" width="100%"></span></div>\r
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For\r
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX Mx) 32-Bit Microcontrollers\r
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+</div>\r
+<p class="MsoNormal"><o:p> </o:p></p>\r
+</div>\r
+</body></html>
\ No newline at end of file
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file startup_stm32f0xx.s\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief STM32F0xx Devices vector table for Atollic toolchain.\r
+ * This module performs:\r
+ * - Set the initial SP\r
+ * - Set the initial PC == Reset_Handler,\r
+ * - Set the vector table entries with the exceptions ISR address\r
+ * - Configure the clock system\r
+ * - Branches to main in the C library (which eventually\r
+ * calls main()).\r
+ * After Reset the Cortex-M0 processor is in Thread mode,\r
+ * priority is Privileged, and the Stack is set to Main.\r
+ *******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+ .syntax unified\r
+ .cpu cortex-m0\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+.global g_pfnVectors\r
+.global Default_Handler\r
+\r
+/* start address for the initialization values of the .data section.\r
+defined in linker script */\r
+.word _sidata\r
+/* start address for the .data section. defined in linker script */\r
+.word _sdata\r
+/* end address for the .data section. defined in linker script */\r
+.word _edata\r
+/* start address for the .bss section. defined in linker script */\r
+.word _sbss\r
+/* end address for the .bss section. defined in linker script */\r
+.word _ebss\r
+\r
+.equ BootRAM, 0xF108F85F\r
+/**\r
+ * @brief This is the code that gets called when the processor first\r
+ * starts execution following a reset event. Only the absolutely\r
+ * necessary set is performed, after which the application\r
+ * supplied main() routine is called.\r
+ * @param None\r
+ * @retval : None\r
+*/\r
+\r
+ .section .text.Reset_Handler\r
+ .weak Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler:\r
+\r
+/* Copy the data segment initializers from flash to SRAM */\r
+ movs r1, #0\r
+ b LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+ ldr r3, =_sidata\r
+ ldr r3, [r3, r1]\r
+ str r3, [r0, r1]\r
+ adds r1, r1, #4\r
+\r
+LoopCopyDataInit:\r
+ ldr r0, =_sdata\r
+ ldr r3, =_edata\r
+ adds r2, r0, r1\r
+ cmp r2, r3\r
+ bcc CopyDataInit\r
+ ldr r2, =_sbss\r
+ b LoopFillZerobss\r
+/* Zero fill the bss segment. */\r
+FillZerobss:\r
+ movs r3, #0\r
+ str r3, [r2], #4\r
+\r
+LoopFillZerobss:\r
+ ldr r3, = _ebss\r
+ cmp r2, r3\r
+ bcc FillZerobss\r
+\r
+/* Call the clock system intitialization function.*/\r
+ bl SystemInit\r
+/* Call static constructors */\r
+ bl __libc_init_array\r
+/* Call the application's entry point.*/\r
+ bl main\r
+ bx lr\r
+.size Reset_Handler, .-Reset_Handler\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor receives an\r
+ * unexpected interrupt. This simply enters an infinite loop, preserving\r
+ * the system state for examination by a debugger.\r
+ *\r
+ * @param None\r
+ * @retval : None\r
+*/\r
+ .section .text.Default_Handler,"ax",%progbits\r
+Default_Handler:\r
+Infinite_Loop:\r
+ b Infinite_Loop\r
+ .size Default_Handler, .-Default_Handler\r
+/******************************************************************************\r
+*\r
+* The minimal vector table for a Cortex M0. Note that the proper constructs\r
+* must be placed on this to ensure that it ends up at physical address\r
+* 0x0000.0000.\r
+*\r
+******************************************************************************/\r
+ .section .isr_vector,"a",%progbits\r
+ .type g_pfnVectors, %object\r
+ .size g_pfnVectors, .-g_pfnVectors\r
+\r
+\r
+g_pfnVectors:\r
+ .word _estack\r
+ .word Reset_Handler\r
+ .word NMI_Handler\r
+ .word HardFault_Handler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word SVC_Handler\r
+ .word 0\r
+ .word 0\r
+ .word PendSV_Handler\r
+ .word SysTick_Handler\r
+ .word WWDG_IRQHandler\r
+ .word PVD_IRQHandler\r
+ .word RTC_IRQHandler\r
+ .word FLASH_IRQHandler\r
+ .word RCC_IRQHandler\r
+ .word EXTI0_1_IRQHandler\r
+ .word EXTI2_3_IRQHandler\r
+ .word EXTI4_15_IRQHandler\r
+ .word TS_IRQHandler\r
+ .word DMA1_Channel1_IRQHandler\r
+ .word DMA1_Channel2_3_IRQHandler\r
+ .word DMA1_Channel4_5_IRQHandler\r
+ .word ADC1_COMP_IRQHandler \r
+ .word TIM1_BRK_UP_TRG_COM_IRQHandler\r
+ .word TIM1_CC_IRQHandler\r
+ .word TIM2_IRQHandler\r
+ .word TIM3_IRQHandler\r
+ .word TIM6_DAC_IRQHandler\r
+ .word 0 \r
+ .word TIM14_IRQHandler\r
+ .word TIM15_IRQHandler\r
+ .word TIM16_IRQHandler\r
+ .word TIM17_IRQHandler\r
+ .word I2C1_IRQHandler\r
+ .word I2C2_IRQHandler\r
+ .word SPI1_IRQHandler\r
+ .word SPI2_IRQHandler\r
+ .word USART1_IRQHandler\r
+ .word USART2_IRQHandler\r
+ .word 0\r
+ .word CEC_IRQHandler\r
+ .word 0\r
+ .word BootRAM /* @0x108. This is for boot in RAM mode for \r
+ STM32F0xx devices. */\r
+\r
+/*******************************************************************************\r
+*\r
+* Provide weak aliases for each Exception handler to the Default_Handler.\r
+* As they are weak aliases, any function with the same name will override\r
+* this definition.\r
+*\r
+*******************************************************************************/\r
+\r
+ .weak NMI_Handler\r
+ .thumb_set NMI_Handler,Default_Handler\r
+\r
+ .weak HardFault_Handler\r
+ .thumb_set HardFault_Handler,Default_Handler\r
+\r
+ .weak SVC_Handler\r
+ .thumb_set SVC_Handler,Default_Handler\r
+\r
+ .weak PendSV_Handler\r
+ .thumb_set PendSV_Handler,Default_Handler\r
+\r
+ .weak SysTick_Handler\r
+ .thumb_set SysTick_Handler,Default_Handler\r
+\r
+ .weak WWDG_IRQHandler\r
+ .thumb_set WWDG_IRQHandler,Default_Handler\r
+\r
+ .weak PVD_IRQHandler\r
+ .thumb_set PVD_IRQHandler,Default_Handler\r
+ \r
+ .weak RTC_IRQHandler\r
+ .thumb_set RTC_IRQHandler,Default_Handler\r
+ \r
+ .weak FLASH_IRQHandler\r
+ .thumb_set FLASH_IRQHandler,Default_Handler\r
+ \r
+ .weak RCC_IRQHandler\r
+ .thumb_set RCC_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI0_1_IRQHandler\r
+ .thumb_set EXTI0_1_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI2_3_IRQHandler\r
+ .thumb_set EXTI2_3_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI4_15_IRQHandler\r
+ .thumb_set EXTI4_15_IRQHandler,Default_Handler\r
+ \r
+ .weak TS_IRQHandler\r
+ .thumb_set TS_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Channel1_IRQHandler\r
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Channel2_3_IRQHandler\r
+ .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Channel4_5_IRQHandler\r
+ .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler\r
+ \r
+ .weak ADC1_COMP_IRQHandler\r
+ .thumb_set ADC1_COMP_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM1_BRK_UP_TRG_COM_IRQHandler\r
+ .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM1_CC_IRQHandler\r
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM2_IRQHandler\r
+ .thumb_set TIM2_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM3_IRQHandler\r
+ .thumb_set TIM3_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM6_DAC_IRQHandler\r
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM14_IRQHandler\r
+ .thumb_set TIM14_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM15_IRQHandler\r
+ .thumb_set TIM15_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM16_IRQHandler\r
+ .thumb_set TIM16_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM17_IRQHandler\r
+ .thumb_set TIM17_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C1_IRQHandler\r
+ .thumb_set I2C1_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C2_IRQHandler\r
+ .thumb_set I2C2_IRQHandler,Default_Handler\r
+ \r
+ .weak SPI1_IRQHandler\r
+ .thumb_set SPI1_IRQHandler,Default_Handler\r
+ \r
+ .weak SPI2_IRQHandler\r
+ .thumb_set SPI2_IRQHandler,Default_Handler\r
+ \r
+ .weak USART1_IRQHandler\r
+ .thumb_set USART1_IRQHandler,Default_Handler\r
+ \r
+ .weak USART2_IRQHandler\r
+ .thumb_set USART2_IRQHandler,Default_Handler\r
+ \r
+ .weak CEC_IRQHandler\r
+ .thumb_set CEC_IRQHandler,Default_Handler\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************\r
+;* File Name : startup_stm32f0xx.s\r
+;* Author : MCD Application Team\r
+;* Version : V1.0.0RC1\r
+;* Date : 27-January-2012\r
+;* Description : STM32F0xx Devices vector table for MDK-ARM toolchain.\r
+;* This module performs:\r
+;* - Set the initial SP\r
+;* - Set the initial PC == Reset_Handler\r
+;* - Set the vector table entries with the exceptions ISR address\r
+;* - Branches to __main in the C library (which eventually\r
+;* calls main()).\r
+;* After Reset the CortexM0 processor is in Thread mode,\r
+;* priority is Privileged, and the Stack is set to Main.\r
+;* <<< Use Configuration Wizard in Context Menu >>> \r
+;*******************************************************************************\r
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+; FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+; LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+;*******************************************************************************\r
+\r
+; Amount of memory (in bytes) allocated for Stack\r
+; Tailor this value to your application needs\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000400\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000200\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __Vectors_End\r
+ EXPORT __Vectors_Size\r
+\r
+__Vectors DCD __initial_sp ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ DCD WWDG_IRQHandler ; Window Watchdog\r
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect\r
+ DCD RTC_IRQHandler ; RTC through EXTI Line\r
+ DCD FLASH_IRQHandler ; FLASH\r
+ DCD RCC_IRQHandler ; RCC\r
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1\r
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3\r
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15\r
+ DCD TS_IRQHandler ; TS\r
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1\r
+ DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3\r
+ DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5\r
+ DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 \r
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation\r
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare\r
+ DCD TIM2_IRQHandler ; TIM2\r
+ DCD TIM3_IRQHandler ; TIM3\r
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC\r
+ DCD 0 ; Reserved\r
+ DCD TIM14_IRQHandler ; TIM14\r
+ DCD TIM15_IRQHandler ; TIM15\r
+ DCD TIM16_IRQHandler ; TIM16\r
+ DCD TIM17_IRQHandler ; TIM17\r
+ DCD I2C1_IRQHandler ; I2C1\r
+ DCD I2C2_IRQHandler ; I2C2\r
+ DCD SPI1_IRQHandler ; SPI1\r
+ DCD SPI2_IRQHandler ; SPI2\r
+ DCD USART1_IRQHandler ; USART1\r
+ DCD USART2_IRQHandler ; USART2\r
+ DCD 0 ; Reserved\r
+ DCD CEC_IRQHandler ; CEC\r
+ DCD 0 ; Reserved\r
+ \r
+__Vectors_End\r
+\r
+__Vectors_Size EQU __Vectors_End - __Vectors\r
+\r
+ AREA |.text|, CODE, READONLY\r
+\r
+; Reset handler routine\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT __main\r
+ IMPORT SystemInit \r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__main\r
+ BX R0\r
+ ENDP\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SVC_Handler PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+PendSV_Handler PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SysTick_Handler PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+Default_Handler PROC\r
+\r
+ EXPORT WWDG_IRQHandler [WEAK]\r
+ EXPORT PVD_IRQHandler [WEAK]\r
+ EXPORT RTC_IRQHandler [WEAK]\r
+ EXPORT FLASH_IRQHandler [WEAK]\r
+ EXPORT RCC_IRQHandler [WEAK]\r
+ EXPORT EXTI0_1_IRQHandler [WEAK]\r
+ EXPORT EXTI2_3_IRQHandler [WEAK]\r
+ EXPORT EXTI4_15_IRQHandler [WEAK]\r
+ EXPORT TS_IRQHandler [WEAK]\r
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]\r
+ EXPORT DMA1_Channel2_3_IRQHandler [WEAK]\r
+ EXPORT DMA1_Channel4_5_IRQHandler [WEAK]\r
+ EXPORT ADC1_COMP_IRQHandler [WEAK]\r
+ EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]\r
+ EXPORT TIM1_CC_IRQHandler [WEAK]\r
+ EXPORT TIM2_IRQHandler [WEAK]\r
+ EXPORT TIM3_IRQHandler [WEAK]\r
+ EXPORT TIM6_DAC_IRQHandler [WEAK]\r
+ EXPORT TIM14_IRQHandler [WEAK]\r
+ EXPORT TIM15_IRQHandler [WEAK]\r
+ EXPORT TIM16_IRQHandler [WEAK]\r
+ EXPORT TIM17_IRQHandler [WEAK]\r
+ EXPORT I2C1_IRQHandler [WEAK]\r
+ EXPORT I2C2_IRQHandler [WEAK]\r
+ EXPORT SPI1_IRQHandler [WEAK]\r
+ EXPORT SPI2_IRQHandler [WEAK]\r
+ EXPORT USART1_IRQHandler [WEAK]\r
+ EXPORT USART2_IRQHandler [WEAK]\r
+ EXPORT CEC_IRQHandler [WEAK]\r
+\r
+\r
+WWDG_IRQHandler\r
+PVD_IRQHandler\r
+RTC_IRQHandler\r
+FLASH_IRQHandler\r
+RCC_IRQHandler\r
+EXTI0_1_IRQHandler\r
+EXTI2_3_IRQHandler\r
+EXTI4_15_IRQHandler\r
+TS_IRQHandler\r
+DMA1_Channel1_IRQHandler\r
+DMA1_Channel2_3_IRQHandler\r
+DMA1_Channel4_5_IRQHandler\r
+ADC1_COMP_IRQHandler \r
+TIM1_BRK_UP_TRG_COM_IRQHandler\r
+TIM1_CC_IRQHandler\r
+TIM2_IRQHandler\r
+TIM3_IRQHandler\r
+TIM6_DAC_IRQHandler\r
+TIM14_IRQHandler\r
+TIM15_IRQHandler\r
+TIM16_IRQHandler\r
+TIM17_IRQHandler\r
+I2C1_IRQHandler\r
+I2C2_IRQHandler\r
+SPI1_IRQHandler\r
+SPI2_IRQHandler\r
+USART1_IRQHandler\r
+USART2_IRQHandler\r
+CEC_IRQHandler \r
+\r
+ B .\r
+\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+;*******************************************************************************\r
+; User Stack and Heap initialization\r
+;*******************************************************************************\r
+ IF :DEF:__MICROLIB \r
+ \r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+ \r
+ ELSE\r
+ \r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+ \r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+ END\r
+\r
+;******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE*****\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file startup_stm32f0xx.s\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief STM32F0xx Devices vector table for RIDE7 toolchain.\r
+ * This module performs:\r
+ * - Set the initial SP\r
+ * - Set the initial PC == Reset_Handler,\r
+ * - Set the vector table entries with the exceptions ISR address\r
+ * - Branches to main in the C library (which eventually\r
+ * calls main()).\r
+ * After Reset the Cortex-M0 processor is in Thread mode,\r
+ * priority is Privileged, and the Stack is set to Main.\r
+ *******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+ \r
+ .syntax unified\r
+ .cpu cortex-m0\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+.global g_pfnVectors\r
+.global Default_Handler\r
+\r
+/* start address for the initialization values of the .data section. \r
+defined in linker script */\r
+.word _sidata\r
+/* start address for the .data section. defined in linker script */ \r
+.word _sdata\r
+/* end address for the .data section. defined in linker script */\r
+.word _edata\r
+/* start address for the .bss section. defined in linker script */\r
+.word _sbss\r
+/* end address for the .bss section. defined in linker script */\r
+.word _ebss\r
+\r
+.equ BootRAM, 0xF108F85F\r
+/**\r
+ * @brief This is the code that gets called when the processor first\r
+ * starts execution following a reset event. Only the absolutely\r
+ * necessary set is performed, after which the application\r
+ * supplied main() routine is called. \r
+ * @param None\r
+ * @retval : None\r
+*/\r
+\r
+ .section .text.Reset_Handler\r
+ .weak Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler:\r
+\r
+/* Copy the data segment initializers from flash to SRAM */ \r
+ movs r1, #0\r
+ b LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+ ldr r3, =_sidata\r
+ ldr r3, [r3, r1]\r
+ str r3, [r0, r1]\r
+ adds r1, r1, #4\r
+ \r
+LoopCopyDataInit:\r
+ ldr r0, =_sdata\r
+ ldr r3, =_edata\r
+ adds r2, r0, r1\r
+ cmp r2, r3\r
+ bcc CopyDataInit\r
+ ldr r2, =_sbss\r
+ b LoopFillZerobss\r
+/* Zero fill the bss segment. */ \r
+FillZerobss:\r
+ movs r3, #0\r
+ str r3, [r2], #4\r
+ \r
+LoopFillZerobss:\r
+ ldr r3, = _ebss\r
+ cmp r2, r3\r
+ bcc FillZerobss\r
+/* Call the clock system intitialization function.*/\r
+ bl SystemInit\r
+/* Call the application's entry point.*/\r
+ bl main\r
+ bx lr\r
+.size Reset_Handler, .-Reset_Handler\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor receives an \r
+ * unexpected interrupt. This simply enters an infinite loop, preserving\r
+ * the system state for examination by a debugger.\r
+ *\r
+ * @param None\r
+ * @retval None\r
+*/\r
+ .section .text.Default_Handler,"ax",%progbits\r
+Default_Handler:\r
+Infinite_Loop:\r
+ b Infinite_Loop\r
+ .size Default_Handler, .-Default_Handler\r
+/*******************************************************************************\r
+*\r
+* The minimal vector table for a Cortex M0. Note that the proper constructs\r
+* must be placed on this to ensure that it ends up at physical address\r
+* 0x0000.0000.\r
+*******************************************************************************/ \r
+ .section .isr_vector,"a",%progbits\r
+ .type g_pfnVectors, %object\r
+ .size g_pfnVectors, .-g_pfnVectors\r
+\r
+\r
+g_pfnVectors:\r
+ .word _estack\r
+ .word Reset_Handler\r
+ .word NMI_Handler\r
+ .word HardFault_Handler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word SVC_Handler\r
+ .word 0\r
+ .word 0\r
+ .word PendSV_Handler\r
+ .word SysTick_Handler\r
+ .word WWDG_IRQHandler\r
+ .word PVD_IRQHandler\r
+ .word RTC_IRQHandler\r
+ .word FLASH_IRQHandler\r
+ .word RCC_IRQHandler\r
+ .word EXTI0_1_IRQHandler\r
+ .word EXTI2_3_IRQHandler\r
+ .word EXTI4_15_IRQHandler\r
+ .word TS_IRQHandler\r
+ .word DMA1_Channel1_IRQHandler\r
+ .word DMA1_Channel2_3_IRQHandler\r
+ .word DMA1_Channel4_5_IRQHandler\r
+ .word ADC1_COMP_IRQHandler \r
+ .word TIM1_BRK_UP_TRG_COM_IRQHandler\r
+ .word TIM1_CC_IRQHandler\r
+ .word TIM2_IRQHandler\r
+ .word TIM3_IRQHandler\r
+ .word TIM6_DAC_IRQHandler\r
+ .word 0 \r
+ .word TIM14_IRQHandler\r
+ .word TIM15_IRQHandler\r
+ .word TIM16_IRQHandler\r
+ .word TIM17_IRQHandler\r
+ .word I2C1_IRQHandler\r
+ .word I2C2_IRQHandler\r
+ .word SPI1_IRQHandler\r
+ .word SPI2_IRQHandler\r
+ .word USART1_IRQHandler\r
+ .word USART2_IRQHandler\r
+ .word 0\r
+ .word CEC_IRQHandler\r
+ .word 0\r
+ .word BootRAM /* @0x108. This is for boot in RAM mode for \r
+ STM32F0xx devices. */\r
+ \r
+/*******************************************************************************\r
+*\r
+* Provide weak aliases for each Exception handler to the Default_Handler. \r
+* As they are weak aliases, any function with the same name will override \r
+* this definition.\r
+*\r
+*******************************************************************************/\r
+ \r
+ .weak NMI_Handler\r
+ .thumb_set NMI_Handler,Default_Handler\r
+\r
+ .weak HardFault_Handler\r
+ .thumb_set HardFault_Handler,Default_Handler\r
+\r
+ .weak SVC_Handler\r
+ .thumb_set SVC_Handler,Default_Handler\r
+\r
+ .weak PendSV_Handler\r
+ .thumb_set PendSV_Handler,Default_Handler\r
+\r
+ .weak SysTick_Handler\r
+ .thumb_set SysTick_Handler,Default_Handler\r
+\r
+ .weak WWDG_IRQHandler\r
+ .thumb_set WWDG_IRQHandler,Default_Handler\r
+\r
+ .weak PVD_IRQHandler\r
+ .thumb_set PVD_IRQHandler,Default_Handler\r
+ \r
+ .weak RTC_IRQHandler\r
+ .thumb_set RTC_IRQHandler,Default_Handler\r
+ \r
+ .weak FLASH_IRQHandler\r
+ .thumb_set FLASH_IRQHandler,Default_Handler\r
+ \r
+ .weak RCC_IRQHandler\r
+ .thumb_set RCC_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI0_1_IRQHandler\r
+ .thumb_set EXTI0_1_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI2_3_IRQHandler\r
+ .thumb_set EXTI2_3_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI4_15_IRQHandler\r
+ .thumb_set EXTI4_15_IRQHandler,Default_Handler\r
+ \r
+ .weak TS_IRQHandler\r
+ .thumb_set TS_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Channel1_IRQHandler\r
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Channel2_3_IRQHandler\r
+ .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Channel4_5_IRQHandler\r
+ .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler\r
+ \r
+ .weak ADC1_COMP_IRQHandler\r
+ .thumb_set ADC1_COMP_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM1_BRK_UP_TRG_COM_IRQHandler\r
+ .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM1_CC_IRQHandler\r
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM2_IRQHandler\r
+ .thumb_set TIM2_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM3_IRQHandler\r
+ .thumb_set TIM3_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM6_DAC_IRQHandler\r
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM14_IRQHandler\r
+ .thumb_set TIM14_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM15_IRQHandler\r
+ .thumb_set TIM15_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM16_IRQHandler\r
+ .thumb_set TIM16_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM17_IRQHandler\r
+ .thumb_set TIM17_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C1_IRQHandler\r
+ .thumb_set I2C1_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C2_IRQHandler\r
+ .thumb_set I2C2_IRQHandler,Default_Handler\r
+ \r
+ .weak SPI1_IRQHandler\r
+ .thumb_set SPI1_IRQHandler,Default_Handler\r
+ \r
+ .weak SPI2_IRQHandler\r
+ .thumb_set SPI2_IRQHandler,Default_Handler\r
+ \r
+ .weak USART1_IRQHandler\r
+ .thumb_set USART1_IRQHandler,Default_Handler\r
+ \r
+ .weak USART2_IRQHandler\r
+ .thumb_set USART2_IRQHandler,Default_Handler\r
+ \r
+ .weak CEC_IRQHandler\r
+ .thumb_set CEC_IRQHandler,Default_Handler \r
+\r
+/******************** (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE***/\r
+\r
--- /dev/null
+;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************\r
+;* File Name : startup_stm32f0xx.s\r
+;* Author : MCD Application Team\r
+;* Version : V1.0.0RC1\r
+;* Date : 27-January-2012\r
+;* Description : STM32F0xx Devices vector table for EWARM toolchain.\r
+;* This module performs:\r
+;* - Set the initial SP\r
+;* - Set the initial PC == __iar_program_start,\r
+;* - Set the vector table entries with the exceptions ISR \r
+;* address.\r
+;* After Reset the Cortex-M0 processor is in Thread mode,\r
+;* priority is Privileged, and the Stack is set to Main.\r
+;********************************************************************************\r
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+;* FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+;* LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+;*******************************************************************************/\r
+;\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; The vector table is normally located at address 0.\r
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
+; The name "__vector_table" has special meaning for C-SPY:\r
+; it is where the SP start value is found, and the NVIC vector\r
+; table register (VTOR) is initialized to this address if != 0.\r
+;\r
+; Cortex-M version\r
+;\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+ SECTION .intvec:CODE:NOROOT(2)\r
+\r
+ EXTERN __iar_program_start\r
+ EXTERN SystemInit \r
+ PUBLIC __vector_table\r
+\r
+ DATA\r
+__vector_table\r
+ DCD sfe(CSTACK)\r
+ DCD Reset_Handler ; Reset Handler\r
+\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ DCD WWDG_IRQHandler ; Window Watchdog\r
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect\r
+ DCD RTC_IRQHandler ; RTC through EXTI Line\r
+ DCD FLASH_IRQHandler ; FLASH\r
+ DCD RCC_IRQHandler ; RCC\r
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1\r
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3\r
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15\r
+ DCD TS_IRQHandler ; TS\r
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1\r
+ DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3\r
+ DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5\r
+ DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 \r
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation\r
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare\r
+ DCD TIM2_IRQHandler ; TIM2\r
+ DCD TIM3_IRQHandler ; TIM3\r
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC\r
+ DCD 0 ; Reserved\r
+ DCD TIM14_IRQHandler ; TIM14\r
+ DCD TIM15_IRQHandler ; TIM15\r
+ DCD TIM16_IRQHandler ; TIM16\r
+ DCD TIM17_IRQHandler ; TIM17\r
+ DCD I2C1_IRQHandler ; I2C1\r
+ DCD I2C2_IRQHandler ; I2C2\r
+ DCD SPI1_IRQHandler ; SPI1\r
+ DCD SPI2_IRQHandler ; SPI2\r
+ DCD USART1_IRQHandler ; USART1\r
+ DCD USART2_IRQHandler ; USART2\r
+ DCD 0 ; Reserved\r
+ DCD CEC_IRQHandler ; CEC\r
+ DCD 0 ; Reserved\r
+ \r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+ THUMB\r
+\r
+ PUBWEAK Reset_Handler\r
+ SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__iar_program_start\r
+ BX R0\r
+ \r
+ PUBWEAK NMI_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+NMI_Handler\r
+ B NMI_Handler\r
+ \r
+ \r
+ PUBWEAK HardFault_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+HardFault_Handler\r
+ B HardFault_Handler\r
+ \r
+ \r
+ PUBWEAK SVC_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SVC_Handler\r
+ B SVC_Handler\r
+ \r
+ \r
+ PUBWEAK PendSV_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+PendSV_Handler\r
+ B PendSV_Handler\r
+ \r
+ \r
+ PUBWEAK SysTick_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SysTick_Handler\r
+ B SysTick_Handler\r
+ \r
+ \r
+ PUBWEAK WWDG_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+WWDG_IRQHandler\r
+ B WWDG_IRQHandler\r
+ \r
+ \r
+ PUBWEAK PVD_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+PVD_IRQHandler\r
+ B PVD_IRQHandler\r
+ \r
+ \r
+ PUBWEAK RTC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+RTC_IRQHandler\r
+ B RTC_IRQHandler\r
+ \r
+ \r
+ PUBWEAK FLASH_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+FLASH_IRQHandler\r
+ B FLASH_IRQHandler\r
+ \r
+ \r
+ PUBWEAK RCC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+RCC_IRQHandler\r
+ B RCC_IRQHandler\r
+ \r
+ \r
+ PUBWEAK EXTI0_1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI0_1_IRQHandler\r
+ B EXTI0_1_IRQHandler\r
+ \r
+ \r
+ PUBWEAK EXTI2_3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI2_3_IRQHandler\r
+ B EXTI2_3_IRQHandler\r
+ \r
+ \r
+ PUBWEAK EXTI4_15_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI4_15_IRQHandler\r
+ B EXTI4_15_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TS_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TS_IRQHandler\r
+ B TS_IRQHandler\r
+ \r
+ \r
+ PUBWEAK DMA1_Channel1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel1_IRQHandler\r
+ B DMA1_Channel1_IRQHandler\r
+ \r
+ \r
+ PUBWEAK DMA1_Channel2_3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel2_3_IRQHandler\r
+ B DMA1_Channel2_3_IRQHandler\r
+ \r
+ \r
+ PUBWEAK DMA1_Channel4_5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel4_5_IRQHandler\r
+ B DMA1_Channel4_5_IRQHandler\r
+ \r
+ \r
+ PUBWEAK ADC1_COMP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+ADC1_COMP_IRQHandler\r
+ B ADC1_COMP_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM1_BRK_UP_TRG_COM_IRQHandler\r
+ B TIM1_BRK_UP_TRG_COM_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM1_CC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM1_CC_IRQHandler\r
+ B TIM1_CC_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM2_IRQHandler\r
+ B TIM2_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM3_IRQHandler\r
+ B TIM3_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM6_DAC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM6_DAC_IRQHandler\r
+ B TIM6_DAC_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM14_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM14_IRQHandler\r
+ B TIM14_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM15_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM15_IRQHandler\r
+ B TIM15_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM16_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM16_IRQHandler\r
+ B TIM16_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM17_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM17_IRQHandler\r
+ B TIM17_IRQHandler\r
+ \r
+ \r
+ PUBWEAK I2C1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C1_IRQHandler\r
+ B I2C1_IRQHandler\r
+ \r
+ \r
+ PUBWEAK I2C2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C2_IRQHandler\r
+ B I2C2_IRQHandler\r
+ \r
+ \r
+ PUBWEAK SPI1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI1_IRQHandler\r
+ B SPI1_IRQHandler\r
+ \r
+ \r
+ PUBWEAK SPI2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI2_IRQHandler\r
+ B SPI2_IRQHandler\r
+ \r
+ \r
+ PUBWEAK USART1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART1_IRQHandler\r
+ B USART1_IRQHandler\r
+ \r
+ \r
+ PUBWEAK USART2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART2_IRQHandler\r
+ B USART2_IRQHandler\r
+ \r
+ \r
+ PUBWEAK CEC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+CEC_IRQHandler\r
+ B CEC_IRQHandler \r
+\r
+ END\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f0xx.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.\r
+ * This file contains the system clock configuration for STM32F0xx devices,\r
+ * and is generated by the clock configuration tool \r
+ * STM32F0xx_Clock_Configuration_VX.Y.Z.xls\r
+ * \r
+ * 1. This file provides two functions and one global variable to be called from \r
+ * user application:\r
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier\r
+ * and Divider factors, AHB/APBx prescalers and Flash settings),\r
+ * depending on the configuration made in the clock xls tool.\r
+ * This function is called at startup just after reset and \r
+ * before branch to main program. This call is made inside\r
+ * the "startup_stm32f0xx.s" file.\r
+ * \r
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+ * by the user application to setup the SysTick \r
+ * timer or configure other parameters.\r
+ * \r
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+ * be called whenever the core clock is changed\r
+ * during program execution.\r
+ * \r
+ * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.\r
+ * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to\r
+ * configure the system clock before to branch to main program.\r
+ * \r
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()\r
+ * function will do nothing and HSI still used as system clock source. User can \r
+ * add some code to deal with this issue inside the SetSysClock() function.\r
+ * \r
+ * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define\r
+ * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or\r
+ * through PLL, and you are using different crystal you have to adapt the HSE\r
+ * value to your own configuration.\r
+ * \r
+ * 5. This file configures the system clock as follows:\r
+ *=============================================================================\r
+ * System Clock Configuration\r
+ *=============================================================================\r
+ * System Clock source | PLL(HSE)\r
+ *-----------------------------------------------------------------------------\r
+ * SYSCLK | 48000000 Hz\r
+ *-----------------------------------------------------------------------------\r
+ * HCLK | 48000000 Hz\r
+ *-----------------------------------------------------------------------------\r
+ * AHB Prescaler | 1\r
+ *-----------------------------------------------------------------------------\r
+ * APB1 Prescaler | 1\r
+ *-----------------------------------------------------------------------------\r
+ * APB2 Prescaler | 1\r
+ *-----------------------------------------------------------------------------\r
+ * HSE Frequency | 8000000 Hz\r
+ *-----------------------------------------------------------------------------\r
+ * PLL MUL | 6\r
+ *-----------------------------------------------------------------------------\r
+ * VDD | 3.3 V\r
+ *-----------------------------------------------------------------------------\r
+ * Flash Latency | 1 WS\r
+ *-----------------------------------------------------------------------------\r
+ *=============================================================================\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f0xx_system\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup STM32F0xx_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32f0xx.h"\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F0xx_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F0xx_System_Private_Defines\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F0xx_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F0xx_System_Private_Variables\r
+ * @{\r
+ */\r
+uint32_t SystemCoreClock = 48000000;\r
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+static void SetSysClock(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F0xx_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the Embedded Flash Interface, the PLL and update the \r
+ * SystemCoreClock variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit (void)\r
+{ \r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */\r
+ RCC->CFGR &= (uint32_t)0xF8FFB80C;\r
+ \r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */\r
+ RCC->CFGR &= (uint32_t)0xFFC0FFFF;\r
+\r
+ /* Reset PREDIV1[3:0] bits */\r
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;\r
+\r
+ /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */\r
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;\r
+ \r
+ /* Reset HSI14 bit */\r
+ RCC->CR2 &= (uint32_t)0xFFFFFFFE;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+ \r
+/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */\r
+ SetSysClock();\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ *\r
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
+ * \r
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
+ * \r
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)\r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value\r
+ * 8 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature.\r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value\r
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate (void)\r
+{\r
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+ \r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock */\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ case 0x04: /* HSE used as system clock */\r
+ SystemCoreClock = HSE_VALUE;\r
+ break;\r
+ case 0x08: /* PLL used as system clock */\r
+ /* Get PLL clock source and multiplication factor ----------------------*/\r
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;\r
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
+ pllmull = ( pllmull >> 18) + 2;\r
+ \r
+ if (pllsource == 0x00)\r
+ {\r
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;\r
+ }\r
+ else\r
+ {\r
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;\r
+ /* HSE oscillator clock selected as PREDIV1 clock entry */\r
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; \r
+ } \r
+ break;\r
+ default: /* HSI used as system clock */\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ }\r
+ /* Compute HCLK clock frequency ----------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+ /* HCLK clock frequency */\r
+ SystemCoreClock >>= tmp; \r
+}\r
+\r
+/**\r
+ * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash\r
+ * settings.\r
+ * @note This function should be called only once the RCC clock configuration\r
+ * is reset to the default reset state (done in SystemInit() function).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClock(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/\r
+ /* Enable HSE */ \r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++; \r
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ } \r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY;\r
+ \r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;\r
+\r
+ /* PLL configuration: = HSE * 6 = 48 MHz */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);\r
+ \r
+ /* Enable PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* Select PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
+\r
+ /* Wait till PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock \r
+ configuration. User can add here some code to deal with this error */\r
+ } \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* ---------------------------------------------------------------------- \r
+* Copyright (C) 2010 ARM Limited. All rights reserved. \r
+* \r
+* $Date: 11. November 2010 \r
+* $Revision: V1.0.2 \r
+* \r
+* Project: CMSIS DSP Library \r
+* Title: arm_common_tables.h \r
+* \r
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions \r
+* \r
+* Target Processor: Cortex-M4/Cortex-M3\r
+* \r
+* Version 1.0.2 2010/11/11 \r
+* Documentation updated. \r
+* \r
+* Version 1.0.1 2010/10/05 \r
+* Production release and review comments incorporated. \r
+* \r
+* Version 1.0.0 2010/09/20 \r
+* Production release and review comments incorporated. \r
+* -------------------------------------------------------------------- */ \r
+ \r
+#ifndef _ARM_COMMON_TABLES_H \r
+#define _ARM_COMMON_TABLES_H \r
+ \r
+#include "arm_math.h" \r
+ \r
+extern uint16_t armBitRevTable[256]; \r
+extern q15_t armRecipTableQ15[64]; \r
+extern q31_t armRecipTableQ31[64]; \r
+extern const q31_t realCoefAQ31[1024];\r
+extern const q31_t realCoefBQ31[1024];\r
+ \r
+#endif /* ARM_COMMON_TABLES_H */ \r
--- /dev/null
+/* ---------------------------------------------------------------------- \r
+ * Copyright (C) 2010 ARM Limited. All rights reserved. \r
+ * \r
+ * $Date: 15. July 2011 \r
+ * $Revision: V1.0.10 \r
+ * \r
+ * Project: CMSIS DSP Library \r
+ * Title: arm_math.h\r
+ * \r
+ * Description: Public header file for CMSIS DSP Library\r
+ * \r
+ * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\r
+ * \r
+ * Version 1.0.10 2011/7/15 \r
+ * Big Endian support added and Merged M0 and M3/M4 Source code. \r
+ * \r
+ * Version 1.0.3 2010/11/29 \r
+ * Re-organized the CMSIS folders and updated documentation. \r
+ * \r
+ * Version 1.0.2 2010/11/11 \r
+ * Documentation updated. \r
+ * \r
+ * Version 1.0.1 2010/10/05 \r
+ * Production release and review comments incorporated. \r
+ * \r
+ * Version 1.0.0 2010/09/20 \r
+ * Production release and review comments incorporated. \r
+ * -------------------------------------------------------------------- */\r
+\r
+/**\r
+ \mainpage CMSIS DSP Software Library\r
+ *\r
+ * <b>Introduction</b>\r
+ *\r
+ * This user manual describes the CMSIS DSP software library, \r
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.\r
+ *\r
+ * The library is divided into a number of modules each covering a specific category:\r
+ * - Basic math functions\r
+ * - Fast math functions\r
+ * - Complex math functions\r
+ * - Filters\r
+ * - Matrix functions\r
+ * - Transforms\r
+ * - Motor control functions\r
+ * - Statistical functions\r
+ * - Support functions\r
+ * - Interpolation functions\r
+ *\r
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r
+ * 32-bit integer and 32-bit floating-point values. \r
+ *\r
+ * <b>Processor Support</b>\r
+ *\r
+ * The library is completely written in C and is fully CMSIS compliant. \r
+ * High performance is achieved through maximum use of Cortex-M4 intrinsics. \r
+ *\r
+ * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor,\r
+ * with the DSP intrinsics being emulated through software. \r
+ *\r
+ *\r
+ * <b>Toolchain Support</b>\r
+ *\r
+ * The library has been developed and tested with MDK-ARM version 4.21. \r
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r
+ *\r
+ * <b>Using the Library</b>\r
+ *\r
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)\r
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)\r
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)\r
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)\r
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)\r
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)\r
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)\r
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)\r
+ *\r
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single \r
+ * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. \r
+ * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or \r
+ * ARM_MATH_CM0 depending on the target processor in the application.\r
+ *\r
+ * <b>Examples</b>\r
+ *\r
+ * The library ships with a number of examples which demonstrate how to use the library functions.\r
+ *\r
+ * <b>Building the Library</b>\r
+ *\r
+ * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\DSP_Lib\Source\ARM</code> folder.\r
+ * - arm_cortexM0b_math.uvproj\r
+ * - arm_cortexM0l_math.uvproj\r
+ * - arm_cortexM3b_math.uvproj\r
+ * - arm_cortexM3l_math.uvproj \r
+ * - arm_cortexM4b_math.uvproj\r
+ * - arm_cortexM4l_math.uvproj\r
+ * - arm_cortexM4bf_math.uvproj\r
+ * - arm_cortexM4lf_math.uvproj\r
+ *\r
+ * Each library project have differant pre-processor macros.\r
+ *\r
+ * <b>ARM_MATH_CMx:</b>\r
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r
+ * and ARM_MATH_CM0 for building library on cortex-M0 target.\r
+ *\r
+ * <b>ARM_MATH_BIG_ENDIAN:</b>\r
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r
+ *\r
+ * <b>ARM_MATH_MATRIX_CHECK:</b>\r
+ * Define macro for checking on the input and output sizes of matrices\r
+ *\r
+ * <b>ARM_MATH_ROUNDING:</b>\r
+ * Define macro for rounding on support functions\r
+ *\r
+ * <b>__FPU_PRESENT:</b>\r
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries \r
+ *\r
+ *\r
+ * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.\r
+ *\r
+ * <b>Copyright Notice</b>\r
+ *\r
+ * Copyright (C) 2010 ARM Limited. All rights reserved.\r
+ */\r
+\r
+\r
+/**\r
+ * @defgroup groupMath Basic Math Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFastMath Fast Math Functions\r
+ * This set of functions provides a fast approximation to sine, cosine, and square root.\r
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions\r
+ * operate on individual values and not arrays.\r
+ * There are separate functions for Q15, Q31, and floating-point data.\r
+ *\r
+ */\r
+\r
+/**\r
+ * @defgroup groupCmplxMath Complex Math Functions\r
+ * This set of functions operates on complex data vectors.\r
+ * The data in the complex arrays is stored in an interleaved fashion\r
+ * (real, imag, real, imag, ...).\r
+ * In the API functions, the number of samples in a complex array refers\r
+ * to the number of complex values; the array contains twice this number of\r
+ * real values.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFilters Filtering Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupMatrix Matrix Functions\r
+ *\r
+ * This set of functions provides basic matrix math operations.\r
+ * The functions operate on matrix data structures. For example,\r
+ * the type\r
+ * definition for the floating-point matrix structure is shown\r
+ * below:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows; // number of rows of the matrix.\r
+ * uint16_t numCols; // number of columns of the matrix.\r
+ * float32_t *pData; // points to the data of the matrix.\r
+ * } arm_matrix_instance_f32;\r
+ * </pre>\r
+ * There are similar definitions for Q15 and Q31 data types.\r
+ *\r
+ * The structure specifies the size of the matrix and then points to\r
+ * an array of data. The array is of size <code>numRows X numCols</code>\r
+ * and the values are arranged in row order. That is, the\r
+ * matrix element (i, j) is stored at:\r
+ * <pre>\r
+ * pData[i*numCols + j]\r
+ * </pre>\r
+ *\r
+ * \par Init Functions\r
+ * There is an associated initialization function for each type of matrix\r
+ * data structure.\r
+ * The initialization function sets the values of the internal structure fields.\r
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\r
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.\r
+ *\r
+ * \par\r
+ * Use of the initialization function is optional. However, if initialization function is used\r
+ * then the instance structure cannot be placed into a const data section.\r
+ * To place the instance structure in a const data\r
+ * section, manually initialize the data structure. For example:\r
+ * <pre>\r
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\r
+ * </pre>\r
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\r
+ * specifies the number of columns, and <code>pData</code> points to the\r
+ * data array.\r
+ *\r
+ * \par Size Checking\r
+ * By default all of the matrix functions perform size checking on the input and\r
+ * output matrices. For example, the matrix addition function verifies that the\r
+ * two input matrices and the output matrix all have the same number of rows and\r
+ * columns. If the size check fails the functions return:\r
+ * <pre>\r
+ * ARM_MATH_SIZE_MISMATCH\r
+ * </pre>\r
+ * Otherwise the functions return\r
+ * <pre>\r
+ * ARM_MATH_SUCCESS\r
+ * </pre>\r
+ * There is some overhead associated with this matrix size checking.\r
+ * The matrix size checking is enabled via the #define\r
+ * <pre>\r
+ * ARM_MATH_MATRIX_CHECK\r
+ * </pre>\r
+ * within the library project settings. By default this macro is defined\r
+ * and size checking is enabled. By changing the project settings and\r
+ * undefining this macro size checking is eliminated and the functions\r
+ * run a bit faster. With size checking disabled the functions always\r
+ * return <code>ARM_MATH_SUCCESS</code>.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupTransforms Transform Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupController Controller Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupStats Statistics Functions\r
+ */\r
+/**\r
+ * @defgroup groupSupport Support Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupInterpolation Interpolation Functions\r
+ * These functions perform 1- and 2-dimensional interpolation of data.\r
+ * Linear interpolation is used for 1-dimensional data and\r
+ * bilinear interpolation is used for 2-dimensional data.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupExamples Examples\r
+ */\r
+#ifndef _ARM_MATH_H\r
+#define _ARM_MATH_H\r
+\r
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */\r
+\r
+#if defined (ARM_MATH_CM4)\r
+ #include "core_cm4.h"\r
+#elif defined (ARM_MATH_CM3)\r
+ #include "core_cm3.h"\r
+#elif defined (ARM_MATH_CM0)\r
+ #include "core_cm0.h"\r
+#else\r
+#include "ARMCM4.h"\r
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."\r
+#endif\r
+\r
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */\r
+#include "string.h"\r
+ #include "math.h"\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Macros required for reciprocal calculation in Normalized LMS\r
+ */\r
+\r
+#define DELTA_Q31 (0x100)\r
+#define DELTA_Q15 0x5\r
+#define INDEX_MASK 0x0000003F\r
+#define PI 3.14159265358979f\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Fast math approximations\r
+ */\r
+\r
+#define TABLE_SIZE 256\r
+#define TABLE_SPACING_Q31 0x800000\r
+#define TABLE_SPACING_Q15 0x80\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Controller functions\r
+ */\r
+ /* 1.31(q31) Fixed value of 2/360 */\r
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r
+#define INPUT_SPACING 0xB60B61\r
+\r
+\r
+ /**\r
+ * @brief Error status returned by some functions in the library.\r
+ */\r
+\r
+ typedef enum\r
+ {\r
+ ARM_MATH_SUCCESS = 0, /**< No error */\r
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */\r
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */\r
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */\r
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */\r
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\r
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */\r
+ } arm_status;\r
+\r
+ /**\r
+ * @brief 8-bit fractional data type in 1.7 format.\r
+ */\r
+ typedef int8_t q7_t;\r
+\r
+ /**\r
+ * @brief 16-bit fractional data type in 1.15 format.\r
+ */\r
+ typedef int16_t q15_t;\r
+\r
+ /**\r
+ * @brief 32-bit fractional data type in 1.31 format.\r
+ */\r
+ typedef int32_t q31_t;\r
+\r
+ /**\r
+ * @brief 64-bit fractional data type in 1.63 format.\r
+ */\r
+ typedef int64_t q63_t;\r
+\r
+ /**\r
+ * @brief 32-bit floating-point type definition.\r
+ */\r
+ typedef float float32_t;\r
+\r
+ /**\r
+ * @brief 64-bit floating-point type definition.\r
+ */\r
+ typedef double float64_t;\r
+\r
+ /**\r
+ * @brief definition to read/write two 16 bit values.\r
+ */\r
+#define __SIMD32(addr) (*(int32_t **) & (addr))\r
+\r
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)\r
+ /**\r
+ * @brief definition to pack two 16 bit values.\r
+ */\r
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \\r
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )\r
+\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief definition to pack four 8 bit values.\r
+ */\r
+#ifndef ARM_MATH_BIG_ENDIAN\r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )\r
+#else \r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )\r
+ \r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q31 values.\r
+ */\r
+ static __INLINE q31_t clip_q63_to_q31(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q15 values.\r
+ */\r
+ static __INLINE q15_t clip_q63_to_q15(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q7 values.\r
+ */\r
+ static __INLINE q7_t clip_q31_to_q7(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q15 values.\r
+ */\r
+ static __INLINE q15_t clip_q31_to_q15(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r
+ */\r
+\r
+ static __INLINE q63_t mult32x64(\r
+ q63_t x,\r
+ q31_t y)\r
+ {\r
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r
+ (((q63_t) (x >> 32) * y)));\r
+ }\r
+\r
+\r
+#if defined (ARM_MATH_CM0) && defined ( __CC_ARM )\r
+#define __CLZ __clz\r
+#endif \r
+\r
+#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )\r
+\r
+ static __INLINE uint32_t __CLZ(q31_t data);\r
+\r
+\r
+ static __INLINE uint32_t __CLZ(q31_t data)\r
+ {\r
+ uint32_t count = 0;\r
+ uint32_t mask = 0x80000000;\r
+\r
+ while((data & mask) == 0)\r
+ {\r
+ count += 1u;\r
+ mask = mask >> 1u;\r
+ }\r
+\r
+ return(count);\r
+\r
+ }\r
+\r
+#endif \r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.\r
+ */\r
+\r
+ static __INLINE uint32_t arm_recip_q31(\r
+ q31_t in,\r
+ q31_t * dst,\r
+ q31_t * pRecipTable)\r
+ {\r
+\r
+ uint32_t out, tempVal;\r
+ uint32_t index, i;\r
+ uint32_t signBits;\r
+\r
+ if(in > 0)\r
+ {\r
+ signBits = __CLZ(in) - 1;\r
+ }\r
+ else\r
+ {\r
+ signBits = __CLZ(-in) - 1;\r
+ }\r
+\r
+ /* Convert input sample to 1.31 format */\r
+ in = in << signBits;\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = (uint32_t) (in >> 24u);\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.31 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0u; i < 2u; i++)\r
+ {\r
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);\r
+ tempVal = 0x7FFFFFFF - tempVal;\r
+ /* 1.31 with exp 1 */\r
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);\r
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1u);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.\r
+ */\r
+ static __INLINE uint32_t arm_recip_q15(\r
+ q15_t in,\r
+ q15_t * dst,\r
+ q15_t * pRecipTable)\r
+ {\r
+\r
+ uint32_t out = 0, tempVal = 0;\r
+ uint32_t index = 0, i = 0;\r
+ uint32_t signBits = 0;\r
+\r
+ if(in > 0)\r
+ {\r
+ signBits = __CLZ(in) - 17;\r
+ }\r
+ else\r
+ {\r
+ signBits = __CLZ(-in) - 17;\r
+ }\r
+\r
+ /* Convert input sample to 1.15 format */\r
+ in = in << signBits;\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = in >> 8;\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.15 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0; i < 2; i++)\r
+ {\r
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);\r
+ tempVal = 0x7FFF - tempVal;\r
+ /* 1.15 with exp 1 */\r
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1);\r
+\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined intrinisic function for only M0 processors\r
+ */\r
+#if defined(ARM_MATH_CM0)\r
+\r
+ static __INLINE q31_t __SSAT(\r
+ q31_t x,\r
+ uint32_t y)\r
+ {\r
+ int32_t posMax, negMin;\r
+ uint32_t i;\r
+\r
+ posMax = 1;\r
+ for (i = 0; i < (y - 1); i++)\r
+ {\r
+ posMax = posMax * 2;\r
+ }\r
+\r
+ if(x > 0)\r
+ {\r
+ posMax = (posMax - 1);\r
+\r
+ if(x > posMax)\r
+ {\r
+ x = posMax;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ negMin = -posMax;\r
+\r
+ if(x < negMin)\r
+ {\r
+ x = negMin;\r
+ }\r
+ }\r
+ return (x);\r
+\r
+\r
+ }\r
+\r
+#endif /* end of ARM_MATH_CM0 */\r
+\r
+\r
+\r
+ /*\r
+ * @brief C custom defined intrinsic function for M3 and M0 processors\r
+ */\r
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)\r
+\r
+ /*\r
+ * @brief C custom defined QADD8 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QADD8(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q7_t r, s, t, u;\r
+\r
+ r = (char) x;\r
+ s = (char) y;\r
+\r
+ r = __SSAT((q31_t) (r + s), 8);\r
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);\r
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);\r
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);\r
+\r
+ sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |\r
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB8 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSUB8(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s, t, u;\r
+\r
+ r = (char) x;\r
+ s = (char) y;\r
+\r
+ r = __SSAT((r - s), 8);\r
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;\r
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;\r
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;\r
+\r
+ sum =\r
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QADD16 for M3 and M0 processors\r
+ */\r
+\r
+ /*\r
+ * @brief C custom defined QADD16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QADD16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = __SSAT(r + s, 16);\r
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHADD16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHADD16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) + (s >> 1));\r
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSUB16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = __SSAT(r - s, 16);\r
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHSUB16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHSUB16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t diff;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) - (s >> 1));\r
+ s = (((x >> 17) - (y >> 17)) << 16);\r
+\r
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return diff;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QASX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QASX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum = 0;\r
+\r
+ sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +\r
+ clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHASX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHASX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) - (y >> 17));\r
+ s = (((x >> 17) + (s >> 1)) << 16);\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSAX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSAX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum = 0;\r
+\r
+ sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +\r
+ clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHSAX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHSAX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) + (y >> 17));\r
+ s = (((x >> 17) - (s >> 1)) << 16);\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUSDX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUSDX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return ((q31_t)(((short) x * (short) (y >> 16)) -\r
+ ((short) (x >> 16) * (short) y)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUADX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUADX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return ((q31_t)(((short) x * (short) (y >> 16)) +\r
+ ((short) (x >> 16) * (short) y)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QADD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QADD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+ return clip_q63_to_q31((q63_t) x + y);\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSUB(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+ return clip_q63_to_q31((q63_t) x - y);\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLAD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMLAD(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +\r
+ ((short) x * (short) y));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLADX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMLADX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) (y)) +\r
+ ((short) x * (short) (y >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLSDX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMLSDX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum - ((short) (x >> 16) * (short) (y)) +\r
+ ((short) x * (short) (y >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLALD for M3 and M0 processors\r
+ */\r
+ static __INLINE q63_t __SMLALD(\r
+ q31_t x,\r
+ q31_t y,\r
+ q63_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +\r
+ ((short) x * (short) y));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLALDX for M3 and M0 processors\r
+ */\r
+ static __INLINE q63_t __SMLALDX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q63_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) y)) +\r
+ ((short) x * (short) (y >> 16));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUAD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUAD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return (((x >> 16) * (y >> 16)) +\r
+ (((x << 16) >> 16) * ((y << 16) >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUSD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUSD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return (-((x >> 16) * (y >> 16)) +\r
+ (((x << 16) >> 16) * ((y << 16) >> 16)));\r
+ }\r
+\r
+\r
+\r
+\r
+#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q7;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 FIR filter.\r
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q7(\r
+ const arm_fir_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed.\r
+ * @return none\r
+ */\r
+ void arm_fir_init_q7(\r
+ arm_fir_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_fast_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>numTaps</code> is not a supported value.\r
+ */\r
+ \r
+ arm_status arm_fir_init_q15(\r
+ arm_fir_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_fast_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return none.\r
+ */\r
+ void arm_fir_init_q31(\r
+ arm_fir_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_f32(\r
+ const arm_fir_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR filter.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return none.\r
+ */\r
+ void arm_fir_init_f32(\r
+ arm_fir_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_casd_df1_inst_q15;\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_casd_df1_inst_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+\r
+\r
+ } arm_biquad_casd_df1_inst_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_q15(\r
+ arm_biquad_casd_df1_inst_q15 * S,\r
+ uint8_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_fast_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 Biquad cascade filter\r
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_fast_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_q31(\r
+ arm_biquad_casd_df1_inst_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int8_t postShift);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_f32(\r
+ const arm_biquad_casd_df1_inst_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_f32(\r
+ arm_biquad_casd_df1_inst_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ float32_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q15_t *pData; /**< points to the data of the matrix. */\r
+\r
+ } arm_matrix_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q31_t *pData; /**< points to the data of the matrix. */\r
+\r
+ } arm_matrix_instance_q31;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @param[in] *pState points to the array for storing intermediate results \r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_fast_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_fast_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Floating-point matrix scaling.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[in] scale scale factor\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ float32_t scale,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix scaling.\r
+ * @param[in] *pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ q15_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix scaling.\r
+ * @param[in] *pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ q31_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_q31(\r
+ arm_matrix_instance_q31 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q31_t *pData);\r
+\r
+ /**\r
+ * @brief Q15 matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_q15(\r
+ arm_matrix_instance_q15 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q15_t *pData);\r
+\r
+ /**\r
+ * @brief Floating-point matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_f32(\r
+ arm_matrix_instance_f32 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ float32_t *pData);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ #ifdef ARM_MATH_CM0 \r
+ q15_t A1;\r
+ q15_t A2; \r
+ #else \r
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r
+ #endif \r
+ q15_t state[3]; /**< The state array of length 3. */\r
+ q15_t Kp; /**< The proportional gain. */\r
+ q15_t Ki; /**< The integral gain. */\r
+ q15_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ q31_t A2; /**< The derived gain, A2 = Kd . */\r
+ q31_t state[3]; /**< The state array of length 3. */\r
+ q31_t Kp; /**< The proportional gain. */\r
+ q31_t Ki; /**< The integral gain. */\r
+ q31_t Kd; /**< The derivative gain. */\r
+\r
+ } arm_pid_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ float32_t A2; /**< The derived gain, A2 = Kd . */\r
+ float32_t state[3]; /**< The state array of length 3. */\r
+ float32_t Kp; /**< The proportional gain. */\r
+ float32_t Ki; /**< The integral gain. */\r
+ float32_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point PID Control.\r
+ * @param[in,out] *S points to an instance of the PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_f32(\r
+ arm_pid_instance_f32 * S,\r
+ int32_t resetStateFlag);\r
+\r
+ /**\r
+ * @brief Reset function for the floating-point PID Control.\r
+ * @param[in,out] *S is an instance of the floating-point PID Control structure\r
+ * @return none\r
+ */\r
+ void arm_pid_reset_f32(\r
+ arm_pid_instance_f32 * S);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_q31(\r
+ arm_pid_instance_q31 * S,\r
+ int32_t resetStateFlag);\r
+\r
+ \r
+ /**\r
+ * @brief Reset function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure\r
+ * @return none\r
+ */\r
+\r
+ void arm_pid_reset_q31(\r
+ arm_pid_instance_q31 * S);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_q15(\r
+ arm_pid_instance_q15 * S,\r
+ int32_t resetStateFlag);\r
+\r
+ /**\r
+ * @brief Reset function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the q15 PID Control structure\r
+ * @return none\r
+ */\r
+ void arm_pid_reset_q15(\r
+ arm_pid_instance_q15 * S);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Linear Interpolate function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t nValues;\r
+ float32_t x1;\r
+ float32_t xSpacing;\r
+ float32_t *pYData; /**< pointer to the table of Y values */\r
+ } arm_linear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ float32_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q31_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q15_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q7_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q7;\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ float32_t onebyfftLen; /**< value of 1/fftLen. */\r
+ } arm_cfft_radix4_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 CFFT/CIFFT.\r
+ * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.\r
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cfft_radix4_q15(\r
+ const arm_cfft_radix4_instance_q15 * S,\r
+ q15_t * pSrc);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 CFFT/CIFFT.\r
+ * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_cfft_radix4_init_q15(\r
+ arm_cfft_radix4_instance_q15 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 CFFT/CIFFT.\r
+ * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure.\r
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cfft_radix4_q31(\r
+ const arm_cfft_radix4_instance_q31 * S,\r
+ q31_t * pSrc);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 CFFT/CIFFT.\r
+ * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.\r
+ */\r
+ \r
+ arm_status arm_cfft_radix4_init_q31(\r
+ arm_cfft_radix4_instance_q31 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point CFFT/CIFFT.\r
+ * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure.\r
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cfft_radix4_f32(\r
+ const arm_cfft_radix4_instance_f32 * S,\r
+ float32_t * pSrc);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point CFFT/CIFFT.\r
+ * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.\r
+ */\r
+ \r
+ arm_status arm_cfft_radix4_init_f32(\r
+ arm_cfft_radix4_instance_f32 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+\r
+\r
+ /*----------------------------------------------------------------------\r
+ * Internal functions prototypes FFT function\r
+ ----------------------------------------------------------------------*/\r
+\r
+ /**\r
+ * @brief Core function for the floating-point CFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to the twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+ \r
+ void arm_radix4_butterfly_f32(\r
+ float32_t * pSrc,\r
+ uint16_t fftLen,\r
+ float32_t * pCoef,\r
+ uint16_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief Core function for the floating-point CIFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @param[in] onebyfftLen value of 1/fftLen.\r
+ * @return none.\r
+ */\r
+ \r
+ void arm_radix4_butterfly_inverse_f32(\r
+ float32_t * pSrc,\r
+ uint16_t fftLen,\r
+ float32_t * pCoef,\r
+ uint16_t twidCoefModifier,\r
+ float32_t onebyfftLen);\r
+\r
+ /**\r
+ * @brief In-place bit reversal function.\r
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.\r
+ * @param[in] fftSize length of the FFT.\r
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.\r
+ * @param[in] *pBitRevTab points to the bit reversal table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_bitreversal_f32(\r
+ float32_t *pSrc,\r
+ uint16_t fftSize,\r
+ uint16_t bitRevFactor,\r
+ uint16_t *pBitRevTab);\r
+\r
+ /**\r
+ * @brief Core function for the Q31 CFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+ \r
+ void arm_radix4_butterfly_q31(\r
+ q31_t *pSrc,\r
+ uint32_t fftLen,\r
+ q31_t *pCoef,\r
+ uint32_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief Core function for the Q31 CIFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+ \r
+ void arm_radix4_butterfly_inverse_q31(\r
+ q31_t * pSrc,\r
+ uint32_t fftLen,\r
+ q31_t * pCoef,\r
+ uint32_t twidCoefModifier);\r
+ \r
+ /**\r
+ * @brief In-place bit reversal function.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table\r
+ * @param[in] *pBitRevTab points to bit reversal table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_bitreversal_q31(\r
+ q31_t * pSrc,\r
+ uint32_t fftLen,\r
+ uint16_t bitRevFactor,\r
+ uint16_t *pBitRevTab);\r
+\r
+ /**\r
+ * @brief Core function for the Q15 CFFT butterfly process.\r
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_q15(\r
+ q15_t *pSrc16,\r
+ uint32_t fftLen,\r
+ q15_t *pCoef16,\r
+ uint32_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief Core function for the Q15 CIFFT butterfly process.\r
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_inverse_q15(\r
+ q15_t *pSrc16,\r
+ uint32_t fftLen,\r
+ q15_t *pCoef16,\r
+ uint32_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief In-place bit reversal function.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table\r
+ * @param[in] *pBitRevTab points to bit reversal table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_bitreversal_q15(\r
+ q15_t * pSrc,\r
+ uint32_t fftLen,\r
+ uint16_t bitRevFactor,\r
+ uint16_t *pBitRevTab);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint32_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ \r
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint32_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint16_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 RFFT/RIFFT.\r
+ * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.\r
+ * @param[in] *pSrc points to the input buffer.\r
+ * @param[out] *pDst points to the output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rfft_q15(\r
+ const arm_rfft_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 RFFT/RIFFT.\r
+ * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure.\r
+ * @param[in] fftLenReal length of the FFT.\r
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_rfft_init_q15(\r
+ arm_rfft_instance_q15 * S,\r
+ arm_cfft_radix4_instance_q15 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 RFFT/RIFFT.\r
+ * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure.\r
+ * @param[in] *pSrc points to the input buffer.\r
+ * @param[out] *pDst points to the output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rfft_q31(\r
+ const arm_rfft_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 RFFT/RIFFT.\r
+ * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure.\r
+ * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure.\r
+ * @param[in] fftLenReal length of the FFT.\r
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_rfft_init_q31(\r
+ arm_rfft_instance_q31 * S,\r
+ arm_cfft_radix4_instance_q31 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point RFFT/RIFFT.\r
+ * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure.\r
+ * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure.\r
+ * @param[in] fftLenReal length of the FFT.\r
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_rfft_init_f32(\r
+ arm_rfft_instance_f32 * S,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point RFFT/RIFFT.\r
+ * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure.\r
+ * @param[in] *pSrc points to the input buffer.\r
+ * @param[out] *pDst points to the output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rfft_f32(\r
+ const arm_rfft_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ float32_t normalize; /**< normalizing factor. */\r
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ float32_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_f32;\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_f32(\r
+ arm_dct4_instance_f32 * S,\r
+ arm_rfft_instance_f32 * S_RFFT,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ float32_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_f32(\r
+ const arm_dct4_instance_f32 * S,\r
+ float32_t * pState,\r
+ float32_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q31_t normalize; /**< normalizing factor. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q31_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q31;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure\r
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_q31(\r
+ arm_dct4_instance_q31 * S,\r
+ arm_rfft_instance_q31 * S_RFFT,\r
+ arm_cfft_radix4_instance_q31 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q31_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_q31(\r
+ const arm_dct4_instance_q31 * S,\r
+ q31_t * pState,\r
+ q31_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q15_t normalize; /**< normalizing factor. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q15_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q15;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_q15(\r
+ arm_dct4_instance_q15 * S,\r
+ arm_rfft_instance_q15 * S_RFFT,\r
+ arm_cfft_radix4_instance_q15 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q15_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_q15(\r
+ const arm_dct4_instance_q15 * S,\r
+ q15_t * pState,\r
+ q15_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Floating-point vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a floating-point vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scale scale factor to be applied\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_f32(\r
+ float32_t * pSrc,\r
+ float32_t scale,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q7 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q7(\r
+ q7_t * pSrc,\r
+ q7_t scaleFract,\r
+ int8_t shift,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q15 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q15(\r
+ q15_t * pSrc,\r
+ q15_t scaleFract,\r
+ int8_t shift,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q31 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q31(\r
+ q31_t * pSrc,\r
+ q31_t scaleFract,\r
+ int8_t shift,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Dot product of floating-point vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t blockSize,\r
+ float32_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q7 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q31_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q15 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q31 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q7(\r
+ q7_t * pSrc,\r
+ int8_t shiftBits,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q15(\r
+ q15_t * pSrc,\r
+ int8_t shiftBits,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q31(\r
+ q31_t * pSrc,\r
+ int8_t shiftBits,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a floating-point vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_f32(\r
+ float32_t * pSrc,\r
+ float32_t offset,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q7 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q7(\r
+ q7_t * pSrc,\r
+ q7_t offset,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q15 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q15(\r
+ q15_t * pSrc,\r
+ q15_t offset,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q31 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q31(\r
+ q31_t * pSrc,\r
+ q31_t offset,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a floating-point vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q7 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q15 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q31 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+ /**\r
+ * @brief Copies the elements of a floating-point vector. \r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q7 vector. \r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q15 vector. \r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q31 vector. \r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+ /**\r
+ * @brief Fills a constant value into a floating-point vector. \r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_f32(\r
+ float32_t value,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q7 vector. \r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q7(\r
+ q7_t value,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q15 vector. \r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q15(\r
+ q15_t value,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q31 vector. \r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q31(\r
+ q31_t value,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+/** \r
+ * @brief Convolution of floating-point sequences. \r
+ * @param[in] *pSrcA points to the first input sequence. \r
+ * @param[in] srcALen length of the first input sequence. \r
+ * @param[in] *pSrcB points to the second input sequence. \r
+ * @param[in] srcBLen length of the second input sequence. \r
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. \r
+ * @return none. \r
+ */ \r
+\r
+ void arm_conv_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+/** \r
+ * @brief Convolution of Q15 sequences. \r
+ * @param[in] *pSrcA points to the first input sequence. \r
+ * @param[in] srcALen length of the first input sequence. \r
+ * @param[in] *pSrcB points to the second input sequence. \r
+ * @param[in] srcBLen length of the second input sequence. \r
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. \r
+ * @return none. \r
+ */\r
+\r
+ void arm_conv_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+ /**\r
+ * @brief Partial convolution of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ } arm_fir_decimate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+\r
+ } arm_fir_decimate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+\r
+ } arm_fir_decimate_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR decimator.\r
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_f32(\r
+ const arm_fir_decimate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR decimator.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_f32(\r
+ arm_fir_decimate_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator.\r
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_fast_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR decimator.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_q15(\r
+ arm_fir_decimate_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator.\r
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_q31(\r
+ const arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_fast_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR decimator.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r
+ } arm_fir_interpolate_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR interpolator.\r
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_q15(\r
+ const arm_fir_interpolate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_q15(\r
+ arm_fir_interpolate_instance_q15 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR interpolator.\r
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_q31(\r
+ const arm_fir_interpolate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_q31(\r
+ arm_fir_interpolate_instance_q31 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR interpolator.\r
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_f32(\r
+ const arm_fir_interpolate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_f32(\r
+ arm_fir_interpolate_instance_f32 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_cas_df1_32x64_ins_q31;\r
+\r
+\r
+ /**\r
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cas_df1_32x64_q31(\r
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cas_df1_32x64_init_q31(\r
+ arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q63_t * pState,\r
+ uint8_t postShift);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_df2T_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the filter data structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df2T_f32(\r
+ const arm_biquad_cascade_df2T_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df2T_init_f32(\r
+ arm_biquad_cascade_df2T_instance_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_f32;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. \r
+ * @param[in] *pState points to the state buffer. The array is of length numStages. \r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_q15(\r
+ arm_fir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_lattice_q15(\r
+ const arm_fir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_q31(\r
+ arm_fir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_q31(\r
+ const arm_fir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+/**\r
+ * @brief Initialization function for the floating-point FIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_f32(\r
+ arm_fir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_f32(\r
+ const arm_fir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point IIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_f32(\r
+ const arm_iir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point IIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_f32(\r
+ arm_iir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t *pkCoeffs,\r
+ float32_t *pvCoeffs,\r
+ float32_t *pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_q31(\r
+ const arm_iir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_q31(\r
+ arm_iir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t *pkCoeffs,\r
+ q31_t *pvCoeffs,\r
+ q31_t *pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_q15(\r
+ const arm_iir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ * @brief Initialization function for the Q15 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_q15(\r
+ arm_iir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t *pkCoeffs,\r
+ q15_t *pvCoeffs,\r
+ q15_t *pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that controls filter coefficient updates. */\r
+ } arm_lms_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for floating-point LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_f32(\r
+ const arm_lms_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to the coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_f32(\r
+ arm_lms_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+ } arm_lms_instance_q15;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to the coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_q15(\r
+ arm_lms_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+ /**\r
+ * @brief Processing function for Q15 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_q15(\r
+ const arm_lms_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+\r
+ } arm_lms_instance_q31;\r
+\r
+ /**\r
+ * @brief Processing function for Q31 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_q31(\r
+ const arm_lms_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_q31(\r
+ arm_lms_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t *pCoeffs,\r
+ q31_t *pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point normalized LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that control filter coefficient updates. */\r
+ float32_t energy; /**< saves previous frame energy. */\r
+ float32_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for floating-point normalized LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point normalized LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 normalized LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */\r
+ q31_t energy; /**< saves previous frame energy. */\r
+ q31_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q31;\r
+\r
+ /**\r
+ * @brief Processing function for Q31 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 normalized LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< Number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */\r
+ q15_t energy; /**< saves previous frame energy. */\r
+ q15_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q15;\r
+\r
+ /**\r
+ * @brief Processing function for Q15 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for Q15 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+ /**\r
+ * @brief Correlation of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q7;\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point sparse FIR filter.\r
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ float32_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ q31_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ q15_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ q7_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ int32_t *pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /*\r
+ * @brief Floating-point sin_cos function.\r
+ * @param[in] theta input value in degrees \r
+ * @param[out] *pSinVal points to the processed sine output. \r
+ * @param[out] *pCosVal points to the processed cos output. \r
+ * @return none.\r
+ */\r
+\r
+ void arm_sin_cos_f32(\r
+ float32_t theta,\r
+ float32_t *pSinVal,\r
+ float32_t *pCcosVal);\r
+\r
+ /*\r
+ * @brief Q31 sin_cos function.\r
+ * @param[in] theta scaled input value in degrees \r
+ * @param[out] *pSinVal points to the processed sine output. \r
+ * @param[out] *pCosVal points to the processed cosine output. \r
+ * @return none.\r
+ */\r
+\r
+ void arm_sin_cos_q31(\r
+ q31_t theta,\r
+ q31_t *pSinVal,\r
+ q31_t *pCosVal);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup PID PID Motor Control\r
+ *\r
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control \r
+ * loop mechanism widely used in industrial control systems.\r
+ * A PID controller is the most commonly used type of feedback controller.\r
+ *\r
+ * This set of functions implements (PID) controllers\r
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample\r
+ * of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>\r
+ * is the input sample value. The functions return the output value.\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r
+ * A0 = Kp + Ki + Kd\r
+ * A1 = (-Kp ) - (2 * Kd )\r
+ * A2 = Kd </pre>\r
+ *\r
+ * \par\r
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant\r
+ * \r
+ * \par \r
+ * \image html PID.gif "Proportional Integral Derivative Controller" \r
+ *\r
+ * \par\r
+ * The PID controller calculates an "error" value as the difference between\r
+ * the measured output and the reference input.\r
+ * The controller attempts to minimize the error by adjusting the process control inputs. \r
+ * The proportional value determines the reaction to the current error, \r
+ * the integral value determines the reaction based on the sum of recent errors, \r
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.\r
+ *\r
+ * \par Instance Structure \r
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. \r
+ * A separate instance structure must be defined for each PID Controller. \r
+ * There are separate instance structure declarations for each of the 3 supported data types. \r
+ * \r
+ * \par Reset Functions \r
+ * There is also an associated reset function for each data type which clears the state array. \r
+ *\r
+ * \par Initialization Functions \r
+ * There is also an associated initialization function for each data type. \r
+ * The initialization function performs the following operations: \r
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r
+ * - Zeros out the values in the state buffer. \r
+ * \r
+ * \par \r
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. \r
+ *\r
+ * \par Fixed-Point Behavior \r
+ * Care must be taken when using the fixed-point versions of the PID Controller functions. \r
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. \r
+ * Refer to the function specific documentation below for usage guidelines. \r
+ */\r
+\r
+ /**\r
+ * @addtogroup PID\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point PID Control.\r
+ * @param[in,out] *S is an instance of the floating-point PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ */\r
+\r
+\r
+ static __INLINE float32_t arm_pid_f32(\r
+ arm_pid_instance_f32 * S,\r
+ float32_t in)\r
+ {\r
+ float32_t out;\r
+\r
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */\r
+ out = (S->A0 * in) +\r
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Process function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b> \r
+ * \par \r
+ * The function is implemented using an internal 64-bit accumulator. \r
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. \r
+ * Thus, if the accumulator result overflows it wraps around rather than clip. \r
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. \r
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. \r
+ */\r
+\r
+ static __INLINE q31_t arm_pid_q31(\r
+ arm_pid_instance_q31 * S,\r
+ q31_t in)\r
+ {\r
+ q63_t acc;\r
+ q31_t out;\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q63_t) S->A0 * in;\r
+\r
+ /* acc += A1 * x[n-1] */\r
+ acc += (q63_t) S->A1 * S->state[0];\r
+\r
+ /* acc += A2 * x[n-2] */\r
+ acc += (q63_t) S->A2 * S->state[1];\r
+\r
+ /* convert output to 1.31 format to add y[n-1] */\r
+ out = (q31_t) (acc >> 31u);\r
+\r
+ /* out += y[n-1] */\r
+ out += S->state[2];\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Process function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b> \r
+ * \par \r
+ * The function is implemented using a 64-bit internal accumulator. \r
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. \r
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. \r
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. \r
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. \r
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.\r
+ */\r
+\r
+ static __INLINE q15_t arm_pid_q15(\r
+ arm_pid_instance_q15 * S,\r
+ q15_t in)\r
+ {\r
+ q63_t acc;\r
+ q15_t out;\r
+\r
+ /* Implementation of PID controller */\r
+\r
+ #ifdef ARM_MATH_CM0\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = ((q31_t) S->A0 )* in ;\r
+\r
+ #else\r
+ \r
+ /* acc = A0 * x[n] */\r
+ acc = (q31_t) __SMUAD(S->A0, in);\r
+ \r
+ #endif\r
+\r
+ #ifdef ARM_MATH_CM0\r
+ \r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ acc += (q31_t) S->A1 * S->state[0] ;\r
+ acc += (q31_t) S->A2 * S->state[1] ;\r
+\r
+ #else\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc);\r
+\r
+ #endif\r
+\r
+ /* acc += y[n-1] */\r
+ acc += (q31_t) S->state[2] << 15;\r
+\r
+ /* saturate the output */\r
+ out = (q15_t) (__SSAT((acc >> 15), 16));\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+ \r
+ /**\r
+ * @} end of PID group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix inverse.\r
+ * @param[in] *src points to the instance of the input floating-point matrix structure.\r
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.\r
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
+ */\r
+\r
+ arm_status arm_mat_inverse_f32(\r
+ const arm_matrix_instance_f32 * src,\r
+ arm_matrix_instance_f32 * dst);\r
+\r
+ \r
+ \r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup clarke Vector Clarke Transform\r
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\r
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\r
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\r
+ * \image html clarke.gif Stator current space vector and its components in (a,b).\r
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\r
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output. \r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeFormula.gif\r
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\r
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point Clarke transform\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @return none.\r
+ */\r
+\r
+ static __INLINE void arm_clarke_f32(\r
+ float32_t Ia,\r
+ float32_t Ib,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Clarke transform for Q31 version\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+\r
+ static __INLINE void arm_clarke_q31(\r
+ q31_t Ia,\r
+ q31_t Ib,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r
+\r
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r
+\r
+ /* pIbeta is calculated by adding the intermediate products */\r
+ *pIbeta = __QADD(product1, product2);\r
+ }\r
+\r
+ /**\r
+ * @} end of clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q31 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_q31(\r
+ q7_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ \r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_clarke Vector Inverse Clarke Transform\r
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r
+ * \r
+ * The function operates on a single sample of data and each call to the function returns the processed output. \r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeInvFormula.gif\r
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\r
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Clarke transform\r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>\r
+ * @return none.\r
+ */\r
+\r
+\r
+ static __INLINE void arm_inv_clarke_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pIa,\r
+ float32_t * pIb)\r
+ {\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Inverse Clarke transform for Q31 version \r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the subtraction, hence there is no risk of overflow.\r
+ */\r
+\r
+ static __INLINE void arm_inv_clarke_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pIa,\r
+ q31_t * pIb)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r
+\r
+ /* pIb is calculated by subtracting the products */\r
+ *pIb = __QSUB(product2, product1);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of inv_clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q15 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_q15(\r
+ q7_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ \r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup park Vector Park Transform\r
+ *\r
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents \r
+ * from the stationary to the moving reference frame and control the spatial relationship between \r
+ * the stator vector current and rotor flux vector.\r
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the \r
+ * current vector and the relationship from the two reference frames:\r
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output. \r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkFormula.gif\r
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components, \r
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the \r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Park transform\r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] *pId points to output rotor reference frame d\r
+ * @param[out] *pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * The function implements the forward Park transform.\r
+ *\r
+ */\r
+\r
+ static __INLINE void arm_park_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pId,\r
+ float32_t * pIq,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r
+ *pId = Ialpha * cosVal + Ibeta * sinVal;\r
+\r
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Park transform for Q31 version \r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] *pId points to output rotor reference frame d\r
+ * @param[out] *pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.\r
+ */\r
+\r
+\r
+ static __INLINE void arm_park_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pId,\r
+ q31_t * pIq,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Ialpha * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Ialpha * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pId by adding the two intermediate products 1 and 2 */\r
+ *pId = __QADD(product1, product2);\r
+\r
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r
+ *pIq = __QSUB(product4, product3);\r
+ }\r
+\r
+ /**\r
+ * @} end of park group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_float(\r
+ q7_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ \r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_park Vector Inverse Park transform\r
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output. \r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkInvFormula.gif\r
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components, \r
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the \r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Park transform\r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ */\r
+\r
+ static __INLINE void arm_inv_park_f32(\r
+ float32_t Id,\r
+ float32_t Iq,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r
+ *pIalpha = Id * cosVal - Iq * sinVal;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r
+ *pIbeta = Id * sinVal + Iq * cosVal;\r
+\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Inverse Park transform for Q31 version \r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+\r
+\r
+ static __INLINE void arm_inv_park_q31(\r
+ q31_t Id,\r
+ q31_t Iq,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Id * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Id * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r
+ *pIalpha = __QSUB(product1, product2);\r
+\r
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r
+ *pIbeta = __QADD(product4, product3);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of Inverse park group\r
+ */\r
+\r
+ \r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_float(\r
+ q31_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup LinearInterpolate Linear Interpolation\r
+ *\r
+ * Linear interpolation is a method of curve fitting using linear polynomials.\r
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r
+ *\r
+ * \par \r
+ * \image html LinearInterp.gif "Linear interpolation"\r
+ *\r
+ * \par\r
+ * A Linear Interpolate function calculates an output value(y), for the input(x)\r
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r
+ * where x0, x1 are nearest values of input x\r
+ * y0, y1 are nearest values to output y\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * This set of functions implements Linear interpolation process\r
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single\r
+ * sample of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.\r
+ * <code>x</code> is the input sample value. The functions returns the output value.\r
+ * \r
+ * \par\r
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table \r
+ * if x is below input range and returns last value of table if x is above range. \r
+ */\r
+\r
+ /**\r
+ * @addtogroup LinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point Linear Interpolation Function.\r
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure\r
+ * @param[in] x input sample to process\r
+ * @return y processed output sample.\r
+ *\r
+ */\r
+\r
+ static __INLINE float32_t arm_linear_interp_f32(\r
+ arm_linear_interp_instance_f32 * S,\r
+ float32_t x)\r
+ {\r
+\r
+ float32_t y;\r
+ float32_t x0, x1; /* Nearest input values */\r
+ float32_t y0, y1; /* Nearest output values */\r
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */\r
+ int32_t i; /* Index variable */\r
+ float32_t *pYData = S->pYData; /* pointer to output table */\r
+\r
+ /* Calculation of index */\r
+ i = (x - S->x1) / xSpacing;\r
+\r
+ if(i < 0)\r
+ {\r
+ /* Iniatilize output for below specified range as least output value of table */\r
+ y = pYData[0];\r
+ }\r
+ else if(i >= S->nValues)\r
+ {\r
+ /* Iniatilize output for above specified range as last output value of table */\r
+ y = pYData[S->nValues-1]; \r
+ }\r
+ else\r
+ { \r
+ /* Calculation of nearest input values */\r
+ x0 = S->x1 + i * xSpacing;\r
+ x1 = S->x1 + (i +1) * xSpacing;\r
+ \r
+ /* Read of nearest output values */\r
+ y0 = pYData[i];\r
+ y1 = pYData[i + 1];\r
+ \r
+ /* Calculation of output */\r
+ y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)); \r
+ \r
+ }\r
+\r
+ /* returns output value */\r
+ return (y);\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q31 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+\r
+\r
+ static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData,\r
+ q31_t x, uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q31_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+ \r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20);\r
+\r
+ if(index >= (nValues - 1))\r
+ {\r
+ return(pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return(pYData[0]);\r
+ }\r
+ else\r
+ {\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left by 11 to keep fract in 1.31 format */\r
+ fract = (x & 0x000FFFFF) << 11;\r
+ \r
+ /* Read two nearest output values from the index in 1.31(q31) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+ \r
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r
+ \r
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r
+ \r
+ /* Convert y to 1.31 format */\r
+ return (y << 1u);\r
+\r
+ }\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q15 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12. \r
+ *\r
+ */\r
+\r
+\r
+ static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues)\r
+ {\r
+ q63_t y; /* output */\r
+ q15_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */ \r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20u); \r
+\r
+ if(index >= (nValues - 1))\r
+ {\r
+ return(pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return(pYData[0]);\r
+ }\r
+ else\r
+ { \r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+ \r
+ /* Read two nearest output values from the index */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+ \r
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r
+ y = ((q63_t) y0 * (0xFFFFF - fract));\r
+ \r
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r
+ y += ((q63_t) y1 * (fract));\r
+ \r
+ /* convert y to 1.15 format */\r
+ return (y >> 20);\r
+ }\r
+\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q7 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ */\r
+\r
+\r
+ static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q7_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+ \r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20u);\r
+\r
+\r
+ if(index >= (nValues - 1))\r
+ {\r
+ return(pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return(pYData[0]);\r
+ }\r
+ else\r
+ {\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+ \r
+ /* Read two nearest output values from the index and are in 1.7(q7) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+ \r
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r
+ y = ((y0 * (0xFFFFF - fract)));\r
+ \r
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r
+ y += (y1 * fract);\r
+ \r
+ /* convert y to 1.7(q7) format */\r
+ return (y >> 20u);\r
+\r
+ }\r
+\r
+ }\r
+ /**\r
+ * @} end of LinearInterpolate group\r
+ */\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ float32_t arm_sin_f32(\r
+ float32_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ q31_t arm_sin_q31(\r
+ q31_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ q15_t arm_sin_q15(\r
+ q15_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ float32_t arm_cos_f32(\r
+ float32_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ q31_t arm_cos_q31(\r
+ q31_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ q15_t arm_cos_q15(\r
+ q15_t x);\r
+\r
+\r
+ /**\r
+ * @ingroup groupFastMath\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup SQRT Square Root\r
+ *\r
+ * Computes the square root of a number.\r
+ * There are separate functions for Q15, Q31, and floating-point data types. \r
+ * The square root function is computed using the Newton-Raphson algorithm.\r
+ * This is an iterative algorithm of the form:\r
+ * <pre>\r
+ * x1 = x0 - f(x0)/f'(x0)\r
+ * </pre>\r
+ * where <code>x1</code> is the current estimate,\r
+ * <code>x0</code> is the previous estimate and\r
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\r
+ * For the square root function, the algorithm reduces to:\r
+ * <pre>\r
+ * x0 = in/2 [initial guess]\r
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]\r
+ * </pre>\r
+ */\r
+\r
+\r
+ /**\r
+ * @addtogroup SQRT\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point square root function.\r
+ * @param[in] in input value.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+\r
+ static __INLINE arm_status arm_sqrt_f32(\r
+ float32_t in, float32_t *pOut)\r
+ {\r
+ if(in > 0)\r
+ {\r
+\r
+// #if __FPU_USED\r
+ #if (__FPU_USED == 1) && defined ( __CC_ARM )\r
+ *pOut = __sqrtf(in);\r
+ #else \r
+ *pOut = sqrtf(in);\r
+ #endif\r
+\r
+ return (ARM_MATH_SUCCESS);\r
+ }\r
+ else\r
+ {\r
+ *pOut = 0.0f;\r
+ return (ARM_MATH_ARGUMENT_ERROR);\r
+ }\r
+\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q31 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q31(\r
+ q31_t in, q31_t *pOut);\r
+\r
+ /**\r
+ * @brief Q15 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q15(\r
+ q15_t in, q15_t *pOut);\r
+\r
+ /**\r
+ * @} end of SQRT group\r
+ */\r
+\r
+\r
+\r
+\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular write function.\r
+ */\r
+\r
+ static __INLINE void arm_circularWrite_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const int32_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular Read function.\r
+ */\r
+ static __INLINE void arm_circularRead_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ int32_t * dst,\r
+ int32_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (int32_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+ /**\r
+ * @brief Q15 Circular write function.\r
+ */\r
+\r
+ static __INLINE void arm_circularWrite_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q15_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief Q15 Circular Read function.\r
+ */\r
+ static __INLINE void arm_circularRead_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q15_t * dst,\r
+ q15_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (q15_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular write function.\r
+ */\r
+\r
+ static __INLINE void arm_circularWrite_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q7_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular Read function.\r
+ */\r
+ static __INLINE void arm_circularRead_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q7_t * dst,\r
+ q7_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (q7_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mean_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q31_t * realResult,\r
+ q31_t * imagResult);\r
+\r
+ /**\r
+ * @brief Q31 complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q63_t * realResult,\r
+ q63_t * imagResult);\r
+\r
+ /**\r
+ * @brief Floating-point complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t numSamples,\r
+ float32_t * realResult,\r
+ float32_t * imagResult);\r
+\r
+ /**\r
+ * @brief Q15 complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_q15(\r
+ q15_t * pSrcCmplx,\r
+ q15_t * pSrcReal,\r
+ q15_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_q31(\r
+ q31_t * pSrcCmplx,\r
+ q31_t * pSrcReal,\r
+ q31_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_f32(\r
+ float32_t * pSrcCmplx,\r
+ float32_t * pSrcReal,\r
+ float32_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *result is output pointer\r
+ * @param[in] index is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * result,\r
+ uint32_t * index);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+ void arm_min_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Minimum value of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q7 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q15 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q31 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a floating-point vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Q15 complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q31 vector. \r
+ * @param[in] *pSrc points to the floating-point input vector \r
+ * @param[out] *pDst points to the Q31 output vector\r
+ * @param[in] blockSize length of the input vector \r
+ * @return none. \r
+ */\r
+ void arm_float_to_q31(\r
+ float32_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q15 vector. \r
+ * @param[in] *pSrc points to the floating-point input vector \r
+ * @param[out] *pDst points to the Q15 output vector\r
+ * @param[in] blockSize length of the input vector \r
+ * @return none\r
+ */\r
+ void arm_float_to_q15(\r
+ float32_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q7 vector. \r
+ * @param[in] *pSrc points to the floating-point input vector \r
+ * @param[out] *pDst points to the Q7 output vector\r
+ * @param[in] blockSize length of the input vector \r
+ * @return none\r
+ */\r
+ void arm_float_to_q7(\r
+ float32_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_q15(\r
+ q31_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_q7(\r
+ q31_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_float(\r
+ q15_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_q31(\r
+ q15_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_q7(\r
+ q15_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup BilinearInterpolate Bilinear Interpolation\r
+ *\r
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\r
+ * determines values between the grid points.\r
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r
+ * Bilinear interpolation is often used in image processing to rescale images.\r
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r
+ *\r
+ * <b>Algorithm</b>\r
+ * \par\r
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r
+ * For floating-point, the instance structure is defined as:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows;\r
+ * uint16_t numCols;\r
+ * float32_t *pData;\r
+ * } arm_bilinear_interp_instance_f32;\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * where <code>numRows</code> specifies the number of rows in the table;\r
+ * <code>numCols</code> specifies the number of columns in the table;\r
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\r
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\r
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\r
+ *\r
+ * \par\r
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:\r
+ * <pre>\r
+ * XF = floor(x)\r
+ * YF = floor(y)\r
+ * </pre>\r
+ * \par\r
+ * The interpolated output point is computed as:\r
+ * <pre>\r
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)\r
+ * </pre>\r
+ * Note that the coordinates (x, y) contain integer and fractional components. \r
+ * The integer components specify which portion of the table to use while the\r
+ * fractional components control the interpolation processor.\r
+ *\r
+ * \par\r
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. \r
+ */\r
+\r
+ /**\r
+ * @addtogroup BilinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate.\r
+ * @param[in] Y interpolation coordinate.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ \r
+ static __INLINE float32_t arm_bilinear_interp_f32(\r
+ const arm_bilinear_interp_instance_f32 * S,\r
+ float32_t X,\r
+ float32_t Y)\r
+ {\r
+ float32_t out;\r
+ float32_t f00, f01, f10, f11;\r
+ float32_t *pData = S->pData;\r
+ int32_t xIndex, yIndex, index;\r
+ float32_t xdiff, ydiff;\r
+ float32_t b1, b2, b3, b4;\r
+\r
+ xIndex = (int32_t) X;\r
+ yIndex = (int32_t) Y;\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+ \r
+ /* Calculation of index for two nearest points in X-direction */\r
+ index = (xIndex - 1) + (yIndex-1) * S->numCols ;\r
+\r
+\r
+ /* Read two nearest points in X-direction */\r
+ f00 = pData[index];\r
+ f01 = pData[index + 1];\r
+\r
+ /* Calculation of index for two nearest points in Y-direction */\r
+ index = (xIndex-1) + (yIndex) * S->numCols;\r
+\r
+\r
+ /* Read two nearest points in Y-direction */\r
+ f10 = pData[index];\r
+ f11 = pData[index + 1];\r
+\r
+ /* Calculation of intermediate values */\r
+ b1 = f00;\r
+ b2 = f01 - f00;\r
+ b3 = f10 - f00;\r
+ b4 = f00 - f01 - f10 + f11;\r
+\r
+ /* Calculation of fractional part in X */\r
+ xdiff = X - xIndex;\r
+\r
+ /* Calculation of fractional part in Y */\r
+ ydiff = Y - yIndex;\r
+\r
+ /* Calculation of bi-linear interpolated output */\r
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Q31 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ static __INLINE q31_t arm_bilinear_interp_q31(\r
+ arm_bilinear_interp_instance_q31 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q31_t out; /* Temporary output */\r
+ q31_t acc = 0; /* output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q31_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q31_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20u);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20u);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left xfract by 11 to keep 1.31 format */\r
+ xfract = (X & 0x000FFFFF) << 11u;\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left yfract by 11 to keep 1.31 format */\r
+ yfract = (Y & 0x000FFFFF) << 11u;\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));\r
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* Convert acc to 1.31(q31) format */\r
+ return (acc << 2u);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Q15 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ static __INLINE q15_t arm_bilinear_interp_q15(\r
+ arm_bilinear_interp_instance_q15 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q15_t x1, x2, y1, y2; /* Nearest output values */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q15_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r
+\r
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */\r
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);\r
+ acc = ((q63_t) out * (0xFFFFF - yfract));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);\r
+ acc += ((q63_t) out * (xfract));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* acc is in 13.51 format and down shift acc by 36 times */\r
+ /* Convert out to 1.15 format */\r
+ return (acc >> 36);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Q7 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ static __INLINE q7_t arm_bilinear_interp_q7(\r
+ arm_bilinear_interp_instance_q7 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q7_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q7_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r
+ out = ((x1 * (0xFFFFF - xfract)));\r
+ acc = (((q63_t) out * (0xFFFFF - yfract)));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */\r
+ out = ((x2 * (0xFFFFF - yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y1 * (0xFFFFF - xfract)));\r
+ acc += (((q63_t) out * (yfract)));\r
+\r
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y2 * (yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r
+ return (acc >> 40);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of BilinearInterpolate group\r
+ */\r
+\r
+\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* _ARM_MATH_H */\r
+\r
+\r
+/**\r
+ *\r
+ * End of file.\r
+ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm0.h\r
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
+ * @version V2.10\r
+ * @date 19. July 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_CM0_H_GENERIC\r
+#define __CORE_CM0_H_GENERIC\r
+\r
+\r
+/** \mainpage CMSIS Cortex-M0\r
+\r
+ This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.\r
+ It consists of:\r
+\r
+ - Cortex-M Core Register Definitions\r
+ - Cortex-M functions\r
+ - Cortex-M instructions\r
+\r
+ The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease\r
+ access to the Cortex-M Core\r
+ */\r
+\r
+/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates following MISRA-C2004 Rules:\r
+ \r
+ - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'. \r
+\r
+ - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+ \r
+ - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code. \r
+\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions\r
+ This file defines all structures and symbols for CMSIS core:\r
+ - CMSIS version number\r
+ - Cortex-M core\r
+ - Cortex-M core Revision Number\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM0 definitions */\r
+#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x00) /*!< Cortex core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ /* add preprocessor checks */\r
+#endif\r
+\r
+#include <stdint.h> /*!< standard types definitions */\r
+#include "core_cmInstr.h" /*!< Core Instruction Access */\r
+#include "core_cmFunc.h" /*!< Core Function Access */\r
+\r
+#endif /* __CORE_CM0_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0_H_DEPENDANT\r
+#define __CORE_CM0_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM0_REV\r
+ #define __CM0_REV 0x0000\r
+ #warning "__CM0_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+/*@} end of group CMSIS_core_definitions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register CMSIS Core Register\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE CMSIS Core\r
+ Type definitions for the Cortex-M Core Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC CMSIS NVIC\r
+ Type definitions for the Cortex-M NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31];\r
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31];\r
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31];\r
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31];\r
+ uint32_t RESERVED4[64];\r
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB CMSIS SCB\r
+ Type definitions for the Cortex-M System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick CMSIS SysTick\r
+ Type definitions for the Cortex-M System Timer Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug CMSIS Core Debug\r
+ Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP\r
+ and not via processor. Therefore they are not covered by the Cortex-M0 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M0 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions\r
+ @{\r
+ */\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ This function enables a device specific interrupt in the NVIC interrupt controller.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the external interrupt to enable\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ This function disables a device specific interrupt in the NVIC interrupt controller.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the external interrupt to disable\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ This function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Number of the interrupt for get pending\r
+ \return 0 Interrupt status is not pending\r
+ \return 1 Interrupt status is pending\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ This function sets the pending bit for the specified interrupt.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the interrupt for set pending\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ This function clears the pending bit for the specified interrupt.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the interrupt for clear pending\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ This function sets the priority for the specified interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+ Note: The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Number of the interrupt for set priority\r
+ \param [in] priority Priority to set\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ else {\r
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ This function reads the priority for the specified interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+ The returned priority value is automatically aligned to the implemented\r
+ priority bits of the microcontroller.\r
+\r
+ \param [in] IRQn Number of the interrupt for get priority\r
+ \return Interrupt Priority\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */\r
+ else {\r
+ return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ This function initiate a system reset request to reset the MCU.\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ This function initialises the system tick timer and its interrupt and start the system tick timer.\r
+ Counter is in free running mode to generate periodical interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#endif /* __CORE_CM0_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V2.10\r
+ * @date 19. July 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_CM3_H_GENERIC\r
+#define __CORE_CM3_H_GENERIC\r
+\r
+\r
+/** \mainpage CMSIS Cortex-M3\r
+\r
+ This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.\r
+ It consists of:\r
+\r
+ - Cortex-M Core Register Definitions\r
+ - Cortex-M functions\r
+ - Cortex-M instructions\r
+\r
+ The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease\r
+ access to the Cortex-M Core\r
+ */\r
+\r
+/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates following MISRA-C2004 Rules:\r
+ \r
+ - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'. \r
+\r
+ - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+ \r
+ - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code. \r
+\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions\r
+ This file defines all structures and symbols for CMSIS core:\r
+ - CMSIS version number\r
+ - Cortex-M core\r
+ - Cortex-M core Revision Number\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM3 definitions */\r
+#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ /* add preprocessor checks */\r
+#endif\r
+\r
+#include <stdint.h> /*!< standard types definitions */\r
+#include "core_cmInstr.h" /*!< Core Instruction Access */\r
+#include "core_cmFunc.h" /*!< Core Function Access */\r
+\r
+#endif /* __CORE_CM3_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM3_H_DEPENDANT\r
+#define __CORE_CM3_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM3_REV\r
+ #define __CM3_REV 0x0200\r
+ #warning "__CM3_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+/*@} end of group CMSIS_core_definitions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register CMSIS Core Register\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE CMSIS Core\r
+ Type definitions for the Cortex-M Core Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC CMSIS NVIC\r
+ Type definitions for the Cortex-M NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB CMSIS SCB\r
+ Type definitions for the Cortex-M System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB\r
+ Type definitions for the Cortex-M System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1[1];\r
+#endif\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick CMSIS SysTick\r
+ Type definitions for the Cortex-M System Timer Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM CMSIS ITM\r
+ Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */\r
+#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU CMSIS MPU\r
+ Type definitions for the Cortex-M Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug CMSIS Core Debug\r
+ Type definitions for the Cortex-M Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ This function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ This function gets the priority grouping from NVIC Interrupt Controller.\r
+ Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+\r
+ \return Priority grouping field\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ This function enables a device specific interrupt in the NVIC interrupt controller.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the external interrupt to enable\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ This function disables a device specific interrupt in the NVIC interrupt controller.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the external interrupt to disable\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ This function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Number of the interrupt for get pending\r
+ \return 0 Interrupt status is not pending\r
+ \return 1 Interrupt status is pending\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ This function sets the pending bit for the specified interrupt.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the interrupt for set pending\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ This function clears the pending bit for the specified interrupt.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the interrupt for clear pending\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ This function reads the active register in NVIC and returns the active bit.\r
+ \param [in] IRQn Number of the interrupt for get active\r
+ \return 0 Interrupt status is not active\r
+ \return 1 Interrupt status is active\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ This function sets the priority for the specified interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+ Note: The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Number of the interrupt for set priority\r
+ \param [in] priority Priority to set\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ This function reads the priority for the specified interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+ The returned priority value is automatically aligned to the implemented\r
+ priority bits of the microcontroller.\r
+\r
+ \param [in] IRQn Number of the interrupt for get priority\r
+ \return Interrupt Priority\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ This function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value and sub priority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+\r
+ The returned priority value can be used for NVIC_SetPriority(...) function\r
+\r
+ \param [in] PriorityGroup Used priority group\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0)\r
+ \param [in] SubPriority Sub priority value (starting from 0)\r
+ \return Encoded priority for the interrupt\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ This function decodes an interrupt priority value with the given priority group to\r
+ preemptive priority value and sub priority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+\r
+ The priority value can be retrieved with NVIC_GetPriority(...) function\r
+\r
+ \param [in] Priority Priority value\r
+ \param [in] PriorityGroup Used priority group\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0)\r
+ \param [out] pSubPriority Sub priority value (starting from 0)\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ This function initiate a system reset request to reset the MCU.\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ This function initialises the system tick timer and its interrupt and start the system tick timer.\r
+ Counter is in free running mode to generate periodical interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ This function transmits a character via the ITM channel 0.\r
+ It just returns when no debugger is connected that has booked the output.\r
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
+\r
+ \param [in] ch Character to transmit\r
+ \return Character to transmit\r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ This function inputs a character via external variable ITM_RxBuffer.\r
+ It just returns when no debugger is connected that has booked the output.\r
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
+\r
+ \return Received character\r
+ \return -1 No character received\r
+ */\r
+static __INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ This function checks external variable ITM_RxBuffer whether a character is available or not.\r
+ It returns '1' if a character is available and '0' if no character is available.\r
+\r
+ \return 0 No character available\r
+ \return 1 Character available\r
+ */\r
+static __INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+#endif /* __CORE_CM3_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4.h\r
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
+ * @version V2.10\r
+ * @date 19. July 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_CM4_H_GENERIC\r
+#define __CORE_CM4_H_GENERIC\r
+\r
+\r
+/** \mainpage CMSIS Cortex-M4\r
+\r
+ This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.\r
+ It consists of:\r
+\r
+ - Cortex-M Core Register Definitions\r
+ - Cortex-M functions\r
+ - Cortex-M instructions\r
+ - Cortex-M SIMD instructions\r
+\r
+ The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease\r
+ access to the Cortex-M Core\r
+ */\r
+\r
+/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates following MISRA-C2004 Rules:\r
+ \r
+ - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'. \r
+\r
+ - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+ \r
+ - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code. \r
+\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions\r
+ This file defines all structures and symbols for CMSIS core:\r
+ - CMSIS version number\r
+ - Cortex-M core\r
+ - Cortex-M core Revision Number\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM4 definitions */\r
+#define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x04) /*!< Cortex core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ /* add preprocessor checks to define __FPU_USED */\r
+ #define __FPU_USED 0\r
+#endif\r
+\r
+#include <stdint.h> /*!< standard types definitions */\r
+#include <core_cmInstr.h> /*!< Core Instruction Access */\r
+#include <core_cmFunc.h> /*!< Core Function Access */\r
+#include <core_cm4_simd.h> /*!< Compiler specific SIMD Intrinsics */\r
+\r
+#endif /* __CORE_CM4_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM4_H_DEPENDANT\r
+#define __CORE_CM4_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM4_REV\r
+ #define __CM4_REV 0x0000\r
+ #warning "__CM4_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+/*@} end of group CMSIS_core_definitions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register CMSIS Core Register\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE CMSIS Core\r
+ Type definitions for the Cortex-M Core Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC CMSIS NVIC\r
+ Type definitions for the Cortex-M NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB CMSIS SCB\r
+ Type definitions for the Cortex-M System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB\r
+ Type definitions for the Cortex-M System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */\r
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */\r
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick CMSIS SysTick\r
+ Type definitions for the Cortex-M System Timer Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM CMSIS ITM\r
+ Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */\r
+#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU CMSIS MPU\r
+ Type definitions for the Cortex-M Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if (__FPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU CMSIS FPU\r
+ Type definitions for the Cortex-M Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register */\r
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register */\r
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register */\r
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug CMSIS Core Debug\r
+ Type definitions for the Cortex-M Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M4 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#if (__FPU_PRESENT == 1)\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ This function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ This function gets the priority grouping from NVIC Interrupt Controller.\r
+ Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+\r
+ \return Priority grouping field\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ This function enables a device specific interrupt in the NVIC interrupt controller.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the external interrupt to enable\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */\r
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ This function disables a device specific interrupt in the NVIC interrupt controller.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the external interrupt to disable\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ This function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Number of the interrupt for get pending\r
+ \return 0 Interrupt status is not pending\r
+ \return 1 Interrupt status is pending\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ This function sets the pending bit for the specified interrupt.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the interrupt for set pending\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ This function clears the pending bit for the specified interrupt.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the interrupt for clear pending\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ This function reads the active register in NVIC and returns the active bit.\r
+ \param [in] IRQn Number of the interrupt for get active\r
+ \return 0 Interrupt status is not active\r
+ \return 1 Interrupt status is active\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ This function sets the priority for the specified interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+ Note: The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Number of the interrupt for set priority\r
+ \param [in] priority Priority to set\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ This function reads the priority for the specified interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+ The returned priority value is automatically aligned to the implemented\r
+ priority bits of the microcontroller.\r
+\r
+ \param [in] IRQn Number of the interrupt for get priority\r
+ \return Interrupt Priority\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ This function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value and sub priority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+\r
+ The returned priority value can be used for NVIC_SetPriority(...) function\r
+\r
+ \param [in] PriorityGroup Used priority group\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0)\r
+ \param [in] SubPriority Sub priority value (starting from 0)\r
+ \return Encoded priority for the interrupt\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ This function decodes an interrupt priority value with the given priority group to\r
+ preemptive priority value and sub priority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+\r
+ The priority value can be retrieved with NVIC_GetPriority(...) function\r
+\r
+ \param [in] Priority Priority value\r
+ \param [in] PriorityGroup Used priority group\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0)\r
+ \param [out] pSubPriority Sub priority value (starting from 0)\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ This function initiate a system reset request to reset the MCU.\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ This function initialises the system tick timer and its interrupt and start the system tick timer.\r
+ Counter is in free running mode to generate periodical interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ This function transmits a character via the ITM channel 0.\r
+ It just returns when no debugger is connected that has booked the output.\r
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
+\r
+ \param [in] ch Character to transmit\r
+ \return Character to transmit\r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ This function inputs a character via external variable ITM_RxBuffer.\r
+ It just returns when no debugger is connected that has booked the output.\r
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
+\r
+ \return Received character\r
+ \return -1 No character received\r
+ */\r
+static __INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ This function checks external variable ITM_RxBuffer whether a character is available or not.\r
+ It returns '1' if a character is available and '0' if no character is available.\r
+\r
+ \return 0 No character available\r
+ \return 1 Character available\r
+ */\r
+static __INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+#endif /* __CORE_CM4_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4_simd.h\r
+ * @brief CMSIS Cortex-M4 SIMD Header File\r
+ * @version V2.10\r
+ * @date 19. July 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#ifndef __CORE_CM4_SIMD_H\r
+#define __CORE_CM4_SIMD_H\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/\r
+#define __SADD8 __sadd8\r
+#define __QADD8 __qadd8\r
+#define __SHADD8 __shadd8\r
+#define __UADD8 __uadd8\r
+#define __UQADD8 __uqadd8\r
+#define __UHADD8 __uhadd8\r
+#define __SSUB8 __ssub8\r
+#define __QSUB8 __qsub8\r
+#define __SHSUB8 __shsub8\r
+#define __USUB8 __usub8\r
+#define __UQSUB8 __uqsub8\r
+#define __UHSUB8 __uhsub8\r
+#define __SADD16 __sadd16\r
+#define __QADD16 __qadd16\r
+#define __SHADD16 __shadd16\r
+#define __UADD16 __uadd16\r
+#define __UQADD16 __uqadd16\r
+#define __UHADD16 __uhadd16\r
+#define __SSUB16 __ssub16\r
+#define __QSUB16 __qsub16\r
+#define __SHSUB16 __shsub16\r
+#define __USUB16 __usub16\r
+#define __UQSUB16 __uqsub16\r
+#define __UHSUB16 __uhsub16\r
+#define __SASX __sasx\r
+#define __QASX __qasx\r
+#define __SHASX __shasx\r
+#define __UASX __uasx\r
+#define __UQASX __uqasx\r
+#define __UHASX __uhasx\r
+#define __SSAX __ssax\r
+#define __QSAX __qsax\r
+#define __SHSAX __shsax\r
+#define __USAX __usax\r
+#define __UQSAX __uqsax\r
+#define __UHSAX __uhsax\r
+#define __USAD8 __usad8\r
+#define __USADA8 __usada8\r
+#define __SSAT16 __ssat16\r
+#define __USAT16 __usat16\r
+#define __UXTB16 __uxtb16\r
+#define __UXTAB16 __uxtab16\r
+#define __SXTB16 __sxtb16\r
+#define __SXTAB16 __sxtab16\r
+#define __SMUAD __smuad\r
+#define __SMUADX __smuadx\r
+#define __SMLAD __smlad\r
+#define __SMLADX __smladx\r
+#define __SMLALD __smlald\r
+#define __SMLALDX __smlaldx\r
+#define __SMUSD __smusd\r
+#define __SMUSDX __smusdx\r
+#define __SMLSD __smlsd\r
+#define __SMLSDX __smlsdx\r
+#define __SMLSLD __smlsld\r
+#define __SMLSLDX __smlsldx\r
+#define __SEL __sel\r
+#define __QADD __qadd\r
+#define __QSUB __qsub\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+\r
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/\r
+/* intrinsic __SADD8 see intrinsics.h */\r
+/* intrinsic __QADD8 see intrinsics.h */\r
+/* intrinsic __SHADD8 see intrinsics.h */\r
+/* intrinsic __UADD8 see intrinsics.h */\r
+/* intrinsic __UQADD8 see intrinsics.h */\r
+/* intrinsic __UHADD8 see intrinsics.h */\r
+/* intrinsic __SSUB8 see intrinsics.h */\r
+/* intrinsic __QSUB8 see intrinsics.h */\r
+/* intrinsic __SHSUB8 see intrinsics.h */\r
+/* intrinsic __USUB8 see intrinsics.h */\r
+/* intrinsic __UQSUB8 see intrinsics.h */\r
+/* intrinsic __UHSUB8 see intrinsics.h */\r
+/* intrinsic __SADD16 see intrinsics.h */\r
+/* intrinsic __QADD16 see intrinsics.h */\r
+/* intrinsic __SHADD16 see intrinsics.h */\r
+/* intrinsic __UADD16 see intrinsics.h */\r
+/* intrinsic __UQADD16 see intrinsics.h */\r
+/* intrinsic __UHADD16 see intrinsics.h */\r
+/* intrinsic __SSUB16 see intrinsics.h */\r
+/* intrinsic __QSUB16 see intrinsics.h */\r
+/* intrinsic __SHSUB16 see intrinsics.h */\r
+/* intrinsic __USUB16 see intrinsics.h */\r
+/* intrinsic __UQSUB16 see intrinsics.h */\r
+/* intrinsic __UHSUB16 see intrinsics.h */\r
+/* intrinsic __SASX see intrinsics.h */\r
+/* intrinsic __QASX see intrinsics.h */\r
+/* intrinsic __SHASX see intrinsics.h */\r
+/* intrinsic __UASX see intrinsics.h */\r
+/* intrinsic __UQASX see intrinsics.h */\r
+/* intrinsic __UHASX see intrinsics.h */\r
+/* intrinsic __SSAX see intrinsics.h */\r
+/* intrinsic __QSAX see intrinsics.h */\r
+/* intrinsic __SHSAX see intrinsics.h */\r
+/* intrinsic __USAX see intrinsics.h */\r
+/* intrinsic __UQSAX see intrinsics.h */\r
+/* intrinsic __UHSAX see intrinsics.h */\r
+/* intrinsic __USAD8 see intrinsics.h */\r
+/* intrinsic __USADA8 see intrinsics.h */\r
+/* intrinsic __SSAT16 see intrinsics.h */\r
+/* intrinsic __USAT16 see intrinsics.h */\r
+/* intrinsic __UXTB16 see intrinsics.h */\r
+/* intrinsic __SXTB16 see intrinsics.h */\r
+/* intrinsic __UXTAB16 see intrinsics.h */\r
+/* intrinsic __SXTAB16 see intrinsics.h */\r
+/* intrinsic __SMUAD see intrinsics.h */\r
+/* intrinsic __SMUADX see intrinsics.h */\r
+/* intrinsic __SMLAD see intrinsics.h */\r
+/* intrinsic __SMLADX see intrinsics.h */\r
+/* intrinsic __SMLALD see intrinsics.h */\r
+/* intrinsic __SMLALDX see intrinsics.h */\r
+/* intrinsic __SMUSD see intrinsics.h */\r
+/* intrinsic __SMUSDX see intrinsics.h */\r
+/* intrinsic __SMLSD see intrinsics.h */\r
+/* intrinsic __SMLSDX see intrinsics.h */\r
+/* intrinsic __SMLSLD see intrinsics.h */\r
+/* intrinsic __SMLSLDX see intrinsics.h */\r
+/* intrinsic __SEL see intrinsics.h */\r
+/* intrinsic __QADD see intrinsics.h */\r
+/* intrinsic __QSUB see intrinsics.h */\r
+/* intrinsic __PKHBT see intrinsics.h */\r
+/* intrinsic __PKHTB see intrinsics.h */\r
+\r
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+ \r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SMLALD(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \\r
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\r
+ })\r
+\r
+#define __SMLALDX(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \\r
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SMLSLD(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \\r
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\r
+ })\r
+\r
+#define __SMLSLDX(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \\r
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+\r
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+/* not yet supported */\r
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+\r
+\r
+#endif\r
+\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CORE_CM4_SIMD_H */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V2.10\r
+ * @date 26. July 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface \r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/** \brief Get ISPR Register\r
+\r
+ This function returns the content of the ISPR Register.\r
+\r
+ \return ISPR Register value\r
+ */\r
+static __INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+static __INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+static __INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+static __INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+static __INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+static __INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+static __INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+ \r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+ \r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+static __INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+static __INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief Enable IRQ Interrupts\r
+\r
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i");\r
+}\r
+\r
+\r
+/** \brief Disable IRQ Interrupts\r
+\r
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i");\r
+}\r
+\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+\r
+/** \brief Get ISPR Register\r
+\r
+ This function returns the content of the ISPR Register.\r
+\r
+ \return ISPR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+ \r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+ \r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+ \r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f");\r
+}\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f");\r
+}\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V2.10\r
+ * @date 19. July 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor, \r
+ so that all instructions following the ISB are fetched from cache or \r
+ memory, after the instruction has been completed.\r
+ */\r
+#define __ISB() __isb(0xF)\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier. \r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __dsb(0xF)\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before \r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __dmb(0xF)\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+static __INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+static __INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __rbit\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz \r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor, \r
+ so that all instructions following the ISB are fetched from cache or \r
+ memory, after the instruction has been completed.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb");\r
+}\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier. \r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb");\r
+}\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before \r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb");\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint8_t result;\r
+ \r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint16_t result;\r
+ \r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex");\r
+}\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ uint8_t result;\r
+ \r
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+* -------------------------------------------------------------------\r
+* Copyright (C) 2011 ARM Limited. All rights reserved. \r
+* \r
+* Date: 25 July 2011 \r
+* Revision: V2.10 \r
+* \r
+* Project: Cortex Microcontroller Software Interface Standard (CMSIS)\r
+* Title: Release Note for CMSIS\r
+*\r
+* -------------------------------------------------------------------\r
+\r
+\r
+NOTE - Open the index.html file to access CMSIS documentation\r
+\r
+\r
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all \r
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects \r
+and reduces time-to-market for new embedded applications.\r
+\r
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").\r
+Any user of the software package is bound to the terms and conditions of the end user license agreement.\r
+\r
+\r
+You will find the following sub-directories:\r
+\r
+Documentation - Contains CMSIS documentation.\r
+ \r
+DSP_Lib - MDK project files, Examples and source files etc.. to build the \r
+ CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.\r
+\r
+Include - CMSIS Core Support and CMSIS DSP Include Files.\r
+\r
+Lib - CMSIS DSP Binaries \r
+---
\ No newline at end of file
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">\r
+<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>\r
+\r
+\r
+\r
+\r
+\r
+\r
+<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">\r
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+-->\r
+</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-fareast-font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]-->\r
+<style type="disc">\r
+</style><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="45058"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]--><meta content="MCD Application Team" name="author"></head><body link="blue" vlink="blue">\r
+<div class="Section1">\r
+<p class="MsoNormal"><span style="font-family: Arial;"><br>\r
+</span><span style="font-family: Arial;"><o:p></o:p></span></p>\r
+<div align="center">\r
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">\r
+<tbody>\r
+<tr style="">\r
+<td style="padding: 0cm;" valign="top">\r
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">\r
+<tbody>\r
+<tr style="">\r
+<td style="padding: 1.5pt;">\r
+\r
+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release\r
+Notes for<o:p></o:p> </span><span style="font-size: 20pt; color: rgb(51, 102, 255); font-family: Verdana;">STM32F0xx Standard Peripherals Library Drivers (StdPeriph_Driver)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span><br>\r
+<span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>\r
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright\r
+© 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>\r
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt;"><img style="border: 0px solid ; width: 86px; height: 65px;" alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp"></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>\r
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">\r
+<tbody>\r
+<tr style="">\r
+<td style="padding: 0cm;" valign="top">\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>\r
+<ol style="margin-top: 0cm;" start="1" type="1">\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F0xx Standard Peripherals Library Drivers update history</a><o:p></o:p></span></li>\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>\r
+</ol>\r
+ <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F0xx Standard Peripherals Library Drivers update history<o:p></o:p></span></h2>\r
+\r
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC1 / 27-January-2012</span></h3>\r
+ <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+Changes<o:p></o:p></span></u></b></p>\r
+\r
+\r
+\r
+ \r
+ \r
+ <ul>\r
+ <li><span style="font-size: 10pt; font-family: Verdana;">Second version for STM32F0xx devices.</span></li>\r
+ <li><span style="font-size: 10pt; font-family: Verdana;">Add more documentation inside all peripherals drivers.<br>\r
+ </span></li>\r
+ </ul>\r
+ <span style="font-size: 10pt; font-family: Verdana;"></span>\r
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 189px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V0.1.0 / 18-November-2011<o:p></o:p></span></h3>\r
+\r
+ \r
+ <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main\r
+Changes<o:p></o:p></span></u></b></p>\r
+\r
+\r
+ \r
+ <ul style="margin-top: 0cm;" type="square">\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Alpha version for STM32F0xx devices.</span><br>\r
+ <span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><br><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="margin-top: 0cm;" type="square"></ul>\r
+\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><small><span style="font-family: Verdana;">The use of this STM32\r
+Firmware is governed by the terms and conditions of the License\r
+Agreement available in the root of this package.</span></small><p class="MsoNormal" style="margin: 4.5pt 0cm;"><b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></p>\r
+<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">\r
+<hr align="center" size="2" width="100%"></span></div>\r
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For\r
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STMicroelectronics<span style="color: black;"> Microcontrollers visit </span><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;">www.st.com</span></u></a></span><span style="color: black;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+</div>\r
+<p class="MsoNormal"><o:p> </o:p></p>\r
+</div>\r
+</body></html>
\ No newline at end of file
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_adc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the ADC firmware \r
+ * library\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_ADC_H\r
+#define __STM32F0XX_ADC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ADC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief ADC Init structure definition\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.\r
+ This parameter can be a value of @ref ADC_Resolution */\r
+\r
+ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in\r
+ Continuous or Single mode.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+\r
+ uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the\r
+ trigger of a regular group. This parameter can be a value\r
+ of @ref ADC_external_trigger_edge_conversion */\r
+\r
+ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog\r
+ to digital conversion of regular channels. This parameter\r
+ can be a value of @ref ADC_external_trigger_sources_for_channels_conversion */\r
+\r
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.\r
+ This parameter can be a value of @ref ADC_data_align */\r
+\r
+ uint32_t ADC_ScanDirection; /*!< Specifies in which direction the channels will be scanned\r
+ in the sequence. \r
+ This parameter can be a value of @ref ADC_Scan_Direction */\r
+}ADC_InitTypeDef;\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Exported_Constants\r
+ * @{\r
+ */ \r
+#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)\r
+\r
+/** @defgroup ADC_JitterOff\r
+ * @{\r
+ */ \r
+#define ADC_JitterOff_PCLKDiv2 ADC_CFGR2_JITOFFDIV2\r
+#define ADC_JitterOff_PCLKDiv4 ADC_CFGR2_JITOFFDIV4\r
+\r
+#define IS_ADC_JITTEROFF(JITTEROFF) (((JITTEROFF) & 0x3FFFFFFF) == (uint32_t)RESET)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_Resolution\r
+ * @{\r
+ */ \r
+#define ADC_Resolution_12b ((uint32_t)0x00000000)\r
+#define ADC_Resolution_10b ADC_CFGR1_RES_0\r
+#define ADC_Resolution_8b ADC_CFGR1_RES_1\r
+#define ADC_Resolution_6b ADC_CFGR1_RES\r
+\r
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \\r
+ ((RESOLUTION) == ADC_Resolution_10b) || \\r
+ ((RESOLUTION) == ADC_Resolution_8b) || \\r
+ ((RESOLUTION) == ADC_Resolution_6b))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_external_trigger_edge_conversion \r
+ * @{\r
+ */ \r
+#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigConvEdge_Rising ADC_CFGR1_EXTEN_0\r
+#define ADC_ExternalTrigConvEdge_Falling ADC_CFGR1_EXTEN_1\r
+#define ADC_ExternalTrigConvEdge_RisingFalling ADC_CFGR1_EXTEN\r
+\r
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \\r
+ ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_external_trigger_sources_for_channels_conversion\r
+ * @{\r
+ */ \r
+\r
+/* TIM1 */\r
+#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000)\r
+#define ADC_ExternalTrigConv_T1_CC4 ADC_CFGR1_EXTSEL_0\r
+\r
+/* TIM2 */\r
+#define ADC_ExternalTrigConv_T2_TRGO ADC_CFGR1_EXTSEL_1\r
+\r
+/* TIM3 */\r
+#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1))\r
+\r
+/* TIM15 */\r
+#define ADC_ExternalTrigConv_T15_TRGO ADC_CFGR1_EXTSEL_2\r
+\r
+#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_ExternalTrigConv_T1_TRGO) || \\r
+ ((CONV) == ADC_ExternalTrigConv_T1_CC4) || \\r
+ ((CONV) == ADC_ExternalTrigConv_T2_TRGO) || \\r
+ ((CONV) == ADC_ExternalTrigConv_T3_TRGO) || \\r
+ ((CONV) == ADC_ExternalTrigConv_T15_TRGO)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_data_align \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)\r
+#define ADC_DataAlign_Left ADC_CFGR1_ALIGN\r
+\r
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \\r
+ ((ALIGN) == ADC_DataAlign_Left))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Scan_Direction \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_ScanDirection_Upward ((uint32_t)0x00000000)\r
+#define ADC_ScanDirection_Backward ADC_CFGR1_SCANDIR\r
+\r
+#define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_ScanDirection_Upward) || \\r
+ ((DIRECTION) == ADC_ScanDirection_Backward))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_Scan_Direction \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_DMAMode_OneShot ((uint32_t)0x00000000)\r
+#define ADC_DMAMode_Circular ADC_CFGR1_DMACFG\r
+\r
+#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || \\r
+ ((MODE) == ADC_DMAMode_Circular))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup ADC_analog_watchdog_selection \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_AnalogWatchdog_Channel_0 ((uint32_t)0x00000000)\r
+#define ADC_AnalogWatchdog_Channel_1 ((uint32_t)0x04000000)\r
+#define ADC_AnalogWatchdog_Channel_2 ((uint32_t)0x08000000)\r
+#define ADC_AnalogWatchdog_Channel_3 ((uint32_t)0x0C000000)\r
+#define ADC_AnalogWatchdog_Channel_4 ((uint32_t)0x10000000)\r
+#define ADC_AnalogWatchdog_Channel_5 ((uint32_t)0x14000000)\r
+#define ADC_AnalogWatchdog_Channel_6 ((uint32_t)0x18000000)\r
+#define ADC_AnalogWatchdog_Channel_7 ((uint32_t)0x1C000000)\r
+#define ADC_AnalogWatchdog_Channel_8 ((uint32_t)0x20000000)\r
+#define ADC_AnalogWatchdog_Channel_9 ((uint32_t)0x24000000)\r
+#define ADC_AnalogWatchdog_Channel_10 ((uint32_t)0x28000000)\r
+#define ADC_AnalogWatchdog_Channel_11 ((uint32_t)0x2C000000)\r
+#define ADC_AnalogWatchdog_Channel_12 ((uint32_t)0x30000000)\r
+#define ADC_AnalogWatchdog_Channel_13 ((uint32_t)0x34000000)\r
+#define ADC_AnalogWatchdog_Channel_14 ((uint32_t)0x38000000)\r
+#define ADC_AnalogWatchdog_Channel_15 ((uint32_t)0x3C000000)\r
+#define ADC_AnalogWatchdog_Channel_16 ((uint32_t)0x40000000)\r
+#define ADC_AnalogWatchdog_Channel_17 ((uint32_t)0x44000000)\r
+#define ADC_AnalogWatchdog_Channel_18 ((uint32_t)0x48000000)\r
+\r
+\r
+#define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_1) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_2) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_3) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_4) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_5) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_6) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_7) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_8) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_9) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_10) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_11) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_12) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_13) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_14) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_15) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_16) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_17) || \\r
+ ((CHANNEL) == ADC_AnalogWatchdog_Channel_18))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup ADC_sampling_times \r
+ * @{\r
+ */ \r
+\r
+#define ADC_SampleTime_1_5Cycles ((uint32_t)0x00000000)\r
+#define ADC_SampleTime_7_5Cycles ((uint32_t)0x00000001)\r
+#define ADC_SampleTime_13_5Cycles ((uint32_t)0x00000002)\r
+#define ADC_SampleTime_28_5Cycles ((uint32_t)0x00000003)\r
+#define ADC_SampleTime_41_5Cycles ((uint32_t)0x00000004)\r
+#define ADC_SampleTime_55_5Cycles ((uint32_t)0x00000005)\r
+#define ADC_SampleTime_71_5Cycles ((uint32_t)0x00000006)\r
+#define ADC_SampleTime_239_5Cycles ((uint32_t)0x00000007)\r
+\r
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles) || \\r
+ ((TIME) == ADC_SampleTime_7_5Cycles) || \\r
+ ((TIME) == ADC_SampleTime_13_5Cycles) || \\r
+ ((TIME) == ADC_SampleTime_28_5Cycles) || \\r
+ ((TIME) == ADC_SampleTime_41_5Cycles) || \\r
+ ((TIME) == ADC_SampleTime_55_5Cycles) || \\r
+ ((TIME) == ADC_SampleTime_71_5Cycles) || \\r
+ ((TIME) == ADC_SampleTime_239_5Cycles))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_thresholds \r
+ * @{\r
+ */ \r
+ \r
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_channels \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_Channel_0 ADC_CHSELR_CHSEL0\r
+#define ADC_Channel_1 ADC_CHSELR_CHSEL1\r
+#define ADC_Channel_2 ADC_CHSELR_CHSEL2\r
+#define ADC_Channel_3 ADC_CHSELR_CHSEL3\r
+#define ADC_Channel_4 ADC_CHSELR_CHSEL4\r
+#define ADC_Channel_5 ADC_CHSELR_CHSEL5\r
+#define ADC_Channel_6 ADC_CHSELR_CHSEL6\r
+#define ADC_Channel_7 ADC_CHSELR_CHSEL7\r
+#define ADC_Channel_8 ADC_CHSELR_CHSEL8\r
+#define ADC_Channel_9 ADC_CHSELR_CHSEL9\r
+#define ADC_Channel_10 ADC_CHSELR_CHSEL10\r
+#define ADC_Channel_11 ADC_CHSELR_CHSEL11\r
+#define ADC_Channel_12 ADC_CHSELR_CHSEL12\r
+#define ADC_Channel_13 ADC_CHSELR_CHSEL13\r
+#define ADC_Channel_14 ADC_CHSELR_CHSEL14\r
+#define ADC_Channel_15 ADC_CHSELR_CHSEL15\r
+#define ADC_Channel_16 ADC_CHSELR_CHSEL16\r
+#define ADC_Channel_17 ADC_CHSELR_CHSEL17\r
+#define ADC_Channel_18 ADC_CHSELR_CHSEL18\r
+\r
+#define ADC_Channel_TempSensor ((uint32_t)ADC_Channel_16)\r
+#define ADC_Channel_Vrefint ((uint32_t)ADC_Channel_17)\r
+#define ADC_Channel_Vbat ((uint32_t)ADC_Channel_18)\r
+\r
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFF80000) == (uint32_t)RESET))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup ADC_interrupts_definition \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_IT_ADRDY ADC_IER_ADRDYIE\r
+#define ADC_IT_EOSMP ADC_IER_EOSMPIE\r
+#define ADC_IT_EOC ADC_IER_EOCIE\r
+#define ADC_IT_EOS ADC_IER_EOSIE\r
+#define ADC_IT_OVR ADC_IER_OVRIE\r
+#define ADC_IT_AWD ADC_IER_AWDIE\r
+ \r
+#define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))\r
+\r
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \\r
+ ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOS) || \\r
+ ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_AWD))\r
+\r
+#define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ADC_flags_definition \r
+ * @{\r
+ */ \r
+ \r
+#define ADC_FLAG_ADRDY ADC_ISR_ADRDY\r
+#define ADC_FLAG_EOSMP ADC_ISR_EOSMP\r
+#define ADC_FLAG_EOC ADC_ISR_EOC\r
+#define ADC_FLAG_EOS ADC_ISR_EOS\r
+#define ADC_FLAG_OVR ADC_ISR_OVR\r
+#define ADC_FLAG_AWD ADC_ISR_AWD\r
+\r
+#define ADC_FLAG_ADEN ((uint32_t)0x01000001)\r
+#define ADC_FLAG_ADDIS ((uint32_t)0x01000002)\r
+#define ADC_FLAG_ADSTART ((uint32_t)0x01000004)\r
+#define ADC_FLAG_ADSTP ((uint32_t)0x01000008)\r
+#define ADC_FLAG_ADCAL ((uint32_t)0x11000000)\r
+\r
+#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xEFFFFF60) == (uint32_t)RESET))\r
+\r
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY) || ((FLAG) == ADC_FLAG_EOSMP) || \\r
+ ((FLAG) == ADC_FLAG_EOC) || ((FLAG)== ADC_FLAG_EOS) || \\r
+ ((FLAG) == ADC_FLAG_AWD) || ((FLAG)== ADC_FLAG_OVR) || \\r
+ ((FLAG) == ADC_FLAG_ADEN) || ((FLAG)== ADC_FLAG_ADDIS) || \\r
+ ((FLAG) == ADC_FLAG_ADSTART) || ((FLAG)== ADC_FLAG_ADSTP) || \\r
+ ((FLAG) == ADC_FLAG_ADCAL))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* Function used to set the ADC configuration to the default reset state *****/\r
+void ADC_DeInit(ADC_TypeDef* ADCx);\r
+\r
+/* Initialization and Configuration functions *********************************/ \r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState);\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+\r
+/* Power saving functions *****************************************************/\r
+void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_AutoDelayConversionCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+\r
+/* Analog Watchdog configuration functions ************************************/\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel);\r
+void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+\r
+/* Temperature Sensor , Vrefint and Vbat management function ******************/\r
+void ADC_TempSensorCmd(FunctionalState NewState);\r
+void ADC_VrefintCmd(FunctionalState NewState);\r
+void ADC_VbatCmd(FunctionalState NewState);\r
+\r
+/* Channels Configuration functions *******************************************/\r
+void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime);\r
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx);\r
+void ADC_StopOfConversion(ADC_TypeDef* ADCx);\r
+void ADC_StartOfConversion(ADC_TypeDef* ADCx);\r
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);\r
+\r
+/* Regular Channels DMA Configuration functions *******************************/\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F0XX_ADC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_cec.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the CEC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_CEC_H\r
+#define __STM32F0XX_CEC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CEC\r
+ * @{\r
+ */\r
+/* Exported types ------------------------------------------------------------*/\r
+ \r
+/** \r
+ * @brief CEC Init structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t CEC_SignalFreeTime; /*!< Specifies the CEC Signal Free Time configuration.\r
+ This parameter can be a value of @ref CEC_Signal_Free_Time */\r
+ uint32_t CEC_RxTolerance; /*!< Specifies the CEC Reception Tolerance.\r
+ This parameter can be a value of @ref CEC_RxTolerance */\r
+ uint32_t CEC_StopReception; /*!< Specifies the CEC Stop Reception.\r
+ This parameter can be a value of @ref CEC_Stop_Reception */\r
+ uint32_t CEC_BitRisingError; /*!< Specifies the CEC Bit Rising Error generation.\r
+ This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */\r
+ uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation.\r
+ This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */\r
+ uint32_t CEC_BRDNoGen; /*!< Specifies the CEC Broadcast Error generation.\r
+ This parameter can be a value of @ref CEC_BDR_No_Gen */\r
+ uint32_t CEC_SFTOption; /*!< Specifies the CEC Signal Free Time option.\r
+ This parameter can be a value of @ref CEC_SFT_Option */\r
+\r
+}CEC_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup CEC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CEC_Signal_Free_Time\r
+ * @{\r
+ */\r
+#define CEC_SignalFreeTime_Standard ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard */\r
+#define CEC_SignalFreeTime_1T ((uint32_t)0x00000001) /*!< CEC 1.5 nominal data bit periods */\r
+#define CEC_SignalFreeTime_2T ((uint32_t)0x00000002) /*!< CEC 2.5 nominal data bit periods */\r
+#define CEC_SignalFreeTime_3T ((uint32_t)0x00000003) /*!< CEC 3.5 nominal data bit periods */\r
+#define CEC_SignalFreeTime_4T ((uint32_t)0x00000004) /*!< CEC 4.5 nominal data bit periods */\r
+#define CEC_SignalFreeTime_5T ((uint32_t)0x00000005) /*!< CEC 5.5 nominal data bit periods */\r
+#define CEC_SignalFreeTime_6T ((uint32_t)0x00000006) /*!< CEC 6.5 nominal data bit periods */\r
+#define CEC_SignalFreeTime_7T ((uint32_t)0x00000007) /*!< CEC 7.5 nominal data bit periods */\r
+\r
+#define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \\r
+ ((TIME) == CEC_SignalFreeTime_1T)|| \\r
+ ((TIME) == CEC_SignalFreeTime_2T)|| \\r
+ ((TIME) == CEC_SignalFreeTime_3T)|| \\r
+ ((TIME) == CEC_SignalFreeTime_4T)|| \\r
+ ((TIME) == CEC_SignalFreeTime_5T)|| \\r
+ ((TIME) == CEC_SignalFreeTime_6T)|| \\r
+ ((TIME) == CEC_SignalFreeTime_7T))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_RxTolerance\r
+ * @{\r
+ */\r
+#define CEC_RxTolerance_Standard ((uint32_t)0x00000000) /*!< Standard Tolerance Margin */\r
+#define CEC_RxTolerance_Extended CEC_CFGR_RXTOL /*!< Extended Tolerance Margin */\r
+\r
+#define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \\r
+ ((TOLERANCE) == CEC_RxTolerance_Extended))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Stop_Reception\r
+ * @{\r
+ */\r
+#define CEC_StopReception_Off ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE) */\r
+#define CEC_StopReception_On CEC_CFGR_BRESTP /*!< RX Stop on bit Rising Error (BRE) */\r
+\r
+#define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \\r
+ ((RECEPTION) == CEC_StopReception_Off))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Bit_Rising_Error_Generation\r
+ * @{\r
+ */\r
+#define CEC_BitRisingError_Off ((uint32_t)0x00000000) /*!< Bit Rising Error generation turned Off */\r
+#define CEC_BitRisingError_On CEC_CFGR_BREGEN /*!< Bit Rising Error generation turned On */\r
+\r
+#define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \\r
+ ((ERROR) == CEC_BitRisingError_On))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Long_Bit_Error_Generation\r
+ * @{\r
+ */\r
+#define CEC_LongBitPeriodError_Off ((uint32_t)0x00000000) /*!< Long Bit Period Error generation turned Off */\r
+#define CEC_LongBitPeriodError_On CEC_CFGR_LREGEN /*!< Long Bit Period Error generation turned On */\r
+\r
+#define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \\r
+ ((ERROR) == CEC_LongBitPeriodError_On))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_BDR_No_Gen\r
+ * @{\r
+ */\r
+\r
+#define CEC_BRDNoGen_Off ((uint32_t)0x00000000) /*!< Broadcast Bit Rising Error generation turned Off */\r
+#define CEC_BRDNoGen_On CEC_CFGR_BRDNOGEN /*!< Broadcast Bit Rising Error generation turned On */\r
+\r
+#define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \\r
+ ((ERROR) == CEC_BRDNoGen_On))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_SFT_Option\r
+ * @{\r
+ */\r
+#define CEC_SFTOption_Off ((uint32_t)0x00000000) /*!< SFT option turned Off */\r
+#define CEC_SFTOption_On CEC_CFGR_SFTOPT /*!< SFT option turned On */\r
+\r
+#define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \\r
+ ((OPTION) == CEC_SFTOption_On))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Own_Address\r
+ * @{\r
+ */\r
+#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Interrupt_Configuration_definition\r
+ * @{\r
+ */\r
+#define CEC_IT_TXACKE CEC_IER_TXACKEIE\r
+#define CEC_IT_TXERR CEC_IER_TXERRIE\r
+#define CEC_IT_TXUDR CEC_IER_TXUDRIE\r
+#define CEC_IT_TXEND CEC_IER_TXENDIE\r
+#define CEC_IT_TXBR CEC_IER_TXBRIE\r
+#define CEC_IT_ARBLST CEC_IER_ARBLSTIE\r
+#define CEC_IT_RXACKE CEC_IER_RXACKEIE\r
+#define CEC_IT_LBPE CEC_IER_LBPEIE\r
+#define CEC_IT_SBPE CEC_IER_SBPEIE\r
+#define CEC_IT_BRE CEC_IER_BREIEIE\r
+#define CEC_IT_RXOVR CEC_IER_RXOVRIE\r
+#define CEC_IT_RXEND CEC_IER_RXENDIE\r
+#define CEC_IT_RXBR CEC_IER_RXBRIE\r
+\r
+#define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \\r
+ ((IT) == CEC_IT_TXERR)|| \\r
+ ((IT) == CEC_IT_TXUDR)|| \\r
+ ((IT) == CEC_IT_TXEND)|| \\r
+ ((IT) == CEC_IT_TXBR)|| \\r
+ ((IT) == CEC_IT_ARBLST)|| \\r
+ ((IT) == CEC_IT_RXACKE)|| \\r
+ ((IT) == CEC_IT_LBPE)|| \\r
+ ((IT) == CEC_IT_SBPE)|| \\r
+ ((IT) == CEC_IT_BRE)|| \\r
+ ((IT) == CEC_IT_RXOVR)|| \\r
+ ((IT) == CEC_IT_RXEND)|| \\r
+ ((IT) == CEC_IT_RXBR))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_ISR_register_flags_definition\r
+ * @{\r
+ */\r
+#define CEC_FLAG_TXACKE CEC_ISR_TXACKE\r
+#define CEC_FLAG_TXERR CEC_ISR_TXERR\r
+#define CEC_FLAG_TXUDR CEC_ISR_TXUDR\r
+#define CEC_FLAG_TXEND CEC_ISR_TXEND\r
+#define CEC_FLAG_TXBR CEC_ISR_TXBR\r
+#define CEC_FLAG_ARBLST CEC_ISR_ARBLST\r
+#define CEC_FLAG_RXACKE CEC_ISR_RXACKE\r
+#define CEC_FLAG_LBPE CEC_ISR_LBPE\r
+#define CEC_FLAG_SBPE CEC_ISR_SBPE\r
+#define CEC_FLAG_BRE CEC_ISR_BRE\r
+#define CEC_FLAG_RXOVR CEC_ISR_RXOVR\r
+#define CEC_FLAG_RXEND CEC_ISR_RXEND\r
+#define CEC_FLAG_RXBR CEC_ISR_RXBR\r
+\r
+#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00))\r
+\r
+#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \\r
+ ((FLAG) == CEC_FLAG_TXERR)|| \\r
+ ((FLAG) == CEC_FLAG_TXUDR)|| \\r
+ ((FLAG) == CEC_FLAG_TXEND)|| \\r
+ ((FLAG) == CEC_FLAG_TXBR)|| \\r
+ ((FLAG) == CEC_FLAG_ARBLST)|| \\r
+ ((FLAG) == CEC_FLAG_RXACKE)|| \\r
+ ((FLAG) == CEC_FLAG_LBPE)|| \\r
+ ((FLAG) == CEC_FLAG_SBPE)|| \\r
+ ((FLAG) == CEC_FLAG_BRE)|| \\r
+ ((FLAG) == CEC_FLAG_RXOVR)|| \\r
+ ((FLAG) == CEC_FLAG_RXEND)|| \\r
+ ((FLAG) == CEC_FLAG_RXBR))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the CEC configuration to the default reset state *****/\r
+void CEC_DeInit(void);\r
+\r
+/* CEC_Initialization and Configuration functions *****************************/\r
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);\r
+void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct);\r
+void CEC_Cmd(FunctionalState NewState);\r
+void CEC_ListenModeCmd(FunctionalState NewState);\r
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);\r
+void CEC_OwnAddressClear(void);\r
+\r
+/* CEC_Data transfers functions ***********************************************/\r
+void CEC_SendData(uint8_t Data);\r
+uint8_t CEC_ReceiveData(void);\r
+void CEC_StartOfMessage(void);\r
+void CEC_EndOfMessage(void);\r
+\r
+/* CEC_Interrupts and flags management functions ******************************/\r
+void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState);\r
+FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);\r
+void CEC_ClearFlag(uint32_t CEC_FLAG);\r
+ITStatus CEC_GetITStatus(uint16_t CEC_IT);\r
+void CEC_ClearITPendingBit(uint16_t CEC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F0XX_CEC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_comp.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the COMP firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_COMP_H\r
+#define __STM32F0XX_COMP_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup COMP\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief COMP Init structure definition \r
+ */\r
+ \r
+typedef struct\r
+{\r
+\r
+ uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator.\r
+ This parameter can be a value of @ref COMP_InvertingInput */\r
+\r
+ uint32_t COMP_Output; /*!< Selects the output redirection of the comparator.\r
+ This parameter can be a value of @ref COMP_Output */\r
+\r
+ uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator.\r
+ This parameter can be a value of @ref COMP_OutputPolarity */\r
+\r
+ uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator.\r
+ This parameter can be a value of @ref COMP_Hysteresis */\r
+\r
+ uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator\r
+ and allows to adjust the speed/consumption.\r
+ This parameter can be a value of @ref COMP_Mode */\r
+\r
+}COMP_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+ \r
+/** @defgroup COMP_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup COMP_Selection\r
+ * @{\r
+ */\r
+\r
+#define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */\r
+#define COMP_Selection_COMP2 ((uint32_t)0x00000010) /*!< COMP2 Selection */\r
+\r
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \\r
+ ((PERIPH) == COMP_Selection_COMP2))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup COMP_InvertingInput\r
+ * @{\r
+ */\r
+\r
+#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */\r
+#define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMP1INSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */\r
+#define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMP1INSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */\r
+#define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */\r
+#define COMP_InvertingInput_DAC1 COMP_CSR_COMP1INSEL_2 /*!< DAC1_OUT connected to comparator inverting input */\r
+#define COMP_InvertingInput_IO ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */\r
+\r
+#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_DAC1) || \\r
+ ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \\r
+ ((INPUT) == COMP_InvertingInput_IO))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup COMP_Output\r
+ * @{\r
+ */\r
+\r
+#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */\r
+#define COMP_Output_TIM1BKIN COMP_CSR_COMP1OUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */\r
+#define COMP_Output_TIM1IC1 COMP_CSR_COMP1OUTSEL_1 /*!< COMP output connected to TIM1 Input Capture 1 */\r
+#define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00000300) /*!< COMP output connected to TIM1 OCREF Clear */\r
+#define COMP_Output_TIM2IC4 COMP_CSR_COMP1OUTSEL_2 /*!< COMP output connected to TIM2 Input Capture 4 */\r
+#define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00000500) /*!< COMP output connected to TIM2 OCREF Clear */\r
+#define COMP_Output_TIM3IC1 ((uint32_t)0x00000600) /*!< COMP output connected to TIM3 Input Capture 1 */\r
+#define COMP_Output_TIM3OCREFCLR COMP_CSR_COMP1OUTSEL /*!< COMP output connected to TIM3 OCREF Clear */\r
+\r
+\r
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \\r
+ ((OUTPUT) == COMP_Output_TIM1BKIN) || \\r
+ ((OUTPUT) == COMP_Output_TIM1IC1) || \\r
+ ((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \\r
+ ((OUTPUT) == COMP_Output_TIM2IC4) || \\r
+ ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \\r
+ ((OUTPUT) == COMP_Output_TIM3IC1) || \\r
+ ((OUTPUT) == COMP_Output_TIM3OCREFCLR))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup COMP_OutputPolarity\r
+ * @{\r
+ */\r
+#define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */\r
+#define COMP_OutputPol_Inverted COMP_CSR_COMP1POL /*!< COMP output on GPIO is inverted */\r
+\r
+#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \\r
+ ((POL) == COMP_OutputPol_Inverted))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup COMP_Hysteresis\r
+ * @{\r
+ */\r
+/* Please refer to the electrical characteristics in the device datasheet for\r
+ the hysteresis level */\r
+#define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */\r
+#define COMP_Hysteresis_Low COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */\r
+#define COMP_Hysteresis_Medium COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */\r
+#define COMP_Hysteresis_High COMP_CSR_COMP1HYST /*!< Hysteresis level high */\r
+\r
+#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \\r
+ ((HYSTERESIS) == COMP_Hysteresis_Low) || \\r
+ ((HYSTERESIS) == COMP_Hysteresis_Medium) || \\r
+ ((HYSTERESIS) == COMP_Hysteresis_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup COMP_Mode\r
+ * @{\r
+ */\r
+/* Please refer to the electrical characteristics in the device datasheet for\r
+ the power consumption values */\r
+#define COMP_Mode_UltraLowPower 0x00000000 /*!< Ultra-low power mode */\r
+#define COMP_Mode_LowPower COMP_CSR_COMP1MODE_0 /*!< Low power mode */\r
+#define COMP_Mode_MediumSpeed COMP_CSR_COMP1MODE_1 /*!< Medium Speed */\r
+#define COMP_Mode_HighSpeed COMP_CSR_COMP1MODE /*!< High Speed */\r
+\r
+#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \\r
+ ((MODE) == COMP_Mode_LowPower) || \\r
+ ((MODE) == COMP_Mode_MediumSpeed) || \\r
+ ((MODE) == COMP_Mode_HighSpeed))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup COMP_OutputLevel\r
+ * @{\r
+ */ \r
+/* When output polarity is not inverted, comparator output is high when\r
+ the non-inverting input is at a higher voltage than the inverting input */\r
+#define COMP_OutputLevel_High COMP_CSR_COMP1OUT\r
+/* When output polarity is not inverted, comparator output is low when\r
+ the non-inverting input is at a lower voltage than the inverting input*/\r
+#define COMP_OutputLevel_Low ((uint32_t)0x00000000)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the COMP configuration to the default reset state ****/\r
+void COMP_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);\r
+void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);\r
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);\r
+void COMP_SwitchCmd(FunctionalState NewState);\r
+uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);\r
+\r
+/* Window mode control function ***********************************************/\r
+void COMP_WindowCmd(FunctionalState NewState);\r
+\r
+/* COMP configuration locking function ****************************************/\r
+void COMP_LockConfig(uint32_t COMP_Selection);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F0XX_COMP_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_crc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the CRC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_CRC_H\r
+#define __STM32F0XX_CRC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*!< Includes ----------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup CRC_Exported_Constants\r
+ * @{\r
+ */\r
+#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */\r
+#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */\r
+#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */\r
+#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */\r
+\r
+#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \\r
+ ((DATA) == CRC_ReverseInputData_8bits) || \\r
+ ((DATA) == CRC_ReverseInputData_16bits) || \\r
+ ((DATA) == CRC_ReverseInputData_32bits))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+/* Configuration of the CRC computation unit **********************************/\r
+void CRC_DeInit(void);\r
+void CRC_ResetDR(void);\r
+void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);\r
+void CRC_ReverseOutputDataCmd(FunctionalState NewState);\r
+void CRC_SetInitRegister(uint32_t CRC_InitValue);\r
+\r
+/* CRC computation ************************************************************/\r
+uint32_t CRC_CalcCRC(uint32_t CRC_Data);\r
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);\r
+uint32_t CRC_GetCRC(void);\r
+\r
+/* Independent register (IDR) access (write/read) *****************************/\r
+void CRC_SetIDRegister(uint8_t CRC_IDValue);\r
+uint8_t CRC_GetIDRegister(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F0XX_CRC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_dac.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the DAC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_DAC_H\r
+#define __STM32F0XX_DAC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+ \r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DAC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief DAC Init structure definition\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.\r
+ This parameter can be a value of @ref DAC_Trigger */\r
+\r
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.\r
+ This parameter can be a value of @ref DAC_OutputBuffer */\r
+}DAC_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DAC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC_Trigger \r
+ * @{\r
+ */\r
+ \r
+#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \r
+ has been loaded, and not by external trigger */\r
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */\r
+\r
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \\r
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T3_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T15_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \\r
+ ((TRIGGER) == DAC_Trigger_Software))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_OutputBuffer \r
+ * @{\r
+ */\r
+\r
+#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)\r
+#define DAC_OutputBuffer_Disable DAC_CR_BOFF1\r
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \\r
+ ((STATE) == DAC_OutputBuffer_Disable))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DAC_Channel_selection \r
+ * @{\r
+ */\r
+\r
+#define DAC_Channel_1 ((uint32_t)0x00000000)\r
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data_alignment\r
+ * @{\r
+ */\r
+\r
+#define DAC_Align_12b_R ((uint32_t)0x00000000)\r
+#define DAC_Align_12b_L ((uint32_t)0x00000004)\r
+#define DAC_Align_8b_R ((uint32_t)0x00000008)\r
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \\r
+ ((ALIGN) == DAC_Align_12b_L) || \\r
+ ((ALIGN) == DAC_Align_8b_R))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data \r
+ * @{\r
+ */\r
+\r
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_interrupts_definition \r
+ * @{\r
+ */ \r
+ \r
+#define DAC_IT_DMAUDR DAC_SR_DMAUDR1\r
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DAC_flags_definition \r
+ * @{\r
+ */ \r
+ \r
+#define DAC_FLAG_DMAUDR DAC_SR_DMAUDR1\r
+ \r
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the DAC configuration to the default reset state *****/\r
+void DAC_DeInit(void);\r
+\r
+/* DAC channels configuration: trigger, output buffer, data format functions */\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);\r
+\r
+/* DMA management functions ***************************************************/\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);\r
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);\r
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F0XX_DAC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_dbgmcu.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the DBGMCU firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_DBGMCU_H\r
+#define __STM32F0XX_DBGMCU_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DBGMCU\r
+ * @{\r
+ */ \r
+/* Exported types ------------------------------------------------------------*/ \r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+\r
+/** @defgroup DBGMCU_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define DBGMCU_STOP DBGMCU_CR_DBG_STOP\r
+#define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY\r
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF9) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+#define DBGMCU_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP\r
+#define DBGMCU_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP\r
+#define DBGMCU_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP\r
+#define DBGMCU_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP\r
+#define DBGMCU_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP\r
+#define DBGMCU_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP\r
+#define DBGMCU_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP\r
+#define DBGMCU_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT\r
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFFDFE2EC) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+#define DBGMCU_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP\r
+#define DBGMCU_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP\r
+#define DBGMCU_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP\r
+#define DBGMCU_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP\r
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8F7FF) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* Device and Revision ID management functions ********************************/ \r
+uint32_t DBGMCU_GetREVID(void);\r
+uint32_t DBGMCU_GetDEVID(void);\r
+\r
+/* Peripherals Configuration functions ****************************************/ \r
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F0XX_DBGMCU_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_dma.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the DMA firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_DMA_H\r
+#define __STM32F0XX_DMA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA\r
+ * @{\r
+ */\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief DMA Init structures definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */\r
+\r
+ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */\r
+\r
+ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.\r
+ This parameter can be a value of @ref DMA_data_transfer_direction */\r
+\r
+ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. \r
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize\r
+ or DMA_MemoryDataSize members depending in the transfer direction */\r
+\r
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.\r
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */\r
+\r
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.\r
+ This parameter can be a value of @ref DMA_memory_incremented_mode */\r
+\r
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.\r
+ This parameter can be a value of @ref DMA_peripheral_data_size */\r
+\r
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.\r
+ This parameter can be a value of @ref DMA_memory_data_size */\r
+\r
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_circular_normal_mode\r
+ @note: The circular buffer mode cannot be used if the memory-to-memory\r
+ data transfer is configured on the selected Channel */\r
+\r
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_priority_level */\r
+\r
+ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.\r
+ This parameter can be a value of @ref DMA_memory_to_memory */\r
+}DMA_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \\r
+ ((PERIPH) == DMA1_Channel2) || \\r
+ ((PERIPH) == DMA1_Channel3) || \\r
+ ((PERIPH) == DMA1_Channel4) || \\r
+ ((PERIPH) == DMA1_Channel5))\r
+\r
+/** @defgroup DMA_data_transfer_direction \r
+ * @{\r
+ */\r
+\r
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)\r
+#define DMA_DIR_PeripheralDST DMA_CCR_DIR\r
+\r
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \\r
+ ((DIR) == DMA_DIR_PeripheralDST))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_peripheral_incremented_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)\r
+#define DMA_PeripheralInc_Enable DMA_CCR_PINC\r
+\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \\r
+ ((STATE) == DMA_PeripheralInc_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_incremented_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)\r
+#define DMA_MemoryInc_Enable DMA_CCR_MINC\r
+\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \\r
+ ((STATE) == DMA_MemoryInc_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_peripheral_data_size \r
+ * @{\r
+ */\r
+\r
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)\r
+#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0\r
+#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1\r
+\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_Word))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_data_size \r
+ * @{\r
+ */\r
+\r
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)\r
+#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0\r
+#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1\r
+\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \\r
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_MemoryDataSize_Word))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_circular_normal_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_Mode_Normal ((uint32_t)0x00000000)\r
+#define DMA_Mode_Circular DMA_CCR_CIRC\r
+\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_priority_level \r
+ * @{\r
+ */\r
+\r
+#define DMA_Priority_VeryHigh DMA_CCR_PL\r
+#define DMA_Priority_High DMA_CCR_PL_1\r
+#define DMA_Priority_Medium DMA_CCR_PL_0\r
+#define DMA_Priority_Low ((uint32_t)0x00000000)\r
+\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \\r
+ ((PRIORITY) == DMA_Priority_High) || \\r
+ ((PRIORITY) == DMA_Priority_Medium) || \\r
+ ((PRIORITY) == DMA_Priority_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_to_memory \r
+ * @{\r
+ */\r
+\r
+#define DMA_M2M_Disable ((uint32_t)0x00000000)\r
+#define DMA_M2M_Enable DMA_CCR_MEM2MEM\r
+\r
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_interrupts_definition\r
+ * @{\r
+ */\r
+\r
+#define DMA_IT_TC DMA_CCR_TCIE\r
+#define DMA_IT_HT DMA_CCR_HTIE\r
+#define DMA_IT_TE DMA_CCR_TEIE\r
+\r
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))\r
+\r
+#define DMA1_IT_GL1 DMA_ISR_GIF1\r
+#define DMA1_IT_TC1 DMA_ISR_TCIF1\r
+#define DMA1_IT_HT1 DMA_ISR_HTIF1\r
+#define DMA1_IT_TE1 DMA_ISR_TEIF1\r
+#define DMA1_IT_GL2 DMA_ISR_GIF2\r
+#define DMA1_IT_TC2 DMA_ISR_TCIF2\r
+#define DMA1_IT_HT2 DMA_ISR_HTIF2\r
+#define DMA1_IT_TE2 DMA_ISR_TEIF2\r
+#define DMA1_IT_GL3 DMA_ISR_GIF3\r
+#define DMA1_IT_TC3 DMA_ISR_TCIF3\r
+#define DMA1_IT_HT3 DMA_ISR_HTIF3\r
+#define DMA1_IT_TE3 DMA_ISR_TEIF3\r
+#define DMA1_IT_GL4 DMA_ISR_GIF4\r
+#define DMA1_IT_TC4 DMA_ISR_TCIF4\r
+#define DMA1_IT_HT4 DMA_ISR_HTIF4\r
+#define DMA1_IT_TE4 DMA_ISR_TEIF4\r
+#define DMA1_IT_GL5 DMA_ISR_GIF5\r
+#define DMA1_IT_TC5 DMA_ISR_TCIF5\r
+#define DMA1_IT_HT5 DMA_ISR_HTIF5\r
+#define DMA1_IT_TE5 DMA_ISR_TEIF5\r
+\r
+#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xFFF00000) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \\r
+ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \\r
+ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \\r
+ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \\r
+ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \\r
+ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \\r
+ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \\r
+ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \\r
+ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \\r
+ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_flags_definition \r
+ * @{\r
+ */\r
+#define DMA1_FLAG_GL1 DMA_ISR_GIF1\r
+#define DMA1_FLAG_TC1 DMA_ISR_TCIF1\r
+#define DMA1_FLAG_HT1 DMA_ISR_HTIF1\r
+#define DMA1_FLAG_TE1 DMA_ISR_TEIF1\r
+#define DMA1_FLAG_GL2 DMA_ISR_GIF2\r
+#define DMA1_FLAG_TC2 DMA_ISR_TCIF2\r
+#define DMA1_FLAG_HT2 DMA_ISR_HTIF2\r
+#define DMA1_FLAG_TE2 DMA_ISR_TEIF2\r
+#define DMA1_FLAG_GL3 DMA_ISR_GIF3\r
+#define DMA1_FLAG_TC3 DMA_ISR_TCIF3\r
+#define DMA1_FLAG_HT3 DMA_ISR_HTIF3\r
+#define DMA1_FLAG_TE3 DMA_ISR_TEIF3\r
+#define DMA1_FLAG_GL4 DMA_ISR_GIF4\r
+#define DMA1_FLAG_TC4 DMA_ISR_TCIF4\r
+#define DMA1_FLAG_HT4 DMA_ISR_HTIF4\r
+#define DMA1_FLAG_TE4 DMA_ISR_TEIF4\r
+#define DMA1_FLAG_GL5 DMA_ISR_GIF5\r
+#define DMA1_FLAG_TC5 DMA_ISR_TCIF5\r
+#define DMA1_FLAG_HT5 DMA_ISR_HTIF5\r
+#define DMA1_FLAG_TE5 DMA_ISR_TEIF5\r
+\r
+#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xFFF00000) == 0x00) && ((FLAG) != 0x00))\r
+\r
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \\r
+ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \\r
+ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \\r
+ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \\r
+ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \\r
+ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \\r
+ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \\r
+ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \\r
+ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \\r
+ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Buffer_Size \r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the DMA configuration to the default reset state ******/\r
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);\r
+\r
+/* Data Counter functions******************************************************/ \r
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);\r
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);\r
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);\r
+void DMA_ClearFlag(uint32_t DMA_FLAG);\r
+ITStatus DMA_GetITStatus(uint32_t DMA_IT);\r
+void DMA_ClearITPendingBit(uint32_t DMA_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F0XX_DMA_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_exti.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the EXTI \r
+ * firmware library\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_EXTI_H\r
+#define __STM32F0XX_EXTI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup EXTI\r
+ * @{\r
+ */\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief EXTI mode enumeration \r
+ */\r
+\r
+typedef enum\r
+{\r
+ EXTI_Mode_Interrupt = 0x00,\r
+ EXTI_Mode_Event = 0x04\r
+}EXTIMode_TypeDef;\r
+\r
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))\r
+\r
+/** \r
+ * @brief EXTI Trigger enumeration \r
+ */\r
+\r
+typedef enum\r
+{\r
+ EXTI_Trigger_Rising = 0x08,\r
+ EXTI_Trigger_Falling = 0x0C,\r
+ EXTI_Trigger_Rising_Falling = 0x10\r
+}EXTITrigger_TypeDef;\r
+\r
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \\r
+ ((TRIGGER) == EXTI_Trigger_Falling) || \\r
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))\r
+/**\r
+ * @brief EXTI Init Structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.\r
+ This parameter can be any combination of @ref EXTI_Lines */\r
+\r
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.\r
+ This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.\r
+ This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.\r
+ This parameter can be set either to ENABLE or DISABLE */\r
+}EXTI_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup EXTI_Exported_Constants\r
+ * @{\r
+ */\r
+/** @defgroup EXTI_Lines \r
+ * @{\r
+ */\r
+\r
+#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */\r
+#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */\r
+#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */\r
+#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */\r
+#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */\r
+#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */\r
+#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */\r
+#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */\r
+#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */\r
+#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */\r
+#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */\r
+#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */\r
+#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */\r
+#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */\r
+#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */\r
+#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */\r
+#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16 \r
+ Connected to the PVD Output */\r
+#define EXTI_Line17 ((uint32_t)0x00020000) /*!< Internal interrupt line 17 \r
+ Connected to the RTC Alarm \r
+ event */\r
+#define EXTI_Line19 ((uint32_t)0x00080000) /*!< Internal interrupt line 19\r
+ Connected to the RTC Tamper\r
+ and Time Stamp events */\r
+#define EXTI_Line21 ((uint32_t)0x00200000) /*!< Internal interrupt line 21\r
+ Connected to the Comparator 1\r
+ event */\r
+#define EXTI_Line22 ((uint32_t)0x00400000) /*!< Internal interrupt line 22\r
+ Connected to the Comparator 2\r
+ event */\r
+#define EXTI_Line23 ((uint32_t)0x00800000) /*!< Internal interrupt line 23\r
+ Connected to the I2C1 wakeup\r
+ event */\r
+#define EXTI_Line25 ((uint32_t)0x02000000) /*!< Internal interrupt line 25\r
+ Connected to the USART1 wakeup\r
+ event */\r
+#define EXTI_Line27 ((uint32_t)0x08000000) /*!< Internal interrupt line 27\r
+ Connected to the CEC wakeup\r
+ event */\r
+\r
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xF5140000) == 0x00) && ((LINE) != (uint16_t)0x00))\r
+\r
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \\r
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \\r
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \\r
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \\r
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \\r
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \\r
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \\r
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \\r
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \\r
+ ((LINE) == EXTI_Line19) || ((LINE) == EXTI_Line21) || \\r
+ ((LINE) == EXTI_Line22))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+/* Function used to set the EXTI configuration to the default reset state *****/\r
+void EXTI_DeInit(void);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearFlag(uint32_t EXTI_Line);\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F0XX_EXTI_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_flash.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the FLASH \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_FLASH_H\r
+#define __STM32F0XX_FLASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief FLASH Status\r
+ */ \r
+typedef enum\r
+{\r
+ FLASH_BUSY = 1,\r
+ FLASH_ERROR_WRP,\r
+ FLASH_ERROR_PROGRAM,\r
+ FLASH_COMPLETE,\r
+ FLASH_TIMEOUT\r
+}FLASH_Status;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+ \r
+/** @defgroup FLASH_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup FLASH_Latency \r
+ * @{\r
+ */ \r
+#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */\r
+#define FLASH_Latency_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */\r
+\r
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \\r
+ ((LATENCY) == FLASH_Latency_1))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Interrupts \r
+ * @{\r
+ */\r
+ \r
+#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */\r
+#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */\r
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Address \r
+ * @{\r
+ */\r
+ \r
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Option_Bytes_Write_Protection \r
+ * @{\r
+ */\r
+ \r
+\r
+#define OB_WRP_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */\r
+#define OB_WRP_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */\r
+#define OB_WRP_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */\r
+#define OB_WRP_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */\r
+#define OB_WRP_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */\r
+#define OB_WRP_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */\r
+#define OB_WRP_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */\r
+#define OB_WRP_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */\r
+#define OB_WRP_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */\r
+#define OB_WRP_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */\r
+#define OB_WRP_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */\r
+#define OB_WRP_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */\r
+#define OB_WRP_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */\r
+#define OB_WRP_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */\r
+#define OB_WRP_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */\r
+#define OB_WRP_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */\r
+\r
+#define OB_WRP_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */\r
+\r
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Option_Bytes_Read_Protection \r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief FLASH_Read Protection Level \r
+ */ \r
+#define OB_RDP_Level_0 ((uint8_t)0xAA)\r
+#define OB_RDP_Level_1 ((uint8_t)0xBB)\r
+/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 \r
+ it's no more possible to go back to level 1 or 0 */\r
+\r
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\\r
+ ((LEVEL) == OB_RDP_Level_1))/*||\\r
+ ((LEVEL) == OB_RDP_Level_2))*/\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Option_Bytes_IWatchdog \r
+ * @{\r
+ */\r
+\r
+#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */\r
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */\r
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Option_Bytes_nRST_STOP \r
+ * @{\r
+ */\r
+\r
+#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */\r
+#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */\r
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Option_Bytes_nRST_STDBY \r
+ * @{\r
+ */\r
+\r
+#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */\r
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */\r
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Option_Bytes_BOOT1\r
+ * @{\r
+ */\r
+\r
+#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */\r
+#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */\r
+#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Option_Bytes_VDDA_Analog_Monitoring\r
+ * @{\r
+ */\r
+\r
+#define OB_VDDA_ANALOG_ON ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source ON */\r
+#define OB_VDDA_ANALOG_OFF ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source OFF */\r
+\r
+#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup FLASH_Flags \r
+ * @{\r
+ */ \r
+\r
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */\r
+#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */\r
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */\r
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */\r
+ \r
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFC3) == 0x00000000) && ((FLAG) != 0x00000000))\r
+\r
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \\r
+ ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Keys \r
+ * @{\r
+ */ \r
+\r
+#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */\r
+#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key: used with FLASH_PEKEY1\r
+ to unlock the write access to the FPEC. */\r
+ \r
+#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */\r
+#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to\r
+ unlock the write access to the option byte block */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASH_Timeout_definition \r
+ * @{\r
+ */ \r
+#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+ \r
+/** \r
+ * @brief FLASH memory functions that can be executed from FLASH. \r
+ */ \r
+/* FLASH Interface configuration functions ************************************/\r
+void FLASH_SetLatency(uint32_t FLASH_Latency);\r
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);\r
+FlagStatus FLASH_GetPrefetchBufferStatus(void);\r
+\r
+/* FLASH Memory Programming functions *****************************************/\r
+void FLASH_Unlock(void);\r
+void FLASH_Lock(void);\r
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
+FLASH_Status FLASH_EraseAllPages(void);\r
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);\r
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
+\r
+/* FLASH Option Bytes Programming functions *****************************************/\r
+void FLASH_OB_Unlock(void);\r
+void FLASH_OB_Lock(void);\r
+void FLASH_OB_Launch(void);\r
+FLASH_Status FLASH_OB_Erase(void);\r
+FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);\r
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);\r
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);\r
+FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);\r
+FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);\r
+FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);\r
+uint8_t FLASH_OB_GetUser(void);\r
+uint32_t FLASH_OB_GetWRP(void);\r
+FlagStatus FLASH_OB_GetRDP(void);\r
+\r
+/* FLASH Interrupts and flags management functions **********************************/\r
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);\r
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);\r
+FLASH_Status FLASH_GetStatus(void);\r
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F0XX_FLASH_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_gpio.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the GPIO \r
+ * firmware library. \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_GPIO_H\r
+#define __STM32F0XX_GPIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO\r
+ * @{\r
+ */\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \\r
+ ((PERIPH) == GPIOB) || \\r
+ ((PERIPH) == GPIOC) || \\r
+ ((PERIPH) == GPIOD) || \\r
+ ((PERIPH) == GPIOF))\r
+\r
+#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \\r
+ ((PERIPH) == GPIOB))\r
+\r
+/** @defgroup Configuration_Mode_enumeration \r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */\r
+ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */\r
+ GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */\r
+ GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */\r
+}GPIOMode_TypeDef;\r
+\r
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \\r
+ ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Output_type_enumeration\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ GPIO_OType_PP = 0x00,\r
+ GPIO_OType_OD = 0x01\r
+}GPIOOType_TypeDef;\r
+\r
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Output_Maximum_frequency_enumeration \r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ GPIO_Speed_Level_1 = 0x01, /*!< Medium Speed */\r
+ GPIO_Speed_Level_2 = 0x02, /*!< Fast Speed */\r
+ GPIO_Speed_Level_3 = 0x03 /*!< High Speed */\r
+}GPIOSpeed_TypeDef;\r
+\r
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \\r
+ ((SPEED) == GPIO_Speed_Level_3))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration \r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ GPIO_PuPd_NOPULL = 0x00,\r
+ GPIO_PuPd_UP = 0x01,\r
+ GPIO_PuPd_DOWN = 0x02\r
+}GPIOPuPd_TypeDef;\r
+\r
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \\r
+ ((PUPD) == GPIO_PuPd_DOWN))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration\r
+ * @{\r
+ */\r
+typedef enum\r
+{ \r
+ Bit_RESET = 0,\r
+ Bit_SET\r
+}BitAction;\r
+\r
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief GPIO Init structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.\r
+ This parameter can be any value of @ref GPIO_pins_define */\r
+ \r
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref GPIOMode_TypeDef */\r
+\r
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.\r
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */\r
+\r
+ GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.\r
+ This parameter can be a value of @ref GPIOOType_TypeDef */\r
+\r
+ GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.\r
+ This parameter can be a value of @ref GPIOPuPd_TypeDef */\r
+}GPIO_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_pins_define \r
+ * @{\r
+ */\r
+#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */\r
+#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */\r
+#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */\r
+#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */\r
+#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */\r
+#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */\r
+#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */\r
+#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */\r
+#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */\r
+#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */\r
+#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */\r
+#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */\r
+#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */\r
+#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */\r
+#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */\r
+#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */\r
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */\r
+\r
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)\r
+\r
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \\r
+ ((PIN) == GPIO_Pin_1) || \\r
+ ((PIN) == GPIO_Pin_2) || \\r
+ ((PIN) == GPIO_Pin_3) || \\r
+ ((PIN) == GPIO_Pin_4) || \\r
+ ((PIN) == GPIO_Pin_5) || \\r
+ ((PIN) == GPIO_Pin_6) || \\r
+ ((PIN) == GPIO_Pin_7) || \\r
+ ((PIN) == GPIO_Pin_8) || \\r
+ ((PIN) == GPIO_Pin_9) || \\r
+ ((PIN) == GPIO_Pin_10) || \\r
+ ((PIN) == GPIO_Pin_11) || \\r
+ ((PIN) == GPIO_Pin_12) || \\r
+ ((PIN) == GPIO_Pin_13) || \\r
+ ((PIN) == GPIO_Pin_14) || \\r
+ ((PIN) == GPIO_Pin_15))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Pin_sources \r
+ * @{\r
+ */\r
+#define GPIO_PinSource0 ((uint8_t)0x00)\r
+#define GPIO_PinSource1 ((uint8_t)0x01)\r
+#define GPIO_PinSource2 ((uint8_t)0x02)\r
+#define GPIO_PinSource3 ((uint8_t)0x03)\r
+#define GPIO_PinSource4 ((uint8_t)0x04)\r
+#define GPIO_PinSource5 ((uint8_t)0x05)\r
+#define GPIO_PinSource6 ((uint8_t)0x06)\r
+#define GPIO_PinSource7 ((uint8_t)0x07)\r
+#define GPIO_PinSource8 ((uint8_t)0x08)\r
+#define GPIO_PinSource9 ((uint8_t)0x09)\r
+#define GPIO_PinSource10 ((uint8_t)0x0A)\r
+#define GPIO_PinSource11 ((uint8_t)0x0B)\r
+#define GPIO_PinSource12 ((uint8_t)0x0C)\r
+#define GPIO_PinSource13 ((uint8_t)0x0D)\r
+#define GPIO_PinSource14 ((uint8_t)0x0E)\r
+#define GPIO_PinSource15 ((uint8_t)0x0F)\r
+\r
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \\r
+ ((PINSOURCE) == GPIO_PinSource1) || \\r
+ ((PINSOURCE) == GPIO_PinSource2) || \\r
+ ((PINSOURCE) == GPIO_PinSource3) || \\r
+ ((PINSOURCE) == GPIO_PinSource4) || \\r
+ ((PINSOURCE) == GPIO_PinSource5) || \\r
+ ((PINSOURCE) == GPIO_PinSource6) || \\r
+ ((PINSOURCE) == GPIO_PinSource7) || \\r
+ ((PINSOURCE) == GPIO_PinSource8) || \\r
+ ((PINSOURCE) == GPIO_PinSource9) || \\r
+ ((PINSOURCE) == GPIO_PinSource10) || \\r
+ ((PINSOURCE) == GPIO_PinSource11) || \\r
+ ((PINSOURCE) == GPIO_PinSource12) || \\r
+ ((PINSOURCE) == GPIO_PinSource13) || \\r
+ ((PINSOURCE) == GPIO_PinSource14) || \\r
+ ((PINSOURCE) == GPIO_PinSource15))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Alternate_function_selection_define \r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief AF 0 selection\r
+ */\r
+#define GPIO_AF_0 ((uint8_t)0x00) /* WKUP, EVENTOUT, TIM15, SPI1, TIM17,\r
+ MCO, SWDAT, SWCLK, TIM14, BOOT,\r
+ USART1, CEC, IR_OUT, SPI2 */\r
+/** \r
+ * @brief AF 1 selection\r
+ */\r
+#define GPIO_AF_1 ((uint8_t)0x01) /* USART2, CEC, Tim3, USART1, USART2,\r
+ EVENTOUT, I2C1, I2C2, TIM15 */\r
+/** \r
+ * @brief AF 2 selection\r
+ */\r
+#define GPIO_AF_2 ((uint8_t)0x02) /* TIM2, TIM1, EVENTOUT, TIM16, TIM17 */\r
+/** \r
+ * @brief AF 3 selection\r
+ */\r
+#define GPIO_AF_3 ((uint8_t)0x03) /* TS, I2C1, TIM15, EVENTOUT */\r
+\r
+/** \r
+ * @brief AF 4 selection\r
+ */\r
+#define GPIO_AF_4 ((uint8_t)0x04) /* TIM14 */\r
+/** \r
+ * @brief AF 5 selection\r
+ */\r
+#define GPIO_AF_5 ((uint8_t)0x05) /* TIM16, TIM17 */\r
+\r
+/** \r
+ * @brief AF 6 selection\r
+ */\r
+#define GPIO_AF_6 ((uint8_t)0x06) /* EVENTOUT */\r
+/** \r
+ * @brief AF 7 selection\r
+ */\r
+#define GPIO_AF_7 ((uint8_t)0x07) /* COMP1 OUT and COMP2 OUT */\r
+\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \\r
+ ((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \\r
+ ((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \\r
+ ((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Speed_Legacy \r
+ * @{\r
+ */\r
+\r
+#define GPIO_Speed_10MHz GPIO_Speed_Level_1 /*!< Fast Speed:10MHz */\r
+#define GPIO_Speed_2MHz GPIO_Speed_Level_2 /*!< Medium Speed:2MHz */\r
+#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< High Speed:50MHz */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+/* Function used to set the GPIO configuration to the default reset state *****/\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+\r
+/* GPIO Read and Write functions **********************************************/\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);\r
+\r
+/* GPIO Alternate functions configuration functions ***************************/\r
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F0XX_GPIO_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_i2c.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the I2C firmware\r
+ * library\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_I2C_H\r
+#define __STM32F0XX_I2C_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2C\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief I2C Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value.\r
+ This parameter must be set by referring to I2C_Timing_Config_Tool*/\r
+\r
+ uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter.\r
+ This parameter can be a value of @ref I2C_Analog_Filter*/\r
+\r
+ uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter.\r
+ This parameter can be a number between 0x00 and 0x0F*/\r
+\r
+ uint32_t I2C_Mode; /*!< Specifies the I2C mode.\r
+ This parameter can be a value of @ref I2C_mode*/\r
+\r
+ uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1.\r
+ This parameter can be a 7-bit or 10-bit address*/\r
+\r
+ uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement.\r
+ This parameter can be a value of @ref I2C_acknowledgement*/\r
+\r
+ uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.\r
+ This parameter can be a value of @ref I2C_acknowledged_address*/\r
+}I2C_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+\r
+/** @defgroup I2C_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \\r
+ ((PERIPH) == I2C2))\r
+ \r
+#define IS_I2C_1_PERIPH(PERIPH) ((PERIPH) == I2C1) \r
+\r
+/** @defgroup I2C_Analog_Filter \r
+ * @{\r
+ */\r
+\r
+#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000)\r
+#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF\r
+\r
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \\r
+ ((FILTER) == I2C_AnalogFilter_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Digital_Filter\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_mode \r
+ * @{\r
+ */\r
+\r
+#define I2C_Mode_I2C ((uint32_t)0x00000000)\r
+#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN\r
+#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN\r
+\r
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \\r
+ ((MODE) == I2C_Mode_SMBusDevice) || \\r
+ ((MODE) == I2C_Mode_SMBusHost))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_acknowledgement\r
+ * @{\r
+ */\r
+\r
+#define I2C_Ack_Enable ((uint32_t)0x00000000)\r
+#define I2C_Ack_Disable I2C_CR2_NACK\r
+\r
+#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \\r
+ ((ACK) == I2C_Ack_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_acknowledged_address\r
+ * @{\r
+ */\r
+\r
+#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000)\r
+#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE\r
+\r
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \\r
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_own_address1\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_transfer_direction \r
+ * @{\r
+ */\r
+\r
+#define I2C_Direction_Transmitter ((uint16_t)0x0000)\r
+#define I2C_Direction_Receiver ((uint16_t)0x0400)\r
+\r
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \\r
+ ((DIRECTION) == I2C_Direction_Receiver))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_DMA_transfer_requests \r
+ * @{\r
+ */\r
+\r
+#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN\r
+#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN\r
+\r
+#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_slave_address\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup I2C_own_address2\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_own_address2_mask\r
+ * @{\r
+ */\r
+\r
+#define I2C_OA2_NoMask ((uint8_t)0x00)\r
+#define I2C_OA2_Mask01 ((uint8_t)0x01) \r
+#define I2C_OA2_Mask02 ((uint8_t)0x02)\r
+#define I2C_OA2_Mask03 ((uint8_t)0x03)\r
+#define I2C_OA2_Mask04 ((uint8_t)0x04)\r
+#define I2C_OA2_Mask05 ((uint8_t)0x05)\r
+#define I2C_OA2_Mask06 ((uint8_t)0x06)\r
+#define I2C_OA2_Mask07 ((uint8_t)0x07)\r
+\r
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \\r
+ ((MASK) == I2C_OA2_Mask01) || \\r
+ ((MASK) == I2C_OA2_Mask02) || \\r
+ ((MASK) == I2C_OA2_Mask03) || \\r
+ ((MASK) == I2C_OA2_Mask04) || \\r
+ ((MASK) == I2C_OA2_Mask05) || \\r
+ ((MASK) == I2C_OA2_Mask06) || \\r
+ ((MASK) == I2C_OA2_Mask07)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_timeout\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_registers \r
+ * @{\r
+ */\r
+\r
+#define I2C_Register_CR1 ((uint8_t)0x00)\r
+#define I2C_Register_CR2 ((uint8_t)0x04)\r
+#define I2C_Register_OAR1 ((uint8_t)0x08)\r
+#define I2C_Register_OAR2 ((uint8_t)0x0C)\r
+#define I2C_Register_TIMINGR ((uint8_t)0x10)\r
+#define I2C_Register_TIMEOUTR ((uint8_t)0x14)\r
+#define I2C_Register_ISR ((uint8_t)0x18)\r
+#define I2C_Register_ICR ((uint8_t)0x1C)\r
+#define I2C_Register_PECR ((uint8_t)0x20)\r
+#define I2C_Register_RXDR ((uint8_t)0x24)\r
+#define I2C_Register_TXDR ((uint8_t)0x28)\r
+\r
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \\r
+ ((REGISTER) == I2C_Register_CR2) || \\r
+ ((REGISTER) == I2C_Register_OAR1) || \\r
+ ((REGISTER) == I2C_Register_OAR2) || \\r
+ ((REGISTER) == I2C_Register_TIMINGR) || \\r
+ ((REGISTER) == I2C_Register_TIMEOUTR) || \\r
+ ((REGISTER) == I2C_Register_ISR) || \\r
+ ((REGISTER) == I2C_Register_ICR) || \\r
+ ((REGISTER) == I2C_Register_PECR) || \\r
+ ((REGISTER) == I2C_Register_RXDR) || \\r
+ ((REGISTER) == I2C_Register_TXDR))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_IT_ERRI I2C_CR1_ERRIE\r
+#define I2C_IT_TCI I2C_CR1_TCIE\r
+#define I2C_IT_STOPI I2C_CR1_STOPIE\r
+#define I2C_IT_NACKI I2C_CR1_NACKIE\r
+#define I2C_IT_ADDRI I2C_CR1_ADDRIE\r
+#define I2C_IT_RXI I2C_CR1_RXIE\r
+#define I2C_IT_TXI I2C_CR1_TXIE\r
+\r
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_flags_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_FLAG_TXE I2C_ISR_TXE\r
+#define I2C_FLAG_TXIS I2C_ISR_TXIS\r
+#define I2C_FLAG_RXNE I2C_ISR_RXNE\r
+#define I2C_FLAG_ADDR I2C_ISR_ADDR\r
+#define I2C_FLAG_NACKF I2C_ISR_NACKF\r
+#define I2C_FLAG_STOPF I2C_ISR_STOPF\r
+#define I2C_FLAG_TC I2C_ISR_TC\r
+#define I2C_FLAG_TCR I2C_ISR_TCR\r
+#define I2C_FLAG_BERR I2C_ISR_BERR\r
+#define I2C_FLAG_ARLO I2C_ISR_ARLO\r
+#define I2C_FLAG_OVR I2C_ISR_OVR\r
+#define I2C_FLAG_PECERR I2C_ISR_PECERR\r
+#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT\r
+#define I2C_FLAG_ALERT I2C_ISR_ALERT\r
+#define I2C_FLAG_BUSY I2C_ISR_BUSY\r
+\r
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))\r
+\r
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \\r
+ ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \\r
+ ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \\r
+ ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \\r
+ ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \\r
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \\r
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \\r
+ ((FLAG) == I2C_FLAG_BUSY))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup I2C_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_IT_TXIS I2C_ISR_TXIS\r
+#define I2C_IT_RXNE I2C_ISR_RXNE\r
+#define I2C_IT_ADDR I2C_ISR_ADDR\r
+#define I2C_IT_NACKF I2C_ISR_NACKF\r
+#define I2C_IT_STOPF I2C_ISR_STOPF\r
+#define I2C_IT_TC I2C_ISR_TC\r
+#define I2C_IT_TCR I2C_ISR_TCR\r
+#define I2C_IT_BERR I2C_ISR_BERR\r
+#define I2C_IT_ARLO I2C_ISR_ARLO\r
+#define I2C_IT_OVR I2C_ISR_OVR\r
+#define I2C_IT_PECERR I2C_ISR_PECERR\r
+#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT\r
+#define I2C_IT_ALERT I2C_ISR_ALERT\r
+\r
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))\r
+ \r
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \\r
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \\r
+ ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \\r
+ ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \\r
+ ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \\r
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \\r
+ ((IT) == I2C_IT_ALERT))\r
+ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_ReloadEndMode_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_Reload_Mode I2C_CR2_RELOAD\r
+#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND\r
+#define I2C_SoftEnd_Mode ((uint32_t)0x00000000)\r
+\r
+ \r
+#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \\r
+ ((MODE) == I2C_AutoEnd_Mode) || \\r
+ ((MODE) == I2C_SoftEnd_Mode))\r
+ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_StartStopMode_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_Generate_Stop I2C_CR2_STOP\r
+#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)\r
+#define I2C_Generate_Start_Write I2C_CR2_START\r
+\r
+ \r
+#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \\r
+ ((MODE) == I2C_Generate_Start_Read) || \\r
+ ((MODE) == I2C_Generate_Start_Write))\r
+ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void I2C_DeInit(I2C_TypeDef* I2Cx);\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);\r
+void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+\r
+/* Communications handling functions ******************************************/\r
+void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint16_t Number_Bytes);\r
+void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);\r
+uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);\r
+void I2C_TCRTransferHandling(I2C_TypeDef* I2Cx, uint16_t Number_Bytes, uint32_t ReloadEndMode);\r
+void I2C_TCTransferHandling(I2C_TypeDef* I2Cx, uint16_t Number_Bytes, uint32_t StartStopMode);\r
+\r
+/* SMBUS management functions ************************************************/\r
+void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);\r
+void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);\r
+\r
+/* I2C registers management functions *****************************************/\r
+uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);\r
+\r
+/* Data transfers management functions ****************************************/\r
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);\r
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F0XX_I2C_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_iwdg.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the IWDG \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_IWDG_H\r
+#define __STM32F0XX_IWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup IWDG\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup IWDG_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG_WriteAccess\r
+ * @{\r
+ */\r
+\r
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)\r
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)\r
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \\r
+ ((ACCESS) == IWDG_WriteAccess_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_prescaler \r
+ * @{\r
+ */\r
+\r
+#define IWDG_Prescaler_4 ((uint8_t)0x00)\r
+#define IWDG_Prescaler_8 ((uint8_t)0x01)\r
+#define IWDG_Prescaler_16 ((uint8_t)0x02)\r
+#define IWDG_Prescaler_32 ((uint8_t)0x03)\r
+#define IWDG_Prescaler_64 ((uint8_t)0x04)\r
+#define IWDG_Prescaler_128 ((uint8_t)0x05)\r
+#define IWDG_Prescaler_256 ((uint8_t)0x06)\r
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \\r
+ ((PRESCALER) == IWDG_Prescaler_8) || \\r
+ ((PRESCALER) == IWDG_Prescaler_16) || \\r
+ ((PRESCALER) == IWDG_Prescaler_32) || \\r
+ ((PRESCALER) == IWDG_Prescaler_64) || \\r
+ ((PRESCALER) == IWDG_Prescaler_128)|| \\r
+ ((PRESCALER) == IWDG_Prescaler_256))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Flag \r
+ * @{\r
+ */\r
+\r
+#define IWDG_FLAG_PVU IWDG_SR_PVU\r
+#define IWDG_FLAG_RVU IWDG_SR_RVU\r
+#define IWDG_FLAG_WVU IWDG_SR_WVU\r
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \\r
+ ((FLAG) == IWDG_FLAG_WVU))\r
+\r
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)\r
+\r
+#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Prescaler and Counter configuration functions ******************************/\r
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);\r
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);\r
+void IWDG_SetReload(uint16_t Reload);\r
+void IWDG_ReloadCounter(void);\r
+void IWDG_SetWindowValue(uint16_t WindowValue);\r
+\r
+/* IWDG activation function ***************************************************/\r
+void IWDG_Enable(void);\r
+\r
+/* Flag management function ***************************************************/\r
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F0XX_IWDG_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_misc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the miscellaneous\r
+ * firmware library functions (add-on to CMSIS functions).\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_MISC_H\r
+#define __STM32F0XX_MISC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup MISC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief NVIC Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.\r
+ This parameter can be a value of @ref IRQn_Type \r
+ (For the complete STM32 Devices IRQ Channels list, \r
+ please refer to stm32f0xx.h file) */\r
+\r
+ uint8_t NVIC_IRQChannelPriority; /*!< Specifies the priority level for the IRQ channel specified\r
+ in NVIC_IRQChannel. This parameter can be a value\r
+ between 0 and 3. */\r
+\r
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel\r
+ will be enabled or disabled. \r
+ This parameter can be set either to ENABLE or DISABLE */ \r
+} NVIC_InitTypeDef;\r
+\r
+/** \r
+ *\r
+@verbatim \r
+\r
+@endverbatim\r
+*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup MISC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup System_Low_Power \r
+ * @{\r
+ */\r
+\r
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)\r
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)\r
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)\r
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\r
+ ((LP) == NVIC_LP_SLEEPDEEP) || \\r
+ ((LP) == NVIC_LP_SLEEPONEXIT))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Preemption_Priority_Group \r
+ * @{\r
+ */\r
+#define IS_NVIC_PRIORITY(PRIORITY) ((PRIORITY) < 0x04)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SysTick_clock_source \r
+ * @{\r
+ */\r
+\r
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)\r
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\r
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F0XX_MISC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_pwr.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the PWR firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_PWR_H\r
+#define __STM32F0XX_PWR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWR\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup PWR_PVD_detection_level \r
+ * @{\r
+ */ \r
+\r
+#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0\r
+#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1\r
+#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2\r
+#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3\r
+#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4\r
+#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5\r
+#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6\r
+#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 \r
+\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \\r
+ ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \\r
+ ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \\r
+ ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_WakeUp_Pins \r
+ * @{\r
+ */\r
+\r
+#define PWR_WakeUpPin_1 PWR_CSR_EWUP1\r
+#define PWR_WakeUpPin_2 PWR_CSR_EWUP2\r
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \\r
+ ((PIN) == PWR_WakeUpPin_2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode \r
+ * @{\r
+ */\r
+\r
+#define PWR_Regulator_ON ((uint32_t)0x00000000)\r
+#define PWR_Regulator_LowPower PWR_CR_LPSDSR\r
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \\r
+ ((REGULATOR) == PWR_Regulator_LowPower))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_SLEEP_mode_entry \r
+ * @{\r
+ */\r
+\r
+#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)\r
+#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)\r
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_STOP_mode_entry \r
+ * @{\r
+ */\r
+\r
+#define PWR_STOPEntry_WFI ((uint8_t)0x01)\r
+#define PWR_STOPEntry_WFE ((uint8_t)0x02)\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Flag \r
+ * @{\r
+ */\r
+\r
+#define PWR_FLAG_WU PWR_CSR_WUF\r
+#define PWR_FLAG_SB PWR_CSR_SBF\r
+#define PWR_FLAG_PVDO PWR_CSR_PVDO\r
+#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF\r
+\r
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \\r
+ ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))\r
+\r
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the PWR configuration to the default reset state ******/\r
+void PWR_DeInit(void);\r
+\r
+/* Backup Domain Access function **********************************************/\r
+void PWR_BackupAccessCmd(FunctionalState NewState);\r
+\r
+/* PVD configuration functions ************************************************/\r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);\r
+void PWR_PVDCmd(FunctionalState NewState);\r
+\r
+/* WakeUp pins configuration functions ****************************************/\r
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);\r
+\r
+/* Low Power modes configuration functions ************************************/\r
+void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);\r
+void PWR_EnterSTANDBYMode(void);\r
+\r
+/* Flags management functions *************************************************/\r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);\r
+void PWR_ClearFlag(uint32_t PWR_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F0XX_PWR_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_rcc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the RCC \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_RCC_H\r
+#define __STM32F0XX_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+typedef struct\r
+{\r
+ uint32_t SYSCLK_Frequency;\r
+ uint32_t HCLK_Frequency;\r
+ uint32_t PCLK_Frequency;\r
+ uint32_t ADCCLK_Frequency;\r
+ uint32_t CECCLK_Frequency;\r
+ uint32_t I2C1CLK_Frequency;\r
+ uint32_t USART1CLK_Frequency;\r
+}RCC_ClocksTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_HSE_configuration \r
+ * @{\r
+ */\r
+\r
+#define RCC_HSE_OFF ((uint8_t)0x00)\r
+#define RCC_HSE_ON ((uint8_t)0x01)\r
+#define RCC_HSE_Bypass ((uint8_t)0x05)\r
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
+ ((HSE) == RCC_HSE_Bypass))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_PLL_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2\r
+#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1\r
+ \r
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \\r
+ ((SOURCE) == RCC_PLLSource_PREDIV1))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_PLL_Multiplication_Factor \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2\r
+#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3\r
+#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4\r
+#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5\r
+#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6\r
+#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7\r
+#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8\r
+#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9\r
+#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10\r
+#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11\r
+#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12\r
+#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13\r
+#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14\r
+#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15\r
+#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16\r
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \\r
+ ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \\r
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \\r
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \\r
+ ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \\r
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \\r
+ ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \\r
+ ((MUL) == RCC_PLLMul_16))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PREDIV1_division_factor\r
+ * @{\r
+ */\r
+#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1\r
+#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2\r
+#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3\r
+#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4\r
+#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5\r
+#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6\r
+#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7\r
+#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8\r
+#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9\r
+#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10\r
+#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11\r
+#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12\r
+#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13\r
+#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14\r
+#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15\r
+#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16\r
+\r
+#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_System_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI\r
+#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE\r
+#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL\r
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_AHB_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1\r
+#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2\r
+#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4\r
+#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8\r
+#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16\r
+#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64\r
+#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128\r
+#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256\r
+#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512\r
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \\r
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \\r
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \\r
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \\r
+ ((HCLK) == RCC_SYSCLK_Div512))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_APB_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1\r
+#define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2\r
+#define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4\r
+#define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8\r
+#define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16\r
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \\r
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \\r
+ ((PCLK) == RCC_HCLK_Div16))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_ADC_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_ADCCLK_HSI14 ((uint32_t)0x00000000)\r
+#define RCC_ADCCLK_PCLK_Div2 ((uint32_t)0x01000000)\r
+#define RCC_ADCCLK_PCLK_Div4 ((uint32_t)0x01004000)\r
+\r
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \\r
+ ((ADCCLK) == RCC_ADCCLK_PCLK_Div4))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_CEC_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_CECCLK_HSI_Div244 ((uint32_t)0x00000000)\r
+#define RCC_CECCLK_LSE RCC_CFGR3_CECSW\r
+\r
+#define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_I2C_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)\r
+#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW\r
+\r
+#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_USART_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_USART1CLK_PCLK ((uint32_t)0x00000000)\r
+#define RCC_USART1CLK_SYSCLK RCC_CFGR3_USART1SW_0\r
+#define RCC_USART1CLK_LSE RCC_CFGR3_USART1SW_1\r
+#define RCC_USART1CLK_HSI RCC_CFGR3_USART1SW\r
+\r
+#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \\r
+ ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_Interrupt_Source \r
+ * @{\r
+ */\r
+\r
+#define RCC_IT_LSIRDY ((uint8_t)0x01)\r
+#define RCC_IT_LSERDY ((uint8_t)0x02)\r
+#define RCC_IT_HSIRDY ((uint8_t)0x04)\r
+#define RCC_IT_HSERDY ((uint8_t)0x08)\r
+#define RCC_IT_PLLRDY ((uint8_t)0x10)\r
+#define RCC_IT_HSI14RDY ((uint8_t)0x20)\r
+#define RCC_IT_CSS ((uint8_t)0x80)\r
+\r
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \\r
+ ((IT) == RCC_IT_CSS))\r
+\r
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_LSE_Configuration \r
+ * @{\r
+ */\r
+\r
+#define RCC_LSE_OFF ((uint32_t)0x00000000)\r
+#define RCC_LSE_ON RCC_BDCR_LSEON\r
+#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))\r
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
+ ((LSE) == RCC_LSE_Bypass))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_RTC_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE\r
+#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI\r
+#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE\r
+\r
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSE_Drive_Configuration \r
+ * @{\r
+ */\r
+\r
+#define RCC_LSEDrive_Low ((uint32_t)0x00000000)\r
+#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0\r
+#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1\r
+#define RCC_LSEDrive_High RCC_BDCR_LSEDRV\r
+#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \\r
+ ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_AHB_Peripherals \r
+ * @{\r
+ */\r
+\r
+#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN\r
+#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN\r
+#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN\r
+#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN\r
+#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN\r
+#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN\r
+#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN\r
+#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN\r
+#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN\r
+#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN\r
+\r
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEA1FFAA) == 0x00) && ((PERIPH) != 0x00))\r
+#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFEA1FFFF) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Peripherals \r
+ * @{\r
+ */\r
+\r
+#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN\r
+#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN\r
+#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN\r
+#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN\r
+#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN\r
+#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN\r
+#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN\r
+#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN\r
+#define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCUEN\r
+\r
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A5FE) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_APB1_Peripherals \r
+ * @{\r
+ */\r
+\r
+#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN\r
+#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN\r
+#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN\r
+#define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN\r
+#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN\r
+#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN\r
+#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN\r
+#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN\r
+#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN\r
+#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN\r
+#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN\r
+#define RCC_APB1Periph_CEC RCC_APB1ENR_CECEN\r
+\r
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8F9DB6EC) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCO_Clock_Source\r
+ * @{\r
+ */\r
+\r
+#define RCC_MCOSource_NoClock ((uint8_t)0x00)\r
+#define RCC_MCOSource_HSI14 ((uint8_t)0x03)\r
+#define RCC_MCOSource_SYSCLK ((uint8_t)0x04)\r
+#define RCC_MCOSource_HSI ((uint8_t)0x05)\r
+#define RCC_MCOSource_HSE ((uint8_t)0x06)\r
+#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)\r
+\r
+#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \\r
+ ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \\r
+ ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_Flag \r
+ * @{\r
+ */\r
+#define RCC_FLAG_HSIRDY ((uint8_t)0x01)\r
+#define RCC_FLAG_HSERDY ((uint8_t)0x11)\r
+#define RCC_FLAG_PLLRDY ((uint8_t)0x19)\r
+#define RCC_FLAG_LSERDY ((uint8_t)0x21)\r
+#define RCC_FLAG_LSIRDY ((uint8_t)0x41)\r
+#define RCC_FLAG_OBLRST ((uint8_t)0x59)\r
+#define RCC_FLAG_PINRST ((uint8_t)0x5A)\r
+#define RCC_FLAG_PORRST ((uint8_t)0x5B)\r
+#define RCC_FLAG_SFTRST ((uint8_t)0x5C)\r
+#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)\r
+#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)\r
+#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)\r
+#define RCC_FLAG_HSI14RDY ((uint8_t)0x61)\r
+\r
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \\r
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \\r
+ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \\r
+ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \\r
+ ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \\r
+ ((FLAG) == RCC_FLAG_HSI14RDY))\r
+\r
+#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
+#define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the RCC clock configuration to the default reset state */\r
+void RCC_DeInit(void);\r
+\r
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/\r
+void RCC_HSEConfig(uint8_t RCC_HSE);\r
+ErrorStatus RCC_WaitForHSEStartUp(void);\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);\r
+void RCC_HSICmd(FunctionalState NewState);\r
+void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue);\r
+void RCC_HSI14Cmd(FunctionalState NewState);\r
+void RCC_HSI14ADCRequestCmd(FunctionalState NewState);\r
+void RCC_LSEConfig(uint32_t RCC_LSE);\r
+void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);\r
+void RCC_LSICmd(FunctionalState NewState);\r
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);\r
+void RCC_PLLCmd(FunctionalState NewState);\r
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);\r
+void RCC_MCOConfig(uint8_t RCC_MCOSource);\r
+\r
+/* System, AHB and APB busses clocks configuration functions ******************/\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);\r
+uint8_t RCC_GetSYSCLKSource(void);\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);\r
+void RCC_PCLKConfig(uint32_t RCC_HCLK);\r
+void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK);\r
+void RCC_CECCLKConfig(uint32_t RCC_CECCLK);\r
+void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);\r
+void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);\r
+\r
+/* Peripheral clocks configuration functions **********************************/\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);\r
+void RCC_RTCCLKCmd(FunctionalState NewState);\r
+void RCC_BackupResetCmd(FunctionalState NewState);\r
+\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);\r
+void RCC_ClearFlag(void);\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F0XX_RCC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_rtc.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the RTC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_RTC_H\r
+#define __STM32F0XX_RTC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RTC\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief RTC Init structures definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.\r
+ This parameter can be a value of @ref RTC_Hour_Formats */\r
+ \r
+ uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.\r
+ This parameter must be set to a value lower than 0x7F */\r
+ \r
+ uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.\r
+ This parameter must be set to a value lower than 0x1FFF */\r
+}RTC_InitTypeDef;\r
+\r
+/** \r
+ * @brief RTC Time structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.\r
+ This parameter must be set to a value in the 0-12 range\r
+ if the RTC_HourFormat_12 is selected or 0-23 range if\r
+ the RTC_HourFormat_24 is selected. */\r
+\r
+ uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.\r
+ This parameter must be set to a value in the 0-59 range. */\r
+ \r
+ uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.\r
+ This parameter must be set to a value in the 0-59 range. */\r
+\r
+ uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.\r
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */\r
+}RTC_TimeTypeDef; \r
+\r
+/** \r
+ * @brief RTC Date structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.\r
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */\r
+ \r
+ uint8_t RTC_Month; /*!< Specifies the RTC Date Month.\r
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */\r
+\r
+ uint8_t RTC_Date; /*!< Specifies the RTC Date.\r
+ This parameter must be set to a value in the 1-31 range. */\r
+ \r
+ uint8_t RTC_Year; /*!< Specifies the RTC Date Year.\r
+ This parameter must be set to a value in the 0-99 range. */\r
+}RTC_DateTypeDef;\r
+\r
+/** \r
+ * @brief RTC Alarm structure definition \r
+ */\r
+typedef struct\r
+{\r
+ RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */\r
+\r
+ uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.\r
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */\r
+\r
+ uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.\r
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */\r
+ \r
+ uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.\r
+ This parameter must be set to a value in the 1-31 range \r
+ if the Alarm Date is selected.\r
+ This parameter can be a value of @ref RTC_WeekDay_Definitions \r
+ if the Alarm WeekDay is selected. */\r
+}RTC_AlarmTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup RTC_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Hour_Formats \r
+ * @{\r
+ */ \r
+#define RTC_HourFormat_24 ((uint32_t)0x00000000)\r
+#define RTC_HourFormat_12 ((uint32_t)0x00000040)\r
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \\r
+ ((FORMAT) == RTC_HourFormat_24))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Asynchronous_Predivider \r
+ * @{\r
+ */ \r
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Synchronous_Predivider \r
+ * @{\r
+ */ \r
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Time_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))\r
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)\r
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)\r
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_AM_PM_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_H12_AM ((uint8_t)0x00)\r
+#define RTC_H12_PM ((uint8_t)0x40)\r
+#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Year_Date_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Month_Date_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Month_January ((uint8_t)0x01)\r
+#define RTC_Month_February ((uint8_t)0x02)\r
+#define RTC_Month_March ((uint8_t)0x03)\r
+#define RTC_Month_April ((uint8_t)0x04)\r
+#define RTC_Month_May ((uint8_t)0x05)\r
+#define RTC_Month_June ((uint8_t)0x06)\r
+#define RTC_Month_July ((uint8_t)0x07)\r
+#define RTC_Month_August ((uint8_t)0x08)\r
+#define RTC_Month_September ((uint8_t)0x09)\r
+#define RTC_Month_October ((uint8_t)0x10)\r
+#define RTC_Month_November ((uint8_t)0x11)\r
+#define RTC_Month_December ((uint8_t)0x12)\r
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))\r
+#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_WeekDay_Definitions \r
+ * @{\r
+ */ \r
+ \r
+#define RTC_Weekday_Monday ((uint8_t)0x01)\r
+#define RTC_Weekday_Tuesday ((uint8_t)0x02)\r
+#define RTC_Weekday_Wednesday ((uint8_t)0x03)\r
+#define RTC_Weekday_Thursday ((uint8_t)0x04)\r
+#define RTC_Weekday_Friday ((uint8_t)0x05)\r
+#define RTC_Weekday_Saturday ((uint8_t)0x6)\r
+#define RTC_Weekday_Sunday ((uint8_t)0x07)\r
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Friday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Sunday))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Alarm_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))\r
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Tuesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Wednesday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Thursday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Friday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Saturday) || \\r
+ ((WEEKDAY) == RTC_Weekday_Sunday))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_AlarmDateWeekDay_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) \r
+#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) \r
+\r
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \\r
+ ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_AlarmMask_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_AlarmMask_None ((uint32_t)0x00000000)\r
+#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) \r
+#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)\r
+#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)\r
+#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)\r
+#define RTC_AlarmMask_All ((uint32_t)0x80808080)\r
+#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Alarms_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Alarm_A ((uint32_t)0x00000100)\r
+#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_Alarm_A)\r
+#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A)) != (uint32_t)RESET)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks Definitions.\r
+ * @{\r
+ */ \r
+#define RTC_AlarmSubSecondMask_All ((uint8_t)0x00) /*!< All Alarm SS fields are masked. \r
+ There is no comparison on sub seconds \r
+ for Alarm */\r
+#define RTC_AlarmSubSecondMask_SS14_1 ((uint8_t)0x01) /*!< SS[14:1] are don't care in Alarm \r
+ comparison. Only SS[0] is compared. */\r
+#define RTC_AlarmSubSecondMask_SS14_2 ((uint8_t)0x02) /*!< SS[14:2] are don't care in Alarm \r
+ comparison. Only SS[1:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_3 ((uint8_t)0x03) /*!< SS[14:3] are don't care in Alarm \r
+ comparison. Only SS[2:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_4 ((uint8_t)0x04) /*!< SS[14:4] are don't care in Alarm \r
+ comparison. Only SS[3:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_5 ((uint8_t)0x05) /*!< SS[14:5] are don't care in Alarm \r
+ comparison. Only SS[4:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_6 ((uint8_t)0x06) /*!< SS[14:6] are don't care in Alarm \r
+ comparison. Only SS[5:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_7 ((uint8_t)0x07) /*!< SS[14:7] are don't care in Alarm \r
+ comparison. Only SS[6:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_8 ((uint8_t)0x08) /*!< SS[14:8] are don't care in Alarm \r
+ comparison. Only SS[7:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_9 ((uint8_t)0x09) /*!< SS[14:9] are don't care in Alarm \r
+ comparison. Only SS[8:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_10 ((uint8_t)0x0A) /*!< SS[14:10] are don't care in Alarm \r
+ comparison. Only SS[9:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_11 ((uint8_t)0x0B) /*!< SS[14:11] are don't care in Alarm \r
+ comparison. Only SS[10:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_12 ((uint8_t)0x0C) /*!< SS[14:12] are don't care in Alarm \r
+ comparison.Only SS[11:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14_13 ((uint8_t)0x0D) /*!< SS[14:13] are don't care in Alarm \r
+ comparison. Only SS[12:0] are compared */\r
+#define RTC_AlarmSubSecondMask_SS14 ((uint8_t)0x0E) /*!< SS[14] is don't care in Alarm \r
+ comparison.Only SS[13:0] are compared */\r
+#define RTC_AlarmSubSecondMask_None ((uint8_t)0x0F) /*!< SS[14:0] are compared and must match \r
+ to activate alarm. */\r
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_SS14) || \\r
+ ((MASK) == RTC_AlarmSubSecondMask_None))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Alarm_Sub_Seconds_Value\r
+ * @{\r
+ */ \r
+ \r
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Time_Stamp_Edges_definitions \r
+ * @{\r
+ */ \r
+#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)\r
+#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)\r
+#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \\r
+ ((EDGE) == RTC_TimeStampEdge_Falling))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Output_selection_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Output_Disable ((uint32_t)0x00000000)\r
+#define RTC_Output_AlarmA ((uint32_t)0x00200000)\r
+ \r
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \\r
+ ((OUTPUT) == RTC_Output_AlarmA))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Output_Polarity_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_OutputPolarity_High ((uint32_t)0x00000000)\r
+#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)\r
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \\r
+ ((POL) == RTC_OutputPolarity_Low))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup RTC_Calib_Output_selection_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) \r
+#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)\r
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \\r
+ ((OUTPUT) == RTC_CalibOutput_1Hz))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Smooth_calib_period_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation\r
+ period is 32s, else 2exp20 RTCCLK seconds */\r
+#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \r
+ period is 16s, else 2exp19 RTCCLK seconds */\r
+#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \r
+ period is 8s, else 2exp18 RTCCLK seconds */\r
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \\r
+ ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \\r
+ ((PERIOD) == RTC_SmoothCalibPeriod_8sec))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added \r
+ during a X -second window = Y - CALM[8:0]. \r
+ with Y = 512, 256, 128 when X = 32, 16, 8 */\r
+#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited\r
+ during a 32-second window = CALM[8:0]. */\r
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \\r
+ ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions \r
+ * @{\r
+ */ \r
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_DayLightSaving_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)\r
+#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)\r
+#define IS_RTC_DAYLIGHT_SAVING(SAVING) (((SAVING) == RTC_DayLightSaving_SUB1H) || \\r
+ ((SAVING) == RTC_DayLightSaving_ADD1H))\r
+\r
+#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)\r
+#define RTC_StoreOperation_Set ((uint32_t)0x00040000)\r
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \\r
+ ((OPERATION) == RTC_StoreOperation_Set))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Tamper_Trigger_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)\r
+#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)\r
+#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)\r
+#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)\r
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \\r
+ ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \\r
+ ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \\r
+ ((TRIGGER) == RTC_TamperTrigger_HighLevel)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Tamper_Filter_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */\r
+\r
+#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 \r
+ consecutive samples at the active level */\r
+#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 \r
+ consecutive samples at the active level */\r
+#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 \r
+ consecutive samples at the active leve. */\r
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \\r
+ ((FILTER) == RTC_TamperFilter_2Sample) || \\r
+ ((FILTER) == RTC_TamperFilter_4Sample) || \\r
+ ((FILTER) == RTC_TamperFilter_8Sample))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 32768 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 16384 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 8192 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 4096 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 2048 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 1024 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 512 */\r
+#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled\r
+ with a frequency = RTCCLK / 256 */\r
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \\r
+ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before \r
+ sampling during 1 RTCCLK cycle */\r
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before \r
+ sampling during 2 RTCCLK cycles */\r
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before \r
+ sampling during 4 RTCCLK cycles */\r
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before \r
+ sampling during 8 RTCCLK cycles */\r
+\r
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \\r
+ ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \\r
+ ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \\r
+ ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Tamper_Pins_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for \r
+ input tamper 1 */\r
+#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for \r
+ input tamper 2 */\r
+#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for \r
+ input tamper 3 */\r
+\r
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Output_Type_ALARM_OUT \r
+ * @{\r
+ */ \r
+#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)\r
+#define RTC_OutputType_PushPull ((uint32_t)0x00040000)\r
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \\r
+ ((TYPE) == RTC_OutputType_PushPull))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Add_1_Second_Parameter_Definitions\r
+ * @{\r
+ */ \r
+#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)\r
+#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)\r
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \\r
+ ((SEL) == RTC_ShiftAdd1S_Set))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Substract_Fraction_Of_Second_Value\r
+ * @{\r
+ */ \r
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Backup_Registers_Definitions \r
+ * @{\r
+ */\r
+\r
+#define RTC_BKP_DR0 ((uint32_t)0x00000000)\r
+#define RTC_BKP_DR1 ((uint32_t)0x00000001)\r
+#define RTC_BKP_DR2 ((uint32_t)0x00000002)\r
+#define RTC_BKP_DR3 ((uint32_t)0x00000003)\r
+#define RTC_BKP_DR4 ((uint32_t)0x00000004)\r
+#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \\r
+ ((BKP) == RTC_BKP_DR1) || \\r
+ ((BKP) == RTC_BKP_DR2) || \\r
+ ((BKP) == RTC_BKP_DR3) || \\r
+ ((BKP) == RTC_BKP_DR4)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Input_parameter_format_definitions \r
+ * @{\r
+ */ \r
+#define RTC_Format_BIN ((uint32_t)0x000000000)\r
+#define RTC_Format_BCD ((uint32_t)0x000000001)\r
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Flags_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)\r
+#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)\r
+#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)\r
+#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)\r
+#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)\r
+#define RTC_FLAG_TSF ((uint32_t)0x00000800)\r
+#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)\r
+#define RTC_FLAG_INITF ((uint32_t)0x00000040)\r
+#define RTC_FLAG_RSF ((uint32_t)0x00000020)\r
+#define RTC_FLAG_INITS ((uint32_t)0x00000010)\r
+#define RTC_FLAG_SHPF ((uint32_t)0x00000008)\r
+\r
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RECALPF) || ((FLAG) == RTC_FLAG_TAMP3F) || \\r
+ ((FLAG) == RTC_FLAG_TAMP2F) || ((FLAG) == RTC_FLAG_TAMP1F) || \\r
+ ((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \\r
+ ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \\r
+ ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_INITS) || \\r
+ ((FLAG) == RTC_FLAG_SHPF))\r
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF06DF) == (uint32_t)RESET))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Interrupts_Definitions \r
+ * @{\r
+ */ \r
+#define RTC_IT_TS ((uint32_t)0x00008000)\r
+#define RTC_IT_ALRA ((uint32_t)0x00001000)\r
+#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */\r
+#define RTC_IT_TAMP1 ((uint32_t)0x00020000)\r
+#define RTC_IT_TAMP2 ((uint32_t)0x00040000)\r
+#define RTC_IT_TAMP3 ((uint32_t)0x00080000)\r
+\r
+#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF6FFB) == (uint32_t)RESET))\r
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_ALRA) || \\r
+ ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \\r
+ ((IT) == RTC_IT_TAMP3)) \r
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF16FFF) == (uint32_t)RESET))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+/* Function used to set the RTC configuration to the default reset state *****/\r
+ErrorStatus RTC_DeInit(void);\r
+\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);\r
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);\r
+void RTC_WriteProtectionCmd(FunctionalState NewState);\r
+ErrorStatus RTC_EnterInitMode(void);\r
+void RTC_ExitInitMode(void);\r
+ErrorStatus RTC_WaitForSynchro(void);\r
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState);\r
+void RTC_BypassShadowCmd(FunctionalState NewState);\r
+\r
+/* Time and Date configuration functions **************************************/\r
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);\r
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);\r
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);\r
+uint32_t RTC_GetSubSecond(void);\r
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);\r
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);\r
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);\r
+\r
+/* Alarms (Alarm A) configuration functions **********************************/\r
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);\r
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);\r
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);\r
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);\r
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask);\r
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);\r
+\r
+/* Daylight Saving configuration functions ************************************/\r
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);\r
+uint32_t RTC_GetStoreOperation(void);\r
+\r
+/* Output pin Configuration function ******************************************/\r
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);\r
+\r
+/* Digital Calibration configuration functions ********************************/\r
+void RTC_CalibOutputCmd(FunctionalState NewState);\r
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);\r
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, \r
+ uint32_t RTC_SmoothCalibPlusPulses,\r
+ uint32_t RTC_SmouthCalibMinusPulsesValue);\r
+\r
+/* TimeStamp configuration functions ******************************************/\r
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);\r
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct);\r
+uint32_t RTC_GetTimeStampSubSecond(void);\r
+\r
+/* Tampers configuration functions ********************************************/\r
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);\r
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);\r
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);\r
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);\r
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);\r
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);\r
+void RTC_TamperPullUpCmd(FunctionalState NewState);\r
+\r
+/* Backup Data Registers configuration functions ******************************/\r
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);\r
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);\r
+\r
+/* Output Type Config configuration functions *********************************/\r
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType);\r
+ \r
+/* RTC_Shift_control_synchonisation_functions *********************************/\r
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);\r
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);\r
+void RTC_ClearFlag(uint32_t RTC_FLAG);\r
+ITStatus RTC_GetITStatus(uint32_t RTC_IT);\r
+void RTC_ClearITPendingBit(uint32_t RTC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F0XX_RTC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_spi.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the SPI \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_SPI_H\r
+#define __STM32F0XX_SPI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SPI\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief SPI Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.\r
+ This parameter can be a value of @ref SPI_data_direction */\r
+\r
+ uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).\r
+ This parameter can be a value of @ref SPI_mode */\r
+ \r
+ uint16_t SPI_DataSize; /*!< Specifies the SPI data size.\r
+ This parameter can be a value of @ref SPI_data_size */\r
+\r
+ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.\r
+ This parameter can be a value of @ref SPI_Clock_Polarity */\r
+\r
+ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.\r
+ This parameter can be a value of @ref SPI_Clock_Phase */\r
+\r
+ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by\r
+ hardware (NSS pin) or by software using the SSI bit.\r
+ This parameter can be a value of @ref SPI_Slave_Select_management */\r
+ \r
+ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be\r
+ used to configure the transmit and receive SCK clock.\r
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler\r
+ @note The communication clock is derived from the master\r
+ clock. The slave clock does not need to be set. */\r
+\r
+ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.\r
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */\r
+\r
+ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */\r
+}SPI_InitTypeDef;\r
+\r
+\r
+/** \r
+ * @brief I2S Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.\r
+ This parameter can be a value of @ref SPI_I2S_Mode */\r
+\r
+ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.\r
+ This parameter can be a value of @ref SPI_I2S_Standard */\r
+\r
+ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.\r
+ This parameter can be a value of @ref SPI_I2S_Data_Format */\r
+\r
+ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.\r
+ This parameter can be a value of @ref SPI_I2S_MCLK_Output */\r
+\r
+ uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.\r
+ This parameter can be a value of @ref SPI_I2S_Audio_Frequency */\r
+\r
+ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.\r
+ This parameter can be a value of @ref SPI_I2S_Clock_Polarity */\r
+}I2S_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup SPI_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \\r
+ ((PERIPH) == SPI2))\r
+\r
+#define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1))\r
+\r
+/** @defgroup SPI_data_direction \r
+ * @{\r
+ */\r
+ \r
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)\r
+#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)\r
+#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)\r
+#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)\r
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \\r
+ ((MODE) == SPI_Direction_2Lines_RxOnly) || \\r
+ ((MODE) == SPI_Direction_1Line_Rx) || \\r
+ ((MODE) == SPI_Direction_1Line_Tx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_mode \r
+ * @{\r
+ */\r
+\r
+#define SPI_Mode_Master ((uint16_t)0x0104)\r
+#define SPI_Mode_Slave ((uint16_t)0x0000)\r
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \\r
+ ((MODE) == SPI_Mode_Slave))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_data_size\r
+ * @{\r
+ */\r
+\r
+#define SPI_DataSize_4b ((uint16_t)0x0300)\r
+#define SPI_DataSize_5b ((uint16_t)0x0400)\r
+#define SPI_DataSize_6b ((uint16_t)0x0500)\r
+#define SPI_DataSize_7b ((uint16_t)0x0600)\r
+#define SPI_DataSize_8b ((uint16_t)0x0700)\r
+#define SPI_DataSize_9b ((uint16_t)0x0800)\r
+#define SPI_DataSize_10b ((uint16_t)0x0900)\r
+#define SPI_DataSize_11b ((uint16_t)0x0A00)\r
+#define SPI_DataSize_12b ((uint16_t)0x0B00)\r
+#define SPI_DataSize_13b ((uint16_t)0x0C00)\r
+#define SPI_DataSize_14b ((uint16_t)0x0D00)\r
+#define SPI_DataSize_15b ((uint16_t)0x0E00)\r
+#define SPI_DataSize_16b ((uint16_t)0x0F00)\r
+#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \\r
+ ((SIZE) == SPI_DataSize_5b) || \\r
+ ((SIZE) == SPI_DataSize_6b) || \\r
+ ((SIZE) == SPI_DataSize_7b) || \\r
+ ((SIZE) == SPI_DataSize_8b) || \\r
+ ((SIZE) == SPI_DataSize_9b) || \\r
+ ((SIZE) == SPI_DataSize_10b) || \\r
+ ((SIZE) == SPI_DataSize_11b) || \\r
+ ((SIZE) == SPI_DataSize_12b) || \\r
+ ((SIZE) == SPI_DataSize_13b) || \\r
+ ((SIZE) == SPI_DataSize_14b) || \\r
+ ((SIZE) == SPI_DataSize_15b) || \\r
+ ((SIZE) == SPI_DataSize_16b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_length\r
+ * @{\r
+ */\r
+\r
+#define SPI_CRCLength_8b ((uint16_t)0x0000)\r
+#define SPI_CRCLength_16b SPI_CR1_CRCL\r
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \\r
+ ((LENGTH) == SPI_CRCLength_16b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Clock_Polarity \r
+ * @{\r
+ */\r
+\r
+#define SPI_CPOL_Low ((uint16_t)0x0000)\r
+#define SPI_CPOL_High SPI_CR1_CPOL\r
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \\r
+ ((CPOL) == SPI_CPOL_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Clock_Phase \r
+ * @{\r
+ */\r
+\r
+#define SPI_CPHA_1Edge ((uint16_t)0x0000)\r
+#define SPI_CPHA_2Edge SPI_CR1_CPHA\r
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \\r
+ ((CPHA) == SPI_CPHA_2Edge))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Slave_Select_management \r
+ * @{\r
+ */\r
+\r
+#define SPI_NSS_Soft SPI_CR1_SSM\r
+#define SPI_NSS_Hard ((uint16_t)0x0000)\r
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \\r
+ ((NSS) == SPI_NSS_Hard))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_BaudRate_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)\r
+#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)\r
+#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)\r
+#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)\r
+#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)\r
+#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)\r
+#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)\r
+#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)\r
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_256))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_MSB_LSB_transmission \r
+ * @{\r
+ */\r
+\r
+#define SPI_FirstBit_MSB ((uint16_t)0x0000)\r
+#define SPI_FirstBit_LSB SPI_CR1_LSBFIRST\r
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \\r
+ ((BIT) == SPI_FirstBit_LSB))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup SPI_I2S_Mode \r
+ * @{\r
+ */\r
+\r
+#define I2S_Mode_SlaveTx ((uint16_t)0x0000)\r
+#define I2S_Mode_SlaveRx ((uint16_t)0x0100)\r
+#define I2S_Mode_MasterTx ((uint16_t)0x0200)\r
+#define I2S_Mode_MasterRx ((uint16_t)0x0300)\r
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \\r
+ ((MODE) == I2S_Mode_SlaveRx) || \\r
+ ((MODE) == I2S_Mode_MasterTx)|| \\r
+ ((MODE) == I2S_Mode_MasterRx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_Standard \r
+ * @{\r
+ */\r
+\r
+#define I2S_Standard_Phillips ((uint16_t)0x0000)\r
+#define I2S_Standard_MSB ((uint16_t)0x0010)\r
+#define I2S_Standard_LSB ((uint16_t)0x0020)\r
+#define I2S_Standard_PCMShort ((uint16_t)0x0030)\r
+#define I2S_Standard_PCMLong ((uint16_t)0x00B0)\r
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \\r
+ ((STANDARD) == I2S_Standard_MSB) || \\r
+ ((STANDARD) == I2S_Standard_LSB) || \\r
+ ((STANDARD) == I2S_Standard_PCMShort) || \\r
+ ((STANDARD) == I2S_Standard_PCMLong))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_Data_Format \r
+ * @{\r
+ */\r
+\r
+#define I2S_DataFormat_16b ((uint16_t)0x0000)\r
+#define I2S_DataFormat_16bextended ((uint16_t)0x0001)\r
+#define I2S_DataFormat_24b ((uint16_t)0x0003)\r
+#define I2S_DataFormat_32b ((uint16_t)0x0005)\r
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \\r
+ ((FORMAT) == I2S_DataFormat_16bextended) || \\r
+ ((FORMAT) == I2S_DataFormat_24b) || \\r
+ ((FORMAT) == I2S_DataFormat_32b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_MCLK_Output \r
+ * @{\r
+ */\r
+\r
+#define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE\r
+#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)\r
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \\r
+ ((OUTPUT) == I2S_MCLKOutput_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_Audio_Frequency \r
+ * @{\r
+ */\r
+\r
+#define I2S_AudioFreq_192k ((uint32_t)192000)\r
+#define I2S_AudioFreq_96k ((uint32_t)96000)\r
+#define I2S_AudioFreq_48k ((uint32_t)48000)\r
+#define I2S_AudioFreq_44k ((uint32_t)44100)\r
+#define I2S_AudioFreq_32k ((uint32_t)32000)\r
+#define I2S_AudioFreq_22k ((uint32_t)22050)\r
+#define I2S_AudioFreq_16k ((uint32_t)16000)\r
+#define I2S_AudioFreq_11k ((uint32_t)11025)\r
+#define I2S_AudioFreq_8k ((uint32_t)8000)\r
+#define I2S_AudioFreq_Default ((uint32_t)2)\r
+\r
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \\r
+ ((FREQ) <= I2S_AudioFreq_192k)) || \\r
+ ((FREQ) == I2S_AudioFreq_Default))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_Clock_Polarity \r
+ * @{\r
+ */\r
+\r
+#define I2S_CPOL_Low ((uint16_t)0x0000)\r
+#define I2S_CPOL_High SPI_I2SCFGR_CKPOL\r
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \\r
+ ((CPOL) == I2S_CPOL_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_FIFO_reception_threshold \r
+ * @{\r
+ */\r
+\r
+#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)\r
+#define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH\r
+#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \\r
+ ((THRESHOLD) == SPI_RxFIFOThreshold_QF))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_DMA_transfer_requests \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN\r
+#define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN\r
+#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_last_DMA_transfers\r
+ * @{\r
+ */\r
+\r
+#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)\r
+#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)\r
+#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)\r
+#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)\r
+#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \\r
+ ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \\r
+ ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \\r
+ ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup SPI_NSS_internal_software_management \r
+ * @{\r
+ */\r
+\r
+#define SPI_NSSInternalSoft_Set SPI_CR1_SSI\r
+#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)\r
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \\r
+ ((INTERNAL) == SPI_NSSInternalSoft_Reset))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_Transmit_Receive \r
+ * @{\r
+ */\r
+\r
+#define SPI_CRC_Tx ((uint8_t)0x00)\r
+#define SPI_CRC_Rx ((uint8_t)0x01)\r
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_direction_transmit_receive \r
+ * @{\r
+ */\r
+\r
+#define SPI_Direction_Rx ((uint16_t)0xBFFF)\r
+#define SPI_Direction_Tx ((uint16_t)0x4000)\r
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \\r
+ ((DIRECTION) == SPI_Direction_Tx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_IT_TXE ((uint8_t)0x71)\r
+#define SPI_I2S_IT_RXNE ((uint8_t)0x60)\r
+#define SPI_I2S_IT_ERR ((uint8_t)0x50)\r
+\r
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == SPI_I2S_IT_RXNE) || \\r
+ ((IT) == SPI_I2S_IT_ERR))\r
+\r
+#define I2S_IT_UDR ((uint8_t)0x53)\r
+#define SPI_IT_MODF ((uint8_t)0x55)\r
+#define SPI_I2S_IT_OVR ((uint8_t)0x56)\r
+#define SPI_I2S_IT_FRE ((uint8_t)0x58)\r
+\r
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \\r
+ ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup SPI_transmission_fifo_status_level \r
+ * @{\r
+ */ \r
+\r
+#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)\r
+#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800) \r
+#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000) \r
+#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_reception_fifo_status_level \r
+ * @{\r
+ */ \r
+#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)\r
+#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200) \r
+#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400) \r
+#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup SPI_I2S_flags_definition \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_FLAG_RXNE SPI_SR_RXNE\r
+#define SPI_I2S_FLAG_TXE SPI_SR_TXE\r
+#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE\r
+#define I2S_FLAG_UDR SPI_SR_UDR\r
+#define SPI_FLAG_CRCERR SPI_SR_CRCERR\r
+#define SPI_FLAG_MODF SPI_SR_MODF\r
+#define SPI_I2S_FLAG_OVR SPI_SR_OVR\r
+#define SPI_I2S_FLAG_BSY SPI_SR_BSY\r
+#define SPI_I2S_FLAG_FRE SPI_SR_FRE\r
+\r
+\r
+\r
+#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))\r
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \\r
+ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \\r
+ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \\r
+ ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \\r
+ ((FLAG) == I2S_FLAG_UDR))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_polynomial \r
+ * @{\r
+ */\r
+\r
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);\r
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);\r
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);\r
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);\r
+void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+\r
+/* Data transfers functions ***************************************************/\r
+void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);\r
+void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);\r
+uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);\r
+uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);\r
+\r
+/* Hardware CRC Calculation functions *****************************************/\r
+void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r
+void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r
+uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);\r
+uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F0XX_SPI_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_syscfg.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the SYSCFG firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/*!< Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_SYSCFG_H\r
+#define __STM32F0XX_SYSCFG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*!< Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SYSCFG\r
+ * @{\r
+ */\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup SYSCFG_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup EXTI_Port_Sources \r
+ * @{\r
+ */ \r
+#define EXTI_PortSourceGPIOA ((uint8_t)0x00)\r
+#define EXTI_PortSourceGPIOB ((uint8_t)0x01)\r
+#define EXTI_PortSourceGPIOC ((uint8_t)0x02)\r
+#define EXTI_PortSourceGPIOD ((uint8_t)0x03)\r
+#define EXTI_PortSourceGPIOF ((uint8_t)0x05)\r
+\r
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \\r
+ ((PORTSOURCE) == EXTI_PortSourceGPIOF)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Pin_sources \r
+ * @{\r
+ */ \r
+#define EXTI_PinSource0 ((uint8_t)0x00)\r
+#define EXTI_PinSource1 ((uint8_t)0x01)\r
+#define EXTI_PinSource2 ((uint8_t)0x02)\r
+#define EXTI_PinSource3 ((uint8_t)0x03)\r
+#define EXTI_PinSource4 ((uint8_t)0x04)\r
+#define EXTI_PinSource5 ((uint8_t)0x05)\r
+#define EXTI_PinSource6 ((uint8_t)0x06)\r
+#define EXTI_PinSource7 ((uint8_t)0x07)\r
+#define EXTI_PinSource8 ((uint8_t)0x08)\r
+#define EXTI_PinSource9 ((uint8_t)0x09)\r
+#define EXTI_PinSource10 ((uint8_t)0x0A)\r
+#define EXTI_PinSource11 ((uint8_t)0x0B)\r
+#define EXTI_PinSource12 ((uint8_t)0x0C)\r
+#define EXTI_PinSource13 ((uint8_t)0x0D)\r
+#define EXTI_PinSource14 ((uint8_t)0x0E)\r
+#define EXTI_PinSource15 ((uint8_t)0x0F)\r
+\r
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \\r
+ ((PINSOURCE) == EXTI_PinSource1) || \\r
+ ((PINSOURCE) == EXTI_PinSource2) || \\r
+ ((PINSOURCE) == EXTI_PinSource3) || \\r
+ ((PINSOURCE) == EXTI_PinSource4) || \\r
+ ((PINSOURCE) == EXTI_PinSource5) || \\r
+ ((PINSOURCE) == EXTI_PinSource6) || \\r
+ ((PINSOURCE) == EXTI_PinSource7) || \\r
+ ((PINSOURCE) == EXTI_PinSource8) || \\r
+ ((PINSOURCE) == EXTI_PinSource9) || \\r
+ ((PINSOURCE) == EXTI_PinSource10) || \\r
+ ((PINSOURCE) == EXTI_PinSource11) || \\r
+ ((PINSOURCE) == EXTI_PinSource12) || \\r
+ ((PINSOURCE) == EXTI_PinSource13) || \\r
+ ((PINSOURCE) == EXTI_PinSource14) || \\r
+ ((PINSOURCE) == EXTI_PinSource15))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_Memory_Remap_Config \r
+ * @{\r
+ */ \r
+#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)\r
+#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01)\r
+#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)\r
+\r
+\r
+#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \\r
+ ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \\r
+ ((REMAP) == SYSCFG_MemoryRemap_SRAM))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_DMA_Remap_Config \r
+ * @{\r
+ */ \r
+#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2 */\r
+#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4 */\r
+#define SYSCFG_DMARemap_USART1Rx SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5 */\r
+#define SYSCFG_DMARemap_USART1Tx SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4 */\r
+#define SYSCFG_DMARemap_ADC1 SYSCFG_CFGR1_ADC_DMA_RMP /* Remap ADC1 DMA requests from channel1 to channel2 */\r
+ \r
+#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \\r
+ ((REMAP) == SYSCFG_DMARemap_TIM16) || \\r
+ ((REMAP) == SYSCFG_DMARemap_USART1Rx) || \\r
+ ((REMAP) == SYSCFG_DMARemap_USART1Tx) || \\r
+ ((REMAP) == SYSCFG_DMARemap_ADC1))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_I2C_FastModePlus_Config \r
+ * @{\r
+ */ \r
+#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /* Enable Fast Mode Plus on PB6 */\r
+#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /* Enable Fast Mode Plus on PB7 */\r
+#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /* Enable Fast Mode Plus on PB8 */\r
+#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /* Enable Fast Mode Plus on PB9 */\r
+\r
+#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \\r
+ ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \\r
+ ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \\r
+ ((PIN) == SYSCFG_I2CFastModePlus_PB9))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_Lock_Config \r
+ * @{\r
+ */ \r
+#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Connects the PVD event to the Break Input of TIM1 */\r
+#define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Connects the SRAM_PARITY error signal to the Break Input of TIM1 */\r
+#define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */\r
+\r
+#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \\r
+ ((CONFIG) == SYSCFG_Break_SRAMParity) || \\r
+ ((CONFIG) == SYSCFG_Break_Lockup))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_flags_definition \r
+ * @{\r
+ */\r
+\r
+#define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE\r
+\r
+#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Function used to set the SYSCFG configuration to the default reset state **/\r
+void SYSCFG_DeInit(void);\r
+\r
+/* SYSCFG configuration functions *********************************************/ \r
+void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);\r
+void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);\r
+void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);\r
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);\r
+void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);\r
+FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);\r
+void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F0XX_SYSCFG_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_tim.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the TIM \r
+ * firmware library. \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_TIM_H\r
+#define __STM32F0XX_TIM_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief TIM Time Base Init structure definition\r
+ * @note This sturcture is used with all TIMx.\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
+ This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.\r
+ This parameter can be a value of @ref TIM_Counter_Mode */\r
+\r
+ uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active\r
+ Auto-Reload Register at the next update event.\r
+ This parameter must be a number between 0x0000 and 0xFFFF. */ \r
+\r
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.\r
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */\r
+\r
+ uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter\r
+ reaches zero, an update event is generated and counting restarts\r
+ from the RCR value (N).\r
+ This means in PWM mode that (N+1) corresponds to:\r
+ - the number of PWM periods in edge-aligned mode\r
+ - the number of half PWM period in center-aligned mode\r
+ This parameter must be a number between 0x00 and 0xFF. \r
+ @note This parameter is valid only for TIM1. */\r
+} TIM_TimeBaseInitTypeDef; \r
+\r
+/** \r
+ * @brief TIM Output Compare Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_state */\r
+\r
+ uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_state\r
+ @note This parameter is valid only for TIM1. */\r
+\r
+ uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
+ This parameter can be a number between 0x0000 and 0xFFFF ( or 0xFFFFFFFF \r
+ for TIM2) */\r
+\r
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+ uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
+ @note This parameter is valid only for TIM1. */\r
+\r
+ uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
+ @note This parameter is valid only for TIM1. */\r
+\r
+ uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
+ @note This parameter is valid only for TIM1. */\r
+} TIM_OCInitTypeDef;\r
+\r
+/** \r
+ * @brief TIM Input Capture Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.\r
+ This parameter can be a value of @ref TIM_Channel */\r
+\r
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint16_t TIM_ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between 0x0 and 0xF */\r
+} TIM_ICInitTypeDef;\r
+\r
+/** \r
+ * @brief TIM_BDTR structure definition \r
+ * @note This sturcture is used only with TIM1. \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.\r
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */\r
+\r
+ uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.\r
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */\r
+\r
+ uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.\r
+ This parameter can be a value of @ref TIM_Lock_level */ \r
+\r
+ uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the\r
+ switching-on of the outputs.\r
+ This parameter can be a number between 0x00 and 0xFF */\r
+\r
+ uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. \r
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */\r
+\r
+ uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.\r
+ This parameter can be a value of @ref TIM_Break_Polarity */\r
+\r
+ uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. \r
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */\r
+} TIM_BDTRInitTypeDef;\r
+\r
+/** \r
+ * @brief TIM Input Capture Init structure definition \r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+ \r
+/** @defgroup TIM_Exported_constants \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM14)|| \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17))\r
+\r
+/* LIST1: TIM 1 */\r
+#define IS_TIM_LIST1_PERIPH(PERIPH) ((PERIPH) == TIM1)\r
+\r
+/* LIST2: TIM 1, 15, 16 and 17 */\r
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17)) \r
+\r
+/* LIST3: TIM 1, 2 and 3 */\r
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3)) \r
+\r
+/* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */\r
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM14) || \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17))\r
+\r
+/* LIST4: TIM 1, 2, 3, 15, 16 and 17 */\r
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17))\r
+\r
+/* LIST5: TIM 1, 2, 3 and 15 */\r
+#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM15)) \r
+\r
+/* LIST7: TIM 1, 2, 3, 6 and 14 */\r
+#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM14))\r
+ \r
+/* LIST8: TIM 1, 2, 3 and 14 */\r
+#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM14))\r
+\r
+/* LIST9: TIM 1, 2, 3, 6 and 15 */\r
+#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM15))\r
+\r
+/* LIST10: TIM 1, 2, 3, 6, 15, 16 and 17 */\r
+#define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17))\r
+\r
+/* LIST1: TIM 11 */\r
+#define IS_TIM_LIST11_PERIPH(PERIPH) ((PERIPH) == TIM14)\r
+ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_and_PWM_modes \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCMode_Timing ((uint16_t)0x0000)\r
+#define TIM_OCMode_Active ((uint16_t)0x0010)\r
+#define TIM_OCMode_Inactive ((uint16_t)0x0020)\r
+#define TIM_OCMode_Toggle ((uint16_t)0x0030)\r
+#define TIM_OCMode_PWM1 ((uint16_t)0x0060)\r
+#define TIM_OCMode_PWM2 ((uint16_t)0x0070)\r
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2))\r
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2) || \\r
+ ((MODE) == TIM_ForcedAction_Active) || \\r
+ ((MODE) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_One_Pulse_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_OPMode_Single ((uint16_t)0x0008)\r
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)\r
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \\r
+ ((MODE) == TIM_OPMode_Repetitive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Channel \r
+ * @{\r
+ */\r
+\r
+#define TIM_Channel_1 ((uint16_t)0x0000)\r
+#define TIM_Channel_2 ((uint16_t)0x0004)\r
+#define TIM_Channel_3 ((uint16_t)0x0008)\r
+#define TIM_Channel_4 ((uint16_t)0x000C)\r
+\r
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2) || \\r
+ ((CHANNEL) == TIM_Channel_3) || \\r
+ ((CHANNEL) == TIM_Channel_4))\r
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2) || \\r
+ ((CHANNEL) == TIM_Channel_3))\r
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Clock_Division_CKD \r
+ * @{\r
+ */\r
+\r
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)\r
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)\r
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)\r
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \\r
+ ((DIV) == TIM_CKD_DIV2) || \\r
+ ((DIV) == TIM_CKD_DIV4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Counter_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_CounterMode_Up ((uint16_t)0x0000)\r
+#define TIM_CounterMode_Down ((uint16_t)0x0010)\r
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)\r
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)\r
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)\r
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \\r
+ ((MODE) == TIM_CounterMode_Down) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPolarity_High ((uint16_t)0x0000)\r
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)\r
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \\r
+ ((POLARITY) == TIM_OCPolarity_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_N_Polarity \r
+ * @{\r
+ */\r
+ \r
+#define TIM_OCNPolarity_High ((uint16_t)0x0000)\r
+#define TIM_OCNPolarity_Low ((uint16_t)0x0008)\r
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \\r
+ ((POLARITY) == TIM_OCNPolarity_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_state\r
+ * @{\r
+ */\r
+\r
+#define TIM_OutputState_Disable ((uint16_t)0x0000)\r
+#define TIM_OutputState_Enable ((uint16_t)0x0001)\r
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \\r
+ ((STATE) == TIM_OutputState_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_N_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OutputNState_Disable ((uint16_t)0x0000)\r
+#define TIM_OutputNState_Enable ((uint16_t)0x0004)\r
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \\r
+ ((STATE) == TIM_OutputNState_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Capture_Compare_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_CCx_Enable ((uint16_t)0x0001)\r
+#define TIM_CCx_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \\r
+ ((CCX) == TIM_CCx_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Capture_Compare_N_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_CCxN_Enable ((uint16_t)0x0004)\r
+#define TIM_CCxN_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \\r
+ ((CCXN) == TIM_CCxN_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Break_Input_enable_disable \r
+ * @{\r
+ */\r
+\r
+#define TIM_Break_Enable ((uint16_t)0x1000)\r
+#define TIM_Break_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \\r
+ ((STATE) == TIM_Break_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Break_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_BreakPolarity_Low ((uint16_t)0x0000)\r
+#define TIM_BreakPolarity_High ((uint16_t)0x2000)\r
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \\r
+ ((POLARITY) == TIM_BreakPolarity_High))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_AOE_Bit_Set_Reset \r
+ * @{\r
+ */\r
+\r
+#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)\r
+#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \\r
+ ((STATE) == TIM_AutomaticOutput_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Lock_level \r
+ * @{\r
+ */\r
+\r
+#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)\r
+#define TIM_LOCKLevel_1 ((uint16_t)0x0100)\r
+#define TIM_LOCKLevel_2 ((uint16_t)0x0200)\r
+#define TIM_LOCKLevel_3 ((uint16_t)0x0300)\r
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \\r
+ ((LEVEL) == TIM_LOCKLevel_1) || \\r
+ ((LEVEL) == TIM_LOCKLevel_2) || \\r
+ ((LEVEL) == TIM_LOCKLevel_3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OSSIState_Enable ((uint16_t)0x0400)\r
+#define TIM_OSSIState_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \\r
+ ((STATE) == TIM_OSSIState_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OSSRState_Enable ((uint16_t)0x0800)\r
+#define TIM_OSSRState_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \\r
+ ((STATE) == TIM_OSSRState_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Idle_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCIdleState_Set ((uint16_t)0x0100)\r
+#define TIM_OCIdleState_Reset ((uint16_t)0x0000)\r
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \\r
+ ((STATE) == TIM_OCIdleState_Reset))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_N_Idle_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCNIdleState_Set ((uint16_t)0x0200)\r
+#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)\r
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \\r
+ ((STATE) == TIM_OCNIdleState_Reset))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)\r
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)\r
+#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)\r
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
+ ((POLARITY) == TIM_ICPolarity_Falling)|| \\r
+ ((POLARITY) == TIM_ICPolarity_BothEdge)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \r
+ connected to IC1, IC2, IC3 or IC4, respectively */\r
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+ connected to IC2, IC1, IC4 or IC3, respectively. */\r
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */\r
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_TRC))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */\r
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */\r
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */\r
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */\r
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_interrupt_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_IT_Update ((uint16_t)0x0001)\r
+#define TIM_IT_CC1 ((uint16_t)0x0002)\r
+#define TIM_IT_CC2 ((uint16_t)0x0004)\r
+#define TIM_IT_CC3 ((uint16_t)0x0008)\r
+#define TIM_IT_CC4 ((uint16_t)0x0010)\r
+#define TIM_IT_COM ((uint16_t)0x0020)\r
+#define TIM_IT_Trigger ((uint16_t)0x0040)\r
+#define TIM_IT_Break ((uint16_t)0x0080)\r
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))\r
+\r
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \\r
+ ((IT) == TIM_IT_CC1) || \\r
+ ((IT) == TIM_IT_CC2) || \\r
+ ((IT) == TIM_IT_CC3) || \\r
+ ((IT) == TIM_IT_CC4) || \\r
+ ((IT) == TIM_IT_COM) || \\r
+ ((IT) == TIM_IT_Trigger) || \\r
+ ((IT) == TIM_IT_Break))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Base_address \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)\r
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)\r
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)\r
+#define TIM_DMABase_DIER ((uint16_t)0x0003)\r
+#define TIM_DMABase_SR ((uint16_t)0x0004)\r
+#define TIM_DMABase_EGR ((uint16_t)0x0005)\r
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)\r
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)\r
+#define TIM_DMABase_CCER ((uint16_t)0x0008)\r
+#define TIM_DMABase_CNT ((uint16_t)0x0009)\r
+#define TIM_DMABase_PSC ((uint16_t)0x000A)\r
+#define TIM_DMABase_ARR ((uint16_t)0x000B)\r
+#define TIM_DMABase_RCR ((uint16_t)0x000C)\r
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)\r
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)\r
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)\r
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)\r
+#define TIM_DMABase_BDTR ((uint16_t)0x0011)\r
+#define TIM_DMABase_DCR ((uint16_t)0x0012)\r
+#define TIM_DMABase_OR ((uint16_t)0x0013)\r
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \\r
+ ((BASE) == TIM_DMABase_CR2) || \\r
+ ((BASE) == TIM_DMABase_SMCR) || \\r
+ ((BASE) == TIM_DMABase_DIER) || \\r
+ ((BASE) == TIM_DMABase_SR) || \\r
+ ((BASE) == TIM_DMABase_EGR) || \\r
+ ((BASE) == TIM_DMABase_CCMR1) || \\r
+ ((BASE) == TIM_DMABase_CCMR2) || \\r
+ ((BASE) == TIM_DMABase_CCER) || \\r
+ ((BASE) == TIM_DMABase_CNT) || \\r
+ ((BASE) == TIM_DMABase_PSC) || \\r
+ ((BASE) == TIM_DMABase_ARR) || \\r
+ ((BASE) == TIM_DMABase_RCR) || \\r
+ ((BASE) == TIM_DMABase_CCR1) || \\r
+ ((BASE) == TIM_DMABase_CCR2) || \\r
+ ((BASE) == TIM_DMABase_CCR3) || \\r
+ ((BASE) == TIM_DMABase_CCR4) || \\r
+ ((BASE) == TIM_DMABase_BDTR) || \\r
+ ((BASE) == TIM_DMABase_OR))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup TIM_DMA_Burst_Length \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)\r
+#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)\r
+#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)\r
+#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)\r
+#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)\r
+#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)\r
+#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)\r
+#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)\r
+#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)\r
+#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)\r
+#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)\r
+#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)\r
+#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)\r
+#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)\r
+#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)\r
+#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)\r
+#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)\r
+#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)\r
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \\r
+ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \\r
+ ((LENGTH) == TIM_DMABurstLength_18Transfers))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMA_Update ((uint16_t)0x0100)\r
+#define TIM_DMA_CC1 ((uint16_t)0x0200)\r
+#define TIM_DMA_CC2 ((uint16_t)0x0400)\r
+#define TIM_DMA_CC3 ((uint16_t)0x0800)\r
+#define TIM_DMA_CC4 ((uint16_t)0x1000)\r
+#define TIM_DMA_COM ((uint16_t)0x2000)\r
+#define TIM_DMA_Trigger ((uint16_t)0x4000)\r
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)\r
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)\r
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)\r
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)\r
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Internal_Trigger_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_TS_ITR0 ((uint16_t)0x0000)\r
+#define TIM_TS_ITR1 ((uint16_t)0x0010)\r
+#define TIM_TS_ITR2 ((uint16_t)0x0020)\r
+#define TIM_TS_ITR3 ((uint16_t)0x0030)\r
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)\r
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)\r
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)\r
+#define TIM_TS_ETRF ((uint16_t)0x0070)\r
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3) || \\r
+ ((SELECTION) == TIM_TS_TI1F_ED) || \\r
+ ((SELECTION) == TIM_TS_TI1FP1) || \\r
+ ((SELECTION) == TIM_TS_TI2FP2) || \\r
+ ((SELECTION) == TIM_TS_ETRF))\r
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_TIx_External_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)\r
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)\r
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Polarity \r
+ * @{\r
+ */ \r
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)\r
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)\r
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \\r
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Prescaler_Reload_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)\r
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)\r
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \\r
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Forced_Action \r
+ * @{\r
+ */\r
+\r
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)\r
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)\r
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \\r
+ ((ACTION) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Encoder_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)\r
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)\r
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)\r
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \\r
+ ((MODE) == TIM_EncoderMode_TI2) || \\r
+ ((MODE) == TIM_EncoderMode_TI12))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup TIM_Event_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_EventSource_Update ((uint16_t)0x0001)\r
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)\r
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)\r
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)\r
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)\r
+#define TIM_EventSource_COM ((uint16_t)0x0020)\r
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)\r
+#define TIM_EventSource_Break ((uint16_t)0x0080)\r
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Update_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow\r
+ or the setting of UG bit, or an update generation\r
+ through the slave mode controller. */\r
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */\r
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \\r
+ ((SOURCE) == TIM_UpdateSource_Regular))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Preload_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)\r
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \\r
+ ((STATE) == TIM_OCPreload_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Fast_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCFast_Enable ((uint16_t)0x0004)\r
+#define TIM_OCFast_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \\r
+ ((STATE) == TIM_OCFast_Disable))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Clear_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCClear_Enable ((uint16_t)0x0080)\r
+#define TIM_OCClear_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \\r
+ ((STATE) == TIM_OCClear_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Trigger_Output_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)\r
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)\r
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)\r
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)\r
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)\r
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)\r
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)\r
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)\r
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \\r
+ ((SOURCE) == TIM_TRGOSource_Enable) || \\r
+ ((SOURCE) == TIM_TRGOSource_Update) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_SlaveMode_Reset ((uint16_t)0x0004)\r
+#define TIM_SlaveMode_Gated ((uint16_t)0x0005)\r
+#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)\r
+#define TIM_SlaveMode_External1 ((uint16_t)0x0007)\r
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \\r
+ ((MODE) == TIM_SlaveMode_Gated) || \\r
+ ((MODE) == TIM_SlaveMode_Trigger) || \\r
+ ((MODE) == TIM_SlaveMode_External1))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Master_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)\r
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \\r
+ ((STATE) == TIM_MasterSlaveMode_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup TIM_Flags \r
+ * @{\r
+ */\r
+\r
+#define TIM_FLAG_Update ((uint16_t)0x0001)\r
+#define TIM_FLAG_CC1 ((uint16_t)0x0002)\r
+#define TIM_FLAG_CC2 ((uint16_t)0x0004)\r
+#define TIM_FLAG_CC3 ((uint16_t)0x0008)\r
+#define TIM_FLAG_CC4 ((uint16_t)0x0010)\r
+#define TIM_FLAG_COM ((uint16_t)0x0020)\r
+#define TIM_FLAG_Trigger ((uint16_t)0x0040)\r
+#define TIM_FLAG_Break ((uint16_t)0x0080)\r
+#define TIM_FLAG_CC1OF ((uint16_t)0x0200)\r
+#define TIM_FLAG_CC2OF ((uint16_t)0x0400)\r
+#define TIM_FLAG_CC3OF ((uint16_t)0x0800)\r
+#define TIM_FLAG_CC4OF ((uint16_t)0x1000)\r
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \\r
+ ((FLAG) == TIM_FLAG_CC1) || \\r
+ ((FLAG) == TIM_FLAG_CC2) || \\r
+ ((FLAG) == TIM_FLAG_CC3) || \\r
+ ((FLAG) == TIM_FLAG_CC4) || \\r
+ ((FLAG) == TIM_FLAG_COM) || \\r
+ ((FLAG) == TIM_FLAG_Trigger) || \\r
+ ((FLAG) == TIM_FLAG_Break) || \\r
+ ((FLAG) == TIM_FLAG_CC1OF) || \\r
+ ((FLAG) == TIM_FLAG_CC2OF) || \\r
+ ((FLAG) == TIM_FLAG_CC3OF) || \\r
+ ((FLAG) == TIM_FLAG_CC4OF))\r
+ \r
+ \r
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup TIM_Input_Capture_Filer_Value \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Filter \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_OCReferenceClear \r
+ * @{\r
+ */\r
+#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)\r
+#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)\r
+#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \\r
+ ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup TIM_Remap \r
+ * @{\r
+ */\r
+#define TIM14_GPIO ((uint16_t)0x0000)\r
+#define TIM14_RTC_CLK ((uint16_t)0x0001)\r
+\r
+#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM14_GPIO)|| \\r
+ ((TIM_REMAP) == TIM14_RTC_CLK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Legacy \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer\r
+#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers\r
+#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers\r
+#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers\r
+#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers\r
+#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers\r
+#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers\r
+#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers\r
+#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers\r
+#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers\r
+#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers\r
+#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers\r
+#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers\r
+#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers\r
+#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers\r
+#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers\r
+#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers\r
+#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */ \r
+\r
+/* TimeBase management ********************************************************/\r
+void TIM_DeInit(TIM_TypeDef* TIMx);\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);\r
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Advanced-control timers (TIM1) specific features*******************/\r
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);\r
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);\r
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Output Compare management **************************************************/\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);\r
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);\r
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Input Capture management ***************************************************/\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);\r
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+\r
+/* Interrupts, DMA and flags management ***************************************/\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Clocks management **********************************************************/\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r
+\r
+\r
+/* Synchronization management *************************************************/\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+\r
+/* Specific interface management **********************************************/ \r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+\r
+/* Specific remapping management **********************************************/\r
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F0XX_TIM_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_usart.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the USART \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_USART_H\r
+#define __STM32F0XX_USART_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup USART\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+ \r
+ \r
+/** \r
+ * @brief USART Init Structure definition \r
+ */ \r
+\r
+typedef struct\r
+{\r
+ uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.\r
+ The baud rate is computed using the following formula:\r
+ - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))\r
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */\r
+\r
+ uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
+ This parameter can be a value of @ref USART_Word_Length */\r
+\r
+ uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.\r
+ This parameter can be a value of @ref USART_Stop_Bits */\r
+\r
+ uint32_t USART_Parity; /*!< Specifies the parity mode.\r
+ This parameter can be a value of @ref USART_Parity\r
+ @note When parity is enabled, the computed parity is inserted\r
+ at the MSB position of the transmitted data (9th bit when\r
+ the word length is set to 9 data bits; 8th bit when the\r
+ word length is set to 8 data bits). */\r
+ \r
+ uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Mode */\r
+\r
+ uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled\r
+ or disabled.\r
+ This parameter can be a value of @ref USART_Hardware_Flow_Control*/\r
+} USART_InitTypeDef;\r
+\r
+/** \r
+ * @brief USART Clock Init Structure definition\r
+ */ \r
+\r
+typedef struct\r
+{\r
+ uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Clock */\r
+\r
+ uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock.\r
+ This parameter can be a value of @ref USART_Clock_Polarity */\r
+\r
+ uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.\r
+ This parameter can be a value of @ref USART_Clock_Phase */\r
+\r
+ uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r
+ This parameter can be a value of @ref USART_Last_Bit */\r
+} USART_ClockInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup USART_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
+ ((PERIPH) == USART2))\r
+\r
+#define IS_USART_1_PERIPH(PERIPH) (((PERIPH) == USART1))\r
+\r
+/** @defgroup USART_Word_Length \r
+ * @{\r
+ */ \r
+\r
+#define USART_WordLength_8b ((uint32_t)0x00000000)\r
+#define USART_WordLength_9b USART_CR1_M\r
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \\r
+ ((LENGTH) == USART_WordLength_9b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Stop_Bits \r
+ * @{\r
+ */ \r
+\r
+#define USART_StopBits_1 ((uint32_t)0x00000000)\r
+#define USART_StopBits_2 ((uint32_t)USART_CR2_STOP_1)\r
+#define USART_StopBits_1_5 ((uint32_t)USART_CR2_STOP_0 | USART_CR2_STOP_1)\r
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \\r
+ ((STOPBITS) == USART_StopBits_2) || \\r
+ ((STOPBITS) == USART_StopBits_1_5))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Parity \r
+ * @{\r
+ */ \r
+\r
+#define USART_Parity_No ((uint32_t)0x00000000)\r
+#define USART_Parity_Even ((uint32_t)USART_CR1_PCE)\r
+#define USART_Parity_Odd ((uint32_t)USART_CR1_PCE | USART_CR1_PS) \r
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \\r
+ ((PARITY) == USART_Parity_Even) || \\r
+ ((PARITY) == USART_Parity_Odd))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Mode \r
+ * @{\r
+ */ \r
+\r
+#define USART_Mode_Rx USART_CR1_RE\r
+#define USART_Mode_Tx USART_CR1_TE\r
+#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \\r
+ ((MODE) != (uint32_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Hardware_Flow_Control \r
+ * @{\r
+ */ \r
+\r
+#define USART_HardwareFlowControl_None ((uint32_t)0x00000000)\r
+#define USART_HardwareFlowControl_RTS ((uint32_t)USART_CR3_RTSE)\r
+#define USART_HardwareFlowControl_CTS ((uint32_t)USART_CR3_CTSE)\r
+#define USART_HardwareFlowControl_RTS_CTS ((uint32_t)USART_CR3_RTSE | USART_CR3_CTSE)\r
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
+ (((CONTROL) == USART_HardwareFlowControl_None) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_CTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock \r
+ * @{\r
+ */ \r
+ \r
+#define USART_Clock_Disable ((uint32_t)0x00000000)\r
+#define USART_Clock_Enable USART_CR2_CLKEN\r
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \\r
+ ((CLOCK) == USART_Clock_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock_Polarity \r
+ * @{\r
+ */\r
+ \r
+#define USART_CPOL_Low ((uint32_t)0x00000000)\r
+#define USART_CPOL_High USART_CR2_CPOL\r
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock_Phase\r
+ * @{\r
+ */\r
+\r
+#define USART_CPHA_1Edge ((uint32_t)0x00000000)\r
+#define USART_CPHA_2Edge USART_CR2_CPHA\r
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Last_Bit\r
+ * @{\r
+ */\r
+\r
+#define USART_LastBit_Disable ((uint32_t)0x00000000)\r
+#define USART_LastBit_Enable USART_CR2_LBCL\r
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \\r
+ ((LASTBIT) == USART_LastBit_Enable))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup USART_DMA_Requests \r
+ * @{\r
+ */\r
+\r
+#define USART_DMAReq_Tx USART_CR3_DMAT\r
+#define USART_DMAReq_Rx USART_CR3_DMAR\r
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \\r
+ ((DMAREQ) != (uint32_t)0x00))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_DMA_Recception_Error\r
+ * @{\r
+ */\r
+\r
+#define USART_DMAOnError_Enable ((uint32_t)0x00000000)\r
+#define USART_DMAOnError_Disable USART_CR3_DDRE\r
+#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \\r
+ ((DMAERROR) == USART_DMAOnError_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_MuteMode_WakeUp_methods\r
+ * @{\r
+ */\r
+\r
+#define USART_WakeUp_IdleLine ((uint32_t)0x00000000)\r
+#define USART_WakeUp_AddressMark USART_CR1_WAKE\r
+#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \\r
+ ((WAKEUP) == USART_WakeUp_AddressMark))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Address_Detection\r
+ * @{\r
+ */ \r
+\r
+#define USART_AddressLength_4b ((uint32_t)0x00000000)\r
+#define USART_AddressLength_7b USART_CR2_ADDM7\r
+#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \\r
+ ((ADDRESS) == USART_AddressLength_7b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_StopMode_WakeUp_methods \r
+ * @{\r
+ */ \r
+\r
+#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000)\r
+#define USART_WakeUpSource_StartBit ((uint32_t)USART_CR3_WUS_1)\r
+#define USART_WakeUpSource_RXNE ((uint32_t)USART_CR3_WUS_0 | USART_CR3_WUS_1)\r
+#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \\r
+ ((SOURCE) == USART_WakeUpSource_StartBit) || \\r
+ ((SOURCE) == USART_WakeUpSource_RXNE))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_LIN_Break_Detection_Length \r
+ * @{\r
+ */\r
+ \r
+#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000)\r
+#define USART_LINBreakDetectLength_11b USART_CR2_LBDL\r
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \\r
+ (((LENGTH) == USART_LINBreakDetectLength_10b) || \\r
+ ((LENGTH) == USART_LINBreakDetectLength_11b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_IrDA_Low_Power \r
+ * @{\r
+ */\r
+\r
+#define USART_IrDAMode_LowPower USART_CR3_IRLP\r
+#define USART_IrDAMode_Normal ((uint32_t)0x00000000)\r
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \\r
+ ((MODE) == USART_IrDAMode_Normal))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_DE_Polarity \r
+ * @{\r
+ */\r
+\r
+#define USART_DEPolarity_High ((uint32_t)0x00000000)\r
+#define USART_DEPolarity_Low USART_CR3_DEP\r
+#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \\r
+ ((POLARITY) == USART_DEPolarity_High))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Inversion_Pins \r
+ * @{\r
+ */\r
+\r
+#define USART_InvPin_Tx USART_CR2_TXINV\r
+#define USART_InvPin_Rx USART_CR2_RXINV\r
+#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \\r
+ ((PIN) != (uint32_t)0x00))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_AutoBaudRate_Mode \r
+ * @{\r
+ */\r
+\r
+#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000)\r
+#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0\r
+#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \\r
+ ((MODE) == USART_AutoBaudRate_FallingEdge))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_OVR_DETECTION\r
+ * @{\r
+ */\r
+\r
+#define USART_OVRDetection_Enable ((uint32_t)0x00000000)\r
+#define USART_OVRDetection_Disable USART_CR3_OVRDIS\r
+#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \\r
+ ((OVR) == USART_OVRDetection_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+/** @defgroup USART_Request \r
+ * @{\r
+ */\r
+\r
+#define USART_Request_ABRRQ USART_RQR_ABRRQ\r
+#define USART_Request_SBKRQ USART_RQR_SBKRQ\r
+#define USART_Request_MMRQ USART_RQR_MMRQ\r
+#define USART_Request_RXFRQ USART_RQR_RXFRQ\r
+#define USART_Request_TXFRQ USART_RQR_TXFRQ\r
+\r
+#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \\r
+ ((REQUEST) == USART_Request_RXFRQ) || \\r
+ ((REQUEST) == USART_Request_MMRQ) || \\r
+ ((REQUEST) == USART_Request_SBKRQ) || \\r
+ ((REQUEST) == USART_Request_ABRRQ))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Flags \r
+ * @{\r
+ */\r
+#define USART_FLAG_REACK USART_ISR_REACK\r
+#define USART_FLAG_TEACK USART_ISR_TEACK\r
+#define USART_FLAG_WU USART_ISR_WUF\r
+#define USART_FLAG_RWU USART_ISR_RWU\r
+#define USART_FLAG_SBK USART_ISR_SBKF\r
+#define USART_FLAG_CM USART_ISR_CMF\r
+#define USART_FLAG_BUSY USART_ISR_BUSY\r
+#define USART_FLAG_ABRF USART_ISR_ABRF\r
+#define USART_FLAG_ABRE USART_ISR_ABRE\r
+#define USART_FLAG_EOB USART_ISR_EOBF\r
+#define USART_FLAG_RTO USART_ISR_RTOF\r
+#define USART_FLAG_nCTSS USART_ISR_CTS \r
+#define USART_FLAG_CTS USART_ISR_CTSIF\r
+#define USART_FLAG_LBD USART_ISR_LBD\r
+#define USART_FLAG_TXE USART_ISR_TXE\r
+#define USART_FLAG_TC USART_ISR_TC\r
+#define USART_FLAG_RXNE USART_ISR_RXNE\r
+#define USART_FLAG_IDLE USART_ISR_IDLE\r
+#define USART_FLAG_ORE USART_ISR_ORE\r
+#define USART_FLAG_NE USART_ISR_NE\r
+#define USART_FLAG_FE USART_ISR_FE\r
+#define USART_FLAG_PE USART_ISR_PE\r
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \\r
+ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \\r
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \\r
+ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \\r
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \\r
+ ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \\r
+ ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \\r
+ ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \\r
+ ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \\r
+ ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \\r
+ ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))\r
+\r
+#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \\r
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \\r
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \\r
+ ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \\r
+ ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \\r
+ ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Interrupt_definition \r
+ * @brief USART Interrupt definition\r
+ * USART_IT possible values\r
+ * Elements values convention: 0xZZZZYYXX\r
+ * XX: Position of the corresponding Interrupt\r
+ * YY: Register index\r
+ * ZZZZ: Flag position\r
+ * @{\r
+ */\r
+\r
+#define USART_IT_WU ((uint32_t)0x00140316)\r
+#define USART_IT_CM ((uint32_t)0x0011010E)\r
+#define USART_IT_EOB ((uint32_t)0x000C011B)\r
+#define USART_IT_RTO ((uint32_t)0x000B011A)\r
+#define USART_IT_PE ((uint32_t)0x00000108)\r
+#define USART_IT_TXE ((uint32_t)0x00070107)\r
+#define USART_IT_TC ((uint32_t)0x00060106)\r
+#define USART_IT_RXNE ((uint32_t)0x00050105)\r
+#define USART_IT_IDLE ((uint32_t)0x00040104)\r
+#define USART_IT_LBD ((uint32_t)0x00080206)\r
+#define USART_IT_CTS ((uint32_t)0x0009030A) \r
+#define USART_IT_ERR ((uint32_t)0x00000300)\r
+#define USART_IT_ORE ((uint32_t)0x00030300)\r
+#define USART_IT_NE ((uint32_t)0x00020300)\r
+#define USART_IT_FE ((uint32_t)0x00010300)\r
+\r
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \\r
+ ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \\r
+ ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))\r
+\r
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \\r
+ ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \\r
+ ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \\r
+ ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))\r
+\r
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \\r
+ ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \\r
+ ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \\r
+ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \\r
+ ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \\r
+ ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Global_definition \r
+ * @{\r
+ */\r
+\r
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))\r
+#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)\r
+#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)\r
+#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)\r
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/* Initialization and Configuration functions *********************************/\r
+void USART_DeInit(USART_TypeDef* USARTx);\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);\r
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);\r
+void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);\r
+\r
+/* STOP Mode functions ********************************************************/\r
+void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource);\r
+\r
+/* AutoBaudRate functions *****************************************************/\r
+void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);\r
+void USART_AutoBaudRateNewRequest(USART_TypeDef* USARTx);\r
+\r
+/* Data transfers functions ***************************************************/\r
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);\r
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);\r
+\r
+/* Multi-Processor Communication functions ************************************/\r
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);\r
+void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);\r
+void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);\r
+/* LIN mode functions *********************************************************/\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength);\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* Half-duplex mode function **************************************************/\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* Smartcard mode functions ***************************************************/\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);\r
+void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount);\r
+void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength);\r
+\r
+/* IrDA mode functions ********************************************************/\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode);\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+\r
+/* RS485 mode functions *******************************************************/\r
+void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);\r
+void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);\r
+void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);\r
+\r
+/* DMA transfers management functions *****************************************/\r
+void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);\r
+void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);\r
+void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);\r
+void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);\r
+void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F0XX_USART_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_wwdg.h\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file contains all the functions prototypes for the WWDG \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F0XX_WWDG_H\r
+#define __STM32F0XX_WWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup WWDG\r
+ * @{\r
+ */ \r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup WWDG_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup WWDG_Prescaler \r
+ * @{\r
+ */ \r
+ \r
+#define WWDG_Prescaler_1 ((uint32_t)0x00000000)\r
+#define WWDG_Prescaler_2 ((uint32_t)0x00000080)\r
+#define WWDG_Prescaler_4 ((uint32_t)0x00000100)\r
+#define WWDG_Prescaler_8 ((uint32_t)0x00000180)\r
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \\r
+ ((PRESCALER) == WWDG_Prescaler_2) || \\r
+ ((PRESCALER) == WWDG_Prescaler_4) || \\r
+ ((PRESCALER) == WWDG_Prescaler_8))\r
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)\r
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+/* Function used to set the WWDG configuration to the default reset state ****/ \r
+void WWDG_DeInit(void);\r
+\r
+/* Prescaler, Refresh window and Counter configuration functions **************/\r
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);\r
+void WWDG_SetWindowValue(uint8_t WindowValue);\r
+void WWDG_EnableIT(void);\r
+void WWDG_SetCounter(uint8_t Counter);\r
+\r
+/* WWDG activation functions **************************************************/\r
+void WWDG_Enable(uint8_t Counter);\r
+\r
+/* Interrupts and flags management functions **********************************/\r
+FlagStatus WWDG_GetFlagStatus(void);\r
+void WWDG_ClearFlag(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F0XX_WWDG_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_adc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Analog to Digital Convertor (ADC) peripheral:\r
+ * + Initialization and Configuration\r
+ * + Power saving\r
+ * + Analog Watchdog configuration\r
+ * + Temperature Sensor, Vrefint (Internal Reference Voltage) and \r
+ * Vbat (Voltage battery) management \r
+ * + ADC Channels Configuration\r
+ * + ADC Channels DMA Configuration\r
+ * + Interrupts and flags management\r
+ *\r
+ * @verbatim\r
+================================================================================\r
+ ##### How to use this driver #####\r
+================================================================================\r
+ [..]\r
+ (#) Enable the ADC interface clock using \r
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); \r
+ (#) ADC pins configuration\r
+ (++) Enable the clock for the ADC GPIOs using the following function:\r
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE); \r
+ (++) Configure these ADC pins in analog mode using GPIO_Init(); \r
+ (#) Configure the ADC conversion resolution, data alignment, external\r
+ trigger and edge, scan direction and Enable/Disable the continuous mode\r
+ using the ADC_Init() function.\r
+ (#) Activate the ADC peripheral using ADC_Cmd() function.\r
+\r
+ *** ADC channels group configuration ***\r
+ ============================================\r
+ [..] \r
+ (+) To configure the ADC channels features, use ADC_Init() and \r
+ ADC_ChannelConfig() functions.\r
+ (+) To activate the continuous mode, use the ADC_ContinuousModeCmd()\r
+ function.\r
+ (+) To activate the Discontinuous mode, use the ADC_DiscModeCmd() functions. \r
+ (+) To activate the overrun mode, use the ADC_OverrunModeCmd() functions.\r
+ (+) To activate the calibration mode, use the ADC_GetCalibrationFactor() functions.\r
+ (+) To read the ADC converted values, use the ADC_GetConversionValue()\r
+ function.\r
+\r
+ *** DMA for ADC channels features configuration ***\r
+ =============================================================\r
+ [..] \r
+ (+) To enable the DMA mode for ADC channels group, use the ADC_DMACmd() function.\r
+ (+) To configure the DMA transfer request, use ADC_DMARequestModeConfig() function.\r
+\r
+ * @endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_adc.h"\r
+#include "stm32f0xx_rcc.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC \r
+ * @brief ADC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ADC CFGR mask */\r
+#define CFGR1_CLEAR_MASK ((uint32_t)0xFFFFD203)\r
+\r
+/* Calibration time out */\r
+#define CALIBRATION_TIMEOUT ((uint32_t)0x0000F000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup ADC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initialize and configure the ADC Prescaler\r
+ (+) ADC Conversion Resolution (12bit..6bit)\r
+ (+) ADC Continuous Conversion Mode (Continuous or Single conversion)\r
+ (+) External trigger Edge and source \r
+ (+) Converted data alignment (left or right)\r
+ (+) The direction in which the channels will be scanned in the sequence\r
+ (+) Enable or disable the ADC peripheral\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes ADC1 peripheral registers to their default reset values.\r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_DeInit(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ if(ADCx == ADC1)\r
+ {\r
+ /* Enable ADC1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);\r
+\r
+ /* Release ADC1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ADCx peripheral according to the specified parameters\r
+ * in the ADC_InitStruct.\r
+ * @note This function is used to configure the global features of the ADC ( \r
+ * Resolution, Data Alignment, continuous mode activation, External \r
+ * trigger source and edge, Sequence Scan Direction). \r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains \r
+ * the configuration information for the specified ADC peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));\r
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));\r
+ assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge));\r
+ assert_param(IS_ADC_EXTERNAL_TRIG_CONV(ADC_InitStruct->ADC_ExternalTrigConv));\r
+ assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));\r
+ assert_param(IS_ADC_SCAN_DIRECTION(ADC_InitStruct->ADC_ScanDirection)); \r
+\r
+ /* Get the ADCx CFGR value */\r
+ tmpreg = ADCx->CFGR1;\r
+\r
+ /* Clear SCANDIR, RES[1:0], ALIGN, EXTSEL[2:0], EXTEN[1:0] and CONT bits */\r
+ tmpreg &= CFGR1_CLEAR_MASK;\r
+\r
+ /*---------------------------- ADCx CFGR Configuration ---------------------*/\r
+\r
+ /* Set RES[1:0] bits according to ADC_Resolution value */\r
+ /* Set CONT bit according to ADC_ContinuousConvMode value */\r
+ /* Set EXTEN[1:0] bits according to ADC_ExternalTrigConvEdge value */\r
+ /* Set EXTSEL[2:0] bits according to ADC_ExternalTrigConv value */\r
+ /* Set ALIGN bit according to ADC_DataAlign value */\r
+ /* Set SCANDIR bit according to ADC_ScanDirection value */\r
+ \r
+ tmpreg |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ((uint32_t)(ADC_InitStruct->ADC_ContinuousConvMode) << 13) |\r
+ ADC_InitStruct->ADC_ExternalTrigConvEdge | ADC_InitStruct->ADC_ExternalTrigConv |\r
+ ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ScanDirection);\r
+\r
+ /* Write to ADCx CFGR */\r
+ ADCx->CFGR1 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each ADC_InitStruct member with its default value.\r
+ * @note This function is used to initialize the global features of the ADC ( \r
+ * Resolution, Data Alignment, continuous mode activation, External \r
+ * trigger source and edge, Sequence Scan Direction).\r
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)\r
+{\r
+ /* Reset ADC init structure parameters values */\r
+ /* Initialize the ADC_Resolution member */\r
+ ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;\r
+\r
+ /* Initialize the ADC_ContinuousConvMode member */\r
+ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;\r
+\r
+ /* Initialize the ADC_ExternalTrigConvEdge member */\r
+ ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;\r
+\r
+ /* Initialize the ADC_ExternalTrigConv member */\r
+ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO;\r
+\r
+ /* Initialize the ADC_DataAlign member */\r
+ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;\r
+\r
+ /* Initialize the ADC_ScanDirection member */\r
+ ADC_InitStruct->ADC_ScanDirection = ADC_ScanDirection_Upward;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC peripheral.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the ADCx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the ADEN bit to Enable the ADC peripheral */\r
+ ADCx->CR |= (uint32_t)ADC_CR_ADEN;\r
+ }\r
+ else\r
+ {\r
+ /* Set the ADDIS to Disable the ADC peripheral */\r
+ ADCx->CR |= (uint32_t)ADC_CR_ADDIS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the jitter when the ADC is clocked by PCLK div2\r
+ * or div4\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_JitterOff: This parameter can be :\r
+ * @arg ADC_JitterOff_PCLKDiv2: Remove jitter when ADC is clocked by PLCK divided by 2\r
+ * @arg ADC_JitterOff_PCLKDiv4: Remove jitter when ADC is clocked by PLCK divided by 4\r
+ * @param NewState: new state of the ADCx jitter. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_JITTEROFF(ADC_JitterOff));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Disable Jitter */\r
+ ADCx->CFGR2 |= (uint32_t)ADC_JitterOff;\r
+ }\r
+ else\r
+ {\r
+ /* Enable Jitter */\r
+ ADCx->CFGR2 &= (uint32_t)(~ADC_JitterOff);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group2 Power saving functions\r
+ * @brief Power saving functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Power saving functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to reduce power consumption.\r
+ [..] The two function must be combined to get the maximal benefits:\r
+ When the ADC frequency is higher than the CPU one, it is recommended to \r
+ (#) Enable the Auto Delayed Conversion mode : \r
+ ==> using ADC_AutoDelayConversionCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+ (#) Enable the power off in Delay phases :\r
+ ==> using ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the ADC Power Off.\r
+ * @note ADC power-on and power-off can be managed by hardware to cut the \r
+ * consumption when the ADC is not converting. \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @note The ADC can be powered down: \r
+ * - During the Auto delay phase \r
+ * => The ADC is powered on again at the end of the delay (until the \r
+ * previous data is read from the ADC data register). \r
+ * - During the ADC is waiting for a trigger event \r
+ * => The ADC is powered up at the next trigger event (when the \r
+ * conversion is started).\r
+ * @param NewState: new state of the ADCx power Off. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the ADC Automatic Power-Off */\r
+ ADCx->CFGR1 |= ADC_CFGR1_AUTOFF;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the ADC Automatic Power-Off */\r
+ ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AUTOFF;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Auto delayed conversion mode.\r
+ * @note When the CPU clock is not fast enough to manage the data rate, a \r
+ * Hardware delay can be introduced between ADC conversions to reduce \r
+ * this data rate. \r
+ * @note The Hardware delay is inserted after :\r
+ * - after each conversions and until the previous data is read from the \r
+ * ADC data register\r
+ * @note This is a way to automatically adapt the speed of the ADC to the speed \r
+ * of the system which will read the data.\r
+ * @note Any hardware triggers wich occur while a conversion is on going or \r
+ * while the automatic Delay is applied are ignored \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the ADCx Auto-Delay.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_AutoDelayConversionCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the ADC Automatic Delayed conversion */\r
+ ADCx->CFGR1 |= ADC_CFGR1_AUTDLY;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the ADC Automatic Delayed conversion */\r
+ ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AUTDLY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group3 Analog Watchdog configuration functions\r
+ * @brief Analog Watchdog configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Analog Watchdog configuration functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to configure the Analog Watchdog\r
+ (AWD) feature in the ADC.\r
+ [..] A typical configuration Analog Watchdog is done following these steps :\r
+ (#) the ADC guarded channel(s) is (are) selected using the \r
+ ADC_AnalogWatchdogSingleChannelConfig() function.\r
+ (#) The Analog watchdog lower and higher threshold are configured using the \r
+ ADC_AnalogWatchdogThresholdsConfig() function.\r
+ (#) The Analog watchdog is enabled and configured to enable the check, on one\r
+ or more channels, using the ADC_AnalogWatchdogCmd() function.\r
+ (#) Enable the analog watchdog on the selected channel using\r
+ ADC_AnalogWatchdogSingleChannelCmd() function\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the analog watchdog \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the ADCx Analog Watchdog.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the ADC Analog Watchdog */\r
+ ADCx->CFGR1 |= ADC_CFGR1_AWDEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the ADC Analog Watchdog */\r
+ ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDEN;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the high and low thresholds of the analog watchdog. \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param HighThreshold: the ADC analog watchdog High threshold value.\r
+ * This parameter must be a 12bit value.\r
+ * @param LowThreshold: the ADC analog watchdog Low threshold value.\r
+ * This parameter must be a 12bit value.\r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,\r
+ uint16_t LowThreshold)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_THRESHOLD(HighThreshold));\r
+ assert_param(IS_ADC_THRESHOLD(LowThreshold));\r
+\r
+ /* Set the ADCx high and low threshold */\r
+ ADCx->TR = LowThreshold | ((uint32_t)HighThreshold << 16);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configures the analog watchdog guarded single channel\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_AnalogWatchdog_Channel: the ADC channel to configure for the analog watchdog.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_AnalogWatchdog_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_17: ADC Channel17 selected\r
+ * @arg ADC_AnalogWatchdog_Channel_18: ADC Channel18 selected\r
+ * @note The channel selected on the AWDCH must be also set into the CHSELR \r
+ * register \r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_ANALOG_WATCHDOG_CHANNEL(ADC_AnalogWatchdog_Channel));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CFGR1;\r
+\r
+ /* Clear the Analog watchdog channel select bits */\r
+ tmpreg &= ~ADC_CFGR1_AWDCH;\r
+\r
+ /* Set the Analog watchdog channel */\r
+ tmpreg |= ADC_AnalogWatchdog_Channel;\r
+\r
+ /* Store the new register value */\r
+ ADCx->CFGR1 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the ADC Analog Watchdog Single Channel.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the ADCx ADC Analog Watchdog Single Channel.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the ADC Analog Watchdog Single Channel */\r
+ ADCx->CFGR1 |= ADC_CFGR1_AWDSGL;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the ADC Analog Watchdog Single Channel */\r
+ ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDSGL;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group4 Temperature Sensor, Vrefint and Vbat management functions\r
+ * @brief Temperature Sensor, Vrefint and Vbat management functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Temperature Sensor, Vrefint and Vbat management function #####\r
+ ===============================================================================\r
+ [..] This section provides a function allowing to enable/disable the internal \r
+ connections between the ADC and the Temperature Sensor, the Vrefint and\r
+ Vbat source.\r
+ \r
+ [..] A typical configuration to get the Temperature sensor, Vrefint and Vbat channels \r
+ voltages is done following these steps :\r
+ (#) Enable the internal connection of Temperature sensor, Vrefint or Vbat sources \r
+ with the ADC channels using ADC_TempSensorCmd(), ADC_VrefintCmd() or ADC_VbatCmd()\r
+ functions. \r
+ (#) select the ADC_Channel_16(Temperature sensor), ADC_Channel_17(Vrefint)\r
+ or ADC_Channel_18(Voltage battery) using ADC_ChannelConfig() function \r
+ (#) Get the voltage values, using ADC_GetConversionValue() function\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the temperature sensor channel.\r
+ * @param NewState: new state of the temperature sensor input channel.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_TempSensorCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the temperature sensor channel*/\r
+ ADC->CCR |= (uint32_t)ADC_CCR_TSEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the temperature sensor channel*/\r
+ ADC->CCR &= (uint32_t)(~ADC_CCR_TSEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Vrefint channel.\r
+ * @param NewState: new state of the Vref input channel.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_VrefintCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Vrefint channel*/\r
+ ADC->CCR |= (uint32_t)ADC_CCR_VREFEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Vrefint channel*/\r
+ ADC->CCR &= (uint32_t)(~ADC_CCR_VREFEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Vbat channel.\r
+ * @param NewState: new state of the Vbat input channel.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_VbatCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Vbat channel*/\r
+ ADC->CCR |= (uint32_t)ADC_CCR_VBATEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Vbat channel*/\r
+ ADC->CCR &= (uint32_t)(~ADC_CCR_VBATEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group5 Channels Configuration functions\r
+ * @brief Channels Configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Channels Configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to manage the ADC channels,\r
+ it is composed of 3 sub sections :\r
+ (#) Configuration and management functions for ADC channels: This subsection \r
+ provides functions allowing to configure the ADC channels : \r
+ (++) Select the ADC channels\r
+ (++) Activate ADC Calibration\r
+ (++) Activate the Overrun Mode.\r
+ (++) Activate the Discontinuous Mode \r
+ (++) Activate the Continuous Mode.\r
+ (++) Configure the sampling time for each channel\r
+ (++) Select the conversion Trigger and Edge for ADC channels\r
+ (++) Select the scan direction.\r
+ -@@- Please Note that the following features for ADC channels are configurated\r
+ using the ADC_Init() function : \r
+ (+@@) Activate the Continuous Mode (can be also activated by ADC_OverrunModeCmd().\r
+ (+@@) Select the conversion Trigger and Edge for ADC channels\r
+ (+@@) Select the scan direction.\r
+ (#) Control the ADC peripheral : This subsection permits to command the ADC:\r
+ (++) Stop or discard an on-going conversion (ADSTP command)\r
+ (++) Start the ADC conversion .\r
+ (#) Get the conversion data: This subsection provides an important function in \r
+ the ADC peripheral since it returns the converted data of the current \r
+ ADC channel. When the Conversion value is read, the EOC Flag is \r
+ automatically cleared.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures for the selected ADC and its sampling time.\r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @arg ADC_Channel_18: ADC Channel18 selected \r
+ * @param ADC_SampleTime: The sample time value to be set for the selected \r
+ * channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_SampleTime_1_5Cycles: Sample time equal to 1.5 cycles \r
+ * @arg ADC_SampleTime_7_5Cycles: Sample time equal to 7.5 cycles\r
+ * @arg ADC_SampleTime_13_5Cycles: Sample time equal to 13.5 cycles\r
+ * @arg ADC_SampleTime_28_5Cycles: Sample time equal to 28.5 cycles\r
+ * @arg ADC_SampleTime_41_5Cycles: Sample time equal to 41.5 cycles\r
+ * @arg ADC_SampleTime_55_5Cycles: Sample time equal to 55.5 cycles\r
+ * @arg ADC_SampleTime_71_5Cycles: Sample time equal to 71.5 cycles\r
+ * @arg ADC_SampleTime_239_5Cycles: Sample time equal to 239.5 cycles\r
+ * @retval None\r
+ */\r
+void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
+\r
+ /* Configure the ADC Channel */\r
+ ADCx->CHSELR |= (uint32_t)ADC_Channel;\r
+\r
+ /* Clear the Sampling time Selection bits */\r
+ tmpreg &= ~ADC_SMPR1_SMPR;\r
+\r
+ /* Set the ADC Sampling Time register */\r
+ tmpreg |= (uint32_t)ADC_SampleTime;\r
+\r
+ /* Configure the ADC Sample time register */\r
+ ADCx->SMPR = tmpreg ;\r
+}\r
+\r
+/**\r
+ * @brief Enable the Continuous mode for the selected ADCx channels.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the Continuous mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note It is not possible to have both discontinuous mode and continuous mode\r
+ * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves \r
+ * as if continuous mode was disabled\r
+ * @retval None\r
+ */\r
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Continuous mode*/\r
+ ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_CONT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Continuous mode */\r
+ ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_CONT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable the discontinuous mode for the selected ADC channels.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the discontinuous mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note It is not possible to have both discontinuous mode and continuous mode\r
+ * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves \r
+ * as if continuous mode was disabled\r
+ * @retval None\r
+ */\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Discontinuous mode */\r
+ ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DISCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Discontinuous mode */\r
+ ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DISCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable the Overrun mode for the selected ADC channels.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the Overrun mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Overrun mode */\r
+ ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_OVRMOD;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Overrun mode */\r
+ ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_OVRMOD);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Active the Calibration operation for the selected ADC.\r
+ * @note The Calibration can be initiated only when ADC is still in the \r
+ * reset configuration (ADEN must be equal to 0).\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval ADC Calibration factor \r
+ */\r
+uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx)\r
+{\r
+ uint32_t tmpreg = 0, calibrationcounter = 0, calibrationstatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ \r
+ /* Set the ADC calibartion */\r
+ ADCx->CR |= (uint32_t)ADC_CR_ADCAL;\r
+ \r
+ /* Wait until no ADC calibration is completed */\r
+ do\r
+ {\r
+ calibrationstatus = ADCx->CR & ADC_CR_ADCAL;\r
+ calibrationcounter++; \r
+ } while((calibrationcounter != CALIBRATION_TIMEOUT) && (calibrationstatus != 0x00));\r
+ \r
+ if((uint32_t)(ADCx->CR & ADC_CR_ADCAL) == RESET)\r
+ {\r
+ /*Get the calibration factor from the ADC data register */\r
+ tmpreg = ADCx->DR;\r
+ }\r
+ else\r
+ {\r
+ /* Error factor */\r
+ tmpreg = 0x00000000;\r
+ }\r
+ return tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Stop the on going conversions for the selected ADC.\r
+ * @note When ADSTP is set, any on going conversion is aborted, and the ADC \r
+ * data register is not updated with current conversion. \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_StopOfConversion(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ \r
+ ADCx->CR |= (uint32_t)ADC_CR_ADSTP;\r
+}\r
+\r
+/**\r
+ * @brief Start Conversion for the selected ADC channels.\r
+ * @note In continuous mode, ADSTART is not cleared by hardware with the \r
+ * assertion of EOS because the sequence is automatic relaunched\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_StartOfConversion(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ \r
+ ADCx->CR |= (uint32_t)ADC_CR_ADSTART;\r
+}\r
+\r
+/**\r
+ * @brief Returns the last ADCx conversion result data for ADC channel. \r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @retval The Data conversion value.\r
+ */\r
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ /* Return the selected ADC conversion value */\r
+ return (uint16_t) ADCx->DR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group6 DMA Configuration functions\r
+ * @brief Regular Channels DMA Configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### DMA Configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to configure the DMA for ADC hannels.\r
+ Since converted channel values are stored into a unique data register, \r
+ it is useful to use DMA for conversion of more than one channel. This \r
+ avoids the loss of the data already stored in the ADC Data register. \r
+ When the DMA mode is enabled (using the ADC_DMACmd() function), after each\r
+ conversion of a channel, a DMA request is generated.\r
+ \r
+ [..] Depending on the "DMA disable selection" configuration (using the \r
+ ADC_DMARequestModeConfig() function), at the end of the last DMA \r
+ transfer, two possibilities are allowed:\r
+ (+) No new DMA request is issued to the DMA controller (One Shot Mode) \r
+ (+) Requests can continue to be generated (Circular Mode).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC DMA request.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param NewState: new state of the selected ADC DMA transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC DMA request */\r
+ ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DMAEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC DMA request */\r
+ ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DMAEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode)\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_DMARequestMode: the ADC channel to configure. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_DMAMode_OneShot : DMA One Shot Mode \r
+ * @arg ADC_DMAMode_Circular : DMA Circular Mode \r
+ * @retval None\r
+ */\r
+void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+\r
+ ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_DMACFG;\r
+ ADCx->CFGR1 |= (uint32_t)ADC_DMARequestMode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Group7 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions.\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to configure the ADC Interrupts \r
+ and get the status and clear flags and Interrupts pending bits.\r
+ \r
+ [..] The ADC provide 6 Interrupts sources and 11 Flags which can be divided into \r
+ 3 groups:\r
+\r
+ *** Flags for ADC status ***\r
+ ======================================================\r
+ [..]\r
+ (+)Flags :\r
+ (##) ADC_FLAG_ADRDY : This flag is set after the ADC has been enabled (bit ADEN=1)\r
+ and when the ADC reaches a state where it is ready to accept conversion requests\r
+ (##) ADC_FLAG_ADEN : This flag is set by software to enable the ADC.\r
+ The ADC will be effectively ready to operate once the ADRDY flag has been set.\r
+ (##) ADC_FLAG_ADDIS : This flag is cleared once the ADC is effectively\r
+ disabled.\r
+ (##) ADC_FLAG_ADSTART : This flag is cleared after the execution of\r
+ ADC_StopOfConversion() function, at the same time as the ADSTP bit is\r
+ cleared by hardware\r
+ (##) ADC_FLAG_ADSTP : This flag is cleared by hardware when the conversion\r
+ is effectively discarded and the ADC is ready to accept a new start conversion\r
+ (##) ADC_FLAG_ADCAL : This flag is set once the calibration is complete.\r
+\r
+ (+)Interrupts \r
+ (##) ADC_IT_ADRDY : specifies the interrupt source for ADC ready event.\r
+\r
+ *** Flags and Interrupts for ADC channel conversion ***\r
+ =====================================================\r
+ [..]\r
+ (+)Flags :\r
+ (##) ADC_FLAG_EOC : This flag is set by hardware at the end of each conversion\r
+ of a channel when a new data result is available in the data register\r
+ (##) ADC_FLAG_EOS : This bit is set by hardware at the end of the conversion\r
+ of a sequence of channels selected by ADC_ChannelConfig() function.\r
+ (##) ADC_FLAG_EOSMP : This bit is set by hardware at the end of the sampling phase.\r
+ (##) ADC_FLAG_OVR : This flag is set by hardware when an overrun occurs,\r
+ meaning that a new conversion has complete while the EOC flag was already set.\r
+\r
+ (+)Interrupts :\r
+ (##) ADC_IT_EOC : specifies the interrupt source for end of conversion event.\r
+ (##) ADC_IT_EOS : specifies the interrupt source for end of sequence event.\r
+ (##) ADC_IT_EOSMP : specifies the interrupt source for end of sampling event.\r
+ (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection \r
+ event.\r
+\r
+ *** Flags and Interrupts for the Analog Watchdog ***\r
+ ================================================\r
+ [..]\r
+ (+)Flags :\r
+ (##) ADC_FLAG_AWD: This flag is set by hardware when the converted\r
+ voltage crosses the values programmed thrsholds\r
+\r
+ (+)Interrupts :\r
+ (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog \r
+ event.\r
+ \r
+ [..] The user should identify which mode will be used in his application to \r
+ manage the ADC controller events: Polling mode or Interrupt mode.\r
+ \r
+ [..] In the Polling Mode it is advised to use the following functions:\r
+ (+) ADC_GetFlagStatus() : to check if flags events occur.\r
+ (+) ADC_ClearFlag() : to clear the flags events.\r
+ \r
+ [..] In the Interrupt Mode it is advised to use the following functions:\r
+ (+) ADC_ITConfig() : to enable or disable the interrupt source.\r
+ (+) ADC_GetITStatus() : to check if Interrupt occurs.\r
+ (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit \r
+ (corresponding Flag).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC interrupts.\r
+ * @param ADCx: where x can be 1 to select the ADC peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_ADRDY: ADC ready interrupt \r
+ * @arg ADC_IT_EOSMP: End of sampling interrupt\r
+ * @arg ADC_IT_EOC: End of conversion interrupt \r
+ * @arg ADC_IT_EOS: End of sequence of conversion interrupt\r
+ * @arg ADC_IT_OVR: overrun interrupt\r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt\r
+ * @param NewState: new state of the specified ADC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_ADC_CONFIG_IT(ADC_IT)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC interrupts */\r
+ ADCx->IER |= ADC_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC interrupts */\r
+ ADCx->IER &= (~(uint32_t)ADC_IT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ADC flag is set or not.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_FLAG: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_FLAG_AWD: Analog watchdog flag\r
+ * @arg ADC_FLAG_OVR: Overrun flag \r
+ * @arg ADC_FLAG_EOS: End of Sequence flag\r
+ * @arg ADC_FLAG_EOC: End of conversion flag\r
+ * @arg ADC_FLAG_EOSMP: End of sampling flag\r
+ * @arg ADC_FLAG_ADRDY: ADC Ready flag\r
+ * @arg ADC_FLAG_ADEN: ADC enable flag \r
+ * @arg ADC_FLAG_ADDIS: ADC disable flag \r
+ * @arg ADC_FLAG_ADSTART: ADC start flag \r
+ * @arg ADC_FLAG_ADSTP: ADC stop flag\r
+ * @arg ADC_FLAG_ADCAL: ADC Calibration flag\r
+ * @retval The new state of ADC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_GET_FLAG(ADC_FLAG));\r
+\r
+ if((uint32_t)(ADC_FLAG & 0x01000000))\r
+ {\r
+ tmpreg = ADCx->CR & 0xFEFFFFFF;\r
+ }\r
+ else\r
+ {\r
+ tmpreg = ADCx->ISR;\r
+ }\r
+ \r
+ /* Check the status of the specified ADC flag */\r
+ if ((tmpreg & ADC_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* ADC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ADCx's pending flags.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_FLAG: specifies the flag to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg ADC_FLAG_AWD: Analog watchdog flag\r
+ * @arg ADC_FLAG_EOC: End of conversion flag\r
+ * @arg ADC_FLAG_ADRDY: ADC Ready flag\r
+ * @arg ADC_FLAG_EOSMP: End of sampling flag\r
+ * @arg ADC_FLAG_EOS: End of Sequence flag\r
+ * @arg ADC_FLAG_OVR: Overrun flag \r
+ * @retval None\r
+ */\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));\r
+\r
+ /* Clear the selected ADC flags */\r
+ ADCx->ISR = (uint32_t)ADC_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ADC interrupt has occurred or not.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral\r
+ * @param ADC_IT: specifies the ADC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_ADRDY: ADC ready interrupt \r
+ * @arg ADC_IT_EOSMP: End of sampling interrupt\r
+ * @arg ADC_IT_EOC: End of conversion interrupt \r
+ * @arg ADC_IT_EOS: End of sequence of conversion interrupt\r
+ * @arg ADC_IT_OVR: overrun interrupt\r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt\r
+ * @retval The new state of ADC_IT (SET or RESET).\r
+ */\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_GET_IT(ADC_IT));\r
+\r
+ /* Get the ADC_IT enable bit status */\r
+ enablestatus = (uint32_t)(ADCx->IER & ADC_IT); \r
+\r
+ /* Check the status of the specified ADC interrupt */\r
+ if (((uint32_t)(ADCx->ISR & ADC_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
+ {\r
+ /* ADC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ADCx's interrupt pending bits.\r
+ * @param ADCx: where x can be 1 to select the ADC1 peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_ADRDY: ADC ready interrupt\r
+ * @arg ADC_IT_EOSMP: End of sampling interrupt\r
+ * @arg ADC_IT_EOC: End of conversion interrupt\r
+ * @arg ADC_IT_EOS: End of sequence of conversion interrupt\r
+ * @arg ADC_IT_OVR: overrun interrupt\r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt\r
+ * @retval None\r
+ */\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CLEAR_IT(ADC_IT));\r
+\r
+ /* Clear the selected ADC interrupt pending bits */\r
+ ADCx->ISR = (uint32_t)ADC_IT; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_cec.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Consumer Electronics Control (CEC) peripheral:\r
+ * + Initialization and Configuration\r
+ * + Data transfers functions\r
+ * + Interrupts and flags management\r
+ * \r
+ * @verbatim\r
+ ==============================================================================\r
+ ##### CEC features #####\r
+ ==============================================================================\r
+ [..] This device provides some features:\r
+ (#) Supports HDMI-CEC specification 1.4.\r
+ (#) Supports two source clocks(HSI/244 or LSE).\r
+ (#) Works in stop mode(without APB clock, but with CEC clock 32KHz).\r
+ It can genarate an interrupt in the CEC clock domain that the CPU \r
+ wakes up from the low power mode.\r
+ (#) Configurable Signal Free Time before of transmission start. The \r
+ number of nominal data bit periods waited before transmission can be\r
+ ruled by Hardware or Software.\r
+ (#) Configurable Peripheral Address (multi-addressing configuration).\r
+ (#) Supports listen mode.The CEC Messages addressed to different destination\r
+ can be received without interfering with CEC bus when Listen mode option is enabled.\r
+ (#) Configurable Rx-Tolerance(Standard and Extended tolerance margin).\r
+ (#) Error detection with configurable error bit generation.\r
+ (#) Arbitration lost error in the case of two CEC devices starting at the same time.\r
+\r
+ ##### How to use this driver ##### \r
+ ==============================================================================\r
+ [..] This driver provides functions to configure and program the CEC device,\r
+ follow steps below:\r
+ (#) The source clock can be configured using:\r
+ (++) RCC_CECCLKConfig(RCC_CECCLK_HSI_Div244) for HSI(Default) \r
+ (++) RCC_CECCLKConfig(RCC_CECCLK_LSE) for LSE.\r
+ (#) Enable CEC peripheral clock using RCC_APBPeriphClockCmd(RCC_APBPeriph_CEC, ENABLE).\r
+ (#) Peripherals alternate function.\r
+ (++) Connect the pin to the desired peripherals' Alternate Function (AF) using \r
+ GPIO_PinAFConfig() function.\r
+ (++) Configure the desired pin in alternate function by:\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.\r
+ (++) Select the type open-drain and output speed via GPIO_OType \r
+ and GPIO_Speed members.\r
+ (++) Call GPIO_Init() function.\r
+ (#) Configure the Signal Free Time, Rx Tolerance, Stop reception generation \r
+ and Bit error generation using the CEC_Init() function.\r
+ The function CEC_Init() must be called when the CEC peripheral is disabled.\r
+ (#) Configure the CEC own address by calling the fuction CEC_OwnAddressConfig().\r
+ (#) Optionally, you can configure the Listen mode using the function CEC_ListenModeCmd().\r
+ (#) Enable the NVIC and the corresponding interrupt using the function \r
+ CEC_ITConfig() if you need to use interrupt mode.\r
+ CEC_ITConfig() must be called before enabling the CEC peripheral.\r
+ (#) Enable the CEC using the CEC_Cmd() function.\r
+ (#) Charge the first data byte in the TXDR register using CEC_SendDataByte().\r
+ (#) Enable the transmission of the Byte of a CEC message using CEC_StartOfMessage() \r
+ (#) Transmit single data through the CEC peripheral using CEC_SendDataByte() \r
+ and Receive the last transmitted byte using CEC_ReceiveDataByte().\r
+ (#) Enable the CEC_EndOfMessage() in order to indicate the last byte of the message.\r
+ [..]\r
+ (@) If the listen mode is enabled, Stop reception generation and Bit error generation \r
+ must be in reset state.\r
+ (@) If the CEC message consists of only 1 byte, the function CEC_EndOfMessage()\r
+ must be called before CEC_StartOfMessage().\r
+ \r
+ @endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_cec.h"\r
+#include "stm32f0xx_rcc.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CEC \r
+ * @brief CEC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define BROADCAST_ADDRESS ((uint32_t)0x0000F)\r
+#define CFGR_CLEAR_MASK ((uint32_t)0x7000FE00) /* CFGR register Mask */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup CEC_Private_Functions \r
+ * @{\r
+ */\r
+\r
+/** @defgroup CEC_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to initialize:\r
+ (+) CEC own addresses\r
+ (+) CEC Signal Free Time\r
+ (+) CEC Rx Tolerance\r
+ (+) CEC Stop Reception\r
+ (+) CEC Bit Rising Error\r
+ (+) CEC Long Bit Period Error\r
+ [..] This section provides also a function to configure the CEC peripheral in Listen Mode.\r
+ Messages addressed to different destination can be received when Listen mode is \r
+ enabled without interfering with CEC bus.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the CEC peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CEC_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CEC peripheral according to the specified parameters\r
+ * in the CEC_InitStruct.\r
+ * @note The CEC parameters must be configured before enabling the CEC peripheral.\r
+ * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that contains\r
+ * the configuration information for the specified CEC peripheral.\r
+ * @retval None\r
+ */\r
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_SIGNAL_FREE_TIME(CEC_InitStruct->CEC_SignalFreeTime));\r
+ assert_param(IS_CEC_RX_TOLERANCE(CEC_InitStruct->CEC_RxTolerance));\r
+ assert_param(IS_CEC_STOP_RECEPTION(CEC_InitStruct->CEC_StopReception));\r
+ assert_param(IS_CEC_BIT_RISING_ERROR(CEC_InitStruct->CEC_BitRisingError));\r
+ assert_param(IS_CEC_LONG_BIT_PERIOD_ERROR(CEC_InitStruct->CEC_LongBitPeriodError));\r
+ assert_param(IS_CEC_BDR_NO_GEN_ERROR(CEC_InitStruct->CEC_BRDNoGen));\r
+ assert_param(IS_CEC_SFT_OPTION(CEC_InitStruct->CEC_SFTOption));\r
+\r
+ /* Get the CEC CFGR value */\r
+ tmpreg = CEC->CFGR;\r
+\r
+ /* Clear CFGR bits */\r
+ tmpreg &= CFGR_CLEAR_MASK;\r
+\r
+ /* Configure the CEC peripheral */\r
+ tmpreg |= (CEC_InitStruct->CEC_SignalFreeTime | CEC_InitStruct->CEC_RxTolerance |\r
+ CEC_InitStruct->CEC_StopReception | CEC_InitStruct->CEC_BitRisingError |\r
+ CEC_InitStruct->CEC_LongBitPeriodError| CEC_InitStruct->CEC_BRDNoGen |\r
+ CEC_InitStruct->CEC_SFTOption);\r
+\r
+ /* Write to CEC CFGR register */\r
+ CEC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each CEC_InitStruct member with its default value.\r
+ * @param CEC_InitStruct: pointer to a CEC_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct)\r
+{\r
+ CEC_InitStruct->CEC_SignalFreeTime = CEC_SignalFreeTime_Standard;\r
+ CEC_InitStruct->CEC_RxTolerance = CEC_RxTolerance_Standard;\r
+ CEC_InitStruct->CEC_StopReception = CEC_StopReception_Off;\r
+ CEC_InitStruct->CEC_BitRisingError = CEC_BitRisingError_Off;\r
+ CEC_InitStruct->CEC_LongBitPeriodError = CEC_LongBitPeriodError_Off;\r
+ CEC_InitStruct->CEC_BRDNoGen = CEC_BRDNoGen_Off;\r
+ CEC_InitStruct->CEC_SFTOption = CEC_SFTOption_Off;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the CEC peripheral.\r
+ * @param NewState: new state of the CEC peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void CEC_Cmd(FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the CEC peripheral */\r
+ CEC->CR |= CEC_CR_CECEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the CEC peripheral */\r
+ CEC->CR &= ~CEC_CR_CECEN;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the CEC Listen Mode.\r
+ * @param NewState: new state of the Listen Mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void CEC_ListenModeCmd(FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Listen Mode */\r
+ CEC->CFGR |= CEC_CFGR_LSTN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Listen Mode */\r
+ CEC->CFGR &= ~CEC_CFGR_LSTN;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Defines the Own Address of the CEC device.\r
+ * @param CEC_OwnAddress: The CEC own address.\r
+ * @retval None\r
+ */\r
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)\r
+{\r
+ uint32_t tmp =0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));\r
+ tmp = 1 <<(CEC_OwnAddress + 16);\r
+ /* Set the CEC own address */\r
+ CEC->CFGR |= tmp;\r
+}\r
+\r
+/**\r
+ * @brief Clears the Own Address of the CEC device.\r
+ * @param CEC_OwnAddress: The CEC own address.\r
+ * @retval None\r
+ */\r
+void CEC_OwnAddressClear(void)\r
+{\r
+ /* Set the CEC own address */\r
+ CEC->CFGR = 0x0;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Group2 Data transfers functions\r
+ * @brief Data transfers functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Data transfers functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing the CEC data transfers.The read \r
+ access of the CEC_RXDR register can be done using the CEC_ReceiveData()function \r
+ and returns the Rx buffered value. Whereas a write access to the CEC_TXDR can be \r
+ done using CEC_SendData() function.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmits single data through the CEC peripheral.\r
+ * @param Data: the data to transmit.\r
+ * @retval None\r
+ */\r
+void CEC_SendData(uint8_t Data)\r
+{\r
+ /* Transmit Data */\r
+ CEC->TXDR = Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the CEC peripheral.\r
+ * @param None\r
+ * @retval The received data.\r
+ */\r
+uint8_t CEC_ReceiveData(void)\r
+{\r
+ /* Receive Data */\r
+ return (uint8_t)(CEC->RXDR);\r
+}\r
+\r
+/**\r
+ * @brief Starts a new message.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CEC_StartOfMessage(void)\r
+{\r
+ /* Starts of new message */\r
+ CEC->CR |= CEC_CR_TXSOM; \r
+}\r
+\r
+/**\r
+ * @brief Transmits message with an EOM bit.\r
+ * @param None.\r
+ * @retval None\r
+ */\r
+void CEC_EndOfMessage(void)\r
+{\r
+ /* The data byte will be transmitted with an EOM bit */\r
+ CEC->CR |= CEC_CR_TXEOM;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+*\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions ##### \r
+ ===============================================================================\r
+ [..] This section provides functions allowing to configure the CEC Interrupts\r
+ sources and check or clear the flags or pending bits status.\r
+ [..] The user should identify which mode will be used in his application to manage\r
+ the communication: Polling mode or Interrupt mode.\r
+ \r
+ [..] In polling mode, the CEC can be managed by the following flags:\r
+ (+) CEC_FLAG_TXACKE : to indicate a missing acknowledge in transmission mode.\r
+ (+) CEC_FLAG_TXERR : to indicate an error occurs during transmission mode.\r
+ The initiator detects low impedance in the CEC line.\r
+ (+) CEC_FLAG_TXUDR : to indicate if an underrun error occurs in transmission mode.\r
+ The transmission is enabled while the software has not yet \r
+ loaded any value into the TXDR register.\r
+ (+) CEC_FLAG_TXEND : to indicate the end of successful transmission.\r
+ (+) CEC_FLAG_TXBR : to indicate the next transmission data has to be written to TXDR.\r
+ (+) CEC_FLAG_ARBLST : to indicate arbitration lost in the case of two CEC devices\r
+ starting at the same time.\r
+ (+) CEC_FLAG_RXACKE : to indicate a missing acknowledge in receive mode.\r
+ (+) CEC_FLAG_LBPE : to indicate a long bit period error generated during receive mode.\r
+ (+) CEC_FLAG_SBPE : to indicate a short bit period error generated during receive mode.\r
+ (+) CEC_FLAG_BRE : to indicate a bit rising error generated during receive mode.\r
+ (+) CEC_FLAG_RXOVR : to indicate if an overrun error occur while receiving a CEC message.\r
+ A byte is not yet received while a new byte is stored in the RXDR register.\r
+ (+) CEC_FLAG_RXEND : to indicate the end Of reception\r
+ (+) CEC_FLAG_RXBR : to indicate a new byte has been received from the CEC line and \r
+ stored into the RXDR buffer.\r
+ [..]\r
+ (@)In this Mode, it is advised to use the following functions:\r
+ FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);\r
+ void CEC_ClearFlag(uint16_t CEC_FLAG);\r
+\r
+ [..] In Interrupt mode, the CEC can be managed by the following interrupt sources:\r
+ (+) CEC_IT_TXACKE : to indicate a TX Missing acknowledge \r
+ (+) CEC_IT_TXACKE : to indicate a missing acknowledge in transmission mode.\r
+ (+) CEC_IT_TXERR : to indicate an error occurs during transmission mode.\r
+ The initiator detects low impedance in the CEC line.\r
+ (+) CEC_IT_TXUDR : to indicate if an underrun error occurs in transmission mode.\r
+ The transmission is enabled while the software has not yet \r
+ loaded any value into the TXDR register.\r
+ (+) CEC_IT_TXEND : to indicate the end of successful transmission.\r
+ (+) CEC_IT_TXBR : to indicate the next transmission data has to be written to TXDR register.\r
+ (+) CEC_IT_ARBLST : to indicate arbitration lost in the case of two CEC devices\r
+ starting at the same time.\r
+ (+) CEC_IT_RXACKE : to indicate a missing acknowledge in receive mode.\r
+ (+) CEC_IT_LBPE : to indicate a long bit period error generated during receive mode.\r
+ (+) CEC_IT_SBPE : to indicate a short bit period error generated during receive mode.\r
+ (+) CEC_IT_BRE : to indicate a bit rising error generated during receive mode.\r
+ (+) CEC_IT_RXOVR : to indicate if an overrun error occur while receiving a CEC message.\r
+ A byte is not yet received while a new byte is stored in the RXDR register.\r
+ (+) CEC_IT_RXEND : to indicate the end Of reception\r
+ (+) CEC_IT_RXBR : to indicate a new byte has been received from the CEC line and \r
+ stored into the RXDR buffer.\r
+ [..]\r
+ (@)In this Mode it is advised to use the following functions:\r
+ void CEC_ITConfig( uint16_t CEC_IT, FunctionalState NewState);\r
+ ITStatus CEC_GetITStatus(uint16_t CEC_IT);\r
+ void CEC_ClearITPendingBit(uint16_t CEC_IT);\r
+ \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the selected CEC interrupts.\r
+ * @param CEC_IT: specifies the CEC interrupt source to be enabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error\r
+ * @arg CEC_IT_TXERR: Tx Error.\r
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun.\r
+ * @arg CEC_IT_TXEND: End of Transmission (successful transmission of the last byte).\r
+ * @arg CEC_IT_TXBR: Tx-Byte Request.\r
+ * @arg CEC_IT_ARBLST: Arbitration Lost\r
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge\r
+ * @arg CEC_IT_LBPE: Rx Long period Error\r
+ * @arg CEC_IT_SBPE: Rx Short period Error\r
+ * @arg CEC_IT_BRE: Rx Bit Rising Error\r
+ * @arg CEC_IT_RXOVR: Rx Overrun.\r
+ * @arg CEC_IT_RXEND: End Of Reception\r
+ * @arg CEC_IT_RXBR: Rx-Byte Received\r
+ * @param NewState: new state of the selected CEC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_CEC_IT(CEC_IT));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected CEC interrupt */\r
+ CEC->IER |= CEC_IT;\r
+ }\r
+ else\r
+ {\r
+ CEC_IT =~CEC_IT;\r
+ /* Disable the selected CEC interrupt */\r
+ CEC->IER &= CEC_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets the CEC flag status.\r
+ * @param CEC_FLAG: specifies the CEC flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error\r
+ * @arg CEC_FLAG_TXERR: Tx Error.\r
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.\r
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).\r
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request.\r
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost\r
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge \r
+ * @arg CEC_FLAG_LBPE: Rx Long period Error\r
+ * @arg CEC_FLAG_SBPE: Rx Short period Error\r
+ * @arg CEC_FLAG_BRE: Rx Bit Rissing Error\r
+ * @arg CEC_FLAG_RXOVR: Rx Overrun.\r
+ * @arg CEC_FLAG_RXEND: End Of Reception.\r
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.\r
+ * @retval The new state of CEC_FLAG (SET or RESET)\r
+ */\r
+FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG) \r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ assert_param(IS_CEC_GET_FLAG(CEC_FLAG));\r
+ \r
+ /* Check the status of the specified CEC flag */\r
+ if ((CEC->ISR & CEC_FLAG) != (uint16_t)RESET)\r
+ {\r
+ /* CEC flag is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CEC flag is reset */\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the CEC flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the CEC's pending flags.\r
+ * @param CEC_FLAG: specifies the flag to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error\r
+ * @arg CEC_FLAG_TXERR: Tx Error\r
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun\r
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).\r
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request\r
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost\r
+ * @arg CEC_FLAG_RXACKE: Rx Missing Acknowledge \r
+ * @arg CEC_FLAG_LBPE: Rx Long period Error\r
+ * @arg CEC_FLAG_SBPE: Rx Short period Error\r
+ * @arg CEC_FLAG_BRE: Rx Bit Rising Error\r
+ * @arg CEC_FLAG_RXOVR: Rx Overrun\r
+ * @arg CEC_FLAG_RXEND: End Of Reception\r
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received\r
+ * @retval None\r
+ */\r
+void CEC_ClearFlag(uint32_t CEC_FLAG)\r
+{\r
+ assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));\r
+\r
+ /* Clear the selected CEC flag */\r
+ CEC->ISR = CEC_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified CEC interrupt has occurred or not.\r
+ * @param CEC_IT: specifies the CEC interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error\r
+ * @arg CEC_IT_TXERR: Tx Error.\r
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun.\r
+ * @arg CEC_IT_TXEND: End of transmission (successful transmission of the last byte).\r
+ * @arg CEC_IT_TXBR: Tx-Byte Request.\r
+ * @arg CEC_IT_ARBLST: Arbitration Lost.\r
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge.\r
+ * @arg CEC_IT_LBPE: Rx Long period Error.\r
+ * @arg CEC_IT_SBPE: Rx Short period Error.\r
+ * @arg CEC_IT_BRE: Rx Bit Rising Error.\r
+ * @arg CEC_IT_RXOVR: Rx Overrun.\r
+ * @arg CEC_IT_RXEND: End Of Reception.\r
+ * @arg CEC_IT_RXBR: Rx-Byte Received \r
+ * @retval The new state of CEC_IT (SET or RESET).\r
+ */\r
+ITStatus CEC_GetITStatus(uint16_t CEC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_GET_IT(CEC_IT));\r
+\r
+ /* Get the CEC IT enable bit status */\r
+ enablestatus = (CEC->IER & CEC_IT);\r
+\r
+ /* Check the status of the specified CEC interrupt */\r
+ if (((CEC->ISR & CEC_IT) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* CEC interrupt is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CEC interrupt is reset */\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the CEC interrupt status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the CEC's interrupt pending bits.\r
+ * @param CEC_IT: specifies the CEC interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error\r
+ * @arg CEC_IT_TXERR: Tx Error\r
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun\r
+ * @arg CEC_IT_TXEND: End of Transmission\r
+ * @arg CEC_IT_TXBR: Tx-Byte Request\r
+ * @arg CEC_IT_ARBLST: Arbitration Lost\r
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge\r
+ * @arg CEC_IT_LBPE: Rx Long period Error\r
+ * @arg CEC_IT_SBPE: Rx Short period Error\r
+ * @arg CEC_IT_BRE: Rx Bit Rising Error\r
+ * @arg CEC_IT_RXOVR: Rx Overrun\r
+ * @arg CEC_IT_RXEND: End Of Reception\r
+ * @arg CEC_IT_RXBR: Rx-Byte Received\r
+ * @retval None\r
+ */\r
+void CEC_ClearITPendingBit(uint16_t CEC_IT)\r
+{\r
+ assert_param(IS_CEC_IT(CEC_IT));\r
+\r
+ /* Clear the selected CEC interrupt pending bits */\r
+ CEC->ISR = CEC_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_comp.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the comparators (COMP1 and COMP2) peripheral: \r
+ * + Comparators configuration\r
+ * + Window mode control\r
+ *\r
+ * @verbatim\r
+ *\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..] \r
+ \r
+ The device integrates two analog comparators COMP1 and COMP2:\r
+ (+) The non inverting input is set to PA1 for COMP1 and to PA3\r
+ for COMP2.\r
+ \r
+ (+) The inverting input can be selected among: DAC_OUT1, \r
+ 1/4 VREFINT, 1/2 VERFINT, 3/4 VREFINT, VREFINT,\r
+ I/O (PA0 for COMP1 and PA2 for COMP2)\r
+ \r
+ (+) The COMP output is internally is available using COMP_GetOutputLevel()\r
+ and can be set on GPIO pins: PA0, PA6, PA11 for COMP1\r
+ and PA2, PA7, PA12 for COMP2\r
+ \r
+ (+) The COMP output can be redirected to embedded timers (TIM1, TIM2\r
+ and TIM3)\r
+ \r
+ (+) The two comparators COMP1 and COMP2 can be combined in window\r
+ mode and only COMP1 non inverting (PA1) can be used as non-\r
+ inverting input.\r
+ \r
+ (+) The two comparators COMP1 and COMP2 have interrupt capability \r
+ with wake-up from Sleep and Stop modes (through the EXTI controller).\r
+ COMP1 and COMP2 outputs are internally connected to EXTI Line 21\r
+ and EXTI Line 22 respectively.\r
+ \r
+\r
+ ##### How to configure the comparator #####\r
+ ===============================================================================\r
+ [..] \r
+ This driver provides functions to configure and program the Comparators \r
+ of all STM32F0xx devices.\r
+ \r
+ [..] To use the comparator, perform the following steps:\r
+ \r
+ (#) Enable the SYSCFG APB clock to get write access to comparator\r
+ register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+ \r
+ (#) Configure the comparator input in analog mode using GPIO_Init()\r
+ \r
+ (#) Configure the comparator output in alternate function mode\r
+ using GPIO_Init() and use GPIO_PinAFConfig() function to map the\r
+ comparator output to the GPIO pin\r
+ \r
+ (#) Configure the comparator using COMP_Init() function:\r
+ (++) Select the inverting input\r
+ (++) Select the output polarity \r
+ (++) Select the output redirection\r
+ (++) Select the hysteresis level\r
+ (++) Select the power mode\r
+ \r
+ (#) Enable the comparator using COMP_Cmd() function\r
+ \r
+ (#) If required enable the COMP interrupt by configuring and enabling\r
+ EXTI line in Interrupt mode and selecting the desired sensitivity\r
+ level using EXTI_Init() function. After that enable the comparator\r
+ interrupt vector using NVIC_Init() function.\r
+ \r
+ @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_comp.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup COMP \r
+ * @brief COMP driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* CSR register Mask */\r
+#define COMP_CSR_CLEAR_MASK ((uint32_t)0x00003FFE)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup COMP_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup COMP_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Deinitializes COMP peripheral registers to their default reset values.\r
+ * @note Deinitialization can't be performed if the COMP configuration is locked.\r
+ * To unlock the configuration, perform a system reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void COMP_DeInit(void)\r
+{\r
+ COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP_CSR register to reset value */\r
+}\r
+\r
+/**\r
+ * @brief Initializes the COMP peripheral according to the specified parameters\r
+ * in COMP_InitStruct\r
+ * @note If the selected comparator is locked, initialization can't be performed.\r
+ * To unlock the configuration, perform a system reset.\r
+ * @note By default, PA1 is selected as COMP1 non inverting input.\r
+ * To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()\r
+ * @param COMP_Selection: the selected comparator. \r
+ * This parameter can be one of the following values:\r
+ * @arg COMP_Selection_COMP1: COMP1 selected\r
+ * @arg COMP_Selection_COMP2: COMP2 selected\r
+ * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains \r
+ * the configuration information for the specified COMP peripheral.\r
+ *\r
+ * @retval None\r
+ */\r
+void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));\r
+ assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));\r
+ assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));\r
+ assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol));\r
+ assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));\r
+ assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));\r
+\r
+ /*!< Get the COMP_CSR register value */\r
+ tmpreg = COMP->CSR;\r
+\r
+ /*!< Clear the COMP1SW1, COMPx_IN_SEL, COMPx_OUT_TIM_SEL, COMPx_POL, COMPx_HYST and COMPx_PWR_MODE bits */ \r
+ tmpreg &= (uint32_t) ~(COMP_CSR_CLEAR_MASK<<COMP_Selection);\r
+\r
+ /*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */\r
+ /*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */\r
+ /*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */\r
+ /*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */\r
+ /*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */\r
+ /*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */ \r
+ tmpreg |= (uint32_t)((COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_Output |\r
+ COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_Hysteresis |\r
+ COMP_InitStruct->COMP_Mode)<<COMP_Selection);\r
+\r
+ /*!< Write to COMP_CSR register */\r
+ COMP->CSR = tmpreg; \r
+}\r
+\r
+/**\r
+ * @brief Fills each COMP_InitStruct member with its default value.\r
+ * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct)\r
+{\r
+ COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT;\r
+ COMP_InitStruct->COMP_Output = COMP_Output_None;\r
+ COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted;\r
+ COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;\r
+ COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower;\r
+}\r
+\r
+/**\r
+ * @brief Enable or disable the COMP peripheral.\r
+ * @note If the selected comparator is locked, enable/disable can't be performed.\r
+ * To unlock the configuration, perform a system reset.\r
+ * @param COMP_Selection: the selected comparator.\r
+ * This parameter can be one of the following values:\r
+ * @arg COMP_Selection_COMP1: COMP1 selected\r
+ * @arg COMP_Selection_COMP2: COMP2 selected\r
+ * @param NewState: new state of the COMP peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When enabled, the comparator compares the non inverting input with \r
+ * the inverting input and the comparison result is available\r
+ * on comparator output.\r
+ * @note When disabled, the comparator doesn't perform comparison and the \r
+ * output level is low.\r
+ * @retval None\r
+ */\r
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected COMP peripheral */\r
+ COMP->CSR |= (uint32_t) (1<<COMP_Selection);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected COMP peripheral */\r
+ COMP->CSR &= (uint32_t)(~((uint32_t)1<<COMP_Selection));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Close or Open the SW1 switch.\r
+ * @note This switch is solely intended to redirect signals onto high\r
+ * impedance input, such as COMP1 non-inverting input (highly resistive switch)\r
+ * @param NewState: New state of the analog switch.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @note When enabled, the SW1 is closed; PA1 is connected to PA4\r
+ * @note When disabled, the SW1 switch is open; PA1 is disconnected from PA4\r
+ * @retval None\r
+ */\r
+void COMP_SwitchCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Close SW1 switch */\r
+ COMP->CSR |= (uint32_t) (COMP_CSR_COMP1SW1);\r
+ }\r
+ else\r
+ {\r
+ /* Open SW1 switch */\r
+ COMP->CSR &= (uint32_t)(~COMP_CSR_COMP1SW1);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Return the output level (high or low) of the selected comparator. \r
+ * @note The output level depends on the selected polarity.\r
+ * If the polarity is not inverted:\r
+ * @note -Comparator output is low when the non-inverting input is at a lower\r
+ * voltage than the inverting input\r
+ * @note -Comparator output is high when the non-inverting input is at a higher\r
+ * voltage than the inverting input\r
+ * @note If the polarity is inverted:\r
+ * @note -Comparator output is high when the non-inverting input is at a lower\r
+ * voltage than the inverting input\r
+ * @note -Comparator output is low when the non-inverting input is at a higher\r
+ * voltage than the inverting input\r
+ * @param COMP_Selection: the selected comparator. \r
+ * This parameter can be one of the following values:\r
+ * @arg COMP_Selection_COMP1: COMP1 selected\r
+ * @arg COMP_Selection_COMP2: COMP2 selected \r
+ * @retval Returns the selected comparator output level: low or high.\r
+ * \r
+ */\r
+uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection)\r
+{\r
+ uint32_t compout = 0x0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));\r
+\r
+ /* Check if selected comparator output is high */\r
+ if ((COMP->CSR & (COMP_CSR_COMP1OUT<<COMP_Selection)) != 0)\r
+ {\r
+ compout = COMP_OutputLevel_High;\r
+ }\r
+ else\r
+ {\r
+ compout = COMP_OutputLevel_Low;\r
+ }\r
+\r
+ /* Return the comparator output level */\r
+ return (uint32_t)(compout);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup COMP_Group2 Window mode control function\r
+ * @brief Window mode control function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Window mode control function #####\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the window mode.\r
+ * In window mode, COMP1 and COMP2 non inverting inputs are connected\r
+ * together and only COMP1 non inverting input (PA1) can be used.\r
+ * param NewState: new state of the window mode.\r
+ * This parameter can be :\r
+ * @arg ENABLE: COMP1 and COMP2 non inverting inputs are connected together.\r
+ * @arg DISABLE: OMP1 and COMP2 non inverting inputs are disconnected.\r
+ * @retval None\r
+ */\r
+void COMP_WindowCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the window mode */\r
+ COMP->CSR |= (uint32_t) COMP_CSR_WNDWEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the window mode */\r
+ COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup COMP_Group3 COMP configuration locking function\r
+ * @brief COMP1 and COMP2 configuration locking function\r
+ * COMP1 and COMP2 configuration can be locked each separately.\r
+ * Unlocking is performed by system reset.\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Configuration Lock function #####\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Lock the selected comparator (COMP1/COMP2) configuration.\r
+ * @note Locking the configuration means that all control bits are read-only.\r
+ * To unlock the comparator configuration, perform a system reset.\r
+ * @param COMP_Selection: selects the comparator to be locked \r
+ * This parameter can be a value of the following values:\r
+ * @arg COMP_Selection_COMP1: COMP1 configuration is locked.\r
+ * @arg COMP_Selection_COMP2: COMP2 configuration is locked. \r
+ * @retval None\r
+ */\r
+void COMP_LockConfig(uint32_t COMP_Selection)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));\r
+\r
+ /* Set the lock bit corresponding to selected comparator */\r
+ COMP->CSR |= (uint32_t) (COMP_CSR_COMP1LOCK<<COMP_Selection);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_crc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of CRC computation unit peripheral:\r
+ * + Configuration of the CRC computation unit\r
+ * + CRC computation of one/many 32-bit data\r
+ * + CRC Independent register (IDR) access\r
+ *\r
+ * @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ \r
+ (+) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE)\r
+ function\r
+ (+) If required, select the reverse operation on input data \r
+ using CRC_ReverseInputDataSelect() \r
+ (+) If required, enable the reverse operation on output data\r
+ using CRC_ReverseOutputDataCmd(Enable)\r
+ (+) use CRC_CalcCRC() function to compute the CRC of a 32-bit data\r
+ or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit \r
+ data buffer\r
+ (@) To compute the CRC of a new data use CRC_ResetDR() to reset\r
+ the CRC computation unit before starting the computation\r
+ otherwise you can get wrong CRC values.\r
+ \r
+ @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_crc.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC \r
+ * @brief CRC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup CRC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions\r
+ * @brief Configuration of the CRC computation unit functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### CRC configuration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes CRC peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CRC_DeInit(void)\r
+{\r
+ /* Set DR register to reset value */\r
+ CRC->DR = 0xFFFFFFFF;\r
+ /* Reset IDR register */\r
+ CRC->IDR = 0x00;\r
+ /* Set INIT register to reset value */\r
+ CRC->INIT = 0xFFFFFFFF;\r
+ /* Reset the CRC calculation unit */\r
+ CRC->CR = CRC_CR_RESET;\r
+}\r
+\r
+/**\r
+ * @brief Resets the CRC calculation unit and sets INIT register content in DR register.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CRC_ResetDR(void)\r
+{\r
+ /* Reset CRC generator */\r
+ CRC->CR = CRC_CR_RESET;\r
+}\r
+\r
+/**\r
+ * @brief Selects the reverse operation to be performed on input data.\r
+ * @param CRC_ReverseInputData: Specifies the reverse operation on input data.\r
+ * This parameter can be:\r
+ * @arg CRC_ReverseInputData_No: No reverse operation is performed\r
+ * @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits\r
+ * @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits\r
+ * @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits\r
+ * @retval None\r
+ */\r
+void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData)\r
+{\r
+ uint32_t tmpcr = 0;\r
+\r
+ /* Check the parameter */\r
+ assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData));\r
+\r
+ /* Get CR register value */\r
+ tmpcr = CRC->CR;\r
+\r
+ /* Reset REV_IN bits */\r
+ tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN);\r
+ /* Set the reverse operation */\r
+ tmpcr |= (uint32_t)CRC_ReverseInputData;\r
+\r
+ /* Write to CR register */\r
+ CRC->CR = (uint32_t)tmpcr;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disable the reverse operation on output data.\r
+ * The reverse operation on output data is performed on 32-bit.\r
+ * @param NewState: new state of the reverse operation on output data.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void CRC_ReverseOutputDataCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable reverse operation on output data */\r
+ CRC->CR |= CRC_CR_REV_OUT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable reverse operation on output data */\r
+ CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the INIT register.\r
+ * @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register\r
+ * @param CRC_InitValue: Programmable initial CRC value\r
+ * @retval None\r
+ */\r
+void CRC_SetInitRegister(uint32_t CRC_InitValue)\r
+{\r
+ CRC->INIT = CRC_InitValue;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions\r
+ * @brief CRC computation of one/many 32-bit data functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### CRC computation functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).\r
+ * @param CRC_Data: data word(32-bit) to compute its CRC\r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_CalcCRC(uint32_t CRC_Data)\r
+{\r
+ CRC->DR = CRC_Data;\r
+ \r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).\r
+ * @param pBuffer: pointer to the buffer containing the data to be computed\r
+ * @param BufferLength: length of the buffer to be computed\r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)\r
+{\r
+ uint32_t index = 0;\r
+ \r
+ for(index = 0; index < BufferLength; index++)\r
+ {\r
+ CRC->DR = pBuffer[index];\r
+ }\r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Returns the current CRC value.\r
+ * @param None\r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_GetCRC(void)\r
+{\r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions\r
+ * @brief CRC Independent Register (IDR) access (write/read) functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### CRC Independent Register (IDR) access functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Stores an 8-bit data in the Independent Data(ID) register.\r
+ * @param CRC_IDValue: 8-bit value to be stored in the ID register \r
+ * @retval None\r
+ */\r
+void CRC_SetIDRegister(uint8_t CRC_IDValue)\r
+{\r
+ CRC->IDR = CRC_IDValue;\r
+}\r
+\r
+/**\r
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register\r
+ * @param None\r
+ * @retval 8-bit value of the ID register \r
+ */\r
+uint8_t CRC_GetIDRegister(void)\r
+{\r
+ return (CRC->IDR);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_dac.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Digital-to-Analog Converter (DAC) peripheral:\r
+ * + DAC channel configuration: trigger, output buffer, data format\r
+ * + DMA management\r
+ * + Interrupts and flags management\r
+ *\r
+ * @verbatim\r
+ *\r
+ ===============================================================================\r
+ ##### DAC Peripheral features #####\r
+ ===============================================================================\r
+ [..] The device integrates one 12-bit Digital Analog Converters refered as\r
+ DAC channel1 with DAC_OUT1 (PA4) as output\r
+ \r
+ [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None\r
+ and DAC_OUT1 is available once writing to DHRx register using \r
+ DAC_SetChannel1Data().\r
+ \r
+ [..] Digital to Analog conversion can be triggered by:\r
+ (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.\r
+ The used pin (GPIOx_Pin9) must be configured in input mode.\r
+ \r
+ (#) Timers TRGO: TIM2, TIM3, TIM6 and TIM15 \r
+ (DAC_Trigger_T2_TRGO, DAC_Trigger_T3_TRGO...)\r
+ The timer TRGO event should be selected using TIM_SelectOutputTrigger()\r
+ \r
+ (#) Software using DAC_Trigger_Software\r
+ \r
+ [..] The DAC channel 1 integrates an output buffer that can be used to \r
+ reduce the output impedance, and to drive external loads directly\r
+ without having to add an external operational amplifier.\r
+ To enable the output buffer use \r
+ DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
+ \r
+ [..] Refer to the device datasheet for more details about output impedance\r
+ value with and without output buffer.\r
+ \r
+ [..] The DAC data format can be:\r
+ (#) 8-bit right alignment using DAC_Align_8b_R\r
+ (#) 12-bit left alignment using DAC_Align_12b_L\r
+ (#) 12-bit right alignment using DAC_Align_12b_R\r
+ \r
+ [..] The analog output voltage on each DAC channel pin is determined\r
+ by the following equation: DAC_OUTx = VREF+ * DOR / 4095\r
+ with DOR is the Data Output Register\r
+ VEF+ is the input voltage reference (refer to the device datasheet)\r
+ e.g. To set DAC_OUT1 to 0.7V, use\r
+ DAC_SetChannel1Data(DAC_Align_12b_R, 868);\r
+ Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V\r
+ \r
+ [..] A DMA1 request can be generated when an external trigger (but not\r
+ a software trigger) occurs if DMA1 requests are enabled using\r
+ DAC_DMACmd()\r
+ DMA1 requests are mapped as following:\r
+ (+) DAC channel1 is mapped on DMA1 channel3 which must be already \r
+ configured\r
+ \r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ (+) Enable DAC APB1 clock to get write access to DAC registers\r
+ using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)\r
+ \r
+ (+) Configure DAC_OUT1 (DAC_OUT1: PA4) in analog mode\r
+ using GPIO_Init() function \r
+ \r
+ (+) Configure the DAC channel using DAC_Init()\r
+ \r
+ (+) Enable the DAC channel using DAC_Cmd()\r
+ \r
+ @endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_dac.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC \r
+ * @brief DAC driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* CR register Mask */\r
+#define CR_CLEAR_MASK ((uint32_t)0x0000003E)\r
+\r
+/* DHR registers offsets */\r
+#define DHR12R1_OFFSET ((uint32_t)0x00000008)\r
+\r
+/* DOR register offset */\r
+#define DOR_OFFSET ((uint32_t)0x0000002C)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup DAC_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup DAC_Group1 DAC channels configuration\r
+ * @brief DAC channels configuration: trigger, output buffer, data format \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### DAC channels configuration: trigger, output buffer, data format #####\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DAC_DeInit(void)\r
+{\r
+ /* Enable DAC reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);\r
+ /* Release DAC from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DAC peripheral according to the specified \r
+ * parameters in the DAC_InitStruct.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that\r
+ * contains the configuration information for the specified DAC channel.\r
+ *\r
+ * @retval None\r
+ */\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+\r
+ /* Check the DAC parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));\r
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));\r
+\r
+ /*---------------------------- DAC CR Configuration ------------------------*/\r
+ /* Get the DAC CR value */\r
+ tmpreg1 = DAC->CR;\r
+\r
+ /* Clear BOFFx, TENx, TSELx bits */\r
+ tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);\r
+\r
+ /* Configure for the selected DAC channel: buffer output, trigger */\r
+ /* Set TSELx and TENx bits according to DAC_Trigger value */\r
+ /* Set BOFFx bit according to DAC_OutputBuffer value */ \r
+ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_OutputBuffer);\r
+\r
+ /* Calculate CR register value depending on DAC_Channel */\r
+ tmpreg1 |= tmpreg2 << DAC_Channel;\r
+\r
+ /* Write to DAC CR */\r
+ DAC->CR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Fills each DAC_InitStruct member with its default value.\r
+ * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+/*--------------- Reset DAC init structure parameters values -----------------*/\r
+ /* Initialize the DAC_Trigger member */\r
+ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;\r
+ /* Initialize the DAC_OutputBuffer member */\r
+ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel.\r
+ * @param DAC_Channel: The selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @param NewState: new state of the DAC channel. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the DAC channel is enabled the trigger source can no more\r
+ * be modified.\r
+ * @retval None\r
+ */\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel */\r
+ DAC->CR |= (DAC_CR_EN1 << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel */\r
+ DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel software trigger.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @param NewState: new state of the selected DAC channel software trigger.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);\r
+ }\r
+ else\r
+ {\r
+ /* Disable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel1.\r
+ * @param DAC_Align: Specifies the data alignment for DAC channel1.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected\r
+ * @param Data : Data to be loaded in the selected data holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)\r
+{ \r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ \r
+ tmp = (uint32_t)DAC_BASE; \r
+ tmp += DHR12R1_OFFSET + DAC_Align;\r
+\r
+ /* Set the DAC channel1 selected data holding register */\r
+ *(__IO uint32_t *) tmp = Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the last data output value of the selected DAC channel.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @retval The selected DAC channel data output value.\r
+ */\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ \r
+ tmp = (uint32_t) DAC_BASE ;\r
+ tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);\r
+ \r
+ /* Returns the DAC channel data output register value */\r
+ return (uint16_t) (*(__IO uint32_t*) tmp);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Group2 DMA management functions\r
+ * @brief DMA management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### DMA management functions #####\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel DMA request.\r
+ * When enabled DMA1 is generated when an external trigger (EXTI Line9,\r
+ * TIM2, TIM3, TIM6 or TIM15 but not a software trigger) occurs\r
+ * @param DAC_Channel: the selected DAC channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @param NewState: new state of the selected DAC channel DMA request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * The DAC channel1 is mapped on DMA1 channel3 which must be already configured. \r
+ * @retval None\r
+ */\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel DMA request */\r
+ DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel DMA request */\r
+ DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC interrupts.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. \r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r
+ * @note The DMA underrun occurs when a second external trigger arrives before\r
+ * the acknowledgement for the first external trigger is received (first request).\r
+ * @param NewState: new state of the specified DAC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */ \r
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) \r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_DAC_IT(DAC_IT)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC interrupts */\r
+ DAC->CR |= (DAC_IT << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC interrupts */\r
+ DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DAC flag is set or not.\r
+ * @param DAC_Channel: thee selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @param DAC_FLAG: specifies the flag to check. \r
+ * This parameter can be only of the following value:\r
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag\r
+ * @note The DMA underrun occurs when a second external trigger arrives before\r
+ * the acknowledgement for the first external trigger is received (first request).\r
+ * @retval The new state of DAC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_FLAG(DAC_FLAG));\r
+\r
+ /* Check the status of the specified DAC flag */\r
+ if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)\r
+ {\r
+ /* DAC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DAC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DAC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DAC channel's pending flags.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @param DAC_FLAG: specifies the flag to clear. \r
+ * This parameter can be of the following value:\r
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag\r
+ * @retval None\r
+ */\r
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_FLAG(DAC_FLAG));\r
+\r
+ /* Clear the selected DAC flags */\r
+ DAC->SR = (DAC_FLAG << DAC_Channel);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DAC interrupt has occurred or not.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @param DAC_IT: specifies the DAC interrupt source to check. \r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r
+ * @note The DMA underrun occurs when a second external trigger arrives before\r
+ * the acknowledgement for the first external trigger is received (first request).\r
+ * @retval The new state of DAC_IT (SET or RESET).\r
+ */\r
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_IT(DAC_IT));\r
+\r
+ /* Get the DAC_IT enable bit status */\r
+ enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;\r
+ \r
+ /* Check the status of the specified DAC interrupt */\r
+ if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* DAC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DAC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DAC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DAC channel's interrupt pending bits.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @param DAC_IT: specifies the DAC interrupt pending bit to clear.\r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask\r
+ * @retval None\r
+ */\r
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_IT(DAC_IT)); \r
+\r
+ /* Clear the selected DAC interrupt pending bits */\r
+ DAC->SR = (DAC_IT << DAC_Channel);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_dbgmcu.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Debug MCU (DBGMCU) peripheral:\r
+ * + Device and Revision ID management\r
+ * + Peripherals Configuration\r
+ * @verbatim\r
+ * @endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_dbgmcu.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DBGMCU \r
+ * @brief DBGMCU driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup DBGMCU_Private_Functions \r
+ * @{\r
+ */\r
+ \r
+\r
+/** @defgroup DBGMCU_Group1 Device and Revision ID management functions\r
+ * @brief Device and Revision ID management functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Device and Revision ID management functions #####\r
+ ==============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the device revision identifier.\r
+ * @param None\r
+ * @retval Device revision identifier\r
+ */\r
+uint32_t DBGMCU_GetREVID(void)\r
+{\r
+ return(DBGMCU->IDCODE >> 16);\r
+}\r
+\r
+/**\r
+ * @brief Returns the device identifier.\r
+ * @param None\r
+ * @retval Device identifier\r
+ */\r
+uint32_t DBGMCU_GetDEVID(void)\r
+{\r
+ return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DBGMCU_Group2 Peripherals Configuration functions\r
+ * @brief Peripherals Configuration\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Peripherals Configuration functions #####\r
+ ==============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures low power mode behavior when the MCU is in Debug mode.\r
+ * @param DBGMCU_Periph: specifies the low power mode.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DBGMCU_STOP: Keep debugger connection during STOP mode\r
+ * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode\r
+ * @param NewState: new state of the specified low power mode in Debug mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ DBGMCU->CR |= DBGMCU_Periph;\r
+ }\r
+ else\r
+ {\r
+ DBGMCU->CR &= ~DBGMCU_Periph;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.\r
+ * @param DBGMCU_Periph: specifies the APB1 peripheral.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted\r
+ * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped \r
+ * when Core is halted.\r
+ * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted\r
+ * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted\r
+ * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped \r
+ * when Core is halted\r
+ * @param NewState: new state of the specified APB1 peripheral in Debug mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ DBGMCU->APB1FZ |= DBGMCU_Periph;\r
+ }\r
+ else\r
+ {\r
+ DBGMCU->APB1FZ &= ~DBGMCU_Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.\r
+ * @param DBGMCU_Periph: specifies the APB2 peripheral.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted\r
+ * @param NewState: new state of the specified APB2 peripheral in Debug mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ DBGMCU->APB2FZ |= DBGMCU_Periph;\r
+ }\r
+ else\r
+ {\r
+ DBGMCU->APB2FZ &= ~DBGMCU_Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_dma.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Direct Memory Access controller (DMA):\r
+ * + Initialization and Configuration\r
+ * + Data Counter\r
+ * + Interrupts and flags management\r
+ *\r
+ * @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Enable The DMA controller clock using \r
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1.\r
+ (#) Enable and configure the peripheral to be connected to the DMA channel\r
+ (except for internal SRAM / FLASH memories: no initialization is necessary).\r
+ (#) For a given Channel, program the Source and Destination addresses, \r
+ the transfer Direction, the Buffer Size, the Peripheral and Memory \r
+ Incrementation mode and Data Size, the Circular or Normal mode, \r
+ the channel transfer Priority and the Memory-to-Memory transfer \r
+ mode (if needed) using the DMA_Init() function.\r
+ (#) Enable the NVIC and the corresponding interrupt(s) using the function \r
+ DMA_ITConfig() if you need to use DMA interrupts.\r
+ (#) Enable the DMA channel using the DMA_Cmd() function.\r
+ (#) Activate the needed channel Request using PPP_DMACmd() function for \r
+ any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) \r
+ The function allowing this operation is provided in each PPP peripheral \r
+ driver (ie. SPI_DMACmd for SPI peripheral).\r
+ (#) Optionally, you can configure the number of data to be transferred\r
+ when the channel is disabled (ie. after each Transfer Complete event\r
+ or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().\r
+ And you can get the number of remaining data to be transferred using \r
+ the function DMA_GetCurrDataCounter() at run time (when the DMA channel is\r
+ enabled and running).\r
+ (#) To control DMA events you can use one of the following two methods:\r
+ (##) Check on DMA channel flags using the function DMA_GetFlagStatus().\r
+ (##) Use DMA interrupts through the function DMA_ITConfig() at initialization\r
+ phase and DMA_GetITStatus() function into interrupt routines in\r
+ communication phase.\r
+ After checking on a flag you should clear it using DMA_ClearFlag()\r
+ function. And after checking on an interrupt event you should \r
+ clear it using DMA_ClearITPendingBit() function.\r
+ @endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_dma.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA \r
+ * @brief DMA driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */\r
+\r
+/* DMA1 Channelx interrupt pending bit masks */\r
+#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))\r
+#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))\r
+#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))\r
+#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))\r
+#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Private_Functions \r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides functions allowing to initialize the DMA channel \r
+ source and destination addresses, incrementation and data sizes, transfer \r
+ direction, buffer size, circular/normal mode selection, memory-to-memory \r
+ mode selection and channel priority value.\r
+ [..] The DMA_Init() function follows the DMA configuration procedures as described \r
+ in reference manual (RM0091).\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Deinitializes the DMAy Channelx registers to their default reset\r
+ * values.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and \r
+ * x can be 1 to 5 for DMA1 to select the DMA Channel.\r
+ * @retval None\r
+ */\r
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+\r
+ /* Disable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);\r
+\r
+ /* Reset DMAy Channelx control register */\r
+ DMAy_Channelx->CCR = 0;\r
+\r
+ /* Reset DMAy Channelx remaining bytes register */\r
+ DMAy_Channelx->CNDTR = 0;\r
+\r
+ /* Reset DMAy Channelx peripheral address register */\r
+ DMAy_Channelx->CPAR = 0;\r
+\r
+ /* Reset DMAy Channelx memory address register */\r
+ DMAy_Channelx->CMAR = 0;\r
+\r
+ if (DMAy_Channelx == DMA1_Channel1)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel1 */\r
+ DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel2)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel2 */\r
+ DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel3)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel3 */\r
+ DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel4)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel4 */\r
+ DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;\r
+ }\r
+ else\r
+ {\r
+ if (DMAy_Channelx == DMA1_Channel5) \r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel5 */\r
+ DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMAy Channelx according to the specified parameters \r
+ * in the DMA_InitStruct.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 5\r
+ * for DMA1 to select the DMA Channel.\r
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains\r
+ * the configuration information for the specified DMA Channel.\r
+ * @retval None\r
+ */\r
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));\r
+ assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));\r
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));\r
+ assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));\r
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));\r
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));\r
+ assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));\r
+ assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));\r
+ assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));\r
+\r
+/*--------------------------- DMAy Channelx CCR Configuration ----------------*/\r
+ /* Get the DMAy_Channelx CCR value */\r
+ tmpreg = DMAy_Channelx->CCR;\r
+\r
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */\r
+ tmpreg &= CCR_CLEAR_MASK;\r
+\r
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */\r
+ /* Set DIR bit according to DMA_DIR value */\r
+ /* Set CIRC bit according to DMA_Mode value */\r
+ /* Set PINC bit according to DMA_PeripheralInc value */\r
+ /* Set MINC bit according to DMA_MemoryInc value */\r
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */\r
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */\r
+ /* Set PL bits according to DMA_Priority value */\r
+ /* Set the MEM2MEM bit according to DMA_M2M value */\r
+ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |\r
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |\r
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |\r
+ DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;\r
+\r
+ /* Write to DMAy Channelx CCR */\r
+ DMAy_Channelx->CCR = tmpreg;\r
+\r
+/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/\r
+ /* Write to DMAy Channelx CNDTR */\r
+ DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;\r
+\r
+/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/\r
+ /* Write to DMAy Channelx CPAR */\r
+ DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;\r
+\r
+/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/\r
+ /* Write to DMAy Channelx CMAR */\r
+ DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;\r
+}\r
+\r
+/**\r
+ * @brief Fills each DMA_InitStruct member with its default value.\r
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+/*-------------- Reset DMA init structure parameters values ------------------*/\r
+ /* Initialize the DMA_PeripheralBaseAddr member */\r
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;\r
+ /* Initialize the DMA_MemoryBaseAddr member */\r
+ DMA_InitStruct->DMA_MemoryBaseAddr = 0;\r
+ /* Initialize the DMA_DIR member */\r
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;\r
+ /* Initialize the DMA_BufferSize member */\r
+ DMA_InitStruct->DMA_BufferSize = 0;\r
+ /* Initialize the DMA_PeripheralInc member */\r
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
+ /* Initialize the DMA_MemoryInc member */\r
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;\r
+ /* Initialize the DMA_PeripheralDataSize member */\r
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;\r
+ /* Initialize the DMA_MemoryDataSize member */\r
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;\r
+ /* Initialize the DMA_Mode member */\r
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;\r
+ /* Initialize the DMA_Priority member */\r
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;\r
+ /* Initialize the DMA_M2M member */\r
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMAy Channelx.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
+ * x can be 1 to 5 for DMA1 to select the DMA Channel.\r
+ * @param NewState: new state of the DMAy Channelx. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR |= DMA_CCR_EN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Group2 Data Counter functions\r
+ * @brief Data Counter functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Data Counter functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides function allowing to configure and read the buffer \r
+ size (number of data to be transferred).The DMA data counter can be written \r
+ only when the DMA channel is disabled (ie. after transfer complete event).\r
+ [..] The following function can be used to write the Channel data counter value:\r
+ (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t \r
+ DataNumber).\r
+ -@- It is advised to use this function rather than DMA_Init() in situations \r
+ where only the Data buffer needs to be reloaded.\r
+ [..] The DMA data counter can be read to indicate the number of remaining transfers \r
+ for the relative DMA channel. This counter is decremented at the end of each \r
+ data transfer and when the transfer is complete: \r
+ (+) If Normal mode is selected: the counter is set to 0.\r
+ (+) If Circular mode is selected: the counter is reloaded with the initial \r
+ value(configured before enabling the DMA channel).\r
+ [..] The following function can be used to read the Channel data counter value:\r
+ (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the number of data units in the current DMAy Channelx transfer.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be \r
+ * 1 to 5 for DMA1 to select the DMA Channel.\r
+ * @param DataNumber: The number of data units in the current DMAy Channelx\r
+ * transfer.\r
+ * @note This function can only be used when the DMAy_Channelx is disabled.\r
+ * @retval None.\r
+ */\r
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+\r
+/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/\r
+ /* Write to DMAy Channelx CNDTR */\r
+ DMAy_Channelx->CNDTR = DataNumber;\r
+}\r
+\r
+/**\r
+ * @brief Returns the number of remaining data units in the current\r
+ * DMAy Channelx transfer.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
+ * x can be 1 to 5 for DMA1 to select the DMA Channel.\r
+ * @retval The number of remaining data units in the current DMAy Channelx\r
+ * transfer.\r
+ */\r
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ /* Return the number of remaining data units for DMAy Channelx */\r
+ return ((uint16_t)(DMAy_Channelx->CNDTR));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides functions allowing to configure the DMA Interrupts \r
+ sources and check or clear the flags or pending bits status.\r
+ The user should identify which mode will be used in his application to manage \r
+ the DMA controller events: Polling mode or Interrupt mode. \r
+ *** Polling Mode ***\r
+ ====================\r
+ [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller \r
+ number x : DMA channel number ).\r
+ (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.\r
+ (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.\r
+ (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.\r
+ (#) DMAy_FLAG_GLx : to indicate that at least one of the events described \r
+ above occurred.\r
+ -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the \r
+ same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).\r
+ [..]In this Mode it is advised to use the following functions:\r
+ (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);\r
+ (+) void DMA_ClearFlag(uint32_t DMA_FLAG);\r
+\r
+ *** Interrupt Mode ***\r
+ ======================\r
+ [..] Each DMA channel can be managed through 4 Interrupts:\r
+ (+) Interrupt Source\r
+ (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete \r
+ event.\r
+ (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete \r
+ event.\r
+ (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event.\r
+ (##) DMA_IT_GL : to indicate that at least one of the interrupts described \r
+ above occurred.\r
+ -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of \r
+ the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).\r
+ [..]In this Mode it is advised to use the following functions:\r
+ (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, \r
+ FunctionalState NewState);\r
+ (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);\r
+ (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMAy Channelx interrupts.\r
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and\r
+ * x can be 1 to 5 for DMA1 to select the DMA Channel.\r
+ * @param DMA_IT: specifies the DMA interrupts sources to be enabled\r
+ * or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA_IT_HT: Half transfer interrupt mask\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask\r
+ * @param NewState: new state of the specified DMA interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_DMA_CONFIG_IT(DMA_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA interrupts */\r
+ DMAy_Channelx->CCR |= DMA_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA interrupts */\r
+ DMAy_Channelx->CCR &= ~DMA_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DMAy Channelx flag is set or not.\r
+ * @param DMA_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
+ * \r
+ * @note\r
+ * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags \r
+ * relative to the same channel is set (Transfer Complete, Half-transfer \r
+ * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or \r
+ * DMAy_FLAG_TEx). \r
+ * \r
+ * @retval The new state of DMA_FLAG (SET or RESET).\r
+ */\r
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_GET_FLAG(DMA_FLAG));\r
+\r
+ /* Check the status of the specified DMA flag */\r
+ if ((DMA1->ISR & DMA_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* DMA_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMA_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the DMA_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DMAy Channelx's pending flags.\r
+ * @param DMA_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination (for the same DMA) of the following values:\r
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
+ *\r
+ * @note\r
+ * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags\r
+ * relative to the same channel (Transfer Complete, Half-transfer Complete and\r
+ * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).\r
+ *\r
+ * @retval None\r
+ */\r
+void DMA_ClearFlag(uint32_t DMA_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));\r
+\r
+ /* Clear the selected DMA flags */\r
+ DMA1->IFCR = DMA_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.\r
+ * @param DMA_IT: specifies the DMA interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
+ * \r
+ * @note\r
+ * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other \r
+ * interrupts relative to the same channel is set (Transfer Complete, \r
+ * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, \r
+ * DMAy_IT_HTx or DMAy_IT_TEx). \r
+ * \r
+ * @retval The new state of DMA_IT (SET or RESET).\r
+ */\r
+ITStatus DMA_GetITStatus(uint32_t DMA_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_GET_IT(DMA_IT));\r
+\r
+ /* Check the status of the specified DMA interrupt */\r
+ if ((DMA1->ISR & DMA_IT) != (uint32_t)RESET)\r
+ {\r
+ /* DMA_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMA_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DMA_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DMAy Channelx's interrupt pending bits.\r
+ * @param DMA_IT: specifies the DMA interrupt pending bit to clear.\r
+ * This parameter can be any combination (for the same DMA) of the following values:\r
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
+ * \r
+ * @note\r
+ * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other \r
+ * interrupts relative to the same channel (Transfer Complete, Half-transfer \r
+ * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and \r
+ * DMAy_IT_TEx). \r
+ * \r
+ * @retval None\r
+ */\r
+void DMA_ClearITPendingBit(uint32_t DMA_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_CLEAR_IT(DMA_IT));\r
+\r
+ /* Clear the selected DMA interrupt pending bits */\r
+ DMA1->IFCR = DMA_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_exti.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the EXTI peripheral:\r
+ * + Initialization and Configuration\r
+ * + Interrupts and flags management\r
+ *\r
+ * @verbatim\r
+ ==============================================================================\r
+ ##### EXTI features ##### \r
+ ==============================================================================\r
+ [..] External interrupt/event lines are mapped as following:\r
+ (#) All available GPIO pins are connected to the 16 external \r
+ interrupt/event lines from EXTI0 to EXTI15.\r
+ (#) EXTI line 16 is connected to the PVD output.\r
+ (#) EXTI line 17 is connected to the RTC Alarm event.\r
+ (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events\r
+ (#) EXTI line 21 is connected to the Comparator 1 wakeup event \r
+ (#) EXTI line 22 is connected to the Comparator 2 wakeup event\r
+ (#) EXTI line 23 is connected to the I2C1 wakeup event\r
+ (#) EXTI line 25 is connected to the USART1 wakeup event\r
+ (#) EXTI line 27 is connected to the CEC wakeup event\r
+\r
+ ##### How to use this driver ##### \r
+ ==============================================================================\r
+ [..] In order to use an I/O pin as an external interrupt source, follow\r
+ steps below:\r
+ (#) Configure the I/O in input mode using GPIO_Init()\r
+ (#) Select the input source pin for the EXTI line using \r
+ SYSCFG_EXTILineConfig().\r
+ (#) Select the mode(interrupt, event) and configure the trigger selection \r
+ (Rising, falling or both) using EXTI_Init(). For the internal interrupt,\r
+ the trigger selection is not needed( the active edge is always the rising one).\r
+ (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init().\r
+ (#) Optionally, you can generate a software interrupt using the function EXTI_GenerateSWInterrupt().\r
+ [..]\r
+ (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx\r
+ registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+ @endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_exti.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI \r
+ * @brief EXTI driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup EXTI_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ==============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the EXTI peripheral registers to their default reset \r
+ * values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void EXTI_DeInit(void)\r
+{\r
+ EXTI->IMR = 0x0F940000;\r
+ EXTI->EMR = 0x00000000;\r
+ EXTI->RTSR = 0x00000000;\r
+ EXTI->FTSR = 0x00000000;\r
+ EXTI->PR = 0x006BFFFF;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the EXTI peripheral according to the specified\r
+ * parameters in the EXTI_InitStruct.\r
+ * EXTI_Line specifies the EXTI line (EXTI0....EXTI27).\r
+ * EXTI_Mode specifies which EXTI line is used as interrupt or an event.\r
+ * EXTI_Trigger selects the trigger. When the trigger occurs, interrupt\r
+ * pending bit will be set.\r
+ * EXTI_LineCmd controls (Enable/Disable) the EXTI line.\r
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that \r
+ * contains the configuration information for the EXTI peripheral.\r
+ * @retval None\r
+ */\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));\r
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));\r
+ assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));\r
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));\r
+\r
+ tmp = (uint32_t)EXTI_BASE;\r
+\r
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)\r
+ {\r
+ /* Clear EXTI line configuration */\r
+ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;\r
+ EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;\r
+\r
+ tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+\r
+ /* Select the trigger for the selected interrupts */\r
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)\r
+ {\r
+ /* Rising Falling edge */\r
+ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ else\r
+ {\r
+ tmp = (uint32_t)EXTI_BASE;\r
+ tmp += EXTI_InitStruct->EXTI_Trigger;\r
+\r
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+ /* Disable the selected external lines */\r
+ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each EXTI_InitStruct member with its reset value.\r
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;\r
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;\r
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;\r
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;\r
+}\r
+\r
+/**\r
+ * @brief Generates a Software interrupt on selected EXTI line.\r
+ * @param EXTI_Line: specifies the EXTI line on which the software interrupt\r
+ * will be generated.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19)\r
+ * @retval None\r
+ */\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+\r
+ EXTI->SWIER |= EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Group2 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ==============================================================================\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line flag is set or not.\r
+ * @param EXTI_Line: specifies the EXTI line flag to check.\r
+ * This parameter can be:\r
+ * EXTI_Linex: External interrupt line x where x(0..19).\r
+ * @retval The new state of EXTI_Line (SET or RESET).\r
+ */\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+\r
+ if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending flags.\r
+ * @param EXTI_Line: specifies the EXTI lines flags to clear.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19)\r
+ * @retval None\r
+ */\r
+void EXTI_ClearFlag(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+\r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line is asserted or not.\r
+ * @param EXTI_Line: specifies the EXTI line to check.\r
+ * This parameter can be:\r
+ * EXTI_Linex: External interrupt line x where x(0..19).\r
+ * @retval The new state of EXTI_Line (SET or RESET).\r
+ */\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+\r
+ enablestatus = EXTI->IMR & EXTI_Line;\r
+ if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending bits.\r
+ * @param EXTI_Line: specifies the EXTI lines to clear.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).\r
+ * @retval None\r
+ */\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+\r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_flash.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the FLASH peripheral:\r
+ * - FLASH Interface configuration\r
+ * - FLASH Memory Programming\r
+ * - Option Bytes Programming\r
+ * - Interrupts and flags management\r
+ *\r
+ * @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..] This driver provides functions to configure and program the Flash \r
+ memory of all STM32F0xx devices. These functions are split in 4 groups\r
+ (#) FLASH Interface configuration functions: this group includes the \r
+ management of following features:\r
+ (++) Set the latency\r
+ (++) Enable/Disable the prefetch buffer\r
+\r
+ (#) FLASH Memory Programming functions: this group includes all needed \r
+ functions to erase and program the main memory:\r
+ (++) Lock and Unlock the Flash interface.\r
+ (++) Erase function: Erase Page, erase all pages.\r
+ (++) Program functions: Half Word and Word write.\r
+\r
+ (#) FLASH Option Bytes Programming functions: this group includes all \r
+ needed functions to:\r
+ (++) Lock and Unlock the Flash Option bytes.\r
+ (++) Launch the Option Bytes loader\r
+ (++) Erase the Option Bytes\r
+ (++)Set/Reset the write protection\r
+ (++) Set the Read protection Level\r
+ (++) Program the user option Bytes\r
+ (++) Set/Reset the BOOT1 bit\r
+ (++) Enable/Disable the VDDA Analog Monitoring\r
+ (++) Get the user option bytes\r
+ (++) Get the Write protection\r
+ (++) Get the read protection status\r
+\r
+ (#) FLASH Interrupts and flag management functions: this group includes \r
+ all needed functions to:\r
+ (++) Enable/Disable the flash interrupt sources\r
+ (++) Get flags status\r
+ (++) Clear flags\r
+ (++) Get Flash operation status\r
+ (++) Wait for last flash operation\r
+\r
+ @endverbatim\r
+ \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_flash.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH \r
+ * @brief FLASH driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+ /* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+ \r
+/** @defgroup FLASH_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup FLASH_Group1 FLASH Interface configuration functions\r
+ * @brief FLASH Interface configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### FLASH Interface configuration functions #####\r
+ ===============================================================================\r
+\r
+ [..] FLASH_Interface configuration_Functions, includes the following functions:\r
+ (+) void FLASH_SetLatency(uint32_t FLASH_Latency):\r
+ [..] To correctly read data from Flash memory, the number of wait states (LATENCY) \r
+ must be correctly programmed according to the frequency of the CPU clock (HCLK) \r
+ [..]\r
+ +--------------------------------------------- +\r
+ | Wait states | HCLK clock frequency (MHz) |\r
+ |---------------|------------------------------|\r
+ |0WS(1CPU cycle)| 0 < HCLK <= 24 |\r
+ |---------------|------------------------------|\r
+ |1WS(2CPU cycle)| 24 < HCLK <= 48 |\r
+ +----------------------------------------------+\r
+ [..]\r
+ (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState);\r
+ [..]\r
+ All these functions don't need the unlock sequence.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the code latency value.\r
+ * @param FLASH_Latency: specifies the FLASH Latency value.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_Latency_0: FLASH Zero Latency cycle\r
+ * @arg FLASH_Latency_1: FLASH One Latency cycle\r
+ * @retval None\r
+ */\r
+void FLASH_SetLatency(uint32_t FLASH_Latency)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));\r
+\r
+ /* Read the ACR register */\r
+ tmpreg = FLASH->ACR; \r
+\r
+ /* Sets the Latency value */\r
+ tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));\r
+ tmpreg |= FLASH_Latency;\r
+\r
+ /* Write the ACR register */\r
+ FLASH->ACR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Prefetch Buffer.\r
+ * @param NewState: new state of the FLASH prefetch buffer.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void FLASH_PrefetchBufferCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if(NewState != DISABLE)\r
+ {\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+ }\r
+ else\r
+ {\r
+ FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTBE));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the FLASH Prefetch Buffer status is set or not.\r
+ * @param None\r
+ * @retval FLASH Prefetch Buffer Status (SET or RESET).\r
+ */\r
+FlagStatus FLASH_GetPrefetchBufferStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ if ((FLASH->ACR & FLASH_ACR_PRFTBS) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */\r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Group2 FLASH Memory Programming functions\r
+ * @brief FLASH Memory Programming functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### FLASH Memory Programming functions #####\r
+ ===============================================================================\r
+\r
+ [..] The FLASH Memory Programming functions, includes the following functions:\r
+ (+) void FLASH_Unlock(void);\r
+ (+) void FLASH_Lock(void);\r
+ (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
+ (+) FLASH_Status FLASH_EraseAllPages(void);\r
+ (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);\r
+ (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
+\r
+ [..] Any operation of erase or program should follow these steps:\r
+ \r
+ (#) Call the FLASH_Unlock() function to enable the flash control register and \r
+ program memory access\r
+ (#) Call the desired function to erase page or program data\r
+ (#) Call the FLASH_Lock() to disable the flash program memory access \r
+ (recommended to protect the FLASH memory against possible unwanted operation)\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlocks the FLASH control register and program memory access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_Unlock(void)\r
+{\r
+ if((FLASH->CR & FLASH_CR_LOCK) != RESET)\r
+ {\r
+ /* Unlocking the program memory access */\r
+ FLASH->KEYR = FLASH_FKEY1;\r
+ FLASH->KEYR = FLASH_FKEY2;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Locks the Program memory access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_Lock(void)\r
+{\r
+ /* Set the LOCK Bit to lock the FLASH control register and program memory access */\r
+ FLASH->CR |= FLASH_CR_LOCK;\r
+}\r
+\r
+/**\r
+ * @brief Erases a specified page in program memory.\r
+ * @note To correctly run this function, the FLASH_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * @param Page_Address: The page address in program memory to be erased.\r
+ * @note A Page is erased in the Program memory only if the address to load \r
+ * is the start address of a page (multiple of 1024 bytes).\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* If the previous operation is completed, proceed to erase the page */\r
+ FLASH->CR |= FLASH_CR_PER;\r
+ FLASH->AR = Page_Address;\r
+ FLASH->CR |= FLASH_CR_STRT;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* Disable the PER Bit */\r
+ FLASH->CR &= ~FLASH_CR_PER;\r
+ }\r
+ \r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Erases all FLASH pages.\r
+ * @note To correctly run this function, the FLASH_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_EraseAllPages(void)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to erase all pages */\r
+ FLASH->CR |= FLASH_CR_MER;\r
+ FLASH->CR |= FLASH_CR_STRT;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+\r
+ /* Disable the MER Bit */\r
+ FLASH->CR &= ~FLASH_CR_MER;\r
+ }\r
+\r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a word at a specified address.\r
+ * @note To correctly run this function, the FLASH_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to program the new first \r
+ half word */\r
+ FLASH->CR |= FLASH_CR_PG;\r
+ \r
+ *(__IO uint16_t*)Address = (uint16_t)Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to program the new second \r
+ half word */\r
+ tmp = Address + 2;\r
+\r
+ *(__IO uint16_t*) tmp = Data >> 16;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= ~FLASH_CR_PG;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= ~FLASH_CR_PG;\r
+ }\r
+ }\r
+ \r
+ /* Return the Program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a half word at a specified address.\r
+ * @note To correctly run this function, the FLASH_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_Lock() to disable the flash memory access \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR |= FLASH_CR_PG;\r
+ \r
+ *(__IO uint16_t*)Address = Data;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= ~FLASH_CR_PG;\r
+ } \r
+ \r
+ /* Return the Program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FLASH_Group3 Option Bytes Programming functions\r
+ * @brief Option Bytes Programming functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Option Bytes Programming functions #####\r
+ ===============================================================================\r
+\r
+ [..] The FLASH_Option Bytes Programming_functions, includes the following functions:\r
+ (+) void FLASH_OB_Unlock(void);\r
+ (+) void FLASH_OB_Lock(void);\r
+ (+) void FLASH_OB_Launch(void);\r
+ (+) FLASH_Status FLASH_OB_Erase(void);\r
+ (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);\r
+ (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);\r
+ (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);\r
+ (+) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);\r
+ (+) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);\r
+ (+) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);\r
+ (+) uint8_t FLASH_OB_GetUser(void);\r
+ (+) uint32_t FLASH_OB_GetWRP(void);\r
+ (+) FlagStatus FLASH_OB_GetRDP(void);\r
+\r
+ [..] Any operation of erase or program should follow these steps:\r
+\r
+ (#) Call the FLASH_OB_Unlock() function to enable the Option Bytes registers access\r
+\r
+ (#) Call one or several functions to program the desired option bytes \r
+ (++) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level\r
+ (++) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) \r
+ => to Enable/Disable the desired sector write protection\r
+ (++) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) \r
+ => to configure the user option Bytes: IWDG, STOP and the Standby.\r
+ (++) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)\r
+ => to set or reset BOOT1 \r
+ (++) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG) \r
+ => to enable or disable the VDDA Analog Monitoring \r
+ (++) You can write all User Options bytes at once using a single function\r
+ by calling FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)\r
+\r
+ (#) Once all needed option bytes to be programmed are correctly written, call the\r
+ FLASH_OB_Launch(void) function to launch the Option Bytes programming process.\r
+\r
+ (#) Call the FLASH_OB_Lock() to disable the Option Bytes registers access (recommended\r
+ to protect the option Bytes against possible unwanted operations)\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlocks the option bytes block access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_OB_Unlock(void)\r
+{\r
+ if((FLASH->CR & FLASH_CR_OPTWRE) == RESET)\r
+ { \r
+ /* Unlocking the option bytes block access */\r
+ FLASH->OPTKEYR = FLASH_OPTKEY1;\r
+ FLASH->OPTKEYR = FLASH_OPTKEY2;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Locks the option bytes block access.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_OB_Lock(void)\r
+{\r
+ /* Set the OPTWREN Bit to lock the option bytes block access */\r
+ FLASH->CR &= ~FLASH_CR_OPTWRE;\r
+}\r
+\r
+/**\r
+ * @brief Launch the option byte loading.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_OB_Launch(void)\r
+{\r
+ /* Set the OBL_Launch bit to launch the option byte loading */\r
+ FLASH->CR |= FLASH_CR_OBL_LAUNCH;\r
+}\r
+\r
+/**\r
+ * @brief Erases the FLASH option bytes.\r
+ * @note To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * @note This functions erases all option bytes except the Read protection (RDP).\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_Erase(void)\r
+{\r
+ uint16_t rdptmp = OB_RDP_Level_0;\r
+\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Get the actual read protection Option Byte value */ \r
+ if(FLASH_OB_GetRDP() != RESET)\r
+ {\r
+ rdptmp = 0x00; \r
+ }\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+\r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* If the previous operation is completed, proceed to erase the option bytes */\r
+ FLASH->CR |= FLASH_CR_OPTER;\r
+ FLASH->CR |= FLASH_CR_STRT;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the erase operation is completed, disable the OPTER Bit */\r
+ FLASH->CR &= ~FLASH_CR_OPTER;\r
+ \r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= FLASH_CR_OPTPG;\r
+\r
+ /* Restore the last read protection Option Byte value */\r
+ OB->RDP = (uint16_t)rdptmp; \r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= ~FLASH_CR_OPTPG;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (status != FLASH_TIMEOUT)\r
+ {\r
+ /* Disable the OPTPG Bit */\r
+ FLASH->CR &= ~FLASH_CR_OPTPG;\r
+ }\r
+ } \r
+ }\r
+ /* Return the erase status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Write protects the desired pages\r
+ * @note To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * @param OB_WRP: specifies the address of the pages to be write protected.\r
+ * This parameter can be:\r
+ * @arg OB_WRP_Pages0to3..OB_WRP_Pages60to63\r
+ * @arg OB_WRP_AllPages\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP)\r
+{\r
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF;\r
+\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP(OB_WRP));\r
+\r
+ OB_WRP = (uint32_t)(~OB_WRP);\r
+ WRP0_Data = (uint16_t)(OB_WRP & OB_WRP0_WRP0);\r
+ WRP1_Data = (uint16_t)((OB_WRP & OB_WRP0_nWRP0) >> 8);\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ FLASH->CR |= FLASH_CR_OPTPG;\r
+\r
+ if(WRP0_Data != 0xFF)\r
+ {\r
+ OB->WRP0 = WRP0_Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ }\r
+ if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))\r
+ {\r
+ OB->WRP1 = WRP1_Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ }\r
+ \r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= ~FLASH_CR_OPTPG;\r
+ }\r
+ } \r
+ /* Return the write protection operation Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the read out protection.\r
+ * @note To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * @param FLASH_ReadProtection_Level: specifies the read protection level. \r
+ * This parameter can be:\r
+ * @arg OB_RDP_Level_0: No protection\r
+ * @arg OB_RDP_Level_1: Read protection of the memory\r
+ * @arg OB_RDP_Level_2: Chip protection\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_RDP(OB_RDP));\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ FLASH->CR |= FLASH_CR_OPTER;\r
+ FLASH->CR |= FLASH_CR_STRT;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* If the erase operation is completed, disable the OPTER Bit */\r
+ FLASH->CR &= ~FLASH_CR_OPTER;\r
+ \r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= FLASH_CR_OPTPG;\r
+ \r
+ OB->RDP = OB_RDP;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); \r
+ \r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= ~FLASH_CR_OPTPG;\r
+ }\r
+ }\r
+ else \r
+ {\r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* Disable the OPTER Bit */\r
+ FLASH->CR &= ~FLASH_CR_OPTER;\r
+ }\r
+ }\r
+ }\r
+ /* Return the protection operation Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.\r
+ * @note To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * @param OB_IWDG: Selects the WDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_SW: Software WDG selected\r
+ * @arg OB_IWDG_HW: Hardware WDG selected\r
+ * @param OB_STOP: Reset event when entering STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STOP_NoRST: No reset generated when entering in STOP\r
+ * @arg OB_STOP_RST: Reset generated when entering in STOP\r
+ * @param OB_STDBY: Reset event when entering Standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY\r
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE; \r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));\r
+ assert_param(IS_OB_STOP_SOURCE(OB_STOP));\r
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= FLASH_CR_OPTPG; \r
+\r
+ OB->USER = (uint16_t)((uint16_t)(OB_IWDG | OB_STOP) | (uint16_t)(OB_STDBY | 0xF8));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+\r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* If the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= ~FLASH_CR_OPTPG;\r
+ }\r
+ } \r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Sets or resets the BOOT1.\r
+ * @param OB_BOOT1: Set or Reset the BOOT1.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_BOOT1_RESET: BOOT1 Reset\r
+ * @arg OB_BOOT1_SET: BOOT1 Set\r
+ * @retval None\r
+ */\r
+FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE; \r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_BOOT1(OB_BOOT1));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= FLASH_CR_OPTPG;\r
+\r
+ OB->USER = OB_BOOT1 | 0xEF;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+\r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* If the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= ~FLASH_CR_OPTPG;\r
+ }\r
+ }\r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Sets or resets the analogue monitoring on VDDA Power source.\r
+ * @param OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON\r
+ * @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF\r
+ * @retval None\r
+ */\r
+FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE; \r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= FLASH_CR_OPTPG; \r
+\r
+ OB->USER = OB_VDDA_ANALOG | 0xDF;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+\r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= ~FLASH_CR_OPTPG;\r
+ }\r
+ }\r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs the FLASH User Option Byte: IWDG_SW, RST_STOP, RST_STDBY,\r
+ * BOOT1 and VDDA ANALOG monitoring.\r
+ * @note To correctly run this function, the FLASH_OB_Unlock() function\r
+ * must be called before.\r
+ * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes \r
+ * (recommended to protect the FLASH memory against possible unwanted operation)\r
+ * @param OB_USER: Selects all user option bytes\r
+ * This parameter is a combination of the following values:\r
+ * @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected\r
+ * @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP\r
+ * @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY\r
+ * @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set\r
+ * @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF \r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE; \r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= FLASH_CR_OPTPG; \r
+\r
+ OB->USER = OB_USER | 0xC8;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);\r
+\r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* If the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= ~FLASH_CR_OPTPG;\r
+ }\r
+ } \r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH User Option Bytes values.\r
+ * @param None\r
+ * @retval The FLASH User Option Bytes .\r
+ */\r
+uint8_t FLASH_OB_GetUser(void)\r
+{\r
+ /* Return the User Option Byte */\r
+ return (uint8_t)(FLASH->OBR >> 8);\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Write Protection Option Bytes value.\r
+ * @param None\r
+ * @retval The FLASH Write Protection Option Bytes value\r
+ */\r
+uint32_t FLASH_OB_GetWRP(void)\r
+{\r
+ /* Return the FLASH write protection Register value */\r
+ return (uint32_t)(FLASH->WRPR);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the FLASH Read out Protection Status is set or not.\r
+ * @param None\r
+ * @retval FLASH ReadOut Protection Status(SET or RESET)\r
+ */\r
+FlagStatus FLASH_OB_GetRDP(void)\r
+{\r
+ FlagStatus readstatus = RESET;\r
+ \r
+ if ((uint8_t)(FLASH->OBR & (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)) != RESET)\r
+ {\r
+ readstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ readstatus = RESET;\r
+ }\r
+ return readstatus;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Group4 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified FLASH interrupts.\r
+ * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or \r
+ * disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_IT_EOP: FLASH end of programming Interrupt\r
+ * @arg FLASH_IT_ERR: FLASH Error Interrupt\r
+ * @retval None \r
+ */\r
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_IT(FLASH_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if(NewState != DISABLE)\r
+ {\r
+ /* Enable the interrupt sources */\r
+ FLASH->CR |= FLASH_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the interrupt sources */\r
+ FLASH->CR &= ~(uint32_t)FLASH_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified FLASH flag is set or not.\r
+ * @param FLASH_FLAG: specifies the FLASH flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag \r
+ * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag\r
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag\r
+ * @arg FLASH_FLAG_EOP: FLASH End of Programming flag\r
+ * @retval The new state of FLASH_FLAG (SET or RESET).\r
+ */\r
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));\r
+\r
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the new state of FLASH_FLAG (SET or RESET) */\r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Clears the FLASH's pending flags.\r
+ * @param FLASH_FLAG: specifies the FLASH flags to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag\r
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag\r
+ * @arg FLASH_FLAG_EOP: FLASH End of Programming flag\r
+ * @retval None\r
+ */\r
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));\r
+ \r
+ /* Clear the flags */\r
+ FLASH->SR = FLASH_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Status.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: \r
+ * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.\r
+ */\r
+FLASH_Status FLASH_GetStatus(void)\r
+{\r
+ FLASH_Status FLASHstatus = FLASH_COMPLETE;\r
+ \r
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
+ {\r
+ FLASHstatus = FLASH_BUSY;\r
+ }\r
+ else \r
+ { \r
+ if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)\r
+ { \r
+ FLASHstatus = FLASH_ERROR_WRP;\r
+ }\r
+ else \r
+ {\r
+ if((FLASH->SR & (uint32_t)(FLASH_SR_PGERR)) != (uint32_t)0x00)\r
+ {\r
+ FLASHstatus = FLASH_ERROR_PROGRAM; \r
+ }\r
+ else\r
+ {\r
+ FLASHstatus = FLASH_COMPLETE;\r
+ }\r
+ }\r
+ }\r
+ /* Return the FLASH Status */\r
+ return FLASHstatus;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.\r
+ * @param Timeout: FLASH programming Timeout\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, \r
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)\r
+{ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check for the FLASH Status */\r
+ status = FLASH_GetStatus();\r
+ \r
+ /* Wait for a FLASH operation to complete or a TIMEOUT to occur */\r
+ while((status == FLASH_BUSY) && (Timeout != 0x00))\r
+ {\r
+ status = FLASH_GetStatus();\r
+ Timeout--;\r
+ }\r
+ \r
+ if(Timeout == 0x00 )\r
+ {\r
+ status = FLASH_TIMEOUT;\r
+ }\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ /**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_gpio.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the GPIO peripheral:\r
+ * + Initialization and Configuration functions\r
+ * + GPIO Read and Write functions\r
+ * + GPIO Alternate functions configuration functions\r
+ *\r
+ * @verbatim\r
+ *\r
+ *\r
+ ===========================================================================\r
+ ##### How to use this driver #####\r
+ ===========================================================================\r
+ [..]\r
+ (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()\r
+ (#) Configure the GPIO pin(s) using GPIO_Init()\r
+ Four possible configuration are available for each pin:\r
+ (++) Input: Floating, Pull-up, Pull-down.\r
+ (++) Output: Push-Pull (Pull-up, Pull-down or no Pull)\r
+ (++) Open Drain (Pull-up, Pull-down or no Pull).\r
+ (++) In output mode, the speed is configurable: Low, Medium, Fast or High.\r
+ (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)\r
+ Open Drain (Pull-up, Pull-down or no Pull).\r
+ (++) Analog: required mode when a pin is to be used as ADC channel,\r
+ DAC output or comparator input.\r
+ (#) Peripherals alternate function:\r
+ (++) For ADC, DAC and comparators, configure the desired pin in analog \r
+ mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN\r
+ (++) For other peripherals (TIM, USART...):\r
+ (+++) Connect the pin to the desired peripherals' Alternate \r
+ Function (AF) using GPIO_PinAFConfig() function. For PortC, \r
+ PortD and PortF, no configuration is needed.\r
+ (+++) Configure the desired pin in alternate function mode using\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ (+++) Select the type, pull-up/pull-down and output speed via \r
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
+ (+++) Call GPIO_Init() function\r
+ (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()\r
+ (#) To set/reset the level of a pin configured in output mode use\r
+ GPIO_SetBits()/GPIO_ResetBits()\r
+ (#) During and just after reset, the alternate functions are not active and \r
+ the GPIO pins are configured in input floating mode (except JTAG pins).\r
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as \r
+ general-purpose (PC14 and PC15, respectively) when the LSE oscillator \r
+ is off. The LSE has priority over the GPIO function.\r
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose \r
+ PD0 and PD1, respectively, when the HSE oscillator is off. The HSE has \r
+ priority over the GPIO function.\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_gpio.h"\r
+#include "stm32f0xx_rcc.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO \r
+ * @brief GPIO driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Private_Functions \r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_Group1 Initialization and Configuration\r
+ * @brief Initialization and Configuration\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and Configuration #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset \r
+ * values.\r
+ * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+\r
+ if(GPIOx == GPIOA)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);\r
+ }\r
+ else if(GPIOx == GPIOB)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);\r
+ }\r
+ else if(GPIOx == GPIOC)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);\r
+ }\r
+ else if(GPIOx == GPIOD)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if(GPIOx == GPIOF)\r
+ {\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the GPIOx peripheral according to the specified \r
+ * parameters in the GPIO_InitStruct.\r
+ * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.\r
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains\r
+ * the configuration information for the specified GPIO peripheral.\r
+ * @note The configured pins can be: GPIO_Pin_0 -> GPIO_Pin_15 for GPIOA, GPIOB and GPIOC,\r
+ * GPIO_Pin_0 -> GPIO_Pin_2 for GPIOD, GPIO_Pin_0 -> GPIO_Pin_3 for GPIOF.\r
+ * @retval None\r
+ */\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));\r
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));\r
+ assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));\r
+\r
+ /*-------------------------- Configure the port pins -----------------------*/\r
+ /*-- GPIO Mode Configuration --*/\r
+ for (pinpos = 0x00; pinpos < 0x10; pinpos++)\r
+ {\r
+ pos = ((uint32_t)0x01) << pinpos;\r
+\r
+ /* Get the port pins position */\r
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;\r
+\r
+ if (currentpin == pos)\r
+ {\r
+ if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))\r
+ {\r
+ /* Check Speed mode parameters */\r
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));\r
+\r
+ /* Speed mode configuration */\r
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));\r
+ GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));\r
+\r
+ /* Check Output mode parameters */\r
+ assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));\r
+\r
+ /* Output mode configuration */\r
+ GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));\r
+ GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));\r
+ }\r
+\r
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));\r
+\r
+ GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));\r
+\r
+ /* Pull-up Pull down resistor configuration */\r
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));\r
+ GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each GPIO_InitStruct member with its default value.\r
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will \r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ /* Reset GPIO init structure parameters values */\r
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;\r
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_2;\r
+ GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;\r
+ GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+}\r
+\r
+/**\r
+ * @brief Locks GPIO Pins configuration registers.\r
+ * The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r
+ * @note The configuration of the locked GPIO pins can no longer be modified\r
+ * until the next reset.\r
+ * @param GPIOx: where x can be (A or B) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ __IO uint32_t tmp = 0x00010000;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_LIST_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ tmp |= GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Reset LCKK bit */\r
+ GPIOx->LCKR = GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Read LCKK bit */\r
+ tmp = GPIOx->LCKR;\r
+ /* Read LCKK bit */\r
+ tmp = GPIOx->LCKR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Group2 GPIO Read and Write\r
+ * @brief GPIO Read and Write\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### GPIO Read and Write #####\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads the specified input port pin.\r
+ * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to read.\r
+ * @note This parameter can be GPIO_Pin_x where x can be:(0..15) for GPIOA, \r
+ * GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF.\r
+ * @retval The input port pin value.\r
+ */\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+\r
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified input port pin.\r
+ * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.\r
+ * @retval The input port pin value.\r
+ */\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+\r
+ return ((uint16_t)GPIOx->IDR);\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified output data port bit.\r
+ * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: Specifies the port bit to read.\r
+ * @note This parameter can be GPIO_Pin_x where x can be:(0..15) for GPIOA, \r
+ * GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF.\r
+ * @retval The output port pin value.\r
+ */\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+\r
+ if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO output data port.\r
+ * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.\r
+ * @retval GPIO output data port value.\r
+ */\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+\r
+ return ((uint16_t)GPIOx->ODR);\r
+}\r
+\r
+/**\r
+ * @brief Sets the selected data port bits.\r
+ * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * @note This parameter can be GPIO_Pin_x where x can be:(0..15) for GPIOA, \r
+ * GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF.\r
+ * @retval None\r
+ */\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ GPIOx->BSRR = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Clears the selected data port bits.\r
+ * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * @note This parameter can be GPIO_Pin_x where x can be: (0..15) for GPIOA, \r
+ * GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF.\r
+ * @retval None\r
+ */\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ GPIOx->BRR = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Sets or clears the selected data port bit.\r
+ * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * @param BitVal: specifies the value to be written to the selected bit.\r
+ * This parameter can be one of the BitAction enumeration values:\r
+ * @arg Bit_RESET: to clear the port pin\r
+ * @arg Bit_SET: to set the port pin\r
+ * @note The GPIO_Pin parameter can be GPIO_Pin_x where x can be: (0..15) for GPIOA, \r
+ * GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF. \r
+ * @retval None\r
+ */\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+ assert_param(IS_GPIO_BIT_ACTION(BitVal));\r
+\r
+ if (BitVal != Bit_RESET)\r
+ {\r
+ GPIOx->BSRR = GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BRR = GPIO_Pin ;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes data to the specified GPIO data port.\r
+ * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.\r
+ * @param PortVal: specifies the value to be written to the port output data \r
+ * register.\r
+ * @retval None\r
+ */\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+\r
+ GPIOx->ODR = PortVal;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions\r
+ * @brief GPIO Alternate functions configuration functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### GPIO Alternate functions configuration functions #####\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Writes data to the specified GPIO data port.\r
+ * @param GPIOx: where x can be (A or B) to select the GPIO peripheral.\r
+ * @param GPIO_PinSource: specifies the pin for the Alternate function.\r
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+ * @param GPIO_AF: selects the pin to used as Alternate function.\r
+ * This parameter can be one of the following value:\r
+ * @arg GPIO_AF_0:WKUP, EVENTOUT, TIM15, SPI1, TIM17,MCO, SWDAT, SWCLK, TIM14,\r
+ * BOOT,USART1, CEC, IR_OUT, SPI2 \r
+ * @arg GPIO_AF_1:USART2, CEC, Tim3, USART1, USART2,EVENTOUT, I2C1, I2C2, TIM15 \r
+ * @arg GPIO_AF_2:TIM2, TIM1, EVENTOUT, TIM16, TIM17.\r
+ * @arg GPIO_AF_3:TS, I2C1, TIM15, EVENTOUT \r
+ * @arg GPIO_AF_4:TIM14.\r
+ * @arg GPIO_AF_5:TIM16, TIM17.\r
+ * @arg GPIO_AF_6:EVENTOUT.\r
+ * @arg GPIO_AF_7:COMP1 OUT, COMP2 OUT \r
+ * @note The pin should already been configured in Alternate Function mode(AF)\r
+ * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ * @note Refer to the Alternate function mapping table in the device datasheet \r
+ * for the detailed mapping of the system and peripherals'alternate \r
+ * function I/O pins.\r
+ * @retval None\r
+ */\r
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)\r
+{\r
+ uint32_t temp = 0x00;\r
+ uint32_t temp_2 = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_LIST_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+ assert_param(IS_GPIO_AF(GPIO_AF));\r
+\r
+ temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));\r
+ GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));\r
+ temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;\r
+ GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_i2c.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Inter-Integrated circuit (I2C):\r
+ * + Initialization and Configuration\r
+ * + Communications handling\r
+ * + SMBUS management\r
+ * + I2C registers management\r
+ * + Data transfers management\r
+ * + DMA transfers management\r
+ * + Interrupts and flags management\r
+ *\r
+ * @verbatim\r
+ ============================================================================\r
+ ##### How to use this driver #####\r
+ ============================================================================\r
+ [..]\r
+ (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)\r
+ function for I2C1 or I2C2.\r
+ (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using \r
+ RCC_AHBPeriphClockCmd() function. \r
+ (#) Peripherals alternate function: \r
+ (++) Connect the pin to the desired peripherals' Alternate \r
+ Function (AF) using GPIO_PinAFConfig() function.\r
+ (++) Configure the desired pin in alternate function by:\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF\r
+ (++) Select the type, OpenDrain and speed via \r
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members\r
+ (++) Call GPIO_Init() function.\r
+ (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address \r
+ using the I2C_Init() function.\r
+ (#) Optionally you can enable/configure the following parameters without\r
+ re-initialization (i.e there is no need to call again I2C_Init() function):\r
+ (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.\r
+ (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.\r
+ (++) Enable the general call using the I2C_GeneralCallCmd() function.\r
+ (++) Enable the clock stretching using I2C_StretchClockCmd() function.\r
+ (++) Enable the PEC Calculation using I2C_CalculatePEC() function.\r
+ (++) For SMBus Mode:\r
+ (+++) Enable the SMBusAlert pin using I2C_SMBusAlertCmd() function.\r
+ (#) Enable the NVIC and the corresponding interrupt using the function\r
+ I2C_ITConfig() if you need to use interrupt mode.\r
+ (#) When using the DMA mode \r
+ (++) Configure the DMA using DMA_Init() function.\r
+ (++) Active the needed channel Request using I2C_DMACmd() function.\r
+ (#) Enable the I2C using the I2C_Cmd() function.\r
+ (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the \r
+ transfers. \r
+ [..]\r
+ (@) When using I2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability\r
+ must be enabled by setting the driving capability control bit in SYSCFG.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_i2c.h"\r
+#include "stm32f0xx_rcc.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C \r
+ * @brief I2C driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+#define CR1_CLEAR_MASK ((uint32_t)0x00CFE0FF) /*<! I2C CR1 clear register Mask */\r
+#define CR2_CLEAR_MASK ((uint32_t)0x07FF7FFF) /*<! I2C CR2 clear register Mask */\r
+#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! I2C TIMING clear register Mask */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Private_Functions\r
+ * @{\r
+ */\r
+\r
+\r
+/** @defgroup I2C_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provides a set of functions allowing to initialize the I2C Mode,\r
+ I2C Timing, I2C filters, I2C Addressing mode, I2C OwnAddress1.\r
+\r
+ [..] The I2C_Init() function follows the I2C configuration procedures (these procedures \r
+ are available in reference manual).\r
+\r
+ [..] When the Software Reset is performed using I2C_SoftwareResetCmd() function, the internal\r
+ states machines are reset and communication control bits, as well as status bits come \r
+ back to their reset value.\r
+\r
+ [..] Before enabling Stop mode using I2C_StopModeCmd() I2C Clock source must be set to\r
+ HSI and Digital filters must be disabled.\r
+\r
+ [..] Before enabling Own Address 2 via I2C_DualAddressCmd() function, OA2 and mask should be\r
+ configured using I2C_OwnAddress2Config() function.\r
+\r
+ [..] I2C_SlaveByteControlCmd() enable Slave byte control that allow user to get control of \r
+ each byte in slave mode when NBYTES is set to 0x01.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the I2Cx peripheral registers to their default reset values.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval None\r
+ */\r
+void I2C_DeInit(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ if (I2Cx == I2C1)\r
+ {\r
+ /* Enable I2C1 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);\r
+ /* Release I2C1 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ /* Enable I2C2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);\r
+ /* Release I2C2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the I2Cx peripheral according to the specified\r
+ * parameters in the I2C_InitStruct.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that\r
+ * contains the configuration information for the specified I2C peripheral.\r
+ * @retval None\r
+ */\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_ANALOG_FILTER(I2C_InitStruct->I2C_AnalogFilter));\r
+ assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter));\r
+ assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));\r
+ assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));\r
+ assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack));\r
+ assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));\r
+\r
+ /* Disable I2Cx Peripheral */\r
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);\r
+\r
+ /*---------------------------- I2Cx FILTERS Configuration ------------------*/\r
+ /* Get the I2Cx CR1 value */\r
+ tmpreg = I2Cx->CR1;\r
+ /* Clear I2Cx CR1 register */\r
+ tmpreg &= CR1_CLEAR_MASK;\r
+ /* Configure I2Cx: analog and digital filter */\r
+ /* Set ANFOFF bit according to I2C_AnalogFilter value */\r
+ /* Set DFN bits according to I2C_DigitalFilter value */\r
+ tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8);\r
+\r
+ /* Write to I2Cx CR1 */\r
+ I2Cx->CR1 = tmpreg;\r
+\r
+ /*---------------------------- I2Cx TIMING Configuration -------------------*/\r
+ /* Configure I2Cx: Timing */\r
+ /* Set TIMINGR bits according to I2C_Timing */\r
+ /* Write to I2Cx TIMING */\r
+ I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK;\r
+\r
+ /* Enable I2Cx Peripheral */\r
+ I2Cx->CR1 |= I2C_CR1_PE;\r
+\r
+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/\r
+ /* Clear tmpreg local variable */\r
+ tmpreg = 0;\r
+ /* Clear OAR1 register */\r
+ I2Cx->OAR1 = (uint32_t)tmpreg;\r
+ /* Clear OAR2 register */\r
+ I2Cx->OAR2 = (uint32_t)tmpreg;\r
+ /* Configure I2Cx: Own Address1 and acknowledged address */\r
+ /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */\r
+ /* Set OA1 bits according to I2C_OwnAddress1 value */\r
+ tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \\r
+ (uint32_t)I2C_InitStruct->I2C_OwnAddress1);\r
+ /* Write to I2Cx OAR1 */\r
+ I2Cx->OAR1 = tmpreg;\r
+ /* Enable Own Address1 acknowledgement */\r
+ I2Cx->OAR1 |= I2C_OAR1_OA1EN;\r
+\r
+ /*---------------------------- I2Cx MODE Configuration ---------------------*/\r
+ /* Configure I2Cx: mode */\r
+ /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */\r
+ tmpreg = I2C_InitStruct->I2C_Mode;\r
+ /* Write to I2Cx CR1 */\r
+ I2Cx->CR1 |= tmpreg;\r
+\r
+ /*---------------------------- I2Cx ACK Configuration ----------------------*/\r
+ /* Get the I2Cx CR2 value */\r
+ tmpreg = I2Cx->CR2;\r
+ /* Clear I2Cx CR2 register */\r
+ tmpreg &= CR2_CLEAR_MASK;\r
+ /* Configure I2Cx: acknowledgement */\r
+ /* Set NACK bit according to I2C_Ack value */\r
+ tmpreg |= I2C_InitStruct->I2C_Ack;\r
+ /* Write to I2Cx CR2 */\r
+ I2Cx->CR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each I2C_InitStruct member with its default value.\r
+ * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+ /*---------------- Reset I2C init structure parameters values --------------*/\r
+ /* Initialize the I2C_Timing member */\r
+ I2C_InitStruct->I2C_Timing = 0;\r
+ /* Initialize the I2C_AnalogFilter member */\r
+ I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable;\r
+ /* Initialize the I2C_DigitalFilter member */\r
+ I2C_InitStruct->I2C_DigitalFilter = 0;\r
+ /* Initialize the I2C_Mode member */\r
+ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;\r
+ /* Initialize the I2C_OwnAddress1 member */\r
+ I2C_InitStruct->I2C_OwnAddress1 = 0;\r
+ /* Initialize the I2C_Ack member */\r
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;\r
+ /* Initialize the I2C_AcknowledgedAddress member */\r
+ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C peripheral */\r
+ I2Cx->CR1 |= I2C_CR1_PE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C peripheral */\r
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C software reset.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C software reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Peripheral under reset */\r
+ I2Cx->CR1 |= I2C_CR1_SWRST;\r
+ }\r
+ else\r
+ {\r
+ /* Peripheral not under reset */\r
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SWRST);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C interrupts.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_IT_ERRI: Error interrupt mask\r
+ * @arg I2C_IT_TCI: Transfer Complete interrupt mask\r
+ * @arg I2C_IT_STOPI: Stop Detection interrupt mask\r
+ * @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask\r
+ * @arg I2C_IT_ADDRI: Address Match interrupt mask \r
+ * @arg I2C_IT_RXI: RX interrupt mask\r
+ * @arg I2C_IT_TXI: TX interrupt mask\r
+ * @param NewState: new state of the specified I2C interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_I2C_CONFIG_IT(I2C_IT));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C interrupts */\r
+ I2Cx->CR1 |= I2C_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C interrupts */\r
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the I2C Clock stretching.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx Clock stretching.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable clock stretching */\r
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH); \r
+ }\r
+ else\r
+ {\r
+ /* Disable clock stretching */\r
+ I2Cx->CR1 |= I2C_CR1_NOSTRETCH;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables I2C wakeup from stop mode.\r
+ * @param I2Cx: where x can be 1 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx stop mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_1_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable wakeup from stop mode */\r
+ I2Cx->CR1 |= I2C_CR1_WUPEN; \r
+ }\r
+ else\r
+ {\r
+ /* Disable wakeup from stop mode */ \r
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the I2C own address 2.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C own address 2.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable own address 2 */\r
+ I2Cx->OAR2 |= I2C_OAR2_OA2EN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable own address 2 */\r
+ I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN);\r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Configures the I2C slave own address 2 and mask.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Address: specifies the slave address to be programmed.\r
+ * @param Mask: specifies own address 2 mask to be programmed.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_OA2_NoMask: no mask.\r
+ * @arg I2C_OA2_Mask01: OA2[1] is masked and don't care.\r
+ * @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care.\r
+ * @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care.\r
+ * @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care.\r
+ * @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care.\r
+ * @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care.\r
+ * @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care.\r
+ * @retval None\r
+ */\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_OWN_ADDRESS2(Address));\r
+ assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask));\r
+ \r
+ /* Get the old register value */\r
+ tmpreg = I2Cx->OAR2;\r
+\r
+ /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0] */\r
+ tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK));\r
+\r
+ /* Set I2Cx SADD */\r
+ tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \\r
+ (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ;\r
+\r
+ /* Store the new register value */\r
+ I2Cx->OAR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the I2C general call mode.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C general call mode.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable general call mode */\r
+ I2Cx->CR1 |= I2C_CR1_GCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable general call mode */\r
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN);\r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Enables or disables the I2C slave byte control.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C slave byte control.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable slave byte control */\r
+ I2Cx->CR1 |= I2C_CR1_SBC;\r
+ }\r
+ else\r
+ {\r
+ /* Disable slave byte control */\r
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the slave address to be transmitted after start generation.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Address: specifies the slave address to be programmed.\r
+ * @note This function should be called before generating start condition.\r
+ * @retval None\r
+ */\r
+void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_SLAVE_ADDRESS(Address));\r
+ \r
+ /* Get the old register value */\r
+ tmpreg = I2Cx->CR2;\r
+\r
+ /* Reset I2Cx SADD bit [9:0] */\r
+ tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD);\r
+\r
+ /* Set I2Cx SADD */\r
+ tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD);\r
+\r
+ /* Store the new register value */\r
+ I2Cx->CR2 = tmpreg;\r
+}\r
+ \r
+/**\r
+ * @brief Enables or disables the I2C 10-bit addressing mode for the master.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C 10-bit addressing mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note This function should be called before generating start condition.\r
+ * @retval None\r
+ */\r
+void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable 10-bit addressing mode */\r
+ I2Cx->CR2 |= I2C_CR2_ADD10;\r
+ }\r
+ else\r
+ {\r
+ /* Disable 10-bit addressing mode */\r
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10);\r
+ }\r
+} \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup I2C_Group2 Communications handling functions\r
+ * @brief Communications handling functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Communications handling functions #####\r
+ =============================================================================== \r
+ [..] This section provides a set of functions that handles I2C communication.\r
+\r
+ [..] Automatic End mode is enabled using I2C_AutoEndCmd() function. When Reload\r
+ mode is enabled via I2C_ReloadCmd() AutoEnd bit has no effect.\r
+\r
+ [..] I2C_NumberOfBytesConfig() function set the number of bytes to be transferred,\r
+ this configuration should be done before generating start condition in master \r
+ mode.\r
+\r
+ [..] When switching from master write operation to read operation in 10Bit addressing\r
+ mode, master can only sends the 1st 7 bits of the 10 bit address, followed by \r
+ Read direction by enabling HEADR bit using I2C_10BitAddressHeader() function.\r
+\r
+ [..] In master mode, when transferring more than 255 bytes Reload mode should be used\r
+ to handle communication. In the first phase of transfer, Nbytes should be set to \r
+ 255. After transferring these bytes TCR flag is set and I2C_TCRTransferHandling()\r
+ function should be called to handle remaining communication.\r
+\r
+ [..] In master mode, when software end mode is selected when all data is transferred\r
+ TC flag is set I2C_TCRTransferHandling() function should be called to generate STOP\r
+ or generate ReStart.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Enables or disables the I2C automatic end mode (stop condition is \r
+ * automatically sent when nbytes data are transferred).\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C automatic end mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note This function has effect if Reload mode is disabled.\r
+ * @retval None\r
+ */\r
+void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable Auto end mode */\r
+ I2Cx->CR2 |= I2C_CR2_AUTOEND;\r
+ }\r
+ else\r
+ {\r
+ /* Disable Auto end mode */\r
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND);\r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Enables or disables the I2C nbytes reload mode.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the nbytes reload mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable Auto Reload mode */\r
+ I2Cx->CR2 |= I2C_CR2_RELOAD;\r
+ }\r
+ else\r
+ {\r
+ /* Disable Auto Reload mode */\r
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the number of bytes to be transmitted/received.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Number_Bytes: specifies the number of bytes to be programmed.\r
+ * @retval None\r
+ */\r
+void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint16_t Number_Bytes)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = I2Cx->CR2;\r
+\r
+ /* Reset I2Cx Nbytes bit [7:0] */\r
+ tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES);\r
+\r
+ /* Set I2Cx Nbytes */\r
+ tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES);\r
+\r
+ /* Store the new register value */\r
+ I2Cx->CR2 = tmpreg;\r
+} \r
+ \r
+/**\r
+ * @brief Configures the type of transfer request for the master.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_Direction: specifies the transfer request direction to be programmed.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_Direction_Transmitter: Master request a write transfer\r
+ * @arg I2C_Direction_Receiver: Master request a read transfer \r
+ * @retval None\r
+ */\r
+void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction)\r
+{\r
+/* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));\r
+ \r
+ /* Test on the direction to set/reset the read/write bit */\r
+ if (I2C_Direction == I2C_Direction_Transmitter)\r
+ {\r
+ /* Request a write Transfer */\r
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN);\r
+ }\r
+ else\r
+ {\r
+ /* Request a read Transfer */\r
+ I2Cx->CR2 |= I2C_CR2_RD_WRN;\r
+ }\r
+} \r
+ \r
+/**\r
+ * @brief Generates I2Cx communication START condition.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C START condition generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a START condition */\r
+ I2Cx->CR2 |= I2C_CR2_START;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the START condition generation */\r
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START);\r
+ }\r
+} \r
+ \r
+/**\r
+ * @brief Generates I2Cx communication STOP condition.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C STOP condition generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a STOP condition */\r
+ I2Cx->CR2 |= I2C_CR2_STOP;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the STOP condition generation */\r
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP);\r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Enables or disables the I2C 10-bit header only mode with read direction.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C 10-bit header only mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note This mode can be used only when switching from master transmitter mode \r
+ * to master receiver mode.\r
+ * @retval None\r
+ */\r
+void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable 10-bit header only mode */\r
+ I2Cx->CR2 |= I2C_CR2_HEAD10R;\r
+ }\r
+ else\r
+ {\r
+ /* Disable 10-bit header only mode */\r
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R);\r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Generates I2C communication Acknowledge.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the Acknowledge.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable ACK generation */\r
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK); \r
+ }\r
+ else\r
+ {\r
+ /* Enable NACK generation */\r
+ I2Cx->CR2 |= I2C_CR2_NACK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the I2C slave matched address .\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval The value of the slave matched address .\r
+ */\r
+uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ \r
+ /* Return the slave matched address in the SR1 register */\r
+ return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ;\r
+}\r
+\r
+/**\r
+ * @brief Returns the I2C slave received request.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval The value of the received request.\r
+ */\r
+uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ uint16_t direction = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ \r
+ /* Return the slave matched address in the SR1 register */\r
+ tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR);\r
+ \r
+ /* If write transfer is requested */\r
+ if (tmpreg == 0)\r
+ {\r
+ /* write transfer is requested */\r
+ direction = I2C_Direction_Transmitter;\r
+ }\r
+ else\r
+ {\r
+ /* Read transfer is requested */\r
+ direction = I2C_Direction_Receiver;\r
+ } \r
+ return direction;\r
+}\r
+\r
+/**\r
+ * @brief Handles I2Cx communication when TCR flag is set.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Number_Bytes: specifies the number of bytes to be programmed.\r
+ * This parameter must be a value between 0 and 255.\r
+ * @param ReloadEndMode: new state of the I2C START condition generation.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_Reload_Mode: Enable Reload mode .\r
+ * @arg I2C_AutoEnd_Mode: Enable Automatic end mode.\r
+ * @arg I2C_SoftEnd_Mode: Enable Software end mode.\r
+ * @retval None\r
+ */\r
+void I2C_TCRTransferHandling(I2C_TypeDef* I2Cx, uint16_t Number_Bytes, uint32_t ReloadEndMode)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_RELOAD_END_MODE(ReloadEndMode));\r
+ \r
+ /* Get the CR2 register value */\r
+ tmpreg = I2Cx->CR2;\r
+ \r
+ /* clear tmpreg specific bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND ));\r
+ \r
+ /* update tmpreg */\r
+ tmpreg |= (uint32_t)((((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | (uint32_t)ReloadEndMode);\r
+ \r
+ /* update CR2 register */\r
+ I2Cx->CR2 = tmpreg; \r
+} \r
+ \r
+/**\r
+ * @brief Handles I2Cx communication when TC flag is set.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Number_Bytes: specifies the number of bytes to be programmed.\r
+ * This parameter must be a value between 0 and 255.\r
+ * @param StartStopMode: new state of the I2C START condition generation.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0).\r
+ * @arg I2C_Generate_Start_Read: Generate Restart for read request.\r
+ * @arg I2C_Generate_Start_Write: Generate Restart for write request.\r
+ * @retval None\r
+ */\r
+void I2C_TCTransferHandling(I2C_TypeDef* I2Cx, uint16_t Number_Bytes, uint32_t StartStopMode)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_START_STOP_MODE(StartStopMode));\r
+ \r
+ /* Get the CR2 register value */\r
+ tmpreg = I2Cx->CR2;\r
+ \r
+ /* clear tmpreg specific bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_NBYTES | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RD_WRN ));\r
+ \r
+ /* update tmpreg */\r
+ tmpreg |= (uint32_t)((((uint32_t)Number_Bytes << 16 ) & (uint32_t)I2C_CR2_NBYTES) | (uint32_t)StartStopMode);\r
+ \r
+ /* update CR2 register */\r
+ I2Cx->CR2 = tmpreg; \r
+} \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup I2C_Group3 SMBUS management functions\r
+ * @brief SMBUS management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### SMBUS management functions #####\r
+ =============================================================================== \r
+ [..] This section provides a set of functions that handles SMBus communication\r
+ and timeouts detection.\r
+\r
+ [..] The SMBus Device default address (0b1100 001) is enabled by calling I2C_Init()\r
+ function and setting I2C_Mode member of I2C_InitTypeDef() structure to \r
+ I2C_Mode_SMBusDevice.\r
+\r
+ [..] The SMBus Host address (0b0001 000) is enabled by calling I2C_Init()\r
+ function and setting I2C_Mode member of I2C_InitTypeDef() structure to \r
+ I2C_Mode_SMBusHost.\r
+\r
+ [..] The Alert Response Address (0b0001 100) is enabled using I2C_SMBusAlertCmd()\r
+ function.\r
+\r
+ [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be \r
+ configured (in accordance to SMBus specification) using I2C_TimeoutBConfig() \r
+ function then I2C_ExtendedClockTimeoutCmd() function should be called to enable\r
+ the detection.\r
+\r
+ [..] SCL low timeout is detected by configuring TIMEOUTB using I2C_TimeoutBConfig()\r
+ function followed by the call of I2C_ClockTimeoutCmd(). When adding to this \r
+ procedure the call of I2C_IdleClockTimeoutCmd() function, Bus Idle condition \r
+ (both SCL and SDA high) is detected also.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables I2C SMBus alert.\r
+ * @param I2Cx: where x can be 1 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx SMBus alert.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_1_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable SMBus alert */\r
+ I2Cx->CR1 |= I2C_CR1_ALERTEN; \r
+ }\r
+ else\r
+ {\r
+ /* Disable SMBus alert */ \r
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables I2C Clock Timeout (SCL Timeout detection).\r
+ * @param I2Cx: where x can be 1 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx clock Timeout.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_1_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable Clock Timeout */\r
+ I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN; \r
+ }\r
+ else\r
+ {\r
+ /* Disable Clock Timeout */ \r
+ I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection).\r
+ * @param I2Cx: where x can be 1 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx Extended clock Timeout.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_1_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable Clock Timeout */\r
+ I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN; \r
+ }\r
+ else\r
+ {\r
+ /* Disable Clock Timeout */ \r
+ I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA \r
+ * high detection).\r
+ * @param I2Cx: where x can be 1 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx Idle clock Timeout.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_1_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable Clock Timeout */\r
+ I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE; \r
+ }\r
+ else\r
+ {\r
+ /* Disable Clock Timeout */ \r
+ I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus \r
+ * idle SCL and SDA high when TIDLE = 1).\r
+ * @param I2Cx: where x can be 1 to select the I2C peripheral.\r
+ * @param Timeout: specifies the TimeoutA to be programmed. \r
+ * @retval None\r
+ */\r
+void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_1_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_TIMEOUT(Timeout));\r
+ \r
+ /* Get the old register value */\r
+ tmpreg = I2Cx->TIMEOUTR;\r
+\r
+ /* Reset I2Cx TIMEOUTA bit [11:0] */\r
+ tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA);\r
+\r
+ /* Set I2Cx TIMEOUTA */\r
+ tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ;\r
+\r
+ /* Store the new register value */\r
+ I2Cx->TIMEOUTR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the I2C Bus Timeout B (SCL cumulative Timeout).\r
+ * @param I2Cx: where x can be 1 to select the I2C peripheral.\r
+ * @param Timeout: specifies the TimeoutB to be programmed. \r
+ * @retval None\r
+ */\r
+void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_1_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_TIMEOUT(Timeout));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = I2Cx->TIMEOUTR;\r
+\r
+ /* Reset I2Cx TIMEOUTB bit [11:0] */\r
+ tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB);\r
+\r
+ /* Set I2Cx TIMEOUTB */\r
+ tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ;\r
+\r
+ /* Store the new register value */\r
+ I2Cx->TIMEOUTR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables I2C PEC calculation.\r
+ * @param I2Cx: where x can be 1 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx PEC calculation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_1_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable PEC calculation */\r
+ I2Cx->CR1 |= I2C_CR1_PECEN; \r
+ }\r
+ else\r
+ {\r
+ /* Disable PEC calculation */ \r
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables I2C PEC transmission/reception request.\r
+ * @param I2Cx: where x can be 1 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx PEC request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_1_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable PEC transmission/reception request */\r
+ I2Cx->CR1 |= I2C_CR2_PECBYTE; \r
+ }\r
+ else\r
+ {\r
+ /* Disable PEC transmission/reception request */ \r
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the I2C PEC.\r
+ * @param I2Cx: where x can be 1 to select the I2C peripheral.\r
+ * @retval The value of the PEC .\r
+ */\r
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_1_PERIPH(I2Cx));\r
+ \r
+ /* Return the slave matched address in the SR1 register */\r
+ return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup I2C_Group4 I2C registers management functions\r
+ * @brief I2C registers management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### I2C registers management functions #####\r
+ =============================================================================== \r
+ [..] This section provides a function that allow user the read of I2C registers \r
+ value.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Reads the specified I2C register and returns its value.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_Register: specifies the register to read.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_Register_CR1: CR1 register.\r
+ * @arg I2C_Register_CR2: CR2 register.\r
+ * @arg I2C_Register_OAR1: OAR1 register.\r
+ * @arg I2C_Register_OAR2: OAR2 register.\r
+ * @arg I2C_Register_TIMINGR: TIMING register.\r
+ * @arg I2C_Register_TIMEOUTR: TIMEOUTR register.\r
+ * @arg I2C_Register_ISR: ISR register.\r
+ * @arg I2C_Register_ICR: ICR register.\r
+ * @arg I2C_Register_PECR: PECR register.\r
+ * @arg I2C_Register_RXDR: RXDR register.\r
+ * @arg I2C_Register_TXDR: TXDR register.\r
+ * @retval The value of the read register.\r
+ */\r
+uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_REGISTER(I2C_Register));\r
+\r
+ tmp = (uint32_t)I2Cx;\r
+ tmp += I2C_Register;\r
+\r
+ /* Return the selected register value */\r
+ return (*(__IO uint32_t *) tmp);\r
+}\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup I2C_Group5 Data transfers management functions\r
+ * @brief Data transfers management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Data transfers management functions #####\r
+ =============================================================================== \r
+ [..] This subsection provides a set of functions allowing to manage \r
+ the I2C data transfers.\r
+\r
+ [..] The read access of the I2C_RXDR register can be done using \r
+ the I2C_ReceiveData() function and returns the received value.\r
+ Whereas a write access to the I2C_TXDR can be done using I2C_SendData()\r
+ function and stores the written data into TXDR.\r
+@endverbatim\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @brief Sends a data byte through the I2Cx peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Data: Byte to be transmitted..\r
+ * @retval None\r
+ */\r
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ \r
+ /* Write in the DR register the data to be sent */\r
+ I2Cx->TXDR = (uint8_t)Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the I2Cx peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval The value of the received data.\r
+ */\r
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ \r
+ /* Return the data in the DR register */\r
+ return (uint8_t)I2Cx->RXDR;\r
+} \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup I2C_Group6 DMA transfers management functions\r
+ * @brief DMA transfers management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### DMA transfers management functions #####\r
+ =============================================================================== \r
+ [..] This section provides two functions that can be used only in DMA mode.\r
+ [..] In DMA Mode, the I2C communication can be managed by 2 DMA Channel \r
+ requests:\r
+ (#) I2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request.\r
+ (#) I2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request.\r
+ [..] In this Mode it is advised to use the following function:\r
+ (+) I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);\r
+@endverbatim\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @brief Enables or disables the I2C DMA interface.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_DMAReq_Tx: Tx DMA transfer request\r
+ * @arg I2C_DMAReq_Rx: Rx DMA transfer request\r
+ * @param NewState: new state of the selected I2C DMA transfer request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_I2C_DMA_REQ(I2C_DMAReq));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C DMA requests */\r
+ I2Cx->CR1 |= I2C_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C DMA requests */\r
+ I2Cx->CR1 &= (uint32_t)~I2C_DMAReq;\r
+ }\r
+}\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup I2C_Group7 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to configure the I2C Interrupts \r
+ sources and check or clear the flags or pending bits status.\r
+ The user should identify which mode will be used in his application to manage \r
+ the communication: Polling mode, Interrupt mode or DMA mode(refer I2C_Group6).\r
+\r
+ *** Polling Mode ***\r
+ ====================\r
+ [..] In Polling Mode, the I2C communication can be managed by 15 flags:\r
+ (#) I2C_FLAG_TXE: to indicate the status of Transmit data register empty flag.\r
+ (#) I2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag .\r
+ (#) I2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag.\r
+ (#) I2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode).\r
+ (#) I2C_FLAG_NACKF: to indicate the status of NACK received flag.\r
+ (#) I2C_FLAG_STOPF: to indicate the status of STOP detection flag.\r
+ (#) I2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode).\r
+ (#) I2C_FLAG_TCR: to indicate the status of Transfer complete reload flag.\r
+ (#) I2C_FLAG_BERR: to indicate the status of Bus error flag.\r
+ (#) I2C_FLAG_ARLO: to indicate the status of Arbitration lost flag.\r
+ (#) I2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag.\r
+ (#) I2C_FLAG_PECERR: to indicate the status of PEC error in reception flag.\r
+ (#) I2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.\r
+ (#) I2C_FLAG_ALERT: to indicate the status of SMBus Alert flag.\r
+ (#) I2C_FLAG_BUSY: to indicate the status of Bus busy flag.\r
+\r
+ [..] In this Mode it is advised to use the following functions:\r
+ (+) FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+ (+) void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+\r
+ [..]\r
+ (@)Do not use the BUSY flag to handle each data transmission or reception.It is \r
+ better to use the TXIS and RXNE flags instead.\r
+\r
+ *** Interrupt Mode ***\r
+ ======================\r
+ [..] In Interrupt Mode, the I2C communication can be managed by 7 interrupt sources\r
+ and 15 pending bits: \r
+ [..] Interrupt Source:\r
+ (#) I2C_IT_ERRI: specifies the interrupt source for the Error interrupt.\r
+ (#) I2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt.\r
+ (#) I2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt.\r
+ (#) I2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt.\r
+ (#) I2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt.\r
+ (#) I2C_IT_RXI: specifies the interrupt source for the RX interrupt.\r
+ (#) I2C_IT_TXI: specifies the interrupt source for the TX interrupt.\r
+\r
+ [..] Pending Bits:\r
+ (#) I2C_IT_TXIS: to indicate the status of Transmit interrupt status flag.\r
+ (#) I2C_IT_RXNE: to indicate the status of Receive data register not empty flag.\r
+ (#) I2C_IT_ADDR: to indicate the status of Address matched flag (slave mode).\r
+ (#) I2C_IT_NACKF: to indicate the status of NACK received flag.\r
+ (#) I2C_IT_STOPF: to indicate the status of STOP detection flag.\r
+ (#) I2C_IT_TC: to indicate the status of Transfer complete flag (master mode).\r
+ (#) I2C_IT_TCR: to indicate the status of Transfer complete reload flag.\r
+ (#) I2C_IT_BERR: to indicate the status of Bus error flag.\r
+ (#) I2C_IT_ARLO: to indicate the status of Arbitration lost flag.\r
+ (#) I2C_IT_OVR: to indicate the status of Overrun/Underrun flag.\r
+ (#) I2C_IT_PECERR: to indicate the status of PEC error in reception flag.\r
+ (#) I2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.\r
+ (#) I2C_IT_ALERT: to indicate the status of SMBus Alert flag.\r
+\r
+ [..] In this Mode it is advised to use the following functions:\r
+ (+) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+ (+) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+\r
+@endverbatim\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Checks whether the specified I2C flag is set or not.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_FLAG: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_FLAG_TXE: Transmit data register empty\r
+ * @arg I2C_FLAG_TXIS: Transmit interrupt status\r
+ * @arg I2C_FLAG_RXNE: Receive data register not empty\r
+ * @arg I2C_FLAG_ADDR: Address matched (slave mode)\r
+ * @arg I2C_FLAG_NACKF: NACK received flag\r
+ * @arg I2C_FLAG_STOPF: STOP detection flag\r
+ * @arg I2C_FLAG_TC: Transfer complete (master mode)\r
+ * @arg I2C_FLAG_TCR: Transfer complete reload\r
+ * @arg I2C_FLAG_BERR: Bus error\r
+ * @arg I2C_FLAG_ARLO: Arbitration lost\r
+ * @arg I2C_FLAG_OVR: Overrun/Underrun\r
+ * @arg I2C_FLAG_PECERR: PEC error in reception\r
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag\r
+ * @arg I2C_FLAG_ALERT: SMBus Alert\r
+ * @arg I2C_FLAG_BUSY: Bus busy\r
+ * @retval The new state of I2C_FLAG (SET or RESET).\r
+ */\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));\r
+ \r
+ /* Get the ISR register value */\r
+ tmpreg = I2Cx->ISR;\r
+ \r
+ /* Get flag status */\r
+ tmpreg &= I2C_FLAG;\r
+ \r
+ if(tmpreg != 0)\r
+ {\r
+ /* I2C_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+} \r
+\r
+/**\r
+ * @brief Clears the I2Cx's pending flags.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_FLAG: specifies the flag to clear. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_FLAG_ADDR: Address matched (slave mode)\r
+ * @arg I2C_FLAG_NACKF: NACK received flag\r
+ * @arg I2C_FLAG_STOPF: STOP detection flag\r
+ * @arg I2C_FLAG_BERR: Bus error\r
+ * @arg I2C_FLAG_ARLO: Arbitration lost\r
+ * @arg I2C_FLAG_OVR: Overrun/Underrun\r
+ * @arg I2C_FLAG_PECERR: PEC error in reception\r
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag\r
+ * @arg I2C_FLAG_ALERT: SMBus Alert\r
+ * @retval The new state of I2C_FLAG (SET or RESET).\r
+ */\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));\r
+\r
+ /* Clear the selected flag */\r
+ I2Cx->ICR = I2C_FLAG;\r
+ }\r
+\r
+/**\r
+ * @brief Checks whether the specified I2C interrupt has occurred or not.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_IT_TXIS: Transmit interrupt status\r
+ * @arg I2C_IT_RXNE: Receive data register not empty\r
+ * @arg I2C_IT_ADDR: Address matched (slave mode)\r
+ * @arg I2C_IT_NACKF: NACK received flag\r
+ * @arg I2C_IT_STOPF: STOP detection flag\r
+ * @arg I2C_IT_TC: Transfer complete (master mode)\r
+ * @arg I2C_IT_TCR: Transfer complete reload\r
+ * @arg I2C_IT_BERR: Bus error\r
+ * @arg I2C_IT_ARLO: Arbitration lost\r
+ * @arg I2C_IT_OVR: Overrun/Underrun\r
+ * @arg I2C_IT_PECERR: PEC error in reception\r
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag\r
+ * @arg I2C_IT_ALERT: SMBus Alert\r
+ * @retval The new state of I2C_IT (SET or RESET).\r
+ */\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ ITStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_GET_IT(I2C_IT));\r
+ \r
+ /* Get the ISR register value */\r
+ tmpreg = I2Cx->ISR;\r
+ \r
+ /* Get flag status */\r
+ tmpreg &= I2C_IT;\r
+ \r
+ if(tmpreg != 0)\r
+ {\r
+ /* I2C_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+} \r
+\r
+/**\r
+ * @brief Clears the I2Cx's interrupt pending bits.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_IT_ADDR: Address matched (slave mode)\r
+ * @arg I2C_IT_NACKF: NACK received flag\r
+ * @arg I2C_IT_STOPF: STOP detection flag\r
+ * @arg I2C_IT_BERR: Bus error\r
+ * @arg I2C_IT_ARLO: Arbitration lost\r
+ * @arg I2C_IT_OVR: Overrun/Underrun\r
+ * @arg I2C_IT_PECERR: PEC error in reception\r
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag\r
+ * @arg I2C_IT_ALERT: SMBus Alert\r
+ * @retval The new state of I2C_IT (SET or RESET).\r
+ */\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLEAR_IT(I2C_IT));\r
+\r
+ /* Clear the selected flag */\r
+ I2Cx->ICR = I2C_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_iwdg.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Independent watchdog (IWDG) peripheral: \r
+ * + Prescaler and Counter configuration\r
+ * + IWDG activation\r
+ * + Flag management\r
+ *\r
+ * @verbatim \r
+ * \r
+ ============================================================================== \r
+ ##### IWDG features #####\r
+ ============================================================================== \r
+ [..] The IWDG can be started by either software or hardware (configurable\r
+ through option byte).\r
+ \r
+ [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and\r
+ thus stays active even if the main clock fails.\r
+ Once the IWDG is started, the LSI is forced ON and cannot be disabled\r
+ (LSI cannot be disabled too), and the counter starts counting down from \r
+ the reset value of 0xFFF. When it reaches the end of count value (0x000)\r
+ a system reset is generated.\r
+ The IWDG counter should be reloaded at regular intervals to prevent\r
+ an MCU reset.\r
+ \r
+ [..] The IWDG is implemented in the VDD voltage domain that is still functional\r
+ in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).\r
+ \r
+ [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG\r
+ reset occurs.\r
+ \r
+ [..] Min-max timeout value @40KHz (LSI): ~0.1ms / ~28.3s\r
+ The IWDG timeout may vary due to LSI frequency dispersion. STM32F0xx\r
+ devices provide the capability to measure the LSI frequency (LSI clock\r
+ should be seleted as RTC clock which is internally connected to TIM10 CH1\r
+ input capture). The measured value can be used to have an IWDG timeout with\r
+ an acceptable accuracy. \r
+ For more information, please refer to the STM32F0xx Reference manual.\r
+ \r
+ ##### How to use this driver ##### \r
+ ============================================================================== \r
+ [..] This driver allows to use IWDG peripheral with either window option enabled\r
+ or disabled. To do so follow one of the two procedures below.\r
+ (#) Window option is enabled: \r
+ (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used\r
+ in software mode (no need to enable the LSI, it will be enabled\r
+ by hardware). \r
+ (++) Enable write access to IWDG_PR and IWDG_RLR registers using\r
+ IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.\r
+ (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.\r
+ (++) Configure the IWDG counter value using IWDG_SetReload() function.\r
+ This value will be loaded in the IWDG counter each time the counter\r
+ is reloaded, then the IWDG will start counting down from this value.\r
+ (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.\r
+ (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function.\r
+\r
+ (#) Window option is disabled: \r
+ (++) Enable write access to IWDG_PR and IWDG_RLR registers using\r
+ IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.\r
+ (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.\r
+ (++) Configure the IWDG counter value using IWDG_SetReload() function.\r
+ This value will be loaded in the IWDG counter each time the counter\r
+ is reloaded, then the IWDG will start counting down from this value.\r
+ (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.\r
+ (++) reload the IWDG counter at regular intervals during normal operation \r
+ to prevent an MCU reset, using IWDG_ReloadCounter() function.\r
+ (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used\r
+ in software mode (no need to enable the LSI, it will be enabled\r
+ by hardware).\r
+ \r
+ @endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_iwdg.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG \r
+ * @brief IWDG driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ---------------------- IWDG registers bit mask ----------------------------*/\r
+/* KR register bit mask */\r
+#define KR_KEY_RELOAD ((uint16_t)0xAAAA)\r
+#define KR_KEY_ENABLE ((uint16_t)0xCCCC)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup IWDG_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions\r
+ * @brief Prescaler and Counter configuration functions\r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Prescaler and Counter configuration functions #####\r
+ ============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.\r
+ * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers\r
+ * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers\r
+ * @retval None\r
+ */\r
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));\r
+ IWDG->KR = IWDG_WriteAccess;\r
+}\r
+\r
+/**\r
+ * @brief Sets IWDG Prescaler value.\r
+ * @param IWDG_Prescaler: specifies the IWDG Prescaler value.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_Prescaler_4: IWDG prescaler set to 4\r
+ * @arg IWDG_Prescaler_8: IWDG prescaler set to 8\r
+ * @arg IWDG_Prescaler_16: IWDG prescaler set to 16\r
+ * @arg IWDG_Prescaler_32: IWDG prescaler set to 32\r
+ * @arg IWDG_Prescaler_64: IWDG prescaler set to 64\r
+ * @arg IWDG_Prescaler_128: IWDG prescaler set to 128\r
+ * @arg IWDG_Prescaler_256: IWDG prescaler set to 256\r
+ * @retval None\r
+ */\r
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));\r
+ IWDG->PR = IWDG_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Sets IWDG Reload value.\r
+ * @param Reload: specifies the IWDG Reload value.\r
+ * This parameter must be a number between 0 and 0x0FFF.\r
+ * @retval None\r
+ */\r
+void IWDG_SetReload(uint16_t Reload)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_RELOAD(Reload));\r
+ IWDG->RLR = Reload;\r
+}\r
+\r
+/**\r
+ * @brief Reloads IWDG counter with value defined in the reload register\r
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void IWDG_ReloadCounter(void)\r
+{\r
+ IWDG->KR = KR_KEY_RELOAD;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the IWDG window value.\r
+ * @param WindowValue: specifies the window value to be compared to the downcounter.\r
+ * @retval None\r
+ */\r
+void IWDG_SetWindowValue(uint16_t WindowValue)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_WINDOW_VALUE(WindowValue));\r
+ IWDG->WINR = WindowValue;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Group2 IWDG activation function\r
+ * @brief IWDG activation function \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### IWDG activation function #####\r
+ ============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).\r
+ * @param None.\r
+ * @retval None.\r
+ */\r
+void IWDG_Enable(void)\r
+{\r
+ IWDG->KR = KR_KEY_ENABLE;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Group3 Flag management function \r
+ * @brief Flag management function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Flag management function ##### \r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified IWDG flag is set or not.\r
+ * @param IWDG_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_FLAG_PVU: Prescaler Value Update on going\r
+ * @arg IWDG_FLAG_RVU: Reload Value Update on going\r
+ * @arg IWDG_FLAG_WVU: Counter Window Value Update on going\r
+ * @retval The new state of IWDG_FLAG (SET or RESET).\r
+ */\r
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));\r
+ if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_misc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides all the miscellaneous firmware functions (add-on\r
+ * to CMSIS functions).\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_misc.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MISC \r
+ * @brief MISC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup MISC_Private_Functions\r
+ * @{\r
+ */\r
+/**\r
+ *\r
+@verbatim\r
+ *******************************************************************************\r
+ ##### Interrupts configuration functions #####\r
+ *******************************************************************************\r
+ [..] This section provide functions allowing to configure the NVIC interrupts\r
+ (IRQ). The Cortex-M0 exceptions are managed by CMSIS functions.\r
+ (#) Enable and Configure the priority of the selected IRQ Channels. \r
+ The priority can be 0..3. \r
+\r
+ -@- Lower priority values gives higher priority.\r
+ -@- Priority Order:\r
+ (#@) Lowest priority.\r
+ (#@) Lowest hardware priority (IRQn position). \r
+ \r
+@endverbatim\r
+*/\r
+\r
+/**\r
+ * @brief Initializes the NVIC peripheral according to the specified\r
+ * parameters in the NVIC_InitStruct.\r
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r
+ * function should be called before. \r
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains\r
+ * the configuration information for the specified NVIC peripheral.\r
+ * @retval None\r
+ */\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
+{\r
+ uint32_t tmppriority = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
+ assert_param(IS_NVIC_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPriority)); \r
+ \r
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
+ {\r
+ /* Compute the Corresponding IRQ Priority --------------------------------*/ \r
+ tmppriority = NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02];\r
+ tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)));\r
+ tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)); \r
+ \r
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02] = tmppriority;\r
+ \r
+ /* Enable the Selected IRQ Channels --------------------------------------*/\r
+ NVIC->ISER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Selected IRQ Channels -------------------------------------*/\r
+ NVIC->ICER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the condition for the system to enter low power mode.\r
+ * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.\r
+ * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.\r
+ * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.\r
+ * @param NewState: new state of LP condition. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_LP(LowPowerMode));\r
+ \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ SCB->SCR |= LowPowerMode;\r
+ }\r
+ else\r
+ {\r
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the SysTick clock source.\r
+ * @param SysTick_CLKSource: specifies the SysTick clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.\r
+ * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.\r
+ * @retval None\r
+ */\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
+ \r
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
+ {\r
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_pwr.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Power Controller (PWR) peripheral:\r
+ * + Backup Domain Access\r
+ * + PVD configuration\r
+ * + WakeUp pins configuration\r
+ * + Low Power modes configuration\r
+ * + Flags management\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_pwr.h"\r
+#include "stm32f0xx_rcc.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR \r
+ * @brief PWR driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* ------------------ PWR registers bit mask ------------------------ */\r
+\r
+/* CR register bit mask */\r
+#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)\r
+#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_Group1 Backup Domain Access function \r
+ * @brief Backup Domain Access function\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Backup Domain Access function #####\r
+ ==============================================================================\r
+\r
+ [..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers\r
+ and RTC backup registers) are protected against possible stray write accesses.\r
+ [..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void PWR_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables access to the Backup domain registers.\r
+ * @note If the HSE divided by 32 is used as the RTC clock, the \r
+ * Backup Domain Access should be kept enabled.\r
+ * @param NewState: new state of the access to the Backup domain registers.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_BackupAccessCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Backup Domain Access */\r
+ PWR->CR |= PWR_CR_DBP;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Backup Domain Access */\r
+ PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_DBP);\r
+ } \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group2 PVD configuration functions\r
+ * @brief PVD configuration functions \r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### PVD configuration functions #####\r
+ ==============================================================================\r
+ [..]\r
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold\r
+ selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\r
+ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the \r
+ PVD threshold. This event is internally connected to the EXTI line16\r
+ and can generate an interrupt if enabled through the EXTI registers.\r
+ (+) The PVD is stopped in Standby mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
+ * @param PWR_PVDLevel: specifies the PVD detection level\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_PVDLevel_0: PVD detection level set to 1.9V\r
+ * @arg PWR_PVDLevel_1: PVD detection level set to 2.1V\r
+ * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V\r
+ * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V\r
+ * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V\r
+ * @arg PWR_PVDLevel_5: PVD detection level set to 2.9V\r
+ * @arg PWR_PVDLevel_6: PVD detection level set to 3.1V\r
+ * @arg PWR_PVDLevel_7: PVD detection level set to 3.3V\r
+ * @retval None\r
+ */\r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));\r
+ \r
+ tmpreg = PWR->CR;\r
+ \r
+ /* Clear PLS[7:5] bits */\r
+ tmpreg &= CR_PLS_MASK;\r
+ \r
+ /* Set PLS[7:5] bits according to PWR_PVDLevel value */\r
+ tmpreg |= PWR_PVDLevel;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Power Voltage Detector(PVD).\r
+ * @param NewState: new state of the PVD.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_PVDCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the PVD */\r
+ PWR->CR |= PWR_CR_PVDE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PVD */\r
+ PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_PVDE);\r
+ } \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group3 WakeUp pins configuration functions\r
+ * @brief WakeUp pins configuration functions \r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### WakeUp pin configuration functions #####\r
+ ==============================================================================\r
+\r
+ (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are \r
+ forced in input pull down configuration and are active on rising edges.\r
+ (+) There are three WakeUp pins: WakeUp Pin 1 on PA.00 and WakeUp Pin 2 on PC.13.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the WakeUp Pin functionality.\r
+ * @param PWR_WakeUpPin: specifies the WakeUpPin.\r
+ * This parameter can be: PWR_WakeUpPin_1 or PWR_WakeUpPin_2.\r
+ * @param NewState: new state of the WakeUp Pin functionality.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the EWUPx pin */\r
+ PWR->CSR |= PWR_WakeUpPin;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the EWUPx pin */\r
+ PWR->CSR &= ~PWR_WakeUpPin;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup PWR_Group4 Low Power modes configuration functions\r
+ * @brief Low Power modes configuration functions \r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Low Power modes configuration functions #####\r
+ ==============================================================================\r
+\r
+ [..] The devices feature three low-power modes:\r
+ (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running.\r
+ (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode\r
+ (+) Standby mode: VCORE domain powered off\r
+\r
+ *** Sleep mode *** \r
+ ==================\r
+ [..] \r
+ (+) Entry:\r
+ (++) The Sleep mode is entered by executing the WFE() or WFI() instructions.\r
+ (+) Exit:\r
+ (++) Any peripheral interrupt acknowledged by the nested vectored interrupt \r
+ controller (NVIC) can wake up the device from Sleep mode.\r
+\r
+ *** Stop mode *** \r
+ =================\r
+ [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI,\r
+ the HSI14 and the HSE RC oscillators are disabled. Internal SRAM and register \r
+ contents are preserved.\r
+ The voltage regulator can be configured either in normal or low-power mode.\r
+\r
+ (+) Entry:\r
+ (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) \r
+ function with regulator in LowPower or with Regulator ON.\r
+ (+) Exit:\r
+ (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode\r
+ or any internal IPs (I2C, UASRT or CEC) wakeup event.\r
+\r
+ *** Standby mode *** \r
+ ====================\r
+ [..] The Standby mode allows to achieve the lowest power consumption. It is based \r
+ on the Cortex-M0 deepsleep mode, with the voltage regulator disabled. \r
+ The VCORE domain is consequently powered off. The PLL, the HSI, the HSI14 \r
+ oscillator and the HSE oscillator are also switched off. SRAM and register \r
+ contents are lost except for the Backup domain (RTC registers, RTC backup \r
+ registers and Standby circuitry).\r
+ \r
+ [..] The voltage regulator is OFF.\r
+\r
+ (+) Entry:\r
+ (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.\r
+ (+) Exit:\r
+ (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,\r
+ tamper event, time-stamp event, external reset in NRST pin, IWDG reset.\r
+\r
+ *** Auto-wakeup (AWU) from low-power mode *** \r
+ =============================================\r
+ [..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper \r
+ event, a time-stamp event, or a comparator event, without depending on an \r
+ external interrupt (Auto-wakeup mode).\r
+\r
+ (+) RTC auto-wakeup (AWU) from the Stop mode\r
+ (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:\r
+ (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt \r
+ or Event modes) using the EXTI_Init() function.\r
+ (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function\r
+ (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() \r
+ and RTC_AlarmCmd() functions.\r
+ (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it \r
+ is necessary to:\r
+ (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt \r
+ or Event modes) using the EXTI_Init() function.\r
+ (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() \r
+ function.\r
+ (+++) Configure the RTC to detect the tamper or time stamp event using the\r
+ RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()\r
+ functions.\r
+\r
+ (+) RTC auto-wakeup (AWU) from the Standby mode\r
+ (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:\r
+ (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.\r
+ (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() \r
+ and RTC_AlarmCmd() functions.\r
+ (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it \r
+ is necessary to:\r
+ (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() \r
+ function.\r
+ (+++) Configure the RTC to detect the tamper or time stamp event using the\r
+ RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()\r
+ functions.\r
+\r
+ (+) Comparator auto-wakeup (AWU) from the Stop mode\r
+ (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup\r
+ event, it is necessary to:\r
+ (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 \r
+ to be sensitive to to the selected edges (falling, rising or falling \r
+ and rising) (Interrupt or Event modes) using the EXTI_Init() function.\r
+ (+++) Configure the comparator to generate the event.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enters Sleep mode.\r
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode.\r
+ * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction\r
+ * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));\r
+\r
+ /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);\r
+ \r
+ /* Select SLEEP mode entry -------------------------------------------------*/\r
+ if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)\r
+ {\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters STOP mode.\r
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
+ * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r
+ * the HSI RC oscillator is selected as system clock.\r
+ * @note When the voltage regulator operates in low power mode, an additional \r
+ * startup delay is incurred when waking up from Stop mode. \r
+ * By keeping the internal regulator ON during Stop mode, the consumption \r
+ * is higher although the startup time is reduced.\r
+ * @param PWR_Regulator: specifies the regulator state in STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_Regulator_ON: STOP mode with regulator ON\r
+ * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode\r
+ * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction\r
+ * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));\r
+\r
+ /* Select the regulator state in STOP mode ---------------------------------*/\r
+ tmpreg = PWR->CR;\r
+ /* Clear PDDS and LPDSR bits */\r
+ tmpreg &= CR_DS_MASK;\r
+\r
+ /* Set LPDSR bit according to PWR_Regulator value */\r
+ tmpreg |= PWR_Regulator;\r
+\r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+\r
+ /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+\r
+ /* Select STOP mode entry --------------------------------------------------*/\r
+ if(PWR_STOPEntry == PWR_STOPEntry_WFI)\r
+ {\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); \r
+}\r
+\r
+/**\r
+ * @brief Enters STANDBY mode.\r
+ * @note In Standby mode, all I/O pins are high impedance except for:\r
+ * Reset pad (still available) \r
+ * RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, \r
+ * time-stamp, RTC Alarm out, or RTC clock calibration out.\r
+ * WKUP pin 1 (PA0) if enabled.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void PWR_EnterSTANDBYMode(void)\r
+{\r
+ /* Clear Wakeup flag */\r
+ PWR->CR |= PWR_CR_CWUF;\r
+\r
+ /* Select STANDBY mode */\r
+ PWR->CR |= PWR_CR_PDDS;\r
+\r
+ /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Group5 Flags management functions\r
+ * @brief Flags management functions \r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Flags management functions #####\r
+ ==============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified PWR flag is set or not.\r
+ * @param PWR_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup\r
+ * event was received from the WKUP pin or from the RTC alarm \r
+ * (Alarm A or Alarm B), RTC Tamper event or RTC TimeStamp event.\r
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the \r
+ * system was resumed from StandBy mode.\r
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD \r
+ * is enabled by the PWR_PVDCmd() function.\r
+ * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. \r
+ * This flag indicates the state of the internal voltage \r
+ * reference, VREFINT.\r
+ * @retval The new state of PWR_FLAG (SET or RESET).\r
+ */\r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));\r
+\r
+ if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the PWR's pending flags.\r
+ * @param PWR_FLAG: specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ * @retval None\r
+ */\r
+void PWR_ClearFlag(uint32_t PWR_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));\r
+\r
+ PWR->CR |= PWR_FLAG << 2;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_rcc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Reset and clock control (RCC) peripheral:\r
+ * + Internal/external clocks, PLL, CSS and MCO configuration\r
+ * + System, AHB and APB busses clocks configuration\r
+ * + Peripheral clocks configuration\r
+ * + Interrupts and flags management\r
+ *\r
+ @verbatim\r
+\r
+ ===============================================================================\r
+ ##### RCC specific features #####\r
+ ===============================================================================\r
+ [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS, \r
+ all peripherals are off except internal SRAM, Flash and SWD.\r
+ (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;\r
+ all peripherals mapped on these busses are running at HSI speed.\r
+ (#) The clock for all peripherals is switched off, except the SRAM and FLASH.\r
+ (#) All GPIOs are in input floating state, except the SWD pins which\r
+ are assigned to be used for debug purpose.\r
+ [..] Once the device started from reset, the user application has to:\r
+ (#) Configure the clock source to be used to drive the System clock\r
+ (if the application needs higher frequency/performance)\r
+ (#) Configure the System clock frequency and Flash settings\r
+ (#) Configure the AHB and APB busses prescalers\r
+ (#) Enable the clock for the peripheral(s) to be used\r
+ (#) Configure the clock source(s) for peripherals which clocks are not\r
+ derived from the System clock (ADC, CEC, I2C, USART, RTC and IWDG)\r
+\r
+ @endverbatim\r
+ \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_rcc.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC \r
+ * @brief RCC driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* ---------------------- RCC registers mask -------------------------------- */\r
+/* RCC Flag Mask */\r
+#define FLAG_MASK ((uint8_t)0x1F)\r
+\r
+/* CR register byte 2 (Bits[23:16]) base address */\r
+#define CR_BYTE2_ADDRESS ((uint32_t)0x40021002)\r
+\r
+/* CFGR register byte 3 (Bits[31:23]) base address */\r
+#define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007)\r
+\r
+/* CIR register byte 1 (Bits[15:8]) base address */\r
+#define CIR_BYTE1_ADDRESS ((uint32_t)0x40021009)\r
+\r
+/* CIR register byte 2 (Bits[23:16]) base address */\r
+#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002100A)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions\r
+ * @brief Internal and external clocks, PLL, CSS and MCO configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to configure the internal/external clocks,\r
+ PLL, CSS and MCO.\r
+ (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly \r
+ or through the PLL as System clock source.\r
+ The HSI clock can be used also to clock the USART, I2C and CEC peripherals.\r
+ (#) HSI14 (high-speed internal for ADC), 14 MHz factory-trimmed RC used to clock\r
+ the ADC peripheral.\r
+ (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC\r
+ clock source.\r
+ (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or\r
+ through the PLL as System clock source. Can be used also as RTC clock source.\r
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. \r
+ LSE can be used also to clock the USART and CEC peripherals. \r
+ (#) PLL (clocked by HSI or HSE), for System clock.\r
+ (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs \r
+ (HSE used directly or through PLL as System clock source), the System clock\r
+ is automatically switched to HSI and an interrupt is generated if enabled. \r
+ The interrupt is linked to the Cortex-M0 NMI (Non-Maskable Interrupt) \r
+ exception vector. \r
+ (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSI14, HSE, \r
+ PLL clock on PA8 pin.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the RCC clock configuration to the default reset state.\r
+ * @note The default reset state of the clock configuration is given below:\r
+ * @note HSI ON and used as system clock source \r
+ * @note HSI14, HSE and PLL OFF\r
+ * @note AHB, APB prescaler set to 1.\r
+ * @note CSS and MCO OFF\r
+ * @note All interrupts disabled\r
+ * @note However, this function doesn't modify the configuration of the\r
+ * @note Peripheral clocks\r
+ * @note LSI, LSE and RTC clocks\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_DeInit(void)\r
+{\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */\r
+ RCC->CFGR &= (uint32_t)0xF8FFB80C;\r
+ \r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */\r
+ RCC->CFGR &= (uint32_t)0xFFC0FFFF;\r
+\r
+ /* Reset PREDIV1[3:0] bits */\r
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;\r
+\r
+ /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */\r
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;\r
+ \r
+ /* Reset HSI14 bit */\r
+ RCC->CR2 &= (uint32_t)0xFFFFFFFE;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External High Speed oscillator (HSE).\r
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
+ * software should wait on HSERDY flag to be set indicating that HSE clock\r
+ * is stable and can be used to clock the PLL and/or system clock.\r
+ * @note HSE state can not be changed if it is used directly or through the\r
+ * PLL as system clock. In this case, you have to select another source\r
+ * of the system clock then change the HSE state (ex. disable it).\r
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.\r
+ * @note This function resets the CSSON bit, so if the Clock security system(CSS)\r
+ * was previously enabled you have to enable it again after calling this\r
+ * function.\r
+ * @param RCC_HSE: specifies the new state of the HSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after\r
+ * 6 HSE oscillator clock cycles.\r
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator\r
+ * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_HSEConfig(uint8_t RCC_HSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSE(RCC_HSE));\r
+\r
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r
+ *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;\r
+\r
+ /* Set the new HSE configuration -------------------------------------------*/\r
+ *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Waits for HSE start-up.\r
+ * @note This function waits on HSERDY flag to be set and return SUCCESS if \r
+ * this flag is set, otherwise returns ERROR if the timeout is reached \r
+ * and this flag is not set. The timeout value is defined by the constant\r
+ * HSE_STARTUP_TIMEOUT in stm32f0xx.h file. You can tailor it depending\r
+ * on the HSE crystal used in your application.\r
+ * - The HSE is stopped by hardware when entering STOP and STANDBY modes.\r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: HSE oscillator is stable and ready to use\r
+ * - ERROR: HSE oscillator not yet ready\r
+ */\r
+ErrorStatus RCC_WaitForHSEStartUp(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0;\r
+ ErrorStatus status = ERROR;\r
+ FlagStatus HSEStatus = RESET;\r
+ \r
+ /* Wait till HSE is ready and if timeout is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r
+ StartUpCounter++; \r
+ } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));\r
+ \r
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ } \r
+ return (status);\r
+}\r
+\r
+/**\r
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal HSI RC.\r
+ * Refer to the Application Note AN3300 for more details on how to \r
+ * calibrate the HSI.\r
+ * @param HSICalibrationValue: specifies the HSI calibration trimming value.\r
+ * This parameter must be a number between 0 and 0x1F.\r
+ * @retval None\r
+ */\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));\r
+ \r
+ tmpreg = RCC->CR;\r
+ \r
+ /* Clear HSITRIM[4:0] bits */\r
+ tmpreg &= ~RCC_CR_HSITRIM;\r
+ \r
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r
+ tmpreg |= (uint32_t)HSICalibrationValue << 3;\r
+\r
+ /* Store the new value */\r
+ RCC->CR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).\r
+ * @note After enabling the HSI, the application software should wait on \r
+ * HSIRDY flag to be set indicating that HSI clock is stable and can\r
+ * be used to clock the PLL and/or system clock.\r
+ * @note HSI can not be stopped if it is used directly or through the PLL\r
+ * as system clock. In this case, you have to select another source \r
+ * of the system clock then stop the HSI.\r
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.\r
+ * @param NewState: new state of the HSI.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
+ * clock cycles.\r
+ * @retval None\r
+ */\r
+void RCC_HSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->CR |= RCC_CR_HSION;\r
+ }\r
+ else\r
+ {\r
+ RCC->CR &= ~RCC_CR_HSION;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Adjusts the Internal High Speed oscillator for ADC (HSI14) \r
+ * calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal HSI RC.\r
+ * Refer to the Application Note AN3300 for more details on how to \r
+ * calibrate the HSI14.\r
+ * @param HSI14CalibrationValue: specifies the HSI14 calibration trimming value.\r
+ * This parameter must be a number between 0 and 0x1F.\r
+ * @retval None\r
+ */\r
+void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSI14_CALIBRATION_VALUE(HSI14CalibrationValue));\r
+ \r
+ tmpreg = RCC->CR2;\r
+ \r
+ /* Clear HSI14TRIM[4:0] bits */\r
+ tmpreg &= ~RCC_CR2_HSI14TRIM;\r
+ \r
+ /* Set the HSITRIM14[4:0] bits according to HSI14CalibrationValue value */\r
+ tmpreg |= (uint32_t)HSI14CalibrationValue << 3;\r
+\r
+ /* Store the new value */\r
+ RCC->CR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal High Speed oscillator for ADC (HSI14).\r
+ * @note After enabling the HSI14, the application software should wait on \r
+ * HSIRDY flag to be set indicating that HSI clock is stable and can\r
+ * be used to clock the ADC.\r
+ * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.\r
+ * @param NewState: new state of the HSI14.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator\r
+ * clock cycles.\r
+ * @retval None\r
+ */\r
+void RCC_HSI14Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->CR2 |= RCC_CR2_HSI14ON;\r
+ }\r
+ else\r
+ {\r
+ RCC->CR2 &= ~RCC_CR2_HSI14ON;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal High Speed oscillator request from ADC.\r
+ * @param NewState: new state of the HSI14 ADC request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_HSI14ADCRequestCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->CR2 &= ~RCC_CR2_HSI14DIS;\r
+ }\r
+ else\r
+ {\r
+ RCC->CR2 |= RCC_CR2_HSI14DIS;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the External Low Speed oscillator (LSE).\r
+ * @note As the LSE is in the Backup domain and write access is denied to this\r
+ * domain after reset, you have to enable write access using \r
+ * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE\r
+ * (to be done once after reset).\r
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application\r
+ * software should wait on LSERDY flag to be set indicating that LSE clock\r
+ * is stable and can be used to clock the RTC.\r
+ * @param RCC_LSE: specifies the new state of the LSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after\r
+ * 6 LSE oscillator clock cycles.\r
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator\r
+ * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_LSEConfig(uint32_t RCC_LSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE(RCC_LSE));\r
+\r
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
+ /* Reset LSEON bit */\r
+ RCC->BDCR &= ~(RCC_BDCR_LSEON);\r
+\r
+ /* Reset LSEBYP bit */\r
+ RCC->BDCR &= ~(RCC_BDCR_LSEBYP);\r
+\r
+ /* Configure LSE */\r
+ RCC->BDCR |= RCC_LSE;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External Low Speed oscillator (LSE) drive capability.\r
+ * @param RCC_LSEDrive: specifies the new state of the LSE drive capability.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.\r
+ * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.\r
+ * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.\r
+ * @arg RCC_LSEDrive_High: LSE oscillator high drive capability.\r
+ * @retval None\r
+ */\r
+void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));\r
+ \r
+ /* Clear LSEDRV[1:0] bits */\r
+ RCC->BDCR &= ~(RCC_BDCR_LSEDRV);\r
+\r
+ /* Set the LSE Drive */\r
+ RCC->BDCR |= RCC_LSEDrive;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).\r
+ * @note After enabling the LSI, the application software should wait on \r
+ * LSIRDY flag to be set indicating that LSI clock is stable and can\r
+ * be used to clock the IWDG and/or the RTC.\r
+ * @note LSI can not be disabled if the IWDG is running.\r
+ * @param NewState: new state of the LSI.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
+ * clock cycles.\r
+ * @retval None\r
+ */\r
+void RCC_LSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->CSR |= RCC_CSR_LSION;\r
+ }\r
+ else\r
+ {\r
+ RCC->CSR &= ~RCC_CSR_LSION;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the PLL clock source and multiplication factor.\r
+ * @note This function must be used only when the PLL is disabled.\r
+ *\r
+ * @param RCC_PLLSource: specifies the PLL entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source\r
+ * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry\r
+ * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as\r
+ * PLL source).\r
+ *\r
+ * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock\r
+ * This parameter can be RCC_PLLMul_x where x:[2,16] \r
+ *\r
+ * @retval None\r
+ */\r
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));\r
+\r
+ /* Clear PLL Source [16] and Multiplier [21:18] bits */\r
+ RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);\r
+\r
+ /* Set the PLL Source and Multiplier */\r
+ RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PLL.\r
+ * @note - After enabling the PLL, the application software should wait on \r
+ * PLLRDY flag to be set indicating that PLL clock is stable and can\r
+ * be used as system clock source.\r
+ * - The PLL can not be disabled if it is used as system clock source\r
+ * - The PLL is disabled by hardware when entering STOP and STANDBY modes.\r
+ * @param NewState: new state of the PLL.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_PLLCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->CR |= RCC_CR_PLLON;\r
+ }\r
+ else\r
+ {\r
+ RCC->CR &= ~RCC_CR_PLLON;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the PREDIV1 division factor.\r
+ * @note This function must be used only when the PLL is disabled.\r
+ * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.\r
+ * This parameter can be RCC_PREDIV1_Divx where x:[1,16]\r
+ * @retval None\r
+ */\r
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));\r
+\r
+ tmpreg = RCC->CFGR2;\r
+ /* Clear PREDIV1[3:0] bits */\r
+ tmpreg &= ~(RCC_CFGR2_PREDIV1);\r
+ /* Set the PREDIV1 division factor */\r
+ tmpreg |= RCC_PREDIV1_Div;\r
+ /* Store the new value */\r
+ RCC->CFGR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Clock Security System.\r
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator\r
+ * is automatically disabled and an interrupt is generated to inform the\r
+ * software about the failure (Clock Security System Interrupt, CSSI),\r
+ * allowing the MCU to perform rescue operations. The CSSI is linked to \r
+ * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.\r
+ * @param NewState: new state of the Clock Security System.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->CR |= RCC_CR_CSSON;\r
+ }\r
+ else\r
+ {\r
+ RCC->CR &= ~RCC_CR_CSSON;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the clock source to output on MCO pin (PA8).\r
+ * @note PA8 should be configured in alternate function mode.\r
+ * @param RCC_MCOSource: specifies the clock source to output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCOSource_NoClock: No clock selected.\r
+ * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.\r
+ * @arg RCC_MCOSource_SYSCLK: System clock selected.\r
+ * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.\r
+ * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.\r
+ * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock selected.\r
+ * @retval None\r
+ */\r
+void RCC_MCOConfig(uint8_t RCC_MCOSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));\r
+ \r
+ /* Select MCO clock source and prescaler */\r
+ *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = RCC_MCOSource;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions\r
+ * @brief System, AHB and APB busses clocks configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### System, AHB and APB busses clocks configuration functions #####\r
+ ===============================================================================\r
+\r
+ [..] This section provide functions allowing to configure the System, AHB and \r
+ APB busses clocks.\r
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,\r
+ HSE and PLL.\r
+ The AHB clock (HCLK) is derived from System clock through configurable prescaler\r
+ and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).\r
+ and APB (PCLK) clocks are derived from AHB clock through \r
+ configurable prescalers and used to clock the peripherals mapped on these busses.\r
+ You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.\r
+\r
+ -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:\r
+ (+@) The ADC clock which is derived from HSI14 or APB (APB divided by a\r
+ programmable prescaler: 2 or 4).\r
+ (+@) The CEC clock which is derived from LSE or HSI divided by 244.\r
+ (+@) The I2C clock which is derived from HSI or system clock (SYSCLK).\r
+ (+@) The USART clock which is derived from HSI, system clock (SYSCLK), APB or LSE.\r
+ (+@) The RTC/LCD clock which is derived from the LSE, LSI or 2 MHz HSE_RTC (HSE\r
+ divided by a programmable prescaler).\r
+ The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD\r
+ clock frequency.\r
+ (+@) IWDG clock which is always the LSI clock.\r
+ \r
+ (#) The maximum frequency of the SYSCLK, HCLK and PCLK is 48 MHz.\r
+ Depending on the maximum frequency, the FLASH wait states (WS) should be \r
+ adapted accordingly:\r
+ +--------------------------------------------- +\r
+ | Wait states | HCLK clock frequency (MHz) |\r
+ |---------------|------------------------------|\r
+ |0WS(1CPU cycle)| 0 < HCLK <= 24 |\r
+ |---------------|------------------------------|\r
+ |1WS(2CPU cycle)| 24 < HCLK <= 48 |\r
+ +----------------------------------------------+\r
+\r
+ (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and \r
+ prefetch is disabled.\r
+ \r
+ [..] It is recommended to use the following software sequences to tune the number\r
+ of wait states needed to access the Flash memory with the CPU frequency (HCLK).\r
+ (+) Increasing the CPU frequency\r
+ (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)" \r
+ function\r
+ (++) Check that Flash Prefetch buffer activation is taken into account by \r
+ reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function\r
+ (++) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function\r
+ (++) Check that the new number of WS is taken into account by reading FLASH_ACR\r
+ (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function\r
+ (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function\r
+ (++) Check that the new CPU clock source is taken into account by reading \r
+ the clock source status, using "RCC_GetSYSCLKSource()" function \r
+ (+) Decreasing the CPU frequency\r
+ (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function\r
+ (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function\r
+ (++) Check that the new CPU clock source is taken into account by reading \r
+ the clock source status, using "RCC_GetSYSCLKSource()" function\r
+ (++) Program the new number of WS, using "FLASH_SetLatency()" function\r
+ (++) Check that the new number of WS is taken into account by reading FLASH_ACR\r
+ (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)" \r
+ function\r
+ (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR\r
+ using the FLASH_GetPrefetchBufferStatus() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the system clock (SYSCLK).\r
+ * @note The HSI is used (enabled by hardware) as system clock source after\r
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case\r
+ * of failure of the HSE used directly or indirectly as system clock\r
+ * (if the Clock Security System CSS is enabled).\r
+ * @note A switch from one clock source to another occurs only if the target\r
+ * clock source is ready (clock stable after startup delay or PLL locked). \r
+ * If a clock source which is not yet ready is selected, the switch will\r
+ * occur when the clock source will be ready. \r
+ * You can use RCC_GetSYSCLKSource() function to know which clock is\r
+ * currently used as system clock source. \r
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock source \r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source\r
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source\r
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source\r
+ * @retval None\r
+ */\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear SW[1:0] bits */\r
+ tmpreg &= ~RCC_CFGR_SW;\r
+ \r
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
+ tmpreg |= RCC_SYSCLKSource;\r
+ \r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the clock source used as system clock.\r
+ * @param None\r
+ * @retval The clock source used as system clock. The returned value can be one \r
+ * of the following values:\r
+ * - 0x00: HSI used as system clock\r
+ * - 0x04: HSE used as system clock \r
+ * - 0x08: PLL used as system clock\r
+ */\r
+uint8_t RCC_GetSYSCLKSource(void)\r
+{\r
+ return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));\r
+}\r
+\r
+/**\r
+ * @brief Configures the AHB clock (HCLK).\r
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from \r
+ * the system clock (SYSCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK\r
+ * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2\r
+ * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4\r
+ * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8\r
+ * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16\r
+ * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64\r
+ * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r
+ * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r
+ * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r
+ * @retval None\r
+ */\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear HPRE[3:0] bits */\r
+ tmpreg &= ~RCC_CFGR_HPRE;\r
+ \r
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r
+ tmpreg |= RCC_SYSCLK;\r
+ \r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the APB clock (PCLK).\r
+ * @param RCC_HCLK: defines the APB clock divider. This clock is derived from \r
+ * the AHB clock (HCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HCLK_Div1: APB clock = HCLK\r
+ * @arg RCC_HCLK_Div2: APB clock = HCLK/2\r
+ * @arg RCC_HCLK_Div4: APB clock = HCLK/4\r
+ * @arg RCC_HCLK_Div8: APB clock = HCLK/8\r
+ * @arg RCC_HCLK_Div16: APB clock = HCLK/16\r
+ * @retval None\r
+ */\r
+void RCC_PCLKConfig(uint32_t RCC_HCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+ \r
+ tmpreg = RCC->CFGR;\r
+ \r
+ /* Clear PPRE[2:0] bits */\r
+ tmpreg &= ~RCC_CFGR_PPRE;\r
+ \r
+ /* Set PPRE[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK;\r
+ \r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the ADC clock (ADCCLK).\r
+ * @param RCC_ADCCLK: defines the ADC clock source. This clock is derived \r
+ * from the HSI14 or APB clock (PCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_ADCCLK_HSI14: ADC clock = HSI14 (14MHz)\r
+ * @arg RCC_ADCCLK_PCLK_Div2: ADC clock = PCLK/2\r
+ * @arg RCC_ADCCLK_PCLK_Div4: ADC clock = PCLK/4 \r
+ * @retval None\r
+ */\r
+void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_ADCCLK(RCC_ADCCLK));\r
+\r
+ /* Clear ADCPRE bit */\r
+ RCC->CFGR &= ~RCC_CFGR_ADCPRE;\r
+ /* Set ADCPRE bits according to RCC_PCLK value */\r
+ RCC->CFGR |= RCC_ADCCLK & 0xFFFF;\r
+\r
+ /* Clear ADCSW bit */\r
+ RCC->CFGR3 &= ~RCC_CFGR3_ADCSW; \r
+ /* Set ADCSW bits according to RCC_ADCCLK value */\r
+ RCC->CFGR3 |= RCC_ADCCLK >> 16; \r
+}\r
+\r
+/**\r
+ * @brief Configures the CEC clock (CECCLK).\r
+ * @param RCC_CECCLK: defines the CEC clock source. This clock is derived \r
+ * from the HSI or LSE clock.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz)\r
+ * @arg RCC_CECCLK_LSE: CEC clock = LSE\r
+ * @retval None\r
+ */\r
+void RCC_CECCLKConfig(uint32_t RCC_CECCLK)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CECCLK(RCC_CECCLK));\r
+\r
+ /* Clear CECSW bit */\r
+ RCC->CFGR3 &= ~RCC_CFGR3_CECSW;\r
+ /* Set CECSW bits according to RCC_CECCLK value */\r
+ RCC->CFGR3 |= RCC_CECCLK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the I2C1 clock (I2C1CLK).\r
+ * @param RCC_I2CCLK: defines the I2C1 clock source. This clock is derived \r
+ * from the HSI or System clock.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C1CLK_HSI: I2C1 clock = HSI\r
+ * @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = System Clock\r
+ * @retval None\r
+ */\r
+void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));\r
+\r
+ /* Clear I2CSW bit */\r
+ RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;\r
+ /* Set I2CSW bits according to RCC_I2CCLK value */\r
+ RCC->CFGR3 |= RCC_I2CCLK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the USART1 clock (USART1CLK).\r
+ * @param RCC_USARTCLK: defines the USART1 clock source. This clock is derived \r
+ * from the HSI or System clock.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART1CLK_PCLK: USART1 clock = APB Clock (PCLK)\r
+ * @arg RCC_USART1CLK_SYSCLK: USART1 clock = System Clock\r
+ * @arg RCC_USART1CLK_LSE: USART1 clock = LSE Clock\r
+ * @arg RCC_USART1CLK_HSI: USART1 clock = HSI Clock\r
+ * @retval None\r
+ */\r
+void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));\r
+\r
+ /* Clear USARTSW[1:0] bit */\r
+ RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;\r
+ /* Set USARTSW bits according to RCC_USARTCLK value */\r
+ RCC->CFGR3 |= RCC_USARTCLK;\r
+}\r
+\r
+/**\r
+ * @brief Returns the frequencies of the System, AHB and APB busses clocks.\r
+ * @note The frequency returned by this function is not the real frequency\r
+ * in the chip. It is calculated based on the predefined constant and\r
+ * the source selected by RCC_SYSCLKConfig():\r
+ * \r
+ * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*)\r
+ * \r
+ * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**)\r
+ * \r
+ * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value\r
+ * 8 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue(). \r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value\r
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * return wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal. \r
+ * \r
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold \r
+ * the clocks frequencies. \r
+ * \r
+ * @note This function can be used by the user application to compute the \r
+ * baudrate for the communication peripherals or configure other parameters.\r
+ * @note Each time SYSCLK, HCLK and/or PCLK clock changes, this function\r
+ * must be called to update the structure's field. Otherwise, any\r
+ * configuration based on this function will be incorrect.\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
+{\r
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+ \r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
+ break;\r
+ case 0x04: /* HSE used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;\r
+ break;\r
+ case 0x08: /* PLL used as system clock */\r
+ /* Get PLL clock source and multiplication factor ----------------------*/\r
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;\r
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
+ pllmull = ( pllmull >> 18) + 2;\r
+ \r
+ if (pllsource == 0x00)\r
+ {\r
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;\r
+ }\r
+ else\r
+ {\r
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;\r
+ /* HSE oscillator clock selected as PREDIV1 clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; \r
+ } \r
+ break;\r
+ default: /* HSI used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
+ break;\r
+ }\r
+ /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = RCC->CFGR & RCC_CFGR_HPRE;\r
+ tmp = tmp >> 4;\r
+ presc = APBAHBPrescTable[tmp]; \r
+ /* HCLK clock frequency */\r
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
+\r
+ /* Get PCLK prescaler */\r
+ tmp = RCC->CFGR & RCC_CFGR_PPRE;\r
+ tmp = tmp >> 8;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* PCLK clock frequency */\r
+ RCC_Clocks->PCLK_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+\r
+ /* ADCCLK clock frequency */\r
+ if((RCC->CFGR3 & RCC_CFGR3_ADCSW) != RCC_CFGR3_ADCSW)\r
+ {\r
+ /* ADC Clock is HSI14 Osc. */\r
+ RCC_Clocks->ADCCLK_Frequency = HSI14_VALUE;\r
+ }\r
+ else\r
+ {\r
+ if((RCC->CFGR & RCC_CFGR_ADCPRE) != RCC_CFGR_ADCPRE)\r
+ {\r
+ /* ADC Clock is derived from PCLK/2 */\r
+ RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 1;\r
+ }\r
+ else\r
+ {\r
+ /* ADC Clock is derived from PCLK/4 */\r
+ RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 2;\r
+ }\r
+ \r
+ }\r
+\r
+ /* CECCLK clock frequency */\r
+ if((RCC->CFGR3 & RCC_CFGR3_CECSW) != RCC_CFGR3_CECSW)\r
+ {\r
+ /* CEC Clock is HSI/256 */\r
+ RCC_Clocks->CECCLK_Frequency = HSI_VALUE / 244;\r
+ }\r
+ else\r
+ {\r
+ /* CECC Clock is LSE Osc. */\r
+ RCC_Clocks->CECCLK_Frequency = LSE_VALUE;\r
+ }\r
+\r
+ /* I2C1CLK clock frequency */\r
+ if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)\r
+ {\r
+ /* I2C1 Clock is HSI Osc. */\r
+ RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;\r
+ }\r
+ else\r
+ {\r
+ /* I2C1 Clock is System Clock */\r
+ RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;\r
+ }\r
+\r
+ /* USART1CLK clock frequency */\r
+ if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)\r
+ {\r
+ /* USART1 Clock is PCLK */\r
+ RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK_Frequency;\r
+ }\r
+ else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)\r
+ {\r
+ /* USART1 Clock is System Clock */\r
+ RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;\r
+ }\r
+ else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)\r
+ {\r
+ /* USART1 Clock is LSE Osc. */\r
+ RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;\r
+ }\r
+ else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)\r
+ {\r
+ /* USART1 Clock is HSI Osc. */\r
+ RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;\r
+ }\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group3 Peripheral clocks configuration functions\r
+ * @brief Peripheral clocks configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ #####Peripheral clocks configuration functions #####\r
+ =============================================================================== \r
+\r
+ [..] This section provide functions allowing to configure the Peripheral clocks. \r
+ (#) The RTC clock which is derived from the LSE, LSI or HSE_Div32 (HSE\r
+ divided by 32).\r
+ (#) After restart from Reset or wakeup from STANDBY, all peripherals are off\r
+ except internal SRAM, Flash and SWD. Before to start using a peripheral you\r
+ have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd(),\r
+ RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.\r
+ (#) To reset the peripherals configuration (to the default state after device reset)\r
+ you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and \r
+ RCC_APB1PeriphResetCmd() functions.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC clock (RTCCLK).\r
+ * @note As the RTC clock configuration bits are in the Backup domain and write\r
+ * access is denied to this domain after reset, you have to enable write\r
+ * access using PWR_BackupAccessCmd(ENABLE) function before to configure\r
+ * the RTC clock source (to be done once after reset). \r
+ * @note Once the RTC clock is configured it can't be changed unless the RTC\r
+ * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)\r
+ * \r
+ * @param RCC_RTCCLKSource: specifies the RTC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock\r
+ * \r
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to\r
+ * work in STOP and STANDBY modes, and can be used as wakeup source.\r
+ * However, when the HSE clock is used as RTC clock source, the RTC\r
+ * cannot be used in STOP and STANDBY modes.\r
+ * \r
+ * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as\r
+ * RTC clock source).\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
+ \r
+ /* Select the RTC clock source */\r
+ RCC->BDCR |= RCC_RTCCLKSource;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC clock.\r
+ * @note This function must be used only after the RTC clock source was selected\r
+ * using the RCC_RTCCLKConfig function.\r
+ * @param NewState: new state of the RTC clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->BDCR |= RCC_BDCR_RTCEN;\r
+ }\r
+ else\r
+ {\r
+ RCC->BDCR &= ~RCC_BDCR_RTCEN;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases the Backup domain reset.\r
+ * @note This function resets the RTC peripheral (including the backup registers)\r
+ * and the RTC clock source selection in RCC_BDCR register.\r
+ * @param NewState: new state of the Backup domain reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_BackupResetCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->BDCR |= RCC_BDCR_BDRST;\r
+ }\r
+ else\r
+ {\r
+ RCC->BDCR &= ~RCC_BDCR_BDRST;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHBPeriph_GPIOA: GPIOA clock\r
+ * @arg RCC_AHBPeriph_GPIOB: GPIOB clock\r
+ * @arg RCC_AHBPeriph_GPIOC: GPIOC clock\r
+ * @arg RCC_AHBPeriph_GPIOD: GPIOD clock\r
+ * @arg RCC_AHBPeriph_GPIOF: GPIOF clock\r
+ * @arg RCC_AHBPeriph_TS: TS clock\r
+ * @arg RCC_AHBPeriph_CRC: CRC clock\r
+ * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode) \r
+ * @arg RCC_AHBPeriph_SRAM: SRAM clock\r
+ * @arg RCC_AHBPeriph_DMA1: DMA1 clock\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBENR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBENR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock\r
+ * @arg RCC_APB2Periph_ADC1: ADC1 clock\r
+ * @arg RCC_APB2Periph_TIM1: TIM1 clock\r
+ * @arg RCC_APB2Periph_SPI1: SPI1 clock\r
+ * @arg RCC_APB2Periph_USART1: USART1 clock\r
+ * @arg RCC_APB2Periph_TIM15: TIM15 clock\r
+ * @arg RCC_APB2Periph_TIM16: TIM16 clock\r
+ * @arg RCC_APB2Periph_TIM17: TIM17 clock\r
+ * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2ENR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2ENR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2: TIM2 clock\r
+ * @arg RCC_APB1Periph_TIM3: TIM3 clock\r
+ * @arg RCC_APB1Periph_TIM6: TIM6 clock\r
+ * @arg RCC_APB1Periph_TIM14: TIM14 clock\r
+ * @arg RCC_APB1Periph_WWDG: WWDG clock\r
+ * @arg RCC_APB1Periph_SPI2: SPI2 clock\r
+ * @arg RCC_APB1Periph_USART2: USART2 clock\r
+ * @arg RCC_APB1Periph_I2C1: I2C1 clock\r
+ * @arg RCC_APB1Periph_I2C2: I2C2 clock\r
+ * @arg RCC_APB1Periph_PWR: PWR clock\r
+ * @arg RCC_APB1Periph_DAC: DAC clock\r
+ * @arg RCC_APB1Periph_CEC: CEC clock \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1ENR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1ENR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases AHB peripheral reset.\r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHBPeriph_GPIOA: GPIOA clock\r
+ * @arg RCC_AHBPeriph_GPIOB: GPIOB clock\r
+ * @arg RCC_AHBPeriph_GPIOC: GPIOC clock\r
+ * @arg RCC_AHBPeriph_GPIOD: GPIOD clock\r
+ * @arg RCC_AHBPeriph_GPIOF: GPIOF clock\r
+ * @arg RCC_AHBPeriph_TS: TS clock\r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBRSTR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBRSTR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock\r
+ * @arg RCC_APB2Periph_ADC1: ADC1 clock\r
+ * @arg RCC_APB2Periph_TIM1: TIM1 clock\r
+ * @arg RCC_APB2Periph_SPI1: SPI1 clock\r
+ * @arg RCC_APB2Periph_USART1: USART1 clock\r
+ * @arg RCC_APB2Periph_TIM15: TIM15 clock\r
+ * @arg RCC_APB2Periph_TIM16: TIM16 clock\r
+ * @arg RCC_APB2Periph_TIM17: TIM17 clock\r
+ * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock\r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2RSTR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2RSTR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2: TIM2 clock\r
+ * @arg RCC_APB1Periph_TIM3: TIM3 clock\r
+ * @arg RCC_APB1Periph_TIM6: TIM6 clock\r
+ * @arg RCC_APB1Periph_TIM14: TIM14 clock\r
+ * @arg RCC_APB1Periph_WWDG: WWDG clock\r
+ * @arg RCC_APB1Periph_SPI2: SPI2 clock\r
+ * @arg RCC_APB1Periph_USART2: USART2 clock\r
+ * @arg RCC_APB1Periph_I2C1: I2C1 clock\r
+ * @arg RCC_APB1Periph_I2C2: I2C2 clock\r
+ * @arg RCC_APB1Periph_PWR: PWR clock\r
+ * @arg RCC_APB1Periph_DAC: DAC clock\r
+ * @arg RCC_APB1Periph_CEC: CEC clock\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1RSTR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1RSTR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Group4 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ===============================================================================\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified RCC interrupts.\r
+ * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled\r
+ * and if the HSE clock fails, the CSS interrupt occurs and an NMI is\r
+ * automatically generated. The NMI will be executed indefinitely, and \r
+ * since NMI has higher priority than any other IRQ (and main program)\r
+ * the application will be stacked in the NMI ISR unless the CSS interrupt\r
+ * pending bit is cleared.\r
+ * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt\r
+ * @param NewState: new state of the specified RCC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_IT(RCC_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE1_ADDRESS |= RCC_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE1_ADDRESS &= (uint8_t)~RCC_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC flag is set or not.\r
+ * @param RCC_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready \r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready\r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+ * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset \r
+ * @arg RCC_FLAG_PINRST: Pin reset\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset\r
+ * @arg RCC_FLAG_SFTRST: Software reset\r
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
+ * @arg RCC_FLAG_LPWRRST: Low Power reset\r
+ * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready \r
+ * @retval The new state of RCC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint32_t statusreg = 0;\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_FLAG(RCC_FLAG));\r
+\r
+ /* Get the RCC register index */\r
+ tmp = RCC_FLAG >> 5;\r
+\r
+ if (tmp == 0) /* The flag to check is in CR register */\r
+ {\r
+ statusreg = RCC->CR;\r
+ }\r
+ else if (tmp == 1) /* The flag to check is in BDCR register */\r
+ {\r
+ statusreg = RCC->BDCR;\r
+ }\r
+ else if (tmp == 2) /* The flag to check is in CSR register */\r
+ {\r
+ statusreg = RCC->CSR;\r
+ }\r
+ else /* The flag to check is in CR2 register */\r
+ {\r
+ statusreg = RCC->CR2;\r
+ } \r
+\r
+ /* Get the flag position */\r
+ tmp = RCC_FLAG & FLAG_MASK;\r
+\r
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC reset flags.\r
+ * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, \r
+ * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_ClearFlag(void)\r
+{\r
+ /* Set RMVF bit to clear the reset flags */\r
+ RCC->CSR |= RCC_CSR_RMVF;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC interrupt has occurred or not.\r
+ * @param RCC_IT: specifies the RCC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval The new state of RCC_IT (SET or RESET).\r
+ */\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_GET_IT(RCC_IT));\r
+ \r
+ /* Check the status of the specified RCC interrupt */\r
+ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the RCC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC's interrupt pending bits.\r
+ * @param RCC_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval None\r
+ */\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r
+ \r
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
+ pending bits */\r
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS = RCC_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_rtc.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Real-Time Clock (RTC) peripheral:\r
+ * + Initialization\r
+ * + Calendar (Time and Date) configuration\r
+ * + Alarms (Alarm A) configuration\r
+ * + Daylight Saving configuration\r
+ * + Output pin Configuration\r
+ * + Digital Calibration configuration \r
+ * + TimeStamp configuration\r
+ * + Tampers configuration\r
+ * + Backup Data Registers configuration\r
+ * + Output Type Config configuration\r
+ * + Shift control synchronisation \r
+ * + Interrupts and flags management\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### Backup Domain Operating Condition #####\r
+ ===============================================================================\r
+ [..] The real-time clock (RTC) and the RTC backup registers can be powered\r
+ from the VBAT voltage when the main VDD supply is powered off.\r
+ To retain the content of the RTC backup registers and supply the RTC \r
+ when VDD is turned off, VBAT pin can be connected to an optional\r
+ standby voltage supplied by a battery or by another source.\r
+ \r
+ [..] To allow the RTC to operate even when the main digital supply (VDD) \r
+ is turned off, the VBAT pin powers the following blocks:\r
+ (#) The RTC\r
+ (#) The LSE oscillator\r
+ (#) PC13 to PC15 I/Os I/Os (when available)\r
+ \r
+ [..] When the backup domain is supplied by VDD (analog switch connected \r
+ to VDD), the following functions are available:\r
+ (#) PC14 and PC15 can be used as either GPIO or LSE pins\r
+ (#) PC13 can be used as a GPIO or as the RTC_AF1 pin\r
+ \r
+ [..] When the backup domain is supplied by VBAT (analog switch connected \r
+ to VBAT because VDD is not present), the following functions are available:\r
+ (#) PC14 and PC15 can be used as LSE pins only\r
+ (#) PC13 can be used as the RTC_AF1 pin \r
+ \r
+ ##### Backup Domain Reset #####\r
+ ===============================================================================\r
+ [..] The backup domain reset sets all RTC registers and the RCC_BDCR \r
+ register to their reset values. \r
+ A backup domain reset is generated when one of the following events\r
+ occurs:\r
+ (#) Software reset, triggered by setting the BDRST bit in the \r
+ RCC Backup domain control register (RCC_BDCR). You can use the\r
+ RCC_BackupResetCmd().\r
+ (#) VDD or VBAT power on, if both supplies have previously been\r
+ powered off.\r
+ \r
+ ##### Backup Domain Access #####\r
+ ===============================================================================\r
+ [..] After reset, the backup domain (RTC registers and RTC backup data \r
+ registers) is protected against possible unwanted write accesses. \r
+ [..] To enable access to the Backup Domain and RTC registers, proceed as follows:\r
+ (#) Enable the Power Controller (PWR) APB1 interface clock using the\r
+ RCC_APB1PeriphClockCmd() function.\r
+ (#) Enable access to Backup domain using the PWR_BackupAccessCmd() function.\r
+ (#) Select the RTC clock source using the RCC_RTCCLKConfig() function.\r
+ (#) Enable RTC Clock using the RCC_RTCCLKCmd() function.\r
+ \r
+ \r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ (+) Enable the backup domain access (see description in the section above)\r
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and\r
+ RTC hour format using the RTC_Init() function.\r
+ \r
+ ***Time and Date configuration ***\r
+ ==================================\r
+ [..]\r
+ (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()\r
+ and RTC_SetDate() functions.\r
+ (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()\r
+ functions.\r
+ (+) To read the RTC subsecond, use the RTC_GetSubSecond() function.\r
+ (+) Use the RTC_DayLightSavingConfig() function to add or sub one\r
+ hour to the RTC Calendar.\r
+ \r
+ ***Alarm configuration ***\r
+ ========================== \r
+ [..] \r
+ (+) To configure the RTC Alarm use the RTC_SetAlarm() function.\r
+ (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function \r
+ (+) To read the RTC Alarm, use the RTC_GetAlarm() function.\r
+ (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.\r
+ \r
+ ***Outputs configuration ***\r
+ ============================\r
+ [..] The RTC has 2 different outputs:\r
+ (+) AFO_ALARM: this output is used to manage the RTC Alarm A.\r
+ To output the selected RTC signal on RTC_AF1 pin, use the \r
+ RTC_OutputConfig() function. \r
+ (+) AFO_CALIB: this output is 512Hz signal or 1Hz .\r
+ To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()\r
+ function. \r
+ \r
+ ***Original Digital Calibration configuration ***\r
+ ================================= \r
+ [..] Configure the RTC Original Digital Calibration Value and the corresponding\r
+ calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()\r
+ function.\r
+ \r
+ ***TimeStamp configuration ***\r
+ ==============================\r
+ [..] \r
+ (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp \r
+ using the RTC_TimeStampCmd() function.\r
+ (+) To read the RTC TimeStamp Time and Date register, use the \r
+ RTC_GetTimeStamp() function.\r
+ (+) To read the RTC TimeStamp SubSecond register, use the \r
+ RTC_GetTimeStampSubSecond() function.\r
+ \r
+ ***Tamper configuration ***\r
+ ===========================\r
+ [..] \r
+ (+) Configure the Tamper filter count using RTC_TamperFilterConfig()\r
+ function. \r
+ (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper \r
+ filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function\r
+ (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()\r
+ function.\r
+ (+) Configure the Tamper precharge or discharge duration using \r
+ RTC_TamperPinsPrechargeDuration() function.\r
+ (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.\r
+ (+) Enable the RTC Tamper using the RTC_TamperCmd() function.\r
+ (+) Enable the Time stamp on Tamper detection event using \r
+ RTC_TSOnTamperDetecCmd() function. \r
+ \r
+ ***Backup Data Registers configuration ***\r
+ ==========================================\r
+ [..] \r
+ (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()\r
+ function. \r
+ (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()\r
+ function. \r
+ \r
+ ##### RTC and low power modes #####\r
+ ===============================================================================\r
+ [..] The MCU can be woken up from a low power mode by an RTC alternate \r
+ function.\r
+ [..] The RTC alternate functions are the RTC alarm (Alarm A), RTC tamper \r
+ event detection and RTC time stamp event detection.\r
+ These RTC alternate functions can wake up the system from the Stop \r
+ and Standby lowpower modes.\r
+ The system can also wake up from low power modes without depending \r
+ on an external interrupt (Auto-wakeup mode), by using the RTC alarm events.\r
+ [..] The RTC provides a programmable time base for waking up from the \r
+ Stop or Standby mode at regular intervals.\r
+ Wakeup from STOP and Standby modes is possible only when the RTC \r
+ clock source is LSE or LSI.\r
+ \r
+ ##### Selection of RTC_AF1 alternate functions #####\r
+ ===============================================================================\r
+ [..] The RTC_AF1 pin (PC13) can be used for the following purposes:\r
+ (+) AFO_ALARM output\r
+ (+) AFO_CALIB output\r
+ (+) AFI_TAMPER\r
+ (+) AFI_TIMESTAMP\r
+ \r
+ +------------------------------------------------------------------------------------------+\r
+ | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2 |ALARMOUTTYPE |\r
+ | configuration | ENABLED | ENABLED | ENABLED | ENABLED |ENABLED | AFO_ALARM |\r
+ | and function | | | | | |Configuration |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | Alarm out | | | | | Don't | |\r
+ | output OD | 1 | 0 |Don't care | Don't care | care | 0 |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | Alarm out | | | | | Don't | |\r
+ | output PP | 1 | 0 |Don't care | Don't care | care | 1 |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | Calibration out | | | | | Don't | |\r
+ | output PP | 0 | 1 |Don't care | Don't care | care | Don't care |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | TAMPER input | | | | | Don't | |\r
+ | floating | 0 | 0 | 1 | 0 | care | Don't care |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | TIMESTAMP and | | | | | Don't | |\r
+ | TAMPER input | 0 | 0 | 1 | 1 | care | Don't care |\r
+ | floating | | | | | | |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | TIMESTAMP input | | | | | Don't | |\r
+ | floating | 0 | 0 | 0 | 1 | care | Don't care |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | Wakeup Pin 2 | 0 | 0 | 0 | 0 | 1 | Don't care |\r
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|\r
+ | Standard GPIO | 0 | 0 | 0 | 0 | 0 | Don't care |\r
+ +------------------------------------------------------------------------------------------+\r
+ \r
+ @endverbatim\r
+ \r
+ *******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_rtc.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTC \r
+ * @brief RTC driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* Masks Definition */\r
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)\r
+#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) \r
+#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) \r
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)\r
+#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_ALRAF | \\r
+ RTC_FLAG_RSF | RTC_FLAG_INITS |RTC_FLAG_INITF | \\r
+ RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | \\r
+ RTC_FLAG_RECALPF | RTC_FLAG_SHPF))\r
+\r
+#define INITMODE_TIMEOUT ((uint32_t) 0x00004000)\r
+#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000)\r
+#define RECALPF_TIMEOUT ((uint32_t) 0x00001000)\r
+#define SHPF_TIMEOUT ((uint32_t) 0x00001000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static uint8_t RTC_ByteToBcd2(uint8_t Value);\r
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RTC_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup RTC_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ =============================================================================== \r
+\r
+ [..] This section provide functions allowing to initialize and configure the RTC\r
+ Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers\r
+ Write protection, enter and exit the RTC initialization mode, RTC registers\r
+ synchronization check and reference clock detection enable.\r
+ \r
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.\r
+ It is split into 2 programmable prescalers to minimize power consumption.\r
+ (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.\r
+ (++) When both prescalers are used, it is recommended to configure the\r
+ asynchronous prescaler to a high value to minimize consumption.\r
+ (#) All RTC registers are Write protected. Writing to the RTC registers\r
+ is enabled by writing a key into the Write Protection register, RTC_WPR.\r
+ (#) To Configure the RTC Calendar, user application should enter\r
+ initialization mode. In this mode, the calendar counter is stopped\r
+ and its value can be updated. When the initialization sequence is\r
+ complete, the calendar restarts counting after 4 RTCCLK cycles.\r
+ (#) To read the calendar through the shadow registers after Calendar\r
+ initialization, calendar update or after wakeup from low power modes\r
+ the software must first clear the RSF flag. The software must then\r
+ wait until it is set again before reading the calendar, which means\r
+ that the calendar registers have been correctly copied into the\r
+ RTC_TR and RTC_DR shadow registers.The RTC_WaitForSynchro() function\r
+ implements the above software sequence (RSF clear and RSF check).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the RTC registers to their default reset values.\r
+ * @note This function doesn't reset the RTC Clock source and RTC Backup Data\r
+ * registers. \r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC registers are deinitialized\r
+ * - ERROR: RTC registers are not deinitialized\r
+ */\r
+ErrorStatus RTC_DeInit(void)\r
+{\r
+ __IO uint32_t wutcounter = 0x00;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Reset TR, DR and CR registers */\r
+ RTC->TR = (uint32_t)0x00000000;\r
+ RTC->DR = (uint32_t)0x00002101;\r
+ RTC->CR &= (uint32_t)0x00000000;\r
+ RTC->PRER = (uint32_t)0x007F00FF;\r
+ RTC->ALRMAR = (uint32_t)0x00000000;\r
+ RTC->SHIFTR = (uint32_t)0x00000000;\r
+ RTC->CAL = (uint32_t)0x00000000;\r
+ RTC->ALRMASSR = (uint32_t)0x00000000;\r
+\r
+ /* Reset ISR register and exit initialization mode */\r
+ RTC->ISR = (uint32_t)0x00000000;\r
+ \r
+ /* Reset Tamper and alternate functions configuration register */\r
+ RTC->TAFCR = 0x00000000;\r
+ \r
+ /* Wait till the RTC RSF flag is set */\r
+ if (RTC_WaitForSynchro() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+\r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the RTC registers according to the specified parameters \r
+ * in RTC_InitStruct.\r
+ * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains \r
+ * the configuration information for the RTC peripheral.\r
+ * @note The RTC Prescaler register is write protected and can be written in \r
+ * initialization mode only. \r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC registers are initialized\r
+ * - ERROR: RTC registers are not initialized \r
+ */\r
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)\r
+{\r
+ ErrorStatus status = ERROR;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));\r
+ assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));\r
+ assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Clear RTC CR FMT Bit */\r
+ RTC->CR &= ((uint32_t)~(RTC_CR_FMT));\r
+ /* Set RTC_CR register */\r
+ RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));\r
+ \r
+ /* Configure the RTC PRER */\r
+ RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);\r
+ RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);\r
+\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode();\r
+\r
+ status = SUCCESS;\r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_InitStruct member with its default value.\r
+ * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be \r
+ * initialized.\r
+ * @retval None\r
+ */\r
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)\r
+{\r
+ /* Initialize the RTC_HourFormat member */\r
+ RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;\r
+\r
+ /* Initialize the RTC_AsynchPrediv member */\r
+ RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;\r
+\r
+ /* Initialize the RTC_SynchPrediv member */\r
+ RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC registers write protection.\r
+ * @note All the RTC registers are write protected except for RTC_ISR[13:8], \r
+ * RTC_TAFCR and RTC_BKPxR.\r
+ * @note Writing a wrong key reactivates the write protection.\r
+ * @note The protection mechanism is not affected by system reset.\r
+ * @param NewState: new state of the write protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_WriteProtectionCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters the RTC Initialization mode.\r
+ * @note The RTC Initialization mode is write protected, use the \r
+ * RTC_WriteProtectionCmd(DISABLE) before calling this function.\r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC is in Init mode\r
+ * - ERROR: RTC is not in Init mode\r
+ */\r
+ErrorStatus RTC_EnterInitMode(void)\r
+{\r
+ __IO uint32_t initcounter = 0x00;\r
+ ErrorStatus status = ERROR;\r
+ uint32_t initstatus = 0x00;\r
+\r
+ /* Check if the Initialization mode is set */\r
+ if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)\r
+ {\r
+ /* Set the Initialization mode */\r
+ RTC->ISR = (uint32_t)RTC_INIT_MASK;\r
+ \r
+ /* Wait till RTC is in INIT state and if Time out is reached exit */\r
+ do\r
+ {\r
+ initstatus = RTC->ISR & RTC_ISR_INITF;\r
+ initcounter++; \r
+ } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));\r
+ \r
+ if ((RTC->ISR & RTC_ISR_INITF) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+\r
+ return (status);\r
+}\r
+\r
+/**\r
+ * @brief Exits the RTC Initialization mode.\r
+ * @note When the initialization sequence is complete, the calendar restarts \r
+ * counting after 4 RTCCLK cycles. \r
+ * @note The RTC Initialization mode is write protected, use the \r
+ * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RTC_ExitInitMode(void)\r
+{\r
+ /* Exit Initialization mode */\r
+ RTC->ISR &= (uint32_t)~RTC_ISR_INIT;\r
+}\r
+\r
+/**\r
+ * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are \r
+ * synchronized with RTC APB clock.\r
+ * @note The RTC Resynchronization mode is write protected, use the \r
+ * RTC_WriteProtectionCmd(DISABLE) before calling this function. \r
+ * @note To read the calendar through the shadow registers after Calendar \r
+ * initialization, calendar update or after wakeup from low power modes \r
+ * the software must first clear the RSF flag. \r
+ * The software must then wait until it is set again before reading \r
+ * the calendar, which means that the calendar registers have been \r
+ * correctly copied into the RTC_TR and RTC_DR shadow registers. \r
+ * @param None\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC registers are synchronised\r
+ * - ERROR: RTC registers are not synchronised\r
+ */\r
+ErrorStatus RTC_WaitForSynchro(void)\r
+{\r
+ __IO uint32_t synchrocounter = 0;\r
+ ErrorStatus status = ERROR;\r
+ uint32_t synchrostatus = 0x00;\r
+\r
+ if ((RTC->CR & RTC_CR_BYPSHAD) != RESET)\r
+ {\r
+ /* Bypass shadow mode */\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Clear RSF flag */\r
+ RTC->ISR &= (uint32_t)RTC_RSF_MASK;\r
+\r
+ /* Wait the registers to be synchronised */\r
+ do\r
+ {\r
+ synchrostatus = RTC->ISR & RTC_ISR_RSF;\r
+ synchrocounter++; \r
+ } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));\r
+\r
+ if ((RTC->ISR & RTC_ISR_RSF) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+ }\r
+\r
+ return (status);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC reference clock detection.\r
+ * @param NewState: new state of the RTC reference clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC reference clock detection is enabled\r
+ * - ERROR: RTC reference clock detection is disabled \r
+ */\r
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState)\r
+{\r
+ ErrorStatus status = ERROR;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the RTC reference clock detection */\r
+ RTC->CR |= RTC_CR_REFCKON;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the RTC reference clock detection */\r
+ RTC->CR &= ~RTC_CR_REFCKON;\r
+ }\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode();\r
+\r
+ status = SUCCESS;\r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the Bypass Shadow feature.\r
+ * @note When the Bypass Shadow is enabled the calendar value are taken \r
+ * directly from the Calendar counter.\r
+ * @param NewState: new state of the Bypass Shadow feature.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+*/\r
+void RTC_BypassShadowCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the BYPSHAD bit */\r
+ RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the BYPSHAD bit */\r
+ RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;\r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group2 Time and Date configuration functions\r
+ * @brief Time and Date configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Time and Date configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provide functions allowing to program and read the RTC\r
+ Calendar (Time and Date).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set the RTC current time.\r
+ * @param RTC_Format: specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains \r
+ * the time configuration information for the RTC.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Time register is configured\r
+ * - ERROR: RTC Time register is not configured\r
+ */\r
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ ErrorStatus status = ERROR;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ \r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));\r
+ assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));\r
+ }\r
+ else\r
+ {\r
+ RTC_TimeStruct->RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));\r
+ assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));\r
+ }\r
+ else\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);\r
+ assert_param(IS_RTC_HOUR12(tmpreg));\r
+ assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); \r
+ } \r
+ else\r
+ {\r
+ RTC_TimeStruct->RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));\r
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));\r
+ }\r
+ \r
+ /* Check the input parameters format */\r
+ if (RTC_Format != RTC_Format_BIN)\r
+ {\r
+ tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \\r
+ ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \\r
+ ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); \r
+ }\r
+ else\r
+ {\r
+ tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \\r
+ (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));\r
+ } \r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Set the RTC_TR register */\r
+ RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);\r
+\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode(); \r
+\r
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r
+ if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)\r
+ {\r
+ if (RTC_WaitForSynchro() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ \r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_TimeStruct member with its default value\r
+ * (Time = 00h:00min:00sec).\r
+ * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be \r
+ * initialized.\r
+ * @retval None\r
+ */\r
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)\r
+{\r
+ /* Time = 00h:00min:00sec */\r
+ RTC_TimeStruct->RTC_H12 = RTC_H12_AM;\r
+ RTC_TimeStruct->RTC_Hours = 0;\r
+ RTC_TimeStruct->RTC_Minutes = 0;\r
+ RTC_TimeStruct->RTC_Seconds = 0; \r
+}\r
+\r
+/**\r
+ * @brief Get the RTC current Time.\r
+ * @param RTC_Format: specifies the format of the returned parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will \r
+ * contain the returned current time configuration.\r
+ * @retval None\r
+ */\r
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+\r
+ /* Get the RTC_TR register */\r
+ tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); \r
+ \r
+ /* Fill the structure fields with the read parameters */\r
+ RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r
+ RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);\r
+ RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));\r
+ RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); \r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ /* Convert the structure parameters to Binary format */\r
+ RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);\r
+ RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);\r
+ RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets the RTC current Calendar Subseconds value.\r
+ * @note This function freeze the Time and Date registers after reading the \r
+ * SSR register.\r
+ * @param None\r
+ * @retval RTC current Calendar Subseconds value.\r
+ */\r
+uint32_t RTC_GetSubSecond(void)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Get subseconds values from the correspondent registers*/\r
+ tmpreg = (uint32_t)(RTC->SSR);\r
+ \r
+ /* Read DR register to unfroze calendar registers */\r
+ (void) (RTC->DR);\r
+ \r
+ return (tmpreg);\r
+}\r
+\r
+/**\r
+ * @brief Set the RTC current date.\r
+ * @param RTC_Format: specifies the format of the entered parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains \r
+ * the date configuration information for the RTC.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Date register is configured\r
+ * - ERROR: RTC Date register is not configured\r
+ */\r
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+\r
+ if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))\r
+ {\r
+ RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;\r
+ } \r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));\r
+ assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));\r
+ assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));\r
+ tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);\r
+ assert_param(IS_RTC_MONTH(tmpreg));\r
+ tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);\r
+ assert_param(IS_RTC_DATE(tmpreg));\r
+ }\r
+ assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));\r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format != RTC_Format_BIN)\r
+ {\r
+ tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \\r
+ (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \\r
+ ((uint32_t)RTC_DateStruct->RTC_Date) | \\r
+ (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); \r
+ } \r
+ else\r
+ {\r
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \\r
+ ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));\r
+ }\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Set Initialization mode */\r
+ if (RTC_EnterInitMode() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ /* Set the RTC_DR register */\r
+ RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);\r
+\r
+ /* Exit Initialization mode */\r
+ RTC_ExitInitMode(); \r
+\r
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r
+ if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)\r
+ {\r
+ if (RTC_WaitForSynchro() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_DateStruct member with its default value\r
+ * (Monday, January 01 xx00).\r
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be \r
+ * initialized.\r
+ * @retval None\r
+ */\r
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)\r
+{\r
+ /* Monday, January 01 xx00 */\r
+ RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;\r
+ RTC_DateStruct->RTC_Date = 1;\r
+ RTC_DateStruct->RTC_Month = RTC_Month_January;\r
+ RTC_DateStruct->RTC_Year = 0;\r
+}\r
+\r
+/**\r
+ * @brief Get the RTC current date.\r
+ * @param RTC_Format: specifies the format of the returned parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will \r
+ * contain the returned current date configuration.\r
+ * @retval None\r
+ */\r
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ \r
+ /* Get the RTC_TR register */\r
+ tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); \r
+\r
+ /* Fill the structure fields with the read parameters */\r
+ RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);\r
+ RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r
+ RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));\r
+ RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); \r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ /* Convert the structure parameters to Binary format */\r
+ RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);\r
+ RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);\r
+ RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);\r
+ RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay); \r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group3 Alarms configuration functions\r
+ * @brief Alarms (Alarm A) configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Alarms (Alarm A and Alarm B) configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provide functions allowing to program and read the RTC \r
+ Alarms.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set the specified RTC Alarm.\r
+ * @note The Alarm register can only be written when the corresponding Alarm\r
+ * is disabled (Use the RTC_AlarmCmd(DISABLE)). \r
+ * @param RTC_Format: specifies the format of the returned parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_Alarm: specifies the alarm to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A\r
+ * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that \r
+ * contains the alarm configuration parameters.\r
+ * @retval None\r
+ */\r
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ assert_param(IS_RTC_ALARM(RTC_Alarm));\r
+ assert_param(IS_RTC_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));\r
+\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));\r
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));\r
+ } \r
+ else\r
+ {\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));\r
+ }\r
+ assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));\r
+ assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));\r
+ \r
+ if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);\r
+ assert_param(IS_RTC_HOUR12(tmpreg));\r
+ assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));\r
+ } \r
+ else\r
+ {\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;\r
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));\r
+ }\r
+ \r
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));\r
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));\r
+ \r
+ if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); \r
+ }\r
+ else\r
+ {\r
+ tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); \r
+ } \r
+ }\r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format != RTC_Format_BIN)\r
+ {\r
+ tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); \r
+ } \r
+ else\r
+ {\r
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \\r
+ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \\r
+ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \\r
+ ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); \r
+ }\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Configure the Alarm register */\r
+ RTC->ALRMAR = (uint32_t)tmpreg;\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+}\r
+\r
+/**\r
+ * @brief Fills each RTC_AlarmStruct member with its default value\r
+ * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =\r
+ * all fields are masked).\r
+ * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which\r
+ * will be initialized.\r
+ * @retval None\r
+ */\r
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)\r
+{\r
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;\r
+\r
+ /* Alarm Date Settings : Date = 1st day of the month */\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;\r
+\r
+ /* Alarm Masks Settings : Mask = all fields are not masked */\r
+ RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;\r
+}\r
+\r
+/**\r
+ * @brief Get the RTC Alarm value and masks.\r
+ * @param RTC_Format: specifies the format of the output parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_Alarm: specifies the alarm to be read.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A\r
+ * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will \r
+ * contains the output alarm configuration values.\r
+ * @retval None\r
+ */\r
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+ assert_param(IS_RTC_ALARM(RTC_Alarm)); \r
+\r
+ /* Get the RTC_ALRMAR register */\r
+ tmpreg = (uint32_t)(RTC->ALRMAR);\r
+\r
+ /* Fill the structure with the read parameters */\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \\r
+ RTC_ALRMAR_HU)) >> 16);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \\r
+ RTC_ALRMAR_MNU)) >> 8);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \\r
+ RTC_ALRMAR_SU));\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);\r
+ RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);\r
+\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\r
+ RTC_AlarmTime.RTC_Hours);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\r
+ RTC_AlarmTime.RTC_Minutes);\r
+ RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \\r
+ RTC_AlarmTime.RTC_Seconds);\r
+ RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified RTC Alarm.\r
+ * @param RTC_Alarm: specifies the alarm to be configured.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A\r
+ * @param NewState: new state of the specified alarm.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Alarm is enabled/disabled\r
+ * - ERROR: RTC Alarm is not enabled/disabled \r
+ */\r
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)\r
+{\r
+ __IO uint32_t alarmcounter = 0x00;\r
+ uint32_t alarmstatus = 0x00;\r
+ ErrorStatus status = ERROR;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Configure the Alarm state */\r
+ if (NewState != DISABLE)\r
+ {\r
+ RTC->CR |= (uint32_t)RTC_Alarm;\r
+\r
+ status = SUCCESS; \r
+ }\r
+ else\r
+ { \r
+ /* Disable the Alarm in RTC_CR register */\r
+ RTC->CR &= (uint32_t)~RTC_Alarm;\r
+ \r
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */\r
+ do\r
+ {\r
+ alarmstatus = RTC->ISR & (RTC_Alarm >> 8);\r
+ alarmcounter++; \r
+ } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));\r
+ \r
+ if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)\r
+ {\r
+ status = ERROR;\r
+ } \r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ } \r
+ } \r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Configure the RTC AlarmA/B Subseconds value and mask.\r
+ * @note This function is performed only when the Alarm is disabled. \r
+ * @param RTC_Alarm: specifies the alarm to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A\r
+ * @param RTC_AlarmSubSecondValue: specifies the Subseconds value.\r
+ * This parameter can be a value from 0 to 0x00007FFF.\r
+ * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked.\r
+ * There is no comparison on sub seconds for Alarm.\r
+ * @arg RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison.\r
+ * Only SS[0] is compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison.\r
+ * Only SS[1:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison.\r
+ * Only SS[2:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison.\r
+ * Only SS[3:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison.\r
+ * Only SS[4:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison.\r
+ * Only SS[5:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison.\r
+ * Only SS[6:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison.\r
+ * Only SS[7:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison.\r
+ * Only SS[8:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.\r
+ * Only SS[9:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.\r
+ * Only SS[10:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.\r
+ * Only SS[11:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.\r
+ * Only SS[12:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison.\r
+ * Only SS[13:0] are compared\r
+ * @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match\r
+ * to activate alarm\r
+ * @retval None\r
+ */\r
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_ALARM(RTC_Alarm));\r
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));\r
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* Configure the Alarm A or Alarm B SubSecond registers */\r
+ tmpreg = (uint32_t) (((uint32_t)(RTC_AlarmSubSecondValue)) | ((uint32_t)(RTC_AlarmSubSecondMask) << 24));\r
+ \r
+ /* Configure the AlarmA SubSecond register */\r
+ RTC->ALRMASSR = tmpreg;\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Gets the RTC Alarm Subseconds value.\r
+ * @param RTC_Alarm: specifies the alarm to be read.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Alarm_A: to select Alarm A\r
+ * @param None\r
+ * @retval RTC Alarm Subseconds value.\r
+ */\r
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Get the RTC_ALRMAR register */\r
+ tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);\r
+\r
+ return (tmpreg);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group4 Daylight Saving configuration functions\r
+ * @brief Daylight Saving configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### WakeUp Timer configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provide functions allowing to program and read the RTC WakeUp. \r
+\r
+ This section provide functions allowing to configure the RTC DayLight Saving.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Adds or substract one hour from the current time.\r
+ * @param RTC_DayLightSaveOperation: the value of hour adjustment. \r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)\r
+ * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)\r
+ * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit \r
+ * in CR register to store the operation.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_StoreOperation_Reset\r
+ * @arg RTC_StoreOperation_Set\r
+ * @retval None\r
+ */\r
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));\r
+ assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Clear the bits to be configured */\r
+ RTC->CR &= (uint32_t)~(RTC_CR_BCK);\r
+\r
+ /* Configure the RTC_CR register */\r
+ RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+}\r
+\r
+/**\r
+ * @brief Returns the RTC Day Light Saving stored operation.\r
+ * @param None\r
+ * @retval RTC Day Light Saving stored operation.\r
+ * - RTC_StoreOperation_Reset\r
+ * - RTC_StoreOperation_Set\r
+ */\r
+uint32_t RTC_GetStoreOperation(void)\r
+{\r
+ return (RTC->CR & RTC_CR_BCK);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group5 Output pin Configuration function\r
+ * @brief Output pin Configuration function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Output pin Configuration function #####\r
+ ===============================================================================\r
+ [..] This section provide functions allowing to configure the RTC Output source.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC output source (AFO_ALARM).\r
+ * @param RTC_Output: Specifies which signal will be routed to the RTC output. \r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Output_Disable: No output selected\r
+ * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output\r
+ * @param RTC_OutputPolarity: Specifies the polarity of the output signal. \r
+ * This parameter can be one of the following:\r
+ * @arg RTC_OutputPolarity_High: The output pin is high when the \r
+ * ALRAF is high (depending on OSEL)\r
+ * @arg RTC_OutputPolarity_Low: The output pin is low when the \r
+ * ALRAF is high (depending on OSEL)\r
+ * @retval None\r
+ */\r
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_OUTPUT(RTC_Output));\r
+ assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Clear the bits to be configured */\r
+ RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);\r
+\r
+ /* Configure the output selection and polarity */\r
+ RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group7 Digital Calibration configuration functions\r
+ * @brief Digital Calibration configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Digital Calibration configuration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the RTC clock to be output through the relative \r
+ * pin.\r
+ * @param NewState: new state of the digital calibration Output.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_CalibOutputCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the RTC clock output */\r
+ RTC->CR |= (uint32_t)RTC_CR_COE;\r
+ }\r
+ else\r
+ { \r
+ /* Disable the RTC clock output */\r
+ RTC->CR &= (uint32_t)~RTC_CR_COE;\r
+ }\r
+ \r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r
+ * @param RTC_CalibOutput : Select the Calibration output Selection .\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. \r
+ * @arg RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz.\r
+ * @retval None\r
+*/\r
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /*clear flags before config*/\r
+ RTC->CR &= (uint32_t)~(RTC_CR_CALSEL);\r
+\r
+ /* Configure the RTC_CR register */\r
+ RTC->CR |= (uint32_t)RTC_CalibOutput;\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Smooth Calibration Settings.\r
+ * @param RTC_SmoothCalibPeriod: Select the Smooth Calibration Period.\r
+ * This parameter can be can be one of the following values:\r
+ * @arg RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s.\r
+ * @arg RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s.\r
+ * @arg RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s.\r
+ * @param RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses.\r
+ * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.\r
+ * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.\r
+ * This parameter can be one any value from 0 to 0x000001FF.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Calib registers are configured\r
+ * - ERROR: RTC Calib registers are not configured\r
+*/\r
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,\r
+ uint32_t RTC_SmoothCalibPlusPulses,\r
+ uint32_t RTC_SmouthCalibMinusPulsesValue)\r
+{\r
+ ErrorStatus status = ERROR;\r
+ uint32_t recalpfcount = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));\r
+ assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));\r
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* check if a calibration is pending*/\r
+ if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)\r
+ {\r
+ /* wait until the Calibration is completed*/\r
+ while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))\r
+ {\r
+ recalpfcount++;\r
+ }\r
+ }\r
+\r
+ /* check if the calibration pending is completed or if there is no calibration operation at all*/\r
+ if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)\r
+ {\r
+ /* Configure the Smooth calibration settings */\r
+ RTC->CAL = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);\r
+\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+ \r
+ return (ErrorStatus)(status);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RTC_Group7 TimeStamp configuration functions\r
+ * @brief TimeStamp configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### TimeStamp configuration functions #####\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or Disables the RTC TimeStamp functionality with the \r
+ * specified time stamp pin stimulating edge.\r
+ * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is \r
+ * activated.\r
+ * This parameter can be one of the following:\r
+ * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising \r
+ * edge of the related pin.\r
+ * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the \r
+ * falling edge of the related pin.\r
+ * @param NewState: new state of the TimeStamp.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Get the RTC_CR register and clear the bits to be configured */\r
+ tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r
+\r
+ /* Get the new configuration */\r
+ if (NewState != DISABLE)\r
+ {\r
+ tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);\r
+ }\r
+ else\r
+ {\r
+ tmpreg |= (uint32_t)(RTC_TimeStampEdge);\r
+ }\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ /* Configure the Time Stamp TSEDGE and Enable bits */\r
+ RTC->CR = (uint32_t)tmpreg;\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+}\r
+\r
+/**\r
+ * @brief Get the RTC TimeStamp value and masks.\r
+ * @param RTC_Format: specifies the format of the output parameters.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_Format_BIN: Binary data format \r
+ * @arg RTC_Format_BCD: BCD data format\r
+ * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will \r
+ * contains the TimeStamp time values. \r
+ * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will \r
+ * contains the TimeStamp date values. \r
+ * @retval None\r
+ */\r
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, \r
+ RTC_DateTypeDef* RTC_StampDateStruct)\r
+{\r
+ uint32_t tmptime = 0, tmpdate = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_FORMAT(RTC_Format));\r
+\r
+ /* Get the TimeStamp time and date registers values */\r
+ tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);\r
+ tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);\r
+\r
+ /* Fill the Time structure fields with the read parameters */\r
+ RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r
+ RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);\r
+ RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));\r
+ RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); \r
+\r
+ /* Fill the Date structure fields with the read parameters */\r
+ RTC_StampDateStruct->RTC_Year = 0;\r
+ RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r
+ RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));\r
+ RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);\r
+\r
+ /* Check the input parameters format */\r
+ if (RTC_Format == RTC_Format_BIN)\r
+ {\r
+ /* Convert the Time structure parameters to Binary format */\r
+ RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);\r
+ RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);\r
+ RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);\r
+\r
+ /* Convert the Date structure parameters to Binary format */\r
+ RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);\r
+ RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);\r
+ RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get the RTC timestamp Subseconds value.\r
+ * @param None\r
+ * @retval RTC current timestamp Subseconds value.\r
+ */\r
+uint32_t RTC_GetTimeStampSubSecond(void)\r
+{\r
+ /* Get timestamp subseconds values from the correspondent registers */\r
+ return (uint32_t)(RTC->TSSSR);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group8 Tampers configuration functions\r
+ * @brief Tampers configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Tampers configuration functions #####\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the select Tamper pin edge.\r
+ * @param RTC_Tamper: Selected tamper pin.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_Tamper_1: Select Tamper 1.\r
+ * @arg RTC_Tamper_2: Select Tamper 2.\r
+ * @arg RTC_Tamper_3: Select Tamper 3.\r
+ * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that \r
+ * stimulates tamper event. \r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.\r
+ * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.\r
+ * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.\r
+ * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.\r
+ * @retval None\r
+ */\r
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER(RTC_Tamper)); \r
+ assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));\r
+ \r
+ if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)\r
+ { \r
+ /* Configure the RTC_TAFCR register */\r
+ RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); \r
+ }\r
+ else\r
+ { \r
+ /* Configure the RTC_TAFCR register */\r
+ RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the Tamper detection.\r
+ * @param RTC_Tamper: Selected tamper pin.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_Tamper_1: Select Tamper 1.\r
+ * @arg RTC_Tamper_2: Select Tamper 2.\r
+ * @arg RTC_Tamper_3: Select Tamper 3.\r
+ * @param NewState: new state of the tamper pin.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER(RTC_Tamper)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected Tamper pin */\r
+ RTC->TAFCR |= (uint32_t)RTC_Tamper;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected Tamper pin */\r
+ RTC->TAFCR &= (uint32_t)~RTC_Tamper; \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Configures the Tampers Filter.\r
+ * @param RTC_TamperFilter: Specifies the tampers filter.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TamperFilter_Disable: Tamper filter is disabled.\r
+ * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive \r
+ * samples at the active level \r
+ * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive \r
+ * samples at the active level\r
+ * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive \r
+ * samples at the active level \r
+ * @retval None\r
+ */\r
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));\r
+ \r
+ /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */\r
+ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);\r
+\r
+ /* Configure the RTC_TAFCR register */\r
+ RTC->TAFCR |= (uint32_t)RTC_TamperFilter;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Tampers Sampling Frequency.\r
+ * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 32768\r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 16384\r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 8192\r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 4096\r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 2048\r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 1024\r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 512 \r
+ * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled\r
+ * with a frequency = RTCCLK / 256 \r
+ * @retval None\r
+ */\r
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));\r
+ \r
+ /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */\r
+ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);\r
+\r
+ /* Configure the RTC_TAFCR register */\r
+ RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Tampers Pins input Precharge Duration.\r
+ * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input\r
+ * Precharge Duration.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle\r
+ * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle\r
+ * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle \r
+ * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle\r
+ * @retval None\r
+ */\r
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));\r
+ \r
+ /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */\r
+ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);\r
+\r
+ /* Configure the RTC_TAFCR register */\r
+ RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the TimeStamp on Tamper Detection Event.\r
+ * @note The timestamp is valid even the TSE bit in tamper control register \r
+ * is reset. \r
+ * @param NewState: new state of the timestamp on tamper event.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Save timestamp on tamper detection event */\r
+ RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;\r
+ }\r
+ else\r
+ {\r
+ /* Tamper detection does not cause a timestamp to be saved */\r
+ RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the Precharge of Tamper pin.\r
+ * @param NewState: new state of tamper pull up.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void RTC_TamperPullUpCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable precharge of the selected Tamper pin */\r
+ RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; \r
+ }\r
+ else\r
+ {\r
+ /* Disable precharge of the selected Tamper pin */\r
+ RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; \r
+ } \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group9 Backup Data Registers configuration functions\r
+ * @brief Backup Data Registers configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Backup Data Registers configuration functions ##### \r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Writes a data in a specified RTC Backup data register.\r
+ * @param RTC_BKP_DR: RTC Backup data Register number.\r
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to \r
+ * specify the register.\r
+ * @param Data: Data to be written in the specified RTC Backup data register. \r
+ * @retval None\r
+ */\r
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_BKP(RTC_BKP_DR));\r
+\r
+ tmp = RTC_BASE + 0x50;\r
+ tmp += (RTC_BKP_DR * 4);\r
+\r
+ /* Write the specified register */\r
+ *(__IO uint32_t *)tmp = (uint32_t)Data;\r
+}\r
+\r
+/**\r
+ * @brief Reads data from the specified RTC Backup data Register.\r
+ * @param RTC_BKP_DR: RTC Backup data Register number.\r
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r
+ * specify the register. \r
+ * @retval None\r
+ */\r
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_BKP(RTC_BKP_DR));\r
+\r
+ tmp = RTC_BASE + 0x50;\r
+ tmp += (RTC_BKP_DR * 4);\r
+ \r
+ /* Read the specified register */\r
+ return (*(__IO uint32_t *)tmp);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group10 Output Type Config configuration functions\r
+ * @brief Output Type Config configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Output Type Config configuration functions ##### \r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the RTC Output Pin mode. \r
+ * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in \r
+ * Open Drain mode.\r
+ * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in \r
+ * Push Pull mode. \r
+ * @retval None\r
+ */\r
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));\r
+ \r
+ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);\r
+ RTC->TAFCR |= (uint32_t)(RTC_OutputType); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group11 Shift control synchronisation functions\r
+ * @brief Shift control synchronisation functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Shift control synchronisation functions #####\r
+ =============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the Synchronization Shift Control Settings.\r
+ * @note When REFCKON is set, firmware must not write to Shift control register \r
+ * @param RTC_ShiftAdd1S: Select to add or not 1 second to the time Calendar.\r
+ * This parameter can be one of the following values :\r
+ * @arg RTC_ShiftAdd1S_Set: Add one second to the clock calendar. \r
+ * @arg RTC_ShiftAdd1S_Reset: No effect.\r
+ * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.\r
+ * This parameter can be one any value from 0 to 0x7FFF.\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: RTC Shift registers are configured\r
+ * - ERROR: RTC Shift registers are not configured\r
+*/\r
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)\r
+{\r
+ ErrorStatus status = ERROR;\r
+ uint32_t shpfcount = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));\r
+ assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+ \r
+ /* Check if a Shift is pending*/\r
+ if ((RTC->ISR & RTC_ISR_SHPF) != RESET)\r
+ {\r
+ /* Wait until the shift is completed*/\r
+ while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))\r
+ {\r
+ shpfcount++;\r
+ }\r
+ }\r
+\r
+ /* Check if the Shift pending is completed or if there is no Shift operation at all*/\r
+ if ((RTC->ISR & RTC_ISR_SHPF) == RESET)\r
+ {\r
+ /* check if the reference clock detection is disabled */\r
+ if((RTC->CR & RTC_CR_REFCKON) == RESET)\r
+ {\r
+ /* Configure the Shift settings */\r
+ RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);\r
+ \r
+ if(RTC_WaitForSynchro() == ERROR)\r
+ {\r
+ status = ERROR;\r
+ }\r
+ else\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ }\r
+\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF;\r
+ \r
+ return (ErrorStatus)(status);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Group12 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ =============================================================================== \r
+ [..] All RTC interrupts are connected to the EXTI controller.\r
+ \r
+ (+) To enable the RTC Alarm interrupt, the following sequence is required:\r
+ (+) Configure and enable the EXTI Line 17 in interrupt mode and select the rising \r
+ edge sensitivity using the EXTI_Init() function.\r
+ (+) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init()\r
+ function.\r
+ (+) Configure the RTC to generate RTC alarms (Alarm A) using\r
+ the RTC_SetAlarm() and RTC_AlarmCmd() functions.\r
+\r
+ (+) To enable the RTC Tamper interrupt, the following sequence is required:\r
+ (+) Configure and enable the EXTI Line 19 in interrupt mode and select the rising \r
+ edge sensitivity using the EXTI_Init() function.\r
+ (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()\r
+ function.\r
+ (+) Configure the RTC to detect the RTC tamper event using the \r
+ RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.\r
+\r
+ (+) To enable the RTC TimeStamp interrupt, the following sequence is required:\r
+ (+) Configure and enable the EXTI Line 19 in interrupt mode and select the rising \r
+ edge sensitivity using the EXTI_Init() function.\r
+ (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()\r
+ function.\r
+ (+) Configure the RTC to detect the RTC time-stamp event using the \r
+ RTC_TimeStampCmd() functions.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified RTC interrupts.\r
+ * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_IT_TS: Time Stamp interrupt mask\r
+ * @arg RTC_IT_ALRA: Alarm A interrupt mask\r
+ * @arg RTC_IT_TAMP: Tamper event interrupt mask\r
+ * @param NewState: new state of the specified RTC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CONFIG_IT(RTC_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* Disable the write protection for RTC registers */\r
+ RTC->WPR = 0xCA;\r
+ RTC->WPR = 0x53;\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Configure the Interrupts in the RTC_CR register */\r
+ RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);\r
+ /* Configure the Tamper Interrupt in the RTC_TAFCR */\r
+ RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);\r
+ }\r
+ else\r
+ {\r
+ /* Configure the Interrupts in the RTC_CR register */\r
+ RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);\r
+ /* Configure the Tamper Interrupt in the RTC_TAFCR */\r
+ RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);\r
+ }\r
+ /* Enable the write protection for RTC registers */\r
+ RTC->WPR = 0xFF; \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RTC flag is set or not.\r
+ * @param RTC_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_FLAG_RECALPF: RECALPF event flag\r
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag\r
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag \r
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag\r
+ * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag\r
+ * @arg RTC_FLAG_TSF: Time Stamp event flag\r
+ * @arg RTC_FLAG_ALRAF: Alarm A flag\r
+ * @arg RTC_FLAG_INITF: Initialization mode flag\r
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag\r
+ * @arg RTC_FLAG_INITS: Registers Configured flag\r
+ * @retval The new state of RTC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_GET_FLAG(RTC_FLAG));\r
+ \r
+ /* Get all the flags */\r
+ tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);\r
+ \r
+ /* Return the status of the flag */\r
+ if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RTC's pending flags.\r
+ * @param RTC_FLAG: specifies the RTC flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag\r
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag\r
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag \r
+ * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag \r
+ * @arg RTC_FLAG_TSF: Time Stamp event flag\r
+ * @arg RTC_FLAG_ALRAF: Alarm A flag\r
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag\r
+ * @retval None\r
+ */\r
+void RTC_ClearFlag(uint32_t RTC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));\r
+\r
+ /* Clear the Flags in the RTC_ISR register */\r
+ RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RTC interrupt has occurred or not.\r
+ * @param RTC_IT: specifies the RTC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_IT_TS: Time Stamp interrupt \r
+ * @arg RTC_IT_ALRA: Alarm A interrupt \r
+ * @arg RTC_IT_TAMP1: Tamper1 event interrupt \r
+ * @arg RTC_IT_TAMP2: Tamper2 event interrupt \r
+ * @arg RTC_IT_TAMP3: Tamper3 event interrupt\r
+ * @retval The new state of RTC_IT (SET or RESET).\r
+ */\r
+ITStatus RTC_GetITStatus(uint32_t RTC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0, enablestatus = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_GET_IT(RTC_IT));\r
+ \r
+ /* Get the TAMPER Interrupt enable bit and pending bit */\r
+ tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));\r
+ \r
+ /* Get the Interrupt enable Status */\r
+ enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15)));\r
+ \r
+ /* Get the Interrupt pending bit */\r
+ tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));\r
+ \r
+ /* Get the status of the Interrupt */\r
+ if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RTC's interrupt pending bits.\r
+ * @param RTC_IT: specifies the RTC interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_IT_TS: Time Stamp interrupt \r
+ * @arg RTC_IT_ALRA: Alarm A interrupt \r
+ * @arg RTC_IT_TAMP1: Tamper1 event interrupt\r
+ * @arg RTC_IT_TAMP2: Tamper2 event interrupt\r
+ * @arg RTC_IT_TAMP3: Tamper3 event interrupt \r
+ * @retval None\r
+ */\r
+void RTC_ClearITPendingBit(uint32_t RTC_IT)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CLEAR_IT(RTC_IT));\r
+\r
+ /* Get the RTC_ISR Interrupt pending bits mask */\r
+ tmpreg = (uint32_t)(RTC_IT >> 4);\r
+\r
+ /* Clear the interrupt pending bits in the RTC_ISR register */\r
+ RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Converts a 2 digit decimal to BCD format.\r
+ * @param Value: Byte to be converted.\r
+ * @retval Converted byte\r
+ */\r
+static uint8_t RTC_ByteToBcd2(uint8_t Value)\r
+{\r
+ uint8_t bcdhigh = 0;\r
+ \r
+ while (Value >= 10)\r
+ {\r
+ bcdhigh++;\r
+ Value -= 10;\r
+ }\r
+ \r
+ return ((uint8_t)(bcdhigh << 4) | Value);\r
+}\r
+\r
+/**\r
+ * @brief Convert from 2 digit BCD to Binary.\r
+ * @param Value: BCD value to be converted.\r
+ * @retval Converted word\r
+ */\r
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)\r
+{\r
+ uint8_t tmp = 0;\r
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;\r
+ return (tmp + (Value & (uint8_t)0x0F));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_spi.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Serial peripheral interface (SPI):\r
+ * + Initialization and Configuration\r
+ * + Data transfers functions\r
+ * + Hardware CRC Calculation\r
+ * + DMA transfers management\r
+ * + Interrupts and flags management\r
+ *\r
+ * @verbatim\r
+\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)\r
+ function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)\r
+ function for SPI2.\r
+ \r
+ (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using \r
+ RCC_AHBPeriphClockCmd() function. \r
+ \r
+ (#) Peripherals alternate function: \r
+ (++) Connect the pin to the desired peripherals' Alternate \r
+ Function (AF) using GPIO_PinAFConfig() function.\r
+ (++) Configure the desired pin in alternate function by:\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.\r
+ (++) Select the type, pull-up/pull-down and output speed via \r
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members.\r
+ (++) Call GPIO_Init() function.\r
+ \r
+ (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave \r
+ Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()\r
+ function.In I2S mode, program the Mode, Standard, Data Format, MCLK \r
+ Output, Audio frequency and Polarity using I2S_Init() function.\r
+ \r
+ (#) Enable the NVIC and the corresponding interrupt using the function \r
+ SPI_ITConfig() if you need to use interrupt mode. \r
+ \r
+ (#) When using the DMA mode \r
+ (++) Configure the DMA using DMA_Init() function.\r
+ (++) Active the needed channel Request using SPI_I2S_DMACmd() function.\r
+ \r
+ (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using\r
+ I2S_Cmd().\r
+ \r
+ (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. \r
+ \r
+ (#) Optionally, you can enable/configure the following parameters without\r
+ re-initialization (i.e there is no need to call again SPI_Init() function):\r
+ (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)\r
+ is programmed as Data direction parameter using the SPI_Init() \r
+ function it can be possible to switch between SPI_Direction_Tx \r
+ or SPI_Direction_Rx using the SPI_BiDirectionalLineConfig() function.\r
+ (++) When SPI_NSS_Soft is selected as Slave Select Management parameter \r
+ using the SPI_Init() function it can be possible to manage the \r
+ NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.\r
+ (++) Reconfigure the data size using the SPI_DataSizeConfig() function.\r
+ (++) Enable or disable the SS output using the SPI_SSOutputCmd() function. \r
+ \r
+ (#) To use the CRC Hardware calculation feature refer to the Peripheral \r
+ CRC hardware Calculation subsection.\r
+ \r
+ @endverbatim \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_spi.h"\r
+#include "stm32f0xx_rcc.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI\r
+ * @brief SPI driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* SPI registers Masks */\r
+#define CR1_CLEAR_MASK ((uint16_t)0x3040)\r
+#define CR1_CLEAR_MASK2 ((uint16_t)0xFFFB)\r
+#define CR2_LDMA_MASK ((uint16_t)0x9FFF)\r
+\r
+#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SPI_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provides a set of functions allowing to initialize the SPI Direction,\r
+ SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud\r
+ Rate Prescaler, SPI First Bit and SPI CRC Polynomial.\r
+\r
+ [..] The SPI_Init() function follows the SPI configuration procedures for Master mode\r
+ and Slave mode (details for these procedures are available in reference manual).\r
+ \r
+ [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected,\r
+ use the following function to manage the NSS bit:\r
+ void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);\r
+\r
+ [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard)\r
+ is selected, use the follwoing function to enable the NSS output feature.\r
+ void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+\r
+ [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the following function:\r
+ void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+ And it can be managed by software in the SPI Motorola mode using this function: \r
+ void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+\r
+ [..] This section provides also functions to initialize the I2S Mode, Standard, \r
+ Data Format, MCLK Output, Audio frequency and Polarity.\r
+ \r
+ [..] The I2S_Init() function follows the I2S configuration procedures for Master mode\r
+ and Slave mode.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the SPIx peripheral registers to their default\r
+ * reset values.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+\r
+ if (SPIx == SPI1)\r
+ {\r
+ /* Enable SPI1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);\r
+ /* Release SPI1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if (SPIx == SPI2)\r
+ {\r
+ /* Enable SPI2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);\r
+ /* Release SPI2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each SPI_InitStruct member with its default value.\r
+ * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+/*--------------- Reset SPI init structure parameters values -----------------*/\r
+ /* Initialize the SPI_Direction member */\r
+ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+ /* Initialize the SPI_Mode member */\r
+ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;\r
+ /* Initialize the SPI_DataSize member */\r
+ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;\r
+ /* Initialize the SPI_CPOL member */\r
+ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;\r
+ /* Initialize the SPI_CPHA member */\r
+ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;\r
+ /* Initialize the SPI_NSS member */\r
+ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;\r
+ /* Initialize the SPI_BaudRatePrescaler member */\r
+ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+ /* Initialize the SPI_FirstBit member */\r
+ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;\r
+ /* Initialize the SPI_CRCPolynomial member */\r
+ SPI_InitStruct->SPI_CRCPolynomial = 7;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SPIx peripheral according to the specified \r
+ * parameters in the SPI_InitStruct.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that\r
+ * contains the configuration information for the specified SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0;\r
+\r
+ /* check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+\r
+ /* Check the SPI parameters */\r
+ assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));\r
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));\r
+ assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize));\r
+ assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));\r
+ assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));\r
+ assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));\r
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));\r
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));\r
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));\r
+\r
+ /*---------------------------- SPIx CR1 Configuration ------------------------*/\r
+ /* Get the SPIx CR1 value */\r
+ tmpreg = SPIx->CR1;\r
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, CPOL and CPHA bits */\r
+ tmpreg &= CR1_CLEAR_MASK;\r
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler\r
+ master/slave mode, CPOL and CPHA */\r
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */\r
+ /* Set SSM, SSI bit according to SPI_NSS values */\r
+ /* Set LSBFirst bit according to SPI_FirstBit value */\r
+ /* Set BR bits according to SPI_BaudRatePrescaler value */\r
+ /* Set CPOL bit according to SPI_CPOL value */\r
+ /* Set CPHA bit according to SPI_CPHA value */\r
+ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit |\r
+ SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA |\r
+ SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler); \r
+ /* Write to SPIx CR1 */\r
+ SPIx->CR1 = tmpreg;\r
+ /*-------------------------Data Size Configuration -----------------------*/\r
+ /* Get the SPIx CR2 value */\r
+ tmpreg = SPIx->CR2;\r
+ /* Clear DS[3:0] bits */\r
+ tmpreg &=(uint16_t)~SPI_CR2_DS;\r
+ /* Configure SPIx: Data Size */\r
+ tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);\r
+ /* Write to SPIx CR2 */\r
+ SPIx->CR2 = tmpreg;\r
+ \r
+ /*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
+ /* Write to SPIx CRCPOLY */\r
+ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;\r
+ \r
+ /*---------------------------- SPIx CR1 Configuration ------------------------*/\r
+ /* Get the SPIx CR1 value */\r
+ tmpreg = SPIx->CR1;\r
+ /* Clear MSTR bit */\r
+ tmpreg &= CR1_CLEAR_MASK2;\r
+ /* Configure SPIx: master/slave mode */ \r
+ /* Set MSTR bit according to SPI_Mode */\r
+ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Mode); \r
+ /* Write to SPIx CR1 */\r
+ SPIx->CR1 = tmpreg; \r
+ \r
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */\r
+ SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);\r
+}\r
+\r
+/**\r
+ * @brief Fills each I2S_InitStruct member with its default value.\r
+ * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)\r
+{\r
+/*--------------- Reset I2S init structure parameters values -----------------*/\r
+ /* Initialize the I2S_Mode member */\r
+ I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;\r
+\r
+ /* Initialize the I2S_Standard member */\r
+ I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;\r
+\r
+ /* Initialize the I2S_DataFormat member */\r
+ I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;\r
+\r
+ /* Initialize the I2S_MCLKOutput member */\r
+ I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;\r
+\r
+ /* Initialize the I2S_AudioFreq member */\r
+ I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;\r
+\r
+ /* Initialize the I2S_CPOL member */\r
+ I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SPIx peripheral according to the specified \r
+ * parameters in the I2S_InitStruct.\r
+ * @param SPIx: where x can be 1 to select the SPI peripheral.\r
+ * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that\r
+ * contains the configuration information for the specified SPI peripheral\r
+ * configured in I2S mode.\r
+ * @note\r
+ * The function calculates the optimal prescaler needed to obtain the most \r
+ * accurate audio frequency (depending on the I2S clock source, the PLL values \r
+ * and the product configuration). But in case the prescaler value is greater \r
+ * than 511, the default value (0x02) will be configured instead. \r
+ * @retval None\r
+ */\r
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;\r
+ uint32_t tmp = 0;\r
+ RCC_ClocksTypeDef RCC_Clocks;\r
+ uint32_t sourceclock = 0;\r
+\r
+ /* Check the I2S parameters */\r
+ assert_param(IS_SPI_1_PERIPH(SPIx));\r
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));\r
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));\r
+ assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));\r
+ assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));\r
+ assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));\r
+ assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); \r
+\r
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r
+ SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; \r
+ SPIx->I2SPR = 0x0002;\r
+\r
+ /* Get the I2SCFGR register value */\r
+ tmpreg = SPIx->I2SCFGR;\r
+\r
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/\r
+ if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)\r
+ {\r
+ i2sodd = (uint16_t)0;\r
+ i2sdiv = (uint16_t)2; \r
+ }\r
+ /* If the requested audio frequency is not the default, compute the prescaler */\r
+ else\r
+ {\r
+ /* Check the frame length (For the Prescaler computing) */\r
+ if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)\r
+ {\r
+ /* Packet length is 16 bits */\r
+ packetlength = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Packet length is 32 bits */\r
+ packetlength = 2;\r
+ }\r
+\r
+ /* I2S Clock source is System clock: Get System Clock frequency */\r
+ RCC_GetClocksFreq(&RCC_Clocks); \r
+\r
+ /* Get the source clock value: based on System Clock value */\r
+ sourceclock = RCC_Clocks.SYSCLK_Frequency; \r
+\r
+ /* Compute the Real divider depending on the MCLK output state with a floating point */\r
+ if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)\r
+ {\r
+ /* MCLK output is enabled */\r
+ tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
+ }\r
+ else\r
+ {\r
+ /* MCLK output is disabled */\r
+ tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
+ }\r
+ \r
+ /* Remove the floating point */\r
+ tmp = tmp / 10;\r
+\r
+ /* Check the parity of the divider */\r
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);\r
+\r
+ /* Compute the i2sdiv prescaler */\r
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);\r
+\r
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */\r
+ i2sodd = (uint16_t) (i2sodd << 8);\r
+ }\r
+\r
+ /* Test if the divider is 1 or 0 or greater than 0xFF */\r
+ if ((i2sdiv < 2) || (i2sdiv > 0xFF))\r
+ {\r
+ /* Set the default values */\r
+ i2sdiv = 2;\r
+ i2sodd = 0;\r
+ }\r
+\r
+ /* Write to SPIx I2SPR register the computed value */\r
+ SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));\r
+\r
+ /* Configure the I2S with the SPI_InitStruct values */\r
+ tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \\r
+ (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \\r
+ (uint16_t)I2S_InitStruct->I2S_CPOL))));\r
+\r
+ /* Write to SPIx I2SCFGR */\r
+ SPIx->I2SCFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI peripheral.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI peripheral */\r
+ SPIx->CR1 |= SPI_CR1_SPE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI peripheral */\r
+ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TI Mode.\r
+ * @note - This function can be called only after the SPI_Init() function has \r
+ * been called. \r
+ * - When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA \r
+ * are not taken into consideration and are configured by hardware \r
+ * respectively to the TI mode requirements. \r
+ * @param SPIx: where x can be 1 to select the SPI peripheral.\r
+ * @param NewState: new state of the selected SPI TI communication mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_1_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the TI mode for the selected SPI peripheral */\r
+ SPIx->CR2 |= SPI_CR2_FRF;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the TI mode for the selected SPI peripheral */\r
+ SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI peripheral (in I2S mode).\r
+ * @param SPIx: where x can be 1 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_1_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI peripheral in I2S mode */\r
+ SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI peripheral in I2S mode */\r
+ SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the data size for the selected SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_DataSize: specifies the SPI data size.\r
+ * For the SPIx peripheral this parameter can be one of the following values:\r
+ * @arg SPI_DataSize_4b: Set data size to 4 bits\r
+ * @arg SPI_DataSize_5b: Set data size to 5 bits\r
+ * @arg SPI_DataSize_6b: Set data size to 6 bits\r
+ * @arg SPI_DataSize_7b: Set data size to 7 bits\r
+ * @arg SPI_DataSize_8b: Set data size to 8 bits\r
+ * @arg SPI_DataSize_9b: Set data size to 9 bits\r
+ * @arg SPI_DataSize_10b: Set data size to 10 bits\r
+ * @arg SPI_DataSize_11b: Set data size to 11 bits\r
+ * @arg SPI_DataSize_12b: Set data size to 12 bits\r
+ * @arg SPI_DataSize_13b: Set data size to 13 bits\r
+ * @arg SPI_DataSize_14b: Set data size to 14 bits\r
+ * @arg SPI_DataSize_15b: Set data size to 15 bits\r
+ * @arg SPI_DataSize_16b: Set data size to 16 bits\r
+ * @retval None\r
+ */\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DATA_SIZE(SPI_DataSize));\r
+ /* Read the CR2 register */\r
+ tmpreg = SPIx->CR2;\r
+ /* Clear DS[3:0] bits */\r
+ tmpreg &= (uint16_t)~SPI_CR2_DS;\r
+ /* Set new DS[3:0] bits value */\r
+ tmpreg |= SPI_DataSize;\r
+ SPIx->CR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the FIFO reception threshold for the selected SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_RxFIFOThreshold: specifies the FIFO reception threshold.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO \r
+ * level is greater or equal to 1/2. \r
+ * @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO \r
+ * level is greater or equal to 1/4. \r
+ * @retval None\r
+ */\r
+void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold));\r
+\r
+ /* Clear FRXTH bit */\r
+ SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH);\r
+\r
+ /* Set new FRXTH bit value */\r
+ SPIx->CR2 |= SPI_RxFIFOThreshold;\r
+}\r
+\r
+/**\r
+ * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_Direction_Tx: Selects Tx transmission direction\r
+ * @arg SPI_Direction_Rx: Selects Rx receive direction\r
+ * @retval None\r
+ */\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DIRECTION(SPI_Direction));\r
+ if (SPI_Direction == SPI_Direction_Tx)\r
+ {\r
+ /* Set the Tx only mode */\r
+ SPIx->CR1 |= SPI_Direction_Tx;\r
+ }\r
+ else\r
+ {\r
+ /* Set the Rx only mode */\r
+ SPIx->CR1 &= SPI_Direction_Rx;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures internally by software the NSS pin for the selected SPI.\r
+ * @note - This function can be called only after the SPI_Init() function has \r
+ * been called. \r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally\r
+ * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally\r
+ * @retval None\r
+ */\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));\r
+\r
+ if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)\r
+ {\r
+ /* Set NSS pin internally by software */\r
+ SPIx->CR1 |= SPI_NSSInternalSoft_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset NSS pin internally by software */\r
+ SPIx->CR1 &= SPI_NSSInternalSoft_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SS output for the selected SPI.\r
+ * @note - This function can be called only after the SPI_Init() function has \r
+ * been called and the NSS hardware management mode is selected. \r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx SS output. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI SS output */\r
+ SPIx->CR2 |= SPI_CR2_SSOE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI SS output */\r
+ SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the NSS pulse management mode.\r
+ * @note - This function can be called only after the SPI_Init() function has \r
+ * been called. \r
+ * - When TI mode is selected, the control bits NSSP is not taken into \r
+ * consideration and are configured by hardware respectively to the \r
+ * TI mode requirements. \r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param NewState: new state of the NSS pulse management mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the NSS pulse management mode */\r
+ SPIx->CR2 |= SPI_CR2_NSSP;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the NSS pulse management mode */\r
+ SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP); \r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group2 Data transfers functions\r
+ * @brief Data transfers functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Data transfers functions #####\r
+ ===============================================================================\r
+ [..] This section provides a set of functions allowing to manage the SPI or I2S\r
+ data transfers.\r
+\r
+ [..] In reception, data are received and then stored into an internal Rx buffer while \r
+ In transmission, data are first stored into an internal Tx buffer before being \r
+ transmitted.\r
+\r
+ [..] The read access of the SPI_DR register can be done using \r
+ SPI_ReceiveData8() (when data size is equal or inferior than 8bits) and.\r
+ SPI_I2S_ReceiveData16() (when data size is superior than 8bits)function\r
+ and returns the Rx buffered value. Whereas a write access to the SPI_DR \r
+ can be done using SPI_SendData8() (when data size is equal or inferior than 8bits)\r
+ and SPI_I2S_SendData16() (when data size is superior than 8bits) function \r
+ and stores the written data into Tx buffer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmits a Data through the SPIx/I2Sx peripheral.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral.\r
+ * @param Data: Data to be transmitted.\r
+ * @retval None\r
+ */\r
+void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data)\r
+{\r
+ uint32_t spixbase = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+\r
+ spixbase = (uint32_t)SPIx; \r
+ spixbase += 0x0C;\r
+ \r
+ *(__IO uint8_t *) spixbase = Data;\r
+}\r
+\r
+/**\r
+ * @brief Transmits a Data through the SPIx/I2Sx peripheral.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select \r
+ * the SPI peripheral. \r
+ * @param Data: Data to be transmitted.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ SPIx->DR = (uint16_t)Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. \r
+ * @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral. \r
+ * @retval The value of the received data.\r
+ */\r
+uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx)\r
+{\r
+ uint32_t spixbase = 0x00;\r
+ \r
+ spixbase = (uint32_t)SPIx; \r
+ spixbase += 0x0C;\r
+ \r
+ return *(__IO uint8_t *) spixbase;\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the SPIx peripheral. \r
+ * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select \r
+ * the SPI peripheral. \r
+ * @retval The value of the received data.\r
+ */\r
+uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx)\r
+{\r
+ return SPIx->DR;\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group3 Hardware CRC Calculation functions\r
+ * @brief Hardware CRC Calculation functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Hardware CRC Calculation functions #####\r
+ ===============================================================================\r
+ [..] This section provides a set of functions allowing to manage the SPI CRC hardware \r
+ calculation.SPI communication using CRC is possible through the following procedure:\r
+\r
+ (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,\r
+ Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()\r
+ function.\r
+ (#) Enable the CRC calculation using the SPI_CalculateCRC() function.\r
+ (#) Enable the SPI using the SPI_Cmd() function\r
+ (#) Before writing the last data to the TX buffer, set the CRCNext bit using the \r
+ SPI_TransmitCRC() function to indicate that after transmission of the last \r
+ data, the CRC should be transmitted.\r
+ (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT\r
+ bit is reset. The CRC is also received and compared against the SPI_RXCRCR \r
+ value. \r
+ If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt\r
+ can be generated when the SPI_I2S_IT_ERR interrupt is enabled.\r
+\r
+ -@-\r
+ (+@) It is advised to don't read the calculate CRC values during the communication.\r
+ (+@) When the SPI is in slave mode, be careful to enable CRC calculation only\r
+ when the clock is stable, that is, when the clock is in the steady state. \r
+ If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive \r
+ to the SCK slave input clock as soon as CRCEN is set, and this, whatever \r
+ the value of the SPE bit.\r
+ (+@) With high bitrate frequencies, be careful when transmitting the CRC.\r
+ As the number of used CPU cycles has to be as low as possible in the CRC \r
+ transfer phase, it is forbidden to call software functions in the CRC \r
+ transmission sequence to avoid errors in the last data and CRC reception. \r
+ In fact, CRCNEXT bit has to be written before the end of the transmission/reception \r
+ of the last data.\r
+ (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the\r
+ degradation of the SPI speed performance due to CPU accesses impacting the \r
+ SPI bandwidth.\r
+ (+@) When the STM32F0xx are configured as slaves and the NSS hardware mode is \r
+ used, the NSS pin needs to be kept low between the data phase and the CRC \r
+ phase.\r
+ (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC\r
+ calculation takes place even if a high level is applied on the NSS pin. \r
+ This may happen for example in case of a multislave environment where the \r
+ communication master addresses slaves alternately.\r
+ (+@) Between a slave deselection (high level on NSS) and a new slave selection\r
+ (low level on NSS), the CRC value should be cleared on both master and slave\r
+ sides in order to resynchronize the master and slave for their respective \r
+ CRC calculation.\r
+\r
+ -@- To clear the CRC, follow the procedure below:\r
+ (#@) Disable SPI using the SPI_Cmd() function\r
+ (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.\r
+ (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.\r
+ (#@) Enable SPI using the SPI_Cmd() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the CRC calculation length for the selected SPI.\r
+ * @note - This function can be called only after the SPI_Init() function has \r
+ * been called. \r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_CRCLength: specifies the SPI CRC calculation length.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits\r
+ * @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits\r
+ * @retval None\r
+ */\r
+void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength));\r
+\r
+ /* Clear CRCL bit */\r
+ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL);\r
+\r
+ /* Set new CRCL bit value */\r
+ SPIx->CR1 |= SPI_CRCLength;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the CRC value calculation of the transferred bytes.\r
+ * @note - This function can be called only after the SPI_Init() function has \r
+ * been called. \r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx CRC value calculation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI CRC calculation */\r
+ SPIx->CR1 |= SPI_CR1_CRCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI CRC calculation */\r
+ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit the SPIx CRC value.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+\r
+ /* Enable the selected SPI CRC transmission */\r
+ SPIx->CR1 |= SPI_CR1_CRCNEXT;\r
+}\r
+\r
+/**\r
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_CRC: specifies the CRC register to be read.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_CRC_Tx: Selects Tx CRC register\r
+ * @arg SPI_CRC_Rx: Selects Rx CRC register\r
+ * @retval The selected CRC register value..\r
+ */\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)\r
+{\r
+ uint16_t crcreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_CRC(SPI_CRC));\r
+\r
+ if (SPI_CRC != SPI_CRC_Rx)\r
+ {\r
+ /* Get the Tx CRC register */\r
+ crcreg = SPIx->TXCRCR;\r
+ }\r
+ else\r
+ {\r
+ /* Get the Rx CRC register */\r
+ crcreg = SPIx->RXCRCR;\r
+ }\r
+ /* Return the selected CRC register */\r
+ return crcreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the CRC Polynomial register value for the specified SPI.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @retval The CRC Polynomial register value.\r
+ */\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+\r
+ /* Return the CRC polynomial register */\r
+ return SPIx->CRCPR;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group4 DMA transfers management functions\r
+ * @brief DMA transfers management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### DMA transfers management functions #####\r
+ ===============================================================================\r
+ [..] This section provides two functions that can be used only in DMA mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the SPIx/I2Sx DMA interface.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select \r
+ * the SPI peripheral.\r
+ * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request\r
+ * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request\r
+ * @param NewState: new state of the selected SPI DMA transfer request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI DMA requests */\r
+ SPIx->CR2 |= SPI_I2S_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI DMA requests */\r
+ SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the number of data to transfer type(Even/Odd) for the DMA\r
+ * last transfers and for the selected SPI.\r
+ * @note - This function have a meaning only if DMA mode is selected and if \r
+ * the packing mode is used (data length <= 8 and DMA transfer size halfword) \r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even\r
+ * and number of data for reception Even.\r
+ * @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd\r
+ * and number of data for reception Even.\r
+ * @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even\r
+ * and number of data for reception Odd.\r
+ * @arg SPI_LastDMATransfer_TxOddRxOdd: Number of data for transmission Odd\r
+ * and number of data for reception Odd.\r
+ * @retval None\r
+ */\r
+void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer));\r
+\r
+ /* Clear LDMA_TX and LDMA_RX bits */\r
+ SPIx->CR2 &= CR2_LDMA_MASK;\r
+\r
+ /* Set new LDMA_TX and LDMA_RX bits value */\r
+ SPIx->CR2 |= SPI_LastDMATransfer; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Group5 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ===============================================================================\r
+ [..] This section provides a set of functions allowing to configure the SPI/I2S Interrupts \r
+ sources and check or clear the flags or pending bits status.\r
+ The user should identify which mode will be used in his application to manage \r
+ the communication: Polling mode, Interrupt mode or DMA mode. \r
+\r
+ *** Polling Mode ***\r
+ ====================\r
+ [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:\r
+ (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register\r
+ (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register\r
+ (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.\r
+ (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur \r
+ (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur\r
+ (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur\r
+ (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.\r
+ (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.\r
+ (#) I2S_FLAG_CHSIDE: to indicate Channel Side.\r
+\r
+ [..]\r
+ (@)Do not use the BSY flag to handle each data transmission or reception. It is better \r
+ to use the TXE and RXNE flags instead.\r
+\r
+ [..] In this Mode it is advised to use the following functions:\r
+ (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+ (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+\r
+ *** Interrupt Mode ***\r
+ ======================\r
+ [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources\r
+ and 5 pending bits: \r
+ [..] Pending Bits:\r
+ (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register\r
+ (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register\r
+ (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur\r
+ (#) I2S_IT_UDR : to indicate an Underrun Error occurs.\r
+ (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.\r
+\r
+ [..] Interrupt Source:\r
+ (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty \r
+ interrupt. \r
+ (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not \r
+ empty interrupt.\r
+ (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.\r
+\r
+ [..] In this Mode it is advised to use the following functions:\r
+ (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r
+ (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+\r
+ *** FIFO Status ***\r
+ ===================\r
+ It is possible to monitor the FIFO status when a transfer is ongoing using the\r
+ following function:\r
+ - uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction); \r
+\r
+ *** DMA Mode ***\r
+ ================\r
+ [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel \r
+ requests:\r
+ (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.\r
+ (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.\r
+\r
+ [..] In this Mode it is advised to use the following function:\r
+ (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI/I2S interrupts.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select \r
+ * the SPI peripheral. \r
+ * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask\r
+ * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask\r
+ * @arg SPI_I2S_IT_ERR: Error interrupt mask\r
+ * @param NewState: new state of the specified SPI interrupt.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)\r
+{\r
+ uint16_t itpos = 0, itmask = 0 ;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI IT index */\r
+ itpos = SPI_I2S_IT >> 4;\r
+\r
+ /* Set the IT mask */\r
+ itmask = (uint16_t)1 << (uint16_t)itpos;\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI interrupt */\r
+ SPIx->CR2 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI interrupt */\r
+ SPIx->CR2 &= (uint16_t)~itmask;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the current SPIx Transmission FIFO filled level.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @retval The Transmission FIFO filling state.\r
+ * - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty\r
+ * - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full.\r
+ * - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full.\r
+ * - SPI_TransmissionFIFOStatus_Full: when FIFO is full.\r
+ */\r
+uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx)\r
+{\r
+ /* Get the SPIx Transmission FIFO level bits */\r
+ return (uint16_t)((SPIx->SR & SPI_SR_FTLVL));\r
+}\r
+\r
+/**\r
+ * @brief Returns the current SPIx Reception FIFO filled level.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @retval The Reception FIFO filling state.\r
+ * - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty\r
+ * - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full.\r
+ * - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full.\r
+ * - SPI_ReceptionFIFOStatus_Full: when FIFO is full.\r
+ */\r
+uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx)\r
+{\r
+ /* Get the SPIx Reception FIFO level bits */\r
+ return (uint16_t)((SPIx->SR & SPI_SR_FRLVL));\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPI flag is set or not.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select \r
+ * the SPI peripheral. \r
+ * @param SPI_I2S_FLAG: specifies the SPI flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.\r
+ * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.\r
+ * @arg SPI_I2S_FLAG_BSY: Busy flag.\r
+ * @arg SPI_I2S_FLAG_OVR: Overrun flag.\r
+ * @arg SPI_I2S_FLAG_MODF: Mode Fault flag.\r
+ * @arg SPI_I2S_FLAG_CRCERR: CRC Error flag.\r
+ * @arg SPI_I2S_FLAG_FRE: TI frame format error flag.\r
+ * @arg I2S_FLAG_UDR: Underrun Error flag.\r
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag. \r
+ * @retval The new state of SPI_I2S_FLAG (SET or RESET).\r
+ */\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));\r
+\r
+ /* Check the status of the specified SPI flag */\r
+ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)\r
+ {\r
+ /* SPI_I2S_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.\r
+ * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+ * @param SPI_I2S_FLAG: specifies the SPI flag to clear. \r
+ * This function clears only CRCERR flag.\r
+ * @note\r
+ * - OVR (OverRun error) flag is cleared by software sequence: a read \r
+ * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read \r
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).\r
+ * - MODF (Mode Fault) flag is cleared by software sequence: a read/write \r
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a \r
+ * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG));\r
+\r
+ /* Clear the selected SPI CRC Error (CRCERR) flag */\r
+ SPIx->SR = (uint16_t)~SPI_I2S_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.\r
+ * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select \r
+ * the SPI peripheral.\r
+ * @param SPI_I2S_IT: specifies the SPI interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.\r
+ * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.\r
+ * @arg SPI_IT_MODF: Mode Fault interrupt.\r
+ * @arg SPI_I2S_IT_OVR: Overrun interrupt.\r
+ * @arg I2S_IT_UDR: Underrun interrupt. \r
+ * @arg SPI_I2S_IT_FRE: Format Error interrupt. \r
+ * @retval The new state of SPI_I2S_IT (SET or RESET).\r
+ */\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI_I2S_IT index */\r
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
+\r
+ /* Get the SPI_I2S_IT IT mask */\r
+ itmask = SPI_I2S_IT >> 4;\r
+\r
+ /* Set the IT mask */\r
+ itmask = 0x01 << itmask;\r
+\r
+ /* Get the SPI_I2S_IT enable bit status */\r
+ enablestatus = (SPIx->CR2 & itmask) ;\r
+\r
+ /* Check the status of the specified SPI interrupt */\r
+ if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)\r
+ {\r
+ /* SPI_I2S_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_syscfg.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the SYSCFG peripheral:\r
+ * + Remapping the memory mapped at 0x00000000 \r
+ * + Remapping the DMA channels\r
+ * + Enabling I2C fast mode plus driving capability for I2C pins \r
+ * + Configuring the EXTI lines connection to the GPIO port\r
+ * + Configuring the CFGR2 features (Connecting some internal signal\r
+ * to the break input of TIM1)\r
+ * \r
+ * @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..] \r
+ The SYSCFG registers can be accessed only when the SYSCFG \r
+ interface APB clock is enabled.\r
+ To enable SYSCFG APB clock use:\r
+ RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE).\r
+ * @endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_syscfg.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SYSCFG \r
+ * @brief SYSCFG driver modules\r
+ * @{\r
+ */ \r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup SYSCFG_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions\r
+ * @brief SYSCFG Initialization and Configuration functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### SYSCFG Initialization and Configuration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the SYSCFG registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ * @note MEM_MODE bits are not affected by APB reset.\r
+ * MEM_MODE bits took the value from the user option bytes.\r
+ * @note CFGR2 register is not affected by APB reset.\r
+ * CLABBB configuration bits are locked when set.\r
+ * To unlock the configuration, perform a system reset.\r
+ */\r
+void SYSCFG_DeInit(void)\r
+{\r
+ /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */\r
+ SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;\r
+ /* Set EXTICRx registers to reset value */\r
+ SYSCFG->EXTICR[0] = 0;\r
+ SYSCFG->EXTICR[1] = 0;\r
+ SYSCFG->EXTICR[2] = 0;\r
+ SYSCFG->EXTICR[3] = 0;\r
+ /* Set CFGR2 register to reset value: clear SRAM parity error flag */\r
+ SYSCFG->CFGR2 |= (uint32_t) SYSCFG_CFGR2_SRAM_PE;\r
+}\r
+\r
+/**\r
+ * @brief Configures the memory mapping at address 0x00000000.\r
+ * @param SYSCFG_MemoryRemap: selects the memory remapping.\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 \r
+ * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000\r
+ * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000\r
+ * @retval None\r
+ */\r
+void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)\r
+{\r
+ uint32_t tmpctrl = 0;\r
+\r
+ /* Check the parameter */\r
+ assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));\r
+\r
+ /* Get CFGR1 register value */\r
+ tmpctrl = SYSCFG->CFGR1;\r
+\r
+ /* Clear MEM_MODE bits */\r
+ tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);\r
+\r
+ /* Set the new MEM_MODE bits value */\r
+ tmpctrl |= (uint32_t) SYSCFG_MemoryRemap;\r
+\r
+ /* Set CFGR1 register with the new memory remap configuration */\r
+ SYSCFG->CFGR1 = tmpctrl;\r
+}\r
+\r
+/**\r
+ * @brief Configure the DMA channels remapping.\r
+ * @param SYSCFG_DMARemap: selects the DMA channels remap.\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2\r
+ * @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4\r
+ * @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5\r
+ * @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4\r
+ * @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2\r
+ * @param NewState: new state of the DMA channel remapping. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note When enabled, DMA channel of the selected peripheral is remapped\r
+ * @note When disabled, Default DMA channel is mapped to the selected peripheral\r
+ * @note \r
+ * By default TIM17 DMA requests is mapped to channel 1\r
+ * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable)\r
+ * to remap TIM17 DMA requests to channel 2\r
+ * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable)\r
+ * to map TIM17 DMA requests to channel 1 (default mapping)\r
+ * @retval None\r
+ */\r
+void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Remap the DMA channel */\r
+ SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;\r
+ }\r
+ else\r
+ {\r
+ /* use the default DMA channel mapping */\r
+ SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure the I2C fast mode plus driving capability.\r
+ * @param SYSCFG_I2CFastModePlus: selects the pin.\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6\r
+ * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7\r
+ * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8\r
+ * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9\r
+ * @param NewState: new state of the DMA channel remapping. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note ENABLE: Enable fast mode plus driving capability for selected pin\r
+ * @note DISABLE: Disable fast mode plus driving capability for selected pin\r
+ * @retval None\r
+ */\r
+void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable fast mode plus driving capability for selected pin */\r
+ SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;\r
+ }\r
+ else\r
+ {\r
+ /* Disable fast mode plus driving capability for selected pin */\r
+ SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the GPIO pin used as EXTI Line.\r
+ * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source \r
+ * for EXTI lines where x can be (A, B, C, D or F).\r
+ * @param EXTI_PinSourcex: specifies the EXTI line to be configured.\r
+ * This parameter can be EXTI_PinSourcex where x can be (0..15)\r
+ * @retval None\r
+ */\r
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)\r
+{\r
+ uint32_t tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));\r
+ assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));\r
+ \r
+ tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));\r
+ SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;\r
+ SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));\r
+}\r
+\r
+/**\r
+ * @brief Connect the selected parameter to the break input of TIM1.\r
+ * @note The selected configuration is locked and can be unlocked by system reset\r
+ * @param SYSCFG_Break: selects the configuration to be connected to break\r
+ * input of TIM1\r
+ * This parameter can be any combination of the following values:\r
+ * @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1.\r
+ * @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 .\r
+ * @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1.\r
+ * @retval None\r
+ */\r
+void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));\r
+\r
+ SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SYSCFG flag is set or not.\r
+ * @param SYSCFG_Flag: specifies the SYSCFG flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SYSCFG_FLAG_PE: SRAM parity error flag.\r
+ * @retval The new state of SYSCFG_Flag (SET or RESET).\r
+ */\r
+FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameter */\r
+ assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));\r
+\r
+ /* Check the status of the specified SPI flag */\r
+ if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)\r
+ {\r
+ /* SYSCFG_Flag is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SYSCFG_Flag is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SYSCFG_Flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clear the selected SYSCFG flag.\r
+ * @param SYSCFG_Flag: selects the flag to be cleared.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg SYSCFG_FLAG_PE: SRAM parity error flag.\r
+ * @retval None\r
+ */\r
+void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));\r
+\r
+ SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_tim.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the TIM peripheral:\r
+ * + TimeBase management\r
+ * + Output Compare management\r
+ * + Input Capture management\r
+ * + Interrupts, DMA and flags management\r
+ * + Clocks management\r
+ * + Synchronization management\r
+ * + Specific interface management\r
+ * + Specific remapping management \r
+ * \r
+ * @verbatim\r
+ \r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..] This driver provides functions to configure and program the TIM \r
+ of all STM32F0xx devices These functions are split in 8 groups: \r
+ (#) TIM TimeBase management: this group includes all needed functions \r
+ to configure the TM Timebase unit:\r
+ (++) Set/Get Prescaler.\r
+ (++) Set/Get Autoreload.\r
+ (++) Counter modes configuration.\r
+ (++) Set Clock division.\r
+ (++) Select the One Pulse mode.\r
+ (++) Update Request Configuration.\r
+ (++) Update Disable Configuration.\r
+ (++) Auto-Preload Configuration.\r
+ (++) Enable/Disable the counter.\r
+ \r
+ (#) TIM Output Compare management: this group includes all needed \r
+ functions to configure the Capture/Compare unit used in Output \r
+ compare mode: \r
+ (++) Configure each channel, independently, in Output Compare mode.\r
+ (++) Select the output compare modes.\r
+ (++) Select the Polarities of each channel.\r
+ (++) Set/Get the Capture/Compare register values.\r
+ (++) Select the Output Compare Fast mode. \r
+ (++) Select the Output Compare Forced mode. \r
+ (++) Output Compare-Preload Configuration. \r
+ (++) Clear Output Compare Reference.\r
+ (++) Select the OCREF Clear signal.\r
+ (++) Enable/Disable the Capture/Compare Channels. \r
+ \r
+ (#) TIM Input Capture management: this group includes all needed \r
+ functions to configure the Capture/Compare unit used in \r
+ Input Capture mode:\r
+ (++) Configure each channel in input capture mode.\r
+ (++) Configure Channel1/2 in PWM Input mode.\r
+ (++) Set the Input Capture Prescaler.\r
+ (++) Get the Capture/Compare values. \r
+ \r
+ (#) Advanced-control timers (TIM1) specific features\r
+ (++) Configures the Break input, dead time, Lock level, the OSSI,\r
+ the OSSR State and the AOE(automatic output enable)\r
+ (++) Enable/Disable the TIM peripheral Main Outputs\r
+ (++) Select the Commutation event\r
+ (++) Set/Reset the Capture Compare Preload Control bit \r
+ \r
+ (#) TIM interrupts, DMA and flags management.\r
+ (++) Enable/Disable interrupt sources.\r
+ (++) Get flags status.\r
+ (++) Clear flags/ Pending bits.\r
+ (++) Enable/Disable DMA requests. \r
+ (++) Configure DMA burst mode.\r
+ (++) Select CaptureCompare DMA request. \r
+ \r
+ (#) TIM clocks management: this group includes all needed functions \r
+ to configure the clock controller unit:\r
+ (++) Select internal/External clock.\r
+ (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx.\r
+ \r
+ (#) TIM synchronization management: this group includes all needed. \r
+ functions to configure the Synchronization unit:\r
+ (++) Select Input Trigger. \r
+ (++) Select Output Trigger. \r
+ (++) Select Master Slave Mode. \r
+ (++) ETR Configuration when used as external trigger. \r
+ \r
+ (#) TIM specific interface management, this group includes all \r
+ needed functions to use the specific TIM interface:\r
+ (++) Encoder Interface Configuration.\r
+ (++) Select Hall Sensor. \r
+ \r
+ (#) TIM specific remapping management includes the Remapping \r
+ configuration of specific timers\r
+ \r
+@endverbatim\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_tim.h"\r
+#include "stm32f0xx_rcc.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM \r
+ * @brief TIM driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* ---------------------- TIM registers bit mask ------------------------ */\r
+#define SMCR_ETR_MASK ((uint16_t)0x00FF) \r
+#define CCMR_OFFSET ((uint16_t)0x0018)\r
+#define CCER_CCE_SET ((uint16_t)0x0001)\r
+#define CCER_CCNE_SET ((uint16_t)0x0004) \r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+\r
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup TIM_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_Group1 TimeBase management functions\r
+ * @brief TimeBase management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### TimeBase management functions #####\r
+ ===============================================================================\r
+ \r
+ *** TIM Driver: how to use it in Timing(Time base) Mode ***\r
+ ===============================================================================\r
+ [..] To use the Timer in Timing(Time base) mode, the following steps are \r
+ mandatory:\r
+ (#) Enable TIM clock using \r
+ RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.\r
+ (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.\r
+ (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure \r
+ the Time Base unit with the corresponding configuration.\r
+ (#) Enable the NVIC if you need to generate the update interrupt. \r
+ (#) Enable the corresponding interrupt using the function \r
+ TIM_ITConfig(TIMx, TIM_IT_Update). \r
+ (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
+ [..]\r
+ (@) All other functions can be used seperatly to modify, if needed,\r
+ a specific feature of the Timer. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM peripheral.\r
+ * @retval None\r
+ * \r
+ */\r
+void TIM_DeInit(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+\r
+ if (TIMx == TIM1)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); \r
+ } \r
+ else if (TIMx == TIM2)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);\r
+ }\r
+ else if (TIMx == TIM3)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);\r
+ }\r
+ else if (TIMx == TIM6)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);\r
+ } \r
+ else if (TIMx == TIM14) \r
+ { \r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); \r
+ } \r
+ else if (TIMx == TIM15)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);\r
+ } \r
+ else if (TIMx == TIM16)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);\r
+ } \r
+ else\r
+ {\r
+ if (TIMx == TIM17)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);\r
+ } \r
+ }\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Time Base Unit peripheral according to \r
+ * the specified parameters in the TIM_TimeBaseInitStruct.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM \r
+ * peripheral.\r
+ * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef\r
+ * structure that contains the configuration information for\r
+ * the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+ uint16_t tmpcr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));\r
+ assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));\r
+\r
+ tmpcr1 = TIMx->CR1; \r
+\r
+ if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3))\r
+ {\r
+ /* Select the Counter Mode */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;\r
+ }\r
+ \r
+ if(TIMx != TIM6)\r
+ {\r
+ /* Set the clock division */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));\r
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;\r
+ }\r
+\r
+ TIMx->CR1 = tmpcr1;\r
+\r
+ /* Set the Autoreload value */\r
+ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;\r
+ \r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;\r
+ \r
+ if ((TIMx == TIM1) || (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) \r
+ {\r
+ /* Set the Repetition Counter value */\r
+ TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;\r
+ }\r
+\r
+ /* Generate an update event to reload the Prescaler and the Repetition counter\r
+ values immediately */\r
+ TIMx->EGR = TIM_PSCReloadMode_Immediate; \r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.\r
+ * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef\r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;\r
+ TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;\r
+ TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;\r
+ TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;\r
+ TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Prescaler.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM peripheral.\r
+ * @param Prescaler: specifies the Prescaler Register value\r
+ * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.\r
+ * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.\r
+ * @retval None\r
+ */\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));\r
+ \r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = Prescaler;\r
+ /* Set or reset the UG Bit */\r
+ TIMx->EGR = TIM_PSCReloadMode;\r
+}\r
+\r
+/**\r
+ * @brief Specifies the TIMx Counter Mode to be used.\r
+ * @param TIMx: where x can be 1, 2, or 3 to select the TIM peripheral.\r
+ * @param TIM_CounterMode: specifies the Counter Mode to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CounterMode_Up: TIM Up Counting Mode\r
+ * @arg TIM_CounterMode_Down: TIM Down Counting Mode\r
+ * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1\r
+ * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2\r
+ * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3\r
+ * @retval None\r
+ */\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)\r
+{\r
+ uint16_t tmpcr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));\r
+ \r
+ tmpcr1 = TIMx->CR1;\r
+ /* Reset the CMS and DIR Bits */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
+ /* Set the Counter Mode */\r
+ tmpcr1 |= TIM_CounterMode;\r
+ /* Write to TIMx CR1 register */\r
+ TIMx->CR1 = tmpcr1;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Counter Register value\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM \r
+ * peripheral.\r
+ * @param Counter: specifies the Counter register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Set the Counter Register value */\r
+ TIMx->CNT = Counter;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Autoreload Register value\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM peripheral.\r
+ * @param Autoreload: specifies the Autoreload register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Set the Autoreload Register value */\r
+ TIMx->ARR = Autoreload;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Counter value.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM \r
+ * peripheral.\r
+ * @retval Counter Register value.\r
+ */\r
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Get the Counter Register value */\r
+ return TIMx->CNT;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Prescaler value.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM \r
+ * peripheral.\r
+ * @retval Prescaler Register value.\r
+ */\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ \r
+ /* Get the Prescaler Register value */\r
+ return TIMx->PSC;\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the TIMx Update event.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM \r
+ * peripheral.\r
+ * @param NewState: new state of the TIMx UDIS bit\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the Update Disable Bit */\r
+ TIMx->CR1 |= TIM_CR1_UDIS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the Update Disable Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Update Request Interrupt source.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM \r
+ * peripheral.\r
+ * @param TIM_UpdateSource: specifies the Update source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow\r
+ or the setting of UG bit, or an update generation\r
+ through the slave mode controller.\r
+ * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.\r
+ * @retval None\r
+ */\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));\r
+ \r
+ if (TIM_UpdateSource != TIM_UpdateSource_Global)\r
+ {\r
+ /* Set the URS Bit */\r
+ TIMx->CR1 |= TIM_CR1_URS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the URS Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables TIMx peripheral Preload register on ARR.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM \r
+ * peripheral.\r
+ * @param NewState: new state of the TIMx peripheral Preload register\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the ARR Preload Bit */\r
+ TIMx->CR1 |= TIM_CR1_ARPE;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the ARR Preload Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx's One Pulse Mode.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM \r
+ * peripheral.\r
+ * @param TIM_OPMode: specifies the OPM Mode to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OPMode_Single\r
+ * @arg TIM_OPMode_Repetitive\r
+ * @retval None\r
+ */\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OPM_MODE(TIM_OPMode));\r
+ \r
+ /* Reset the OPM Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);\r
+ /* Configure the OPM Mode */\r
+ TIMx->CR1 |= TIM_OPMode;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Clock Division value.\r
+ * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.\r
+ * @param TIM_CKD: specifies the clock division value.\r
+ * This parameter can be one of the following value:\r
+ * @arg TIM_CKD_DIV1: TDTS = Tck_tim\r
+ * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim\r
+ * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim\r
+ * @retval None\r
+ */\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CKD_DIV(TIM_CKD));\r
+ \r
+ /* Reset the CKD Bits */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);\r
+ /* Set the CKD value */\r
+ TIMx->CR1 |= TIM_CKD;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM peripheral.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17to select the TIMx\r
+ * peripheral.\r
+ * @param NewState: new state of the TIMx peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the TIM Counter */\r
+ TIMx->CR1 |= TIM_CR1_CEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the TIM Counter */\r
+ TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group2 Advanced-control timers (TIM1) specific features\r
+ * @brief Advanced-control timers (TIM1) specific features\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Advanced-control timers (TIM1) specific features #####\r
+ =============================================================================== \r
+ \r
+ =================================================================== \r
+ *** TIM Driver: how to use the Break feature ***\r
+ =================================================================== \r
+ [..] After configuring the Timer channel(s) in the appropriate Output Compare mode: \r
+ \r
+ (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer\r
+ Break Polarity, dead time, Lock level, the OSSI/OSSR State and the \r
+ AOE(automatic output enable).\r
+ \r
+ (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer\r
+ \r
+ (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) \r
+ \r
+ (#) Once the break even occurs, the Timer's output signals are put in reset\r
+ state or in a known state (according to the configuration made in\r
+ TIM_BDTRConfig() function).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Configures the: Break feature, dead time, Lock level, the OSSI,\r
+ * the OSSR State and the AOE(automatic output enable).\r
+ * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM \r
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that\r
+ * contains the BDTR Register configuration information for the TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));\r
+ assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));\r
+ assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));\r
+ assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));\r
+ assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));\r
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));\r
+ /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,\r
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */\r
+ TIMx->BDTR |= (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |\r
+ TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |\r
+ TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |\r
+ TIM_BDTRInitStruct->TIM_AutomaticOutput;\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_BDTRInitStruct member with its default value.\r
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which\r
+ * will be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;\r
+ TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;\r
+ TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;\r
+ TIM_BDTRInitStruct->TIM_DeadTime = 0x00;\r
+ TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;\r
+ TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;\r
+ TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM peripheral Main Outputs.\r
+ * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral.\r
+ * @param NewState: new state of the TIM peripheral Main Outputs.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the TIM Main Output */\r
+ TIMx->BDTR |= TIM_BDTR_MOE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the TIM Main Output */\r
+ TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));\r
+ } \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group3 Output Compare management functions\r
+ * @brief Output Compare management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Output Compare management functions #####\r
+ ===============================================================================\r
+ *** TIM Driver: how to use it in Output Compare Mode ***\r
+ ===============================================================================\r
+ [..] To use the Timer in Output Compare mode, the following steps are mandatory:\r
+ (#) Enable TIM clock using \r
+ RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.\r
+ (#) Configure the TIM pins by configuring the corresponding GPIO pins\r
+ (#) Configure the Time base unit as described in the first part of this \r
+ driver, if needed, else the Timer will run with the default \r
+ configuration:\r
+ (++) Autoreload value = 0xFFFF.\r
+ (++) Prescaler value = 0x0000.\r
+ (++) Counter mode = Up counting.\r
+ (++) Clock Division = TIM_CKD_DIV1.\r
+ (#) Fill the TIM_OCInitStruct with the desired parameters including:\r
+ (++) The TIM Output Compare mode: TIM_OCMode.\r
+ (++) TIM Output State: TIM_OutputState.\r
+ (++) TIM Pulse value: TIM_Pulse.\r
+ (++) TIM Output Compare Polarity : TIM_OCPolarity.\r
+ (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired \r
+ channel with the corresponding configuration.\r
+ (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
+ [..]\r
+ (@) All other functions can be used separately to modify, if needed,\r
+ a specific feature of the Timer.\r
+ (@) In case of PWM mode, this function is mandatory:\r
+ TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE).\r
+ (@) If the corresponding interrupt or DMA request are needed, the user should:\r
+ (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).\r
+ (#@) Enable the corresponding interrupt (or DMA request) using the function\r
+ TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel1 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));\r
+\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OutputState;\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17))\r
+ {\r
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
+ \r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;\r
+ \r
+ /* Reset the Output N State */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); \r
+ /* Set the Output N State */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OutputNState;\r
+ \r
+ /* Reset the Ouput Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));\r
+ \r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; \r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel2 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));\r
+ \r
+ /* Get the TIMx CCER register value */ \r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);\r
+ \r
+ if(TIMx == TIM1)\r
+ {\r
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
+ \r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);\r
+ \r
+ /* Reset the Output N State */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); \r
+ /* Set the Output N State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);\r
+ \r
+ /* Reset the Ouput Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));\r
+ \r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel3 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);\r
+ \r
+ if(TIMx == TIM1)\r
+ {\r
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
+ \r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);\r
+ /* Reset the Output N State */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));\r
+ \r
+ /* Set the Output N State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);\r
+ /* Reset the Ouput Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel4 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 2: Reset the CC4E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);\r
+ \r
+ if(TIMx == TIM1)\r
+ {\r
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
+ /* Reset the Ouput Compare IDLE State */\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR2 */ \r
+ TIMx->CCMR2 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_OCInitStruct member with its default value.\r
+ * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;\r
+ TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;\r
+ TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;\r
+ TIM_OCInitStruct->TIM_Pulse = 0x0000000;\r
+ TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;\r
+ TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;\r
+ TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;\r
+ TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM Output Compare Mode.\r
+ * @note This function disables the selected channel before changing the Output\r
+ * Compare Mode.\r
+ * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.\r
+ * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_Channel: specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @arg TIM_Channel_4: TIM Channel 4\r
+ * @param TIM_OCMode: specifies the TIM Output Compare Mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCMode_Timing\r
+ * @arg TIM_OCMode_Active\r
+ * @arg TIM_OCMode_Toggle\r
+ * @arg TIM_OCMode_PWM1\r
+ * @arg TIM_OCMode_PWM2\r
+ * @arg TIM_ForcedAction_Active\r
+ * @arg TIM_ForcedAction_InActive\r
+ * @retval None\r
+ */\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint16_t tmp1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OCM(TIM_OCMode));\r
+ \r
+ tmp = (uint32_t) TIMx;\r
+ tmp += CCMR_OFFSET;\r
+\r
+ tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;\r
+\r
+ /* Disable the Channel: Reset the CCxE Bit */\r
+ TIMx->CCER &= (uint16_t) ~tmp1;\r
+\r
+ if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))\r
+ {\r
+ tmp += (TIM_Channel>>1);\r
+\r
+ /* Reset the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);\r
+ \r
+ /* Configure the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp |= TIM_OCMode;\r
+ }\r
+ else\r
+ {\r
+ tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;\r
+\r
+ /* Reset the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);\r
+ \r
+ /* Configure the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare1 Register value\r
+ * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param Compare1: specifies the Capture Compare1 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare1 Register value */\r
+ TIMx->CCR1 = Compare1;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare2 Register value\r
+ * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.\r
+ * @param Compare2: specifies the Capture Compare2 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare2 Register value */\r
+ TIMx->CCR2 = Compare2;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare3 Register value\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param Compare3: specifies the Capture Compare3 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare3 Register value */\r
+ TIMx->CCR3 = Compare3;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare4 Register value\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param Compare4: specifies the Capture Compare4 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ \r
+ /* Set the Capture Compare4 Register value */\r
+ TIMx->CCR4 = Compare4;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC1REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1M Bits */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= TIM_ForcedAction;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+ \r
+/**\r
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM \r
+ * peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC2REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2M Bits */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC3REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC1M Bits */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= TIM_ForcedAction;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC4REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC2M Bits */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.\r
+ * @param TIMx: where x can be 1, 2, 3 or 15 \r
+ * to select the TIMx peripheral\r
+ * @param NewState: new state of the Capture Compare Preload Control bit\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the CCPC Bit */\r
+ TIMx->CR2 |= TIM_CR2_CCPC;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the CCPC Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR1.\r
+ * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1PE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr1 |= TIM_OCPreload;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR2.\r
+ * @param TIMx: where x can be 1, 2, 3 and 15 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2PE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR3.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3PE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr2 |= TIM_OCPreload;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR4.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4PE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 1 Fast feature.\r
+ * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1FE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr1 |= TIM_OCFast;\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 2 Fast feature.\r
+ * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2FE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 3 Fast feature.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3FE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr2 |= TIM_OCFast;\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 4 Fast feature.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4FE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF1 signal on an external event\r
+ * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1CE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr1 |= TIM_OCClear;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF2 signal on an external event\r
+ * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2CE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF3 signal on an external event\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3CE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr2 |= TIM_OCClear;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF4 signal on an external event\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ \r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4CE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 1 polarity.\r
+ * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC1 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC1P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);\r
+ tmpccer |= TIM_OCPolarity;\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Channel 1N polarity.\r
+ * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_OCNPolarity: specifies the OC1N Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCNPolarity_High: Output Compare active high\r
+ * @arg TIM_OCNPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC1NP Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);\r
+ tmpccer |= TIM_OCNPolarity;\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 2 polarity.\r
+ * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC2 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC2P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 4);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Channel 2N polarity.\r
+ * @param TIMx: where x can be 1 to select the TIM peripheral.\r
+ * @param TIM_OCNPolarity: specifies the OC2N Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCNPolarity_High: Output Compare active high\r
+ * @arg TIM_OCNPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC2NP Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);\r
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 3 polarity.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC3 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC3P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 8);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Channel 3N polarity.\r
+ * @param TIMx: where x can be 1 to select the TIM peripheral.\r
+ * @param TIM_OCNPolarity: specifies the OC3N Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCNPolarity_High: Output Compare active high\r
+ * @arg TIM_OCNPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC3NP Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);\r
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 4 polarity.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC4 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC4P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 12);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Selects the OCReference Clear source.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_OCReferenceClear: specifies the OCReference Clear source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.\r
+ * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. \r
+ * @retval None\r
+ */\r
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));\r
+\r
+ /* Set the TIM_OCReferenceClear source */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);\r
+ TIMx->SMCR |= TIM_OCReferenceClear;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel x.\r
+ * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_Channel: specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @arg TIM_Channel_4: TIM Channel 4\r
+ * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.\r
+ * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. \r
+ * @retval None\r
+ */\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)\r
+{\r
+ uint16_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_CCX(TIM_CCx));\r
+\r
+ tmp = CCER_CCE_SET << TIM_Channel;\r
+\r
+ /* Reset the CCxE Bit */\r
+ TIMx->CCER &= (uint16_t)~ tmp;\r
+\r
+ /* Set or reset the CCxE Bit */ \r
+ TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel xN.\r
+ * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_Channel: specifies the TIM Channel\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.\r
+ * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. \r
+ * @retval None\r
+ */\r
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)\r
+{\r
+ uint16_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));\r
+ assert_param(IS_TIM_CCXN(TIM_CCxN));\r
+\r
+ tmp = CCER_CCNE_SET << TIM_Channel;\r
+\r
+ /* Reset the CCxNE Bit */\r
+ TIMx->CCER &= (uint16_t) ~tmp;\r
+\r
+ /* Set or reset the CCxNE Bit */ \r
+ TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM peripheral Commutation event.\r
+ * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral\r
+ * @param NewState: new state of the Commutation event.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the COM Bit */\r
+ TIMx->CR2 |= TIM_CR2_CCUS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the COM Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group4 Input Capture management functions\r
+ * @brief Input Capture management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Input Capture management functions #####\r
+ ===============================================================================\r
+ \r
+ *** TIM Driver: how to use it in Input Capture Mode ***\r
+ ===============================================================================\r
+ [..] To use the Timer in Input Capture mode, the following steps are mandatory:\r
+ (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) \r
+ function.\r
+ (#) Configure the TIM pins by configuring the corresponding GPIO pins.\r
+ (#) Configure the Time base unit as described in the first part of this \r
+ driver, if needed, else the Timer will run with the default configuration:\r
+ (++) Autoreload value = 0xFFFF.\r
+ (++) Prescaler value = 0x0000.\r
+ (++) Counter mode = Up counting.\r
+ (++) Clock Division = TIM_CKD_DIV1.\r
+ (#) Fill the TIM_ICInitStruct with the desired parameters including:\r
+ (++) TIM Channel: TIM_Channel.\r
+ (++) TIM Input Capture polarity: TIM_ICPolarity.\r
+ (++) TIM Input Capture selection: TIM_ICSelection.\r
+ (++) TIM Input Capture Prescaler: TIM_ICPrescaler.\r
+ (++) TIM Input CApture filter value: TIM_ICFilter.\r
+ (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired \r
+ channel with the corresponding configuration and to measure only \r
+ frequency or duty cycle of the input signal,or, Call \r
+ TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired \r
+ channels with the corresponding configuration and to measure the \r
+ frequency and the duty cycle of the input signal.\r
+ (#) Enable the NVIC or the DMA to read the measured frequency.\r
+ (#) Enable the corresponding interrupt (or DMA request) to read \r
+ the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx)\r
+ (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).\r
+ (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.\r
+ (#) Use TIM_GetCapturex(TIMx); to read the captured value.\r
+ [..]\r
+ (@) All other functions can be used separately to modify, if needed,\r
+ a specific feature of the Timer. \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the TIM peripheral according to the specified\r
+ * parameters in the TIM_ICInitStruct.\r
+ * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); \r
+ assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));\r
+ assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));\r
+\r
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)\r
+ {\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)\r
+ {\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ /* TI3 Configuration */\r
+ TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ /* TI4 Configuration */\r
+ TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_ICInitStruct member with its default value.\r
+ * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;\r
+ TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;\r
+ TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;\r
+ TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;\r
+ TIM_ICInitStruct->TIM_ICFilter = 0x00;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM peripheral according to the specified\r
+ * parameters in the TIM_ICInitStruct to measure an external PWM signal.\r
+ * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.\r
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM \r
+ * peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ uint16_t icoppositepolarity = TIM_ICPolarity_Rising;\r
+ uint16_t icoppositeselection = TIM_ICSelection_DirectTI;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ /* Select the Opposite Input Polarity */\r
+ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)\r
+ {\r
+ icoppositepolarity = TIM_ICPolarity_Falling;\r
+ }\r
+ else\r
+ {\r
+ icoppositepolarity = TIM_ICPolarity_Rising;\r
+ }\r
+ /* Select the Opposite Input */\r
+ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)\r
+ {\r
+ icoppositeselection = TIM_ICSelection_IndirectTI;\r
+ }\r
+ else\r
+ {\r
+ icoppositeselection = TIM_ICSelection_DirectTI;\r
+ }\r
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else\r
+ { \r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 1 value.\r
+ * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.\r
+ * @retval Capture Compare 1 Register value.\r
+ */\r
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ \r
+ /* Get the Capture 1 Register value */\r
+ return TIMx->CCR1;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 2 value.\r
+ * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.\r
+ * @retval Capture Compare 2 Register value.\r
+ */\r
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ \r
+ /* Get the Capture 2 Register value */\r
+ return TIMx->CCR2;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 3 value.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @retval Capture Compare 3 Register value.\r
+ */\r
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
+ \r
+ /* Get the Capture 3 Register value */\r
+ return TIMx->CCR3;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 4 value.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @retval Capture Compare 4 Register value.\r
+ */\r
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ \r
+ /* Get the Capture 4 Register value */\r
+ return TIMx->CCR4;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 1 prescaler.\r
+ * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC1PSC Bits */\r
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);\r
+ /* Set the IC1PSC value */\r
+ TIMx->CCMR1 |= TIM_ICPSC;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 2 prescaler.\r
+ * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC2PSC Bits */\r
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);\r
+ /* Set the IC2PSC value */\r
+ TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 3 prescaler.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC3PSC Bits */\r
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);\r
+ /* Set the IC3PSC value */\r
+ TIMx->CCMR2 |= TIM_ICPSC;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 4 prescaler.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ \r
+ /* Reset the IC4PSC Bits */\r
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);\r
+ /* Set the IC4PSC value */\r
+ TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group5 Interrupts DMA and flags management functions\r
+ * @brief Interrupts, DMA and flags management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Interrupts, DMA and flags management functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM interrupts.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIMx peripheral.\r
+ * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_IT_Update: TIM update Interrupt source\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+ * @arg TIM_IT_Break: TIM Break Interrupt source\r
+ * @note \r
+ * - TIM6 can only generate an update interrupt.\r
+ * - TIM15 can have only TIM_IT_Update, TIM_IT_CC1,\r
+ * TIM_IT_CC2 or TIM_IT_Trigger. \r
+ * - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. \r
+ * - TIM_IT_Break is used only with TIM1 and TIM15. \r
+ * - TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. \r
+ * @param NewState: new state of the TIM interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IT(TIM_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Interrupt sources */\r
+ TIMx->DIER |= TIM_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Interrupt sources */\r
+ TIMx->DIER &= (uint16_t)~TIM_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx event to be generate by software.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the \r
+ * TIM peripheral.\r
+ * @param TIM_EventSource: specifies the event source.\r
+ * This parameter can be one or more of the following values: \r
+ * @arg TIM_EventSource_Update: Timer update Event source\r
+ * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source\r
+ * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source\r
+ * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source\r
+ * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source\r
+ * @arg TIM_EventSource_COM: Timer COM event source \r
+ * @arg TIM_EventSource_Trigger: Timer Trigger Event source\r
+ * @arg TIM_EventSource_Break: Timer Break event source\r
+ * @note \r
+ * - TIM6 can only generate an update event. \r
+ * - TIM9 can only generate an update event, Capture Compare 1 event, \r
+ * Capture Compare 2 event and TIM_EventSource_Trigger. \r
+ * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1. \r
+ * @retval None\r
+ */\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); \r
+ /* Set the event sources */\r
+ TIMx->EGR = TIM_EventSource;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified TIM flag is set or not.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_FLAG_Update: TIM update Flag\r
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
+ * @arg TIM_FLAG_COM: TIM Commutation Flag\r
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
+ * @arg TIM_FLAG_Break: TIM Break Flag\r
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
+ * @note\r
+ * - TIM6 can have only one update flag. \r
+ * - TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or \r
+ * TIM_FLAG_Trigger. \r
+ * - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. \r
+ * - TIM_FLAG_Break is used only with TIM1 and TIM15. \r
+ * - TIM_FLAG_COM is used only with TIM1 TIM15, TIM16 and TIM17. \r
+ * @retval The new state of TIM_FLAG (SET or RESET).\r
+ */\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
+{ \r
+ ITStatus bitstatus = RESET; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_GET_FLAG(TIM_FLAG));\r
+ \r
+ if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIMx's pending flags.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_FLAG: specifies the flag bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_FLAG_Update: TIM update Flag\r
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
+ * @arg TIM_FLAG_COM: TIM Commutation Flag\r
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
+ * @arg TIM_FLAG_Break: TIM Break Flag\r
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
+ * @note\r
+ * - TIM6 can have only one update flag. \r
+ * - TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,TIM_FLAG_CC2 or \r
+ * TIM_FLAG_Trigger. \r
+ * - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. \r
+ * - TIM_FLAG_Break is used only with TIM1 and TIM15. \r
+ * - TIM_FLAG_COM is used only with TIM1, TIM15, TIM16 and TIM17.\r
+ * @retval None\r
+ */\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));\r
+ \r
+ /* Clear the flags */\r
+ TIMx->SR = (uint16_t)~TIM_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the TIM interrupt has occurred or not.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_IT: specifies the TIM interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_Update: TIM update Interrupt source\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+ * @arg TIM_IT_Break: TIM Break Interrupt source\r
+ * @note\r
+ * - TIM6 can generate only an update interrupt.\r
+ * - TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. \r
+ * - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. \r
+ * - TIM_IT_Break is used only with TIM1 and TIM15. \r
+ * - TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.\r
+ * @retval The new state of the TIM_IT(SET or RESET).\r
+ */\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
+{\r
+ ITStatus bitstatus = RESET; \r
+ uint16_t itstatus = 0x0, itenable = 0x0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_GET_IT(TIM_IT));\r
+ \r
+ itstatus = TIMx->SR & TIM_IT;\r
+ \r
+ itenable = TIMx->DIER & TIM_IT;\r
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIMx's interrupt pending bits.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_IT: specifies the pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_IT_Update: TIM1 update Interrupt source\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+ * @arg TIM_IT_Break: TIM Break Interrupt source\r
+ * @note\r
+ * - TIM6 can generate only an update interrupt.\r
+ * - TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. \r
+ * - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. \r
+ * - TIM_IT_Break is used only with TIM1 and TIM15. \r
+ * - TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.\r
+ * @retval None\r
+ */\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IT(TIM_IT));\r
+ \r
+ /* Clear the IT pending Bit */\r
+ TIMx->SR = (uint16_t)~TIM_IT;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx's DMA interface.\r
+ * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_DMABase: DMA Base address.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMABase_CR1, TIM_DMABase_CR2, TIM_DMABase_SMCR,\r
+ * TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,\r
+ * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,\r
+ * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,\r
+ * TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3, \r
+ * TIM_DMABase_CCR4, TIM_DMABase_DCR, TIM_DMABase_OR.\r
+ * @param TIM_DMABurstLength: DMA Burst length.\r
+ * This parameter can be one value between:\r
+ * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.\r
+ * @retval None\r
+ */\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); \r
+ assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));\r
+ /* Set the DMA Base and the DMA Burst Length */\r
+ TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx's DMA Requests.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, 15, 16 or 17 to select the TIM peripheral. \r
+ * @param TIM_DMASource: specifies the DMA Request sources.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_DMA_Update: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_COM: TIM Commutation DMA source\r
+ * @arg TIM_DMA_Trigger: TIM Trigger DMA source\r
+ * @param NewState: new state of the DMA Request sources.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST10_PERIPH(TIMx));\r
+ assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA sources */\r
+ TIMx->DIER |= TIM_DMASource; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA sources */\r
+ TIMx->DIER &= (uint16_t)~TIM_DMASource;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.\r
+ * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param NewState: new state of the Capture Compare DMA source\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST5_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the CCDS Bit */\r
+ TIMx->CR2 |= TIM_CR2_CCDS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the CCDS Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group6 Clocks management functions\r
+ * @brief Clocks management functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Clocks management functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the TIMx internal Clock\r
+ * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ /* Disable slave mode to clock the prescaler directly with the internal clock */\r
+ TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Internal Trigger as External Clock\r
+ * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.\r
+ * @param TIM_ITRSource: Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal Trigger 0\r
+ * @arg TIM_TS_ITR1: Internal Trigger 1\r
+ * @arg TIM_TS_ITR2: Internal Trigger 2\r
+ * @arg TIM_TS_ITR3: Internal Trigger 3\r
+ * @retval None\r
+ */\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+ /* Select the Internal Trigger */\r
+ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);\r
+ /* Select the External clock mode1 */\r
+ TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Trigger as External Clock\r
+ * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.\r
+ * @param TIM_TIxExternalCLKSource: Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector\r
+ * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1\r
+ * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2\r
+ * @param TIM_ICPolarity: specifies the TIx Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param ICFilter : specifies the filter value.\r
+ * This parameter must be a value between 0x0 and 0xF.\r
+ * @retval None\r
+ */\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+ uint16_t TIM_ICPolarity, uint16_t ICFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));\r
+ assert_param(IS_TIM_IC_FILTER(ICFilter));\r
+ \r
+ /* Configure the Timer Input Clock Source */\r
+ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)\r
+ {\r
+ TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+ }\r
+ else\r
+ {\r
+ TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+ }\r
+ /* Select the Trigger source */\r
+ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);\r
+ /* Select the External clock mode1 */\r
+ TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External clock Mode1\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ \r
+ /* Configure the ETR Clock source */\r
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+ \r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the SMS Bits */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+ /* Select the External clock mode1 */\r
+ tmpsmcr |= TIM_SlaveMode_External1;\r
+ /* Select the Trigger selection : ETRF */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
+ tmpsmcr |= TIM_TS_ETRF;\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External clock Mode2\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ \r
+ /* Configure the ETR Clock source */\r
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+ /* Enable the External clock mode2 */\r
+ TIMx->SMCR |= TIM_SMCR_ECE;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group7 Synchronization management functions\r
+ * @brief Synchronization management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Synchronization management functions #####\r
+ ===============================================================================\r
+ *** TIM Driver: how to use it in synchronization Mode ***\r
+ ===============================================================================\r
+ [..] Case of two/several Timers\r
+ (#) Configure the Master Timers using the following functions:\r
+ (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx,\r
+ uint16_t TIM_TRGOSource).\r
+ (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx,\r
+ uint16_t TIM_MasterSlaveMode); \r
+ (#) Configure the Slave Timers using the following functions: \r
+ (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, \r
+ uint16_t TIM_InputTriggerSource); \r
+ (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
+ [..] Case of Timers and external trigger(ETR pin)\r
+ (#) Configure the Etrenal trigger using this function:\r
+ (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,\r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r
+ (#) Configure the Slave Timers using the following functions:\r
+ (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx,\r
+ uint16_t TIM_InputTriggerSource);\r
+ (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Selects the Input Trigger source\r
+ * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.\r
+ * @param TIM_InputTriggerSource: The Input Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal Trigger 0\r
+ * @arg TIM_TS_ITR1: Internal Trigger 1\r
+ * @arg TIM_TS_ITR2: Internal Trigger 2\r
+ * @arg TIM_TS_ITR3: Internal Trigger 3\r
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
+ * @arg TIM_TS_ETRF: External Trigger input\r
+ * @retval None\r
+ */\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the TS Bits */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
+ /* Set the Input Trigger source */\r
+ tmpsmcr |= TIM_InputTriggerSource;\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx Trigger Output Mode.\r
+ * @param TIMx: where x can be 1, 2, 3, 6, or 15 to select the TIM peripheral.\r
+ * @param TIM_TRGOSource: specifies the Trigger Output source.\r
+ * This paramter can be one of the following values:\r
+ *\r
+ * For all TIMx\r
+ * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).\r
+ *\r
+ * For all TIMx except TIM6 \r
+ * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag\r
+ * is to be set, as soon as a capture or compare match occurs (TRGO).\r
+ * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).\r
+ *\r
+ * @retval None\r
+ */\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST9_PERIPH(TIMx));\r
+ assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));\r
+\r
+ /* Reset the MMS Bits */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);\r
+ /* Select the TRGO source */\r
+ TIMx->CR2 |= TIM_TRGOSource;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx Slave Mode.\r
+ * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.\r
+ * @param TIM_SlaveMode: specifies the Timer Slave Mode.\r
+ * This paramter can be one of the following values:\r
+ * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes\r
+ * the counter and triggers an update of the registers.\r
+ * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.\r
+ * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.\r
+ * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.\r
+ * @retval None\r
+ */\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));\r
+ \r
+ /* Reset the SMS Bits */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);\r
+ /* Select the Slave Mode */\r
+ TIMx->SMCR |= TIM_SlaveMode;\r
+}\r
+\r
+/**\r
+ * @brief Sets or Resets the TIMx Master/Slave Mode.\r
+ * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.\r
+ * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.\r
+ * This paramter can be one of the following values:\r
+ * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer\r
+ * and its slaves (through TRGO).\r
+ * @arg TIM_MasterSlaveMode_Disable: No action\r
+ * @retval None\r
+ */\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));\r
+ \r
+ /* Reset the MSM Bit */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);\r
+ \r
+ /* Set or Reset the MSM Bit */\r
+ TIMx->SMCR |= TIM_MasterSlaveMode;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx External Trigger (ETR).\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ \r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the ETR Bits */\r
+ tmpsmcr &= SMCR_ETR_MASK;\r
+ /* Set the Prescaler, the Filter value and the Polarity */\r
+ tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group8 Specific interface management functions\r
+ * @brief Specific interface management functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Specific interface management functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the TIMx Encoder Interface.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.\r
+ * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.\r
+ * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending\r
+ * on the level of the other input.\r
+ * @param TIM_IC1Polarity: specifies the IC1 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @param TIM_IC2Polarity: specifies the IC2 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @retval None\r
+ */\r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ uint16_t tmpccmr1 = 0;\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));\r
+ \r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Set the encoder Mode */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+ tmpsmcr |= TIM_EncoderMode;\r
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));\r
+ tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;\r
+ /* Set the TI1 and the TI2 Polarities */\r
+ tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));\r
+ tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx's Hall sensor interface.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx Hall sensor interface.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the TI1S Bit */\r
+ TIMx->CR2 |= TIM_CR2_TI1S;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the TI1S Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group9 Specific remapping management function\r
+ * @brief Specific remapping management function\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Specific remapping management function #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Configures the TIM14 Remapping input Capabilities.\r
+ * @param TIMx: where x can be 14 to select the TIM peripheral.\r
+ * @param TIM_Remap: specifies the TIM input reampping source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM14_GPIO : TIM14 Channel 1 is connected to GPIO.\r
+ * @arg TIM14_RTC_CLK : TIM14 Channel 1 is connected to RTC input clock.\r
+ * RTC input clock can be LSE, LSI or HSE/div128.\r
+ * @retval : None\r
+ */\r
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST11_PERIPH(TIMx));\r
+ assert_param(IS_TIM_REMAP(TIM_Remap));\r
+\r
+ /* Set the Timer remapping configuration */\r
+ TIMx->OR = TIM_Remap;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Configure the TI1 as Input.\r
+ * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr1 = 0, tmpccer = 0;\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));\r
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
+ \r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI2 as Input.\r
+ * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 4);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));\r
+ tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);\r
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); \r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); \r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI3 as Input.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+ /* Disable the Channel 3: Reset the CC3E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 8);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));\r
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
+ /* Select the Polarity and set the CC3E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); \r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI4 as Input.\r
+ * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+\r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 12);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));\r
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);\r
+ tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); \r
+ /* Select the Polarity and set the CC4E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_usart.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Universal synchronous asynchronous receiver\r
+ * transmitter (USART):\r
+ * - Initialization and Configuration\r
+ * - STOP Mode\r
+ * - AutoBaudRate\r
+ * - Data transfers\r
+ * - Multi-Processor Communication\r
+ * - LIN mode\r
+ * - Half-duplex mode\r
+ * - Smartcard mode\r
+ * - IrDA mode\r
+ * - RS485 mode \r
+ * - DMA transfers management\r
+ * - Interrupts and flags management\r
+ * \r
+ * @verbatim\r
+ ===============================================================================\r
+ ##### How to use this driver #####\r
+ ===============================================================================\r
+ [..]\r
+ (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)\r
+ function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)\r
+ function for USART2 and USART3.\r
+ (#) According to the USART mode, enable the GPIO clocks using \r
+ RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS, \r
+ or and SCLK). \r
+ (#) Peripheral's alternate function: \r
+ (++) Connect the pin to the desired peripherals' Alternate \r
+ Function (AF) using GPIO_PinAFConfig() function.\r
+ (++) Configure the desired pin in alternate function by:\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.\r
+ (++) Select the type, pull-up/pull-down and output speed via \r
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members.\r
+ (++) Call GPIO_Init() function. \r
+ (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware \r
+ flow control and Mode(Receiver/Transmitter) using the SPI_Init()\r
+ function. \r
+ (#) For synchronous mode, enable the clock and program the polarity,\r
+ phase and last bit using the USART_ClockInit() function. \r
+ (#) Enable the NVIC and the corresponding interrupt using the function \r
+ USART_ITConfig() if you need to use interrupt mode. \r
+ (#) When using the DMA mode: \r
+ (++) Configure the DMA using DMA_Init() function.\r
+ (++) Active the needed channel Request using USART_DMACmd() function. \r
+ (#) Enable the USART using the USART_Cmd() function. \r
+ (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. \r
+ [..]\r
+ Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections\r
+ for more details.\r
+ \r
+@endverbatim\r
+ \r
+ ******************************************************************************\r
+ @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_usart.h"\r
+#include "stm32f0xx_rcc.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART \r
+ * @brief USART driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/*!< USART CR1 register clear Mask ((~(uint32_t)0xFFFFE6F3)) */\r
+#define CR1_CLEAR_MASK ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \\r
+ USART_CR1_PS | USART_CR1_TE | \\r
+ USART_CR1_RE))\r
+\r
+/*!< USART CR2 register clock bits clear Mask ((~(uint32_t)0xFFFFF0FF)) */\r
+#define CR2_CLOCK_CLEAR_MASK ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \\r
+ USART_CR2_CPHA | USART_CR2_LBCL))\r
+\r
+/*!< USART CR3 register clear Mask ((~(uint32_t)0xFFFFFCFF)) */\r
+#define CR3_CLEAR_MASK ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))\r
+\r
+/*!< USART Interrupts mask */\r
+#define IT_MASK ((uint32_t)0x000000FF)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup USART_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART_Group1 Initialization and Configuration functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to initialize the USART \r
+ in asynchronous and in synchronous modes.\r
+ (+) For the asynchronous mode only these parameters can be configured: \r
+ (+) Baud Rate.\r
+ (+) Word Length.\r
+ (+) Stop Bit.\r
+ (+) Parity: If the parity is enabled, then the MSB bit of the data written\r
+ in the data register is transmitted but is changed by the parity bit.\r
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),\r
+ the possible USART frame formats are as listed in the following table:\r
+ [..]\r
+ +-------------------------------------------------------------+ \r
+ | M bit | PCE bit | USART frame |\r
+ |---------------------|---------------------------------------| \r
+ | 0 | 0 | | SB | 8 bit data | STB | |\r
+ |---------|-----------|---------------------------------------| \r
+ | 0 | 1 | | SB | 7 bit data | PB | STB | |\r
+ |---------|-----------|---------------------------------------| \r
+ | 1 | 0 | | SB | 9 bit data | STB | |\r
+ |---------|-----------|---------------------------------------| \r
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |\r
+ +-------------------------------------------------------------+ \r
+ [..]\r
+ (+) Hardware flow control.\r
+ (+) Receiver/transmitter modes.\r
+ [..] The USART_Init() function follows the USART asynchronous configuration \r
+ procedure(details for the procedure are available in reference manual.\r
+ (+) For the synchronous mode in addition to the asynchronous mode parameters\r
+ these parameters should be also configured:\r
+ (++) USART Clock Enabled.\r
+ (++) USART polarity.\r
+ (++) USART phase.\r
+ (++) USART LastBit.\r
+ [..] These parameters can be configured using the USART_ClockInit() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Deinitializes the USARTx peripheral registers to their default reset values.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @retval None\r
+ */\r
+void USART_DeInit(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+\r
+ if (USARTx == USART1)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);\r
+ }\r
+ else \r
+ {\r
+ if (USARTx == USART2)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the USARTx peripheral according to the specified\r
+ * parameters in the USART_InitStruct .\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+ * that contains the configuration information for the specified USART peripheral.\r
+ * @retval None\r
+ */\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0, apbclock = 0;\r
+ uint32_t integerdivider = 0;\r
+ uint32_t fractionaldivider = 0;\r
+ RCC_ClocksTypeDef RCC_ClocksStatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); \r
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));\r
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));\r
+ assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));\r
+ assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));\r
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));\r
+ \r
+ /* Disable USART */\r
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);\r
+ \r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR2;\r
+ /* Clear STOP[13:12] bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);\r
+\r
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/\r
+ /* Set STOP[13:12] bits according to USART_StopBits value */\r
+ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;\r
+ \r
+ /* Write to USART CR2 */\r
+ USARTx->CR2 = tmpreg;\r
+\r
+/*---------------------------- USART CR1 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR1;\r
+ /* Clear M, PCE, PS, TE and RE bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);\r
+\r
+ /* Configure the USART Word Length, Parity and mode ----------------------- */\r
+ /* Set the M bits according to USART_WordLength value */\r
+ /* Set PCE and PS bits according to USART_Parity value */\r
+ /* Set TE and RE bits according to USART_Mode value */\r
+ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |\r
+ USART_InitStruct->USART_Mode;\r
+\r
+ /* Write to USART CR1 */\r
+ USARTx->CR1 = tmpreg;\r
+\r
+/*---------------------------- USART CR3 Configuration -----------------------*/ \r
+ tmpreg = USARTx->CR3;\r
+ /* Clear CTSE and RTSE bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);\r
+\r
+ /* Configure the USART HFC -------------------------------------------------*/\r
+ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */\r
+ tmpreg |= USART_InitStruct->USART_HardwareFlowControl;\r
+\r
+ /* Write to USART CR3 */\r
+ USARTx->CR3 = tmpreg;\r
+\r
+/*---------------------------- USART BRR Configuration -----------------------*/\r
+ /* Configure the USART Baud Rate -------------------------------------------*/\r
+ RCC_GetClocksFreq(&RCC_ClocksStatus);\r
+ \r
+ if (USARTx == USART1)\r
+ {\r
+ apbclock = RCC_ClocksStatus.USART1CLK_Frequency;\r
+ }\r
+ else\r
+ {\r
+ apbclock = RCC_ClocksStatus.PCLK_Frequency;\r
+ }\r
+ /* Determine the integer part */\r
+ if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r
+ {\r
+ /* Integer part computing in case Oversampling mode is 8 Samples */\r
+ integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); \r
+ }\r
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
+ {\r
+ /* Integer part computing in case Oversampling mode is 16 Samples */\r
+ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); \r
+ }\r
+ tmpreg = (integerdivider / 100) << 4;\r
+\r
+ /* Determine the fractional part */\r
+ fractionaldivider = integerdivider - (100 * (tmpreg >> 4));\r
+\r
+ /* Implement the fractional part in the register */\r
+ if ((USARTx->CR1 & USART_CR1_OVER8) != 0)\r
+ {\r
+ tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);\r
+ }\r
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
+ {\r
+ tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);\r
+ }\r
+ \r
+ /* Write to USART BRR */\r
+ USARTx->BRR = (uint16_t)tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each USART_InitStruct member with its default value.\r
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+ * which will be initialized.\r
+ * @retval None\r
+ */\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ /* USART_InitStruct members default value */\r
+ USART_InitStruct->USART_BaudRate = 9600;\r
+ USART_InitStruct->USART_WordLength = USART_WordLength_8b;\r
+ USART_InitStruct->USART_StopBits = USART_StopBits_1;\r
+ USART_InitStruct->USART_Parity = USART_Parity_No ;\r
+ USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
+ USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the USARTx peripheral Clock according to the \r
+ * specified parameters in the USART_ClockInitStruct.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+ * structure that contains the configuration information for the specified \r
+ * USART peripheral. \r
+ * @retval None\r
+ */\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));\r
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));\r
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));\r
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));\r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR2;\r
+ /* Clear CLKEN, CPOL, CPHA, LBCL and SSM bits */\r
+ tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);\r
+ /* Configure the USART Clock, CPOL, CPHA, LastBit and SSM ------------*/\r
+ /* Set CLKEN bit according to USART_Clock value */\r
+ /* Set CPOL bit according to USART_CPOL value */\r
+ /* Set CPHA bit according to USART_CPHA value */\r
+ /* Set LBCL bit according to USART_LastBit value */\r
+ tmpreg |= (uint32_t)(USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | \r
+ USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit);\r
+ /* Write to USART CR2 */\r
+ USARTx->CR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each USART_ClockInitStruct member with its default value.\r
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+ /* USART_ClockInitStruct members default value */\r
+ USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;\r
+ USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;\r
+ USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;\r
+ USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified USART peripheral.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param NewState: new state of the USARTx peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected USART by setting the UE bit in the CR1 register */\r
+ USARTx->CR1 |= USART_CR1_UE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected USART by clearing the UE bit in the CR1 register */\r
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's transmitter or receiver.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_Direction: specifies the USART direction.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_Mode_Tx: USART Transmitter\r
+ * @arg USART_Mode_Rx: USART Receiver\r
+ * @param NewState: new state of the USART transfer direction.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_MODE(USART_DirectionMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the USART's transfer interface by setting the TE and/or RE bits \r
+ in the USART CR1 register */\r
+ USARTx->CR1 |= USART_DirectionMode;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the USART's transfer interface by clearing the TE and/or RE bits\r
+ in the USART CR3 register */\r
+ USARTx->CR1 &= (uint32_t)~USART_DirectionMode;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's 8x oversampling mode.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param NewState: new state of the USART 8x oversampling mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note\r
+ * This function has to be called before calling USART_Init()\r
+ * function in order to have correct baudrate Divider value.\r
+ * @retval None\r
+ */\r
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */\r
+ USARTx->CR1 |= USART_CR1_OVER8;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */\r
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_OVER8);\r
+ }\r
+} \r
+\r
+/**\r
+ * @brief Enables or disables the USART's one bit sampling method.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param NewState: new state of the USART one bit sampling method.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note\r
+ * This function has to be called before calling USART_Cmd() function. \r
+ * @retval None\r
+ */\r
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_ONEBIT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */\r
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's most significant bit first \r
+ * transmitted/received following the start bit.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param NewState: new state of the USART most significant bit first\r
+ * transmitted/received following the start bit.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note\r
+ * This function has to be called before calling USART_Cmd() function. \r
+ * @retval None\r
+ */\r
+void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the most significant bit first transmitted/received following the \r
+ start bit by setting the MSBFIRST bit in the CR2 register */\r
+ USARTx->CR2 |= USART_CR2_MSBFIRST;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the most significant bit first transmitted/received following the \r
+ start bit by clearing the MSBFIRST bit in the CR2 register */\r
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_MSBFIRST);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the binary data inversion.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param NewState: new defined levels for the USART data.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * - ENABLE: Logical data from the data register are send/received in negative\r
+ * logic. (1=L, 0=H). The parity bit is also inverted.\r
+ * - DISABLE: Logical data from the data register are send/received in positive\r
+ * logic. (1=H, 0=L) \r
+ * @note\r
+ * This function has to be called before calling USART_Cmd() function. \r
+ * @retval None\r
+ */\r
+void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the binary data inversion feature by setting the DATAINV bit in \r
+ the CR2 register */\r
+ USARTx->CR2 |= USART_CR2_DATAINV;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the binary data inversion feature by clearing the DATAINV bit in \r
+ the CR2 register */\r
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_DATAINV);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Pin(s) active level inversion.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_InvPin: specifies the USART pin(s) to invert.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_InvPin_Tx: USART Tx pin active level inversion.\r
+ * @arg USART_InvPin_Rx: USART Rx pin active level inversion.\r
+ * @param NewState: new active level status for the USART pin(s).\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * - ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1).\r
+ * - DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0).\r
+ * @note\r
+ * This function has to be called before calling USART_Cmd() function. \r
+ * @retval None\r
+ */\r
+void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_INVERSTION_PIN(USART_InvPin)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the active level inversion for selected pins by setting the TXINV \r
+ and/or RXINV bits in the USART CR2 register */\r
+ USARTx->CR2 |= USART_InvPin;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the active level inversion for selected requests by clearing the \r
+ TXINV and/or RXINV bits in the USART CR2 register */\r
+ USARTx->CR2 &= (uint32_t)~USART_InvPin;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the swap Tx/Rx pins.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param NewState: new state of the USARTx TX/RX pins pinout.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * - ENABLE: The TX and RX pins functions are swapped.\r
+ * - DISABLE: TX/RX pins are used as defined in standard pinout\r
+ * @note\r
+ * This function has to be called before calling USART_Cmd() function. \r
+ * @retval None\r
+ */\r
+void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the SWAP feature by setting the SWAP bit in the CR2 register */\r
+ USARTx->CR2 |= USART_CR2_SWAP;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SWAP feature by clearing the SWAP bit in the CR2 register */\r
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_SWAP);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the receiver Time Out feature.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param NewState: new state of the USARTx receiver Time Out.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the receiver time out feature by setting the RTOEN bit in the CR2 \r
+ register */\r
+ USARTx->CR2 |= USART_CR2_RTOEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the receiver time out feature by clearing the RTOEN bit in the CR2 \r
+ register */\r
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_RTOEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the receiver Time Out value.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param USART_ReceiverTimeOut: specifies the Receiver Time Out value.\r
+ * @retval None\r
+ */\r
+void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx));\r
+ assert_param(IS_USART_TIMEOUT(USART_ReceiverTimeOut));\r
+\r
+ /* Clear the receiver Time Out value by clearing the RTO[23:0] bits in the RTOR\r
+ register */\r
+ USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_RTO);\r
+ /* Set the receiver Time Out value by setting the RTO[23:0] bits in the RTOR\r
+ register */\r
+ USARTx->RTOR |= USART_ReceiverTimeOut;\r
+}\r
+\r
+/**\r
+ * @brief Sets the system clock prescaler.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param USART_Prescaler: specifies the prescaler clock.\r
+ * @note\r
+ * This function has to be called before calling USART_Cmd() function. \r
+ * @retval None\r
+ */\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx));\r
+ \r
+ /* Clear the USART prescaler */\r
+ USARTx->GTPR &= USART_GTPR_GT;\r
+ /* Set the USART prescaler */\r
+ USARTx->GTPR |= USART_Prescaler;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup USART_Group2 STOP Mode functions\r
+ * @brief STOP Mode functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### STOP Mode functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage \r
+ WakeUp from STOP mode.\r
+\r
+ [..] The USART is able to WakeUp from Stop Mode if USART clock is set to HSI\r
+ or LSI.\r
+ \r
+ [..] The WakeUp source is configured by calling USART_StopModeWakeUpSourceConfig()\r
+ function.\r
+ \r
+ [..] After configuring the source of WakeUp and before entering in Stop Mode \r
+ USART_STOPModeCmd() function should be called to allow USART WakeUp.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified USART peripheral in STOP Mode.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param NewState: new state of the USARTx peripheral state in stop mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note\r
+ * This function has to be called when USART clock is set to HSI or LSE. \r
+ * @retval None\r
+ */\r
+void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected USART in STOP mode by setting the UESM bit in the CR1\r
+ register */\r
+ USARTx->CR1 |= USART_CR1_UESM;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected USART in STOP mode by clearing the UE bit in the CR1\r
+ register */\r
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UESM);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the USART WakeUp method form stop mode.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param USART_WakeUp: specifies the selected USART wakeup method.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_WakeUpSource_AddressMatch: WUF active on address match.\r
+ * @arg USART_WakeUpSource_StartBit: WUF active on Start bit detection.\r
+ * @arg USART_WakeUpSource_RXNE: WUF active on RXNE.\r
+ * @note\r
+ * This function has to be called before calling USART_Cmd() function. \r
+ * @retval None\r
+ */\r
+void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx));\r
+ assert_param(IS_USART_STOPMODE_WAKEUPSOURCE(USART_WakeUpSource));\r
+\r
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_WUS);\r
+ USARTx->CR3 |= USART_WakeUpSource;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup USART_Group3 AutoBaudRate functions\r
+ * @brief AutoBaudRate functions \r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### AutoBaudRate functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage \r
+ the AutoBaudRate detections.\r
+ \r
+ [..] Before Enabling AutoBaudRate detection using USART_AutoBaudRateCmd ()\r
+ The character patterns used to calculate baudrate must be chosen by calling \r
+ USART_AutoBaudRateConfig() function. These function take as parameter :\r
+ (#)USART_AutoBaudRate_StartBit : any character starting with a bit 1.\r
+ (#)USART_AutoBaudRate_FallingEdge : any character starting with a 10xx bit pattern. \r
+ \r
+ [..] At any later time, another request for AutoBaudRate detection can be performed\r
+ using USART_AutoBaudRateNewRequest() function.\r
+ \r
+ [..] The AutoBaudRate detection is monitored by the status of ABRF flag which indicate\r
+ that the AutoBaudRate detection is completed. In addition to ABRF flag, the ABRE flag\r
+ indicate that this procedure is completed without success. USART_GetFlagStatus () \r
+ function should be used to monitor the status of these flags. \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the Auto Baud Rate.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param NewState: new state of the USARTx auto baud rate.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the auto baud rate feature by setting the ABREN bit in the CR2 \r
+ register */\r
+ USARTx->CR2 |= USART_CR2_ABREN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the auto baud rate feature by clearing the ABREN bit in the CR2 \r
+ register */\r
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABREN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the USART auto baud rate method.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param USART_AutoBaudRate: specifies the selected USART auto baud rate method.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_AutoBaudRate_StartBit: Start Bit duration measurement.\r
+ * @arg USART_AutoBaudRate_FallingEdge: Falling edge to falling edge measurement.\r
+ * @note\r
+ * This function has to be called before calling USART_Cmd() function. \r
+ * @retval None\r
+ */\r
+void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx));\r
+ assert_param(IS_USART_AUTOBAUDRATE_MODE(USART_AutoBaudRate));\r
+\r
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABRMODE);\r
+ USARTx->CR2 |= USART_AutoBaudRate;\r
+}\r
+\r
+/**\r
+ * @brief Requests a new AutoBaudRate detection.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @retval None\r
+ */\r
+void USART_AutoBaudRateNewRequest(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+\r
+ USARTx->ISR &= (uint32_t)~((uint32_t)USART_FLAG_ABRF);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup USART_Group4 Data transfers functions\r
+ * @brief Data transfers functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Data transfers functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage \r
+ the USART data transfers.\r
+ [..] During an USART reception, data shifts in least significant bit first \r
+ through the RX pin. When a transmission is taking place, a write instruction to \r
+ the USART_TDR register stores the data in the shift register.\r
+ [..] The read access of the USART_RDR register can be done using \r
+ the USART_ReceiveData() function and returns the RDR value.\r
+ Whereas a write access to the USART_TDR can be done using USART_SendData()\r
+ function and stores the written data into TDR.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmits single data through the USARTx peripheral.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param Data: the data to transmit.\r
+ * @retval None\r
+ */\r
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DATA(Data)); \r
+ \r
+ /* Transmit Data */\r
+ USARTx->TDR = (Data & (uint16_t)0x01FF);\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the USARTx peripheral.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @retval The received data.\r
+ */\r
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Receive Data */\r
+ return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group5 MultiProcessor Communication functions\r
+ * @brief Multi-Processor Communication functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Multi-Processor Communication functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage the USART\r
+ multiprocessor communication.\r
+ [..] For instance one of the USARTs can be the master, its TX output is\r
+ connected to the RX input of the other USART. The others are slaves,\r
+ their respective TX outputs are logically ANDed together and connected \r
+ to the RX input of the master. USART multiprocessor communication is \r
+ possible through the following procedure:\r
+ (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, \r
+ Mode transmitter or Mode receiver and hardware flow control values \r
+ using the USART_Init() function.\r
+ (#) Configures the USART address using the USART_SetAddress() function.\r
+ (#) Configures the wake up methode (USART_WakeUp_IdleLine or \r
+ USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only \r
+ for the slaves.\r
+ (#) Enable the USART using the USART_Cmd() function.\r
+ (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() \r
+ function.\r
+ [..] The USART Slave exit from mute mode when receive the wake up condition.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the address of the USART node.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_Address: Indicates the address of the USART node.\r
+ * @retval None\r
+ */\r
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Clear the USART address */\r
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADD);\r
+ /* Set the USART address node */\r
+ USARTx->CR2 |=((uint32_t)USART_Address << (uint32_t)0x18);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's mute mode.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param NewState: new state of the USART mute mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the USART mute mode by setting the MME bit in the CR1 register */\r
+ USARTx->CR1 |= USART_CR1_MME;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the USART mute mode by clearing the MME bit in the CR1 register */\r
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_MME);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the USART WakeUp method from mute mode.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_WakeUp: specifies the USART wakeup method.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection\r
+ * @arg USART_WakeUp_AddressMark: WakeUp by an address mark\r
+ * @retval None\r
+ */\r
+void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_MUTEMODE_WAKEUP(USART_WakeUp));\r
+\r
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_WAKE);\r
+ USARTx->CR1 |= USART_WakeUp;\r
+}\r
+\r
+/**\r
+ * @brief Configure the the USART Address detection length.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_AddressLength: specifies the USART address length detection.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_AddressLength_4b: 4-bit address length detection \r
+ * @arg USART_AddressLength_7b: 7-bit address length detection \r
+ * @retval None\r
+ */\r
+void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_ADDRESS_DETECTION(USART_AddressLength));\r
+\r
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADDM7);\r
+ USARTx->CR2 |= USART_AddressLength;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group6 LIN mode functions\r
+ * @brief LIN mode functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### LIN mode functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage the USART \r
+ LIN Mode communication.\r
+ [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance \r
+ with the LIN standard.\r
+ [..] Only this LIN Feature is supported by the USART IP:\r
+ (+) LIN Master Synchronous Break send capability and LIN slave break \r
+ detection capability : 13-bit break generation and 10/11 bit break \r
+ detection.\r
+ [..] USART LIN Master transmitter communication is possible through the \r
+ following procedure:\r
+ (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, \r
+ Mode transmitter or Mode receiver and hardware flow control values \r
+ using the USART_Init() function.\r
+ (#) Enable the LIN mode using the USART_LINCmd() function.\r
+ (#) Enable the USART using the USART_Cmd() function.\r
+ (#) Send the break character using USART_SendBreak() function.\r
+ [..] USART LIN Master receiver communication is possible through the \r
+ following procedure:\r
+ (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, \r
+ Mode transmitter or Mode receiver and hardware flow control values \r
+ using the USART_Init() function.\r
+ (#) Configures the break detection length \r
+ using the USART_LINBreakDetectLengthConfig() function.\r
+ (#) Enable the LIN mode using the USART_LINCmd() function.\r
+ -@- In LIN mode, the following bits must be kept cleared:\r
+ (+@) CLKEN in the USART_CR2 register.\r
+ (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.\r
+ (#) Enable the USART using the USART_Cmd() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the USART LIN Break detection length.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param USART_LINBreakDetectLength: specifies the LIN break detection length.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_LINBreakDetectLength_10b: 10-bit break detection\r
+ * @arg USART_LINBreakDetectLength_11b: 11-bit break detection\r
+ * @retval None\r
+ */\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx));\r
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));\r
+\r
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LBDL);\r
+ USARTx->CR2 |= USART_LINBreakDetectLength; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's LIN mode.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param NewState: new state of the USART LIN mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
+ USARTx->CR2 |= USART_CR2_LINEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */\r
+ USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LINEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group7 Halfduplex mode function\r
+ * @brief Half-duplex mode function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Half-duplex mode function #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage the USART\r
+ Half-duplex communication.\r
+ [..] The USART can be configured to follow a single-wire half-duplex protocol \r
+ where the TX and RX lines are internally connected.\r
+ [..] USART Half duplex communication is possible through the following procedure:\r
+ (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter \r
+ or Mode receiver and hardware flow control values using the USART_Init()\r
+ function.\r
+ (#) Configures the USART address using the USART_SetAddress() function.\r
+ (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.\r
+ (#) Enable the USART using the USART_Cmd() function.\r
+ -@- The RX pin is no longer used.\r
+ -@- In Half-duplex mode the following bits must be kept cleared:\r
+ (+@) LINEN and CLKEN bits in the USART_CR2 register.\r
+ (+@) SCEN and IREN bits in the USART_CR3 register.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the USART's Half Duplex communication.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param NewState: new state of the USART Communication.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_HDSEL;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_HDSEL);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup USART_Group8 Smartcard mode functions\r
+ * @brief Smartcard mode functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Smartcard mode functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage the USART\r
+ Smartcard communication.\r
+ [..] The Smartcard interface is designed to support asynchronous protocol \r
+ Smartcards as defined in the ISO 7816-3 standard. The USART can provide \r
+ a clock to the smartcard through the SCLK output. In smartcard mode, \r
+ SCLK is not associated to the communication but is simply derived from \r
+ the internal peripheral input clock through a 5-bit prescaler.\r
+ [..] Smartcard communication is possible through the following procedure:\r
+ (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler() \r
+ function.\r
+ (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() \r
+ function.\r
+ (#) Program the USART clock using the USART_ClockInit() function as following:\r
+ (++) USART Clock enabled.\r
+ (++) USART CPOL Low.\r
+ (++) USART CPHA on first edge.\r
+ (++) USART Last Bit Clock Enabled.\r
+ (#) Program the Smartcard interface using the USART_Init() function as \r
+ following:\r
+ (++) Word Length = 9 Bits.\r
+ (++) 1.5 Stop Bit.\r
+ (++) Even parity.\r
+ (++) BaudRate = 12096 baud.\r
+ (++) Hardware flow control disabled (RTS and CTS signals).\r
+ (++) Tx and Rx enabled\r
+ (#) Optionally you can enable the parity error interrupt using \r
+ the USART_ITConfig() function.\r
+ (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.\r
+ (#) Enable the Smartcard interface using the USART_SmartCardCmd() function.\r
+ (#) Enable the USART using the USART_Cmd() function.\r
+ [..] \r
+ Please refer to the ISO 7816-3 specification for more details.\r
+ [..] \r
+ (@) It is also possible to choose 0.5 stop bit for receiving but it is \r
+ recommended to use 1.5 stop bits for both transmitting and receiving \r
+ to avoid switching between the two configurations.\r
+ (@) In smartcard mode, the following bits must be kept cleared:\r
+ (+@) LINEN bit in the USART_CR2 register.\r
+ (+@) HDSEL and IREN bits in the USART_CR3 register.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the specified USART guard time.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param USART_GuardTime: specifies the guard time.\r
+ * @retval None\r
+ */\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx));\r
+\r
+ /* Clear the USART Guard time */\r
+ USARTx->GTPR &= USART_GTPR_PSC;\r
+ /* Set the USART guard time */\r
+ USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's Smart Card mode.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param NewState: new state of the Smart Card mode.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_SCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SC mode by clearing the SCEN bit in the CR3 register */\r
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables NACK transmission.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param NewState: new state of the NACK transmission.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the NACK transmission by setting the NACK bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_NACK;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */\r
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_NACK);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the Smart Card number of retries in transmit and receive.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param USART_AutoCount: specifies the Smart Card auto retry count.\r
+ * @retval None\r
+ */\r
+void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx));\r
+ assert_param(IS_USART_AUTO_RETRY_COUNTER(USART_AutoCount));\r
+ /* Clear the USART auto retry count */\r
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCARCNT);\r
+ /* Set the USART auto retry count*/\r
+ USARTx->CR3 |= (uint32_t)((uint32_t)USART_AutoCount << 0x11);\r
+}\r
+\r
+/**\r
+ * @brief Sets the Smart Card Block length.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param USART_BlockLength: specifies the Smart Card block length.\r
+ * @retval None\r
+ */\r
+void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx));\r
+\r
+ /* Clear the Smart card block length */\r
+ USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_BLEN);\r
+ /* Set the Smart Card block length */\r
+ USARTx->RTOR |= (uint32_t)((uint32_t)USART_BlockLength << 0x18);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group9 IrDA mode functions\r
+ * @brief IrDA mode functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IrDA mode functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage the USART\r
+ IrDA communication.\r
+ [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, \r
+ any data on the IrDA receive line will be ignored by the IrDA decoder \r
+ and if the Receiver is busy, data on the TX from the USART to IrDA will \r
+ not be encoded by IrDA. While receiving data, transmission should be \r
+ avoided as the data to be transmitted could be corrupted.\r
+ [..] IrDA communication is possible through the following procedure:\r
+ (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, \r
+ Transmitter/Receiver modes and hardware flow control values using \r
+ the USART_Init() function.\r
+ (#) Configures the IrDA pulse width by configuring the prescaler using \r
+ the USART_SetPrescaler() function.\r
+ (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal \r
+ mode using the USART_IrDAConfig() function.\r
+ (#) Enable the IrDA using the USART_IrDACmd() function.\r
+ (#) Enable the USART using the USART_Cmd() function. \r
+ [..]\r
+ (@) A pulse of width less than two and greater than one PSC period(s) may or \r
+ may not be rejected.\r
+ (@) The receiver set up time should be managed by software. The IrDA physical \r
+ layer specification specifies a minimum of 10 ms delay between \r
+ transmission and reception (IrDA is a half duplex protocol).\r
+ (@) In IrDA mode, the following bits must be kept cleared:\r
+ (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.\r
+ (+@) SCEN and HDSEL bits in the USART_CR3 register.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the USART's IrDA interface.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param USART_IrDAMode: specifies the IrDA mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IrDAMode_LowPower\r
+ * @arg USART_IrDAMode_Normal\r
+ * @retval None\r
+ */\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx));\r
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));\r
+\r
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IRLP);\r
+ USARTx->CR3 |= USART_IrDAMode;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's IrDA interface.\r
+ * @param USARTx: where x can be 1 to select the USART peripheral.\r
+ * @param NewState: new state of the IrDA mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_IREN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IREN);\r
+ }\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group10 RS485 mode function\r
+ * @brief RS485 mode function \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### RS485 mode functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to manage the USART\r
+ RS485 flow control.\r
+ [..] RS485 flow control (Driver enable feature) handling is possible through\r
+ the following procedure:\r
+ (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, \r
+ Transmitter/Receiver modes and hardware flow control values using \r
+ the USART_Init() function.\r
+ (#) Enable the Driver Enable using the USART_DECmd() function.\r
+ (#) Configures the Driver Enable polarity using the USART_DEPolarityConfig()\r
+ function.\r
+ (#) Configures the Driver Enable assertion time using USART_SetDEAssertionTime() \r
+ function and deassertion time using the USART_SetDEDeassertionTime()\r
+ function. \r
+ (#) Enable the USART using the USART_Cmd() function.\r
+ -@- \r
+ (+@) The assertion and dessertion times are expressed in sample time units (1/8 or \r
+ 1/16 bit time, depending on the oversampling rate).\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the USART's DE functionality.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param NewState: new state of the driver enable mode.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DE functionality by setting the DEM bit in the CR3 register */\r
+ USARTx->CR3 |= USART_CR3_DEM;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DE functionality by clearing the DEM bit in the CR3 register */\r
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEM);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the USART's DE polarity\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_DEPolarity: specifies the DE polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_DEPolarity_Low\r
+ * @arg USART_DEPolarity_High\r
+ * @retval None\r
+ */\r
+void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DE_POLARITY(USART_DEPolarity));\r
+\r
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEP);\r
+ USARTx->CR3 |= USART_DEPolarity;\r
+}\r
+\r
+/**\r
+ * @brief Sets the specified RS485 DE assertion time\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_AssertionTime: specifies the time between the activation of the DE\r
+ * signal and the beginning of the start bit\r
+ * @retval None\r
+ */\r
+void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEAssertionTime)); \r
+\r
+ /* Clear the DE assertion time */\r
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEAT);\r
+ /* Set the new value for the DE assertion time */\r
+ USARTx->CR1 |=((uint32_t)USART_DEAssertionTime << (uint32_t)0x15);\r
+}\r
+\r
+/**\r
+ * @brief Sets the specified RS485 DE deassertion time\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_DeassertionTime: specifies the time between the middle of the last \r
+ * stop bit in a transmitted message and the de-activation of the DE signal\r
+ * @retval None\r
+ */\r
+void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEDeassertionTime)); \r
+\r
+ /* Clear the DE deassertion time */\r
+ USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEDT);\r
+ /* Set the new value for the DE deassertion time */\r
+ USARTx->CR1 |=((uint32_t)USART_DEDeassertionTime << (uint32_t)0x10);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Group11 DMA transfers management functions\r
+ * @brief DMA transfers management functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### DMA transfers management functions #####\r
+ ===============================================================================\r
+ [..] This section provides two functions that can be used only in DMA mode.\r
+ [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel \r
+ requests:\r
+ (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request.\r
+ (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request.\r
+ [..] In this Mode it is advised to use the following function:\r
+ (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, \r
+ FunctionalState NewState).\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the USART's DMA interface.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_DMAReq: specifies the DMA request.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_DMAReq_Tx: USART DMA transmit request\r
+ * @arg USART_DMAReq_Rx: USART DMA receive request\r
+ * @param NewState: new state of the DMA Request sources.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DMAREQ(USART_DMAReq)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 |= USART_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 &= (uint32_t)~USART_DMAReq;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's DMA interface when reception error occurs.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_DMAOnError: specifies the DMA status in case of reception error.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_DMAOnError_Enable: DMA receive request enabled when the USART DMA \r
+ * reception error is asserted.\r
+ * @arg USART_DMAOnError_Disable: DMA receive request disabled when the USART DMA \r
+ * reception error is asserted.\r
+ * @retval None\r
+ */\r
+void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DMAONERROR(USART_DMAOnError)); \r
+ \r
+ /* Clear the DMA Reception error detection bit */\r
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DDRE);\r
+ /* Set the new value for the DMA Reception error detection bit */\r
+ USARTx->CR3 |= USART_DMAOnError;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup USART_Group12 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to configure the \r
+ USART Interrupts sources, Requests and check or clear the flags or pending bits status. \r
+ The user should identify which mode will be used in his application to \r
+ manage the communication: Polling mode, Interrupt mode.\r
+\r
+ *** Polling Mode ***\r
+ ====================\r
+ [..] In Polling Mode, the SPI communication can be managed by these flags:\r
+ (#) USART_FLAG_REACK: to indicate the status of the Receive Enable \r
+ acknowledge flag\r
+ (#) USART_FLAG_TEACK: to indicate the status of the Transmit Enable \r
+ acknowledge flag.\r
+ (#) USART_FLAG_WUF: to indicate the status of the Wake up flag.\r
+ (#) USART_FLAG_RWU: to indicate the status of the Receive Wake up flag.\r
+ (#) USART_FLAG_SBK: to indicate the status of the Send Break flag.\r
+ (#) USART_FLAG_CMF: to indicate the status of the Character match flag.\r
+ (#) USART_FLAG_BUSY: to indicate the status of the Busy flag.\r
+ (#) USART_FLAG_ABRF: to indicate the status of the Auto baud rate flag.\r
+ (#) USART_FLAG_ABRE: to indicate the status of the Auto baud rate error flag.\r
+ (#) USART_FLAG_EOBF: to indicate the status of the End of block flag.\r
+ (#) USART_FLAG_RTOF: to indicate the status of the Receive time out flag.\r
+ (#) USART_FLAG_nCTSS: to indicate the status of the Inverted nCTS input \r
+ bit status.\r
+ (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register.\r
+ (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register.\r
+ (#) USART_FLAG_TC: to indicate the status of the transmit operation.\r
+ (#) USART_FLAG_IDLE: to indicate the status of the Idle Line.\r
+ (#) USART_FLAG_CTS: to indicate the status of the nCTS input.\r
+ (#) USART_FLAG_LBD: to indicate the status of the LIN break detection.\r
+ (#) USART_FLAG_NE: to indicate if a noise error occur.\r
+ (#) USART_FLAG_FE: to indicate if a frame error occur.\r
+ (#) USART_FLAG_PE: to indicate if a parity error occur.\r
+ (#) USART_FLAG_ORE: to indicate if an Overrun error occur.\r
+ [..] In this Mode it is advised to use the following functions:\r
+ (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG).\r
+ (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG).\r
+\r
+ *** Interrupt Mode ***\r
+ ======================\r
+ [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt \r
+ sources and 10 pending bits:\r
+ (+) Pending Bits:\r
+ (##) USART_IT_WU: to indicate the status of the Wake up interrupt.\r
+ (##) USART_IT_CM: to indicate the status of Character match interrupt.\r
+ (##) USART_IT_EOB: to indicate the status of End of block interrupt.\r
+ (##) USART_IT_RTO: to indicate the status of Receive time out interrupt.\r
+ (##) USART_IT_CTS: to indicate the status of CTS change interrupt.\r
+ (##) USART_IT_LBD: to indicate the status of LIN Break detection interrupt.\r
+ (##) USART_IT_TC: to indicate the status of Transmission complete interrupt.\r
+ (##) USART_IT_IDLE: to indicate the status of IDLE line detected interrupt.\r
+ (##) USART_IT_ORE: to indicate the status of OverRun Error interrupt.\r
+ (##) USART_IT_NE: to indicate the status of Noise Error interrupt.\r
+ (##) USART_IT_FE: to indicate the status of Framing Error interrupt.\r
+ (##) USART_IT_PE: to indicate the status of Parity Error interrupt. \r
+\r
+ (+) Interrupt Source:\r
+ (##) USART_IT_WU: specifies the interrupt source for Wake up interrupt.\r
+ (##) USART_IT_CM: specifies the interrupt source for Character match \r
+ interrupt.\r
+ (##) USART_IT_EOB: specifies the interrupt source for End of block\r
+ interrupt.\r
+ (##) USART_IT_RTO: specifies the interrupt source for Receive time-out\r
+ interrupt.\r
+ (##) USART_IT_CTS: specifies the interrupt source for CTS change interrupt.\r
+ (##) USART_IT_LBD: specifies the interrupt source for LIN Break \r
+ detection interrupt.\r
+ (##) USART_IT_TXE: specifies the interrupt source for Tansmit Data \r
+ Register empty interrupt.\r
+ (##) USART_IT_TC: specifies the interrupt source for Transmission \r
+ complete interrupt.\r
+ (##) USART_IT_RXNE: specifies the interrupt source for Receive Data \r
+ register not empty interrupt.\r
+ (##) USART_IT_IDLE: specifies the interrupt source for Idle line \r
+ detection interrupt.\r
+ (##) USART_IT_PE: specifies the interrupt source for Parity Error interrupt.\r
+ (##) USART_IT_ERR: specifies the interrupt source for Error interrupt\r
+ (Frame error, noise error, overrun error)\r
+ -@@- Some parameters are coded in order to use them as interrupt \r
+ source or as pending bits.\r
+ [..] In this Mode it is advised to use the following functions:\r
+ (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState).\r
+ (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT).\r
+ (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT).\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified USART interrupts.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_WU: Wake up interrupt.\r
+ * @arg USART_IT_CM: Character match interrupt.\r
+ * @arg USART_IT_EOB: End of block interrupt.\r
+ * @arg USART_IT_RTO: Receive time out interrupt.\r
+ * @arg USART_IT_CTS: CTS change interrupt.\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt.\r
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt.\r
+ * @arg USART_IT_TC: Transmission complete interrupt.\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt.\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt.\r
+ * @arg USART_IT_PE: Parity Error interrupt.\r
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @param NewState: new state of the specified USARTx interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState)\r
+{\r
+ uint32_t usartreg = 0, itpos = 0, itmask = 0;\r
+ uint32_t usartxbase = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CONFIG_IT(USART_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ usartxbase = (uint32_t)USARTx;\r
+ \r
+ /* Get the USART register index */\r
+ usartreg = (((uint16_t)USART_IT) >> 0x08);\r
+ \r
+ /* Get the interrupt position */\r
+ itpos = USART_IT & IT_MASK;\r
+ itmask = (((uint32_t)0x01) << itpos);\r
+ \r
+ if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ usartxbase += 0x04;\r
+ }\r
+ else if (usartreg == 0x03) /* The IT is in CR3 register */\r
+ {\r
+ usartxbase += 0x08;\r
+ }\r
+ else /* The IT is in CR1 register */\r
+ {\r
+ }\r
+ if (NewState != DISABLE)\r
+ {\r
+ *(__IO uint32_t*)usartxbase |= itmask;\r
+ }\r
+ else\r
+ {\r
+ *(__IO uint32_t*)usartxbase &= ~itmask;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the specified USART's Request.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_Request: specifies the USART request.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_Request_TXFRQ: Transmit data flush ReQuest\r
+ * @arg USART_Request_RXFRQ: Receive data flush ReQuest\r
+ * @arg USART_Request_MMRQ: Mute Mode ReQuest\r
+ * @arg USART_Request_SBKRQ: Send Break ReQuest\r
+ * @arg USART_Request_ABRRQ: Auto Baud Rate ReQuest\r
+ * @param NewState: new state of the DMA interface when reception error occurs.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_REQUEST(USART_Request));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the USART ReQuest by setting the dedicated request bit in the RQR\r
+ register.*/\r
+ USARTx->RQR |= USART_Request;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the USART ReQuest by clearing the dedicated request bit in the RQR\r
+ register.*/\r
+ USARTx->RQR &= (uint32_t)~USART_Request;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's Overrun detection.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_OVRDetection: specifies the OVR detection status in case of OVR error.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_OVRDetection_Enable: OVR error detection enabled when the USART OVR error \r
+ * is asserted.\r
+ * @arg USART_OVRDetection_Disable: OVR error detection disabled when the USART OVR error \r
+ * is asserted.\r
+ * @retval None\r
+ */\r
+void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_OVRDETECTION(USART_OVRDetection));\r
+ \r
+ /* Clear the OVR detection bit */\r
+ USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_OVRDIS);\r
+ /* Set the new value for the OVR detection bit */\r
+ USARTx->CR3 |= USART_OVRDetection;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified USART flag is set or not.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_FLAG_REACK: Receive Enable acknowledge flag.\r
+ * @arg USART_FLAG_TEACK: Transmit Enable acknowledge flag.\r
+ * @arg USART_FLAG_WUF: Wake up flag.\r
+ * @arg USART_FLAG_RWU: Receive Wake up flag.\r
+ * @arg USART_FLAG_SBK: Send Break flag.\r
+ * @arg USART_FLAG_CMF: Character match flag.\r
+ * @arg USART_FLAG_BUSY: Busy flag.\r
+ * @arg USART_FLAG_ABRF: Auto baud rate flag.\r
+ * @arg USART_FLAG_ABRE: Auto baud rate error flag.\r
+ * @arg USART_FLAG_EOBF: End of block flag.\r
+ * @arg USART_FLAG_RTOF: Receive time out flag.\r
+ * @arg USART_FLAG_nCTSS: Inverted nCTS input bit status.\r
+ * @arg USART_FLAG_CTS: CTS Change flag.\r
+ * @arg USART_FLAG_LBD: LIN Break detection flag.\r
+ * @arg USART_FLAG_TXE: Transmit data register empty flag.\r
+ * @arg USART_FLAG_TC: Transmission Complete flag.\r
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.\r
+ * @arg USART_FLAG_IDLE: Idle Line detection flag.\r
+ * @arg USART_FLAG_ORE: OverRun Error flag.\r
+ * @arg USART_FLAG_NE: Noise Error flag.\r
+ * @arg USART_FLAG_FE: Framing Error flag.\r
+ * @arg USART_FLAG_PE: Parity Error flag.\r
+ * @retval The new state of USART_FLAG (SET or RESET).\r
+ */\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_FLAG(USART_FLAG));\r
+ \r
+ if ((USARTx->ISR & USART_FLAG) != (uint16_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the USARTx's pending flags.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_FLAG_WUF: Wake up flag.\r
+ * @arg USART_FLAG_CMF: Character match flag.\r
+ * @arg USART_FLAG_EOBF: End of block flag.\r
+ * @arg USART_FLAG_RTOF: Receive time out flag.\r
+ * @arg USART_FLAG_CTS: CTS Change flag.\r
+ * @arg USART_FLAG_LBD: LIN Break detection flag.\r
+ * @arg USART_FLAG_TC: Transmission Complete flag.\r
+ * @arg USART_FLAG_IDLE: IDLE line detected flag.\r
+ * @arg USART_FLAG_ORE: OverRun Error flag.\r
+ * @arg USART_FLAG_NE: Noise Error flag.\r
+ * @arg USART_FLAG_FE: Framing Error flag.\r
+ * @arg USART_FLAG_PE: Parity Errorflag.\r
+ * \r
+ * @note\r
+ * - RXNE pending bit is cleared by a read to the USART_RDR register \r
+ * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register USART_RQR\r
+ * (USART_RequestCmd()).\r
+ * - TC flag can be also cleared by software sequence: a read operation to \r
+ * USART_SR register (USART_GetFlagStatus()) followed by a write operation\r
+ * to USART_TDR register (USART_SendData()).\r
+ * - TXE flag is cleared by a write to the USART_TDR register \r
+ * (USART_SendData()) or by writing 1 to the TXFRQ in the register USART_RQR\r
+ * (USART_RequestCmd()).\r
+ * - SBKF flag is cleared by 1 to the SBKRQ in the register USART_RQR\r
+ * (USART_RequestCmd()).\r
+ * @retval None\r
+ */\r
+void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));\r
+ \r
+ USARTx->ICR = USART_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified USART interrupt has occurred or not.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_IT: specifies the USART interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_WU: Wake up interrupt.\r
+ * @arg USART_IT_CM: Character match interrupt.\r
+ * @arg USART_IT_EOB: End of block interrupt.\r
+ * @arg USART_IT_RTO: Receive time out interrupt.\r
+ * @arg USART_IT_CTS: CTS change interrupt.\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt.\r
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt.\r
+ * @arg USART_IT_TC: Transmission complete interrupt.\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt.\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt.\r
+ * @arg USART_IT_ORE: OverRun Error interrupt.\r
+ * @arg USART_IT_NE: Noise Error interrupt.\r
+ * @arg USART_IT_FE: Framing Error interrupt.\r
+ * @arg USART_IT_PE: Parity Error interrupt.\r
+ * @retval The new state of USART_IT (SET or RESET).\r
+ */\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT)\r
+{\r
+ uint32_t bitpos = 0, itmask = 0, usartreg = 0;\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_GET_IT(USART_IT)); \r
+ \r
+ /* Get the USART register index */\r
+ usartreg = (((uint16_t)USART_IT) >> 0x08);\r
+ /* Get the interrupt position */\r
+ itmask = USART_IT & IT_MASK;\r
+ itmask = (uint32_t)0x01 << itmask;\r
+ \r
+ if (usartreg == 0x01) /* The IT is in CR1 register */\r
+ {\r
+ itmask &= USARTx->CR1;\r
+ }\r
+ else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ itmask &= USARTx->CR2;\r
+ }\r
+ else /* The IT is in CR3 register */\r
+ {\r
+ itmask &= USARTx->CR3;\r
+ }\r
+ \r
+ bitpos = USART_IT >> 0x10;\r
+ bitpos = (uint32_t)0x01 << bitpos;\r
+ bitpos &= USARTx->ISR;\r
+ if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Clears the USARTx's interrupt pending bits.\r
+ * @param USARTx: where x can be 1 or 2 to select the USART peripheral.\r
+ * @param USART_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_WU: Wake up interrupt.\r
+ * @arg USART_IT_CM: Character match interrupt.\r
+ * @arg USART_IT_EOB: End of block interrupt.\r
+ * @arg USART_IT_RTO: Receive time out interrupt.\r
+ * @arg USART_IT_CTS: CTS change interrupt.\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt.\r
+ * @arg USART_IT_TC: Transmission complete interrupt.\r
+ * @arg USART_IT_IDLE: IDLE line detected interrupt.\r
+ * @arg USART_IT_ORE: OverRun Error interrupt.\r
+ * @arg USART_IT_NE: Noise Error interrupt.\r
+ * @arg USART_IT_FE: Framing Error interrupt.\r
+ * @arg USART_IT_PE: Parity Error interrupt.\r
+ * @note\r
+ * - RXNE pending bit is cleared by a read to the USART_RDR register \r
+ * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register USART_RQR\r
+ * (USART_RequestCmd()).\r
+ * - TC pending bit can be also cleared by software sequence: a read \r
+ * operation to USART_SR register (USART_GetITStatus()) followed by a write \r
+ * operation to USART_TDR register (USART_SendData()).\r
+ * - TXE pending bit is cleared by a write to the USART_TDR register \r
+ * (USART_SendData()) or by writing 1 to the TXFRQ in the register USART_RQR\r
+ * (USART_RequestCmd()).\r
+ * @retval None\r
+ */\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT)\r
+{\r
+ uint32_t bitpos = 0, itmask = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLEAR_IT(USART_IT)); \r
+ \r
+ bitpos = USART_IT >> 0x10;\r
+ itmask = ((uint32_t)0x01 << (uint32_t)bitpos);\r
+ USARTx->ICR = (uint32_t)itmask;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f0xx_wwdg.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0RC1\r
+ * @date 27-January-2012\r
+ * @brief This file provides firmware functions to manage the following \r
+ * functionalities of the Window watchdog (WWDG) peripheral:\r
+ * + Prescaler, Refresh window and Counter configuration\r
+ * + WWDG activation\r
+ * + Interrupts and flags management\r
+ * \r
+ * @verbatim\r
+ * \r
+ ============================================================================== \r
+ ##### WWDG features ##### \r
+ ============================================================================== \r
+ [..] Once enabled the WWDG generates a system reset on expiry of a programmed\r
+ time period, unless the program refreshes the counter (downcounter) \r
+ before to reach 0x3F value (i.e. a reset is generated when the counter\r
+ value rolls over from 0x40 to 0x3F). \r
+ [..] An MCU reset is also generated if the counter value is refreshed\r
+ before the counter has reached the refresh window value. This \r
+ implies that the counter must be refreshed in a limited window.\r
+\r
+ [..] Once enabled the WWDG cannot be disabled except by a system reset.\r
+\r
+ [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG\r
+ reset occurs.\r
+\r
+ [..] The WWDG counter input clock is derived from the APB clock divided \r
+ by a programmable prescaler.\r
+\r
+ [..] WWDG counter clock = PCLK1 / Prescaler.\r
+ [..] WWDG timeout = (WWDG counter clock) * (counter value).\r
+\r
+ [..] Min-max timeout value @32MHz (PCLK1): ~85us / ~43ms.\r
+\r
+ ##### How to use this driver ##### \r
+ ==============================================================================\r
+ [..]\r
+ (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) \r
+ function.\r
+ \r
+ (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.\r
+ \r
+ (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.\r
+ \r
+ (#) Set the WWDG counter value and start it using WWDG_Enable() function.\r
+ When the WWDG is enabled the counter value should be configured to \r
+ a value greater than 0x40 to prevent generating an immediate reset.\r
+ \r
+ (#) Optionally you can enable the Early wakeup interrupt which is \r
+ generated when the counter reach 0x40.\r
+ Once enabled this interrupt cannot be disabled except by a system reset.\r
+ \r
+ (#) Then the application program must refresh the WWDG counter at regular\r
+ intervals during normal operation to prevent an MCU reset, using\r
+ WWDG_SetCounter() function. This operation must occur only when\r
+ the counter value is lower than the refresh window value, \r
+ programmed using WWDG_SetWindowValue().\r
+ \r
+ * @endverbatim\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f0xx_wwdg.h"\r
+#include "stm32f0xx_rcc.h"\r
+\r
+/** @addtogroup STM32F0xx_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG \r
+ * @brief WWDG driver modules\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* --------------------- WWDG registers bit mask ---------------------------- */\r
+/* CFR register bit mask */\r
+#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)\r
+#define CFR_W_MASK ((uint32_t)0xFFFFFF80)\r
+#define BIT_MASK ((uint8_t)0x7F)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup WWDG_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions\r
+ * @brief Prescaler, Refresh window and Counter configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Prescaler, Refresh window and Counter configuration functions #####\r
+ ============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the WWDG peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG Prescaler.\r
+ * @param WWDG_Prescaler: specifies the WWDG Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1\r
+ * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2\r
+ * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4\r
+ * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8\r
+ * @retval None\r
+ */\r
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));\r
+ /* Clear WDGTB[1:0] bits */\r
+ tmpreg = WWDG->CFR & CFR_WDGTB_MASK;\r
+ /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */\r
+ tmpreg |= WWDG_Prescaler;\r
+ /* Store the new value */\r
+ WWDG->CFR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG window value.\r
+ * @param WindowValue: specifies the window value to be compared to the downcounter.\r
+ * This parameter value must be lower than 0x80.\r
+ * @retval None\r
+ */\r
+void WWDG_SetWindowValue(uint8_t WindowValue)\r
+{\r
+ __IO uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));\r
+ /* Clear W[6:0] bits */\r
+\r
+ tmpreg = WWDG->CFR & CFR_W_MASK;\r
+\r
+ /* Set W[6:0] bits according to WindowValue value */\r
+ tmpreg |= WindowValue & (uint32_t) BIT_MASK;\r
+\r
+ /* Store the new value */\r
+ WWDG->CFR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the WWDG Early Wakeup interrupt(EWI).\r
+ * @note Once enabled this interrupt cannot be disabled except by a system reset. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_EnableIT(void)\r
+{\r
+ WWDG->CFR |= WWDG_CFR_EWI;\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG counter value.\r
+ * @param Counter: specifies the watchdog counter value.\r
+ * This parameter must be a number between 0x40 and 0x7F (to prevent generating\r
+ * an immediate reset).\r
+ * @retval None\r
+ */\r
+void WWDG_SetCounter(uint8_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_COUNTER(Counter));\r
+ /* Write to T[6:0] bits to configure the counter value, no need to do\r
+ a read-modify-write; writing a 0 to WDGA bit does nothing */\r
+ WWDG->CR = Counter & BIT_MASK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Group2 WWDG activation functions\r
+ * @brief WWDG activation functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### WWDG activation function #####\r
+ ============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables WWDG and load the counter value. \r
+ * @param Counter: specifies the watchdog counter value.\r
+ * This parameter must be a number between 0x40 and 0x7F (to prevent generating\r
+ * an immediate reset).\r
+ * @retval None\r
+ */\r
+void WWDG_Enable(uint8_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_COUNTER(Counter));\r
+ WWDG->CR = WWDG_CR_WDGA | Counter;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Group3 Interrupts and flags management functions\r
+ * @brief Interrupts and flags management functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Interrupts and flags management functions #####\r
+ ============================================================================== \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the Early Wakeup interrupt flag is set or not.\r
+ * @param None\r
+ * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).\r
+ */\r
+FlagStatus WWDG_GetFlagStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ if ((WWDG->SR) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears Early Wakeup interrupt flag.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_ClearFlag(void)\r
+{\r
+ WWDG->SR = (uint32_t)RESET;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple GPIO (parallel port) IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Standard demo include. */\r
+#include "partest.h"\r
+\r
+/* Hardware includes. */\r
+#include "stm320518_eval.h"\r
+\r
+/* Only the LEDs on one of the two seven segment displays are used. */\r
+#define partstMAX_LEDS 4\r
+\r
+static const Led_TypeDef xLEDs[ partstMAX_LEDS ] = { LED1, LED2, LED3, LED4 };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Initialise all four LEDs that are built onto the starter kit. */\r
+ STM_EVAL_LEDInit( LED1 );\r
+ STM_EVAL_LEDInit( LED2 );\r
+ STM_EVAL_LEDInit( LED3 );\r
+ STM_EVAL_LEDInit( LED4 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned long ulLED, signed portBASE_TYPE xValue )\r
+{\r
+ if( ulLED < partstMAX_LEDS )\r
+ {\r
+ if( xValue == pdTRUE )\r
+ {\r
+ STM_EVAL_LEDOn( xLEDs[ ulLED ] );\r
+ }\r
+ else\r
+ {\r
+ STM_EVAL_LEDOff( xLEDs[ ulLED ] );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned long ulLED )\r
+{\r
+ if( ulLED < partstMAX_LEDS )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ STM_EVAL_LEDToggle( xLEDs[ ulLED ] );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>23</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>4.41A</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>STLINK_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>6.30.3.53229</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CLowLevel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCBE8Slave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CDevice</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoadersV3</name>\r
+ <state>$TOOLKIT_DIR$\config\flashloader\</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OverrideDefFlashBoard</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDeviceConfigMacroFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimEnablePSP</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspOverrideConfig</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspConfigFile</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>GDBSERVER_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>14</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>100</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>200</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadioV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCUSBDevice</name>\r
+ <version>1</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetList</name>\r
+ <version>6</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSourceDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>#UNINITIALIZED#</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>Browse to your RDI driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDIJTAGJET_ID</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JTAGjetConfigure</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>STLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>Browse to your third-party driver</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XDS100_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCXDS100AttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>21</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>19</version>\r
+ <state>34</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>3</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>Full formatting.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>2</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>Full formatting.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>2</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>4.41A</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>6.30.3.53229</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>Default None</state>\r
+ </option>\r
+ <option>\r
+ <name>GenLowLevelInterface</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianModeBE</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGBufferedTerminalOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenStdoutInterface</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>19</version>\r
+ <state>34</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>19</version>\r
+ <state>34</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>28</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state>USE_STM320518_EVAL</state>\r
+ <state>STM32F0XX</state>\r
+ <state>USE_STDPERIPH_DRIVER</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state>Pa082</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>1</version>\r
+ <state>0000000</state>\r
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+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IEndianMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangConformance</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSignedPlainChar</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>$FILE_BNAME$.o</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIncludePath2</name>\r
+ <state>$PROJ_DIR$\Libraries\STM32F0xx_StdPeriph_Driver\inc</state>\r
+ <state>$PROJ_DIR$\Libraries\CMSIS\Device\ST\STM32F0xx\Include</state>\r
+ <state>$PROJ_DIR$\Libraries\CMSIS\Include</state>\r
+ <state>$PROJ_DIR$\Eval-Board</state>\r
+ <state>$PROJ_DIR$</state>\r
+ <state>$PROJ_DIR$\..\..\Source\include</state>\r
+ <state>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM0</state>\r
+ <state>$PROJ_DIR$\..\Common\include</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCodeSection</name>\r
+ <state>.text</state>\r
+ </option>\r
+ <option>\r
+ <name>IInterwork2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessorMode2</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptStrategy</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevelSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRopi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRwpi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndNoDynInit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLang</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccAllowVLA</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccExceptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccRTTI</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccStaticDestr</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppInlineSemantics</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>AARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>8</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>AObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ACaseSensitivity</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacroChars</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnWhat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnOne</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ADebug</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AltRegisterNames</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ADefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AListHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AListing</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Includes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacDefs</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExps</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExec</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OnlyAssed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MultiLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>TabSpacing</name>\r
+ <state>8</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDefines</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefInternal</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDual</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AOutputFile</name>\r
+ <state>$FILE_BNAME$.o</state>\r
+ </option>\r
+ <option>\r
+ <name>AMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsEdit</name>\r
+ <state>100</state>\r
+ </option>\r
+ <option>\r
+ <name>AIgnoreStdInclude</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AUserIncludes</name>\r
+ <state>$PROJ_DIR$</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsCheckV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsV2</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>OBJCOPY</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OOCOutputFormat</name>\r
+ <version>2</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>OCOutputOverride</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCOutputFile</name>\r
+ <state>RTOSDemo.bin</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCCommandLineProducer</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCObjCopyEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CUSTOM</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ <settings>\r
+ <name>BUILDACTION</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <prebuild></prebuild>\r
+ <postbuild></postbuild>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>14</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>IlinkLibIOConfig</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XLinkMisraHandler</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkInputFileSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOutputFile</name>\r
+ <state>RTOSDemo.out</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkDebugInfoEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkKeepSymbols</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinaryFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinarySymbol</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinarySegment</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinaryAlign</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkConfigDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkMapFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogInitialization</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogModule</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogSection</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogVeneer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfOverride</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfFile</name>\r
+ <state>$PROJ_DIR$\stm32f0xx_flash.icf</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfFileSlave</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkSuppressDiags</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsRem</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsWarn</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsErr</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkWarningsAreErrors</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkUseExtraOptions</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLowLevelInterfaceSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkAutoLibEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkAdditionalLibs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOverrideProgramEntryLabel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkProgramEntryLabelSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkProgramEntryLabel</name>\r
+ <state>__iar_program_start</state>\r
+ </option>\r
+ <option>\r
+ <name>DoFill</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerByte</name>\r
+ <state>0xFF</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerStart</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerEnd</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcSize</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlgo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcPoly</name>\r
+ <state>0x11021</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcCompl</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcBitOrder</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcInitialValue</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoCrc</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkBE8Slave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkBufferedTerminalOutput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStdoutInterfaceSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcFullSize</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIElfToolPostProcess</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogAutoLibSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogRedirSymbols</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogUnusedFragments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcReverseByteOrder</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcUseAsInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptInline</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsAllow</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptExceptionsForce</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStackAnalysisEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStackControlFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStackCallGraphFile</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARCHIVE</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>IarchiveInputs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOutput</name>\r
+ <state>###Unitialized###</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ </configuration>\r
+ <group>\r
+ <name>Eval-Board</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\Eval-Board\stm320518_eval.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>FreeRTOS</name>\r
+ <group>\r
+ <name>Portable</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM0\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM0\portasm.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM0\portmacro.h</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\timers.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Libraries</name>\r
+ <group>\r
+ <name>CMSIS</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\Libraries\CMSIS\Device\ST\STM32F0xx\Source\Templates\system_stm32f0xx.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>StdPeriph_Driver</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_gpio.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_rcc.c</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+ <group>\r
+ <name>Standard-Demo-Tasks</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\countsem.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\dynamic.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\recmutex.c</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\FreeRTOSConfig.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main-blinky.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main-full.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\main.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\ParTest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\RegTest.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\startup_stm32f0xx.s</name>\r
+ </file>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+ </project>\r
+ <batchBuild/>\r
+</workspace>\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+ RSEG CODE:CODE(2)\r
+ thumb\r
+\r
+ EXTERN ulRegTest1LoopCounter\r
+ EXTERN ulRegTest2LoopCounter\r
+\r
+ PUBLIC vRegTest1Task\r
+ PUBLIC vRegTest2Task\r
+\r
+/*-----------------------------------------------------------*/\r
+vRegTest1Task\r
+\r
+ /* Fill the core registers with known values. This is only done once. */\r
+ movs r1, #101\r
+ movs r2, #102\r
+ movs r3, #103\r
+ movs r4, #104\r
+ movs r5, #105\r
+ movs r6, #106\r
+ movs r7, #107\r
+ movs r0, #108\r
+ mov r8, r0\r
+ movs r0, #109\r
+ mov r9, r0\r
+ movs r0, #110\r
+ mov r10, r0\r
+ movs r0, #111\r
+ mov r11, r0\r
+ movs r0, #112\r
+ mov r12, r0\r
+ movs r0, #100\r
+\r
+reg1_loop\r
+ /* Repeatedly check that each register still contains the value written to\r
+ it when the task started. */\r
+ cmp r0, #100\r
+ bne reg1_error_loop\r
+ cmp r1, #101\r
+ bne reg1_error_loop\r
+ cmp r2, #102\r
+ bne reg1_error_loop\r
+ cmp r3, #103\r
+ bne reg1_error_loop\r
+ cmp r4, #104\r
+ bne reg1_error_loop\r
+ cmp r5, #105\r
+ bne reg1_error_loop\r
+ cmp r6, #106\r
+ bne reg1_error_loop\r
+ cmp r7, #107\r
+ bne reg1_error_loop\r
+ movs r0, #108\r
+ cmp r8, r0\r
+ bne reg1_error_loop\r
+ movs r0, #109\r
+ cmp r9, r0\r
+ bne reg1_error_loop\r
+ movs r0, #110\r
+ cmp r10, r0\r
+ bne reg1_error_loop\r
+ movs r0, #111\r
+ cmp r11, r0\r
+ bne reg1_error_loop\r
+ movs r0, #112\r
+ cmp r12, r0\r
+ bne reg1_error_loop\r
+\r
+ /* Everything passed, increment the loop counter. */\r
+ push { r1 }\r
+ ldr r0, =ulRegTest1LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r1 }\r
+\r
+ /* Start again. */\r
+ movs r0, #100\r
+ b reg1_loop\r
+\r
+reg1_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ b reg1_error_loop\r
+ nop\r
+\r
+\r
+\r
+vRegTest2Task\r
+\r
+ /* Fill the core registers with known values. This is only done once. */\r
+ movs r1, #1\r
+ movs r2, #2\r
+ movs r3, #3\r
+ movs r4, #4\r
+ movs r5, #5\r
+ movs r6, #6\r
+ movs r7, #7\r
+ movs r0, #8\r
+ mov r8, r0\r
+ movs r0, #9\r
+ mov r9, r0\r
+ movs r0, #10\r
+ mov r10, r0\r
+ movs r0, #11\r
+ mov r11, r0\r
+ movs r0, #12\r
+ mov r12, r0\r
+ movs r0, #10\r
+\r
+reg2_loop\r
+ /* Repeatedly check that each register still contains the value written to\r
+ it when the task started. */\r
+ cmp r0, #10\r
+ bne reg2_error_loop\r
+ cmp r1, #1\r
+ bne reg2_error_loop\r
+ cmp r2, #2\r
+ bne reg2_error_loop\r
+ cmp r3, #3\r
+ bne reg2_error_loop\r
+ cmp r4, #4\r
+ bne reg2_error_loop\r
+ cmp r5, #5\r
+ bne reg2_error_loop\r
+ cmp r6, #6\r
+ bne reg2_error_loop\r
+ cmp r7, #7\r
+ bne reg2_error_loop\r
+ movs r0, #8\r
+ cmp r8, r0\r
+ bne reg2_error_loop\r
+ movs r0, #9\r
+ cmp r9, r0\r
+ bne reg2_error_loop\r
+ movs r0, #10\r
+ cmp r10, r0\r
+ bne reg2_error_loop\r
+ movs r0, #11\r
+ cmp r11, r0\r
+ bne reg2_error_loop\r
+ movs r0, #12\r
+ cmp r12, r0\r
+ bne reg2_error_loop\r
+\r
+ /* Everything passed, increment the loop counter. */\r
+ push { r1 }\r
+ ldr r0, =ulRegTest2LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r1 }\r
+\r
+ /* Start again. */\r
+ movs r0, #10\r
+ b reg2_loop\r
+\r
+reg2_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ b reg2_error_loop\r
+ nop\r
+\r
+ END\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky(). Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky(). When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, toggles LED 1. The 'block\r
+ * time' parameter passed to the queue receive function specifies that the\r
+ * task should be held in the Blocked state indefinitely to wait for data to\r
+ * be available on the queue. The queue receive task will only leave the\r
+ * Blocked state when the queue send task writes to the queue. As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo includes. */\r
+#include "ParTest.h"\r
+\r
+/* Hardware includes. */\r
+#include "stm320518_eval.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_RATE_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* Values passed to the two tasks just to check the task parameter\r
+functionality. */\r
+#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )\r
+#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * Called by main() to create the simply blinky style application if\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*\r
+ * The hardware only has a single LED. Simply toggle it.\r
+ */\r
+extern void vMainToggleLED( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was insufficient FreeRTOS heap memory available for the idle and/or\r
+ timer tasks to be created. See the memory management section on the\r
+ FreeRTOS web site for more details. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Check the task parameter is as expected. */\r
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again.\r
+ The block time is specified in ticks, the constant used converts ticks\r
+ to ms. While in the Blocked state this task will not consume any CPU\r
+ time. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+ /* Check the task parameter is as expected. */\r
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == 100UL )\r
+ {\r
+ vParTestToggleLED( LED1 );\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the comprehensive test and demo version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_full() creates a set of standard demo tasks, some application specific\r
+ * tasks, and four timers. It then starts the scheduler. The web documentation\r
+ * provides more details of the standard demo application tasks, which provide\r
+ * no particular functionality, but do provide a good example of how to use the\r
+ * FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and timer are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill the registers with known values, then check\r
+ * that each register maintains its expected value for the lifetime of the\r
+ * task. Each task uses a different set of values. The reg test tasks execute\r
+ * with a very low priority, so get preempted very frequently. A register\r
+ * containing an unexpected value is indicative of an error in the context\r
+ * switching mechanism.\r
+ *\r
+ * "Flash timers" - A software timer callback function is defined that does\r
+ * nothing but toggle an LED. Three software timers are created that each\r
+ * use the same callback function, but each toggles a different LED at a\r
+ * different frequency. One software timer uses LED1, another LED2 and the\r
+ * third LED3.\r
+ *\r
+ * "Check" software timer - The check timer period is initially set to three\r
+ * seconds. Its callback function checks that all the standard demo tasks, and\r
+ * the register check tasks, are not only still executing, but are executing\r
+ * without reporting any errors. If the check timer callback discovers that a\r
+ * task has either stalled, or reported an error, then it changes the period of\r
+ * the check timer from the initial three seconds, to just 200ms. The callback\r
+ * function also toggles LED 4 each time it is called. This provides a visual\r
+ * indication of the system status: If the LED toggles every three seconds,\r
+ * then no issues have been discovered. If the LED toggles every 200ms, then\r
+ * an issue has been discovered with at least one task.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "timers.h"\r
+\r
+/* Common demo includes. */\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "recmutex.h"\r
+#include "ParTest.h"\r
+#include "dynamic.h"\r
+\r
+/* Hardware includes. */\r
+#include "stm320518_eval.h"\r
+\r
+/* The period after which the check timer will expire provided no errors have\r
+been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_RATE_MS constant. */\r
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the check timer will expire if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_RATE_MS constant. */\r
+#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The base toggle rate used by the flash timers. Each toggle rate is a\r
+multiple of this. */\r
+#define mainFLASH_TIMER_BASE_RATE ( 200UL / portTICK_RATE_MS )\r
+\r
+/* The LED toggle by the check timer. */\r
+#define mainCHECK_LED ( 3 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Register check tasks, as described at the top of this file. The nature of\r
+ * these files necessitates that they are written in an assembly.\r
+ */\r
+extern void vRegTest1Task( void *pvParameters );\r
+extern void vRegTest2Task( void *pvParameters );\r
+\r
+/*\r
+ * The hardware only has a single LED. Simply toggle it.\r
+ */\r
+extern void vMainToggleLED( void );\r
+\r
+/*\r
+ * The check timer callback function, as described at the top of this file.\r
+ */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer );\r
+\r
+/*\r
+ * The flash timer callback function, as described at the top of this file.\r
+ * This callback function is assigned to three separate software timers.\r
+ */\r
+static void prvFlashTimerCallback( xTimerHandle xTimer );\r
+\r
+/*\r
+ * Called by main() to create the comprehensive test/demo application if\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is not set to 1.\r
+ */\r
+void main_full( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The following two variables are used to communicate the status of the\r
+register check tasks to the check software timer. If the variables keep\r
+incrementing, then the register check tasks has not discovered any errors. If\r
+a variable stops incrementing, then an error has been found. */\r
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+xTimerHandle xTimer = NULL;\r
+unsigned long ulTimer;\r
+const unsigned long ulTimersToCreate = 3L;\r
+/* The register test tasks are asm functions that don't use a stack. The\r
+stack allocated just has to be large enough to hold the task context, and\r
+for the additional required for the stack overflow checking to work (if\r
+configured). */\r
+const size_t xRegTestStackSize = 25U;\r
+\r
+ /* Create the standard demo tasks */\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartRecursiveMutexTasks();\r
+ vStartDynamicPriorityTasks();\r
+\r
+ /* Create the register test tasks as described at the top of this file.\r
+ These are naked functions that don't use any stack. A stack still has\r
+ to be allocated to hold the task context. */\r
+ xTaskCreate( vRegTest1Task, /* Function that implements the task. */\r
+ ( signed char * ) "Reg1", /* Text name of the task. */\r
+ xRegTestStackSize, /* Stack allocated to the task. */\r
+ NULL, /* The task parameter is not used. */\r
+ tskIDLE_PRIORITY, /* The priority to assign to the task. */\r
+ NULL ); /* Don't receive a handle back, it is not needed. */\r
+\r
+ xTaskCreate( vRegTest2Task, /* Function that implements the task. */\r
+ ( signed char * ) "Reg2", /* Text name of the task. */\r
+ xRegTestStackSize, /* Stack allocated to the task. */\r
+ NULL, /* The task parameter is not used. */\r
+ tskIDLE_PRIORITY, /* The priority to assign to the task. */\r
+ NULL ); /* Don't receive a handle back, it is not needed. */\r
+\r
+ /* Create the three flash timers. */\r
+ for( ulTimer = 0UL; ulTimer < ulTimersToCreate; ulTimer++ )\r
+ {\r
+ xTimer = xTimerCreate( ( const signed char * ) "FlashTimer", /* A text name, purely to help debugging. */\r
+ ( mainFLASH_TIMER_BASE_RATE * ( ulTimer + 1UL ) ), /* The timer period, in this case 3000ms (3s). */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) ulTimer, /* The ID is used to hold the number of the LED that will be flashed. */\r
+ prvFlashTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
+ );\r
+ \r
+ if( xTimer != NULL )\r
+ {\r
+ xTimerStart( xTimer, mainDONT_BLOCK );\r
+ }\r
+ }\r
+ \r
+ /* Create the software timer that performs the 'check' functionality,\r
+ as described at the top of this file. */\r
+ xTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
+ );\r
+\r
+ /* If the software timer was created successfully, start it. It won't\r
+ actually start running until the scheduler starts. A block time of\r
+ zero is used in this call, although any value could be used as the block\r
+ time will be ignored because the scheduler has not started yet. */\r
+ if( xTimer != NULL )\r
+ {\r
+ xTimerStart( xTimer, mainDONT_BLOCK );\r
+ }\r
+\r
+ /* Start the kernel. From here on, only tasks and interrupts will run. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then there\r
+ was insufficient FreeRTOS heap memory available for the idle and/or timer\r
+ tasks to be created. See the memory management section on the FreeRTOS web\r
+ site, or the FreeRTOS tutorial books for more details. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the description at the top of this file. */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer )\r
+{\r
+static long lChangedTimerPeriodAlready = pdFALSE;\r
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Check all the demo and test tasks to ensure that they are all still\r
+ running, and that none have detected an error. */\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound |= ( 0x01UL << 0UL );\r
+ }\r
+\r
+ if( xAreBlockTimeTestTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound |= ( 0x01UL << 1UL );\r
+ }\r
+\r
+ if( xAreCountingSemaphoreTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound |= ( 0x01UL << 2UL );\r
+ }\r
+\r
+ if( xAreRecursiveMutexTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound |= ( 0x01UL << 3UL );\r
+ }\r
+\r
+ /* Check that the register test 1 task is still running. */\r
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
+ {\r
+ ulErrorFound |= ( 0x01UL << 4UL );\r
+ }\r
+ ulLastRegTest1Value = ulRegTest1LoopCounter;\r
+\r
+ /* Check that the register test 2 task is still running. */\r
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
+ {\r
+ ulErrorFound |= ( 0x01UL << 5UL );\r
+ }\r
+ ulLastRegTest2Value = ulRegTest2LoopCounter;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+\r
+ /* Have any errors been latched in ulErrorFound? If so, shorten the\r
+ period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.\r
+ This will result in an increase in the rate at which mainCHECK_LED\r
+ toggles. */\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ if( lChangedTimerPeriodAlready == pdFALSE )\r
+ {\r
+ lChangedTimerPeriodAlready = pdTRUE;\r
+\r
+ /* This call to xTimerChangePeriod() uses a zero block time.\r
+ Functions called from inside of a timer callback function must\r
+ *never* attempt to block. */\r
+ xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvFlashTimerCallback( xTimerHandle xTimer )\r
+{\r
+unsigned long ulLED;\r
+\r
+ /* This callback function is assigned to three separate software timers.\r
+ Each timer toggles a different LED. Obtain the number of the LED that\r
+ this timer is toggling. */\r
+ ulLED = ( unsigned long ) pvTimerGetTimerID( xTimer );\r
+\r
+ /* Toggle the LED. */\r
+ vParTestToggleLED( ulLED ); \r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project,\r
+ * and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
+ * select between the two. The simply blinky demo is implemented and described\r
+ * in main_blinky.c. The more comprehensive test and demo application is\r
+ * implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and FreeRTOS hook functions. It also contains a dummy\r
+ * interrupt service routine called Dummy_IRQHandler() that is provided as an\r
+ * example of how to use interrupt safe FreeRTOS API functions (those that end\r
+ * in "FromISR").\r
+ *\r
+ *****************************************************************************/\r
+\r
+\r
+/* Standard includes. */\r
+#include "string.h"\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application include. */\r
+#include "ParTest.h"\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive test and demo application. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Perform any application specific hardware configuration. The clocks,\r
+ * memory, etc. are configured before main() is called.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */\r
+void main_blinky( void );\r
+void main_full( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Prepare the hardware to run this demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+ of this file. */\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1\r
+ {\r
+ main_blinky();\r
+ }\r
+ #else\r
+ {\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* vApplicationMallocFailedHook() will only be called if\r
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ function that will get called if a call to pvPortMalloc() fails.\r
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+ timer or semaphore is created. It is also called by various parts of the\r
+ demo application. If heap_1.c or heap_2.c are used, then the size of the\r
+ heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+ FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+ to query the size of free heap space that remains (although it does not\r
+ provide information on how the remaining heap might be fragmented). */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
+ task. It is essential that code added to this hook function never attempts\r
+ to block in any way (for example, call xQueueReceive() with a block time\r
+ specified, or call vTaskDelay()). If the application makes use of the\r
+ vTaskDelete() API function (as this demo application does) then it is also\r
+ important that vApplicationIdleHook() is permitted to return to its calling\r
+ function, because it is the responsibility of the idle task to clean up\r
+ memory allocated by the kernel to any task that has since been deleted. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ /* This function will be called by each tick interrupt if\r
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
+ added here, but the tick hook is called from an interrupt context, so\r
+ code must not attempt to block, and only the interrupt safe FreeRTOS API\r
+ functions can be used (those that end in FromISR()). */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef JUST_AN_EXAMPLE_ISR\r
+\r
+void Dummy_IRQHandler(void)\r
+{\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* Clear the interrupt if necessary. */\r
+ Dummy_ClearITPendingBit();\r
+\r
+ /* This interrupt does nothing more than demonstrate how to synchronise a\r
+ task with an interrupt. A semaphore is used for this purpose. Note\r
+ lHigherPriorityTaskWoken is initialised to zero. */\r
+ xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );\r
+\r
+ /* If there was a task that was blocked on the semaphore, and giving the\r
+ semaphore caused the task to unblock, and the unblocked task has a priority\r
+ higher than the current Running state task (the task that this interrupt\r
+ interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE\r
+ internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the\r
+ portEND_SWITCHING_ISR() macro will result in a context switch being pended to\r
+ ensure this interrupt returns directly to the unblocked, higher priority,\r
+ task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */\r
+ portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );\r
+}\r
+\r
+#endif /* JUST_AN_EXAMPLE_ISR */\r
+\r
+\r
+\r
+\r
--- /dev/null
+;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************\r
+;* File Name : startup_stm32f0xx.s\r
+;* Author : MCD Application Team\r
+;* Version : V1.0.0RC1\r
+;* Date : 27-January-2012\r
+;* Description : STM32F0xx Devices vector table for EWARM toolchain.\r
+;* This module performs:\r
+;* - Set the initial SP\r
+;* - Set the initial PC == __iar_program_start,\r
+;* - Set the vector table entries with the exceptions ISR \r
+;* address.\r
+;* After Reset the Cortex-M0 processor is in Thread mode,\r
+;* priority is Privileged, and the Stack is set to Main.\r
+;********************************************************************************\r
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+;* FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
+;* LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
+;*******************************************************************************/\r
+;\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; The vector table is normally located at address 0.\r
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
+; The name "__vector_table" has special meaning for C-SPY:\r
+; it is where the SP start value is found, and the NVIC vector\r
+; table register (VTOR) is initialized to this address if != 0.\r
+;\r
+; Cortex-M version\r
+;\r
+\r
+ MODULE ?cstartup\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+ SECTION .intvec:CODE:NOROOT(2)\r
+\r
+ EXTERN __iar_program_start\r
+ EXTERN SystemInit \r
+ PUBLIC __vector_table\r
+\r
+ DATA\r
+__vector_table\r
+ DCD sfe(CSTACK)\r
+ DCD Reset_Handler ; Reset Handler\r
+\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; External Interrupts\r
+ DCD WWDG_IRQHandler ; Window Watchdog\r
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect\r
+ DCD RTC_IRQHandler ; RTC through EXTI Line\r
+ DCD FLASH_IRQHandler ; FLASH\r
+ DCD RCC_IRQHandler ; RCC\r
+ DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1\r
+ DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3\r
+ DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15\r
+ DCD TS_IRQHandler ; TS\r
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1\r
+ DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3\r
+ DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5\r
+ DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 \r
+ DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation\r
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare\r
+ DCD TIM2_IRQHandler ; TIM2\r
+ DCD TIM3_IRQHandler ; TIM3\r
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC\r
+ DCD 0 ; Reserved\r
+ DCD TIM14_IRQHandler ; TIM14\r
+ DCD TIM15_IRQHandler ; TIM15\r
+ DCD TIM16_IRQHandler ; TIM16\r
+ DCD TIM17_IRQHandler ; TIM17\r
+ DCD I2C1_IRQHandler ; I2C1\r
+ DCD I2C2_IRQHandler ; I2C2\r
+ DCD SPI1_IRQHandler ; SPI1\r
+ DCD SPI2_IRQHandler ; SPI2\r
+ DCD USART1_IRQHandler ; USART1\r
+ DCD USART2_IRQHandler ; USART2\r
+ DCD 0 ; Reserved\r
+ DCD CEC_IRQHandler ; CEC\r
+ DCD 0 ; Reserved\r
+ \r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+ THUMB\r
+\r
+ EXTERN __ICFEDIT_region_RAM_start__\r
+ EXTERN __ICFEDIT_region_RAM_end__\r
+ SECTION `.text`:CODE:NOROOT(2)\r
+ DATA\r
+??DataTable22:\r
+ DC32 __ICFEDIT_region_RAM_start__\r
+??DataTable22_1:\r
+ DC32 __ICFEDIT_region_RAM_end__\r
+\r
+ THUMB\r
+\r
+ PUBWEAK Reset_Handler\r
+ SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+\r
+ LDR R0,=??DataTable22\r
+ LDR R0,[R0, #+0]\r
+ LDR R1,=??DataTable22_1\r
+??x_0:\r
+ MOVS R2,#+0\r
+ STRB R2,[R0]\r
+ ADDS R0,R0,#0x1\r
+ LDR R2,[R1, #+0]\r
+ CMP R2,R0\r
+ BCS.N ??x_0\r
+\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__iar_program_start\r
+ BX R0\r
+\r
+ \r
+ PUBWEAK NMI_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+NMI_Handler\r
+ B NMI_Handler\r
+ \r
+ \r
+ PUBWEAK HardFault_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+HardFault_Handler\r
+ B HardFault_Handler\r
+ \r
+ \r
+ PUBWEAK SVC_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SVC_Handler\r
+ B SVC_Handler\r
+ \r
+ \r
+ PUBWEAK PendSV_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+PendSV_Handler\r
+ B PendSV_Handler\r
+ \r
+ \r
+ PUBWEAK SysTick_Handler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SysTick_Handler\r
+ B SysTick_Handler\r
+ \r
+ \r
+ PUBWEAK WWDG_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+WWDG_IRQHandler\r
+ B WWDG_IRQHandler\r
+ \r
+ \r
+ PUBWEAK PVD_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+PVD_IRQHandler\r
+ B PVD_IRQHandler\r
+ \r
+ \r
+ PUBWEAK RTC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+RTC_IRQHandler\r
+ B RTC_IRQHandler\r
+ \r
+ \r
+ PUBWEAK FLASH_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+FLASH_IRQHandler\r
+ B FLASH_IRQHandler\r
+ \r
+ \r
+ PUBWEAK RCC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+RCC_IRQHandler\r
+ B RCC_IRQHandler\r
+ \r
+ \r
+ PUBWEAK EXTI0_1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI0_1_IRQHandler\r
+ B EXTI0_1_IRQHandler\r
+ \r
+ \r
+ PUBWEAK EXTI2_3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI2_3_IRQHandler\r
+ B EXTI2_3_IRQHandler\r
+ \r
+ \r
+ PUBWEAK EXTI4_15_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+EXTI4_15_IRQHandler\r
+ B EXTI4_15_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TS_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TS_IRQHandler\r
+ B TS_IRQHandler\r
+ \r
+ \r
+ PUBWEAK DMA1_Channel1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel1_IRQHandler\r
+ B DMA1_Channel1_IRQHandler\r
+ \r
+ \r
+ PUBWEAK DMA1_Channel2_3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel2_3_IRQHandler\r
+ B DMA1_Channel2_3_IRQHandler\r
+ \r
+ \r
+ PUBWEAK DMA1_Channel4_5_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+DMA1_Channel4_5_IRQHandler\r
+ B DMA1_Channel4_5_IRQHandler\r
+ \r
+ \r
+ PUBWEAK ADC1_COMP_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+ADC1_COMP_IRQHandler\r
+ B ADC1_COMP_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM1_BRK_UP_TRG_COM_IRQHandler\r
+ B TIM1_BRK_UP_TRG_COM_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM1_CC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM1_CC_IRQHandler\r
+ B TIM1_CC_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM2_IRQHandler\r
+ B TIM2_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM3_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM3_IRQHandler\r
+ B TIM3_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM6_DAC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM6_DAC_IRQHandler\r
+ B TIM6_DAC_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM14_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM14_IRQHandler\r
+ B TIM14_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM15_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM15_IRQHandler\r
+ B TIM15_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM16_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM16_IRQHandler\r
+ B TIM16_IRQHandler\r
+ \r
+ \r
+ PUBWEAK TIM17_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+TIM17_IRQHandler\r
+ B TIM17_IRQHandler\r
+ \r
+ \r
+ PUBWEAK I2C1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C1_IRQHandler\r
+ B I2C1_IRQHandler\r
+ \r
+ \r
+ PUBWEAK I2C2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+I2C2_IRQHandler\r
+ B I2C2_IRQHandler\r
+ \r
+ \r
+ PUBWEAK SPI1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI1_IRQHandler\r
+ B SPI1_IRQHandler\r
+ \r
+ \r
+ PUBWEAK SPI2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+SPI2_IRQHandler\r
+ B SPI2_IRQHandler\r
+ \r
+ \r
+ PUBWEAK USART1_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART1_IRQHandler\r
+ B USART1_IRQHandler\r
+ \r
+ \r
+ PUBWEAK USART2_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+USART2_IRQHandler\r
+ B USART2_IRQHandler\r
+ \r
+ \r
+ PUBWEAK CEC_IRQHandler\r
+ SECTION .text:CODE:NOROOT:REORDER(1)\r
+CEC_IRQHandler\r
+ B CEC_IRQHandler \r
+\r
+ END\r
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;\r
+define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x400;\r
+define symbol __ICFEDIT_size_heap__ = 0x00;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+\r
+define memory mem with size = 4G;\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+export symbol __ICFEDIT_region_RAM_start__;\r
+export symbol __ICFEDIT_region_RAM_end__;\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+\r
+place in ROM_region { readonly };\r
+place in RAM_region { readwrite,\r
+ block CSTACK, block HEAP };
\ No newline at end of file
projects / freertos / commitdiff