]> git.sur5r.net Git - openocd/commitdiff
armv4_5_core_reg_t -> struct armv4_5_core_reg
authorZachary T Welch <zw@superlucidity.net>
Fri, 13 Nov 2009 16:41:14 +0000 (08:41 -0800)
committerZachary T Welch <zw@superlucidity.net>
Fri, 13 Nov 2009 19:58:10 +0000 (11:58 -0800)
Remove misleading typedef and redundant suffix from struct armv4_5_core_reg.

src/target/arm7_9_common.c
src/target/armv4_5.c
src/target/armv4_5.h

index 75998fe9d6f2c36746ca51611205f0baf184f751..1cd3456b7d80766af55597054d4fc9b56783009e 100644 (file)
@@ -1600,7 +1600,7 @@ int arm7_9_restore_context(target_t *target)
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
        reg_t *reg;
-       armv4_5_core_reg_t *reg_arch_info;
+       struct armv4_5_core_reg *reg_arch_info;
        enum armv4_5_mode current_mode = armv4_5->core_mode;
        int i, j;
        int dirty;
@@ -2114,7 +2114,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
 
-       enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
+       enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
 
        if ((num < 0) || (num > 16))
                return ERROR_INVALID_ARGUMENTS;
@@ -2144,7 +2144,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
                /* read a program status register
                 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
                 */
-               armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
+               struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
                int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
 
                arm7_9->read_xpsr(target, &value, spsr);
@@ -2178,7 +2178,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
 
-       enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
+       enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
 
        if ((num < 0) || (num > 16))
                return ERROR_INVALID_ARGUMENTS;
@@ -2207,7 +2207,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
                /* write a program status register
                * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
                */
-               armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
+               struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
                int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
 
                /* if we're writing the CPSR, mask the T bit */
index a89b98b8a2ef876c259b923bb287497dae50b851..bde9e2222e6bc88b25b48db7687429b912d3268d 100644 (file)
@@ -80,7 +80,7 @@ char* armv4_5_state_strings[] =
 
 int armv4_5_core_reg_arch_type = -1;
 
-armv4_5_core_reg_t armv4_5_core_reg_list_arch_info[] =
+struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
 {
        {0, ARMV4_5_MODE_ANY, NULL, NULL},
        {1, ARMV4_5_MODE_ANY, NULL, NULL},
@@ -170,7 +170,7 @@ reg_t armv4_5_gdb_dummy_fps_reg =
 int armv4_5_get_core_reg(reg_t *reg)
 {
        int retval;
-       armv4_5_core_reg_t *armv4_5 = reg->arch_info;
+       struct armv4_5_core_reg *armv4_5 = reg->arch_info;
        target_t *target = armv4_5->target;
 
        if (target->state != TARGET_HALTED)
@@ -187,7 +187,7 @@ int armv4_5_get_core_reg(reg_t *reg)
 
 int armv4_5_set_core_reg(reg_t *reg, uint8_t *buf)
 {
-       armv4_5_core_reg_t *armv4_5 = reg->arch_info;
+       struct armv4_5_core_reg *armv4_5 = reg->arch_info;
        target_t *target = armv4_5->target;
        struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target);
        uint32_t value = buf_get_u32(buf, 0, 32);
@@ -254,7 +254,7 @@ reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5
        int num_regs = 37;
        reg_cache_t *cache = malloc(sizeof(reg_cache_t));
        reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
-       armv4_5_core_reg_t *arch_info = malloc(sizeof(armv4_5_core_reg_t) * num_regs);
+       struct armv4_5_core_reg *arch_info = malloc(sizeof(struct armv4_5_core_reg) * num_regs);
        int i;
 
        cache->name = "arm v4/5 registers";
index 22069d1b0066a924580ba1ac9aec7d53de0ab2cb..3cc8937eb3f81fd09ee6c08c5ea74b65feec4bce 100644 (file)
@@ -127,13 +127,13 @@ struct armv4_5_algorithm
        enum armv4_5_state core_state;
 };
 
-typedef struct armv4_5_core_reg_s
+struct armv4_5_core_reg
 {
        int num;
        enum armv4_5_mode mode;
        target_t *target;
        armv4_5_common_t *armv4_5_common;
-} armv4_5_core_reg_t;
+};
 
 reg_cache_t* armv4_5_build_reg_cache(target_t *target,
                armv4_5_common_t *armv4_5_common);