# flash bank <driver> <base> <size> <chip_width> <bus_width>
# 29LV650 64Mbit Flash
-flash bank cfi 0x00000000 0x800000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x800000 2 2 0
reset_config trst_and_srst separate
# works for P30 flash
-flash bank cfi 0x00000000 0x2000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x2000000 2 2 $_TARGETNAME
source [find target/at91rm9200.cfg]
# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
-flash bank cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
# ETM9 trace port connector present on this board, 16 data pins.
if { [info exists ETM_DRIVER] } {
#M29DW323DB - not working
#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x50000000 0x0400000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x50000000 0x0400000 2 2 0
#flash configuration
#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
-flash bank cfi 0x00000000 0x1000000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x1000000 2 2 0
}
# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
-flash bank cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
$_TARGETNAME configure -event reset-init {
$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0
# CS0, CS1 -- two banks of CFI flash, 32 MBytes each
# each bank is 32-bits wide, two 16-bit chips in parallel
-flash bank cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
-flash bank cfi 0x04000000 0x02000000 2 4 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 4 $_TARGETNAME
# CS2 low -- FPGA registers
# CS2 high -- 1 MByte SRAM at 0x0a00.0000 ... last 64K for scratch
# Board configs can vary a *LOT* ... parts, jumpers, etc.
# This GP board boots from cs0 using NOR (2x32M), and also
# has 64M NAND on cs6.
-flash bank cfi 0x04000000 0x02000000 2 2 $_TARGETNAME
-flash bank cfi 0x06000000 0x02000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x06000000 0x02000000 2 2 $_TARGETNAME
# standard boards populate two 16 MB chips, but manufacturing
# options or an expansion board could change this config.
-flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
-flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
proc osk5912_init {} {
omap5912_reset
$_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
# flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options]
-flash bank cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
proc pxa255_sst_init {} {
xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
}
#flash bank str9x <base> <size> 0 0 <target#> <variant>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0
# For more information about the configuration files, take a look at:
# openocd.texi
# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
# it's really 16MB but the upper 8mb is controller via gpio
# openocd does not support 'complex reads/writes' to NOR
-flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
# writing data to memory does not work without this
memwrite burst disable
\ No newline at end of file
#####################
#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x20000000 0x2000000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x2000000 2 2 0
#####################
#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x20000000 0x1000000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x1000000 2 2 0
#####################
#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x10000000 0x01000000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 0
# 1MB CFI capable flash
# flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank cfi 0xac000000 0x100000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xac000000 0x100000 2 2 0
proc x300t_init { } {
# Setup SDRAM config and flash mapping
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
-flash bank ecosflash 0x01000000 0x200000 2 2 $_TARGETNAME ecos/at91eb40a.elf
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME ecosflash 0x01000000 0x200000 2 2 $_TARGETNAME ecos/at91eb40a.elf
$_TARGETNAME configure -event reset-init {
# Set up chip selects & timings
mww 0xFFE00000 0x0100273D
## flash configuration
# only target number is needed
-flash bank aduc702x 0 0 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME aduc702x 0 0 0 0 0
## If you use the watchdog, the following code makes sure that the board
## doesn't reboot when halted via JTAG. Yes, on the older generation
arm7_9 dcc_downloads enable
#flash driver
-flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
# required for usable performance. Used for lots of
# other things than flash programming.
$_TARGETNAME configure -work-area-phys 0x3C000 -work-area-size 0x4000 -work-area-backup 0
-flash bank cfi 0x10000000 0x400000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x400000 2 2 $_TARGETNAME
# For more information about the configuration files, take a look at:
# openocd.texi
source [find target/at91sam3uxx.cfg]
# size is automatically "calculated" by probing
-flash bank at91sam3 0x000080000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
source [find target/at91sam3uxx.cfg]
# size is automatically "calculated" by probing
-flash bank at91sam3 0x000080000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
source [find target/at91sam3uxx.cfg]
# size is automatically "calculated" by probing
-flash bank at91sam3 0x000080000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
source [find target/at91sam3uxx.cfg]
# size is automatically "calculated" by probing
-flash bank at91sam3 0x000080000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
source [find target/at91sam3uxx.cfg]
# size is automatically "calculated" by probing
-flash bank at91sam3 0x000080000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
# This is a 256K chip, it has the 2nd bank
-flash bank at91sam3 0x000100000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
source [find target/at91sam3uxx.cfg]
# size is automatically "calculated" by probing
-flash bank at91sam3 0x000080000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
# This is a 256K chip - it has the 2nd bank
-flash bank at91sam3 0x000100000 0 1 1 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
# For more information about the configuration files, take a look at:
# openocd.texi
# Flash configuration
#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
proc at91sam_init { } {
#flash configuration
#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
-flash bank cfi 0x60000000 0x1000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x60000000 0x1000000 2 2 $_TARGETNAME
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
#dummy flash driver
-flash bank faux 0x01000000 0x200000 2 2 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME faux 0x01000000 0x200000 2 2 0
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
#flash configuration
-flash bank stellaris 0 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
# flash configuration -- one bank of 128K
-flash bank stellaris 0 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
#flash configuration
-flash bank stellaris 0 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
#flash configuration
-flash bank stellaris 0 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x4000
#flash configuration
-flash bank stellaris 0 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
# LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region).
# flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum]
-flash bank lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 12000 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 12000 calc_checksum
# 4MHz / 6 = 666kHz, so use 500
jtag_khz 500
# 32kB of internal Flash, core clocked with 12MHz crystal
# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc_checksum]
-flash bank lpc2000 0x0 0x8000 0 0 $_TARGETNAME lpc2000_v2 12000 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x8000 0 0 $_TARGETNAME lpc2000_v2 12000 calc_checksum
#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14745 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14745 calc_checksum
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14765 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14765 calc_checksum
}
# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc_checksum]
-flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME lpc2000_v2 14765 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME lpc2000_v2 14765 calc_checksum
#flash configuration
#flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
-flash bank lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14765 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14765 calc_checksum
# For more information about the configuration files, take a look at:
# openocd.texi
# LPC2378 has 512kB of FLASH, but upper 8kB are occupied by bootloader.
# After reset the chip uses its internal 4MHz RC oscillator
#flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
-flash bank lpc2000 0x0 0x0007D000 0 0 $_TARGETNAME lpc2000_v2 4000 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x0007D000 0 0 $_TARGETNAME lpc2000_v2 4000 calc_checksum
# 4MHz / 6 = 666kHz, so use 500
jtag_khz 500
# LPC2378 has 512kB of FLASH, but upper 8kB are occupied by bootloader.
# After reset the chip uses its internal 4MHz RC oscillator.
# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
-flash bank lpc2000 0x0 0x7D000 0 0 $_TARGETNAME lpc2000_v2 12000 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x7D000 0 0 $_TARGETNAME lpc2000_v2 12000 calc_checksum
# Try to use RCLK, if RCLK is not available use "normal" mode. 4MHz / 6 = 666kHz, so use 500.
jtag_rclk 500
# Flash bank configuration:
# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz>
# Flash base address, total flash size, and number of sectors are all configured automatically.
-flash bank lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK
#$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-flash bank avr 0 0 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME avr 0 0 0 0 0
#to use it, script will be like:
#init
$_TARGETNAME configure -work-area-phys 0xa0000000 -work-area-size 16384 -work-area-backup 0
-flash bank pic32mx 0xbd000000 0 0 0 0
-flash bank pic32mx 0xbfc00000 0 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME pic32mx 0xbd000000 0 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME pic32mx 0xbfc00000 0 0 0 0
# For more information about the configuration files, take a look at:
# openocd.texi
$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
# For more information about the configuration files, take a look at:
# openocd.texi
source [find target/samsung_s3c6410.cfg]
-flash bank cfi 0x00000000 0x00100000 2 2 $_TARGETNAME jedec_probe
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x00100000 2 2 $_TARGETNAME jedec_probe
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-flash bank stm32x 0 0 0 0 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32x 0 0 0 0 $_TARGETNAME
# For more information about the configuration files, take a look at:
# openocd.texi
$_TARGETNAME configure -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0
#flash bank str7x <base> <size> 0 0 <target#> <variant>
-flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
-flash bank str7x 0x400C0000 0x00004000 0 0 0 STR71x
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 0 STR71x
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str7x 0x400C0000 0x00004000 0 0 0 STR71x
# For more information about the configuration files, take a look at:
# openocd.texi
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank str7x 0x20000000 0x00040000 0 0 0 STR3x
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 0 STR3x
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank str7x 0x20000000 0x00040000 0 0 0 STR75x
-flash bank str7x 0x200C0000 0x00004000 0 0 0 STR75x
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 0 STR75x
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str7x 0x200C0000 0x00004000 0 0 0 STR75x
$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
#flash bank str9x <base> <size> 0 0 <target#> <variant>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0
# For more information about the configuration files, take a look at:
# openocd.texi
# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
# it's really 16MB but the upper 8mb is controller via gpio
# openocd does not support 'complex reads/writes' to NOR
-flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
# writing data to memory does not work without this
memwrite burst disable
\ No newline at end of file
$_TARGETNAME configure -work-area-phys 0x20010000 -work-area-size 0x8060 -work-area-backup 0
-flash bank cfi 0x50000000 0x400000 2 2 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x50000000 0x400000 2 2 $_TARGETNAME
init
reset init
-flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765