End of line comments fixed with ';' before '#'.
Added few additional 'space' to keep indentation in
multi-line comments.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
# jtag speed without causing GDB keep alive problem.
arm7_9 fast_memory_access disable
- adapter_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow.
- halt # Make sure processor is halted, or error will result in following steps.
+ adapter_khz 2 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+ halt ;# Make sure processor is halted, or error will result in following steps.
wait_halt 10000
- mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset.
+ mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset.
}
proc at91sam9g20_reset_init { } {
# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
- mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog.
+ mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog.
# Enable the main 18.432 MHz oscillator in CKGR_MOR register.
# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
# a number of registers. The first step involves setting up the general I/O pins on the processor
# to be able to interface and support the external memory.
- mww 0xfffffc10 0x00000010 # PMC_PCER : enable PIOC clock
- mww 0xfffff800 0x00006000 # PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
- mww 0xfffff810 0x00004000 # PIOC_OER : enable output on 14
- mww 0xfffff814 0x00002000 # PIOC_ODR : disable output on 13
- mww 0xfffff830 0x00004000 # PIOC_SODR : set 14 to disable NAND
+ mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock
+ mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
+ mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14
+ mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
+ mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
# The exact physical timing characteristics for the memory type used on the current board
# (MT29F2G08AACWP) can be established by setting four registers in order: SMC_SETUP3,
# is a little tedious to do here. If you have questions about how to do this, Atmel has
# a decent application note #6255B that covers this process.
- mww 0xffffec30 0x00020002 # SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
- mww 0xffffec34 0x04040404 # SMC_PULSE3 : 4 clock cycle pulse for all signals
- mww 0xffffec38 0x00070006 # SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
- mww 0xffffec3C 0x00020003 # SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+ mww 0xffffec30 0x00020002 ;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
+ mww 0xffffec34 0x04040404 ;# SMC_PULSE3 : 4 clock cycle pulse for all signals
+ mww 0xffffec38 0x00070006 ;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
+ mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
- mww 0xffffe800 0x00000001 # ECC_CR : reset the ECC parity registers
- mww 0xffffe804 0x00000002 # ECC_MR : page size is 2112 words (word is 8 bits)
+ mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
+ mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
# Identify NandFlash bank 0.
}
$_TARGETNAME configure -event reset-init {
- mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
+ mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
- mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
- sleep 20 # wait 20 ms
- mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
- sleep 10 # wait 10 ms
- mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198.656 MHz
- sleep 20 # wait 20 ms
- mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler (divide by 2)
- sleep 10 # wait 10 ms
- mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
- sleep 10 # wait 10 ms
+ mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
+ sleep 20 ;# wait 20 ms
+ mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198.656 MHz
+ sleep 20 ;# wait 20 ms
+ mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2)
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
+ sleep 10 ;# wait 10 ms
# Increase JTAG Speed to 6 MHz if RCLK is not supported
jtag_rclk 6000
- arm7_9 dcc_downloads enable # Enable faster DCC downloads
+ arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
- mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
- mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
+ mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
+ mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
- mww 0xffffef1c 0x00010002 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
+ mww 0xffffef1c 0x00010002 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
- mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
+ mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
- mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
+ mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
mww 0x20000000 0
- mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
+ mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
mww 0x20000000 0
- mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+ mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
- mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
+ mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
mww 0x20000000 0
- mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
+ mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
mww 0x20000000 0
- mww 0xffffea04 0x2b6 # SDRAMC_TR : Set refresh timer count to 7us
+ mww 0xffffea04 0x2b6 ;# SDRAMC_TR : Set refresh timer count to 7us
}
}
$_TARGETNAME configure -event reset-init {
- mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
+ mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
- mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
- sleep 20 # wait 20 ms
- mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
- sleep 10 # wait 10 ms
- mww 0xfffffc28 0x2031bf03 # CKGR_PLLR: Set PLL Register for 200 MHz
- sleep 20 # wait 20 ms
- mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler (divide by 2)
- sleep 10 # wait 10 ms
- mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLL is selected (100 MHz)
- sleep 10 # wait 10 ms
+ mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
+ sleep 20 ;# wait 20 ms
+ mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc28 0x2031bf03 ;# CKGR_PLLR: Set PLL Register for 200 MHz
+ sleep 20 ;# wait 20 ms
+ mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2)
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLL is selected (100 MHz)
+ sleep 10 ;# wait 10 ms
# Increase JTAG Speed to 6 MHz if RCLK is not supported
jtag_rclk 6000
- arm7_9 dcc_downloads enable # Enable faster DCC downloads
+ arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
- mww 0xfffff670 0xffff0000 # PIO_ASR : Select peripheral function for D16..D31 (PIOB)
- mww 0xfffff604 0xffff0000 # PIO_PDR : Disable PIO function for D16..D31 (PIOB)
+ mww 0xfffff670 0xffff0000 ;# PIO_ASR : Select peripheral function for D16..D31 (PIOB)
+ mww 0xfffff604 0xffff0000 ;# PIO_PDR : Disable PIO function for D16..D31 (PIOB)
- mww 0xffffef20 0x00010002 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
+ mww 0xffffef20 0x00010002 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
- mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
+ mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
- mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
+ mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
mww 0x20000000 0
- mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
+ mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
mww 0x20000000 0
- mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+ mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
- mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
+ mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
mww 0x20000000 0
- mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
+ mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
mww 0x20000000 0
- mww 0xffffea04 0x2b6 # SDRAMC_TR : Set refresh timer count to 7us
+ mww 0xffffea04 0x2b6 ;# SDRAMC_TR : Set refresh timer count to 7us
}
$_TARGETNAME configure -event reset-init {
mww 0x90600104 0x33313333
- mww 0xA0700000 0x00000001 # Enable the memory controller.
- mww 0xA0700024 0x00000006 # Set the refresh counter 6
- mww 0xA0700028 0x00000001 #
- mww 0xA0700030 0x00000001 # Set the precharge period
- mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles
- mww 0xA070003C 0x00000001 # tAPR
- mww 0xA0700040 0x00000005 # tDAL
- mww 0xA0700044 0x00000001 # tWR
- mww 0xA0700048 0x00000006 # tRC 32 clock cycles
- mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
- mww 0xA0700054 0x00000001 # tRRD
- mww 0xA0700058 0x00000001 # tMRD
- mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
- mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
- mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
- mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
+ mww 0xA0700000 0x00000001 ;# Enable the memory controller.
+ mww 0xA0700024 0x00000006 ;# Set the refresh counter 6
+ mww 0xA0700028 0x00000001 ;#
+ mww 0xA0700030 0x00000001 ;# Set the precharge period
+ mww 0xA0700034 0x00000004 ;# Active to precharge command period is 16 clock cycles
+ mww 0xA070003C 0x00000001 ;# tAPR
+ mww 0xA0700040 0x00000005 ;# tDAL
+ mww 0xA0700044 0x00000001 ;# tWR
+ mww 0xA0700048 0x00000006 ;# tRC 32 clock cycles
+ mww 0xA070004C 0x00000006 ;# tRFC 32 clock cycles
+ mww 0xA0700054 0x00000001 ;# tRRD
+ mww 0xA0700058 0x00000001 ;# tMRD
+ mww 0xA0700100 0x00004280 ;# Dynamic Config 0 (cs4)
+ mww 0xA0700120 0x00004280 ;# Dynamic Config 1 (cs5)
+ mww 0xA0700140 0x00004280 ;# Dynamic Config 2 (cs6)
+ mww 0xA0700160 0x00004280 ;# Dynamic Config 3 (cs7)
#
- mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz
- mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz
- mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz
- mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz
+ mww 0xA0700104 0x00000203 ;# CAS latency is 2 at 100 MHz
+ mww 0xA0700124 0x00000203 ;# CAS latency is 2 at 100 MHz
+ mww 0xA0700144 0x00000203 ;# CAS latency is 2 at 100 MHz
+ mww 0xA0700164 0x00000203 ;# CAS latency is 2 at 100 MHz
#
- mww 0xA0700020 0x00000103 # issue SDRAM PALL command
+ mww 0xA0700020 0x00000103 ;# issue SDRAM PALL command
#
- mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as possible
+ mww 0xA0700024 0x00000001 ;# Set the refresh counter to be as small as possible
#
# Add some dummy writes to give the SDRAM time to settle, it needs two
# AHB clock cycles, here we poke in the debugger flag, this lets
mdw 0xA0900000
mdw 0xA0900000
#
- mww 0xA0700024 0x00000030 # Set the refresh counter to 30
- mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
+ mww 0xA0700024 0x00000030 ;# Set the refresh counter to 30
+ mww 0xA0700020 0x00000083 ;# Issue SDRAM MODE command
#
# Next we perform a read of RAM.
# mw = move word.
mdw 0x00022000
# mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
#
- mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command
- mww 0xA0700100 0x00084280 # Enable buffer access
- mww 0xA0700120 0x00084280 # Enable buffer access
- mww 0xA0700140 0x00084280 # Enable buffer access
- mww 0xA0700160 0x00084280 # Enable buffer access
+ mww 0xA0700020 0x00000003 ;# issue SDRAM NORMAL command
+ mww 0xA0700100 0x00084280 ;# Enable buffer access
+ mww 0xA0700120 0x00084280 ;# Enable buffer access
+ mww 0xA0700140 0x00084280 ;# Enable buffer access
+ mww 0xA0700160 0x00084280 ;# Enable buffer access
#Set byte lane state (static mem 1)"
mww 0xA0700220 0x00000082
#
# Enable SDRAM control at PIO A.
- mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
- mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
+ mww 0xfffff474 0x3f800000 ;# PIO_BSR_OFF
+ mww 0xfffff404 0x3f800000 ;# PIO_PDR_OFF
# Enable address bus (A0, A2-A11, A13-A17) at PIO B
- mww 0xfffff674 0x0003effd # PIO_BSR_OFF
- mww 0xfffff604 0x0003effd # PIO_PDR_OFF
+ mww 0xfffff674 0x0003effd ;# PIO_BSR_OFF
+ mww 0xfffff604 0x0003effd ;# PIO_PDR_OFF
# Enable 16 bit data bus at PIO C
- mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
- mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
+ mww 0xfffff870 0x0000ffff ;# PIO_ASR_OFF
+ mww 0xfffff804 0x0000ffff ;# PIO_PDR_OFF
# Enable SDRAM chip select
- mww 0xffffff80 0x00000002 # EBI_CSA_OFF
+ mww 0xffffff80 0x00000002 ;# EBI_CSA_OFF
# Set SDRAM characteristics in configuration register.
# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
- mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
+ mww 0xffffffb8 0x2192215a ;# SDRAMC_CR_OFF
sleep 10
# Issue 16 bit SDRAM command: NOP
- mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000011 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
# Issue 16 bit SDRAM command: Precharge all
- mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000012 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
# Issue 8 auto-refresh cycles
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
# Issue 16 bit SDRAM command: Set mode register
- mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000013 ;# SDRAMC_MR_OFF
mww 0x20000014 0xcafedede
# Set refresh rate count ???
- mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
+ mww 0xffffffb4 0x00000013 ;# SDRAMC_TR_OFF
# Issue 16 bit SDRAM command: Normal mode
- mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
+ mww 0xffffffb0 0x00000010 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000180
#
if {[expr [read_register 0xE01FC080] & 0x03] == 3} {
# Disconnect it, but leave it enabled
# (This MUST be done in two steps)
- mww 0xE01FC080 0x00000001 # PLLCON: disconnect PLL
- mww 0xE01FC08C 0x000000AA # PLLFEED
- mww 0xE01FC08C 0x00000055 # PLLFEED
+ mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL
+ mww 0xE01FC08C 0x000000AA ;# PLLFEED
+ mww 0xE01FC08C 0x00000055 ;# PLLFEED
}
# Disable PLL (as it might already be enabled at this time!)
- mww 0xE01FC080 0x00000000 # PLLCON: disable PLL
- mww 0xE01FC08C 0x000000AA # PLLFEED
- mww 0xE01FC08C 0x00000055 # PLLFEED
+ mww 0xE01FC080 0x00000000 ;# PLLCON: disable PLL
+ mww 0xE01FC08C 0x000000AA ;# PLLFEED
+ mww 0xE01FC08C 0x00000055 ;# PLLFEED
# Setup PLL to generate 288 MHz from internal RC oscillator
- mww 0xE01FC10C 0x00000000 # CLKSRCSEL: IRC
- mww 0xE01FC084 0x00000023 # PLLCFG: N=1, M=36
- mww 0xE01FC08C 0x000000AA # PLLFEED
- mww 0xE01FC08C 0x00000055 # PLLFEED
- mww 0xE01FC080 0x00000001 # PLLCON: enable PLL
- mww 0xE01FC08C 0x000000AA # PLLFEED
- mww 0xE01FC08C 0x00000055 # PLLFEED
+ mww 0xE01FC10C 0x00000000 ;# CLKSRCSEL: IRC
+ mww 0xE01FC084 0x00000023 ;# PLLCFG: N=1, M=36
+ mww 0xE01FC08C 0x000000AA ;# PLLFEED
+ mww 0xE01FC08C 0x00000055 ;# PLLFEED
+ mww 0xE01FC080 0x00000001 ;# PLLCON: enable PLL
+ mww 0xE01FC08C 0x000000AA ;# PLLFEED
+ mww 0xE01FC08C 0x00000055 ;# PLLFEED
sleep 100
- mww 0xE01FC104 0x00000003 # CCLKCFG: divide by 4 (72 MHz)
- mww 0xE01FC080 0x00000003 # PLLCON: connect PLL
- mww 0xE01FC08C 0x000000AA # PLLFEED
- mww 0xE01FC08C 0x00000055 # PLLFEED
+ mww 0xE01FC104 0x00000003 ;# CCLKCFG: divide by 4 (72 MHz)
+ mww 0xE01FC080 0x00000003 ;# PLLCON: connect PLL
+ mww 0xE01FC08C 0x000000AA ;# PLLFEED
+ mww 0xE01FC08C 0x00000055 ;# PLLFEED
}
$_TARGETNAME configure -event reset-init {
arm core_state arm
- arm7_9 dcc_downloads enable # Speed up downloads by using DCC transfer
+ arm7_9 dcc_downloads enable ;# Speed up downloads by using DCC transfer
arm7_9 fast_memory_access enable
# Peripheral clocks
- mww 0xE01FC0C4 0x04280FFE # PCONP: (reset value)
+ mww 0xE01FC0C4 0x04280FFE ;# PCONP: (reset value)
# Map the user flash to the vector table area (0x00...0x3F)
- mww 0xE01FC040 0x00000001 # MEMMAP: User flash
+ mww 0xE01FC040 0x00000001 ;# MEMMAP: User flash
# Memory accelerator module
- mww 0xE01FC004 0x00000003 # MAMTIM: 3 clock cycles
- mww 0xE01FC000 0x00000002 # MAMCR: fully enabled
+ mww 0xE01FC004 0x00000003 ;# MAMTIM: 3 clock cycles
+ mww 0xE01FC000 0x00000002 ;# MAMCR: fully enabled
# Enable external memory bus (32-bit SDRAM at DYCS0, 16-bit flash at CS0)
- mww 0xE002C014 0x55010115 # PINSEL5: P2.16=CAS, P2.17=RAS, P2.18=CLKOUT0,
- # P2.20=DYCS0, P2.24=CKEOUT0, P2.28=DQMOUT0,
- # P2.29=DQMOUT1, P2.30=DQMOUT2, P2.31=DQMOUT3
- mww 0xE002C018 0x55555555 # PINSEL6: P3.0...P3.15=D0...D15
- mww 0xE002C01C 0x55555555 # PINSEL7: P3.16...P3.31=D16...D31
- mww 0xE002C020 0x55555555 # PINSEL8: P4.0...P4.15=A0...A15
- mww 0xE002C024 0x50051555 # PINSEL9: P4.16...P4.22=A16...A22, P4.24=OE,
- # P4.25=WE, P4.30=CS0, P4.31=CS1
- mww 0xFFE08000 0x00000001 # EMCControl: Enable EMC
+ mww 0xE002C014 0x55010115 ;# PINSEL5: P2.16=CAS, P2.17=RAS, P2.18=CLKOUT0,
+ # P2.20=DYCS0, P2.24=CKEOUT0, P2.28=DQMOUT0,
+ # P2.29=DQMOUT1, P2.30=DQMOUT2, P2.31=DQMOUT3
+ mww 0xE002C018 0x55555555 ;# PINSEL6: P3.0...P3.15=D0...D15
+ mww 0xE002C01C 0x55555555 ;# PINSEL7: P3.16...P3.31=D16...D31
+ mww 0xE002C020 0x55555555 ;# PINSEL8: P4.0...P4.15=A0...A15
+ mww 0xE002C024 0x50051555 ;# PINSEL9: P4.16...P4.22=A16...A22, P4.24=OE,
+ # P4.25=WE, P4.30=CS0, P4.31=CS1
+ mww 0xFFE08000 0x00000001 ;# EMCControl: Enable EMC
# Start PLL, then use faster JTAG clock
enable_pll
jtag_rclk 3000
# 16-bit flash @ CS0 (SST39VF3201-70)
- mww 0xFFE08200 0x00080081 # EMCStaticConfig0: 16 bit, PB=1, buffers on
- mww 0xFFE08204 0x00000000 # EMCStaticWaitWen0
- mww 0xFFE08208 0x00000000 # EMCStaticWaitOen0
- mww 0xFFE0820C 0x00000005 # EMCStaticWaitRd0
- mww 0xFFE08210 0x00000005 # EMCStaticWaitPage0
- mww 0xFFE08214 0x00000003 # EMCStaticWaitWr0
- mww 0xFFE08218 0x00000001 # EMCStaticWaitTurn0
+ mww 0xFFE08200 0x00080081 ;# EMCStaticConfig0: 16 bit, PB=1, buffers on
+ mww 0xFFE08204 0x00000000 ;# EMCStaticWaitWen0
+ mww 0xFFE08208 0x00000000 ;# EMCStaticWaitOen0
+ mww 0xFFE0820C 0x00000005 ;# EMCStaticWaitRd0
+ mww 0xFFE08210 0x00000005 ;# EMCStaticWaitPage0
+ mww 0xFFE08214 0x00000003 ;# EMCStaticWaitWr0
+ mww 0xFFE08218 0x00000001 ;# EMCStaticWaitTurn0
# 8-bit NAND @ CS1
# TODO
# 32-bit SDRAM @ DYCS0 (K4M563233G-HN75)
- mww 0xFFE08028 0x00000001 # EMCDynamicReadConfig
- mww 0xFFE08030 0x00000001 # EMCDynamicRP
- mww 0xFFE08034 0x00000003 # EMCDynamicRAS
- mww 0xFFE08038 0x00000005 # EMCDynamicSREX
- mww 0xFFE0803C 0x00000001 # EMCDynamicAPR
- mww 0xFFE08040 0x00000005 # EMCDynamicDAL
- mww 0xFFE08044 0x00000001 # EMCDynamicWR
- mww 0xFFE08048 0x00000005 # EMCDynamicRC
- mww 0xFFE0804C 0x00000005 # EMCDynamicRFC
- mww 0xFFE08050 0x00000005 # EMCDynamicXSR
- mww 0xFFE08054 0x00000001 # EMCDynamicRRD
- mww 0xFFE08058 0x00000001 # EMCDynamicMRD
+ mww 0xFFE08028 0x00000001 ;# EMCDynamicReadConfig
+ mww 0xFFE08030 0x00000001 ;# EMCDynamicRP
+ mww 0xFFE08034 0x00000003 ;# EMCDynamicRAS
+ mww 0xFFE08038 0x00000005 ;# EMCDynamicSREX
+ mww 0xFFE0803C 0x00000001 ;# EMCDynamicAPR
+ mww 0xFFE08040 0x00000005 ;# EMCDynamicDAL
+ mww 0xFFE08044 0x00000001 ;# EMCDynamicWR
+ mww 0xFFE08048 0x00000005 ;# EMCDynamicRC
+ mww 0xFFE0804C 0x00000005 ;# EMCDynamicRFC
+ mww 0xFFE08050 0x00000005 ;# EMCDynamicXSR
+ mww 0xFFE08054 0x00000001 ;# EMCDynamicRRD
+ mww 0xFFE08058 0x00000001 ;# EMCDynamicMRD
#
- mww 0xFFE08104 0x00000202 # EMCDynamicRasCas0
- mww 0xFFE08100 0x00005488 # EMCDynamicConfig0
+ mww 0xFFE08104 0x00000202 ;# EMCDynamicRasCas0
+ mww 0xFFE08100 0x00005488 ;# EMCDynamicConfig0
sleep 100
- mww 0xFFE08020 0x00000183 # EMCDynamicControl: Clock on continuously, NOP
+ mww 0xFFE08020 0x00000183 ;# EMCDynamicControl: Clock on continuously, NOP
sleep 10
- mww 0xFFE08020 0x00000103 # EMCDynamicControl: PRECHARGE-ALL
- mww 0xFFE08024 0x00000046 # EMCDynamicRefresh
+ mww 0xFFE08020 0x00000103 ;# EMCDynamicControl: PRECHARGE-ALL
+ mww 0xFFE08024 0x00000046 ;# EMCDynamicRefresh
sleep 100
- mww 0xFFE08020 0x00000083 # EMCDynamicControl: MODE
- mdw 0xA0011000 1 # Set SDRAM mode register
- mww 0xFFE08020 0x00000000 # EMCDynamicControl: NORMAL
- mww 0xFFE08100 0x00085488 # EMCDynamicConfig0: Enable buffers
+ mww 0xFFE08020 0x00000083 ;# EMCDynamicControl: MODE
+ mdw 0xA0011000 1 ;# Set SDRAM mode register
+ mww 0xFFE08020 0x00000000 ;# EMCDynamicControl: NORMAL
+ mww 0xFFE08100 0x00085488 ;# EMCDynamicConfig0: Enable buffers
}
$_TARGETNAME configure -event reset-init {
# Flash
- mww 0x20200010 0x00000007 # FBWST: 7 wait states, not chached
+ mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not chached
# Use PLL
- mww 0xFFFF8020 0x00000001 # XTAL_OSC_CONTROL: enable, 1-20 MHz
- mww 0xFFFF8070 0x01000000 # SYS_CLK_CONF: Crystal
- mww 0xFFFF8028 0x00000005 # PLL: (power down)
- mww 0xFFFF8028 0x01060004 # PLL: M=7, 2P=2 (power up)
- # --> f=112 MHz, fcco=224 MHz
+ mww 0xFFFF8020 0x00000001 ;# XTAL_OSC_CONTROL: enable, 1-20 MHz
+ mww 0xFFFF8070 0x01000000 ;# SYS_CLK_CONF: Crystal
+ mww 0xFFFF8028 0x00000005 ;# PLL: (power down)
+ mww 0xFFFF8028 0x01060004 ;# PLL: M=7, 2P=2 (power up)
+ # --> f=112 MHz, fcco=224 MHz
sleep 100
- mww 0xFFFF8070 0x02000000 # SYS_CLK_CONF: PLL
+ mww 0xFFFF8070 0x02000000 ;# SYS_CLK_CONF: PLL
# Increase JTAG speed
adapter_khz 6000
# Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
- mww 0xE0001138 0x0000001F # P1.14 = D0
- mww 0xE000113C 0x0000001F # P1.15 = D1
- mww 0xE0001140 0x0000001F # P1.16 = D2
- mww 0xE0001144 0x0000001F # P1.17 = D3
- mww 0xE0001148 0x0000001F # P1.18 = D4
- mww 0xE000114C 0x0000001F # P1.19 = D5
- mww 0xE0001150 0x0000001F # P1.20 = D6
- mww 0xE0001154 0x0000001F # P1.21 = D7
- mww 0xE0001200 0x0000001F # P2.0 = D8
- mww 0xE0001204 0x0000001F # P2.1 = D9
- mww 0xE0001208 0x0000001F # P2.2 = D10
- mww 0xE000120C 0x0000001F # P2.3 = D11
- mww 0xE0001210 0x0000001F # P2.4 = D12
- mww 0xE0001214 0x0000001F # P2.5 = D13
- mww 0xE0001218 0x0000001F # P2.6 = D14
- mww 0xE000121C 0x0000001F # P2.7 = D15
- mww 0xE0001104 0x00000007 # P1.1 = A1
- mww 0xE0001108 0x00000007 # P1.2 = A2
- mww 0xE000110C 0x00000007 # P1.3 = A3
- mww 0xE0001110 0x00000007 # P1.4 = A4
- mww 0xE0001114 0x00000007 # P1.5 = A5
- mww 0xE0001118 0x00000007 # P1.6 = A6
- mww 0xE000111C 0x00000007 # P1.7 = A7
- mww 0xE0001028 0x00000007 # P0.10 = A8
- mww 0xE000102C 0x00000007 # P0.11 = A9
- mww 0xE0001030 0x00000007 # P0.12 = A10
- mww 0xE0001034 0x00000007 # P0.13 = A11
- mww 0xE0001038 0x00000007 # P0.14 = A12
- mww 0xE000103C 0x00000007 # P0.15 = A13
- mww 0xE0001048 0x00000007 # P0.18 = A14
- mww 0xE000104C 0x00000007 # P0.19 = A15
- mww 0xE0001050 0x00000007 # P0.20 = A16
- mww 0xE0001054 0x00000007 # P0.21 = A17
- mww 0xE0001058 0x00000007 # P0.22 = A18
- mww 0xE000105C 0x00000007 # P0.23 = A19
- mww 0xE0001238 0x00000007 # P2.14 = BLS0
- mww 0xE000123C 0x00000007 # P2.15 = BLS1
- mww 0xE0001300 0x00000007 # P3.0 = CS6
- mww 0xE0001304 0x00000007 # P3.1 = CS7
- mww 0xE0001130 0x00000007 # P1.12 = OE_N
- mww 0xE0001134 0x00000007 # P1.13 = WE_N
- mww 0x600000BC 0x00000041 # Bank6 16-bit mode, RBLE=1
- mww 0x600000B4 0x00000000 # Bank6 WSTOEN=0
- mww 0x600000AC 0x00000005 # Bank6 WST1=5
- mww 0x600000B8 0x00000001 # Bank6 WSTWEN=1
- mww 0x600000B0 0x00000006 # Bank6 WST2=6
- mww 0x600000A8 0x00000002 # Bank6 IDCY=2
- mww 0x600000D8 0x00000041 # Bank7 16-bit mode, RBLE=1
- mww 0x600000D0 0x00000000 # Bank7 WSTOEN=0
- mww 0x600000C8 0x0000000A # Bank7 WST1=10
- mww 0x600000D4 0x00000001 # Bank7 WSTWEN=1
- mww 0x600000CC 0x0000000C # Bank7 WST2=8
- mww 0x600000C4 0x00000002 # Bank7 IDCY=2
+ mww 0xE0001138 0x0000001F ;# P1.14 = D0
+ mww 0xE000113C 0x0000001F ;# P1.15 = D1
+ mww 0xE0001140 0x0000001F ;# P1.16 = D2
+ mww 0xE0001144 0x0000001F ;# P1.17 = D3
+ mww 0xE0001148 0x0000001F ;# P1.18 = D4
+ mww 0xE000114C 0x0000001F ;# P1.19 = D5
+ mww 0xE0001150 0x0000001F ;# P1.20 = D6
+ mww 0xE0001154 0x0000001F ;# P1.21 = D7
+ mww 0xE0001200 0x0000001F ;# P2.0 = D8
+ mww 0xE0001204 0x0000001F ;# P2.1 = D9
+ mww 0xE0001208 0x0000001F ;# P2.2 = D10
+ mww 0xE000120C 0x0000001F ;# P2.3 = D11
+ mww 0xE0001210 0x0000001F ;# P2.4 = D12
+ mww 0xE0001214 0x0000001F ;# P2.5 = D13
+ mww 0xE0001218 0x0000001F ;# P2.6 = D14
+ mww 0xE000121C 0x0000001F ;# P2.7 = D15
+ mww 0xE0001104 0x00000007 ;# P1.1 = A1
+ mww 0xE0001108 0x00000007 ;# P1.2 = A2
+ mww 0xE000110C 0x00000007 ;# P1.3 = A3
+ mww 0xE0001110 0x00000007 ;# P1.4 = A4
+ mww 0xE0001114 0x00000007 ;# P1.5 = A5
+ mww 0xE0001118 0x00000007 ;# P1.6 = A6
+ mww 0xE000111C 0x00000007 ;# P1.7 = A7
+ mww 0xE0001028 0x00000007 ;# P0.10 = A8
+ mww 0xE000102C 0x00000007 ;# P0.11 = A9
+ mww 0xE0001030 0x00000007 ;# P0.12 = A10
+ mww 0xE0001034 0x00000007 ;# P0.13 = A11
+ mww 0xE0001038 0x00000007 ;# P0.14 = A12
+ mww 0xE000103C 0x00000007 ;# P0.15 = A13
+ mww 0xE0001048 0x00000007 ;# P0.18 = A14
+ mww 0xE000104C 0x00000007 ;# P0.19 = A15
+ mww 0xE0001050 0x00000007 ;# P0.20 = A16
+ mww 0xE0001054 0x00000007 ;# P0.21 = A17
+ mww 0xE0001058 0x00000007 ;# P0.22 = A18
+ mww 0xE000105C 0x00000007 ;# P0.23 = A19
+ mww 0xE0001238 0x00000007 ;# P2.14 = BLS0
+ mww 0xE000123C 0x00000007 ;# P2.15 = BLS1
+ mww 0xE0001300 0x00000007 ;# P3.0 = CS6
+ mww 0xE0001304 0x00000007 ;# P3.1 = CS7
+ mww 0xE0001130 0x00000007 ;# P1.12 = OE_N
+ mww 0xE0001134 0x00000007 ;# P1.13 = WE_N
+ mww 0x600000BC 0x00000041 ;# Bank6 16-bit mode, RBLE=1
+ mww 0x600000B4 0x00000000 ;# Bank6 WSTOEN=0
+ mww 0x600000AC 0x00000005 ;# Bank6 WST1=5
+ mww 0x600000B8 0x00000001 ;# Bank6 WSTWEN=1
+ mww 0x600000B0 0x00000006 ;# Bank6 WST2=6
+ mww 0x600000A8 0x00000002 ;# Bank6 IDCY=2
+ mww 0x600000D8 0x00000041 ;# Bank7 16-bit mode, RBLE=1
+ mww 0x600000D0 0x00000000 ;# Bank7 WSTOEN=0
+ mww 0x600000C8 0x0000000A ;# Bank7 WST1=10
+ mww 0x600000D4 0x00000001 ;# Bank7 WSTWEN=1
+ mww 0x600000CC 0x0000000C ;# Bank7 WST2=8
+ mww 0x600000C4 0x00000002 ;# Bank7 IDCY=2
}
mww 0x53f00004 0x77777777
# clock setup
- mww 0x53F80004 0x00821000 # first need to set IPU_HND_BYP
- mww 0x53F80004 0x00821000 #arm clock is 399Mhz and ahb clock is 133Mhz.
+ mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP
+ mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz.
#=================================================
# WEIM config
mww 0x43FAC474 0x00000006
mww 0x43FAC478 0x00000006
mww 0x43FAC47c 0x00000006
- mww 0x43FAC480 0x00000006 # CSD0
- mww 0x43FAC484 0x00000006 # CSD1
+ mww 0x43FAC480 0x00000006 ;# CSD0
+ mww 0x43FAC484 0x00000006 ;# CSD1
mww 0x43FAC488 0x00000006
mww 0x43FAC48c 0x00000006
mww 0x43FAC490 0x00000006
mww 0x43FAC498 0x00000006
mww 0x43FAC49c 0x00000006
mww 0x43FAC4A0 0x00000006
- mww 0x43FAC4A4 0x00000006 # RAS
- mww 0x43FAC4A8 0x00000006 # CAS
- mww 0x43FAC4Ac 0x00000006 # SDWE
- mww 0x43FAC4B0 0x00000006 # SDCKE0
- mww 0x43FAC4B4 0x00000006 # SDCKE1
- mww 0x43FAC4B8 0x00000002 # SDCLK
+ mww 0x43FAC4A4 0x00000006 ;# RAS
+ mww 0x43FAC4A8 0x00000006 ;# CAS
+ mww 0x43FAC4Ac 0x00000006 ;# SDWE
+ mww 0x43FAC4B0 0x00000006 ;# SDCKE0
+ mww 0x43FAC4B4 0x00000006 ;# SDCKE1
+ mww 0x43FAC4B8 0x00000002 ;# SDCLK
# SDQS0 through SDQS3
mww 0x43FAC4Bc 0x00000082
# DDR2 : Load reg EMR1 -- OCD default
mwb 0x82000780 0xda
# DDR2 : Load reg EMR1 -- OCD exit
- mwb 0x82000400 0xda # ODT disabled
+ mwb 0x82000400 0xda ;# ODT disabled
# ESD_ESDCTL0 : select normal-operation mode
# DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
# Adjust the ESDCDLY5 register
#***********************************************
# Vary DQS_ABS_OFFSET5 for writes
- mww 0xB8001020 0x00F48000 # this is the default value
- mww 0xB8001024 0x00F48000 # this is the default value
- mww 0xB8001028 0x00F48000 # this is the default value
- mww 0xB800102c 0x00F48000 # this is the default value
+ mww 0xB8001020 0x00F48000 ;# this is the default value
+ mww 0xB8001024 0x00F48000 ;# this is the default value
+ mww 0xB8001028 0x00F48000 ;# this is the default value
+ mww 0xB800102c 0x00F48000 ;# this is the default value
#Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
# usb clock are off 12mHz xtal
#-----------------------------------------------
- mww phys 0x4C000014 0x00000005 # Clock Divider control Reg
- mww phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register
- mww phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg
- mww phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg
+ mww phys 0x4C000014 0x00000005 ;# Clock Divider control Reg
+ mww phys 0x4C000000 0xFFFFFFFF ;# LOCKTIME count register
+ mww phys 0x4C000008 0x00038022 ;# UPPLCON USB clock config Reg
+ mww phys 0x4C000004 0x0007F021 ;# MPPLCON Proc clock config Reg
#-----------------------------------------------
# Configure Memory controller
# DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
#-----------------------------------------------
- mww phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width
- mww phys 0x48000010 0x00001112 # BANKCON4 - ?
- mww phys 0x4800001c 0x00018009 # BANKCON6 - DRAM
- mww phys 0x48000020 0x00018009 # BANKCON7 - DRAM
- mww phys 0x48000024 0x008E04EB # REFRESH - DRAM
- mww phys 0x48000028 0x000000B2 # BANKSIZE - DRAM
- mww phys 0x4800002C 0x00000030 # MRSRB6 - DRAM
- mww phys 0x48000030 0x00000030 # MRSRB7 - DRAM
+ mww phys 0x48000000 0x22111112 ;# BWSCON - Bank and Bus Width
+ mww phys 0x48000010 0x00001112 ;# BANKCON4 - ?
+ mww phys 0x4800001c 0x00018009 ;# BANKCON6 - DRAM
+ mww phys 0x48000020 0x00018009 ;# BANKCON7 - DRAM
+ mww phys 0x48000024 0x008E04EB ;# REFRESH - DRAM
+ mww phys 0x48000028 0x000000B2 ;# BANKSIZE - DRAM
+ mww phys 0x4800002C 0x00000030 ;# MRSRB6 - DRAM
+ mww phys 0x48000030 0x00000030 ;# MRSRB7 - DRAM
#-----------------------------------------------
# Now port configuration for enables for memory
# and other stuff.
#-----------------------------------------------
- mww phys 0x56000000 0x007FFFFF # GPACON
+ mww phys 0x56000000 0x007FFFFF ;# GPACON
- mww phys 0x56000010 0x00295559 # GPBCON
- mww phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE)
- mww phys 0x56000014 0x000007C2 # GPBDAT
+ mww phys 0x56000010 0x00295559 ;# GPBCON
+ mww phys 0x56000018 0x000003FF ;# GPBUP (PULLUP ENABLE)
+ mww phys 0x56000014 0x000007C2 ;# GPBDAT
- mww phys 0x56000020 0xAAAAA6AA # GPCCON
- mww phys 0x56000028 0x0000FFFF # GPCUP
- mww phys 0x56000024 0x00000020 # GPCDAT
+ mww phys 0x56000020 0xAAAAA6AA ;# GPCCON
+ mww phys 0x56000028 0x0000FFFF ;# GPCUP
+ mww phys 0x56000024 0x00000020 ;# GPCDAT
- mww phys 0x56000030 0xAAAAAAAA # GPDCON
- mww phys 0x56000038 0x0000FFFF # GPDUP
+ mww phys 0x56000030 0xAAAAAAAA ;# GPDCON
+ mww phys 0x56000038 0x0000FFFF ;# GPDUP
- mww phys 0x56000040 0xAAAAAAAA # GPECON
- mww phys 0x56000048 0x0000FFFF # GPEUP
+ mww phys 0x56000040 0xAAAAAAAA ;# GPECON
+ mww phys 0x56000048 0x0000FFFF ;# GPEUP
- mww phys 0x56000050 0x00001555 # GPFCON
- mww phys 0x56000058 0x0000007F # GPFUP
- mww phys 0x56000054 0x00000000 # GPFDAT
+ mww phys 0x56000050 0x00001555 ;# GPFCON
+ mww phys 0x56000058 0x0000007F ;# GPFUP
+ mww phys 0x56000054 0x00000000 ;# GPFDAT
- mww phys 0x56000060 0x00150114 # GPGCON
- mww phys 0x56000068 0x0000007F # GPGUP
+ mww phys 0x56000060 0x00150114 ;# GPGCON
+ mww phys 0x56000068 0x0000007F ;# GPGUP
- mww phys 0x56000070 0x0015AAAA # GPHCON
- mww phys 0x56000078 0x000003FF # GPGUP
+ mww phys 0x56000070 0x0015AAAA ;# GPHCON
+ mww phys 0x56000078 0x000003FF ;# GPGUP
}
}
$_TARGETNAME configure -event reset-init {
- mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
+ mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
##
# Clock configuration for 99.328 MHz main clock.
##
echo "Setting up clock"
- mww 0xfffffc20 0x00004001 # CKGR_MOR : enable main oscillator, 512 slow clock startup
- sleep 20 # wait 20 ms (need 15.6 ms for startup)
- mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator (18.432 MHz)
- sleep 10 # wait 10 ms
- mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup
- sleep 20 # wait 20 ms (need 1.9 ms for startup)
- mww 0xfffffc30 0x00000101 # PMC_MCKR : no scale on proc clock, master is proc / 2
- sleep 10 # wait 10 ms
- mww 0xfffffc30 0x00000102 # PMC_MCKR : switch to PLLA (99.328 MHz)
+ mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable main oscillator, 512 slow clock startup
+ sleep 20 ;# wait 20 ms (need 15.6 ms for startup)
+ mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator (18.432 MHz)
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup
+ sleep 20 ;# wait 20 ms (need 1.9 ms for startup)
+ mww 0xfffffc30 0x00000101 ;# PMC_MCKR : no scale on proc clock, master is proc / 2
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc30 0x00000102 ;# PMC_MCKR : switch to PLLA (99.328 MHz)
# Increase JTAG speed to 6 MHz if RCLK is not supported.
jtag_rclk 6000
- arm7_9 dcc_downloads enable # Enable faster DCC downloads.
+ arm7_9 dcc_downloads enable ;# Enable faster DCC downloads.
##
# SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
##
echo "Configuring SDRAM"
- mww 0xfffff870 0xffff0000 # PIOC_ASR : select peripheral function for D15..D31
- mww 0xfffff804 0xffff0000 # PIOC_PDR : disable PIO function for D15..D31
+ mww 0xfffff870 0xffff0000 ;# PIOC_ASR : select peripheral function for D15..D31
+ mww 0xfffff804 0xffff0000 ;# PIOC_PDR : disable PIO function for D15..D31
- mww 0xffffef1c 0x00010002 # EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory
+ mww 0xffffef1c 0x00010002 ;# EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory
- mww 0xffffea08 0x85237259 # SDRAMC_CR : configure SDRAM for Samsung chips
+ mww 0xffffea08 0x85237259 ;# SDRAMC_CR : configure SDRAM for Samsung chips
- mww 0xffffea00 0x1 # SDRAMC_MR : issue NOP command
+ mww 0xffffea00 0x1 ;# SDRAMC_MR : issue NOP command
mww 0x20000000 0
- mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
+ mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
mww 0x20000000 0
- mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' command
+ mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' command
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
- mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
+ mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
mww 0x20000000 0
- mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
+ mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
mww 0x20000000 0
- mww 0xffffea04 0x2b6 # SDRAMC_TR : set refresh timer count to 7 us
+ mww 0xffffea04 0x2b6 ;# SDRAMC_TR : set refresh timer count to 7 us
##
# NAND Flash Configuration for 1 x Samsung K9F4G08U0M, 512M x 8Bit.
arm mcr 15 0 0 1 0 0x00052078
- mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
- mww 0xD0001404 0x37543000 # Dunit Control Low Register
- mww 0xD0001408 0x22125451 # DDR SDRAM Timing (Low) Register
- mww 0xD000140C 0x00000A33 # DDR SDRAM Timing (High) Register
- mww 0xD0001410 0x000000CC # DDR SDRAM Address Control Register
- mww 0xD0001414 0x00000000 # DDR SDRAM Open Pages Control Register
- mww 0xD0001418 0x00000000 # DDR SDRAM Operation Register
- mww 0xD000141C 0x00000C52 # DDR SDRAM Mode Register
- mww 0xD0001420 0x00000004 # DDR SDRAM Extended Mode Register
- mww 0xD0001424 0x0000F17F # Dunit Control High Register
- mww 0xD0001428 0x00085520 # Dunit Control High Register
- mww 0xD000147c 0x00008552 # Dunit Control High Register
- mww 0xD0001504 0x0FFFFFF1 # CS0n Size Register
- mww 0xD0001508 0x10000000 # CS1n Base Register
- mww 0xD000150C 0x0FFFFFF5 # CS1n Size Register
- mww 0xD0001514 0x00000000 # CS2n Size Register
- mww 0xD000151C 0x00000000 # CS3n Size Register
- mww 0xD0001494 0x00120012 # DDR2 SDRAM ODT Control (Low) Register
- mww 0xD0001498 0x00000000 # DDR2 SDRAM ODT Control (High) REgister
- mww 0xD000149C 0x0000E40F # DDR2 Dunit ODT Control Register
- mww 0xD0001480 0x00000001 # DDR SDRAM Initialization Control Register
- mww 0xD0020204 0x00000000 # Main IRQ Interrupt Mask Register
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
-
- mww 0xD0010000 0x01111111 # MPP 0 to 7
- mww 0xD0010004 0x11113322 # MPP 8 to 15
- mww 0xD0010008 0x00001111 # MPP 16 to 23
-
- mww 0xD0010418 0x003E07CF # NAND Read Parameters REgister
- mww 0xD001041C 0x000F0F0F # NAND Write Parameters Register
- mww 0xD0010470 0x01C7D943 # NAND Flash Control Register
+ mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
+ mww 0xD0001404 0x37543000 ;# Dunit Control Low Register
+ mww 0xD0001408 0x22125451 ;# DDR SDRAM Timing (Low) Register
+ mww 0xD000140C 0x00000A33 ;# DDR SDRAM Timing (High) Register
+ mww 0xD0001410 0x000000CC ;# DDR SDRAM Address Control Register
+ mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
+ mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
+ mww 0xD000141C 0x00000C52 ;# DDR SDRAM Mode Register
+ mww 0xD0001420 0x00000004 ;# DDR SDRAM Extended Mode Register
+ mww 0xD0001424 0x0000F17F ;# Dunit Control High Register
+ mww 0xD0001428 0x00085520 ;# Dunit Control High Register
+ mww 0xD000147c 0x00008552 ;# Dunit Control High Register
+ mww 0xD0001504 0x0FFFFFF1 ;# CS0n Size Register
+ mww 0xD0001508 0x10000000 ;# CS1n Base Register
+ mww 0xD000150C 0x0FFFFFF5 ;# CS1n Size Register
+ mww 0xD0001514 0x00000000 ;# CS2n Size Register
+ mww 0xD000151C 0x00000000 ;# CS3n Size Register
+ mww 0xD0001494 0x00120012 ;# DDR2 SDRAM ODT Control (Low) Register
+ mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
+ mww 0xD000149C 0x0000E40F ;# DDR2 Dunit ODT Control Register
+ mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register
+ mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+
+ mww 0xD0010000 0x01111111 ;# MPP 0 to 7
+ mww 0xD0010004 0x11113322 ;# MPP 8 to 15
+ mww 0xD0010008 0x00001111 ;# MPP 16 to 23
+
+ mww 0xD0010418 0x003E07CF ;# NAND Read Parameters REgister
+ mww 0xD001041C 0x000F0F0F ;# NAND Write Parameters Register
+ mww 0xD0010470 0x01C7D943 ;# NAND Flash Control Register
}
jtag_rclk 4
# Enable user reset and disable watchdog
- mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
- mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
+ mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset
+ mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
# Oscillator setup
- mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator (18.432 MHz)
- sleep 20 # wait 20 ms
- mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
- sleep 10 # wait 10 ms
+ mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator (18.432 MHz)
+ sleep 20 ;# wait 20 ms
+ mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
+ sleep 10 ;# wait 10 ms
# now we are running at 18.432 MHz kHz => 1/8 * 18.432 MHz = 2.304 MHz
jtag_rclk 2000
- mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz
- sleep 20 # wait 20 ms
- mww 0xfffffc2c 0x207c3f0c # CKGR_PLLBR: Set PLLB Register for USB usage (USB_CLK = 48 MHz)
- sleep 10 # wait 10 ms
- mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler
- sleep 10 # wait 10 ms
- mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
- sleep 10 # wait 10 ms
+ mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
+ sleep 20 ;# wait 20 ms
+ mww 0xfffffc2c 0x207c3f0c ;# CKGR_PLLBR: Set PLLB Register for USB usage (USB_CLK = 48 MHz)
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected
+ sleep 10 ;# wait 10 ms
# now we are running at 198.656 MHz kHz => full speed jtag
jtag_rclk 30000
- arm7_9 dcc_downloads enable # Enable faster DCC downloads
+ arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
# Configure PIO Controller for SDRAM data-lines D16-D31
# PC16-PC31 = Peripheral A: D16-D32
- mww 0xfffff844 0xffff0000 # Interrupt Disable
- mww 0xfffff854 0xffff0000 # Multi-Drive Disable
- mww 0xfffff860 0xffff0000 # Pull-Up Disable
- mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral A function for D15..D31
- mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31 (Peripheral function enable)
- mww 0xfffffc10 0x00000010 # Enable PIO-C Clock in PMC (PID=4)
+ mww 0xfffff844 0xffff0000 ;# Interrupt Disable
+ mww 0xfffff854 0xffff0000 ;# Multi-Drive Disable
+ mww 0xfffff860 0xffff0000 ;# Pull-Up Disable
+ mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral A function for D15..D31
+ mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31 (Peripheral function enable)
+ mww 0xfffffc10 0x00000010 ;# Enable PIO-C Clock in PMC (PID=4)
# SD-Ram setup
- mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
- mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (IS42S32160A: 4M Words x 32 Bits x 4 Banks (512-Mbit))
- mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
+ mww 0xffffef1c 0x2 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
+ mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (IS42S32160A: 4M Words x 32 Bits x 4 Banks (512-Mbit))
+ mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
mww 0x20000000 0
- mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
+ mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
mww 0x20000000 0
- mww 0xffffea00 0x4 # SDRAMC_MR : issue an 'Auto-Refresh' command (1st)
+ mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (1st)
mww 0x20000000 0
- mww 0xffffea00 0x4 # SDRAMC_MR : issue an 'Auto-Refresh' command (2nd)
+ mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (2nd)
mww 0x20000000 0
- mww 0xffffea00 0x4 # SDRAMC_MR : issue an 'Auto-Refresh' command (3th)
+ mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (3th)
mww 0x20000000 0
- mww 0xffffea00 0x4 # SDRAMC_MR : issue an 'Auto-Refresh' command (4th)
+ mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (4th)
mww 0x20000000 0
- mww 0xffffea00 0x4 # SDRAMC_MR : issue an 'Auto-Refresh' command (5th)
+ mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (5th)
mww 0x20000000 0
- mww 0xffffea00 0x4 # SDRAMC_MR : issue an 'Auto-Refresh' command (6th)
+ mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (6th)
mww 0x20000000 0
- mww 0xffffea00 0x4 # SDRAMC_MR : issue an 'Auto-Refresh' command (7th)
+ mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (7th)
mww 0x20000000 0
- mww 0xffffea00 0x4 # SDRAMC_MR : issue an 'Auto-Refresh' command (8th)
+ mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (8th)
mww 0x20000000 0
- mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
+ mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
mww 0x20000000 0
- mww 0xffffea00 0x0 # SDRAMC_MR : Normal Mode
+ mww 0xffffea00 0x0 ;# SDRAMC_MR : Normal Mode
mww 0x20000000 0
- mww 0xFFFFEA04 0x30d # SDRAM Refresh Time Register
- # datasheet: 8k refresh cycles / 64 ms
- # MCLK / (8*1024 / 64e-3) = 100e6 / 128000 = 781 = 0x30d
+ mww 0xFFFFEA04 0x30d ;# SDRAM Refresh Time Register
+ # datasheet: 8k refresh cycles / 64 ms
+ # MCLK / (8*1024 / 64e-3) = 100e6 / 128000 = 781 = 0x30d
}
flash bank $_FLASHNAME cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
proc pxa255_sst_init {} {
- xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
+ xscale cp15 15 0x00002001 ;#Enable CP0 and CP13 access
#
# setup GPIO
#
- mww 0x40E00018 0x00008000 #CPSR0
+ mww 0x40E00018 0x00008000 ;#CPSR0
sleep 20
- mww 0x40E0001C 0x00000002 #GPSR1
+ mww 0x40E0001C 0x00000002 ;#GPSR1
sleep 20
- mww 0x40E00020 0x00000008 #GPSR2
+ mww 0x40E00020 0x00000008 ;#GPSR2
sleep 20
- mww 0x40E0000C 0x00008000 #GPDR0
+ mww 0x40E0000C 0x00008000 ;#GPDR0
sleep 20
- mww 0x40E00054 0x80000000 #GAFR0_L
+ mww 0x40E00054 0x80000000 ;#GAFR0_L
sleep 20
- mww 0x40E00058 0x00188010 #GAFR0_H
+ mww 0x40E00058 0x00188010 ;#GAFR0_H
sleep 20
- mww 0x40E0005C 0x60908018 #GAFR1_L
+ mww 0x40E0005C 0x60908018 ;#GAFR1_L
sleep 20
- mww 0x40E0000C 0x0280E000 #GPDR0
+ mww 0x40E0000C 0x0280E000 ;#GPDR0
sleep 20
- mww 0x40E00010 0x821C88B2 #GPDR1
+ mww 0x40E00010 0x821C88B2 ;#GPDR1
sleep 20
- mww 0x40E00014 0x000F03DB #GPDR2
+ mww 0x40E00014 0x000F03DB ;#GPDR2
sleep 20
- mww 0x40E00000 0x000F03DB #GPLR0
+ mww 0x40E00000 0x000F03DB ;#GPLR0
sleep 20
- mww 0x40F00004 0x00000020 #PSSR
+ mww 0x40F00004 0x00000020 ;#PSSR
sleep 20
#
# setup memory controller
#
- mww 0x48000008 0x01111998 #MSC0
+ mww 0x48000008 0x01111998 ;#MSC0
sleep 20
- mww 0x48000010 0x00047ff0 #MSC2
+ mww 0x48000010 0x00047ff0 ;#MSC2
sleep 20
- mww 0x48000014 0x00000000 #MECR
+ mww 0x48000014 0x00000000 ;#MECR
sleep 20
- mww 0x48000028 0x00010504 #MCMEM0
+ mww 0x48000028 0x00010504 ;#MCMEM0
sleep 20
- mww 0x4800002C 0x00010504 #MCMEM1
+ mww 0x4800002C 0x00010504 ;#MCMEM1
sleep 20
- mww 0x48000030 0x00010504 #MCATT0
+ mww 0x48000030 0x00010504 ;#MCATT0
sleep 20
- mww 0x48000034 0x00010504 #MCATT1
+ mww 0x48000034 0x00010504 ;#MCATT1
sleep 20
- mww 0x48000038 0x00004715 #MCIO0
+ mww 0x48000038 0x00004715 ;#MCIO0
sleep 20
- mww 0x4800003C 0x00004715 #MCIO1
+ mww 0x4800003C 0x00004715 ;#MCIO1
sleep 20
#
- mww 0x48000004 0x03CA4018 #MDREF
+ mww 0x48000004 0x03CA4018 ;#MDREF
sleep 20
- mww 0x48000004 0x004B4018 #MDREF
+ mww 0x48000004 0x004B4018 ;#MDREF
sleep 20
- mww 0x48000004 0x000B4018 #MDREF
+ mww 0x48000004 0x000B4018 ;#MDREF
sleep 20
- mww 0x48000004 0x000BC018 #MDREF
+ mww 0x48000004 0x000BC018 ;#MDREF
sleep 20
- mww 0x48000000 0x00001AC8 #MDCNFG
+ mww 0x48000000 0x00001AC8 ;#MDCNFG
sleep 20
sleep 20
- mww 0x48000000 0x00001AC9 #MDCNFG
+ mww 0x48000000 0x00001AC9 ;#MDCNFG
sleep 20
- mww 0x48000040 0x00000000 #MDMRS
+ mww 0x48000040 0x00000000 ;#MDMRS
sleep 20
}
adapter_nsrst_delay 200
jtag_ntrst_delay 200
-#xscale debug_handler 0 0xFFFF0800 # debug handler base address
+#xscale debug_handler 0 0xFFFF0800 ;# debug handler base address
# switch on PLL for 200MHz operation
# running from 15MHz input clock
- mww 0xB0000200 0x00000030 # CLKEN
- mww 0xB0000204 0x00000f3c # CLKSEL
- mww 0xB0000208 0x05007000 # CLKDIV
- mww 0xB000020C 0x00004f24 # PLLCON0
- mww 0xB0000210 0x00002b63 # PLLCON1
- mww 0xB000000C 0x08817fa6 # MFSEL
+ mww 0xB0000200 0x00000030 ;# CLKEN
+ mww 0xB0000204 0x00000f3c ;# CLKSEL
+ mww 0xB0000208 0x05007000 ;# CLKDIV
+ mww 0xB000020C 0x00004f24 ;# PLLCON0
+ mww 0xB0000210 0x00002b63 ;# PLLCON1
+ mww 0xB000000C 0x08817fa6 ;# MFSEL
sleep 10
# we are now running @ 200MHz
# map nor flash to 0x20000000
# map sdram to 0x00000000
- mww 0xb0001000 0x000530c1 # EBICON
- mww 0xb0001004 0x40030084 # ROMCON
- mww 0xb0001008 0x000010ee # SDCONF0
- mww 0xb000100C 0x00000000 # SDCONF1
- mww 0xb0001010 0x0000015b # SDTIME0
- mww 0xb0001014 0x0000015b # SDTIME1
- mww 0xb0001018 0x00000000 # EXT0CON
- mww 0xb000101C 0x00000000 # EXT1CON
- mww 0xb0001020 0x00000000 # EXT2CON
- mww 0xb0001024 0x00000000 # EXT3CON
- mww 0xb000102c 0x00ff0048 # CKSKEW
+ mww 0xb0001000 0x000530c1 ;# EBICON
+ mww 0xb0001004 0x40030084 ;# ROMCON
+ mww 0xb0001008 0x000010ee ;# SDCONF0
+ mww 0xb000100C 0x00000000 ;# SDCONF1
+ mww 0xb0001010 0x0000015b ;# SDTIME0
+ mww 0xb0001014 0x0000015b ;# SDTIME1
+ mww 0xb0001018 0x00000000 ;# EXT0CON
+ mww 0xb000101C 0x00000000 ;# EXT1CON
+ mww 0xb0001020 0x00000000 ;# EXT2CON
+ mww 0xb0001024 0x00000000 ;# EXT3CON
+ mww 0xb000102c 0x00ff0048 ;# CKSKEW
}
arm mcr 15 0 0 1 0 0x00052078
- mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
- mww 0xD0001404 0x39543000 # Dunit Control Low Register
- mww 0xD0001408 0x22125451 # DDR SDRAM Timing (Low) Register
- mww 0xD000140C 0x00000833 # DDR SDRAM Timing (High) Register
- mww 0xD0001410 0x000000CC # DDR SDRAM Address Control Register
- mww 0xD0001414 0x00000000 # DDR SDRAM Open Pages Control Register
- mww 0xD0001418 0x00000000 # DDR SDRAM Operation Register
- mww 0xD000141C 0x00000C52 # DDR SDRAM Mode Register
- mww 0xD0001420 0x00000042 # DDR SDRAM Extended Mode Register
- mww 0xD0001424 0x0000F17F # Dunit Control High Register
- mww 0xD0001428 0x00085520 # Dunit Control High Register
- mww 0xD000147c 0x00008552 # Dunit Control High Register
- mww 0xD0001504 0x0FFFFFF1 # CS0n Size Register
- mww 0xD0001508 0x10000000 # CS1n Base Register
- mww 0xD000150C 0x0FFFFFF5 # CS1n Size Register
- mww 0xD0001514 0x00000000 # CS2n Size Register
- mww 0xD000151C 0x00000000 # CS3n Size Register
- mww 0xD0001494 0x003C0000 # DDR2 SDRAM ODT Control (Low) Register
- mww 0xD0001498 0x00000000 # DDR2 SDRAM ODT Control (High) REgister
- mww 0xD000149C 0x0000F80F # DDR2 Dunit ODT Control Register
- mww 0xD0001480 0x00000001 # DDR SDRAM Initialization Control Register
- mww 0xD0020204 0x00000000 # Main IRQ Interrupt Mask Register
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
- mww 0xD0020204 0x00000000 # "
-
- mww 0xD0010000 0x01111111 # MPP 0 to 7
- mww 0xD0010004 0x11113322 # MPP 8 to 15
- mww 0xD0010008 0x00001111 # MPP 16 to 23
-
- mww 0xD0010418 0x003E07CF # NAND Read Parameters REgister
- mww 0xD001041C 0x000F0F0F # NAND Write Parameters Register
- mww 0xD0010470 0x01C7D943 # NAND Flash Control Register
+ mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
+ mww 0xD0001404 0x39543000 ;# Dunit Control Low Register
+ mww 0xD0001408 0x22125451 ;# DDR SDRAM Timing (Low) Register
+ mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
+ mww 0xD0001410 0x000000CC ;# DDR SDRAM Address Control Register
+ mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
+ mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
+ mww 0xD000141C 0x00000C52 ;# DDR SDRAM Mode Register
+ mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register
+ mww 0xD0001424 0x0000F17F ;# Dunit Control High Register
+ mww 0xD0001428 0x00085520 ;# Dunit Control High Register
+ mww 0xD000147c 0x00008552 ;# Dunit Control High Register
+ mww 0xD0001504 0x0FFFFFF1 ;# CS0n Size Register
+ mww 0xD0001508 0x10000000 ;# CS1n Base Register
+ mww 0xD000150C 0x0FFFFFF5 ;# CS1n Size Register
+ mww 0xD0001514 0x00000000 ;# CS2n Size Register
+ mww 0xD000151C 0x00000000 ;# CS3n Size Register
+ mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
+ mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
+ mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register
+ mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register
+ mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+ mww 0xD0020204 0x00000000 ;# "
+
+ mww 0xD0010000 0x01111111 ;# MPP 0 to 7
+ mww 0xD0010004 0x11113322 ;# MPP 8 to 15
+ mww 0xD0010008 0x00001111 ;# MPP 16 to 23
+
+ mww 0xD0010418 0x003E07CF ;# NAND Read Parameters REgister
+ mww 0xD001041C 0x000F0F0F ;# NAND Write Parameters Register
+ mww 0xD0010470 0x01C7D943 ;# NAND Flash Control Register
}
$_TARGETNAME configure -event reset-init { spear310evb20_init }
proc spear310evb20_init {} {
- reg pc 0xffff0020 # loop forever
+ reg pc 0xffff0020 ;# loop forever
sp3xx_clock_default
sp3xx_common_init
$_TARGETNAME configure -event reset-deassert-post {
# Force target into ARM state.
-# soft_reset_halt # not implemented on ARM11
+# soft_reset_halt ;# not implemented on ARM11
echo "Detected SRSRT asserted on C100.CPU"
}
flash bank $_FLASHNAME cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
# writing data to memory does not work without this
-arm11 memwrite burst disable
\ No newline at end of file
+arm11 memwrite burst disable
}
# comment the following out if usinf J-Link, it soes not support DCC
-arm7_9 dcc_downloads enable # Enable faster DCC downloads
+arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
#####################
}
# comment the following out if usinf J-Link, it soes not support DCC
-arm7_9 dcc_downloads enable # Enable faster DCC downloads
+arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
#####################
$_TARGETNAME configure -event reset-init {
- mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
-
- mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
- sleep 20 # wait 20 ms
- mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
- sleep 10 # wait 10 ms
- mww 0xfffffc28 0x205dbf09 # CKGR_PLLAR: Set PLLA Register for 192.512MHz
- sleep 20 # wait 20 ms
- mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler (divide by 2)
- sleep 10 # wait 10 ms
- mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected (96.256 MHz)
- sleep 10 # wait 10 ms
+ mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
+
+ mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
+ sleep 20 ;# wait 20 ms
+ mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc28 0x205dbf09 ;# CKGR_PLLAR: Set PLLA Register for 192.512MHz
+ sleep 20 ;# wait 20 ms
+ mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2)
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected (96.256 MHz)
+ sleep 10 ;# wait 10 ms
# Increase JTAG Speed to 6 MHz if RCLK is not supported
jtag_rclk 6000
- arm7_9 dcc_downloads enable # Enable faster DCC downloads
+ arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
- mww 0xffffec00 0x01020102 # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
- mww 0xffffec04 0x09070806 # SMC_PULSE0
- mww 0xffffec08 0x000d000b # SMC_CYCLE0
- mww 0xffffec0c 0x00001003 # SMC_MODE0
+ mww 0xffffec00 0x01020102 ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
+ mww 0xffffec04 0x09070806 ;# SMC_PULSE0
+ mww 0xffffec08 0x000d000b ;# SMC_CYCLE0
+ mww 0xffffec0c 0x00001003 ;# SMC_MODE0
- flash probe 0 # Identify flash bank 0
+ flash probe 0 ;# Identify flash bank 0
- mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
- mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
- mww 0xfffff860 0xffff0000 # PIO_PUDR : Disable D15..D31 pull-ups
+ mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
+ mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
+ mww 0xfffff860 0xffff0000 ;# PIO_PUDR : Disable D15..D31 pull-ups
- mww 0xffffef1c 0x00010102 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
- # VDDIOMSEL set for +3V3 memory
- # Disable D0..D15 pull-ups
+ mww 0xffffef1c 0x00010102 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
+ # VDDIOMSEL set for +3V3 memory
+ # Disable D0..D15 pull-ups
- mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
+ mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
- mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
+ mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
mww 0x20000000 0
- mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
+ mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
mww 0x20000000 0
- mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+ mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
- mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
+ mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
mww 0x20000000 0
- mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
+ mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
mww 0x20000000 0
- mww 0xffffea04 0x2a2 # SDRAMC_TR : Set refresh timer count to 7us
+ mww 0xffffea04 0x2a2 ;# SDRAMC_TR : Set refresh timer count to 7us
}
proc sp310_init {} {
- mww 0xfca80034 0x0000ffff # enable all RAS clocks
- mww 0xfca80040 0x00000000 # remove all RAS resets
- mww 0xb4000008 0x00002ff4 # RAS function enable
+ mww 0xfca80034 0x0000ffff ;# enable all RAS clocks
+ mww 0xfca80040 0x00000000 ;# remove all RAS resets
+ mww 0xb4000008 0x00002ff4 ;# RAS function enable
- mww 0xfca8013c 0x2f7bc210 # plgpio_pad_drv
+ mww 0xfca8013c 0x2f7bc210 ;# plgpio_pad_drv
mww 0xfca80140 0x017bdef6
}
mmw 0xfca8013c 0x00039ce7 0x00000000
# set safe EMI timing as in BootROM
- #mww 0x4f000000 0x0000000f # tAP_0_reg
- #mww 0x4f000004 0x00000000 # tSDP_0_reg
- #mww 0x4f000008 0x000000ff # tDPw_0_reg
- #mww 0x4f00000c 0x00000111 # tDPr_0_reg
- #mww 0x4f000010 0x00000002 # tDCS_0_reg
+ #mww 0x4f000000 0x0000000f ;# tAP_0_reg
+ #mww 0x4f000004 0x00000000 ;# tSDP_0_reg
+ #mww 0x4f000008 0x000000ff ;# tDPw_0_reg
+ #mww 0x4f00000c 0x00000111 ;# tDPr_0_reg
+ #mww 0x4f000010 0x00000002 ;# tDCS_0_reg
# set fast EMI timing as in Linux
- mww 0x4f000000 0x00000010 # tAP_0_reg
- mww 0x4f000004 0x00000005 # tSDP_0_reg
- mww 0x4f000008 0x0000000a # tDPw_0_reg
- mww 0x4f00000c 0x0000000a # tDPr_0_reg
- mww 0x4f000010 0x00000005 # tDCS_0_re
+ mww 0x4f000000 0x00000010 ;# tAP_0_reg
+ mww 0x4f000004 0x00000005 ;# tSDP_0_reg
+ mww 0x4f000008 0x0000000a ;# tDPw_0_reg
+ mww 0x4f00000c 0x0000000a ;# tDPr_0_reg
+ mww 0x4f000010 0x00000005 ;# tDCS_0_re
# 32bit wide, 8/16/32bit access
- mww 0x4f000014 0x0000000e # control_0_reg
- mww 0x4f000094 0x0000003f # ack_reg
+ mww 0x4f000014 0x0000000e ;# control_0_reg
+ mww 0x4f000094 0x0000003f ;# ack_reg
}
# - HCLK = 166 MHz
# - PCLK = 83 MHz
proc sp3xx_clock_default {} {
- mww 0xfca00000 0x00000002 # set sysclk slow
- mww 0xfca00014 0x0ffffff8 # set pll timeout to minimum (100us ?!?)
+ mww 0xfca00000 0x00000002 ;# set sysclk slow
+ mww 0xfca00014 0x0ffffff8 ;# set pll timeout to minimum (100us ?!?)
# DDRCORE disable to change frequency
set val [expr ([mrw 0xfca8002c] & ~0x20000000) | 0x40000000]
mww 0xfca8002c $val
- mww 0xfca8002c $val # Yes, write twice!
+ mww 0xfca8002c $val ;# Yes, write twice!
# programming PLL1
- mww 0xfca8000c 0xa600010c # M=166 P=1 N=12
- mww 0xfca80008 0x00001c0a # power down
- mww 0xfca80008 0x00001c0e # enable
- mww 0xfca80008 0x00001c06 # strobe
+ mww 0xfca8000c 0xa600010c ;# M=166 P=1 N=12
+ mww 0xfca80008 0x00001c0a ;# power down
+ mww 0xfca80008 0x00001c0e ;# enable
+ mww 0xfca80008 0x00001c06 ;# strobe
mww 0xfca80008 0x00001c0e
while { [expr [mrw 0xfca80008] & 0x01] == 0x00 } { sleep 1 }
# programming PLL2
- mww 0xfca80018 0xa600010c # M=166, P=1, N=12
- mww 0xfca80014 0x00001c0a # power down
- mww 0xfca80014 0x00001c0e # enable
- mww 0xfca80014 0x00001c06 # strobe
+ mww 0xfca80018 0xa600010c ;# M=166, P=1, N=12
+ mww 0xfca80014 0x00001c0a ;# power down
+ mww 0xfca80014 0x00001c0e ;# enable
+ mww 0xfca80014 0x00001c06 ;# strobe
mww 0xfca80014 0x00001c0e
while { [expr [mrw 0xfca80014] & 0x01] == 0x00 } { sleep 1 }
- mww 0xfca80028 0x00000082 # enable plltimeen
- mww 0xfca80024 0x00000511 # set hclkdiv="/2" & pclkdiv="/2"
+ mww 0xfca80028 0x00000082 ;# enable plltimeen
+ mww 0xfca80024 0x00000511 ;# set hclkdiv="/2" & pclkdiv="/2"
- mww 0xfca00000 0x00000004 # setting SYSCTL to NORMAL mode
+ mww 0xfca00000 0x00000004 ;# setting SYSCTL to NORMAL mode
while { [expr [mrw 0xfca00000] & 0x20] != 0x20 } { sleep 1 }
# Select source of DDR clock
}
proc sp3xx_common_init {} {
- mww 0xfca8002c 0xfffffff8 # enable clock of all peripherals
- mww 0xfca80038 0x00000000 # remove reset of all peripherals
+ mww 0xfca8002c 0xfffffff8 ;# enable clock of all peripherals
+ mww 0xfca80038 0x00000000 ;# remove reset of all peripherals
- mww 0xfca800e4 0x78000008 # COMP1V8_REG
- mww 0xfca800ec 0x78000008 # COMP3V3_REG
+ mww 0xfca800e4 0x78000008 ;# COMP1V8_REG
+ mww 0xfca800ec 0x78000008 ;# COMP3V3_REG
- mww 0xfca80050 0x00000001 # Enable clk mem port 1
+ mww 0xfca80050 0x00000001 ;# Enable clk mem port 1
- mww 0xfc000000 0x10000f5f # init SMI and set HW mode
+ mww 0xfc000000 0x10000f5f ;# init SMI and set HW mode
mww 0xfc000000 0x00000f5f
# Initialize Bus Interconnection Matrix
# Use "1:2 sync" only when DDR clock source is PLL1 and
# HCLK is half of PLL1
- mww 0xfc600000 0x00000001 # MEMCTL_AHB_SET_00 # This is async
- mww 0xfc600004 0x00000000 # MEMCTL_AHB_SET_01
-# mww 0xfc600000 0x02020201 # MEMCTL_AHB_SET_00 # This is 1:2 sync
-# mww 0xfc600004 0x02020202 # MEMCTL_AHB_SET_01
+ mww 0xfc600000 0x00000001 ;# MEMCTL_AHB_SET_00 # This is async
+ mww 0xfc600004 0x00000000 ;# MEMCTL_AHB_SET_01
+# mww 0xfc600000 0x02020201 ;# MEMCTL_AHB_SET_00 # This is 1:2 sync
+# mww 0xfc600004 0x02020202 ;# MEMCTL_AHB_SET_01
- mww 0xfc600008 0x01000000 # MEMCTL_RFSH_SET_00
- mww 0xfc60000c 0x00000101 # MEMCTL_DLL_SET_00
- mww 0xfc600010 0x00000101 # MEMCTL_GP_00
- mww 0xfc600014 0x01000000 # MEMCTL_GP_01
- mww 0xfc600018 0x00010001 # MEMCTL_GP_02
- mww 0xfc60001c 0x00000100 # MEMCTL_GP_03
- mww 0xfc600020 0x00010001 # MEMCTL_GP_04
- mww 0xfc600024 0x01020203 # MEMCTL_GP_05
- mww 0xfc600028 0x01000102 # MEMCTL_GP_06
- mww 0xfc60002c 0x02000202 # MEMCTL_AHB_SET_02
- mww 0xfc600030 0x04040105 # MEMCTL_AHB_SET_03
- mww 0xfc600034 0x03030302 # MEMCTL_AHB_SET_04
- mww 0xfc600038 0x02040101 # MEMCTL_AHB_SET_05
- mww 0xfc60003c 0x00000002 # MEMCTL_AHB_SET_06
- mww 0xfc600044 0x03000405 # MEMCTL_DQS_SET_0
- mww 0xfc600048 0x03040002 # MEMCTL_TIME_SET_01
- mww 0xfc60004c 0x04000305 # MEMCTL_TIME_SET_02
- mww 0xfc600050 0x0505053f # MEMCTL_AHB_RELPR_00
- mww 0xfc600054 0x05050505 # MEMCTL_AHB_RELPR_01
- mww 0xfc600058 0x04040405 # MEMCTL_AHB_RELPR_02
- mww 0xfc60005c 0x04040404 # MEMCTL_AHB_RELPR_03
- mww 0xfc600060 0x03030304 # MEMCTL_AHB_RELPR_04
- mww 0xfc600064 0x03030303 # MEMCTL_AHB_RELPR_05
- mww 0xfc600068 0x02020203 # MEMCTL_AHB_RELPR_06
- mww 0xfc60006c 0x02020202 # MEMCTL_AHB_RELPR_07
- mww 0xfc600070 0x01010102 # MEMCTL_AHB_RELPR_08
- mww 0xfc600074 0x01010101 # MEMCTL_AHB_RELPR_09
- mww 0xfc600078 0x00000001 # MEMCTL_AHB_RELPR_10
- mww 0xfc600088 0x0a0c0a00 # MEMCTL_DQS_SET_1
- mww 0xfc60008c 0x0000023f # MEMCTL_GP_07
- mww 0xfc600090 0x00050a00 # MEMCTL_GP_08
- mww 0xfc600094 0x11000000 # MEMCTL_GP_09
- mww 0xfc600098 0x00001302 # MEMCTL_GP_10
- mww 0xfc60009c 0x00001c1c # MEMCTL_DLL_SET_01
- mww 0xfc6000a0 0x7c000000 # MEMCTL_DQS_OUT_SHIFT
- mww 0xfc6000a4 0x005c0000 # MEMCTL_WR_DQS_SHIFT
- mww 0xfc6000a8 0x2b050e00 # MEMCTL_TIME_SET_03
- mww 0xfc6000ac 0x00640064 # MEMCTL_AHB_PRRLX_00
- mww 0xfc6000b0 0x00640064 # MEMCTL_AHB_PRRLX_01
- mww 0xfc6000b4 0x00000064 # MEMCTL_AHB_PRRLX_02
- mww 0xfc6000b8 0x00000000 # MEMCTL_OUTRANGE_LGTH
- mww 0xfc6000bc 0x00200020 # MEMCTL_AHB_RW_SET_00
- mww 0xfc6000c0 0x00200020 # MEMCTL_AHB_RW_SET_01
- mww 0xfc6000c4 0x00200020 # MEMCTL_AHB_RW_SET_02
- mww 0xfc6000c8 0x00200020 # MEMCTL_AHB_RW_SET_03
- mww 0xfc6000cc 0x00200020 # MEMCTL_AHB_RW_SET_04
- mww 0xfc6000d8 0x00000a24 # MEMCTL_TREF
- mww 0xfc6000dc 0x00000000 # MEMCTL_EMRS3_DATA
- mww 0xfc6000e0 0x5b1c00c8 # MEMCTL_TIME_SET_04
- mww 0xfc6000e4 0x00c8002e # MEMCTL_TIME_SET_05
- mww 0xfc6000e8 0x00000000 # MEMCTL_VERSION
- mww 0xfc6000ec 0x0001046b # MEMCTL_TINIT
- mww 0xfc6000f0 0x00000000 # MEMCTL_OUTRANGE_ADDR_01
- mww 0xfc6000f4 0x00000000 # MEMCTL_OUTRANGE_ADDR_02
- mww 0xfc600104 0x001c0000 # MEMCTL_DLL_DQS_DELAY_BYPASS_0
- mww 0xfc600108 0x0019001c # MEMCTL_DLL_SET_02
- mww 0xfc60010c 0x00100000 # MEMCTL_DLL_SET_03
- mww 0xfc600110 0x001e007a # MEMCTL_DQS_SET_2
- mww 0xfc600188 0x00000000 # MEMCTL_USER_DEF_REG_0
- mww 0xfc60018c 0x00000000 # MEMCTL_USER_DEF_REG_1
- mww 0xfc600190 0x01010001 # MEMCTL_GP_11
- mww 0xfc600194 0x01000000 # MEMCTL_GP_12
- mww 0xfc600198 0x00000001 # MEMCTL_GP_13
- mww 0xfc60019c 0x00400000 # MEMCTL_GP_14
- mww 0xfc6001a0 0x00000000 # MEMCTL_EMRS2_DATA_X
- mww 0xfc6001a4 0x00000000 # MEMCTL_LWPWR_CNT
- mww 0xfc6001a8 0x00000000 # MEMCTL_LWPWR_REG
- mww 0xfc6001ac 0x00860000 # MEMCTL_GP_15
- mww 0xfc6001b0 0x00000002 # MEMCTL_TPDEX
+ mww 0xfc600008 0x01000000 ;# MEMCTL_RFSH_SET_00
+ mww 0xfc60000c 0x00000101 ;# MEMCTL_DLL_SET_00
+ mww 0xfc600010 0x00000101 ;# MEMCTL_GP_00
+ mww 0xfc600014 0x01000000 ;# MEMCTL_GP_01
+ mww 0xfc600018 0x00010001 ;# MEMCTL_GP_02
+ mww 0xfc60001c 0x00000100 ;# MEMCTL_GP_03
+ mww 0xfc600020 0x00010001 ;# MEMCTL_GP_04
+ mww 0xfc600024 0x01020203 ;# MEMCTL_GP_05
+ mww 0xfc600028 0x01000102 ;# MEMCTL_GP_06
+ mww 0xfc60002c 0x02000202 ;# MEMCTL_AHB_SET_02
+ mww 0xfc600030 0x04040105 ;# MEMCTL_AHB_SET_03
+ mww 0xfc600034 0x03030302 ;# MEMCTL_AHB_SET_04
+ mww 0xfc600038 0x02040101 ;# MEMCTL_AHB_SET_05
+ mww 0xfc60003c 0x00000002 ;# MEMCTL_AHB_SET_06
+ mww 0xfc600044 0x03000405 ;# MEMCTL_DQS_SET_0
+ mww 0xfc600048 0x03040002 ;# MEMCTL_TIME_SET_01
+ mww 0xfc60004c 0x04000305 ;# MEMCTL_TIME_SET_02
+ mww 0xfc600050 0x0505053f ;# MEMCTL_AHB_RELPR_00
+ mww 0xfc600054 0x05050505 ;# MEMCTL_AHB_RELPR_01
+ mww 0xfc600058 0x04040405 ;# MEMCTL_AHB_RELPR_02
+ mww 0xfc60005c 0x04040404 ;# MEMCTL_AHB_RELPR_03
+ mww 0xfc600060 0x03030304 ;# MEMCTL_AHB_RELPR_04
+ mww 0xfc600064 0x03030303 ;# MEMCTL_AHB_RELPR_05
+ mww 0xfc600068 0x02020203 ;# MEMCTL_AHB_RELPR_06
+ mww 0xfc60006c 0x02020202 ;# MEMCTL_AHB_RELPR_07
+ mww 0xfc600070 0x01010102 ;# MEMCTL_AHB_RELPR_08
+ mww 0xfc600074 0x01010101 ;# MEMCTL_AHB_RELPR_09
+ mww 0xfc600078 0x00000001 ;# MEMCTL_AHB_RELPR_10
+ mww 0xfc600088 0x0a0c0a00 ;# MEMCTL_DQS_SET_1
+ mww 0xfc60008c 0x0000023f ;# MEMCTL_GP_07
+ mww 0xfc600090 0x00050a00 ;# MEMCTL_GP_08
+ mww 0xfc600094 0x11000000 ;# MEMCTL_GP_09
+ mww 0xfc600098 0x00001302 ;# MEMCTL_GP_10
+ mww 0xfc60009c 0x00001c1c ;# MEMCTL_DLL_SET_01
+ mww 0xfc6000a0 0x7c000000 ;# MEMCTL_DQS_OUT_SHIFT
+ mww 0xfc6000a4 0x005c0000 ;# MEMCTL_WR_DQS_SHIFT
+ mww 0xfc6000a8 0x2b050e00 ;# MEMCTL_TIME_SET_03
+ mww 0xfc6000ac 0x00640064 ;# MEMCTL_AHB_PRRLX_00
+ mww 0xfc6000b0 0x00640064 ;# MEMCTL_AHB_PRRLX_01
+ mww 0xfc6000b4 0x00000064 ;# MEMCTL_AHB_PRRLX_02
+ mww 0xfc6000b8 0x00000000 ;# MEMCTL_OUTRANGE_LGTH
+ mww 0xfc6000bc 0x00200020 ;# MEMCTL_AHB_RW_SET_00
+ mww 0xfc6000c0 0x00200020 ;# MEMCTL_AHB_RW_SET_01
+ mww 0xfc6000c4 0x00200020 ;# MEMCTL_AHB_RW_SET_02
+ mww 0xfc6000c8 0x00200020 ;# MEMCTL_AHB_RW_SET_03
+ mww 0xfc6000cc 0x00200020 ;# MEMCTL_AHB_RW_SET_04
+ mww 0xfc6000d8 0x00000a24 ;# MEMCTL_TREF
+ mww 0xfc6000dc 0x00000000 ;# MEMCTL_EMRS3_DATA
+ mww 0xfc6000e0 0x5b1c00c8 ;# MEMCTL_TIME_SET_04
+ mww 0xfc6000e4 0x00c8002e ;# MEMCTL_TIME_SET_05
+ mww 0xfc6000e8 0x00000000 ;# MEMCTL_VERSION
+ mww 0xfc6000ec 0x0001046b ;# MEMCTL_TINIT
+ mww 0xfc6000f0 0x00000000 ;# MEMCTL_OUTRANGE_ADDR_01
+ mww 0xfc6000f4 0x00000000 ;# MEMCTL_OUTRANGE_ADDR_02
+ mww 0xfc600104 0x001c0000 ;# MEMCTL_DLL_DQS_DELAY_BYPASS_0
+ mww 0xfc600108 0x0019001c ;# MEMCTL_DLL_SET_02
+ mww 0xfc60010c 0x00100000 ;# MEMCTL_DLL_SET_03
+ mww 0xfc600110 0x001e007a ;# MEMCTL_DQS_SET_2
+ mww 0xfc600188 0x00000000 ;# MEMCTL_USER_DEF_REG_0
+ mww 0xfc60018c 0x00000000 ;# MEMCTL_USER_DEF_REG_1
+ mww 0xfc600190 0x01010001 ;# MEMCTL_GP_11
+ mww 0xfc600194 0x01000000 ;# MEMCTL_GP_12
+ mww 0xfc600198 0x00000001 ;# MEMCTL_GP_13
+ mww 0xfc60019c 0x00400000 ;# MEMCTL_GP_14
+ mww 0xfc6001a0 0x00000000 ;# MEMCTL_EMRS2_DATA_X
+ mww 0xfc6001a4 0x00000000 ;# MEMCTL_LWPWR_CNT
+ mww 0xfc6001a8 0x00000000 ;# MEMCTL_LWPWR_REG
+ mww 0xfc6001ac 0x00860000 ;# MEMCTL_GP_15
+ mww 0xfc6001b0 0x00000002 ;# MEMCTL_TPDEX
# MPMC START
mww 0xfc60001c 0x01000100
}
#buspirate_port /dev/ttyUSB0
# communication speed setting
-buspirate_speed normal # or fast
+buspirate_speed normal ;# or fast
# voltage regulator Enabled = 1 Disabled = 0
#buspirate_vreg 0
$TARGETNAME configure -event reset-halt-post {
#setup PLL to lowest common denominator 300/300/150 setting
- mww 0xb8050000 0x000f40a3 # reset val + CPU:3 DDR:3 AHB:0
- mww 0xb8050000 0x800f40a3 # send to PLL
+ mww 0xb8050000 0x000f40a3 ;# reset val + CPU:3 DDR:3 AHB:0
+ mww 0xb8050000 0x800f40a3 ;# send to PLL
#next command will reset for PLL changes to take effect
- mww 0xb8050008 3 # set reset_switch and clock_switch (resets SoC)
+ mww 0xb8050008 3 ;# set reset_switch and clock_switch (resets SoC)
}
$TARGETNAME configure -event reset-init {
#complete pll initialization
- mww 0xb8050000 0x800f0080 # set sw_update bit
- mww 0xb8050008 0 # clear reset_switch bit
- mww 0xb8050000 0x800f00e8 # clr pwrdwn & bypass
- mww 0xb8050008 1 # set clock_switch bit
- sleep 1 # wait for lock
+ mww 0xb8050000 0x800f0080 ;# set sw_update bit
+ mww 0xb8050008 0 ;# clear reset_switch bit
+ mww 0xb8050000 0x800f00e8 ;# clr pwrdwn & bypass
+ mww 0xb8050008 1 ;# set clock_switch bit
+ sleep 1 ;# wait for lock
# Setup DDR config and flash mapping
- mww 0xb8000000 0xefbc8cd0 # DDR cfg cdl val (rst: 0x5bfc8d0)
- mww 0xb8000004 0x8e7156a2 # DDR cfg2 cdl val (rst: 0x80d106a8)
-
- mww 0xb8000010 8 # force precharge all banks
- mww 0xb8000010 1 # force EMRS update cycle
- mww 0xb800000c 0 # clr ext. mode register
- mww 0xb8000010 2 # force auto refresh all banks
- mww 0xb8000010 8 # force precharge all banks
- mww 0xb8000008 0x31 # set DDR mode value CAS=3
- mww 0xb8000010 1 # force EMRS update cycle
- mww 0xb8000014 0x461b # DDR refresh value
- mww 0xb8000018 0xffff # DDR Read Data This Cycle value (16bit: 0xffff)
- mww 0xb800001c 0x7 # delay added to the DQS line (normal = 7)
+ mww 0xb8000000 0xefbc8cd0 ;# DDR cfg cdl val (rst: 0x5bfc8d0)
+ mww 0xb8000004 0x8e7156a2 ;# DDR cfg2 cdl val (rst: 0x80d106a8)
+
+ mww 0xb8000010 8 ;# force precharge all banks
+ mww 0xb8000010 1 ;# force EMRS update cycle
+ mww 0xb800000c 0 ;# clr ext. mode register
+ mww 0xb8000010 2 ;# force auto refresh all banks
+ mww 0xb8000010 8 ;# force precharge all banks
+ mww 0xb8000008 0x31 ;# set DDR mode value CAS=3
+ mww 0xb8000010 1 ;# force EMRS update cycle
+ mww 0xb8000014 0x461b ;# DDR refresh value
+ mww 0xb8000018 0xffff ;# DDR Read Data This Cycle value (16bit: 0xffff)
+ mww 0xb800001c 0x7 ;# delay added to the DQS line (normal = 7)
mww 0xb8000020 0
mww 0xb8000024 0
mww 0xb8000028 0
arm7_9 fast_memory_access enable
proc at91sam_init { } {
- mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
- mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
-
- mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
- sleep 20 # wait 20 ms
- mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
- sleep 10 # wait 10 ms
- mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz
- sleep 20 # wait 20 ms
- mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler
- sleep 10 # wait 10 ms
- mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
- sleep 10 # wait 10 ms
+ mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset
+ mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
+
+ mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
+ sleep 20 ;# wait 20 ms
+ mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
+ sleep 20 ;# wait 20 ms
+ mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected
+ sleep 10 ;# wait 10 ms
# Now run at anything fast... ie: 10mhz!
- jtag_rclk 10000 # Increase JTAG Speed to 6 MHz
+ jtag_rclk 10000 ;# Increase JTAG Speed to 6 MHz
- mww 0xffffec00 0x0a0a0a0a # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
- mww 0xffffec04 0x0b0b0b0b # SMC_PULSE0
- mww 0xffffec08 0x00160016 # SMC_CYCLE0
- mww 0xffffec0c 0x00161003 # SMC_MODE0
+ mww 0xffffec00 0x0a0a0a0a ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
+ mww 0xffffec04 0x0b0b0b0b ;# SMC_PULSE0
+ mww 0xffffec08 0x00160016 ;# SMC_CYCLE0
+ mww 0xffffec0c 0x00161003 ;# SMC_MODE0
- mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
- mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
+ mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
+ mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
- mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
+ mww 0xffffef1c 0x2 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
- mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
- #mww 0xffffea08 0x85227254 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
+ mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
+ #mww 0xffffea08 0x85227254 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
- mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
+ mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
mww 0x20000000 0
- mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
+ mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
mww 0x20000000 0
- mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+ mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
- mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
+ mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
mww 0x20000000 0
- mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
+ mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
mww 0x20000000 0
- mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us
+ mww 0xffffea04 0x5d2 ;# SDRAMC_TR : Set refresh timer count to 15us
}
echo "\nRunning reset init script for LPC3131\n"
halt
wait_halt
- reg cpsr 0xa00000d3 #Supervisor mode
+ reg cpsr 0xa00000d3 ;#Supervisor mode
reg pc 0x11029000
poll
sleep 500
#############################################################################
# setup expansion bus CS, disable external wdt
#############################################################################
- mww 0xc4000000 0xbd113842 #CS0 : Flash, write enabled @0x50000000
- mww 0xc4000004 0x94d10013 #CS1
- mww 0xc4000008 0x95960003 #CS2
- mww 0xc400000c 0x00000000 #CS3
- mww 0xc4000010 0x80900003 #CS4
- mww 0xc4000014 0x9d520003 #CS5
- mww 0xc4000018 0x81860001 #CS6
- mww 0xc400001c 0x80900003 #CS7
+ mww 0xc4000000 0xbd113842 ;#CS0 : Flash, write enabled @0x50000000
+ mww 0xc4000004 0x94d10013 ;#CS1
+ mww 0xc4000008 0x95960003 ;#CS2
+ mww 0xc400000c 0x00000000 ;#CS3
+ mww 0xc4000010 0x80900003 ;#CS4
+ mww 0xc4000014 0x9d520003 ;#CS5
+ mww 0xc4000018 0x81860001 ;#CS6
+ mww 0xc400001c 0x80900003 ;#CS7
#############################################################################
# init SDRAM controller: 16MB, one bank, CL3
#############################################################################
- mww 0xCC000000 0x2A # SDRAM_CFG: 64MBit, CL3
- mww 0xCC000004 0 # disable refresh
- mww 0xCC000008 3 # NOP
+ mww 0xCC000000 0x2A ;# SDRAM_CFG: 64MBit, CL3
+ mww 0xCC000004 0 ;# disable refresh
+ mww 0xCC000008 3 ;# NOP
sleep 100
- mww 0xCC000004 2100 # set refresh counter
- mww 0xCC000008 2 # Precharge All Banks
+ mww 0xCC000004 2100 ;# set refresh counter
+ mww 0xCC000008 2 ;# Precharge All Banks
sleep 100
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 4 # Auto Refresh
- mww 0xCC000008 1 # Mode Select CL3
-
- #mww 0xc4000020 0xffffee # CFG0: remove expansion bus boot flash
+ mww 0xCC000008 4 ;# Auto Refresh
+ mww 0xCC000008 4 ;# Auto Refresh
+ mww 0xCC000008 4 ;# Auto Refresh
+ mww 0xCC000008 4 ;# Auto Refresh
+ mww 0xCC000008 4 ;# Auto Refresh
+ mww 0xCC000008 4 ;# Auto Refresh
+ mww 0xCC000008 4 ;# Auto Refresh
+ mww 0xCC000008 4 ;# Auto Refresh
+ mww 0xCC000008 1 ;# Mode Select CL3
+
+ #mww 0xc4000020 0xffffee ;# CFG0: remove expansion bus boot flash
#mirror at 0x00000000
#big endian
projects / openocd / commitdiff