uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
uint32_t component_base;
unsigned part_num;
- char *type, *full;
+ const char *type, *full;
component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
if (((c_cid1 >> 4) & 0x0f) == 9) {
uint32_t devtype;
unsigned minor;
- char *major = "Reserved", *subtype = "Reserved";
+ const char *major = "Reserved", *subtype = "Reserved";
retval = mem_ap_read_atomic_u32(dap,
(component_base & 0xfffff000) | 0xfcc,
#include <helper/log.h>
#include <sys/stat.h>
-static int open_modeflags[12] = {
+static const int open_modeflags[12] = {
O_RDONLY,
O_RDONLY | O_BINARY,
O_RDWR,
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
-static char *armv7m_exception_strings[] = {
+static const char * const armv7m_exception_strings[] = {
"", "Reset", "NMI", "HardFault",
"MemManage", "BusFault", "UsageFault", "RESERVED",
"RESERVED", "RESERVED", "RESERVED", "SVCall",
* They are assigned by vendors, which generally assign different numbers to
* peripherals (such as UART0 or a USB peripheral controller).
*/
-char *armv7m_exception_string(int number)
+const char *armv7m_exception_string(int number)
{
static char enamebuf[32];
extern const int armv7m_psp_reg_map[];
extern const int armv7m_msp_reg_map[];
-char *armv7m_exception_string(int number);
+const char *armv7m_exception_string(int number);
/* offsets into armv7m core register cache */
enum {
#include "avr32_regs.h"
#include "avr32_ap7k.h"
-static char *avr32_core_reg_list[] = {
+static const char * const avr32_core_reg_list[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8",
"r9", "r10", "r11", "r12", "sp", "lr", "pc", "sr"
};
-static struct avr32_core_reg
+static const struct avr32_core_reg
avr32_core_reg_list_arch_info[AVR32NUMCOREREGS] = {
{0, NULL, NULL},
{1, NULL, NULL},
#include <helper/log.h>
#include "breakpoints.h"
-static char *breakpoint_type_strings[] = {
+static const char * const breakpoint_type_strings[] = {
"hardware",
"software"
};
-static char *watchpoint_rw_strings[] = {
+static const char * const watchpoint_rw_strings[] = {
"read",
"write",
"access"
{
struct breakpoint *breakpoint = target->breakpoints;
struct breakpoint **breakpoint_p = &target->breakpoints;
- char *reason;
+ const char *reason;
int retval;
int n;
struct watchpoint *watchpoint = target->watchpoints;
struct watchpoint **watchpoint_p = &target->watchpoints;
int retval;
- char *reason;
+ const char *reason;
while (watchpoint) {
if (watchpoint->address == address) {
((s & 1) << 16) | ((w & 1) << 15) | ((d & 0x3f) << 8) | (p & 0x3f))
/* the gdb register list is send in this order */
-static uint8_t gdb_reg_list_idx[] = {
+static const uint8_t gdb_reg_list_idx[] = {
DSP563XX_REG_IDX_X1, DSP563XX_REG_IDX_X0, DSP563XX_REG_IDX_Y1, DSP563XX_REG_IDX_Y0,
DSP563XX_REG_IDX_A2, DSP563XX_REG_IDX_A1, DSP563XX_REG_IDX_A0, DSP563XX_REG_IDX_B2,
DSP563XX_REG_IDX_B1, DSP563XX_REG_IDX_B0, DSP563XX_REG_IDX_PC, DSP563XX_REG_IDX_SR,
#define DSP563XX_ONCE_NOREG 0x01F /* no register selected */
struct once_reg {
- uint8_t num;
- uint8_t addr;
- uint8_t len;
+ const uint8_t num;
+ const uint8_t addr;
+ const uint8_t len;
const char *name;
uint32_t reg;
};
* From: ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
*/
static const struct {
- char *name;
- unsigned short addr;
- unsigned short width;
+ const char *name;
+ unsigned short addr;
+ unsigned short width;
} eice_regs[] = {
[EICE_DBG_CTRL] = {
.name = "debug_ctrl",
#include "etb.h"
#include "register.h"
-static char *etb_reg_list[] = {
+static const char * const etb_reg_list[] = {
"ETB_identification",
"ETB_ram_depth",
"ETB_ram_width",
uint8_t size; /* low-N of 32 bits */
uint8_t mode; /* RO, WO, RW */
uint8_t bcd_vers; /* 1.0, 2.0, etc */
- char *name;
+ const char *name;
};
/*
static bool nds32_reg_init_done;
static struct nds32_reg_s nds32_regs[TOTAL_REG_NUM];
-static struct nds32_reg_exception_s nds32_ex_reg_values[] = {
+static const struct nds32_reg_exception_s nds32_ex_reg_values[] = {
{IR0, 3, 0x3, 2},
{IR0, 3, 0x3, 3},
{IR1, 3, 0x3, 2},
bool nds32_reg_exception(uint32_t number, uint32_t value)
{
int i;
- struct nds32_reg_exception_s *ex_reg_value;
+ const struct nds32_reg_exception_s *ex_reg_value;
uint32_t field_value;
i = 0;
* the client should be forced into character mode. However it doesn't make any difference.
*/
-static char *negotiate =
+static const char * const negotiate =
"\xFF\xFB\x03" /* IAC WILL Suppress Go Ahead */
"\xFF\xFB\x01" /* IAC WILL Echo */
"\xFF\xFD\x03" /* IAC DO Suppress Go Ahead */
static struct or1k_core_reg *or1k_core_reg_list_arch_info;
-struct or1k_core_reg_init or1k_init_reg_list[] = {
+static const struct or1k_core_reg_init or1k_init_reg_list[] = {
{"r0" , GROUP0 + 1024, "org.gnu.gdb.or1k.group0", NULL},
{"r1" , GROUP0 + 1025, "org.gnu.gdb.or1k.group0", NULL},
{"r2" , GROUP0 + 1026, "org.gnu.gdb.or1k.group0", NULL},
#define OR1K_TAP_INST_IDCODE 0x2
#define OR1K_TAP_INST_DEBUG 0x8
-static char *id_to_string(unsigned char id)
+static const char *id_to_string(unsigned char id)
{
switch (id) {
case VJTAG_NODE_ID:
#include "xscale_debug.inc"
};
-static char *const xscale_reg_list[] = {
+static const char *const xscale_reg_list[] = {
"XSCALE_MAINID", /* 0 */
"XSCALE_CACHETYPE",
"XSCALE_CTRL",