#
VERSION = 1
-PATCHLEVEL = 2
+PATCHLEVEL = 3
SUBLEVEL = 0
-EXTRAVERSION =
+EXTRAVERSION = -rc1
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
VERSION_FILE = $(obj)include/version_autogenerated.h
#endif
-static struct pci_controller hose = {
+static struct pci_controller hose[] = {
#ifndef CONFIG_PCI_PNP
- config_table: pci_stxgp3_config_table,
+ { config_table: pci_stxgp3_config_table,},
+#ifdef CONFIG_MPC85XX_PCI2
+ {},
+#endif
#endif
};
#ifdef CONFIG_PCI
extern void pci_mpc85xx_init(struct pci_controller *hose);
- pci_mpc85xx_init(&hose);
+ pci_mpc85xx_init(hose);
#endif /* CONFIG_PCI */
}
int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
-static uchar rx_buff[FEC_MAX_PKT_SIZE];
+static uchar rx_buff[FEC_BUFFER_SIZE];
static int rx_buff_idx = 0;
/********************************************************************/
/* Set Opcode/Pause Duration Register */
fec->eth->op_pause = 0x00010020;
- /* Frame length=1518; MII mode */
- fec->eth->r_cntrl = 0x05ee0024;
+ /* Frame length=1522; MII mode */
+ fec->eth->r_cntrl = (FEC_MAX_FRAME_LEN << 16) | 0x24;
/* Half-duplex, heartbeat disabled */
fec->eth->x_cntrl = 0x00000000;
/* Setup recv fifo start and buff size */
fec->eth->r_fstart = 0x500;
- fec->eth->r_buff_size = 0x5e0;
+ fec->eth->r_buff_size = FEC_BUFFER_SIZE;
/* Setup BD base addresses */
fec->eth->r_des_start = (uint32)fec->bdBase->rbd;
#define FEC_RBD_NUM 32 /* The user can adjust this value */
/* packet size limit */
-#define FEC_MAX_PKT_SIZE 1536
+#define FEC_MAX_FRAME_LEN 1522 /* recommended default value */
+
+/* Buffer size must be evenly divisible by 16 */
+#define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
typedef struct {
- uint8 frame[FEC_MAX_PKT_SIZE];
+ uint8 frame[FEC_BUFFER_SIZE];
} mpc512x_frame;
typedef struct {
#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */
#if defined(CONFIG_PCI) /* PCI Ethernet card */
-
+#define CONFIG_MPC85XX_PCI2 1
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define IH_CPU_NIOS2 15 /* Nios-II */
#define IH_CPU_BLACKFIN 16 /* Blackfin */
#define IH_CPU_AVR32 17 /* AVR32 */
+#define IH_CPU_ST200 18 /* STMicroelectronics ST200 */
/*
* Image Types
@rm -f $(obj)nand_ecc.c
ln -s $(SRCTREE)/drivers/nand/nand_ecc.c $(obj)nand_ecc.c
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)sdram.c:
+ @rm -f $(obj)sdram.c
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/sdram.c $(obj)sdram.c
+endif
+
#########################################################################
$(obj)%.o: $(obj)%.S