--- /dev/null
+/******************************************************************\r
+ ***** *****\r
+ ***** Ver.: 1.0 *****\r
+ ***** Date: 07/05/2001 *****\r
+ ***** Auth: Andreas Dannenberg *****\r
+ ***** HTWK Leipzig *****\r
+ ***** university of applied sciences *****\r
+ ***** Germany *****\r
+ ***** Func: ethernet packet-driver for use with LAN- *****\r
+ ***** controller CS8900 from Crystal/Cirrus Logic *****\r
+ ***** *****\r
+ ***** Keil: Module modified for use with Philips *****\r
+ ***** LPC2378 EMAC Ethernet controller *****\r
+ ***** *****\r
+ ******************************************************************/\r
+\r
+/* Adapted from file originally written by Andreas Dannenberg. Supplied with permission. */\r
+#include "FreeRTOS.h"\r
+#include "semphr.h"\r
+#include "task.h"\r
+#include "LPC17xx_defs.h"\r
+#include "EthDev_LPC17xx.h"\r
+\r
+#define emacPINSEL2_VALUE 0x50150105\r
+\r
+#define emacWAIT_FOR_LINK_TO_ESTABLISH ( 500 / portTICK_RATE_MS )\r
+#define emacSHORT_DELAY ( 2 )\r
+\r
+#define emacLINK_ESTABLISHED ( 0x0001 )\r
+#define emacFULL_DUPLEX_ENABLED ( 0x0004 )\r
+#define emac10BASE_T_MODE ( 0x0002 )\r
+\r
+/* The semaphore used to wake the uIP task when data arives. */\r
+xSemaphoreHandle xEMACSemaphore = NULL;\r
+\r
+static unsigned short *rptr;\r
+static unsigned short *tptr;\r
+\r
+static void prvInitDescriptors( void );\r
+static void prvSetupEMACHardware( void );\r
+static void prvConfigurePHY( void );\r
+static long prvSetupLinkStatus( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int write_PHY( long lPhyReg, long lValue )\r
+{\r
+const long lMaxTime = 10;\r
+long x;\r
+\r
+ MAC_MADR = DP83848C_DEF_ADR | lPhyReg;\r
+ MAC_MWTD = lValue;\r
+\r
+ x = 0;\r
+ for( x = 0; x < lMaxTime; x++ )\r
+ {\r
+ if( ( MAC_MIND & MIND_BUSY ) == 0 )\r
+ {\r
+ /* Operation has finished. */\r
+ break;\r
+ }\r
+\r
+ vTaskDelay( emacSHORT_DELAY );\r
+ }\r
+\r
+ if( x < lMaxTime )\r
+ {\r
+ return pdPASS;\r
+ }\r
+ else\r
+ {\r
+ return pdFAIL;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned short read_PHY( unsigned char ucPhyReg, portBASE_TYPE *pxStatus )\r
+{\r
+long x;\r
+const long lMaxTime = 10;\r
+\r
+ MAC_MADR = DP83848C_DEF_ADR | ucPhyReg;\r
+ MAC_MCMD = MCMD_READ;\r
+\r
+ for( x = 0; x < lMaxTime; x++ )\r
+ {\r
+ /* Operation has finished. */\r
+ if( ( MAC_MIND & MIND_BUSY ) == 0 )\r
+ {\r
+ break;\r
+ }\r
+\r
+ vTaskDelay( emacSHORT_DELAY );\r
+ }\r
+\r
+ MAC_MCMD = 0;\r
+\r
+ if( x >= lMaxTime )\r
+ {\r
+ *pxStatus = pdFAIL;\r
+ }\r
+\r
+ return( MAC_MRDD );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvInitDescriptors( void )\r
+{\r
+long x;\r
+\r
+ for( x = 0; x < NUM_RX_FRAG; x++ )\r
+ {\r
+ RX_DESC_PACKET( x ) = RX_BUF( x );\r
+ RX_DESC_CTRL( x ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );\r
+ RX_STAT_INFO( x ) = 0;\r
+ RX_STAT_HASHCRC( x ) = 0;\r
+ }\r
+\r
+ /* Set EMAC Receive Descriptor Registers. */\r
+ MAC_RXDESCRIPTOR = RX_DESC_BASE;\r
+ MAC_RXSTATUS = RX_STAT_BASE;\r
+ MAC_RXDESCRIPTORNUM = NUM_RX_FRAG - 1;\r
+\r
+ /* Rx Descriptors Point to 0 */\r
+ MAC_RXCONSUMEINDEX = 0;\r
+\r
+ for( x = 0; x < NUM_TX_FRAG; x++ )\r
+ {\r
+ TX_DESC_PACKET( x ) = TX_BUF( x );\r
+ TX_DESC_CTRL( x ) = 0;\r
+ TX_STAT_INFO( x ) = 0;\r
+ }\r
+\r
+ /* Set EMAC Transmit Descriptor Registers. */\r
+ MAC_TXDESCRIPTOR = TX_DESC_BASE;\r
+ MAC_TXSTATUS = TX_STAT_BASE;\r
+ MAC_TXDESCRIPTORNUM = NUM_TX_FRAG - 1;\r
+\r
+ /* Tx Descriptors Point to 0 */\r
+ MAC_TXPRODUCEINDEX = 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupEMACHardware( void )\r
+{\r
+unsigned short us;\r
+long x;\r
+\r
+ /* Enable P1 Ethernet Pins. */\r
+ PINSEL2 = emacPINSEL2_VALUE;\r
+ PINSEL3 = ( PINSEL3 & ~0x0000000F ) | 0x00000005;\r
+\r
+ /* Power Up the EMAC controller. */\r
+ PCONP |= PCONP_PCENET;\r
+ vTaskDelay( emacSHORT_DELAY );\r
+\r
+ /* Reset all EMAC internal modules. */\r
+ MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;\r
+ MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;\r
+\r
+ /* A short delay after reset. */\r
+ vTaskDelay( emacSHORT_DELAY );\r
+\r
+ /* Initialize MAC control registers. */\r
+ MAC_MAC1 = MAC1_PASS_ALL;\r
+ MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;\r
+ MAC_MAXF = ETH_MAX_FLEN;\r
+ MAC_CLRT = CLRT_DEF;\r
+ MAC_IPGR = IPGR_DEF;\r
+\r
+ /* Enable Reduced MII interface. */\r
+ MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM;\r
+\r
+ /* Reset Reduced MII Logic. */\r
+ MAC_SUPP = SUPP_RES_RMII;\r
+ vTaskDelay( emacSHORT_DELAY );\r
+ MAC_SUPP = 0;\r
+\r
+ /* Put the PHY in reset mode */\r
+ write_PHY( PHY_REG_BMCR, MCFG_RES_MII );\r
+ write_PHY( PHY_REG_BMCR, MCFG_RES_MII );\r
+\r
+ /* Wait for hardware reset to end. */\r
+ for( x = 0; x < 100; x++ )\r
+ {\r
+ vTaskDelay( emacSHORT_DELAY * 5 );\r
+ us = read_PHY( PHY_REG_BMCR, &us );\r
+ if( !( us & MCFG_RES_MII ) )\r
+ {\r
+ /* Reset complete */\r
+ break;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvConfigurePHY( void )\r
+{\r
+unsigned short us;\r
+long x;\r
+\r
+ /* Auto negotiate the configuration. */\r
+ if( write_PHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )\r
+ {\r
+ vTaskDelay( emacSHORT_DELAY * 5 );\r
+\r
+ for( x = 0; x < 10; x++ )\r
+ {\r
+ us = read_PHY( PHY_REG_BMSR, &us );\r
+\r
+ if( us & PHY_AUTO_NEG_COMPLETE )\r
+ {\r
+ break;\r
+ }\r
+\r
+ vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static long prvSetupLinkStatus( void )\r
+{\r
+long lReturn = pdFAIL, x;\r
+unsigned short usLinkStatus;\r
+\r
+ for( x = 0; x < 10; x++ )\r
+ {\r
+ usLinkStatus = read_PHY( PHY_REG_STS, &lReturn );\r
+ if( usLinkStatus & emacLINK_ESTABLISHED )\r
+ {\r
+ /* Link is established. */\r
+ lReturn = pdPASS;\r
+ break;\r
+ }\r
+\r
+ vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );\r
+ }\r
+\r
+ if( lReturn == pdPASS )\r
+ {\r
+ /* Configure Full/Half Duplex mode. */\r
+ if( usLinkStatus & emacFULL_DUPLEX_ENABLED )\r
+ {\r
+ /* Full duplex is enabled. */\r
+ MAC_MAC2 |= MAC2_FULL_DUP;\r
+ MAC_COMMAND |= CR_FULL_DUP;\r
+ MAC_IPGT = IPGT_FULL_DUP;\r
+ }\r
+ else\r
+ {\r
+ /* Half duplex mode. */\r
+ MAC_IPGT = IPGT_HALF_DUP;\r
+ }\r
+\r
+ /* Configure 100MBit/10MBit mode. */\r
+ if( usLinkStatus & emac10BASE_T_MODE )\r
+ {\r
+ /* 10MBit mode. */\r
+ MAC_SUPP = 0;\r
+ }\r
+ else\r
+ {\r
+ /* 100MBit mode. */\r
+ MAC_SUPP = SUPP_SPEED;\r
+ }\r
+ }\r
+\r
+ return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE Init_EMAC( void )\r
+{\r
+portBASE_TYPE xReturn = pdPASS;\r
+volatile unsigned long regv, tout;\r
+unsigned long ulID1, ulID2;\r
+\r
+ /* Reset peripherals, configure port pins and registers. */\r
+ prvSetupEMACHardware();\r
+\r
+ /* Check if connected to a DP83848C PHY. */\r
+ ulID1 = read_PHY( PHY_REG_IDR1, &xReturn );\r
+ ulID2 = read_PHY( PHY_REG_IDR2, &xReturn );\r
+ if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFF0UL ) ) == DP83848C_ID )\r
+ {\r
+ /* Set the Ethernet MAC Address registers */\r
+ MAC_SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;\r
+ MAC_SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;\r
+ MAC_SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;\r
+\r
+ /* Initialize Tx and Rx DMA Descriptors */\r
+ prvInitDescriptors();\r
+\r
+ /* Receive Broadcast and Perfect Match Packets */\r
+ MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;\r
+\r
+ /* Create the semaphore used to wake the uIP task. */\r
+ vSemaphoreCreateBinary( xEMACSemaphore );\r
+\r
+ /* Setup the PHY. */\r
+ prvConfigurePHY();\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ /* Check the link status. */\r
+ if( xReturn == pdPASS )\r
+ {\r
+ xReturn = prvSetupLinkStatus();\r
+ }\r
+\r
+ if( xReturn == pdPASS )\r
+ {\r
+ /* Reset all interrupts */\r
+ MAC_INTCLEAR = 0xFFFF;\r
+\r
+ /* Enable receive and transmit mode of MAC Ethernet core */\r
+ MAC_COMMAND |= ( CR_RX_EN | CR_TX_EN );\r
+ MAC_MAC1 |= MAC1_REC_EN;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+// reads a word in little-endian byte order from RX_BUFFER\r
+unsigned short ReadFrame_EMAC( void )\r
+{\r
+ return( *rptr++ );\r
+}\r
+\r
+// copies bytes from frame port to MCU-memory\r
+// NOTES: * an odd number of byte may only be transfered\r
+// if the frame is read to the end!\r
+// * MCU-memory MUST start at word-boundary\r
+void CopyFromFrame_EMAC( void *Dest, unsigned short Size )\r
+{\r
+ unsigned short *piDest; // Keil: Pointer added to correct expression\r
+ piDest = Dest; // Keil: Line added\r
+ while( Size > 1 )\r
+ {\r
+ *piDest++ = ReadFrame_EMAC();\r
+ Size -= 2;\r
+ }\r
+\r
+ if( Size )\r
+ { // check for leftover byte...\r
+ *( unsigned char * ) piDest = ( char ) ReadFrame_EMAC(); // the LAN-Controller will return 0\r
+ } // for the highbyte\r
+}\r
+\r
+\r
+// Reads the length of the received ethernet frame and checks if the\r
+// destination address is a broadcast message or not\r
+// returns the frame length\r
+unsigned short StartReadFrame( void )\r
+{\r
+ unsigned short RxLen;\r
+ unsigned int idx;\r
+\r
+ idx = MAC_RXCONSUMEINDEX;\r
+ RxLen = ( RX_STAT_INFO(idx) & RINFO_SIZE ) - 3;\r
+ rptr = ( unsigned short * ) RX_DESC_PACKET( idx );\r
+ return( RxLen );\r
+}\r
+\r
+void EndReadFrame( void )\r
+{\r
+ unsigned int idx;\r
+\r
+ /* DMA free packet. */\r
+ idx = MAC_RXCONSUMEINDEX;\r
+\r
+ if( ++idx == NUM_RX_FRAG )\r
+ {\r
+ idx = 0;\r
+ }\r
+\r
+ MAC_RXCONSUMEINDEX = idx;\r
+}\r
+\r
+unsigned int uiGetEMACRxData( unsigned char *ucBuffer )\r
+{\r
+ unsigned int uiLen = 0;\r
+\r
+ if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX )\r
+ {\r
+ uiLen = StartReadFrame();\r
+ CopyFromFrame_EMAC( ucBuffer, uiLen );\r
+ EndReadFrame();\r
+ }\r
+\r
+ return uiLen;\r
+}\r
+\r
+// requests space in EMAC memory for storing an outgoing frame\r
+void RequestSend( void )\r
+{\r
+ unsigned int idx;\r
+\r
+ idx = MAC_TXPRODUCEINDEX;\r
+ tptr = ( unsigned short * ) TX_DESC_PACKET( idx );\r
+}\r
+\r
+// writes a word in little-endian byte order to TX_BUFFER\r
+void WriteFrame_EMAC( unsigned short Data )\r
+{\r
+ *tptr++ = Data;\r
+}\r
+\r
+// copies bytes from MCU-memory to frame port\r
+// NOTES: * an odd number of byte may only be transfered\r
+// if the frame is written to the end!\r
+// * MCU-memory MUST start at word-boundary\r
+void CopyToFrame_EMAC( void *Source, unsigned int Size )\r
+{\r
+ unsigned short *piSource;\r
+\r
+ piSource = Source;\r
+ Size = ( Size + 1 ) & 0xFFFE; // round Size up to next even number\r
+ while( Size > 0 )\r
+ {\r
+ WriteFrame_EMAC( *piSource++ );\r
+ Size -= 2;\r
+ }\r
+}\r
+\r
+void DoSend_EMAC( unsigned short FrameSize )\r
+{\r
+ unsigned int idx;\r
+\r
+ idx = MAC_TXPRODUCEINDEX;\r
+ TX_DESC_CTRL( idx ) = FrameSize | TCTRL_LAST;\r
+ if( ++idx == NUM_TX_FRAG )\r
+ {\r
+ idx = 0;\r
+ }\r
+\r
+ MAC_TXPRODUCEINDEX = idx;\r
+}\r
+\r
+void vEMAC_ISR( void )\r
+{\r
+ portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* Clear the interrupt. */\r
+ MAC_INTCLEAR = 0xffff;\r
+\r
+ /* Ensure the uIP task is not blocked as data has arrived. */\r
+ xSemaphoreGiveFromISR( xEMACSemaphore, &xHigherPriorityTaskWoken );\r
+\r
+ portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
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