Add interrupt nesting support, cache setup and reg test tasks.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@445 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Demo/ColdFire_MCF5282_Eclipse/RTOSDemo/Makefile b/Demo/ColdFire_MCF5282_Eclipse/RTOSDemo/Makefile
index 89cba4beb1480ebc23e8f9608236bb8d3592dd64..f28efe17c2e6d33a76fe30a3c0f48e92c3e994ed 100644 (file)
--- a/Demo/ColdFire_MCF5282_Eclipse/RTOSDemo/Makefile
+++ b/Demo/ColdFire_MCF5282_Eclipse/RTOSDemo/Makefile
@@ -31,6 +31,8 @@ OBJS =                $(OUTPUT_DIR)/portasm.o \
                        $(OUTPUT_DIR)/tasks.o \\r
                        $(OUTPUT_DIR)/queue.o \\r
                        $(OUTPUT_DIR)/heap_2.o \\r
+                       $(OUTPUT_DIR)/IntQueueTimer.o \\r
+                       $(OUTPUT_DIR)/IntQueue.o \\r
                        $(OUTPUT_DIR)/FreeRTOS_Tick_Setup.o\r
                        \r
 C_DEPS = $(OBJS:.o=.d)\r
@@ -44,6 +46,7 @@ CFLAGS=               -I"$(FREERTOS_SOURCE_DIR)/include" \
                        -I. \\r
                        -D COLDFIRE_V2_GCC \\r
                        -O0 \\r
+                       -fno-strict-aliasing \\r
                        -g3 \\r
                        -Wall \\r
                        -Wextra \\r

diff --git a/Demo/ColdFire_MCF5282_Eclipse/RTOSDemo/main.c b/Demo/ColdFire_MCF5282_Eclipse/RTOSDemo/main.c
index 1f1b3978bc424e1720dfac3a8d81e1e5eca13fa1..eb3f368abc50a659598e9a8a6766f9b8e33499eb 100644 (file)
--- a/Demo/ColdFire_MCF5282_Eclipse/RTOSDemo/main.c
+++ b/Demo/ColdFire_MCF5282_Eclipse/RTOSDemo/main.c
@@ -124,9 +124,11 @@ static void prvSetupHardware( void );
  * file.\r
  */\r
 static void prvCheckTask( void *pvParameters );\r
-\r
+static void vRegTest1Task( void *pvParameters );\r
+static void vRegTest2Task( void *pvParameters );\r
 \r
 /*-----------------------------------------------------------*/\r
+static volatile unsigned portLONG ulRegTest1Counter = 0, ulRegTest2Counter = 0;\r
 \r
 int main( void )\r
 {\r
@@ -143,6 +145,10 @@ int main( void )
        vStartQueuePeekTasks();\r
        vStartRecursiveMutexTasks();\r
        vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+       vStartInterruptQueueTasks();\r
+\r
+       xTaskCreate( vRegTest1Task, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+       xTaskCreate( vRegTest2Task, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
 \r
        /* Create the check task. */\r
        xTaskCreate( prvCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
@@ -163,7 +169,7 @@ int main( void )
 \r
 static void prvCheckTask( void *pvParameters )\r
 {\r
-unsigned ulTicksToWait = mainNO_ERROR_PERIOD, ulError = 0;\r
+unsigned ulTicksToWait = mainNO_ERROR_PERIOD, ulError = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
 portTickType xLastExecutionTime;\r
 \r
        ( void ) pvParameters;\r
@@ -182,43 +188,70 @@ portTickType xLastExecutionTime;
                {\r
                        ulError |= 0x01UL;\r
                }\r
-               else if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+\r
+               if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
                {\r
                        ulError |= 0x02UL;\r
                }\r
-               else if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+\r
+               if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
                {\r
                        ulError |= 0x04UL;\r
                }\r
-               else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+\r
+               if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
                {\r
                        ulError |= 0x10UL;\r
                }\r
-           else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+\r
+               if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
            {\r
                ulError |= 0x20UL;\r
            }\r
-           else if( xArePollingQueuesStillRunning() != pdTRUE )\r
+\r
+               if( xArePollingQueuesStillRunning() != pdTRUE )\r
            {\r
                ulError |= 0x40UL;\r
            }\r
-           else if( xIsCreateTaskStillRunning() != pdTRUE )\r
+\r
+               if( xIsCreateTaskStillRunning() != pdTRUE )\r
            {\r
                ulError |= 0x80UL;\r
            }\r
-           else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+\r
+               if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
            {\r
                ulError |= 0x100UL;\r
            }\r
-           else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+\r
+               if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
            {\r
                ulError |= 0x200UL;\r
            }\r
-           else if( xAreComTestTasksStillRunning() != pdTRUE )\r
+\r
+               if( xAreComTestTasksStillRunning() != pdTRUE )\r
                {\r
                ulError |= 0x400UL;\r
                }\r
 \r
+               if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
+           {\r
+               ulError |= 0x800UL;\r
+           }\r
+\r
+               if( ulLastRegTest1Count == ulRegTest1Counter )\r
+               {\r
+                       ulError |= 0x1000UL;\r
+               }\r
+\r
+               if( ulLastRegTest2Count == ulRegTest2Counter )\r
+               {\r
+                       ulError |= 0x1000UL;\r
+               }\r
+\r
+               ulLastRegTest1Count = ulRegTest1Counter;\r
+               ulLastRegTest2Count = ulRegTest2Counter;\r
+\r
                if( ulError != 0 )\r
                {\r
                ulTicksToWait = mainERROR_PERIOD;\r
@@ -231,6 +264,11 @@ portTickType xLastExecutionTime;
 \r
 void prvSetupHardware( void )\r
 {\r
+extern void mcf5xxx_wr_cacr( unsigned portLONG );\r
+\r
+       /* Enable the cache. */\r
+       mcf5xxx_wr_cacr( MCF5XXX_CACR_CENB | MCF5XXX_CACR_CINV | MCF5XXX_CACR_DISD | MCF5XXX_CACR_CEIB | MCF5XXX_CACR_CLNF_00 );\r
+\r
        /* Multiply 8Mhz reference crystal by 8 to achieve system clock of 64Mhz. */\r
        MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD( 2 );\r
 \r
@@ -251,5 +289,141 @@ void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTask
 \r
        for( ;; );\r
 }\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vRegTest1Task( void *pvParameters )\r
+{\r
+       ( void ) pvParameters;\r
 \r
+       asm volatile    (       "reg_test_1_start:                                              \n\t"\r
+                                               "       moveq           #1, %d0                                 \n\t"\r
+                                               "       moveq           #2, %d1                                 \n\t"\r
+                                               "       moveq           #3, %d2                                 \n\t"\r
+                                               "       moveq           #4, %d3                                 \n\t"\r
+                                               "       moveq           #5, %d4                                 \n\t"\r
+                                               "       moveq           #6, %d5                                 \n\t"\r
+                                               "       moveq           #7, %d6                                 \n\t"\r
+                                               "       moveq           #8, %d7                                 \n\t"\r
+                                               "       move            #9, %a0                                 \n\t"\r
+                                               "       move            #10, %a1                                        \n\t"\r
+                                               "       move            #11, %a2                                \n\t"\r
+                                               "       move            #12, %a3                                \n\t"\r
+                                               "       move            #13, %a4                                \n\t"\r
+                                               "       move            #14, %a5                                \n\t"\r
+                                               "       move            #15, %a6                                \n\t"\r
+                                               "                                                                               \n\t"\r
+                                               "       cmpi.l          #1, %d0                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #2, %d1                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #3, %d2                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #4, %d3                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #5, %d4                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #6, %d5                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #7, %d6                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       cmpi.l          #8, %d7                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a0, %d0                                \n\t"\r
+                                               "       cmpi.l          #9, %d0                                 \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a1, %d0                                \n\t"\r
+                                               "       cmpi.l          #10, %d0                                        \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a2, %d0                                \n\t"\r
+                                               "       cmpi.l          #11, %d0                                        \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a3, %d0                                \n\t"\r
+                                               "       cmpi.l          #12, %d0                                        \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a4, %d0                                \n\t"\r
+                                               "       cmpi.l          #13, %d0                                        \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a5, %d0                                \n\t"\r
+                                               "       cmpi.l          #14, %d0                                        \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       move            %a6, %d0                                \n\t"\r
+                                               "       cmpi.l          #15, %d0                                        \n\t"\r
+                                               "       bne                     reg_test_1_error                \n\t"\r
+                                               "       movel           ulRegTest1Counter, %d0  \n\t"\r
+                                               "       addql           #1, %d0                                 \n\t"\r
+                                               "       movel           %d0, ulRegTest1Counter  \n\t"\r
+                                               "       bra                     reg_test_1_start                \n\t"\r
+                                               "reg_test_1_error:                                              \n\t"\r
+                                               "       bra                     reg_test_1_error                \n\t"\r
+                                       );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vRegTest2Task( void *pvParameters )\r
+{\r
+       ( void ) pvParameters;\r
+\r
+       asm volatile    (       "reg_test_2_start:                                              \n\t"\r
+                                               "       moveq           #10, %d0                                        \n\t"\r
+                                               "       moveq           #20, %d1                                        \n\t"\r
+                                               "       moveq           #30, %d2                                        \n\t"\r
+                                               "       moveq           #40, %d3                                        \n\t"\r
+                                               "       moveq           #50, %d4                                        \n\t"\r
+                                               "       moveq           #60, %d5                                        \n\t"\r
+                                               "       moveq           #70, %d6                                        \n\t"\r
+                                               "       moveq           #80, %d7                                        \n\t"\r
+                                               "       move            #90, %a0                                        \n\t"\r
+                                               "       move            #100, %a1                                       \n\t"\r
+                                               "       move            #110, %a2                               \n\t"\r
+                                               "       move            #120, %a3                               \n\t"\r
+                                               "       move            #130, %a4                               \n\t"\r
+                                               "       move            #140, %a5                               \n\t"\r
+                                               "       move            #150, %a6                               \n\t"\r
+                                               "                                                                               \n\t"\r
+                                               "       cmpi.l          #10, %d0                                        \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #20, %d1                                        \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #30, %d2                                        \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #40, %d3                                        \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #50, %d4                                        \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #60, %d5                                        \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #70, %d6                                        \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       cmpi.l          #80, %d7                                        \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a0, %d0                                \n\t"\r
+                                               "       cmpi.l          #90, %d0                                        \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a1, %d0                                \n\t"\r
+                                               "       cmpi.l          #100, %d0                                       \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a2, %d0                                \n\t"\r
+                                               "       cmpi.l          #110, %d0                                       \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a3, %d0                                \n\t"\r
+                                               "       cmpi.l          #120, %d0                                       \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a4, %d0                                \n\t"\r
+                                               "       cmpi.l          #130, %d0                                       \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a5, %d0                                \n\t"\r
+                                               "       cmpi.l          #140, %d0                                       \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       move            %a6, %d0                                \n\t"\r
+                                               "       cmpi.l          #150, %d0                                       \n\t"\r
+                                               "       bne                     reg_test_2_error                \n\t"\r
+                                               "       movel           ulRegTest1Counter, %d0  \n\t"\r
+                                               "       addql           #1, %d0                                 \n\t"\r
+                                               "       movel           %d0, ulRegTest2Counter  \n\t"\r
+                                               "       bra                     reg_test_2_start                \n\t"\r
+                                               "reg_test_2_error:                                              \n\t"\r
+                                               "       bra                     reg_test_2_error                \n\t"\r
+                                       );\r
+}\r
+/*-----------------------------------------------------------*/\r
 \r