--- /dev/null
+/*\r
+ FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * If you are: *\r
+ * *\r
+ * + New to FreeRTOS, *\r
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *\r
+ * + Looking for basic training, *\r
+ * + Wanting to improve your FreeRTOS skills and productivity *\r
+ * *\r
+ * then take a look at the FreeRTOS eBook *\r
+ * *\r
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * A pdf reference manual is also available. Both are usually delivered *\r
+ * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+ * and 8pm GMT (although please allow up to 24 hours in case of *\r
+ * exceptional circumstances). Thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+ a combined work that includes FreeRTOS without being obliged to provide the\r
+ source code for proprietary components outside of the FreeRTOS kernel.\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public \r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it \r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained \r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned long ) 72000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 18 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+#define configUSE_MUTEXES 1\r
+#define configUSE_COUNTING_SEMAPHORES 0\r
+#define configUSE_ALTERNATIVE_API 0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+/* This is the raw value as per the Cortex-M3 NVIC. Values can be 255\r
+(lowest) to 0 (1?) (highest). */\r
+#define configKERNEL_INTERRUPT_PRIORITY 255\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xb0, or priority 11. */\r
+\r
+\r
+/* This is the value being used as per the ST library which permits 16\r
+priority values, 0 to 15. This must correspond to the\r
+configKERNEL_INTERRUPT_PRIORITY setting. Here 15 corresponds to the lowest\r
+NVIC value of 255. */\r
+#define configLIBRARY_KERNEL_INTERRUPT_PRIORITY 15\r
+\r
+/*-----------------------------------------------------------\r
+ * Ethernet configuration.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* MAC address configuration. */\r
+#define configMAC_ADDR0 0x00\r
+#define configMAC_ADDR1 0x12\r
+#define configMAC_ADDR2 0x13\r
+#define configMAC_ADDR3 0x10\r
+#define configMAC_ADDR4 0x15\r
+#define configMAC_ADDR5 0x11\r
+\r
+/* IP address configuration. */\r
+#define configIP_ADDR0 172\r
+#define configIP_ADDR1 25\r
+#define configIP_ADDR2 218\r
+#define configIP_ADDR3 202\r
+\r
+/* Netmask configuration. */\r
+#define configNET_MASK0 255\r
+#define configNET_MASK1 255\r
+#define configNET_MASK2 255\r
+#define configNET_MASK3 0\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * If you are: *\r
+ * *\r
+ * + New to FreeRTOS, *\r
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *\r
+ * + Looking for basic training, *\r
+ * + Wanting to improve your FreeRTOS skills and productivity *\r
+ * *\r
+ * then take a look at the FreeRTOS eBook *\r
+ * *\r
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * A pdf reference manual is also available. Both are usually delivered *\r
+ * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+ * and 8pm GMT (although please allow up to 24 hours in case of *\r
+ * exceptional circumstances). Thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+ a combined work that includes FreeRTOS without being obliged to provide the\r
+ source code for proprietary components outside of the FreeRTOS kernel.\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public \r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it \r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained \r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* FreeRTOS.org includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "partest.h"\r
+\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Library includes. */\r
+#include "stm32f10x_lib.h"\r
+\r
+#define partstNUM_LEDs 8\r
+\r
+/* Holds the current output state for each of the LEDs. */\r
+static unsigned char ucBitStates[ partstNUM_LEDs ];\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+ /* Configure PE14, PD13, PD3 and PD4 output push-pull */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r
+ GPIO_Init( GPIOB, &GPIO_InitStructure );\r
+\r
+ memset( ucBitStates, 0x00, sizeof( ucBitStates ) );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ if( uxLED < partstNUM_LEDs )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ if( xValue != pdFALSE )\r
+ {\r
+ ucBitStates[ uxLED ] = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ ucBitStates[ uxLED ] = pdFALSE;\r
+ }\r
+\r
+ GPIO_WriteBit( GPIOB, ( GPIO_Pin_8 << uxLED ), ucBitStates[ uxLED ] );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED < partstNUM_LEDs )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ ucBitStates[ uxLED ] = !ucBitStates[ uxLED ];\r
+ GPIO_WriteBit( GPIOB, ( GPIO_Pin_8 << uxLED ), ucBitStates[ uxLED ] );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xGetLEDState( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED < partstNUM_LEDs )\r
+ {\r
+ return ( portBASE_TYPE ) ucBitStates[ uxLED ];\r
+ }\r
+ else\r
+ {\r
+ return 0;\r
+ }\r
+}\r
--- /dev/null
+<!DOCTYPE CrossStudio_Project_File>
+<solution Name="RTOSDemo" version="2">
+ <project Name="RTOSDemo">
+ <configuration Name="Common" Target="STM32F103RB" arm_architecture="v7M" arm_core_type="Cortex-M3" arm_linker_fiq_stack_size="0" arm_linker_heap_size="128" arm_linker_irq_stack_size="0" arm_linker_jtag_pad_pre_dr="1" arm_linker_jtag_pad_pre_ir="5" arm_linker_stack_size="128" arm_simulator_memory_simulation_filename="$(PackagesDir)/targets/ST_STM32F10x/STM32F10xSimulatorMemory.dll" arm_simulator_memory_simulation_parameter="0x20000;0x4000" arm_target_debug_interface_type="ADIv5" arm_target_loader_parameter="8000000" c_only_additional_options="-Wall;-Wextra" c_system_include_directories="$(StudioDir)/include;$(PackagesDir)/include;$(PackagesDir)/targets/stm32/include" c_user_include_directories=".;..\\..\\Source\\include;..\\..\\Source\\portable\\GCC\\ARM_CM3;..\\Common\\Include;ST Library\\inc" link_include_startup_code="No" linker_memory_map_file="$(TargetsDir)/ST_STM32F10x/ST_STM32F103RB_MemoryMap.xml" linker_printf_width_precision_supported="No" oscillator_frequency="8MHz" project_directory="" project_type="Executable" property_groups_file_path="$(PackagesDir)/targets/ST_STM32F10x/propertyGroups.xml"/>
+ <configuration Name="RAM" Placement="RAM" linker_section_placement_file="$(StudioDir)/targets/sram_placement.xml" target_reset_script="SRAMReset()"/>
+ <configuration Name="Flash" Placement="Flash" arm_target_flash_loader_file_path="$(PackagesDir)/targets/ST_STM32F10x/Release/Loader_rpc.elf" arm_target_flash_loader_type="LIBMEM RPC Loader" linker_section_placement_file="$(StudioDir)/targets/flash_placement.xml" target_reset_script="FLASHReset()"/>
+ <folder Name="Source Files">
+ <configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc"/>
+ <folder Name="FreeRTOS Source">
+ <file file_name="../../Source/portable/GCC/ARM_CM3/port.c"/>
+ <file file_name="../../Source/tasks.c"/>
+ <file file_name="../../Source/list.c"/>
+ <file file_name="../../Source/queue.c"/>
+ <file file_name="../../Source/portable/MemMang/heap_2.c"/>
+ </folder>
+ <file file_name="main.c"/>
+ <folder Name="Common Demo Tasks">
+ <file file_name="../Common/Minimal/recmutex.c"/>
+ <file file_name="../Common/Minimal/semtest.c"/>
+ <file file_name="../Common/Minimal/BlockQ.c"/>
+ <file file_name="../Common/Minimal/flash.c"/>
+ <file file_name="../Common/Minimal/GenQTest.c"/>
+ <file file_name="../Common/Minimal/integer.c"/>
+ <file file_name="../Common/Minimal/PollQ.c"/>
+ <file file_name="../Common/Minimal/QPeek.c"/>
+ </folder>
+ <file file_name="ParTest/ParTest.c"/>
+ <folder Name="ST Library">
+ <file file_name="ST Library/src/stm32f10x_gpio.c"/>
+ <file file_name="ST Library/src/stm32f10x_lib.c"/>
+ <file file_name="ST Library/src/stm32f10x_systick.c"/>
+ <file file_name="ST Library/src/stm32f10x_rcc.c"/>
+ <file file_name="ST Library/src/stm32f10x_nvic.c"/>
+ <file file_name="ST Library/src/stm32f10x_spi.c"/>
+ <file file_name="ST Library/src/stm32f10x_usart.c"/>
+ <file file_name="ST Library/src/stm32f10x_can.c"/>
+ <file file_name="ST Library/src/stm32f10x_i2c.c"/>
+ </folder>
+ <file file_name="serial/serial.c"/>
+ </folder>
+ <folder Name="System Files">
+ <file file_name="$(StudioDir)/source/thumb_crt0.s"/>
+ <file file_name="$(TargetsDir)/ST_STM32F10x/STM32F10x_Target.js">
+ <configuration Name="Common" file_type="Reset Script"/>
+ </file>
+ <file file_name="STM32F10x_Startup.s"/>
+ </folder>
+ </project>
+ <configuration Name="THUMB Flash Debug" inherited_configurations="THUMB;Flash;Debug"/>
+ <configuration Name="THUMB" Platform="ARM" arm_instruction_set="THUMB" arm_library_instruction_set="THUMB" c_preprocessor_definitions="__THUMB" hidden="Yes"/>
+ <configuration Name="Flash" c_preprocessor_definitions="__FLASH_BUILD" hidden="Yes"/>
+ <configuration Name="Debug" build_debug_information="Yes" c_preprocessor_definitions="DEBUG" gcc_optimization_level="None" hidden="Yes" link_include_startup_code="No"/>
+ <configuration Name="THUMB Flash Release" inherited_configurations="THUMB;Flash;Release"/>
+ <configuration Name="Release" build_debug_information="No" c_additional_options="-g1" c_preprocessor_definitions="NDEBUG" gcc_optimization_level="Level 1" hidden="Yes" link_include_startup_code="No"/>
+</solution>
--- /dev/null
+<!DOCTYPE CrossStudio_for_ARM_Session_File>
+<session>
+ <Bookmarks/>
+ <Breakpoints/>
+ <ExecutionCountWindow/>
+ <Memory1>
+ <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
+ </Memory1>
+ <Memory2>
+ <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
+ </Memory2>
+ <Memory3>
+ <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
+ </Memory3>
+ <Memory4>
+ <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
+ </Memory4>
+ <Project>
+ <ProjectSessionItem path="RTOSDemo" name="unnamed" />
+ <ProjectSessionItem path="RTOSDemo;RTOSDemo" name="unnamed" />
+ <ProjectSessionItem path="RTOSDemo;RTOSDemo;System Files" name="unnamed" />
+ </Project>
+ <Register1>
+ <RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
+ </Register1>
+ <Register2>
+ <RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
+ </Register2>
+ <Register3>
+ <RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
+ </Register3>
+ <Register4>
+ <RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
+ </Register4>
+ <TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
+ <TraceWindow>
+ <Trace enabled="Yes" />
+ </TraceWindow>
+ <Watch1>
+ <Watches active="1" update="Never" />
+ </Watch1>
+ <Watch2>
+ <Watches active="0" update="Never" />
+ </Watch2>
+ <Watch3>
+ <Watches active="0" update="Never" />
+ </Watch3>
+ <Watch4>
+ <Watches active="0" update="Never" />
+ </Watch4>
+ <Files>
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\E\Dev\FreeRTOS\WorkingCopy\Demo\CORTEX_STM32F103_GCC_Rowley\STM32F10x_Startup.s" y="148" path="C:\E\Dev\FreeRTOS\WorkingCopy\Demo\CORTEX_STM32F103_GCC_Rowley\STM32F10x_Startup.s" left="0" selected="0" name="unnamed" top="27" />
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="46" debugPath="C:\E\Dev\FreeRTOS\WorkingCopy\Demo\CORTEX_STM32F103_GCC_Rowley\main.c" y="142" path="C:\E\Dev\FreeRTOS\WorkingCopy\Demo\CORTEX_STM32F103_GCC_Rowley\main.c" left="0" selected="1" name="unnamed" top="0" />
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="29" debugPath="C:\E\Dev\FreeRTOS\WorkingCopy\Demo\CORTEX_STM32F103_GCC_Rowley\FreeRTOSConfig.h" y="88" path="C:\E\Dev\FreeRTOS\WorkingCopy\Demo\CORTEX_STM32F103_GCC_Rowley\FreeRTOSConfig.h" left="0" selected="0" name="unnamed" top="63" />
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" y="1385" path="C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" left="0" selected="0" name="unnamed" top="1365" />
+ <SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\E\Dev\FreeRTOS\WorkingCopy\Demo\CORTEX_STM32F103_GCC_Rowley\ST Library\src\stm32f10x_gpio.c" y="53" path="C:\E\Dev\FreeRTOS\WorkingCopy\Demo\CORTEX_STM32F103_GCC_Rowley\ST Library\src\stm32f10x_gpio.c" left="0" selected="0" name="unnamed" top="38" />
+ </Files>
+ <ARMCrossStudioWindow activeProject="RTOSDemo" autoConnectTarget="USB CrossConnect for ARM" debugSearchFileMap="" fileDialogInitialDirectory="C:\E\Dev\FreeRTOS\WorkingCopy\Demo\CORTEX_STM32F103_GCC_Rowley\serial" fileDialogDefaultFilter="*.c" autoConnectCapabilities="388991" debugSearchPath="" buildConfiguration="THUMB Flash Debug" />
+</session>
--- /dev/null
+// Copyright (c) 2009 Rowley Associates Limited.\r
+//\r
+// This file may be distributed under the terms of the License Agreement\r
+// provided with this software.\r
+//\r
+// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE\r
+// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\r
+\r
+#ifndef __STM32F10x_H__\r
+#define __STM32F10x_H__\r
+\r
+#define STM32F101C4 0x10114\r
+#define STM32F101C6 0x10116\r
+#define STM32F101C8 0x10118\r
+#define STM32F101CB 0x1011B\r
+\r
+#define STM32F101R4 0x10124\r
+#define STM32F101R6 0x10126\r
+#define STM32F101R8 0x10128\r
+#define STM32F101RB 0x1012B\r
+#define STM32F101RC 0x1012C\r
+#define STM32F101RD 0x1012D\r
+#define STM32F101RE 0x1012E\r
+\r
+#define STM32F101T4 0x10134\r
+#define STM32F101T6 0x10136\r
+#define STM32F101T8 0x10138\r
+\r
+#define STM32F101V8 0x10148\r
+#define STM32F101VB 0x1014B\r
+#define STM32F101VC 0x1014C\r
+#define STM32F101VD 0x1014D\r
+#define STM32F101VE 0x1014E\r
+\r
+#define STM32F101ZC 0x1015C\r
+#define STM32F101ZD 0x1015D\r
+#define STM32F101ZE 0x1015E\r
+\r
+#define STM32F102C4 0x10214\r
+#define STM32F102C6 0x10216\r
+#define STM32F102C8 0x10218\r
+#define STM32F102CB 0x1021B\r
+\r
+#define STM32F102R4 0x10228\r
+#define STM32F102R6 0x1022B\r
+#define STM32F102R8 0x10228\r
+#define STM32F102RB 0x1022B\r
+\r
+#define STM32F103C4 0x10314\r
+#define STM32F103C6 0x10316\r
+#define STM32F103C8 0x10318\r
+#define STM32F103CB 0x1031B\r
+\r
+#define STM32F103R4 0x10324\r
+#define STM32F103R6 0x10326\r
+#define STM32F103R8 0x10328\r
+#define STM32F103RB 0x1032B\r
+#define STM32F103RC 0x1032C\r
+#define STM32F103RD 0x1032D\r
+#define STM32F103RE 0x1032E\r
+\r
+#define STM32F103T4 0x10334\r
+#define STM32F103T6 0x10336\r
+#define STM32F103T8 0x10338\r
+#define STM32F103TB 0x1033B\r
+\r
+#define STM32F103V8 0x10348\r
+#define STM32F103VB 0x1034B\r
+#define STM32F103VC 0x1034C\r
+#define STM32F103VD 0x1034D\r
+#define STM32F103VE 0x1034E\r
+\r
+#define STM32F103ZC 0x1035C\r
+#define STM32F103ZD 0x1035D\r
+#define STM32F103ZE 0x1035E\r
+\r
+#define STM32F105R8 0x10528\r
+#define STM32F105RB 0x1052B\r
+#define STM32F105RC 0x1052C\r
+\r
+#define STM32F105V8 0x10548\r
+#define STM32F105VB 0x1054B\r
+#define STM32F105VC 0x1054C\r
+\r
+#define STM32F107RB 0x1072B\r
+#define STM32F107RC 0x1072C\r
+\r
+#define STM32F107VB 0x1074B\r
+#define STM32F107VC 0x1074C\r
+\r
+#if (__TARGET_PROCESSOR == STM32F101C4)\r
+#include <targets/STM32F101C4.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101C6)\r
+#include <targets/STM32F101C6.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101C8)\r
+#include <targets/STM32F101C6.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101CB)\r
+#include <targets/STM32F101C8.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101R4)\r
+#include <targets/STM32F101R4.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101R6)\r
+#include <targets/STM32F101R6.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101R8)\r
+#include <targets/STM32F101R8.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101RB)\r
+#include <targets/STM32F101RB.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101RC)\r
+#include <targets/STM32F101RC.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101RD)\r
+#include <targets/STM32F101RD.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101RE)\r
+#include <targets/STM32F101RE.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101T4)\r
+#include <targets/STM32F101T4.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101T6)\r
+#include <targets/STM32F101T6.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101T8)\r
+#include <targets/STM32F101T8.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101V8)\r
+#include <targets/STM32F101V8.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101VB)\r
+#include <targets/STM32F101VB.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101VC)\r
+#include <targets/STM32F101VC.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101VD)\r
+#include <targets/STM32F101VD.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101VE)\r
+#include <targets/STM32F101VE.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101ZC)\r
+#include <targets/STM32F101ZC.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101ZD)\r
+#include <targets/STM32F101ZD.h>\r
+#elif (__TARGET_PROCESSOR == STM32F101ZE)\r
+#include <targets/STM32F101ZE.h>\r
+#elif (__TARGET_PROCESSOR == STM32F102C4)\r
+#include <targets/STM32F102C4.h>\r
+#elif (__TARGET_PROCESSOR == STM32F102C6)\r
+#include <targets/STM32F102C6.h>\r
+#elif (__TARGET_PROCESSOR == STM32F102C8)\r
+#include <targets/STM32F102C8.h>\r
+#elif (__TARGET_PROCESSOR == STM32F102CB)\r
+#include <targets/STM32F102CB.h>\r
+#elif (__TARGET_PROCESSOR == STM32F102R4)\r
+#include <targets/STM32F102R4.h>\r
+#elif (__TARGET_PROCESSOR == STM32F102R6)\r
+#include <targets/STM32F102R6.h>\r
+#elif (__TARGET_PROCESSOR == STM32F102R8)\r
+#include <targets/STM32F102R8.h>\r
+#elif (__TARGET_PROCESSOR == STM32F102RB)\r
+#include <targets/STM32F102RB.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103C4)\r
+#include <targets/STM32F103C4.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103C6)\r
+#include <targets/STM32F103C6.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103C8)\r
+#include <targets/STM32F103C8.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103CB)\r
+#include <targets/STM32F103CB.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103R4)\r
+#include <targets/STM32F103R4.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103R6)\r
+#include <targets/STM32F103R6.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103R8)\r
+#include <targets/STM32F101C6.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103RB)\r
+#include <targets/STM32F103RB.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103RC)\r
+#include <targets/STM32F103RC.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103RD)\r
+#include <targets/STM32F103RD.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103RE)\r
+#include <targets/STM32F103RE.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103T4)\r
+#include <targets/STM32F103T4.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103T6)\r
+#include <targets/STM32F103T6.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103T8)\r
+#include <targets/STM32F103T8.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103TB)\r
+#include <targets/STM32F103TB.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103V8)\r
+#include <targets/STM32F103V8.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103VB)\r
+#include <targets/STM32F103VB.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103VC)\r
+#include <targets/STM32F103VC.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103VD)\r
+#include <targets/STM32F103VD.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103VE)\r
+#include <targets/STM32F103VE.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103ZC)\r
+#include <targets/STM32F103ZC.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103ZD)\r
+#include <targets/STM32F103ZD.h>\r
+#elif (__TARGET_PROCESSOR == STM32F103ZE)\r
+#include <targets/STM32F103ZE.h>\r
+#elif (__TARGET_PROCESSOR == STM32F105R8)\r
+#include <targets/STM32F105R8.h>\r
+#elif (__TARGET_PROCESSOR == STM32F105RB)\r
+#include <targets/STM32F105RB.h>\r
+#elif (__TARGET_PROCESSOR == STM32F105RC)\r
+#include <targets/STM32F105RC.h>\r
+#elif (__TARGET_PROCESSOR == STM32F105V8)\r
+#include <targets/STM32F105V8.h>\r
+#elif (__TARGET_PROCESSOR == STM32F105VB)\r
+#include <targets/STM32F105VB.h>\r
+#elif (__TARGET_PROCESSOR == STM32F105VC)\r
+#include <targets/STM32F105VC.h>\r
+#elif (__TARGET_PROCESSOR == STM32F107RB)\r
+#include <targets/STM32F107RB.h>\r
+#elif (__TARGET_PROCESSOR == STM32F107RC)\r
+#include <targets/STM32F107RC.h>\r
+#elif (__TARGET_PROCESSOR == STM32F107VB)\r
+#include <targets/STM32F107VB.h>\r
+#elif (__TARGET_PROCESSOR == STM32F107VC)\r
+#include <targets/STM32F107VC.h>\r
+#else\r
+#error bad __TARGET_PROCESSOR\r
+#endif\r
+\r
+#endif
\ No newline at end of file
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : cortexm3_macro.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : Header file for cortexm3_macro.s.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __CORTEXM3_MACRO_H\r
+#define __CORTEXM3_MACRO_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_type.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void __WFI(void);\r
+void __WFE(void);\r
+void __SEV(void);\r
+void __ISB(void);\r
+void __DSB(void);\r
+void __DMB(void);\r
+void __SVC(void);\r
+u32 __MRS_CONTROL(void);\r
+void __MSR_CONTROL(u32 Control);\r
+u32 __MRS_PSP(void);\r
+void __MSR_PSP(u32 TopOfProcessStack);\r
+u32 __MRS_MSP(void);\r
+void __MSR_MSP(u32 TopOfMainStack);\r
+void __RESETPRIMASK(void);\r
+void __SETPRIMASK(void);\r
+u32 __READ_PRIMASK(void);\r
+void __RESETFAULTMASK(void);\r
+void __SETFAULTMASK(void);\r
+u32 __READ_FAULTMASK(void);\r
+void __BASEPRICONFIG(u32 NewPriority);\r
+u32 __GetBASEPRI(void);\r
+u16 __REV_HalfWord(u16 Data);\r
+u32 __REV_Word(u32 Data);\r
+\r
+#endif /* __CORTEXM3_MACRO_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_adc.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* ADC firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_ADC_H\r
+#define __STM32F10x_ADC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* ADC Init structure definition */\r
+typedef struct\r
+{\r
+ u32 ADC_Mode;\r
+ FunctionalState ADC_ScanConvMode; \r
+ FunctionalState ADC_ContinuousConvMode;\r
+ u32 ADC_ExternalTrigConv;\r
+ u32 ADC_DataAlign;\r
+ u8 ADC_NbrOfChannel;\r
+}ADC_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+#define IS_ADC_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == ADC2_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == ADC3_BASE))\r
+ \r
+#define IS_ADC_DMA_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == ADC3_BASE))\r
+\r
+/* ADC dual mode -------------------------------------------------------------*/\r
+#define ADC_Mode_Independent ((u32)0x00000000)\r
+#define ADC_Mode_RegInjecSimult ((u32)0x00010000)\r
+#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000)\r
+#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000)\r
+#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000)\r
+#define ADC_Mode_InjecSimult ((u32)0x00050000)\r
+#define ADC_Mode_RegSimult ((u32)0x00060000)\r
+#define ADC_Mode_FastInterl ((u32)0x00070000)\r
+#define ADC_Mode_SlowInterl ((u32)0x00080000)\r
+#define ADC_Mode_AlterTrig ((u32)0x00090000)\r
+\r
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \\r
+ ((MODE) == ADC_Mode_RegInjecSimult) || \\r
+ ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \\r
+ ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \\r
+ ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \\r
+ ((MODE) == ADC_Mode_InjecSimult) || \\r
+ ((MODE) == ADC_Mode_RegSimult) || \\r
+ ((MODE) == ADC_Mode_FastInterl) || \\r
+ ((MODE) == ADC_Mode_SlowInterl) || \\r
+ ((MODE) == ADC_Mode_AlterTrig))\r
+\r
+/* ADC extrenal trigger sources for regular channels conversion --------------*/\r
+/* for ADC1 and ADC2 */\r
+#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000)\r
+#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000)\r
+#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000)\r
+#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000)\r
+#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000)\r
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((u32)0x000C0000)\r
+/* for ADC1, ADC2 and ADC3 */\r
+#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000)\r
+#define ADC_ExternalTrigConv_None ((u32)0x000E0000)\r
+/* for ADC3 */\r
+#define ADC_ExternalTrigConv_T3_CC1 ((u32)0x00000000)\r
+#define ADC_ExternalTrigConv_T2_CC3 ((u32)0x00020000)\r
+#define ADC_ExternalTrigConv_T8_CC1 ((u32)0x00060000)\r
+#define ADC_ExternalTrigConv_T8_TRGO ((u32)0x00080000)\r
+#define ADC_ExternalTrigConv_T5_CC1 ((u32)0x000A0000)\r
+#define ADC_ExternalTrigConv_T5_CC3 ((u32)0x000C0000)\r
+\r
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_None) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))\r
+\r
+/* ADC data align ------------------------------------------------------------*/\r
+#define ADC_DataAlign_Right ((u32)0x00000000)\r
+#define ADC_DataAlign_Left ((u32)0x00000800)\r
+\r
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \\r
+ ((ALIGN) == ADC_DataAlign_Left))\r
+\r
+/* ADC channels --------------------------------------------------------------*/\r
+#define ADC_Channel_0 ((u8)0x00)\r
+#define ADC_Channel_1 ((u8)0x01)\r
+#define ADC_Channel_2 ((u8)0x02)\r
+#define ADC_Channel_3 ((u8)0x03)\r
+#define ADC_Channel_4 ((u8)0x04)\r
+#define ADC_Channel_5 ((u8)0x05)\r
+#define ADC_Channel_6 ((u8)0x06)\r
+#define ADC_Channel_7 ((u8)0x07)\r
+#define ADC_Channel_8 ((u8)0x08)\r
+#define ADC_Channel_9 ((u8)0x09)\r
+#define ADC_Channel_10 ((u8)0x0A)\r
+#define ADC_Channel_11 ((u8)0x0B)\r
+#define ADC_Channel_12 ((u8)0x0C)\r
+#define ADC_Channel_13 ((u8)0x0D)\r
+#define ADC_Channel_14 ((u8)0x0E)\r
+#define ADC_Channel_15 ((u8)0x0F)\r
+#define ADC_Channel_16 ((u8)0x10)\r
+#define ADC_Channel_17 ((u8)0x11)\r
+\r
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \\r
+ ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \\r
+ ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \\r
+ ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \\r
+ ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \\r
+ ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \\r
+ ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \\r
+ ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \\r
+ ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))\r
+\r
+/* ADC sampling times --------------------------------------------------------*/\r
+#define ADC_SampleTime_1Cycles5 ((u8)0x00)\r
+#define ADC_SampleTime_7Cycles5 ((u8)0x01)\r
+#define ADC_SampleTime_13Cycles5 ((u8)0x02)\r
+#define ADC_SampleTime_28Cycles5 ((u8)0x03)\r
+#define ADC_SampleTime_41Cycles5 ((u8)0x04)\r
+#define ADC_SampleTime_55Cycles5 ((u8)0x05)\r
+#define ADC_SampleTime_71Cycles5 ((u8)0x06)\r
+#define ADC_SampleTime_239Cycles5 ((u8)0x07)\r
+\r
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_7Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_13Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_28Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_41Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_55Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_71Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_239Cycles5))\r
+\r
+/* ADC extrenal trigger sources for injected channels conversion -------------*/\r
+/* For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000)\r
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000)\r
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000)\r
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000)\r
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((u32)0x00006000)\r
+/* For ADC1, ADC2 and ADC3 */\r
+#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000)\r
+#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000)\r
+#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000)\r
+/* For ADC3 */\r
+#define ADC_ExternalTrigInjecConv_T4_CC3 ((u32)0x00002000)\r
+#define ADC_ExternalTrigInjecConv_T8_CC2 ((u32)0x00003000)\r
+#define ADC_ExternalTrigInjecConv_T8_CC4 ((u32)0x00004000)\r
+#define ADC_ExternalTrigInjecConv_T5_TRGO ((u32)0x00005000)\r
+#define ADC_ExternalTrigInjecConv_T5_CC4 ((u32)0x00006000)\r
+\r
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))\r
+\r
+/* ADC injected channel selection --------------------------------------------*/\r
+#define ADC_InjectedChannel_1 ((u8)0x14)\r
+#define ADC_InjectedChannel_2 ((u8)0x18)\r
+#define ADC_InjectedChannel_3 ((u8)0x1C)\r
+#define ADC_InjectedChannel_4 ((u8)0x20)\r
+\r
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_2) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_3) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_4))\r
+\r
+/* ADC analog watchdog selection ---------------------------------------------*/\r
+#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200)\r
+#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200)\r
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200)\r
+#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000)\r
+#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000)\r
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000)\r
+#define ADC_AnalogWatchdog_None ((u32)0x00000000)\r
+\r
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_None))\r
+\r
+/* ADC interrupts definition -------------------------------------------------*/\r
+#define ADC_IT_EOC ((u16)0x0220)\r
+#define ADC_IT_AWD ((u16)0x0140)\r
+#define ADC_IT_JEOC ((u16)0x0480)\r
+\r
+#define IS_ADC_IT(IT) ((((IT) & (u16)0xF81F) == 0x00) && ((IT) != 0x00))\r
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \\r
+ ((IT) == ADC_IT_JEOC))\r
+\r
+/* ADC flags definition ------------------------------------------------------*/\r
+#define ADC_FLAG_AWD ((u8)0x01)\r
+#define ADC_FLAG_EOC ((u8)0x02)\r
+#define ADC_FLAG_JEOC ((u8)0x04)\r
+#define ADC_FLAG_JSTRT ((u8)0x08)\r
+#define ADC_FLAG_STRT ((u8)0x10)\r
+\r
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (u8)0xE0) == 0x00) && ((FLAG) != 0x00))\r
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \\r
+ ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \\r
+ ((FLAG) == ADC_FLAG_STRT))\r
+\r
+/* ADC thresholds ------------------------------------------------------------*/\r
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)\r
+\r
+/* ADC injected offset -------------------------------------------------------*/\r
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)\r
+\r
+/* ADC injected length -------------------------------------------------------*/\r
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))\r
+\r
+/* ADC injected rank ---------------------------------------------------------*/\r
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))\r
+\r
+/* ADC regular length --------------------------------------------------------*/\r
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))\r
+\r
+/* ADC regular rank ----------------------------------------------------------*/\r
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))\r
+\r
+/* ADC regular discontinuous mode number -------------------------------------*/\r
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void ADC_DeInit(ADC_TypeDef* ADCx);\r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState);\r
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);\r
+void ADC_StartCalibration(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);\r
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number);\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);\r
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+u16 ADC_GetConversionValue(ADC_TypeDef* ADCx);\r
+u32 ADC_GetDualModeConversionValue(void);\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv);\r
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length);\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset);\r
+u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel);\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog);\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold);\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel);\r
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG);\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG);\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT);\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT);\r
+\r
+#endif /*__STM32F10x_ADC_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_bkp.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* BKP firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_BKP_H\r
+#define __STM32F10x_BKP_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Tamper Pin active level */\r
+#define BKP_TamperPinLevel_High ((u16)0x0000)\r
+#define BKP_TamperPinLevel_Low ((u16)0x0001)\r
+\r
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \\r
+ ((LEVEL) == BKP_TamperPinLevel_Low))\r
+\r
+/* RTC output source to output on the Tamper pin */\r
+#define BKP_RTCOutputSource_None ((u16)0x0000)\r
+#define BKP_RTCOutputSource_CalibClock ((u16)0x0080)\r
+#define BKP_RTCOutputSource_Alarm ((u16)0x0100)\r
+#define BKP_RTCOutputSource_Second ((u16)0x0300)\r
+\r
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \\r
+ ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \\r
+ ((SOURCE) == BKP_RTCOutputSource_Alarm) || \\r
+ ((SOURCE) == BKP_RTCOutputSource_Second))\r
+\r
+/* Data Backup Register */\r
+#define BKP_DR1 ((u16)0x0004)\r
+#define BKP_DR2 ((u16)0x0008)\r
+#define BKP_DR3 ((u16)0x000C)\r
+#define BKP_DR4 ((u16)0x0010)\r
+#define BKP_DR5 ((u16)0x0014)\r
+#define BKP_DR6 ((u16)0x0018)\r
+#define BKP_DR7 ((u16)0x001C)\r
+#define BKP_DR8 ((u16)0x0020)\r
+#define BKP_DR9 ((u16)0x0024)\r
+#define BKP_DR10 ((u16)0x0028)\r
+#define BKP_DR11 ((u16)0x0040)\r
+#define BKP_DR12 ((u16)0x0044)\r
+#define BKP_DR13 ((u16)0x0048)\r
+#define BKP_DR14 ((u16)0x004C)\r
+#define BKP_DR15 ((u16)0x0050)\r
+#define BKP_DR16 ((u16)0x0054)\r
+#define BKP_DR17 ((u16)0x0058)\r
+#define BKP_DR18 ((u16)0x005C)\r
+#define BKP_DR19 ((u16)0x0060)\r
+#define BKP_DR20 ((u16)0x0064)\r
+#define BKP_DR21 ((u16)0x0068)\r
+#define BKP_DR22 ((u16)0x006C)\r
+#define BKP_DR23 ((u16)0x0070)\r
+#define BKP_DR24 ((u16)0x0074)\r
+#define BKP_DR25 ((u16)0x0078)\r
+#define BKP_DR26 ((u16)0x007C)\r
+#define BKP_DR27 ((u16)0x0080)\r
+#define BKP_DR28 ((u16)0x0084)\r
+#define BKP_DR29 ((u16)0x0088)\r
+#define BKP_DR30 ((u16)0x008C)\r
+#define BKP_DR31 ((u16)0x0090)\r
+#define BKP_DR32 ((u16)0x0094)\r
+#define BKP_DR33 ((u16)0x0098)\r
+#define BKP_DR34 ((u16)0x009C)\r
+#define BKP_DR35 ((u16)0x00A0)\r
+#define BKP_DR36 ((u16)0x00A4)\r
+#define BKP_DR37 ((u16)0x00A8)\r
+#define BKP_DR38 ((u16)0x00AC)\r
+#define BKP_DR39 ((u16)0x00B0)\r
+#define BKP_DR40 ((u16)0x00B4)\r
+#define BKP_DR41 ((u16)0x00B8)\r
+#define BKP_DR42 ((u16)0x00BC)\r
+\r
+#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \\r
+ ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \\r
+ ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \\r
+ ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \\r
+ ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \\r
+ ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \\r
+ ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \\r
+ ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \\r
+ ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \\r
+ ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \\r
+ ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \\r
+ ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \\r
+ ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \\r
+ ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))\r
+\r
+#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void BKP_DeInit(void);\r
+void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel);\r
+void BKP_TamperPinCmd(FunctionalState NewState);\r
+void BKP_ITConfig(FunctionalState NewState);\r
+void BKP_RTCOutputConfig(u16 BKP_RTCOutputSource);\r
+void BKP_SetRTCCalibrationValue(u8 CalibrationValue);\r
+void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data);\r
+u16 BKP_ReadBackupRegister(u16 BKP_DR);\r
+FlagStatus BKP_GetFlagStatus(void);\r
+void BKP_ClearFlag(void);\r
+ITStatus BKP_GetITStatus(void);\r
+void BKP_ClearITPendingBit(void);\r
+\r
+#endif /* __STM32F10x_BKP_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_can.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* CAN firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_CAN_H\r
+#define __STM32F10x_CAN_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* CAN init structure definition */\r
+typedef struct\r
+{\r
+ FunctionalState CAN_TTCM;\r
+ FunctionalState CAN_ABOM;\r
+ FunctionalState CAN_AWUM;\r
+ FunctionalState CAN_NART;\r
+ FunctionalState CAN_RFLM;\r
+ FunctionalState CAN_TXFP;\r
+ u8 CAN_Mode;\r
+ u8 CAN_SJW;\r
+ u8 CAN_BS1;\r
+ u8 CAN_BS2;\r
+ u16 CAN_Prescaler;\r
+} CAN_InitTypeDef;\r
+\r
+/* CAN filter init structure definition */\r
+typedef struct\r
+{\r
+ u8 CAN_FilterNumber;\r
+ u8 CAN_FilterMode;\r
+ u8 CAN_FilterScale;\r
+ u16 CAN_FilterIdHigh;\r
+ u16 CAN_FilterIdLow;\r
+ u16 CAN_FilterMaskIdHigh;\r
+ u16 CAN_FilterMaskIdLow;\r
+ u16 CAN_FilterFIFOAssignment;\r
+ FunctionalState CAN_FilterActivation;\r
+} CAN_FilterInitTypeDef;\r
+\r
+/* CAN Tx message structure definition */\r
+typedef struct\r
+{\r
+ u32 StdId;\r
+ u32 ExtId;\r
+ u8 IDE;\r
+ u8 RTR;\r
+ u8 DLC;\r
+ u8 Data[8];\r
+} CanTxMsg;\r
+\r
+/* CAN Rx message structure definition */\r
+typedef struct\r
+{\r
+ u32 StdId;\r
+ u32 ExtId;\r
+ u8 IDE;\r
+ u8 RTR;\r
+ u8 DLC;\r
+ u8 Data[8];\r
+ u8 FMI;\r
+} CanRxMsg;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/* CAN sleep constants */\r
+#define CANINITFAILED ((u8)0x00) /* CAN initialization failed */\r
+#define CANINITOK ((u8)0x01) /* CAN initialization failed */\r
+\r
+/* CAN operating mode */\r
+#define CAN_Mode_Normal ((u8)0x00) /* normal mode */\r
+#define CAN_Mode_LoopBack ((u8)0x01) /* loopback mode */\r
+#define CAN_Mode_Silent ((u8)0x02) /* silent mode */\r
+#define CAN_Mode_Silent_LoopBack ((u8)0x03) /* loopback combined with silent mode */\r
+\r
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \\r
+ ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))\r
+\r
+/* CAN synchronisation jump width */\r
+#define CAN_SJW_1tq ((u8)0x00) /* 1 time quantum */\r
+#define CAN_SJW_2tq ((u8)0x01) /* 2 time quantum */\r
+#define CAN_SJW_3tq ((u8)0x02) /* 3 time quantum */\r
+#define CAN_SJW_4tq ((u8)0x03) /* 4 time quantum */\r
+\r
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \\r
+ ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))\r
+\r
+/* time quantum in bit segment 1 */\r
+#define CAN_BS1_1tq ((u8)0x00) /* 1 time quantum */\r
+#define CAN_BS1_2tq ((u8)0x01) /* 2 time quantum */\r
+#define CAN_BS1_3tq ((u8)0x02) /* 3 time quantum */\r
+#define CAN_BS1_4tq ((u8)0x03) /* 4 time quantum */\r
+#define CAN_BS1_5tq ((u8)0x04) /* 5 time quantum */\r
+#define CAN_BS1_6tq ((u8)0x05) /* 6 time quantum */\r
+#define CAN_BS1_7tq ((u8)0x06) /* 7 time quantum */\r
+#define CAN_BS1_8tq ((u8)0x07) /* 8 time quantum */\r
+#define CAN_BS1_9tq ((u8)0x08) /* 9 time quantum */\r
+#define CAN_BS1_10tq ((u8)0x09) /* 10 time quantum */\r
+#define CAN_BS1_11tq ((u8)0x0A) /* 11 time quantum */\r
+#define CAN_BS1_12tq ((u8)0x0B) /* 12 time quantum */\r
+#define CAN_BS1_13tq ((u8)0x0C) /* 13 time quantum */\r
+#define CAN_BS1_14tq ((u8)0x0D) /* 14 time quantum */\r
+#define CAN_BS1_15tq ((u8)0x0E) /* 15 time quantum */\r
+#define CAN_BS1_16tq ((u8)0x0F) /* 16 time quantum */\r
+\r
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)\r
+\r
+/* time quantum in bit segment 2 */\r
+#define CAN_BS2_1tq ((u8)0x00) /* 1 time quantum */\r
+#define CAN_BS2_2tq ((u8)0x01) /* 2 time quantum */\r
+#define CAN_BS2_3tq ((u8)0x02) /* 3 time quantum */\r
+#define CAN_BS2_4tq ((u8)0x03) /* 4 time quantum */\r
+#define CAN_BS2_5tq ((u8)0x04) /* 5 time quantum */\r
+#define CAN_BS2_6tq ((u8)0x05) /* 6 time quantum */\r
+#define CAN_BS2_7tq ((u8)0x06) /* 7 time quantum */\r
+#define CAN_BS2_8tq ((u8)0x07) /* 8 time quantum */\r
+\r
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)\r
+\r
+/* CAN clock prescaler */\r
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))\r
+\r
+/* CAN filter number */\r
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)\r
+\r
+/* CAN filter mode */\r
+#define CAN_FilterMode_IdMask ((u8)0x00) /* id/mask mode */\r
+#define CAN_FilterMode_IdList ((u8)0x01) /* identifier list mode */\r
+\r
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \\r
+ ((MODE) == CAN_FilterMode_IdList))\r
+\r
+/* CAN filter scale */\r
+#define CAN_FilterScale_16bit ((u8)0x00) /* 16-bit filter scale */\r
+#define CAN_FilterScale_32bit ((u8)0x01) /* 2-bit filter scale */\r
+\r
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \\r
+ ((SCALE) == CAN_FilterScale_32bit))\r
+\r
+/* CAN filter FIFO assignation */\r
+#define CAN_FilterFIFO0 ((u8)0x00) /* Filter FIFO 0 assignment for filter x */\r
+#define CAN_FilterFIFO1 ((u8)0x01) /* Filter FIFO 1 assignment for filter x */\r
+\r
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \\r
+ ((FIFO) == CAN_FilterFIFO1))\r
+\r
+/* CAN Tx */\r
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((u8)0x02))\r
+#define IS_CAN_STDID(STDID) ((STDID) <= ((u32)0x7FF))\r
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((u32)0x1FFFFFFF))\r
+#define IS_CAN_DLC(DLC) ((DLC) <= ((u8)0x08))\r
+\r
+/* CAN identifier type */\r
+#define CAN_ID_STD ((u32)0x00000000) /* Standard Id */\r
+#define CAN_ID_EXT ((u32)0x00000004) /* Extended Id */\r
+\r
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT))\r
+\r
+/* CAN remote transmission request */\r
+#define CAN_RTR_DATA ((u32)0x00000000) /* Data frame */\r
+#define CAN_RTR_REMOTE ((u32)0x00000002) /* Remote frame */\r
+\r
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))\r
+\r
+/* CAN transmit constants */\r
+#define CANTXFAILED ((u8)0x00) /* CAN transmission failed */\r
+#define CANTXOK ((u8)0x01) /* CAN transmission succeeded */\r
+#define CANTXPENDING ((u8)0x02) /* CAN transmission pending */\r
+#define CAN_NO_MB ((u8)0x04) /* CAN cell did not provide an empty mailbox */\r
+\r
+/* CAN receive FIFO number constants */\r
+#define CAN_FIFO0 ((u8)0x00) /* CAN FIFO0 used to receive */\r
+#define CAN_FIFO1 ((u8)0x01) /* CAN FIFO1 used to receive */\r
+\r
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))\r
+\r
+/* CAN sleep constants */\r
+#define CANSLEEPFAILED ((u8)0x00) /* CAN did not enter the sleep mode */\r
+#define CANSLEEPOK ((u8)0x01) /* CAN entered the sleep mode */\r
+\r
+/* CAN wake up constants */\r
+#define CANWAKEUPFAILED ((u8)0x00) /* CAN did not leave the sleep mode */\r
+#define CANWAKEUPOK ((u8)0x01) /* CAN leaved the sleep mode */\r
+\r
+/* CAN flags */\r
+#define CAN_FLAG_EWG ((u32)0x00000001) /* Error Warning Flag */\r
+#define CAN_FLAG_EPV ((u32)0x00000002) /* Error Passive Flag */\r
+#define CAN_FLAG_BOF ((u32)0x00000004) /* Bus-Off Flag */\r
+\r
+#define IS_CAN_FLAG(FLAG) (((FLAG) == CAN_FLAG_EWG) || ((FLAG) == CAN_FLAG_EPV) ||\\r
+ ((FLAG) == CAN_FLAG_BOF))\r
+\r
+/* CAN interrupts */\r
+#define CAN_IT_RQCP0 ((u32)0x00000005) /* Request completed mailbox 0 */\r
+#define CAN_IT_RQCP1 ((u32)0x00000006) /* Request completed mailbox 1 */\r
+#define CAN_IT_RQCP2 ((u32)0x00000007) /* Request completed mailbox 2 */\r
+#define CAN_IT_TME ((u32)0x00000001) /* Transmit mailbox empty */\r
+#define CAN_IT_FMP0 ((u32)0x00000002) /* FIFO 0 message pending */\r
+#define CAN_IT_FF0 ((u32)0x00000004) /* FIFO 0 full */\r
+#define CAN_IT_FOV0 ((u32)0x00000008) /* FIFO 0 overrun */\r
+#define CAN_IT_FMP1 ((u32)0x00000010) /* FIFO 1 message pending */\r
+#define CAN_IT_FF1 ((u32)0x00000020) /* FIFO 1 full */\r
+#define CAN_IT_FOV1 ((u32)0x00000040) /* FIFO 1 overrun */\r
+#define CAN_IT_EWG ((u32)0x00000100) /* Error warning */\r
+#define CAN_IT_EPV ((u32)0x00000200) /* Error passive */\r
+#define CAN_IT_BOF ((u32)0x00000400) /* Bus-off */\r
+#define CAN_IT_LEC ((u32)0x00000800) /* Last error code */\r
+#define CAN_IT_ERR ((u32)0x00008000) /* Error */\r
+#define CAN_IT_WKU ((u32)0x00010000) /* Wake-up */\r
+#define CAN_IT_SLK ((u32)0x00020000) /* Sleep */\r
+\r
+#define IS_CAN_ITConfig(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\\r
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\\r
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\\r
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\\r
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\r
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
+\r
+#define IS_CAN_ITStatus(IT) (((IT) == CAN_IT_RQCP0) || ((IT) == CAN_IT_RQCP1) ||\\r
+ ((IT) == CAN_IT_RQCP2) || ((IT) == CAN_IT_FF0) ||\\r
+ ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\\r
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\\r
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported function protypes ----------------------------------------------- */\r
+void CAN_DeInit(void);\r
+u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct);\r
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);\r
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);\r
+void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState);\r
+u8 CAN_Transmit(CanTxMsg* TxMessage);\r
+u8 CAN_TransmitStatus(u8 TransmitMailbox);\r
+void CAN_CancelTransmit(u8 Mailbox);\r
+void CAN_FIFORelease(u8 FIFONumber);\r
+u8 CAN_MessagePending(u8 FIFONumber);\r
+void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage);\r
+u8 CAN_Sleep(void);\r
+u8 CAN_WakeUp(void);\r
+FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG);\r
+void CAN_ClearFlag(u32 CAN_FLAG);\r
+ITStatus CAN_GetITStatus(u32 CAN_IT);\r
+void CAN_ClearITPendingBit(u32 CAN_IT);\r
+\r
+#endif /* __STM32F10x_CAN_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_crc.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* CRC firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_CRC_H\r
+#define __STM32F10x_CRC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void CRC_ResetDR(void);\r
+u32 CRC_CalcCRC(u32 Data);\r
+u32 CRC_CalcBlockCRC(u32 pBuffer[], u32 BufferLength);\r
+u32 CRC_GetCRC(void);\r
+void CRC_SetIDRegister(u8 IDValue);\r
+u8 CRC_GetIDRegister(void);\r
+\r
+#endif /* __STM32F10x_CRC_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_dac.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* DAC firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_DAC_H\r
+#define __STM32F10x_DAC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* DAC Init structure definition */\r
+typedef struct\r
+{\r
+ u32 DAC_Trigger;\r
+ u32 DAC_WaveGeneration;\r
+ u32 DAC_LFSRUnmask_TriangleAmplitude;\r
+ u32 DAC_OutputBuffer; \r
+}DAC_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* DAC trigger selection */\r
+#define DAC_Trigger_None ((u32)0x00000000)\r
+#define DAC_Trigger_T6_TRGO ((u32)0x00000004)\r
+#define DAC_Trigger_T8_TRGO ((u32)0x0000000C)\r
+#define DAC_Trigger_T7_TRGO ((u32)0x00000014)\r
+#define DAC_Trigger_T5_TRGO ((u32)0x0000001C)\r
+#define DAC_Trigger_T2_TRGO ((u32)0x00000024)\r
+#define DAC_Trigger_T4_TRGO ((u32)0x0000002C)\r
+#define DAC_Trigger_Ext_IT9 ((u32)0x00000034)\r
+#define DAC_Trigger_Software ((u32)0x0000003C)\r
+\r
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \\r
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T8_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T5_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \\r
+ ((TRIGGER) == DAC_Trigger_Software))\r
+\r
+/* DAC wave generation */\r
+#define DAC_WaveGeneration_None ((u32)0x00000000)\r
+#define DAC_WaveGeneration_Noise ((u32)0x00000040)\r
+#define DAC_WaveGeneration_Triangle ((u32)0x00000080)\r
+\r
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \\r
+ ((WAVE) == DAC_WaveGeneration_Noise) || \\r
+ ((WAVE) == DAC_WaveGeneration_Triangle))\r
+\r
+/* DAC noise wave generation mask / triangle wave generation max amplitude */\r
+#define DAC_LFSRUnmask_Bit0 ((u32)0x00000000)\r
+#define DAC_LFSRUnmask_Bits1_0 ((u32)0x00000100)\r
+#define DAC_LFSRUnmask_Bits2_0 ((u32)0x00000200)\r
+#define DAC_LFSRUnmask_Bits3_0 ((u32)0x00000300)\r
+#define DAC_LFSRUnmask_Bits4_0 ((u32)0x00000400)\r
+#define DAC_LFSRUnmask_Bits5_0 ((u32)0x00000500)\r
+#define DAC_LFSRUnmask_Bits6_0 ((u32)0x00000600)\r
+#define DAC_LFSRUnmask_Bits7_0 ((u32)0x00000700)\r
+#define DAC_LFSRUnmask_Bits8_0 ((u32)0x00000800)\r
+#define DAC_LFSRUnmask_Bits9_0 ((u32)0x00000900)\r
+#define DAC_LFSRUnmask_Bits10_0 ((u32)0x00000A00)\r
+#define DAC_LFSRUnmask_Bits11_0 ((u32)0x00000B00)\r
+\r
+#define DAC_TriangleAmplitude_1 ((u32)0x00000000)\r
+#define DAC_TriangleAmplitude_3 ((u32)0x00000100)\r
+#define DAC_TriangleAmplitude_7 ((u32)0x00000200)\r
+#define DAC_TriangleAmplitude_15 ((u32)0x00000300)\r
+#define DAC_TriangleAmplitude_31 ((u32)0x00000400)\r
+#define DAC_TriangleAmplitude_63 ((u32)0x00000500)\r
+#define DAC_TriangleAmplitude_127 ((u32)0x00000600)\r
+#define DAC_TriangleAmplitude_255 ((u32)0x00000700)\r
+#define DAC_TriangleAmplitude_511 ((u32)0x00000800)\r
+#define DAC_TriangleAmplitude_1023 ((u32)0x00000900)\r
+#define DAC_TriangleAmplitude_2047 ((u32)0x00000A00)\r
+#define DAC_TriangleAmplitude_4095 ((u32)0x00000B00)\r
+\r
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_3) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_7) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_15) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_31) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_63) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_127) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_255) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_511) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_4095))\r
+\r
+/* DAC output buffer */\r
+#define DAC_OutputBuffer_Enable ((u32)0x00000000)\r
+#define DAC_OutputBuffer_Disable ((u32)0x00000002)\r
+\r
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \\r
+ ((STATE) == DAC_OutputBuffer_Disable))\r
+\r
+/* DAC Channel selection */\r
+#define DAC_Channel_1 ((u32)0x00000000)\r
+#define DAC_Channel_2 ((u32)0x00000010)\r
+\r
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \\r
+ ((CHANNEL) == DAC_Channel_2))\r
+\r
+/* DAC data alignement */\r
+#define DAC_Align_12b_R ((u32)0x00000000)\r
+#define DAC_Align_12b_L ((u32)0x00000004)\r
+#define DAC_Align_8b_R ((u32)0x00000008)\r
+\r
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \\r
+ ((ALIGN) == DAC_Align_12b_L) || \\r
+ ((ALIGN) == DAC_Align_8b_R))\r
+\r
+/* DAC wave generation */\r
+#define DAC_Wave_Noise ((u32)0x00000040)\r
+#define DAC_Wave_Triangle ((u32)0x00000080)\r
+\r
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \\r
+ ((WAVE) == DAC_Wave_Triangle))\r
+\r
+/* DAC data ------------------------------------------------------------------*/\r
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+void DAC_DeInit(void);\r
+void DAC_Init(u32 DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_Cmd(u32 DAC_Channel, FunctionalState NewState);\r
+void DAC_DMACmd(u32 DAC_Channel, FunctionalState NewState);\r
+void DAC_SoftwareTriggerCmd(u32 DAC_Channel, FunctionalState NewState);\r
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);\r
+void DAC_WaveGenerationCmd(u32 DAC_Channel, u32 DAC_Wave, FunctionalState NewState);\r
+void DAC_SetChannel1Data(u32 DAC_Align, u16 Data);\r
+void DAC_SetChannel2Data(u32 DAC_Align, u16 Data);\r
+void DAC_SetDualChannelData(u32 DAC_Align, u16 Data2, u16 Data1);\r
+u16 DAC_GetDataOutputValue(u32 DAC_Channel);\r
+\r
+#endif /*__STM32F10x_DAC_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_dbgmcu.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* DBGMCU firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_DBGMCU_H\r
+#define __STM32F10x_DBGMCU_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+#define DBGMCU_SLEEP ((u32)0x00000001)\r
+#define DBGMCU_STOP ((u32)0x00000002)\r
+#define DBGMCU_STANDBY ((u32)0x00000004)\r
+#define DBGMCU_IWDG_STOP ((u32)0x00000100)\r
+#define DBGMCU_WWDG_STOP ((u32)0x00000200)\r
+#define DBGMCU_TIM1_STOP ((u32)0x00000400)\r
+#define DBGMCU_TIM2_STOP ((u32)0x00000800)\r
+#define DBGMCU_TIM3_STOP ((u32)0x00001000)\r
+#define DBGMCU_TIM4_STOP ((u32)0x00002000)\r
+#define DBGMCU_CAN_STOP ((u32)0x00004000)\r
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((u32)0x00008000)\r
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((u32)0x00010000)\r
+#define DBGMCU_TIM5_STOP ((u32)0x00020000)\r
+#define DBGMCU_TIM6_STOP ((u32)0x00040000)\r
+#define DBGMCU_TIM7_STOP ((u32)0x00080000)\r
+#define DBGMCU_TIM8_STOP ((u32)0x00100000)\r
+ \r
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFE000F8) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+u32 DBGMCU_GetREVID(void);\r
+u32 DBGMCU_GetDEVID(void);\r
+void DBGMCU_Config(u32 DBGMCU_Periph, FunctionalState NewState);\r
+\r
+#endif /* __STM32F10x_DBGMCU_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
+\r
+\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_dma.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* DMA firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_DMA_H\r
+#define __STM32F10x_DMA_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* DMA Init structure definition */\r
+typedef struct\r
+{\r
+ u32 DMA_PeripheralBaseAddr;\r
+ u32 DMA_MemoryBaseAddr;\r
+ u32 DMA_DIR;\r
+ u32 DMA_BufferSize;\r
+ u32 DMA_PeripheralInc;\r
+ u32 DMA_MemoryInc;\r
+ u32 DMA_PeripheralDataSize;\r
+ u32 DMA_MemoryDataSize;\r
+ u32 DMA_Mode;\r
+ u32 DMA_Priority;\r
+ u32 DMA_M2M;\r
+}DMA_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+#define IS_DMA_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == DMA1_Channel1_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == DMA1_Channel2_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == DMA1_Channel3_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == DMA1_Channel4_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == DMA1_Channel5_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == DMA1_Channel6_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == DMA1_Channel7_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == DMA2_Channel1_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == DMA2_Channel2_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == DMA2_Channel3_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == DMA2_Channel4_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == DMA2_Channel5_BASE))\r
+\r
+/* DMA data transfer direction -----------------------------------------------*/\r
+#define DMA_DIR_PeripheralDST ((u32)0x00000010)\r
+#define DMA_DIR_PeripheralSRC ((u32)0x00000000)\r
+\r
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \\r
+ ((DIR) == DMA_DIR_PeripheralSRC))\r
+\r
+/* DMA peripheral incremented mode -------------------------------------------*/\r
+#define DMA_PeripheralInc_Enable ((u32)0x00000040)\r
+#define DMA_PeripheralInc_Disable ((u32)0x00000000)\r
+\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \\r
+ ((STATE) == DMA_PeripheralInc_Disable))\r
+\r
+/* DMA memory incremented mode -----------------------------------------------*/\r
+#define DMA_MemoryInc_Enable ((u32)0x00000080)\r
+#define DMA_MemoryInc_Disable ((u32)0x00000000)\r
+\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \\r
+ ((STATE) == DMA_MemoryInc_Disable))\r
+\r
+/* DMA peripheral data size --------------------------------------------------*/\r
+#define DMA_PeripheralDataSize_Byte ((u32)0x00000000)\r
+#define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100)\r
+#define DMA_PeripheralDataSize_Word ((u32)0x00000200)\r
+\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_Word))\r
+\r
+/* DMA memory data size ------------------------------------------------------*/\r
+#define DMA_MemoryDataSize_Byte ((u32)0x00000000)\r
+#define DMA_MemoryDataSize_HalfWord ((u32)0x00000400)\r
+#define DMA_MemoryDataSize_Word ((u32)0x00000800)\r
+\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \\r
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_MemoryDataSize_Word))\r
+\r
+/* DMA circular/normal mode --------------------------------------------------*/\r
+#define DMA_Mode_Circular ((u32)0x00000020)\r
+#define DMA_Mode_Normal ((u32)0x00000000)\r
+\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))\r
+\r
+/* DMA priority level --------------------------------------------------------*/\r
+#define DMA_Priority_VeryHigh ((u32)0x00003000)\r
+#define DMA_Priority_High ((u32)0x00002000)\r
+#define DMA_Priority_Medium ((u32)0x00001000)\r
+#define DMA_Priority_Low ((u32)0x00000000)\r
+\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \\r
+ ((PRIORITY) == DMA_Priority_High) || \\r
+ ((PRIORITY) == DMA_Priority_Medium) || \\r
+ ((PRIORITY) == DMA_Priority_Low))\r
+\r
+/* DMA memory to memory ------------------------------------------------------*/\r
+#define DMA_M2M_Enable ((u32)0x00004000)\r
+#define DMA_M2M_Disable ((u32)0x00000000)\r
+\r
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))\r
+\r
+/* DMA interrupts definition -------------------------------------------------*/\r
+#define DMA_IT_TC ((u32)0x00000002)\r
+#define DMA_IT_HT ((u32)0x00000004)\r
+#define DMA_IT_TE ((u32)0x00000008)\r
+\r
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))\r
+\r
+/* For DMA1 */\r
+#define DMA1_IT_GL1 ((u32)0x00000001)\r
+#define DMA1_IT_TC1 ((u32)0x00000002)\r
+#define DMA1_IT_HT1 ((u32)0x00000004)\r
+#define DMA1_IT_TE1 ((u32)0x00000008)\r
+#define DMA1_IT_GL2 ((u32)0x00000010)\r
+#define DMA1_IT_TC2 ((u32)0x00000020)\r
+#define DMA1_IT_HT2 ((u32)0x00000040)\r
+#define DMA1_IT_TE2 ((u32)0x00000080)\r
+#define DMA1_IT_GL3 ((u32)0x00000100)\r
+#define DMA1_IT_TC3 ((u32)0x00000200)\r
+#define DMA1_IT_HT3 ((u32)0x00000400)\r
+#define DMA1_IT_TE3 ((u32)0x00000800)\r
+#define DMA1_IT_GL4 ((u32)0x00001000)\r
+#define DMA1_IT_TC4 ((u32)0x00002000)\r
+#define DMA1_IT_HT4 ((u32)0x00004000)\r
+#define DMA1_IT_TE4 ((u32)0x00008000)\r
+#define DMA1_IT_GL5 ((u32)0x00010000)\r
+#define DMA1_IT_TC5 ((u32)0x00020000)\r
+#define DMA1_IT_HT5 ((u32)0x00040000)\r
+#define DMA1_IT_TE5 ((u32)0x00080000)\r
+#define DMA1_IT_GL6 ((u32)0x00100000)\r
+#define DMA1_IT_TC6 ((u32)0x00200000)\r
+#define DMA1_IT_HT6 ((u32)0x00400000)\r
+#define DMA1_IT_TE6 ((u32)0x00800000)\r
+#define DMA1_IT_GL7 ((u32)0x01000000)\r
+#define DMA1_IT_TC7 ((u32)0x02000000)\r
+#define DMA1_IT_HT7 ((u32)0x04000000)\r
+#define DMA1_IT_TE7 ((u32)0x08000000)\r
+/* For DMA2 */\r
+#define DMA2_IT_GL1 ((u32)0x10000001)\r
+#define DMA2_IT_TC1 ((u32)0x10000002)\r
+#define DMA2_IT_HT1 ((u32)0x10000004)\r
+#define DMA2_IT_TE1 ((u32)0x10000008)\r
+#define DMA2_IT_GL2 ((u32)0x10000010)\r
+#define DMA2_IT_TC2 ((u32)0x10000020)\r
+#define DMA2_IT_HT2 ((u32)0x10000040)\r
+#define DMA2_IT_TE2 ((u32)0x10000080)\r
+#define DMA2_IT_GL3 ((u32)0x10000100)\r
+#define DMA2_IT_TC3 ((u32)0x10000200)\r
+#define DMA2_IT_HT3 ((u32)0x10000400)\r
+#define DMA2_IT_TE3 ((u32)0x10000800)\r
+#define DMA2_IT_GL4 ((u32)0x10001000)\r
+#define DMA2_IT_TC4 ((u32)0x10002000)\r
+#define DMA2_IT_HT4 ((u32)0x10004000)\r
+#define DMA2_IT_TE4 ((u32)0x10008000)\r
+#define DMA2_IT_GL5 ((u32)0x10010000)\r
+#define DMA2_IT_TC5 ((u32)0x10020000)\r
+#define DMA2_IT_HT5 ((u32)0x10040000)\r
+#define DMA2_IT_TE5 ((u32)0x10080000)\r
+\r
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))\r
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \\r
+ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \\r
+ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \\r
+ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \\r
+ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \\r
+ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \\r
+ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \\r
+ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \\r
+ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \\r
+ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \\r
+ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \\r
+ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \\r
+ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \\r
+ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \\r
+ ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \\r
+ ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \\r
+ ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \\r
+ ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \\r
+ ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \\r
+ ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \\r
+ ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \\r
+ ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \\r
+ ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \\r
+ ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))\r
+\r
+/* DMA flags definition ------------------------------------------------------*/\r
+/* For DMA1 */\r
+#define DMA1_FLAG_GL1 ((u32)0x00000001)\r
+#define DMA1_FLAG_TC1 ((u32)0x00000002)\r
+#define DMA1_FLAG_HT1 ((u32)0x00000004)\r
+#define DMA1_FLAG_TE1 ((u32)0x00000008)\r
+#define DMA1_FLAG_GL2 ((u32)0x00000010)\r
+#define DMA1_FLAG_TC2 ((u32)0x00000020)\r
+#define DMA1_FLAG_HT2 ((u32)0x00000040)\r
+#define DMA1_FLAG_TE2 ((u32)0x00000080)\r
+#define DMA1_FLAG_GL3 ((u32)0x00000100)\r
+#define DMA1_FLAG_TC3 ((u32)0x00000200)\r
+#define DMA1_FLAG_HT3 ((u32)0x00000400)\r
+#define DMA1_FLAG_TE3 ((u32)0x00000800)\r
+#define DMA1_FLAG_GL4 ((u32)0x00001000)\r
+#define DMA1_FLAG_TC4 ((u32)0x00002000)\r
+#define DMA1_FLAG_HT4 ((u32)0x00004000)\r
+#define DMA1_FLAG_TE4 ((u32)0x00008000)\r
+#define DMA1_FLAG_GL5 ((u32)0x00010000)\r
+#define DMA1_FLAG_TC5 ((u32)0x00020000)\r
+#define DMA1_FLAG_HT5 ((u32)0x00040000)\r
+#define DMA1_FLAG_TE5 ((u32)0x00080000)\r
+#define DMA1_FLAG_GL6 ((u32)0x00100000)\r
+#define DMA1_FLAG_TC6 ((u32)0x00200000)\r
+#define DMA1_FLAG_HT6 ((u32)0x00400000)\r
+#define DMA1_FLAG_TE6 ((u32)0x00800000)\r
+#define DMA1_FLAG_GL7 ((u32)0x01000000)\r
+#define DMA1_FLAG_TC7 ((u32)0x02000000)\r
+#define DMA1_FLAG_HT7 ((u32)0x04000000)\r
+#define DMA1_FLAG_TE7 ((u32)0x08000000)\r
+/* For DMA2 */\r
+#define DMA2_FLAG_GL1 ((u32)0x10000001)\r
+#define DMA2_FLAG_TC1 ((u32)0x10000002)\r
+#define DMA2_FLAG_HT1 ((u32)0x10000004)\r
+#define DMA2_FLAG_TE1 ((u32)0x10000008)\r
+#define DMA2_FLAG_GL2 ((u32)0x10000010)\r
+#define DMA2_FLAG_TC2 ((u32)0x10000020)\r
+#define DMA2_FLAG_HT2 ((u32)0x10000040)\r
+#define DMA2_FLAG_TE2 ((u32)0x10000080)\r
+#define DMA2_FLAG_GL3 ((u32)0x10000100)\r
+#define DMA2_FLAG_TC3 ((u32)0x10000200)\r
+#define DMA2_FLAG_HT3 ((u32)0x10000400)\r
+#define DMA2_FLAG_TE3 ((u32)0x10000800)\r
+#define DMA2_FLAG_GL4 ((u32)0x10001000)\r
+#define DMA2_FLAG_TC4 ((u32)0x10002000)\r
+#define DMA2_FLAG_HT4 ((u32)0x10004000)\r
+#define DMA2_FLAG_TE4 ((u32)0x10008000)\r
+#define DMA2_FLAG_GL5 ((u32)0x10010000)\r
+#define DMA2_FLAG_TC5 ((u32)0x10020000)\r
+#define DMA2_FLAG_HT5 ((u32)0x10040000)\r
+#define DMA2_FLAG_TE5 ((u32)0x10080000)\r
+\r
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))\r
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \\r
+ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \\r
+ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \\r
+ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \\r
+ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \\r
+ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \\r
+ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \\r
+ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \\r
+ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \\r
+ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \\r
+ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \\r
+ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \\r
+ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \\r
+ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \\r
+ ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \\r
+ ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \\r
+ ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \\r
+ ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \\r
+ ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \\r
+ ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \\r
+ ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \\r
+ ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \\r
+ ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \\r
+ ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))\r
+\r
+/* DMA Buffer Size -----------------------------------------------------------*/\r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);\r
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, u32 DMA_IT, FunctionalState NewState);\r
+u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);\r
+FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG);\r
+void DMA_ClearFlag(u32 DMA_FLAG);\r
+ITStatus DMA_GetITStatus(u32 DMA_IT);\r
+void DMA_ClearITPendingBit(u32 DMA_IT);\r
+\r
+#endif /*__STM32F10x_DMA_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_exti.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* EXTI firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_EXTI_H\r
+#define __STM32F10x_EXTI_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* EXTI mode enumeration -----------------------------------------------------*/\r
+typedef enum\r
+{\r
+ EXTI_Mode_Interrupt = 0x00,\r
+ EXTI_Mode_Event = 0x04\r
+}EXTIMode_TypeDef;\r
+\r
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))\r
+ \r
+/* EXTI Trigger enumeration --------------------------------------------------*/\r
+typedef enum\r
+{\r
+ EXTI_Trigger_Rising = 0x08,\r
+ EXTI_Trigger_Falling = 0x0C, \r
+ EXTI_Trigger_Rising_Falling = 0x10\r
+}EXTITrigger_TypeDef;\r
+\r
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \\r
+ ((TRIGGER) == EXTI_Trigger_Falling) || \\r
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))\r
+\r
+/* EXTI Init Structure definition --------------------------------------------*/\r
+typedef struct\r
+{\r
+ u32 EXTI_Line;\r
+ EXTIMode_TypeDef EXTI_Mode;\r
+ EXTITrigger_TypeDef EXTI_Trigger;\r
+ FunctionalState EXTI_LineCmd;\r
+}EXTI_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* EXTI Lines ----------------------------------------------------------------*/\r
+#define EXTI_Line0 ((u32)0x00001) /* External interrupt line 0 */\r
+#define EXTI_Line1 ((u32)0x00002) /* External interrupt line 1 */\r
+#define EXTI_Line2 ((u32)0x00004) /* External interrupt line 2 */\r
+#define EXTI_Line3 ((u32)0x00008) /* External interrupt line 3 */\r
+#define EXTI_Line4 ((u32)0x00010) /* External interrupt line 4 */\r
+#define EXTI_Line5 ((u32)0x00020) /* External interrupt line 5 */\r
+#define EXTI_Line6 ((u32)0x00040) /* External interrupt line 6 */\r
+#define EXTI_Line7 ((u32)0x00080) /* External interrupt line 7 */\r
+#define EXTI_Line8 ((u32)0x00100) /* External interrupt line 8 */\r
+#define EXTI_Line9 ((u32)0x00200) /* External interrupt line 9 */\r
+#define EXTI_Line10 ((u32)0x00400) /* External interrupt line 10 */\r
+#define EXTI_Line11 ((u32)0x00800) /* External interrupt line 11 */\r
+#define EXTI_Line12 ((u32)0x01000) /* External interrupt line 12 */\r
+#define EXTI_Line13 ((u32)0x02000) /* External interrupt line 13 */\r
+#define EXTI_Line14 ((u32)0x04000) /* External interrupt line 14 */\r
+#define EXTI_Line15 ((u32)0x08000) /* External interrupt line 15 */\r
+#define EXTI_Line16 ((u32)0x10000) /* External interrupt line 16\r
+ Connected to the PVD Output */\r
+#define EXTI_Line17 ((u32)0x20000) /* External interrupt line 17 \r
+ Connected to the RTC Alarm event */\r
+#define EXTI_Line18 ((u32)0x40000) /* External interrupt line 18 \r
+ Connected to the USB Wakeup from \r
+ suspend event */\r
+\r
+#define IS_EXTI_LINE(LINE) ((((LINE) & (u32)0xFFF80000) == 0x00) && ((LINE) != (u16)0x00))\r
+\r
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \\r
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \\r
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \\r
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \\r
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \\r
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \\r
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \\r
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \\r
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \\r
+ ((LINE) == EXTI_Line18))\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void EXTI_DeInit(void);\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_GenerateSWInterrupt(u32 EXTI_Line);\r
+FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line);\r
+void EXTI_ClearFlag(u32 EXTI_Line);\r
+ITStatus EXTI_GetITStatus(u32 EXTI_Line);\r
+void EXTI_ClearITPendingBit(u32 EXTI_Line);\r
+\r
+#endif /* __STM32F10x_EXTI_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_flash.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* FLASH firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_FLASH_H\r
+#define __STM32F10x_FLASH_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+#ifdef _FLASH_PROG\r
+/* FLASH Status */\r
+typedef enum\r
+{ \r
+ FLASH_BUSY = 1,\r
+ FLASH_ERROR_PG,\r
+ FLASH_ERROR_WRP,\r
+ FLASH_COMPLETE,\r
+ FLASH_TIMEOUT\r
+}FLASH_Status;\r
+#endif\r
+\r
+/* Flash Latency -------------------------------------------------------------*/\r
+#define FLASH_Latency_0 ((u32)0x00000000) /* FLASH Zero Latency cycle */\r
+#define FLASH_Latency_1 ((u32)0x00000001) /* FLASH One Latency cycle */\r
+#define FLASH_Latency_2 ((u32)0x00000002) /* FLASH Two Latency cycles */\r
+\r
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \\r
+ ((LATENCY) == FLASH_Latency_1) || \\r
+ ((LATENCY) == FLASH_Latency_2))\r
+\r
+/* Half Cycle Enable/Disable -------------------------------------------------*/\r
+#define FLASH_HalfCycleAccess_Enable ((u32)0x00000008) /* FLASH Half Cycle Enable */\r
+#define FLASH_HalfCycleAccess_Disable ((u32)0x00000000) /* FLASH Half Cycle Disable */\r
+\r
+#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \\r
+ ((STATE) == FLASH_HalfCycleAccess_Disable)) \r
+\r
+\r
+/* Prefetch Buffer Enable/Disable --------------------------------------------*/\r
+#define FLASH_PrefetchBuffer_Enable ((u32)0x00000010) /* FLASH Prefetch Buffer Enable */\r
+#define FLASH_PrefetchBuffer_Disable ((u32)0x00000000) /* FLASH Prefetch Buffer Disable */\r
+\r
+#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \\r
+ ((STATE) == FLASH_PrefetchBuffer_Disable)) \r
+\r
+#ifdef _FLASH_PROG\r
+/* Option Bytes Write Protection ---------------------------------------------*/\r
+/* Values to be used with STM32F10Xxx Medium-density devices: FLASH memory density\r
+ ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */\r
+#define FLASH_WRProt_Pages0to3 ((u32)0x00000001) /* Write protection of page 0 to 3 */\r
+#define FLASH_WRProt_Pages4to7 ((u32)0x00000002) /* Write protection of page 4 to 7 */\r
+#define FLASH_WRProt_Pages8to11 ((u32)0x00000004) /* Write protection of page 8 to 11 */\r
+#define FLASH_WRProt_Pages12to15 ((u32)0x00000008) /* Write protection of page 12 to 15 */\r
+#define FLASH_WRProt_Pages16to19 ((u32)0x00000010) /* Write protection of page 16 to 19 */\r
+#define FLASH_WRProt_Pages20to23 ((u32)0x00000020) /* Write protection of page 20 to 23 */\r
+#define FLASH_WRProt_Pages24to27 ((u32)0x00000040) /* Write protection of page 24 to 27 */\r
+#define FLASH_WRProt_Pages28to31 ((u32)0x00000080) /* Write protection of page 28 to 31 */\r
+#define FLASH_WRProt_Pages32to35 ((u32)0x00000100) /* Write protection of page 32 to 35 */\r
+#define FLASH_WRProt_Pages36to39 ((u32)0x00000200) /* Write protection of page 36 to 39 */\r
+#define FLASH_WRProt_Pages40to43 ((u32)0x00000400) /* Write protection of page 40 to 43 */\r
+#define FLASH_WRProt_Pages44to47 ((u32)0x00000800) /* Write protection of page 44 to 47 */\r
+#define FLASH_WRProt_Pages48to51 ((u32)0x00001000) /* Write protection of page 48 to 51 */\r
+#define FLASH_WRProt_Pages52to55 ((u32)0x00002000) /* Write protection of page 52 to 55 */\r
+#define FLASH_WRProt_Pages56to59 ((u32)0x00004000) /* Write protection of page 56 to 59 */\r
+#define FLASH_WRProt_Pages60to63 ((u32)0x00008000) /* Write protection of page 60 to 63 */\r
+#define FLASH_WRProt_Pages64to67 ((u32)0x00010000) /* Write protection of page 64 to 67 */\r
+#define FLASH_WRProt_Pages68to71 ((u32)0x00020000) /* Write protection of page 68 to 71 */\r
+#define FLASH_WRProt_Pages72to75 ((u32)0x00040000) /* Write protection of page 72 to 75 */\r
+#define FLASH_WRProt_Pages76to79 ((u32)0x00080000) /* Write protection of page 76 to 79 */\r
+#define FLASH_WRProt_Pages80to83 ((u32)0x00100000) /* Write protection of page 80 to 83 */\r
+#define FLASH_WRProt_Pages84to87 ((u32)0x00200000) /* Write protection of page 84 to 87 */\r
+#define FLASH_WRProt_Pages88to91 ((u32)0x00400000) /* Write protection of page 88 to 91 */\r
+#define FLASH_WRProt_Pages92to95 ((u32)0x00800000) /* Write protection of page 92 to 95 */\r
+#define FLASH_WRProt_Pages96to99 ((u32)0x01000000) /* Write protection of page 96 to 99 */\r
+#define FLASH_WRProt_Pages100to103 ((u32)0x02000000) /* Write protection of page 100 to 103 */\r
+#define FLASH_WRProt_Pages104to107 ((u32)0x04000000) /* Write protection of page 104 to 107 */\r
+#define FLASH_WRProt_Pages108to111 ((u32)0x08000000) /* Write protection of page 108 to 111 */\r
+#define FLASH_WRProt_Pages112to115 ((u32)0x10000000) /* Write protection of page 112 to 115 */\r
+#define FLASH_WRProt_Pages116to119 ((u32)0x20000000) /* Write protection of page 115 to 119 */\r
+#define FLASH_WRProt_Pages120to123 ((u32)0x40000000) /* Write protection of page 120 to 123 */\r
+#define FLASH_WRProt_Pages124to127 ((u32)0x80000000) /* Write protection of page 124 to 127 */\r
+/* Values to be used with STM32F10Xxx High-density devices: FLASH memory density\r
+ ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */\r
+#define FLASH_WRProt_Pages0to1 ((u32)0x00000001) /* Write protection of page 0 to 1 */\r
+#define FLASH_WRProt_Pages2to3 ((u32)0x00000002) /* Write protection of page 2 to 3 */\r
+#define FLASH_WRProt_Pages4to5 ((u32)0x00000004) /* Write protection of page 4 to 5 */\r
+#define FLASH_WRProt_Pages6to7 ((u32)0x00000008) /* Write protection of page 6 to 7 */\r
+#define FLASH_WRProt_Pages8to9 ((u32)0x00000010) /* Write protection of page 8 to 9 */\r
+#define FLASH_WRProt_Pages10to11 ((u32)0x00000020) /* Write protection of page 10 to 11 */\r
+#define FLASH_WRProt_Pages12to13 ((u32)0x00000040) /* Write protection of page 12 to 13 */\r
+#define FLASH_WRProt_Pages14to15 ((u32)0x00000080) /* Write protection of page 14 to 15 */\r
+#define FLASH_WRProt_Pages16to17 ((u32)0x00000100) /* Write protection of page 16 to 17 */\r
+#define FLASH_WRProt_Pages18to19 ((u32)0x00000200) /* Write protection of page 18 to 19 */\r
+#define FLASH_WRProt_Pages20to21 ((u32)0x00000400) /* Write protection of page 20 to 21 */\r
+#define FLASH_WRProt_Pages22to23 ((u32)0x00000800) /* Write protection of page 22 to 23 */\r
+#define FLASH_WRProt_Pages24to25 ((u32)0x00001000) /* Write protection of page 24 to 25 */\r
+#define FLASH_WRProt_Pages26to27 ((u32)0x00002000) /* Write protection of page 26 to 27 */\r
+#define FLASH_WRProt_Pages28to29 ((u32)0x00004000) /* Write protection of page 28 to 29 */\r
+#define FLASH_WRProt_Pages30to31 ((u32)0x00008000) /* Write protection of page 30 to 31 */\r
+#define FLASH_WRProt_Pages32to33 ((u32)0x00010000) /* Write protection of page 32 to 33 */\r
+#define FLASH_WRProt_Pages34to35 ((u32)0x00020000) /* Write protection of page 34 to 35 */\r
+#define FLASH_WRProt_Pages36to37 ((u32)0x00040000) /* Write protection of page 36 to 37 */\r
+#define FLASH_WRProt_Pages38to39 ((u32)0x00080000) /* Write protection of page 38 to 39 */\r
+#define FLASH_WRProt_Pages40to41 ((u32)0x00100000) /* Write protection of page 40 to 41 */\r
+#define FLASH_WRProt_Pages42to43 ((u32)0x00200000) /* Write protection of page 42 to 43 */\r
+#define FLASH_WRProt_Pages44to45 ((u32)0x00400000) /* Write protection of page 44 to 45 */\r
+#define FLASH_WRProt_Pages46to47 ((u32)0x00800000) /* Write protection of page 46 to 47 */\r
+#define FLASH_WRProt_Pages48to49 ((u32)0x01000000) /* Write protection of page 48 to 49 */\r
+#define FLASH_WRProt_Pages50to51 ((u32)0x02000000) /* Write protection of page 50 to 51 */\r
+#define FLASH_WRProt_Pages52to53 ((u32)0x04000000) /* Write protection of page 52 to 53 */\r
+#define FLASH_WRProt_Pages54to55 ((u32)0x08000000) /* Write protection of page 54 to 55 */\r
+#define FLASH_WRProt_Pages56to57 ((u32)0x10000000) /* Write protection of page 56 to 57 */\r
+#define FLASH_WRProt_Pages58to59 ((u32)0x20000000) /* Write protection of page 58 to 59 */\r
+#define FLASH_WRProt_Pages60to61 ((u32)0x40000000) /* Write protection of page 60 to 61 */\r
+#define FLASH_WRProt_Pages62to255 ((u32)0x80000000) /* Write protection of page 62 to 255 */\r
+#define FLASH_WRProt_AllPages ((u32)0xFFFFFFFF) /* Write protection of all Pages */\r
+\r
+#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))\r
+\r
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF))\r
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))\r
+\r
+/* Option Bytes IWatchdog ----------------------------------------------------*/\r
+#define OB_IWDG_SW ((u16)0x0001) /* Software IWDG selected */\r
+#define OB_IWDG_HW ((u16)0x0000) /* Hardware IWDG selected */\r
+\r
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
+\r
+/* Option Bytes nRST_STOP ----------------------------------------------------*/\r
+#define OB_STOP_NoRST ((u16)0x0002) /* No reset generated when entering in STOP */\r
+#define OB_STOP_RST ((u16)0x0000) /* Reset generated when entering in STOP */\r
+\r
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))\r
+\r
+/* Option Bytes nRST_STDBY ---------------------------------------------------*/\r
+#define OB_STDBY_NoRST ((u16)0x0004) /* No reset generated when entering in STANDBY */\r
+#define OB_STDBY_RST ((u16)0x0000) /* Reset generated when entering in STANDBY */\r
+\r
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))\r
+\r
+/* FLASH Interrupts ----------------------------------------------------------*/\r
+#define FLASH_IT_ERROR ((u32)0x00000400) /* FPEC error interrupt source */\r
+#define FLASH_IT_EOP ((u32)0x00001000) /* End of FLASH Operation Interrupt source */\r
+\r
+#define IS_FLASH_IT(IT) ((((IT) & (u32)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))\r
+\r
+/* FLASH Flags ---------------------------------------------------------------*/\r
+#define FLASH_FLAG_BSY ((u32)0x00000001) /* FLASH Busy flag */\r
+#define FLASH_FLAG_EOP ((u32)0x00000020) /* FLASH End of Operation flag */\r
+#define FLASH_FLAG_PGERR ((u32)0x00000004) /* FLASH Program error flag */\r
+#define FLASH_FLAG_WRPRTERR ((u32)0x00000010) /* FLASH Write protected error flag */\r
+#define FLASH_FLAG_OPTERR ((u32)0x00000001) /* FLASH Option Byte error flag */\r
+ \r
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))\r
+\r
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \\r
+ ((FLAG) == FLASH_FLAG_OPTERR))\r
+#endif\r
+ \r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void FLASH_SetLatency(u32 FLASH_Latency);\r
+void FLASH_HalfCycleAccessCmd(u32 FLASH_HalfCycleAccess);\r
+void FLASH_PrefetchBufferCmd(u32 FLASH_PrefetchBuffer);\r
+\r
+#ifdef _FLASH_PROG\r
+void FLASH_Unlock(void);\r
+void FLASH_Lock(void);\r
+FLASH_Status FLASH_ErasePage(u32 Page_Address);\r
+FLASH_Status FLASH_EraseAllPages(void);\r
+FLASH_Status FLASH_EraseOptionBytes(void);\r
+FLASH_Status FLASH_ProgramWord(u32 Address, u32 Data);\r
+FLASH_Status FLASH_ProgramHalfWord(u32 Address, u16 Data);\r
+FLASH_Status FLASH_ProgramOptionByteData(u32 Address, u8 Data);\r
+FLASH_Status FLASH_EnableWriteProtection(u32 FLASH_Pages);\r
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);\r
+FLASH_Status FLASH_UserOptionByteConfig(u16 OB_IWDG, u16 OB_STOP, u16 OB_STDBY);\r
+u32 FLASH_GetUserOptionByte(void);\r
+u32 FLASH_GetWriteProtectionOptionByte(void);\r
+FlagStatus FLASH_GetReadOutProtectionStatus(void);\r
+FlagStatus FLASH_GetPrefetchBufferStatus(void);\r
+void FLASH_ITConfig(u16 FLASH_IT, FunctionalState NewState);\r
+FlagStatus FLASH_GetFlagStatus(u16 FLASH_FLAG);\r
+void FLASH_ClearFlag(u16 FLASH_FLAG);\r
+FLASH_Status FLASH_GetStatus(void);\r
+FLASH_Status FLASH_WaitForLastOperation(u32 Timeout);\r
+#endif\r
+\r
+#endif /* __STM32F10x_FLASH_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_fsmc.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* FSMC firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_FSMC_H\r
+#define __STM32F10x_FSMC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Timing parameters For NOR/SRAM Banks */\r
+typedef struct\r
+{\r
+ u32 FSMC_AddressSetupTime;\r
+ u32 FSMC_AddressHoldTime;\r
+ u32 FSMC_DataSetupTime;\r
+ u32 FSMC_BusTurnAroundDuration;\r
+ u32 FSMC_CLKDivision;\r
+ u32 FSMC_DataLatency;\r
+ u32 FSMC_AccessMode;\r
+}FSMC_NORSRAMTimingInitTypeDef;\r
+\r
+/* FSMC NOR/SRAM Init structure definition */\r
+typedef struct\r
+{\r
+ u32 FSMC_Bank;\r
+ u32 FSMC_DataAddressMux;\r
+ u32 FSMC_MemoryType;\r
+ u32 FSMC_MemoryDataWidth;\r
+ u32 FSMC_BurstAccessMode;\r
+ u32 FSMC_WaitSignalPolarity;\r
+ u32 FSMC_WrapMode;\r
+ u32 FSMC_WaitSignalActive;\r
+ u32 FSMC_WriteOperation;\r
+ u32 FSMC_WaitSignal;\r
+ u32 FSMC_ExtendedMode;\r
+ u32 FSMC_AsyncWait;\r
+ u32 FSMC_WriteBurst;\r
+ /* Timing Parameters for write and read access if the ExtendedMode is not used*/\r
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;\r
+ /* Timing Parameters for write access if the ExtendedMode is used*/\r
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;\r
+}FSMC_NORSRAMInitTypeDef;\r
+\r
+/* Timing parameters For FSMC NAND and PCCARD Banks */\r
+typedef struct\r
+{\r
+ u32 FSMC_SetupTime;\r
+ u32 FSMC_WaitSetupTime;\r
+ u32 FSMC_HoldSetupTime;\r
+ u32 FSMC_HiZSetupTime;\r
+}FSMC_NAND_PCCARDTimingInitTypeDef;\r
+\r
+/* FSMC NAND Init structure definition */\r
+typedef struct\r
+{\r
+ u32 FSMC_Bank;\r
+ u32 FSMC_Waitfeature;\r
+ u32 FSMC_MemoryDataWidth;\r
+ u32 FSMC_ECC;\r
+ u32 FSMC_ECCPageSize;\r
+ u32 FSMC_AddressLowMapping;\r
+ u32 FSMC_TCLRSetupTime;\r
+ u32 FSMC_TARSetupTime;\r
+ /* FSMC Common Space Timing */\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;\r
+ /* FSMC Attribute Space Timing */\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;\r
+}FSMC_NANDInitTypeDef;\r
+\r
+/* FSMC PCCARD Init structure definition */\r
+typedef struct\r
+{\r
+ u32 FSMC_Waitfeature;\r
+ u32 FSMC_AddressLowMapping;\r
+ u32 FSMC_TCLRSetupTime;\r
+ u32 FSMC_TARSetupTime;\r
+ /* FSMC Common Space Timing */\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;\r
+ /* FSMC Attribute Space Timing */\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;\r
+ /* FSMC IO Space Timing */\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct;\r
+}FSMC_PCCARDInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/*-------------------------------FSMC Banks definitions ----------------------*/\r
+#define FSMC_Bank1_NORSRAM1 ((u32)0x00000000)\r
+#define FSMC_Bank1_NORSRAM2 ((u32)0x00000002)\r
+#define FSMC_Bank1_NORSRAM3 ((u32)0x00000004)\r
+#define FSMC_Bank1_NORSRAM4 ((u32)0x00000006)\r
+#define FSMC_Bank2_NAND ((u32)0x00000010)\r
+#define FSMC_Bank3_NAND ((u32)0x00000100)\r
+#define FSMC_Bank4_PCCARD ((u32)0x00001000)\r
+\r
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM2) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM3) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM4)) \r
+\r
+\r
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
+ ((BANK) == FSMC_Bank3_NAND))\r
+\r
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
+ ((BANK) == FSMC_Bank3_NAND) || \\r
+ ((BANK) == FSMC_Bank4_PCCARD))\r
+ \r
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
+ ((BANK) == FSMC_Bank3_NAND) || \\r
+ ((BANK) == FSMC_Bank4_PCCARD)) \r
+\r
+\r
+/*------------------------------- NOR/SRAM Banks -----------------------------*/\r
+/* FSMC Data/Address Bus Multiplexing ----------------------------------------*/\r
+#define FSMC_DataAddressMux_Disable ((u32)0x00000000)\r
+#define FSMC_DataAddressMux_Enable ((u32)0x00000002)\r
+\r
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \\r
+ ((MUX) == FSMC_DataAddressMux_Enable)) \r
+\r
+/* FSMC Memory Type ----------------------------------------------------------*/\r
+#define FSMC_MemoryType_SRAM ((u32)0x00000000)\r
+#define FSMC_MemoryType_CRAM ((u32)0x00000004)\r
+#define FSMC_MemoryType_NOR ((u32)0x00000008)\r
+#define FSMC_MemoryType_COSMORAM ((u32)0x0000000C)\r
+\r
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \\r
+ ((MEMORY) == FSMC_MemoryType_CRAM)|| \\r
+ ((MEMORY) == FSMC_MemoryType_NOR)|| \\r
+ ((MEMORY) == FSMC_MemoryType_COSMORAM))\r
+ \r
+/* FSMC Data Width ----------------------------------------------------------*/\r
+#define FSMC_MemoryDataWidth_8b ((u32)0x00000000)\r
+#define FSMC_MemoryDataWidth_16b ((u32)0x00000010)\r
+\r
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \\r
+ ((WIDTH) == FSMC_MemoryDataWidth_16b))\r
+ \r
+ \r
+/* FSMC Burst Access Mode ----------------------------------------------------*/\r
+#define FSMC_BurstAccessMode_Disable ((u32)0x00000000) \r
+#define FSMC_BurstAccessMode_Enable ((u32)0x00000100)\r
+\r
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \\r
+ ((STATE) == FSMC_BurstAccessMode_Enable))\r
+\r
+/* FSMC Wait Signal Polarity -------------------------------------------------*/ \r
+#define FSMC_WaitSignalPolarity_Low ((u32)0x00000000)\r
+#define FSMC_WaitSignalPolarity_High ((u32)0x00000200)\r
+\r
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \\r
+ ((POLARITY) == FSMC_WaitSignalPolarity_High)) \r
+ \r
+/* FSMC Wrap Mode ------------------------------------------------------------*/ \r
+#define FSMC_WrapMode_Disable ((u32)0x00000000)\r
+#define FSMC_WrapMode_Enable ((u32)0x00000400) \r
+\r
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \\r
+ ((MODE) == FSMC_WrapMode_Enable))\r
+ \r
+/* FSMC Wait Timing ----------------------------------------------------------*/ \r
+#define FSMC_WaitSignalActive_BeforeWaitState ((u32)0x00000000)\r
+#define FSMC_WaitSignalActive_DuringWaitState ((u32)0x00000800) \r
+\r
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \\r
+ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))\r
+ \r
+/* FSMC Write Operation ------------------------------------------------------*/\r
+#define FSMC_WriteOperation_Disable ((u32)0x00000000)\r
+#define FSMC_WriteOperation_Enable ((u32)0x00001000)\r
+\r
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \\r
+ ((OPERATION) == FSMC_WriteOperation_Enable))\r
+ \r
+/* FSMC Wait Signal ----------------------------------------------------------*/\r
+#define FSMC_WaitSignal_Disable ((u32)0x00000000)\r
+#define FSMC_WaitSignal_Enable ((u32)0x00002000) \r
+\r
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \\r
+ ((SIGNAL) == FSMC_WaitSignal_Enable))\r
+\r
+/* FSMC Extended Mode --------------------------------------------------------*/\r
+#define FSMC_ExtendedMode_Disable ((u32)0x00000000)\r
+#define FSMC_ExtendedMode_Enable ((u32)0x00004000) \r
+\r
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \\r
+ ((MODE) == FSMC_ExtendedMode_Enable)) \r
+ \r
+/* FSMC Asynchronous Wait ----------------------------------------------------*/\r
+#define FSMC_AsyncWait_Disable ((u32)0x00000000)\r
+#define FSMC_AsyncWait_Enable ((u32)0x00008000)\r
+\r
+#define IS_FSMC_ASYNC_WAIT(WAIT) (((WAIT) == FSMC_AsyncWait_Disable) || \\r
+ ((WAIT) == FSMC_AsyncWait_Enable))\r
+ \r
+/* FSMC Write Burst ----------------------------------------------------------*/ \r
+#define FSMC_WriteBurst_Disable ((u32)0x00000000)\r
+#define FSMC_WriteBurst_Enable ((u32)0x00080000) \r
+\r
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \\r
+ ((BURST) == FSMC_WriteBurst_Enable))\r
+\r
+/* FSMC Address Setup Time ---------------------------------------------------*/\r
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)\r
+\r
+/* FSMC Address Hold Time ----------------------------------------------------*/\r
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)\r
+\r
+/* FSMC Data Setup Time ------------------------------------------------------*/\r
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))\r
+\r
+/* FSMC Bus Turn around Duration ---------------------------------------------*/\r
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)\r
+\r
+/* FSMC CLK Division ---------------------------------------------------------*/\r
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)\r
+\r
+/* FSMC Data Latency ---------------------------------------------------------*/\r
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)\r
+\r
+/* FSMC Access Mode ----------------------------------------------------------*/\r
+#define FSMC_AccessMode_A ((u32)0x00000000)\r
+#define FSMC_AccessMode_B ((u32)0x10000000) \r
+#define FSMC_AccessMode_C ((u32)0x20000000)\r
+#define FSMC_AccessMode_D ((u32)0x30000000)\r
+\r
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \\r
+ ((MODE) == FSMC_AccessMode_B) || \\r
+ ((MODE) == FSMC_AccessMode_C) || \\r
+ ((MODE) == FSMC_AccessMode_D)) \r
+ \r
+/*----------------------------- NAND and PCCARD Banks ------------------------*/\r
+/* FSMC Wait feature ---------------------------------------------------------*/\r
+#define FSMC_Waitfeature_Disable ((u32)0x00000000)\r
+#define FSMC_Waitfeature_Enable ((u32)0x00000002)\r
+\r
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \\r
+ ((FEATURE) == FSMC_Waitfeature_Enable))\r
+ \r
+/* FSMC Memory Data Width ----------------------------------------------------*/\r
+#define FSMC_MemoryDataWidth_8b ((u32)0x00000000)\r
+#define FSMC_MemoryDataWidth_16b ((u32)0x00000010)\r
+\r
+#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \\r
+ ((WIDTH) == FSMC_MemoryDataWidth_16b))\r
+ \r
+/* FSMC ECC ------------------------------------------------------------------*/\r
+#define FSMC_ECC_Disable ((u32)0x00000000)\r
+#define FSMC_ECC_Enable ((u32)0x00000040)\r
+\r
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \\r
+ ((STATE) == FSMC_ECC_Enable))\r
+ \r
+/* FSMC ECC Page Size --------------------------------------------------------*/\r
+#define FSMC_ECCPageSize_256Bytes ((u32)0x00000000)\r
+#define FSMC_ECCPageSize_512Bytes ((u32)0x00020000)\r
+#define FSMC_ECCPageSize_1024Bytes ((u32)0x00040000)\r
+#define FSMC_ECCPageSize_2048Bytes ((u32)0x00060000)\r
+#define FSMC_ECCPageSize_4096Bytes ((u32)0x00080000)\r
+#define FSMC_ECCPageSize_8192Bytes ((u32)0x000A0000)\r
+\r
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_512Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_8192Bytes))\r
+ \r
+/* FSMC Address Low Mapping --------------------------------------------------*/\r
+#define FSMC_AddressLowMapping_Direct ((u32)0x00000000)\r
+#define FSMC_AddressLowMapping_InDirect ((u32)0x00000100)\r
+\r
+#define IS_FSMC_ADDRESS_LOW_MAPPING(MAPPING) (((MAPPING) == FSMC_AddressLowMapping_Direct) || \\r
+ ((MAPPING) == FSMC_AddressLowMapping_InDirect))\r
+/* FSMC TCLR Setup Time ------------------------------------------------------*/\r
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/* FSMC TAR Setup Time -------------------------------------------------------*/\r
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/* FSMC Setup Time ----------------------------------------------------*/\r
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/* FSMC Wait Setup Time -----------------------------------------------*/\r
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/* FSMC Hold Setup Time -----------------------------------------------*/\r
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/* FSMC HiZ Setup Time ------------------------------------------------*/\r
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/* FSMC Interrupt sources ----------------------------------------------------*/\r
+#define FSMC_IT_RisingEdge ((u32)0x00000008)\r
+#define FSMC_IT_Level ((u32)0x00000010)\r
+#define FSMC_IT_FallingEdge ((u32)0x00000020)\r
+\r
+#define IS_FSMC_IT(IT) ((((IT) & (u32)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))\r
+\r
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \\r
+ ((IT) == FSMC_IT_Level) || \\r
+ ((IT) == FSMC_IT_FallingEdge)) \r
+\r
+/* FSMC Flags ----------------------------------------------------------------*/\r
+#define FSMC_FLAG_RisingEdge ((u32)0x00000001)\r
+#define FSMC_FLAG_Level ((u32)0x00000002)\r
+#define FSMC_FLAG_FallingEdge ((u32)0x00000004)\r
+#define FSMC_FLAG_FEMPT ((u32)0x00000040)\r
+\r
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \\r
+ ((FLAG) == FSMC_FLAG_Level) || \\r
+ ((FLAG) == FSMC_FLAG_FallingEdge) || \\r
+ ((FLAG) == FSMC_FLAG_FEMPT))\r
+\r
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void FSMC_NORSRAMDeInit(u32 FSMC_Bank);\r
+void FSMC_NANDDeInit(u32 FSMC_Bank);\r
+void FSMC_PCCARDDeInit(void);\r
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
+void FSMC_NORSRAMCmd(u32 FSMC_Bank, FunctionalState NewState);\r
+void FSMC_NANDCmd(u32 FSMC_Bank, FunctionalState NewState);\r
+void FSMC_PCCARDCmd(FunctionalState NewState);\r
+void FSMC_NANDECCCmd(u32 FSMC_Bank, FunctionalState NewState);\r
+u32 FSMC_GetECC(u32 FSMC_Bank);\r
+void FSMC_ITConfig(u32 FSMC_Bank, u32 FSMC_IT, FunctionalState NewState);\r
+FlagStatus FSMC_GetFlagStatus(u32 FSMC_Bank, u32 FSMC_FLAG);\r
+void FSMC_ClearFlag(u32 FSMC_Bank, u32 FSMC_FLAG);\r
+ITStatus FSMC_GetITStatus(u32 FSMC_Bank, u32 FSMC_IT);\r
+void FSMC_ClearITPendingBit(u32 FSMC_Bank, u32 FSMC_IT);\r
+\r
+#endif /*__STM32F10x_FSMC_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_gpio.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* GPIO firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_GPIO_H\r
+#define __STM32F10x_GPIO_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == GPIOA_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == GPIOB_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == GPIOC_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == GPIOD_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == GPIOE_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == GPIOF_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == GPIOG_BASE))\r
+ \r
+/* Output Maximum frequency selection ----------------------------------------*/\r
+typedef enum\r
+{ \r
+ GPIO_Speed_10MHz = 1,\r
+ GPIO_Speed_2MHz, \r
+ GPIO_Speed_50MHz\r
+}GPIOSpeed_TypeDef;\r
+\r
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \\r
+ ((SPEED) == GPIO_Speed_50MHz))\r
+ \r
+/* Configuration Mode enumeration --------------------------------------------*/\r
+typedef enum\r
+{ GPIO_Mode_AIN = 0x0,\r
+ GPIO_Mode_IN_FLOATING = 0x04,\r
+ GPIO_Mode_IPD = 0x28,\r
+ GPIO_Mode_IPU = 0x48,\r
+ GPIO_Mode_Out_OD = 0x14,\r
+ GPIO_Mode_Out_PP = 0x10,\r
+ GPIO_Mode_AF_OD = 0x1C,\r
+ GPIO_Mode_AF_PP = 0x18\r
+}GPIOMode_TypeDef;\r
+\r
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \\r
+ ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \\r
+ ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \\r
+ ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))\r
+ \r
+/* GPIO Init structure definition */\r
+typedef struct\r
+{\r
+ u16 GPIO_Pin;\r
+ GPIOSpeed_TypeDef GPIO_Speed;\r
+ GPIOMode_TypeDef GPIO_Mode;\r
+}GPIO_InitTypeDef;\r
+\r
+/* Bit_SET and Bit_RESET enumeration -----------------------------------------*/\r
+typedef enum\r
+{ Bit_RESET = 0,\r
+ Bit_SET\r
+}BitAction;\r
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* GPIO pins define ----------------------------------------------------------*/\r
+#define GPIO_Pin_0 ((u16)0x0001) /* Pin 0 selected */\r
+#define GPIO_Pin_1 ((u16)0x0002) /* Pin 1 selected */\r
+#define GPIO_Pin_2 ((u16)0x0004) /* Pin 2 selected */\r
+#define GPIO_Pin_3 ((u16)0x0008) /* Pin 3 selected */\r
+#define GPIO_Pin_4 ((u16)0x0010) /* Pin 4 selected */\r
+#define GPIO_Pin_5 ((u16)0x0020) /* Pin 5 selected */\r
+#define GPIO_Pin_6 ((u16)0x0040) /* Pin 6 selected */\r
+#define GPIO_Pin_7 ((u16)0x0080) /* Pin 7 selected */\r
+#define GPIO_Pin_8 ((u16)0x0100) /* Pin 8 selected */\r
+#define GPIO_Pin_9 ((u16)0x0200) /* Pin 9 selected */\r
+#define GPIO_Pin_10 ((u16)0x0400) /* Pin 10 selected */\r
+#define GPIO_Pin_11 ((u16)0x0800) /* Pin 11 selected */\r
+#define GPIO_Pin_12 ((u16)0x1000) /* Pin 12 selected */\r
+#define GPIO_Pin_13 ((u16)0x2000) /* Pin 13 selected */\r
+#define GPIO_Pin_14 ((u16)0x4000) /* Pin 14 selected */\r
+#define GPIO_Pin_15 ((u16)0x8000) /* Pin 15 selected */\r
+#define GPIO_Pin_All ((u16)0xFFFF) /* All pins selected */\r
+\r
+#define IS_GPIO_PIN(PIN) ((((PIN) & (u16)0x00) == 0x00) && ((PIN) != (u16)0x00))\r
+\r
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \\r
+ ((PIN) == GPIO_Pin_1) || \\r
+ ((PIN) == GPIO_Pin_2) || \\r
+ ((PIN) == GPIO_Pin_3) || \\r
+ ((PIN) == GPIO_Pin_4) || \\r
+ ((PIN) == GPIO_Pin_5) || \\r
+ ((PIN) == GPIO_Pin_6) || \\r
+ ((PIN) == GPIO_Pin_7) || \\r
+ ((PIN) == GPIO_Pin_8) || \\r
+ ((PIN) == GPIO_Pin_9) || \\r
+ ((PIN) == GPIO_Pin_10) || \\r
+ ((PIN) == GPIO_Pin_11) || \\r
+ ((PIN) == GPIO_Pin_12) || \\r
+ ((PIN) == GPIO_Pin_13) || \\r
+ ((PIN) == GPIO_Pin_14) || \\r
+ ((PIN) == GPIO_Pin_15))\r
+ \r
+/* GPIO Remap define ---------------------------------------------------------*/\r
+#define GPIO_Remap_SPI1 ((u32)0x00000001) /* SPI1 Alternate Function mapping */\r
+#define GPIO_Remap_I2C1 ((u32)0x00000002) /* I2C1 Alternate Function mapping */\r
+#define GPIO_Remap_USART1 ((u32)0x00000004) /* USART1 Alternate Function mapping */\r
+#define GPIO_Remap_USART2 ((u32)0x00000008) /* USART2 Alternate Function mapping */\r
+#define GPIO_PartialRemap_USART3 ((u32)0x00140010) /* USART3 Partial Alternate Function mapping */\r
+#define GPIO_FullRemap_USART3 ((u32)0x00140030) /* USART3 Full Alternate Function mapping */\r
+#define GPIO_PartialRemap_TIM1 ((u32)0x00160040) /* TIM1 Partial Alternate Function mapping */\r
+#define GPIO_FullRemap_TIM1 ((u32)0x001600C0) /* TIM1 Full Alternate Function mapping */\r
+#define GPIO_PartialRemap1_TIM2 ((u32)0x00180100) /* TIM2 Partial1 Alternate Function mapping */\r
+#define GPIO_PartialRemap2_TIM2 ((u32)0x00180200) /* TIM2 Partial2 Alternate Function mapping */\r
+#define GPIO_FullRemap_TIM2 ((u32)0x00180300) /* TIM2 Full Alternate Function mapping */\r
+#define GPIO_PartialRemap_TIM3 ((u32)0x001A0800) /* TIM3 Partial Alternate Function mapping */\r
+#define GPIO_FullRemap_TIM3 ((u32)0x001A0C00) /* TIM3 Full Alternate Function mapping */\r
+#define GPIO_Remap_TIM4 ((u32)0x00001000) /* TIM4 Alternate Function mapping */\r
+#define GPIO_Remap1_CAN ((u32)0x001D4000) /* CAN Alternate Function mapping */\r
+#define GPIO_Remap2_CAN ((u32)0x001D6000) /* CAN Alternate Function mapping */\r
+#define GPIO_Remap_PD01 ((u32)0x00008000) /* PD01 Alternate Function mapping */\r
+#define GPIO_Remap_TIM5CH4_LSI ((u32)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */\r
+#define GPIO_Remap_ADC1_ETRGINJ ((u32)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */\r
+#define GPIO_Remap_ADC1_ETRGREG ((u32)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */\r
+#define GPIO_Remap_ADC2_ETRGINJ ((u32)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */\r
+#define GPIO_Remap_ADC2_ETRGREG ((u32)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */\r
+#define GPIO_Remap_SWJ_NoJTRST ((u32)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */\r
+#define GPIO_Remap_SWJ_JTAGDisable ((u32)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */\r
+#define GPIO_Remap_SWJ_Disable ((u32)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */\r
+\r
+\r
+#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \\r
+ ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \\r
+ ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \\r
+ ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \\r
+ ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \\r
+ ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \\r
+ ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \\r
+ ((REMAP) == GPIO_Remap1_CAN) || ((REMAP) == GPIO_Remap2_CAN) || \\r
+ ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \\r
+ ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \\r
+ ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \\r
+ ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \\r
+ ((REMAP) == GPIO_Remap_SWJ_Disable))\r
+ \r
+/* GPIO Port Sources ---------------------------------------------------------*/\r
+#define GPIO_PortSourceGPIOA ((u8)0x00)\r
+#define GPIO_PortSourceGPIOB ((u8)0x01)\r
+#define GPIO_PortSourceGPIOC ((u8)0x02)\r
+#define GPIO_PortSourceGPIOD ((u8)0x03)\r
+#define GPIO_PortSourceGPIOE ((u8)0x04)\r
+#define GPIO_PortSourceGPIOF ((u8)0x05)\r
+#define GPIO_PortSourceGPIOG ((u8)0x06)\r
+\r
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOE))\r
+ \r
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOG))\r
+ \r
+/* GPIO Pin sources ----------------------------------------------------------*/\r
+#define GPIO_PinSource0 ((u8)0x00)\r
+#define GPIO_PinSource1 ((u8)0x01)\r
+#define GPIO_PinSource2 ((u8)0x02)\r
+#define GPIO_PinSource3 ((u8)0x03)\r
+#define GPIO_PinSource4 ((u8)0x04)\r
+#define GPIO_PinSource5 ((u8)0x05)\r
+#define GPIO_PinSource6 ((u8)0x06)\r
+#define GPIO_PinSource7 ((u8)0x07)\r
+#define GPIO_PinSource8 ((u8)0x08)\r
+#define GPIO_PinSource9 ((u8)0x09)\r
+#define GPIO_PinSource10 ((u8)0x0A)\r
+#define GPIO_PinSource11 ((u8)0x0B)\r
+#define GPIO_PinSource12 ((u8)0x0C)\r
+#define GPIO_PinSource13 ((u8)0x0D)\r
+#define GPIO_PinSource14 ((u8)0x0E)\r
+#define GPIO_PinSource15 ((u8)0x0F)\r
+\r
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \\r
+ ((PINSOURCE) == GPIO_PinSource1) || \\r
+ ((PINSOURCE) == GPIO_PinSource2) || \\r
+ ((PINSOURCE) == GPIO_PinSource3) || \\r
+ ((PINSOURCE) == GPIO_PinSource4) || \\r
+ ((PINSOURCE) == GPIO_PinSource5) || \\r
+ ((PINSOURCE) == GPIO_PinSource6) || \\r
+ ((PINSOURCE) == GPIO_PinSource7) || \\r
+ ((PINSOURCE) == GPIO_PinSource8) || \\r
+ ((PINSOURCE) == GPIO_PinSource9) || \\r
+ ((PINSOURCE) == GPIO_PinSource10) || \\r
+ ((PINSOURCE) == GPIO_PinSource11) || \\r
+ ((PINSOURCE) == GPIO_PinSource12) || \\r
+ ((PINSOURCE) == GPIO_PinSource13) || \\r
+ ((PINSOURCE) == GPIO_PinSource14) || \\r
+ ((PINSOURCE) == GPIO_PinSource15))\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);\r
+void GPIO_AFIODeInit(void);\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);\r
+u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);\r
+u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx);\r
+u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);\r
+u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal);\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal);\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);\r
+void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);\r
+void GPIO_EventOutputCmd(FunctionalState NewState);\r
+void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState);\r
+void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);\r
+\r
+#endif /* __STM32F10x_GPIO_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_i2c.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* I2C firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_I2C_H \r
+#define __STM32F10x_I2C_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* I2C Init structure definition */\r
+typedef struct\r
+{\r
+ u16 I2C_Mode;\r
+ u16 I2C_DutyCycle;\r
+ u16 I2C_OwnAddress1;\r
+ u16 I2C_Ack;\r
+ u16 I2C_AcknowledgedAddress;\r
+ u32 I2C_ClockSpeed;\r
+}I2C_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+#define IS_I2C_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == I2C1_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == I2C2_BASE))\r
+\r
+/* I2C modes */\r
+#define I2C_Mode_I2C ((u16)0x0000)\r
+#define I2C_Mode_SMBusDevice ((u16)0x0002)\r
+#define I2C_Mode_SMBusHost ((u16)0x000A)\r
+\r
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \\r
+ ((MODE) == I2C_Mode_SMBusDevice) || \\r
+ ((MODE) == I2C_Mode_SMBusHost))\r
+/* I2C duty cycle in fast mode */\r
+#define I2C_DutyCycle_16_9 ((u16)0x4000)\r
+#define I2C_DutyCycle_2 ((u16)0xBFFF)\r
+\r
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \\r
+ ((CYCLE) == I2C_DutyCycle_2))\r
+\r
+/* I2C cknowledgementy */\r
+#define I2C_Ack_Enable ((u16)0x0400)\r
+#define I2C_Ack_Disable ((u16)0x0000)\r
+\r
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \\r
+ ((STATE) == I2C_Ack_Disable))\r
+\r
+/* I2C transfer direction */\r
+#define I2C_Direction_Transmitter ((u8)0x00)\r
+#define I2C_Direction_Receiver ((u8)0x01)\r
+\r
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \\r
+ ((DIRECTION) == I2C_Direction_Receiver))\r
+\r
+/* I2C acknowledged address defines */\r
+#define I2C_AcknowledgedAddress_7bit ((u16)0x4000)\r
+#define I2C_AcknowledgedAddress_10bit ((u16)0xC000)\r
+\r
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \\r
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))\r
+\r
+/* I2C registers */\r
+#define I2C_Register_CR1 ((u8)0x00)\r
+#define I2C_Register_CR2 ((u8)0x04)\r
+#define I2C_Register_OAR1 ((u8)0x08)\r
+#define I2C_Register_OAR2 ((u8)0x0C)\r
+#define I2C_Register_DR ((u8)0x10)\r
+#define I2C_Register_SR1 ((u8)0x14)\r
+#define I2C_Register_SR2 ((u8)0x18)\r
+#define I2C_Register_CCR ((u8)0x1C)\r
+#define I2C_Register_TRISE ((u8)0x20)\r
+\r
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \\r
+ ((REGISTER) == I2C_Register_CR2) || \\r
+ ((REGISTER) == I2C_Register_OAR1) || \\r
+ ((REGISTER) == I2C_Register_OAR2) || \\r
+ ((REGISTER) == I2C_Register_DR) || \\r
+ ((REGISTER) == I2C_Register_SR1) || \\r
+ ((REGISTER) == I2C_Register_SR2) || \\r
+ ((REGISTER) == I2C_Register_CCR) || \\r
+ ((REGISTER) == I2C_Register_TRISE))\r
+\r
+/* I2C SMBus alert pin level */\r
+#define I2C_SMBusAlert_Low ((u16)0x2000)\r
+#define I2C_SMBusAlert_High ((u16)0xDFFF)\r
+\r
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \\r
+ ((ALERT) == I2C_SMBusAlert_High))\r
+\r
+/* I2C PEC position */\r
+#define I2C_PECPosition_Next ((u16)0x0800)\r
+#define I2C_PECPosition_Current ((u16)0xF7FF)\r
+\r
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \\r
+ ((POSITION) == I2C_PECPosition_Current))\r
+\r
+/* I2C interrupts definition */\r
+#define I2C_IT_BUF ((u16)0x0400)\r
+#define I2C_IT_EVT ((u16)0x0200)\r
+#define I2C_IT_ERR ((u16)0x0100)\r
+\r
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (u16)0xF8FF) == 0x00) && ((IT) != 0x00))\r
+\r
+/* I2C interrupts definition */\r
+#define I2C_IT_SMBALERT ((u32)0x10008000)\r
+#define I2C_IT_TIMEOUT ((u32)0x10004000)\r
+#define I2C_IT_PECERR ((u32)0x10001000)\r
+#define I2C_IT_OVR ((u32)0x10000800)\r
+#define I2C_IT_AF ((u32)0x10000400)\r
+#define I2C_IT_ARLO ((u32)0x10000200)\r
+#define I2C_IT_BERR ((u32)0x10000100)\r
+#define I2C_IT_TXE ((u32)0x00000080)\r
+#define I2C_IT_RXNE ((u32)0x00000040)\r
+#define I2C_IT_STOPF ((u32)0x60000010)\r
+#define I2C_IT_ADD10 ((u32)0x20000008)\r
+#define I2C_IT_BTF ((u32)0x60000004)\r
+#define I2C_IT_ADDR ((u32)0xA0000002)\r
+#define I2C_IT_SB ((u32)0x20000001)\r
+\r
+#define IS_I2C_CLEAR_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \\r
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \\r
+ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \\r
+ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_STOPF) || \\r
+ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \\r
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))\r
+\r
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \\r
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \\r
+ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \\r
+ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \\r
+ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \\r
+ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \\r
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))\r
+\r
+/* I2C flags definition */\r
+#define I2C_FLAG_DUALF ((u32)0x00800000)\r
+#define I2C_FLAG_SMBHOST ((u32)0x00400000)\r
+#define I2C_FLAG_SMBDEFAULT ((u32)0x00200000)\r
+#define I2C_FLAG_GENCALL ((u32)0x00100000)\r
+#define I2C_FLAG_TRA ((u32)0x00040000)\r
+#define I2C_FLAG_BUSY ((u32)0x00020000)\r
+#define I2C_FLAG_MSL ((u32)0x00010000)\r
+#define I2C_FLAG_SMBALERT ((u32)0x10008000)\r
+#define I2C_FLAG_TIMEOUT ((u32)0x10004000)\r
+#define I2C_FLAG_PECERR ((u32)0x10001000)\r
+#define I2C_FLAG_OVR ((u32)0x10000800)\r
+#define I2C_FLAG_AF ((u32)0x10000400)\r
+#define I2C_FLAG_ARLO ((u32)0x10000200)\r
+#define I2C_FLAG_BERR ((u32)0x10000100)\r
+#define I2C_FLAG_TXE ((u32)0x00000080)\r
+#define I2C_FLAG_RXNE ((u32)0x00000040)\r
+#define I2C_FLAG_STOPF ((u32)0x60000010)\r
+#define I2C_FLAG_ADD10 ((u32)0x20000008)\r
+#define I2C_FLAG_BTF ((u32)0x60000004)\r
+#define I2C_FLAG_ADDR ((u32)0xA0000002)\r
+#define I2C_FLAG_SB ((u32)0x20000001)\r
+\r
+#define IS_I2C_CLEAR_FLAG(FLAG) (((FLAG) == I2C_FLAG_SMBALERT) || ((FLAG) == I2C_FLAG_TIMEOUT) || \\r
+ ((FLAG) == I2C_FLAG_PECERR) || ((FLAG) == I2C_FLAG_OVR) || \\r
+ ((FLAG) == I2C_FLAG_AF) || ((FLAG) == I2C_FLAG_ARLO) || \\r
+ ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_STOPF) || \\r
+ ((FLAG) == I2C_FLAG_ADD10) || ((FLAG) == I2C_FLAG_BTF) || \\r
+ ((FLAG) == I2C_FLAG_ADDR) || ((FLAG) == I2C_FLAG_SB))\r
+\r
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \\r
+ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \\r
+ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \\r
+ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \\r
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \\r
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \\r
+ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \\r
+ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \\r
+ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \\r
+ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \\r
+ ((FLAG) == I2C_FLAG_SB))\r
+\r
+/* I2C Events */\r
+/* EV1 */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((u32)0x00060082) /* TRA, BUSY, TXE and ADDR flags */\r
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((u32)0x00020002) /* BUSY and ADDR flags */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((u32)0x00860080) /* DUALF, TRA, BUSY and TXE flags */\r
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((u32)0x00820000) /* DUALF and BUSY flags */\r
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((u32)0x00120000) /* GENCALL and BUSY flags */\r
+\r
+/* EV2 */\r
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((u32)0x00020040) /* BUSY and RXNE flags */\r
+ \r
+/* EV3 */\r
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((u32)0x00060084) /* TRA, BUSY, TXE and BTF flags */\r
+\r
+/* EV4 */\r
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((u32)0x00000010) /* STOPF flag */\r
+\r
+/* EV5 */\r
+#define I2C_EVENT_MASTER_MODE_SELECT ((u32)0x00030001) /* BUSY, MSL and SB flag */\r
+\r
+/* EV6 */\r
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((u32)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */\r
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((u32)0x00030002) /* BUSY, MSL and ADDR flags */\r
+\r
+/* EV7 */\r
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((u32)0x00030040) /* BUSY, MSL and RXNE flags */\r
+\r
+/* EV8 */\r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((u32)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */\r
+ \r
+/* EV9 */\r
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((u32)0x00030008) /* BUSY, MSL and ADD10 flags */\r
+ \r
+/* EV3_2 */\r
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((u32)0x00000400) /* AF flag */\r
+\r
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))\r
+\r
+/* I2C own address1 -----------------------------------------------------------*/\r
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)\r
+/* I2C clock speed ------------------------------------------------------------*/\r
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void I2C_DeInit(I2C_TypeDef* I2Cx);\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address);\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState);\r
+void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data);\r
+u8 I2C_ReceiveData(I2C_TypeDef* I2Cx);\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction);\r
+u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register);\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert);\r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition);\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+u8 I2C_GetPEC(I2C_TypeDef* I2Cx);\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle);\r
+u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx);\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT);\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG);\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG);\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT);\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT);\r
+\r
+#endif /*__STM32F10x_I2C_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_iwdg.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* IWDG firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_IWDG_H\r
+#define __STM32F10x_IWDG_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Write access to IWDG_PR and IWDG_RLR registers */\r
+#define IWDG_WriteAccess_Enable ((u16)0x5555)\r
+#define IWDG_WriteAccess_Disable ((u16)0x0000)\r
+\r
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \\r
+ ((ACCESS) == IWDG_WriteAccess_Disable))\r
+\r
+/* IWDG prescaler */\r
+#define IWDG_Prescaler_4 ((u8)0x00)\r
+#define IWDG_Prescaler_8 ((u8)0x01)\r
+#define IWDG_Prescaler_16 ((u8)0x02)\r
+#define IWDG_Prescaler_32 ((u8)0x03)\r
+#define IWDG_Prescaler_64 ((u8)0x04)\r
+#define IWDG_Prescaler_128 ((u8)0x05)\r
+#define IWDG_Prescaler_256 ((u8)0x06)\r
+\r
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \\r
+ ((PRESCALER) == IWDG_Prescaler_8) || \\r
+ ((PRESCALER) == IWDG_Prescaler_16) || \\r
+ ((PRESCALER) == IWDG_Prescaler_32) || \\r
+ ((PRESCALER) == IWDG_Prescaler_64) || \\r
+ ((PRESCALER) == IWDG_Prescaler_128)|| \\r
+ ((PRESCALER) == IWDG_Prescaler_256))\r
+\r
+/* IWDG Flag */\r
+#define IWDG_FLAG_PVU ((u16)0x0001)\r
+#define IWDG_FLAG_RVU ((u16)0x0002)\r
+\r
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))\r
+\r
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess);\r
+void IWDG_SetPrescaler(u8 IWDG_Prescaler);\r
+void IWDG_SetReload(u16 Reload);\r
+void IWDG_ReloadCounter(void);\r
+void IWDG_Enable(void);\r
+FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG);\r
+\r
+#endif /* __STM32F10x_IWDG_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_lib.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file includes the peripherals header files in the\r
+* user application.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_LIB_H\r
+#define __STM32F10x_LIB_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+#ifdef _ADC\r
+ #include "stm32f10x_adc.h"\r
+#endif /*_ADC */\r
+\r
+#ifdef _BKP\r
+ #include "stm32f10x_bkp.h"\r
+#endif /*_BKP */\r
+\r
+#ifdef _CAN\r
+ #include "stm32f10x_can.h"\r
+#endif /*_CAN */\r
+\r
+#ifdef _CRC\r
+ #include "stm32f10x_crc.h"\r
+#endif /*_CRC */\r
+\r
+#ifdef _DAC\r
+ #include "stm32f10x_dac.h"\r
+#endif /*_DAC */\r
+\r
+#ifdef _DBGMCU\r
+ #include "stm32f10x_dbgmcu.h"\r
+#endif /*_DBGMCU */\r
+\r
+#ifdef _DMA\r
+ #include "stm32f10x_dma.h"\r
+#endif /*_DMA */\r
+\r
+#ifdef _EXTI\r
+ #include "stm32f10x_exti.h"\r
+#endif /*_EXTI */\r
+\r
+#ifdef _FLASH\r
+ #include "stm32f10x_flash.h"\r
+#endif /*_FLASH */\r
+\r
+#ifdef _FSMC\r
+ #include "stm32f10x_fsmc.h"\r
+#endif /*_FSMC */\r
+\r
+#ifdef _GPIO\r
+ #include "stm32f10x_gpio.h"\r
+#endif /*_GPIO */\r
+\r
+#ifdef _I2C\r
+ #include "stm32f10x_i2c.h"\r
+#endif /*_I2C */\r
+\r
+#ifdef _IWDG\r
+ #include "stm32f10x_iwdg.h"\r
+#endif /*_IWDG */\r
+\r
+#ifdef _NVIC\r
+ #include "stm32f10x_nvic.h"\r
+#endif /*_NVIC */\r
+\r
+#ifdef _PWR\r
+ #include "stm32f10x_pwr.h"\r
+#endif /*_PWR */\r
+\r
+#ifdef _RCC\r
+ #include "stm32f10x_rcc.h"\r
+#endif /*_RCC */\r
+\r
+#ifdef _RTC\r
+ #include "stm32f10x_rtc.h"\r
+#endif /*_RTC */\r
+\r
+#ifdef _SDIO\r
+ #include "stm32f10x_sdio.h"\r
+#endif /*_SDIO */\r
+\r
+#ifdef _SPI\r
+ #include "stm32f10x_spi.h"\r
+#endif /*_SPI */\r
+\r
+#ifdef _SysTick\r
+ #include "stm32f10x_systick.h"\r
+#endif /*_SysTick */\r
+\r
+#ifdef _TIM\r
+ #include "stm32f10x_tim.h"\r
+#endif /*_TIM */\r
+\r
+#ifdef _USART\r
+ #include "stm32f10x_usart.h"\r
+#endif /*_USART */\r
+\r
+#ifdef _WWDG\r
+ #include "stm32f10x_wwdg.h"\r
+#endif /*_WWDG */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void debug(void);\r
+\r
+#endif /* __STM32F10x_LIB_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_map.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the peripheral register's definitions\r
+* and memory mapping.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_MAP_H\r
+#define __STM32F10x_MAP_H\r
+\r
+#ifndef EXT\r
+ #define EXT extern\r
+#endif /* EXT */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_conf.h"\r
+#include "stm32f10x_type.h"\r
+#include "cortexm3_macro.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/******************************************************************************/\r
+/* Peripheral registers structures */\r
+/******************************************************************************/\r
+\r
+/*------------------------ Analog to Digital Converter -----------------------*/\r
+typedef struct\r
+{\r
+ vu32 SR;\r
+ vu32 CR1;\r
+ vu32 CR2;\r
+ vu32 SMPR1;\r
+ vu32 SMPR2;\r
+ vu32 JOFR1;\r
+ vu32 JOFR2;\r
+ vu32 JOFR3;\r
+ vu32 JOFR4;\r
+ vu32 HTR;\r
+ vu32 LTR;\r
+ vu32 SQR1;\r
+ vu32 SQR2;\r
+ vu32 SQR3;\r
+ vu32 JSQR;\r
+ vu32 JDR1;\r
+ vu32 JDR2;\r
+ vu32 JDR3;\r
+ vu32 JDR4;\r
+ vu32 DR;\r
+} ADC_TypeDef;\r
+\r
+/*------------------------ Backup Registers ----------------------------------*/\r
+typedef struct\r
+{\r
+ u32 RESERVED0;\r
+ vu16 DR1;\r
+ u16 RESERVED1;\r
+ vu16 DR2;\r
+ u16 RESERVED2;\r
+ vu16 DR3;\r
+ u16 RESERVED3;\r
+ vu16 DR4;\r
+ u16 RESERVED4;\r
+ vu16 DR5;\r
+ u16 RESERVED5;\r
+ vu16 DR6;\r
+ u16 RESERVED6;\r
+ vu16 DR7;\r
+ u16 RESERVED7;\r
+ vu16 DR8;\r
+ u16 RESERVED8;\r
+ vu16 DR9;\r
+ u16 RESERVED9;\r
+ vu16 DR10;\r
+ u16 RESERVED10; \r
+ vu16 RTCCR;\r
+ u16 RESERVED11;\r
+ vu16 CR;\r
+ u16 RESERVED12;\r
+ vu16 CSR;\r
+ u16 RESERVED13[5];\r
+ vu16 DR11;\r
+ u16 RESERVED14;\r
+ vu16 DR12;\r
+ u16 RESERVED15;\r
+ vu16 DR13;\r
+ u16 RESERVED16;\r
+ vu16 DR14;\r
+ u16 RESERVED17;\r
+ vu16 DR15;\r
+ u16 RESERVED18;\r
+ vu16 DR16;\r
+ u16 RESERVED19;\r
+ vu16 DR17;\r
+ u16 RESERVED20;\r
+ vu16 DR18;\r
+ u16 RESERVED21;\r
+ vu16 DR19;\r
+ u16 RESERVED22;\r
+ vu16 DR20;\r
+ u16 RESERVED23;\r
+ vu16 DR21;\r
+ u16 RESERVED24;\r
+ vu16 DR22;\r
+ u16 RESERVED25;\r
+ vu16 DR23;\r
+ u16 RESERVED26;\r
+ vu16 DR24;\r
+ u16 RESERVED27;\r
+ vu16 DR25;\r
+ u16 RESERVED28;\r
+ vu16 DR26;\r
+ u16 RESERVED29;\r
+ vu16 DR27;\r
+ u16 RESERVED30;\r
+ vu16 DR28;\r
+ u16 RESERVED31;\r
+ vu16 DR29;\r
+ u16 RESERVED32;\r
+ vu16 DR30;\r
+ u16 RESERVED33; \r
+ vu16 DR31;\r
+ u16 RESERVED34;\r
+ vu16 DR32;\r
+ u16 RESERVED35;\r
+ vu16 DR33;\r
+ u16 RESERVED36;\r
+ vu16 DR34;\r
+ u16 RESERVED37;\r
+ vu16 DR35;\r
+ u16 RESERVED38;\r
+ vu16 DR36;\r
+ u16 RESERVED39;\r
+ vu16 DR37;\r
+ u16 RESERVED40;\r
+ vu16 DR38;\r
+ u16 RESERVED41;\r
+ vu16 DR39;\r
+ u16 RESERVED42;\r
+ vu16 DR40;\r
+ u16 RESERVED43;\r
+ vu16 DR41;\r
+ u16 RESERVED44;\r
+ vu16 DR42;\r
+ u16 RESERVED45; \r
+} BKP_TypeDef;\r
+\r
+/*------------------------ Controller Area Network ---------------------------*/\r
+typedef struct\r
+{\r
+ vu32 TIR;\r
+ vu32 TDTR;\r
+ vu32 TDLR;\r
+ vu32 TDHR;\r
+} CAN_TxMailBox_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 RIR;\r
+ vu32 RDTR;\r
+ vu32 RDLR;\r
+ vu32 RDHR;\r
+} CAN_FIFOMailBox_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 FR1;\r
+ vu32 FR2;\r
+} CAN_FilterRegister_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 MCR;\r
+ vu32 MSR;\r
+ vu32 TSR;\r
+ vu32 RF0R;\r
+ vu32 RF1R;\r
+ vu32 IER;\r
+ vu32 ESR;\r
+ vu32 BTR;\r
+ u32 RESERVED0[88];\r
+ CAN_TxMailBox_TypeDef sTxMailBox[3];\r
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];\r
+ u32 RESERVED1[12];\r
+ vu32 FMR;\r
+ vu32 FM1R;\r
+ u32 RESERVED2;\r
+ vu32 FS1R;\r
+ u32 RESERVED3;\r
+ vu32 FFA1R;\r
+ u32 RESERVED4;\r
+ vu32 FA1R;\r
+ u32 RESERVED5[8];\r
+ CAN_FilterRegister_TypeDef sFilterRegister[14];\r
+} CAN_TypeDef;\r
+\r
+/*------------------------ CRC calculation unit ------------------------------*/\r
+typedef struct\r
+{\r
+ vu32 DR;\r
+ vu8 IDR;\r
+ u8 RESERVED0;\r
+ u16 RESERVED1;\r
+ vu32 CR;\r
+} CRC_TypeDef;\r
+\r
+\r
+/*------------------------ Digital to Analog Converter -----------------------*/\r
+typedef struct\r
+{\r
+ vu32 CR;\r
+ vu32 SWTRIGR;\r
+ vu32 DHR12R1;\r
+ vu32 DHR12L1;\r
+ vu32 DHR8R1;\r
+ vu32 DHR12R2;\r
+ vu32 DHR12L2;\r
+ vu32 DHR8R2;\r
+ vu32 DHR12RD;\r
+ vu32 DHR12LD;\r
+ vu32 DHR8RD;\r
+ vu32 DOR1;\r
+ vu32 DOR2;\r
+} DAC_TypeDef;\r
+\r
+/*------------------------ Debug MCU -----------------------------------------*/\r
+typedef struct\r
+{\r
+ vu32 IDCODE;\r
+ vu32 CR; \r
+}DBGMCU_TypeDef;\r
+\r
+/*------------------------ DMA Controller ------------------------------------*/\r
+typedef struct\r
+{\r
+ vu32 CCR;\r
+ vu32 CNDTR;\r
+ vu32 CPAR;\r
+ vu32 CMAR;\r
+} DMA_Channel_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 ISR;\r
+ vu32 IFCR;\r
+} DMA_TypeDef;\r
+\r
+/*------------------------ External Interrupt/Event Controller ---------------*/\r
+typedef struct\r
+{\r
+ vu32 IMR;\r
+ vu32 EMR;\r
+ vu32 RTSR;\r
+ vu32 FTSR;\r
+ vu32 SWIER;\r
+ vu32 PR;\r
+} EXTI_TypeDef;\r
+\r
+/*------------------------ FLASH and Option Bytes Registers ------------------*/\r
+typedef struct\r
+{\r
+ vu32 ACR;\r
+ vu32 KEYR;\r
+ vu32 OPTKEYR;\r
+ vu32 SR;\r
+ vu32 CR;\r
+ vu32 AR;\r
+ vu32 RESERVED;\r
+ vu32 OBR;\r
+ vu32 WRPR;\r
+} FLASH_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu16 RDP;\r
+ vu16 USER;\r
+ vu16 Data0;\r
+ vu16 Data1;\r
+ vu16 WRP0;\r
+ vu16 WRP1;\r
+ vu16 WRP2;\r
+ vu16 WRP3;\r
+} OB_TypeDef;\r
+\r
+/*------------------------ Flexible Static Memory Controller -----------------*/\r
+typedef struct\r
+{\r
+ vu32 BTCR[8]; \r
+} FSMC_Bank1_TypeDef; \r
+\r
+typedef struct\r
+{\r
+ vu32 BWTR[7];\r
+} FSMC_Bank1E_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 PCR2;\r
+ vu32 SR2;\r
+ vu32 PMEM2;\r
+ vu32 PATT2;\r
+ u32 RESERVED0; \r
+ vu32 ECCR2; \r
+} FSMC_Bank2_TypeDef; \r
+\r
+typedef struct\r
+{\r
+ vu32 PCR3;\r
+ vu32 SR3;\r
+ vu32 PMEM3;\r
+ vu32 PATT3;\r
+ u32 RESERVED0; \r
+ vu32 ECCR3; \r
+} FSMC_Bank3_TypeDef; \r
+\r
+typedef struct\r
+{\r
+ vu32 PCR4;\r
+ vu32 SR4;\r
+ vu32 PMEM4;\r
+ vu32 PATT4;\r
+ vu32 PIO4; \r
+} FSMC_Bank4_TypeDef; \r
+\r
+/*------------------------ General Purpose and Alternate Function IO ---------*/\r
+typedef struct\r
+{\r
+ vu32 CRL;\r
+ vu32 CRH;\r
+ vu32 IDR;\r
+ vu32 ODR;\r
+ vu32 BSRR;\r
+ vu32 BRR;\r
+ vu32 LCKR;\r
+} GPIO_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 EVCR;\r
+ vu32 MAPR;\r
+ vu32 EXTICR[4];\r
+} AFIO_TypeDef;\r
+\r
+/*------------------------ Inter-integrated Circuit Interface ----------------*/\r
+typedef struct\r
+{\r
+ vu16 CR1;\r
+ u16 RESERVED0;\r
+ vu16 CR2;\r
+ u16 RESERVED1;\r
+ vu16 OAR1;\r
+ u16 RESERVED2;\r
+ vu16 OAR2;\r
+ u16 RESERVED3;\r
+ vu16 DR;\r
+ u16 RESERVED4;\r
+ vu16 SR1;\r
+ u16 RESERVED5;\r
+ vu16 SR2;\r
+ u16 RESERVED6;\r
+ vu16 CCR;\r
+ u16 RESERVED7;\r
+ vu16 TRISE;\r
+ u16 RESERVED8;\r
+} I2C_TypeDef;\r
+\r
+/*------------------------ Independent WATCHDOG ------------------------------*/\r
+typedef struct\r
+{\r
+ vu32 KR;\r
+ vu32 PR;\r
+ vu32 RLR;\r
+ vu32 SR;\r
+} IWDG_TypeDef;\r
+\r
+/*------------------------ Nested Vectored Interrupt Controller --------------*/\r
+typedef struct\r
+{\r
+ vu32 ISER[2];\r
+ u32 RESERVED0[30];\r
+ vu32 ICER[2];\r
+ u32 RSERVED1[30];\r
+ vu32 ISPR[2];\r
+ u32 RESERVED2[30];\r
+ vu32 ICPR[2];\r
+ u32 RESERVED3[30];\r
+ vu32 IABR[2];\r
+ u32 RESERVED4[62];\r
+ vu32 IPR[15];\r
+} NVIC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vuc32 CPUID;\r
+ vu32 ICSR;\r
+ vu32 VTOR;\r
+ vu32 AIRCR;\r
+ vu32 SCR;\r
+ vu32 CCR;\r
+ vu32 SHPR[3];\r
+ vu32 SHCSR;\r
+ vu32 CFSR;\r
+ vu32 HFSR;\r
+ vu32 DFSR;\r
+ vu32 MMFAR;\r
+ vu32 BFAR;\r
+ vu32 AFSR;\r
+} SCB_TypeDef;\r
+\r
+/*------------------------ Power Control -------------------------------------*/\r
+typedef struct\r
+{\r
+ vu32 CR;\r
+ vu32 CSR;\r
+} PWR_TypeDef;\r
+\r
+/*------------------------ Reset and Clock Control ---------------------------*/\r
+typedef struct\r
+{\r
+ vu32 CR;\r
+ vu32 CFGR;\r
+ vu32 CIR;\r
+ vu32 APB2RSTR;\r
+ vu32 APB1RSTR;\r
+ vu32 AHBENR;\r
+ vu32 APB2ENR;\r
+ vu32 APB1ENR;\r
+ vu32 BDCR;\r
+ vu32 CSR;\r
+} RCC_TypeDef;\r
+\r
+/*------------------------ Real-Time Clock -----------------------------------*/\r
+typedef struct\r
+{\r
+ vu16 CRH;\r
+ u16 RESERVED0;\r
+ vu16 CRL;\r
+ u16 RESERVED1;\r
+ vu16 PRLH;\r
+ u16 RESERVED2;\r
+ vu16 PRLL;\r
+ u16 RESERVED3;\r
+ vu16 DIVH;\r
+ u16 RESERVED4;\r
+ vu16 DIVL;\r
+ u16 RESERVED5;\r
+ vu16 CNTH;\r
+ u16 RESERVED6;\r
+ vu16 CNTL;\r
+ u16 RESERVED7;\r
+ vu16 ALRH;\r
+ u16 RESERVED8;\r
+ vu16 ALRL;\r
+ u16 RESERVED9;\r
+} RTC_TypeDef;\r
+\r
+/*------------------------ SD host Interface ---------------------------------*/\r
+typedef struct\r
+{\r
+ vu32 POWER;\r
+ vu32 CLKCR;\r
+ vu32 ARG;\r
+ vu32 CMD;\r
+ vuc32 RESPCMD;\r
+ vuc32 RESP1;\r
+ vuc32 RESP2;\r
+ vuc32 RESP3;\r
+ vuc32 RESP4;\r
+ vu32 DTIMER;\r
+ vu32 DLEN;\r
+ vu32 DCTRL;\r
+ vuc32 DCOUNT;\r
+ vuc32 STA;\r
+ vu32 ICR;\r
+ vu32 MASK;\r
+ u32 RESERVED0[2];\r
+ vuc32 FIFOCNT;\r
+ u32 RESERVED1[13];\r
+ vu32 FIFO;\r
+} SDIO_TypeDef;\r
+\r
+/*------------------------ Serial Peripheral Interface -----------------------*/\r
+typedef struct\r
+{\r
+ vu16 CR1;\r
+ u16 RESERVED0;\r
+ vu16 CR2;\r
+ u16 RESERVED1;\r
+ vu16 SR;\r
+ u16 RESERVED2;\r
+ vu16 DR;\r
+ u16 RESERVED3;\r
+ vu16 CRCPR;\r
+ u16 RESERVED4;\r
+ vu16 RXCRCR;\r
+ u16 RESERVED5;\r
+ vu16 TXCRCR;\r
+ u16 RESERVED6;\r
+ vu16 I2SCFGR;\r
+ u16 RESERVED7;\r
+ vu16 I2SPR;\r
+ u16 RESERVED8; \r
+} SPI_TypeDef;\r
+\r
+/*------------------------ SystemTick ----------------------------------------*/\r
+typedef struct\r
+{\r
+ vu32 CTRL;\r
+ vu32 LOAD;\r
+ vu32 VAL;\r
+ vuc32 CALIB;\r
+} SysTick_TypeDef;\r
+\r
+/*------------------------ TIM -----------------------------------------------*/\r
+typedef struct\r
+{\r
+ vu16 CR1;\r
+ u16 RESERVED0;\r
+ vu16 CR2;\r
+ u16 RESERVED1;\r
+ vu16 SMCR;\r
+ u16 RESERVED2;\r
+ vu16 DIER;\r
+ u16 RESERVED3;\r
+ vu16 SR;\r
+ u16 RESERVED4;\r
+ vu16 EGR;\r
+ u16 RESERVED5;\r
+ vu16 CCMR1;\r
+ u16 RESERVED6;\r
+ vu16 CCMR2;\r
+ u16 RESERVED7;\r
+ vu16 CCER;\r
+ u16 RESERVED8;\r
+ vu16 CNT;\r
+ u16 RESERVED9;\r
+ vu16 PSC;\r
+ u16 RESERVED10;\r
+ vu16 ARR;\r
+ u16 RESERVED11;\r
+ vu16 RCR;\r
+ u16 RESERVED12;\r
+ vu16 CCR1;\r
+ u16 RESERVED13;\r
+ vu16 CCR2;\r
+ u16 RESERVED14;\r
+ vu16 CCR3;\r
+ u16 RESERVED15;\r
+ vu16 CCR4;\r
+ u16 RESERVED16;\r
+ vu16 BDTR;\r
+ u16 RESERVED17;\r
+ vu16 DCR;\r
+ u16 RESERVED18;\r
+ vu16 DMAR;\r
+ u16 RESERVED19;\r
+} TIM_TypeDef;\r
+\r
+/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/\r
+typedef struct\r
+{\r
+ vu16 SR;\r
+ u16 RESERVED0;\r
+ vu16 DR;\r
+ u16 RESERVED1;\r
+ vu16 BRR;\r
+ u16 RESERVED2;\r
+ vu16 CR1;\r
+ u16 RESERVED3;\r
+ vu16 CR2;\r
+ u16 RESERVED4;\r
+ vu16 CR3;\r
+ u16 RESERVED5;\r
+ vu16 GTPR;\r
+ u16 RESERVED6;\r
+} USART_TypeDef;\r
+\r
+/*------------------------ Window WATCHDOG -----------------------------------*/\r
+typedef struct\r
+{\r
+ vu32 CR;\r
+ vu32 CFR;\r
+ vu32 SR;\r
+} WWDG_TypeDef;\r
+\r
+/******************************************************************************/\r
+/* Peripheral memory map */\r
+/******************************************************************************/\r
+/* Peripheral and SRAM base address in the alias region */\r
+#define PERIPH_BB_BASE ((u32)0x42000000)\r
+#define SRAM_BB_BASE ((u32)0x22000000)\r
+\r
+/* Peripheral and SRAM base address in the bit-band region */\r
+#define SRAM_BASE ((u32)0x20000000)\r
+#define PERIPH_BASE ((u32)0x40000000)\r
+\r
+/* FSMC registers base address */\r
+#define FSMC_R_BASE ((u32)0xA0000000)\r
+\r
+/* Peripheral memory map */\r
+#define APB1PERIPH_BASE PERIPH_BASE\r
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)\r
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)\r
+\r
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)\r
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)\r
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)\r
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)\r
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)\r
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)\r
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)\r
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)\r
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)\r
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)\r
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)\r
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)\r
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)\r
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)\r
+#define CAN_BASE (APB1PERIPH_BASE + 0x6400)\r
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)\r
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)\r
+\r
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)\r
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)\r
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)\r
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)\r
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)\r
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)\r
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)\r
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)\r
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)\r
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)\r
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)\r
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)\r
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)\r
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)\r
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)\r
+#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)\r
+\r
+#define SDIO_BASE (PERIPH_BASE + 0x18000)\r
+\r
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)\r
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)\r
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)\r
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)\r
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)\r
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)\r
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)\r
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)\r
+#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)\r
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)\r
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)\r
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)\r
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)\r
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)\r
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)\r
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)\r
+\r
+/* Flash registers base address */\r
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)\r
+/* Flash Option Bytes base address */\r
+#define OB_BASE ((u32)0x1FFFF800)\r
+\r
+/* FSMC Bankx registers base address */\r
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)\r
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)\r
+#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)\r
+#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)\r
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)\r
+\r
+/* Debug MCU registers base address */\r
+#define DBGMCU_BASE ((u32)0xE0042000)\r
+\r
+/* System Control Space memory map */\r
+#define SCS_BASE ((u32)0xE000E000)\r
+\r
+#define SysTick_BASE (SCS_BASE + 0x0010)\r
+#define NVIC_BASE (SCS_BASE + 0x0100)\r
+#define SCB_BASE (SCS_BASE + 0x0D00)\r
+\r
+/******************************************************************************/\r
+/* Peripheral declaration */\r
+/******************************************************************************/\r
+\r
+/*------------------------ Non Debug Mode ------------------------------------*/\r
+#ifndef DEBUG\r
+#ifdef _TIM2\r
+ #define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#endif /*_TIM2 */\r
+\r
+#ifdef _TIM3\r
+ #define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#endif /*_TIM3 */\r
+\r
+#ifdef _TIM4\r
+ #define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
+#endif /*_TIM4 */\r
+\r
+#ifdef _TIM5\r
+ #define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
+#endif /*_TIM5 */\r
+\r
+#ifdef _TIM6\r
+ #define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
+#endif /*_TIM6 */\r
+\r
+#ifdef _TIM7\r
+ #define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#endif /*_TIM7 */\r
+\r
+#ifdef _RTC\r
+ #define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#endif /*_RTC */\r
+\r
+#ifdef _WWDG\r
+ #define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
+#endif /*_WWDG */\r
+\r
+#ifdef _IWDG\r
+ #define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
+#endif /*_IWDG */\r
+\r
+#ifdef _SPI2\r
+ #define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#endif /*_SPI2 */\r
+\r
+#ifdef _SPI3\r
+ #define SPI3 ((SPI_TypeDef *) SPI3_BASE)\r
+#endif /*_SPI3 */\r
+\r
+#ifdef _USART2\r
+ #define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#endif /*_USART2 */\r
+\r
+#ifdef _USART3\r
+ #define USART3 ((USART_TypeDef *) USART3_BASE)\r
+#endif /*_USART3 */\r
+\r
+#ifdef _UART4\r
+ #define UART4 ((USART_TypeDef *) UART4_BASE)\r
+#endif /*_UART4 */\r
+\r
+#ifdef _UART5\r
+ #define UART5 ((USART_TypeDef *) UART5_BASE)\r
+#endif /*_USART5 */\r
+\r
+#ifdef _I2C1\r
+ #define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#endif /*_I2C1 */\r
+\r
+#ifdef _I2C2\r
+ #define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+#endif /*_I2C2 */\r
+\r
+#ifdef _CAN\r
+ #define CAN ((CAN_TypeDef *) CAN_BASE)\r
+#endif /*_CAN */\r
+\r
+#ifdef _BKP\r
+ #define BKP ((BKP_TypeDef *) BKP_BASE)\r
+#endif /*_BKP */\r
+\r
+#ifdef _PWR\r
+ #define PWR ((PWR_TypeDef *) PWR_BASE)\r
+#endif /*_PWR */\r
+\r
+#ifdef _DAC\r
+ #define DAC ((DAC_TypeDef *) DAC_BASE)\r
+#endif /*_DAC */\r
+\r
+#ifdef _AFIO\r
+ #define AFIO ((AFIO_TypeDef *) AFIO_BASE)\r
+#endif /*_AFIO */\r
+\r
+#ifdef _EXTI\r
+ #define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+#endif /*_EXTI */\r
+\r
+#ifdef _GPIOA\r
+ #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#endif /*_GPIOA */\r
+\r
+#ifdef _GPIOB\r
+ #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#endif /*_GPIOB */\r
+\r
+#ifdef _GPIOC\r
+ #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#endif /*_GPIOC */\r
+\r
+#ifdef _GPIOD\r
+ #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#endif /*_GPIOD */\r
+\r
+#ifdef _GPIOE\r
+ #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
+#endif /*_GPIOE */\r
+\r
+#ifdef _GPIOF\r
+ #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r
+#endif /*_GPIOF */\r
+\r
+#ifdef _GPIOG\r
+ #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\r
+#endif /*_GPIOG */\r
+\r
+#ifdef _ADC1\r
+ #define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#endif /*_ADC1 */\r
+\r
+#ifdef _ADC2\r
+ #define ADC2 ((ADC_TypeDef *) ADC2_BASE)\r
+#endif /*_ADC2 */\r
+\r
+#ifdef _TIM1\r
+ #define TIM1 ((TIM_TypeDef *) TIM1_BASE)\r
+#endif /*_TIM1 */\r
+\r
+#ifdef _SPI1\r
+ #define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
+#endif /*_SPI1 */\r
+\r
+#ifdef _TIM8\r
+ #define TIM8 ((TIM_TypeDef *) TIM8_BASE)\r
+#endif /*_TIM8 */\r
+\r
+#ifdef _USART1\r
+ #define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#endif /*_USART1 */\r
+\r
+#ifdef _ADC3\r
+ #define ADC3 ((ADC_TypeDef *) ADC3_BASE)\r
+#endif /*_ADC3 */\r
+\r
+#ifdef _SDIO\r
+ #define SDIO ((SDIO_TypeDef *) SDIO_BASE)\r
+#endif /*_SDIO */\r
+\r
+#ifdef _DMA\r
+ #define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
+ #define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
+#endif /*_DMA */\r
+\r
+#ifdef _DMA1_Channel1\r
+ #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\r
+#endif /*_DMA1_Channel1 */\r
+\r
+#ifdef _DMA1_Channel2\r
+ #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\r
+#endif /*_DMA1_Channel2 */\r
+\r
+#ifdef _DMA1_Channel3\r
+ #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\r
+#endif /*_DMA1_Channel3 */\r
+\r
+#ifdef _DMA1_Channel4\r
+ #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\r
+#endif /*_DMA1_Channel4 */\r
+\r
+#ifdef _DMA1_Channel5\r
+ #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\r
+#endif /*_DMA1_Channel5 */\r
+\r
+#ifdef _DMA1_Channel6\r
+ #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\r
+#endif /*_DMA1_Channel6 */\r
+\r
+#ifdef _DMA1_Channel7\r
+ #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)\r
+#endif /*_DMA1_Channel7 */\r
+\r
+#ifdef _DMA2_Channel1\r
+ #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)\r
+#endif /*_DMA2_Channel1 */\r
+\r
+#ifdef _DMA2_Channel2\r
+ #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)\r
+#endif /*_DMA2_Channel2 */\r
+\r
+#ifdef _DMA2_Channel3\r
+ #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)\r
+#endif /*_DMA2_Channel3 */\r
+\r
+#ifdef _DMA2_Channel4\r
+ #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)\r
+#endif /*_DMA2_Channel4 */\r
+\r
+#ifdef _DMA2_Channel5\r
+ #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)\r
+#endif /*_DMA2_Channel5 */\r
+\r
+#ifdef _RCC\r
+ #define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#endif /*_RCC */\r
+\r
+#ifdef _CRC\r
+ #define CRC ((CRC_TypeDef *) CRC_BASE)\r
+#endif /*_CRC */\r
+\r
+#ifdef _FLASH\r
+ #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
+ #define OB ((OB_TypeDef *) OB_BASE) \r
+#endif /*_FLASH */\r
+\r
+#ifdef _FSMC\r
+ #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\r
+ #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\r
+ #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)\r
+ #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)\r
+ #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)\r
+#endif /*_FSMC */\r
+\r
+#ifdef _DBGMCU\r
+ #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+#endif /*_DBGMCU */\r
+\r
+#ifdef _SysTick\r
+ #define SysTick ((SysTick_TypeDef *) SysTick_BASE)\r
+#endif /*_SysTick */\r
+\r
+#ifdef _NVIC\r
+ #define NVIC ((NVIC_TypeDef *) NVIC_BASE)\r
+ #define SCB ((SCB_TypeDef *) SCB_BASE) \r
+#endif /*_NVIC */\r
+\r
+/*------------------------ Debug Mode ----------------------------------------*/\r
+#else /* DEBUG */\r
+#ifdef _TIM2\r
+ EXT TIM_TypeDef *TIM2;\r
+#endif /*_TIM2 */\r
+\r
+#ifdef _TIM3\r
+ EXT TIM_TypeDef *TIM3;\r
+#endif /*_TIM3 */\r
+\r
+#ifdef _TIM4\r
+ EXT TIM_TypeDef *TIM4;\r
+#endif /*_TIM4 */\r
+\r
+#ifdef _TIM5\r
+ EXT TIM_TypeDef *TIM5;\r
+#endif /*_TIM5 */\r
+\r
+#ifdef _TIM6\r
+ EXT TIM_TypeDef *TIM6;\r
+#endif /*_TIM6 */\r
+\r
+#ifdef _TIM7\r
+ EXT TIM_TypeDef *TIM7;\r
+#endif /*_TIM7 */\r
+\r
+#ifdef _RTC\r
+ EXT RTC_TypeDef *RTC;\r
+#endif /*_RTC */\r
+\r
+#ifdef _WWDG\r
+ EXT WWDG_TypeDef *WWDG;\r
+#endif /*_WWDG */\r
+\r
+#ifdef _IWDG\r
+ EXT IWDG_TypeDef *IWDG;\r
+#endif /*_IWDG */\r
+\r
+#ifdef _SPI2\r
+ EXT SPI_TypeDef *SPI2;\r
+#endif /*_SPI2 */\r
+\r
+#ifdef _SPI3\r
+ EXT SPI_TypeDef *SPI3;\r
+#endif /*_SPI3 */\r
+\r
+#ifdef _USART2\r
+ EXT USART_TypeDef *USART2;\r
+#endif /*_USART2 */\r
+\r
+#ifdef _USART3\r
+ EXT USART_TypeDef *USART3;\r
+#endif /*_USART3 */\r
+\r
+#ifdef _UART4\r
+ EXT USART_TypeDef *UART4;\r
+#endif /*_UART4 */\r
+\r
+#ifdef _UART5\r
+ EXT USART_TypeDef *UART5;\r
+#endif /*_UART5 */\r
+\r
+#ifdef _I2C1\r
+ EXT I2C_TypeDef *I2C1;\r
+#endif /*_I2C1 */\r
+\r
+#ifdef _I2C2\r
+ EXT I2C_TypeDef *I2C2;\r
+#endif /*_I2C2 */\r
+\r
+#ifdef _CAN\r
+ EXT CAN_TypeDef *CAN;\r
+#endif /*_CAN */\r
+\r
+#ifdef _BKP\r
+ EXT BKP_TypeDef *BKP;\r
+#endif /*_BKP */\r
+\r
+#ifdef _PWR\r
+ EXT PWR_TypeDef *PWR;\r
+#endif /*_PWR */\r
+\r
+#ifdef _DAC\r
+ EXT DAC_TypeDef *DAC;\r
+#endif /*_DAC */\r
+\r
+#ifdef _AFIO\r
+ EXT AFIO_TypeDef *AFIO;\r
+#endif /*_AFIO */\r
+\r
+#ifdef _EXTI\r
+ EXT EXTI_TypeDef *EXTI;\r
+#endif /*_EXTI */\r
+\r
+#ifdef _GPIOA\r
+ EXT GPIO_TypeDef *GPIOA;\r
+#endif /*_GPIOA */\r
+\r
+#ifdef _GPIOB\r
+ EXT GPIO_TypeDef *GPIOB;\r
+#endif /*_GPIOB */\r
+\r
+#ifdef _GPIOC\r
+ EXT GPIO_TypeDef *GPIOC;\r
+#endif /*_GPIOC */\r
+\r
+#ifdef _GPIOD\r
+ EXT GPIO_TypeDef *GPIOD;\r
+#endif /*_GPIOD */\r
+\r
+#ifdef _GPIOE\r
+ EXT GPIO_TypeDef *GPIOE;\r
+#endif /*_GPIOE */\r
+\r
+#ifdef _GPIOF\r
+ EXT GPIO_TypeDef *GPIOF;\r
+#endif /*_GPIOF */\r
+\r
+#ifdef _GPIOG\r
+ EXT GPIO_TypeDef *GPIOG;\r
+#endif /*_GPIOG */\r
+\r
+#ifdef _ADC1\r
+ EXT ADC_TypeDef *ADC1;\r
+#endif /*_ADC1 */\r
+\r
+#ifdef _ADC2\r
+ EXT ADC_TypeDef *ADC2;\r
+#endif /*_ADC2 */\r
+\r
+#ifdef _TIM1\r
+ EXT TIM_TypeDef *TIM1;\r
+#endif /*_TIM1 */\r
+\r
+#ifdef _SPI1\r
+ EXT SPI_TypeDef *SPI1;\r
+#endif /*_SPI1 */\r
+\r
+#ifdef _TIM8\r
+ EXT TIM_TypeDef *TIM8;\r
+#endif /*_TIM8 */\r
+\r
+#ifdef _USART1\r
+ EXT USART_TypeDef *USART1;\r
+#endif /*_USART1 */\r
+\r
+#ifdef _ADC3\r
+ EXT ADC_TypeDef *ADC3;\r
+#endif /*_ADC3 */\r
+\r
+#ifdef _SDIO\r
+ EXT SDIO_TypeDef *SDIO;\r
+#endif /*_SDIO */\r
+\r
+#ifdef _DMA\r
+ EXT DMA_TypeDef *DMA1;\r
+ EXT DMA_TypeDef *DMA2;\r
+#endif /*_DMA */\r
+\r
+#ifdef _DMA1_Channel1\r
+ EXT DMA_Channel_TypeDef *DMA1_Channel1;\r
+#endif /*_DMA1_Channel1 */\r
+\r
+#ifdef _DMA1_Channel2\r
+ EXT DMA_Channel_TypeDef *DMA1_Channel2;\r
+#endif /*_DMA1_Channel2 */\r
+\r
+#ifdef _DMA1_Channel3\r
+ EXT DMA_Channel_TypeDef *DMA1_Channel3;\r
+#endif /*_DMA1_Channel3 */\r
+\r
+#ifdef _DMA1_Channel4\r
+ EXT DMA_Channel_TypeDef *DMA1_Channel4;\r
+#endif /*_DMA1_Channel4 */\r
+\r
+#ifdef _DMA1_Channel5\r
+ EXT DMA_Channel_TypeDef *DMA1_Channel5;\r
+#endif /*_DMA1_Channel5 */\r
+\r
+#ifdef _DMA1_Channel6\r
+ EXT DMA_Channel_TypeDef *DMA1_Channel6;\r
+#endif /*_DMA1_Channel6 */\r
+\r
+#ifdef _DMA1_Channel7\r
+ EXT DMA_Channel_TypeDef *DMA1_Channel7;\r
+#endif /*_DMA1_Channel7 */\r
+\r
+#ifdef _DMA2_Channel1\r
+ EXT DMA_Channel_TypeDef *DMA2_Channel1;\r
+#endif /*_DMA2_Channel1 */\r
+\r
+#ifdef _DMA2_Channel2\r
+ EXT DMA_Channel_TypeDef *DMA2_Channel2;\r
+#endif /*_DMA2_Channel2 */\r
+\r
+#ifdef _DMA2_Channel3\r
+ EXT DMA_Channel_TypeDef *DMA2_Channel3;\r
+#endif /*_DMA2_Channel3 */\r
+\r
+#ifdef _DMA2_Channel4\r
+ EXT DMA_Channel_TypeDef *DMA2_Channel4;\r
+#endif /*_DMA2_Channel4 */\r
+\r
+#ifdef _DMA2_Channel5\r
+ EXT DMA_Channel_TypeDef *DMA2_Channel5;\r
+#endif /*_DMA2_Channel5 */\r
+\r
+#ifdef _RCC\r
+ EXT RCC_TypeDef *RCC;\r
+#endif /*_RCC */\r
+\r
+#ifdef _CRC\r
+ EXT CRC_TypeDef *CRC;\r
+#endif /*_CRC */\r
+\r
+#ifdef _FLASH\r
+ EXT FLASH_TypeDef *FLASH;\r
+ EXT OB_TypeDef *OB; \r
+#endif /*_FLASH */\r
+\r
+#ifdef _FSMC\r
+ EXT FSMC_Bank1_TypeDef *FSMC_Bank1;\r
+ EXT FSMC_Bank1E_TypeDef *FSMC_Bank1E;\r
+ EXT FSMC_Bank2_TypeDef *FSMC_Bank2;\r
+ EXT FSMC_Bank3_TypeDef *FSMC_Bank3;\r
+ EXT FSMC_Bank4_TypeDef *FSMC_Bank4;\r
+#endif /*_FSMC */\r
+\r
+#ifdef _DBGMCU\r
+ EXT DBGMCU_TypeDef *DBGMCU;\r
+#endif /*_DBGMCU */\r
+\r
+#ifdef _SysTick\r
+ EXT SysTick_TypeDef *SysTick;\r
+#endif /*_SysTick */\r
+\r
+#ifdef _NVIC\r
+ EXT NVIC_TypeDef *NVIC;\r
+ EXT SCB_TypeDef *SCB;\r
+#endif /*_NVIC */\r
+\r
+#endif /* DEBUG */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+#endif /* __STM32F10x_MAP_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_nvic.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* NVIC firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_NVIC_H\r
+#define __STM32F10x_NVIC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* NVIC Init Structure definition */\r
+typedef struct\r
+{\r
+ u8 NVIC_IRQChannel;\r
+ u8 NVIC_IRQChannelPreemptionPriority;\r
+ u8 NVIC_IRQChannelSubPriority;\r
+ FunctionalState NVIC_IRQChannelCmd;\r
+} NVIC_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* IRQ Channels --------------------------------------------------------------*/\r
+#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */\r
+#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */\r
+#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */\r
+#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */\r
+#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */\r
+#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */\r
+#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */\r
+#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */\r
+#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */\r
+#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */\r
+#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */\r
+#define DMA1_Channel1_IRQChannel ((u8)0x0B) /* DMA1 Channel 1 global Interrupt */\r
+#define DMA1_Channel2_IRQChannel ((u8)0x0C) /* DMA1 Channel 2 global Interrupt */\r
+#define DMA1_Channel3_IRQChannel ((u8)0x0D) /* DMA1 Channel 3 global Interrupt */\r
+#define DMA1_Channel4_IRQChannel ((u8)0x0E) /* DMA1 Channel 4 global Interrupt */\r
+#define DMA1_Channel5_IRQChannel ((u8)0x0F) /* DMA1 Channel 5 global Interrupt */\r
+#define DMA1_Channel6_IRQChannel ((u8)0x10) /* DMA1 Channel 6 global Interrupt */\r
+#define DMA1_Channel7_IRQChannel ((u8)0x11) /* DMA1 Channel 7 global Interrupt */\r
+#define ADC1_2_IRQChannel ((u8)0x12) /* ADC1 et ADC2 global Interrupt */\r
+#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */\r
+#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */\r
+#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */\r
+#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */\r
+#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */\r
+#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */\r
+#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */\r
+#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */\r
+#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */\r
+#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */\r
+#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */\r
+#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */\r
+#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */\r
+#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */\r
+#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */\r
+#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */\r
+#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */\r
+#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */\r
+#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */\r
+#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */\r
+#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */\r
+#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */\r
+#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */\r
+#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */\r
+#define TIM8_BRK_IRQChannel ((u8)0x2B) /* TIM8 Break Interrupt */\r
+#define TIM8_UP_IRQChannel ((u8)0x2C) /* TIM8 Update Interrupt */\r
+#define TIM8_TRG_COM_IRQChannel ((u8)0x2D) /* TIM8 Trigger and Commutation Interrupt */\r
+#define TIM8_CC_IRQChannel ((u8)0x2E) /* TIM8 Capture Compare Interrupt */\r
+#define ADC3_IRQChannel ((u8)0x2F) /* ADC3 global Interrupt */\r
+#define FSMC_IRQChannel ((u8)0x30) /* FSMC global Interrupt */\r
+#define SDIO_IRQChannel ((u8)0x31) /* SDIO global Interrupt */\r
+#define TIM5_IRQChannel ((u8)0x32) /* TIM5 global Interrupt */\r
+#define SPI3_IRQChannel ((u8)0x33) /* SPI3 global Interrupt */\r
+#define UART4_IRQChannel ((u8)0x34) /* UART4 global Interrupt */\r
+#define UART5_IRQChannel ((u8)0x35) /* UART5 global Interrupt */\r
+#define TIM6_IRQChannel ((u8)0x36) /* TIM6 global Interrupt */\r
+#define TIM7_IRQChannel ((u8)0x37) /* TIM7 global Interrupt */\r
+#define DMA2_Channel1_IRQChannel ((u8)0x38) /* DMA2 Channel 1 global Interrupt */\r
+#define DMA2_Channel2_IRQChannel ((u8)0x39) /* DMA2 Channel 2 global Interrupt */\r
+#define DMA2_Channel3_IRQChannel ((u8)0x3A) /* DMA2 Channel 3 global Interrupt */\r
+#define DMA2_Channel4_5_IRQChannel ((u8)0x3B) /* DMA2 Channel 4 and DMA2 Channel 5 global Interrupt */\r
+\r
+\r
+#define IS_NVIC_IRQ_CHANNEL(CHANNEL) (((CHANNEL) == WWDG_IRQChannel) || \\r
+ ((CHANNEL) == PVD_IRQChannel) || \\r
+ ((CHANNEL) == TAMPER_IRQChannel) || \\r
+ ((CHANNEL) == RTC_IRQChannel) || \\r
+ ((CHANNEL) == FLASH_IRQChannel) || \\r
+ ((CHANNEL) == RCC_IRQChannel) || \\r
+ ((CHANNEL) == EXTI0_IRQChannel) || \\r
+ ((CHANNEL) == EXTI1_IRQChannel) || \\r
+ ((CHANNEL) == EXTI2_IRQChannel) || \\r
+ ((CHANNEL) == EXTI3_IRQChannel) || \\r
+ ((CHANNEL) == EXTI4_IRQChannel) || \\r
+ ((CHANNEL) == DMA1_Channel1_IRQChannel) || \\r
+ ((CHANNEL) == DMA1_Channel2_IRQChannel) || \\r
+ ((CHANNEL) == DMA1_Channel3_IRQChannel) || \\r
+ ((CHANNEL) == DMA1_Channel4_IRQChannel) || \\r
+ ((CHANNEL) == DMA1_Channel5_IRQChannel) || \\r
+ ((CHANNEL) == DMA1_Channel6_IRQChannel) || \\r
+ ((CHANNEL) == DMA1_Channel7_IRQChannel) || \\r
+ ((CHANNEL) == ADC1_2_IRQChannel) || \\r
+ ((CHANNEL) == USB_HP_CAN_TX_IRQChannel) || \\r
+ ((CHANNEL) == USB_LP_CAN_RX0_IRQChannel) || \\r
+ ((CHANNEL) == CAN_RX1_IRQChannel) || \\r
+ ((CHANNEL) == CAN_SCE_IRQChannel) || \\r
+ ((CHANNEL) == EXTI9_5_IRQChannel) || \\r
+ ((CHANNEL) == TIM1_BRK_IRQChannel) || \\r
+ ((CHANNEL) == TIM1_UP_IRQChannel) || \\r
+ ((CHANNEL) == TIM1_TRG_COM_IRQChannel) || \\r
+ ((CHANNEL) == TIM1_CC_IRQChannel) || \\r
+ ((CHANNEL) == TIM2_IRQChannel) || \\r
+ ((CHANNEL) == TIM3_IRQChannel) || \\r
+ ((CHANNEL) == TIM4_IRQChannel) || \\r
+ ((CHANNEL) == I2C1_EV_IRQChannel) || \\r
+ ((CHANNEL) == I2C1_ER_IRQChannel) || \\r
+ ((CHANNEL) == I2C2_EV_IRQChannel) || \\r
+ ((CHANNEL) == I2C2_ER_IRQChannel) || \\r
+ ((CHANNEL) == SPI1_IRQChannel) || \\r
+ ((CHANNEL) == SPI2_IRQChannel) || \\r
+ ((CHANNEL) == USART1_IRQChannel) || \\r
+ ((CHANNEL) == USART2_IRQChannel) || \\r
+ ((CHANNEL) == USART3_IRQChannel) || \\r
+ ((CHANNEL) == EXTI15_10_IRQChannel) || \\r
+ ((CHANNEL) == RTCAlarm_IRQChannel) || \\r
+ ((CHANNEL) == USBWakeUp_IRQChannel) || \\r
+ ((CHANNEL) == TIM8_BRK_IRQChannel) || \\r
+ ((CHANNEL) == TIM8_UP_IRQChannel) || \\r
+ ((CHANNEL) == TIM8_TRG_COM_IRQChannel) || \\r
+ ((CHANNEL) == TIM8_CC_IRQChannel) || \\r
+ ((CHANNEL) == ADC3_IRQChannel) || \\r
+ ((CHANNEL) == FSMC_IRQChannel) || \\r
+ ((CHANNEL) == SDIO_IRQChannel) || \\r
+ ((CHANNEL) == TIM5_IRQChannel) || \\r
+ ((CHANNEL) == SPI3_IRQChannel) || \\r
+ ((CHANNEL) == UART4_IRQChannel) || \\r
+ ((CHANNEL) == UART5_IRQChannel) || \\r
+ ((CHANNEL) == TIM6_IRQChannel) || \\r
+ ((CHANNEL) == TIM7_IRQChannel) || \\r
+ ((CHANNEL) == DMA2_Channel1_IRQChannel) || \\r
+ ((CHANNEL) == DMA2_Channel2_IRQChannel) || \\r
+ ((CHANNEL) == DMA2_Channel3_IRQChannel) || \\r
+ ((CHANNEL) == DMA2_Channel4_5_IRQChannel))\r
+\r
+\r
+/* System Handlers -----------------------------------------------------------*/\r
+#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */\r
+#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */\r
+#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */\r
+#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */\r
+#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */\r
+#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */\r
+#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */\r
+#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */\r
+#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */\r
+\r
+#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \\r
+ ((HANDLER) == SystemHandler_BusFault) || \\r
+ ((HANDLER) == SystemHandler_UsageFault))\r
+\r
+#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \\r
+ ((HANDLER) == SystemHandler_BusFault) || \\r
+ ((HANDLER) == SystemHandler_UsageFault) || \\r
+ ((HANDLER) == SystemHandler_SVCall) || \\r
+ ((HANDLER) == SystemHandler_DebugMonitor) || \\r
+ ((HANDLER) == SystemHandler_PSV) || \\r
+ ((HANDLER) == SystemHandler_SysTick))\r
+\r
+#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \\r
+ ((HANDLER) == SystemHandler_BusFault) || \\r
+ ((HANDLER) == SystemHandler_SVCall))\r
+\r
+#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_NMI) || \\r
+ ((HANDLER) == SystemHandler_PSV) || \\r
+ ((HANDLER) == SystemHandler_SysTick))\r
+\r
+#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_PSV) || \\r
+ ((HANDLER) == SystemHandler_SysTick))\r
+\r
+#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \\r
+ ((HANDLER) == SystemHandler_BusFault) || \\r
+ ((HANDLER) == SystemHandler_UsageFault) || \\r
+ ((HANDLER) == SystemHandler_SVCall) || \\r
+ ((HANDLER) == SystemHandler_DebugMonitor) || \\r
+ ((HANDLER) == SystemHandler_PSV) || \\r
+ ((HANDLER) == SystemHandler_SysTick))\r
+\r
+#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_HardFault) || \\r
+ ((HANDLER) == SystemHandler_MemoryManage) || \\r
+ ((HANDLER) == SystemHandler_BusFault) || \\r
+ ((HANDLER) == SystemHandler_UsageFault) || \\r
+ ((HANDLER) == SystemHandler_DebugMonitor)) \r
+\r
+#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \\r
+ ((HANDLER) == SystemHandler_BusFault))\r
+\r
+\r
+/* Vector Table Base ---------------------------------------------------------*/\r
+#define NVIC_VectTab_RAM ((u32)0x20000000)\r
+#define NVIC_VectTab_FLASH ((u32)0x08000000)\r
+\r
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \\r
+ ((VECTTAB) == NVIC_VectTab_FLASH))\r
+\r
+/* System Low Power ----------------------------------------------------------*/\r
+#define NVIC_LP_SEVONPEND ((u8)0x10)\r
+#define NVIC_LP_SLEEPDEEP ((u8)0x04)\r
+#define NVIC_LP_SLEEPONEXIT ((u8)0x02)\r
+\r
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\r
+ ((LP) == NVIC_LP_SLEEPDEEP) || \\r
+ ((LP) == NVIC_LP_SLEEPONEXIT))\r
+\r
+/* Preemption Priority Group -------------------------------------------------*/\r
+#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority\r
+ 4 bits for subpriority */\r
+#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority\r
+ 3 bits for subpriority */\r
+#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority\r
+ 2 bits for subpriority */\r
+#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority\r
+ 1 bits for subpriority */\r
+#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority\r
+ 0 bits for subpriority */\r
+\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \\r
+ ((GROUP) == NVIC_PriorityGroup_1) || \\r
+ ((GROUP) == NVIC_PriorityGroup_2) || \\r
+ ((GROUP) == NVIC_PriorityGroup_3) || \\r
+ ((GROUP) == NVIC_PriorityGroup_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)\r
+#define IS_NVIC_BASE_PRI(PRI) ((PRI) < 0x10)\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void NVIC_DeInit(void);\r
+void NVIC_SCBDeInit(void);\r
+void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup);\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
+void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct);\r
+void NVIC_SETPRIMASK(void);\r
+void NVIC_RESETPRIMASK(void);\r
+void NVIC_SETFAULTMASK(void);\r
+void NVIC_RESETFAULTMASK(void);\r
+void NVIC_BASEPRICONFIG(u32 NewPriority);\r
+u32 NVIC_GetBASEPRI(void);\r
+u16 NVIC_GetCurrentPendingIRQChannel(void);\r
+ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel);\r
+void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel);\r
+void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel);\r
+u16 NVIC_GetCurrentActiveHandler(void);\r
+ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel);\r
+u32 NVIC_GetCPUID(void);\r
+void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);\r
+void NVIC_GenerateSystemReset(void);\r
+void NVIC_GenerateCoreReset(void);\r
+void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState);\r
+void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState);\r
+void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,\r
+ u8 SystemHandlerSubPriority);\r
+ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler);\r
+void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler);\r
+void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler);\r
+ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler);\r
+u32 NVIC_GetFaultHandlerSources(u32 SystemHandler);\r
+u32 NVIC_GetFaultAddress(u32 SystemHandler);\r
+\r
+#endif /* __STM32F10x_NVIC_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_pwr.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* PWR firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_PWR_H\r
+#define __STM32F10x_PWR_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* PVD detection level */\r
+#define PWR_PVDLevel_2V2 ((u32)0x00000000)\r
+#define PWR_PVDLevel_2V3 ((u32)0x00000020)\r
+#define PWR_PVDLevel_2V4 ((u32)0x00000040)\r
+#define PWR_PVDLevel_2V5 ((u32)0x00000060)\r
+#define PWR_PVDLevel_2V6 ((u32)0x00000080)\r
+#define PWR_PVDLevel_2V7 ((u32)0x000000A0)\r
+#define PWR_PVDLevel_2V8 ((u32)0x000000C0)\r
+#define PWR_PVDLevel_2V9 ((u32)0x000000E0)\r
+\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \\r
+ ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \\r
+ ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \\r
+ ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))\r
+\r
+/* Regulator state is STOP mode */\r
+#define PWR_Regulator_ON ((u32)0x00000000)\r
+#define PWR_Regulator_LowPower ((u32)0x00000001)\r
+\r
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \\r
+ ((REGULATOR) == PWR_Regulator_LowPower))\r
+\r
+/* STOP mode entry */\r
+#define PWR_STOPEntry_WFI ((u8)0x01)\r
+#define PWR_STOPEntry_WFE ((u8)0x02)\r
+\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))\r
+ \r
+/* PWR Flag */\r
+#define PWR_FLAG_WU ((u32)0x00000001)\r
+#define PWR_FLAG_SB ((u32)0x00000002)\r
+#define PWR_FLAG_PVDO ((u32)0x00000004)\r
+\r
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \\r
+ ((FLAG) == PWR_FLAG_PVDO))\r
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void PWR_DeInit(void);\r
+void PWR_BackupAccessCmd(FunctionalState NewState);\r
+void PWR_PVDCmd(FunctionalState NewState);\r
+void PWR_PVDLevelConfig(u32 PWR_PVDLevel);\r
+void PWR_WakeUpPinCmd(FunctionalState NewState);\r
+void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry);\r
+void PWR_EnterSTANDBYMode(void);\r
+FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG);\r
+void PWR_ClearFlag(u32 PWR_FLAG);\r
+\r
+#endif /* __STM32F10x_PWR_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_rcc.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* RCC firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_RCC_H\r
+#define __STM32F10x_RCC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ u32 SYSCLK_Frequency;\r
+ u32 HCLK_Frequency;\r
+ u32 PCLK1_Frequency;\r
+ u32 PCLK2_Frequency;\r
+ u32 ADCCLK_Frequency;\r
+}RCC_ClocksTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* HSE configuration */\r
+#define RCC_HSE_OFF ((u32)0x00000000)\r
+#define RCC_HSE_ON ((u32)0x00010000)\r
+#define RCC_HSE_Bypass ((u32)0x00040000)\r
+\r
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
+ ((HSE) == RCC_HSE_Bypass))\r
+\r
+/* PLL entry clock source */\r
+#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000)\r
+#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000)\r
+#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000)\r
+\r
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \\r
+ ((SOURCE) == RCC_PLLSource_HSE_Div1) || \\r
+ ((SOURCE) == RCC_PLLSource_HSE_Div2))\r
+\r
+/* PLL multiplication factor */\r
+#define RCC_PLLMul_2 ((u32)0x00000000)\r
+#define RCC_PLLMul_3 ((u32)0x00040000)\r
+#define RCC_PLLMul_4 ((u32)0x00080000)\r
+#define RCC_PLLMul_5 ((u32)0x000C0000)\r
+#define RCC_PLLMul_6 ((u32)0x00100000)\r
+#define RCC_PLLMul_7 ((u32)0x00140000)\r
+#define RCC_PLLMul_8 ((u32)0x00180000)\r
+#define RCC_PLLMul_9 ((u32)0x001C0000)\r
+#define RCC_PLLMul_10 ((u32)0x00200000)\r
+#define RCC_PLLMul_11 ((u32)0x00240000)\r
+#define RCC_PLLMul_12 ((u32)0x00280000)\r
+#define RCC_PLLMul_13 ((u32)0x002C0000)\r
+#define RCC_PLLMul_14 ((u32)0x00300000)\r
+#define RCC_PLLMul_15 ((u32)0x00340000)\r
+#define RCC_PLLMul_16 ((u32)0x00380000)\r
+\r
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \\r
+ ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \\r
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \\r
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \\r
+ ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \\r
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \\r
+ ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \\r
+ ((MUL) == RCC_PLLMul_16))\r
+\r
+/* System clock source */\r
+#define RCC_SYSCLKSource_HSI ((u32)0x00000000)\r
+#define RCC_SYSCLKSource_HSE ((u32)0x00000001)\r
+#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002)\r
+\r
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))\r
+\r
+/* AHB clock source */\r
+#define RCC_SYSCLK_Div1 ((u32)0x00000000)\r
+#define RCC_SYSCLK_Div2 ((u32)0x00000080)\r
+#define RCC_SYSCLK_Div4 ((u32)0x00000090)\r
+#define RCC_SYSCLK_Div8 ((u32)0x000000A0)\r
+#define RCC_SYSCLK_Div16 ((u32)0x000000B0)\r
+#define RCC_SYSCLK_Div64 ((u32)0x000000C0)\r
+#define RCC_SYSCLK_Div128 ((u32)0x000000D0)\r
+#define RCC_SYSCLK_Div256 ((u32)0x000000E0)\r
+#define RCC_SYSCLK_Div512 ((u32)0x000000F0)\r
+\r
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \\r
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \\r
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \\r
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \\r
+ ((HCLK) == RCC_SYSCLK_Div512))\r
+\r
+/* APB1/APB2 clock source */\r
+#define RCC_HCLK_Div1 ((u32)0x00000000)\r
+#define RCC_HCLK_Div2 ((u32)0x00000400)\r
+#define RCC_HCLK_Div4 ((u32)0x00000500)\r
+#define RCC_HCLK_Div8 ((u32)0x00000600)\r
+#define RCC_HCLK_Div16 ((u32)0x00000700)\r
+\r
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \\r
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \\r
+ ((PCLK) == RCC_HCLK_Div16))\r
+\r
+/* RCC Interrupt source */\r
+#define RCC_IT_LSIRDY ((u8)0x01)\r
+#define RCC_IT_LSERDY ((u8)0x02)\r
+#define RCC_IT_HSIRDY ((u8)0x04)\r
+#define RCC_IT_HSERDY ((u8)0x08)\r
+#define RCC_IT_PLLRDY ((u8)0x10)\r
+#define RCC_IT_CSS ((u8)0x80)\r
+\r
+#define IS_RCC_IT(IT) ((((IT) & (u8)0xE0) == 0x00) && ((IT) != 0x00))\r
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))\r
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (u8)0x60) == 0x00) && ((IT) != 0x00))\r
+\r
+/* USB clock source */\r
+#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00)\r
+#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01)\r
+\r
+#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \\r
+ ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))\r
+\r
+/* ADC clock source */\r
+#define RCC_PCLK2_Div2 ((u32)0x00000000)\r
+#define RCC_PCLK2_Div4 ((u32)0x00004000)\r
+#define RCC_PCLK2_Div6 ((u32)0x00008000)\r
+#define RCC_PCLK2_Div8 ((u32)0x0000C000)\r
+\r
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \\r
+ ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))\r
+\r
+/* LSE configuration */\r
+#define RCC_LSE_OFF ((u8)0x00)\r
+#define RCC_LSE_ON ((u8)0x01)\r
+#define RCC_LSE_Bypass ((u8)0x04)\r
+\r
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
+ ((LSE) == RCC_LSE_Bypass))\r
+\r
+/* RTC clock source */\r
+#define RCC_RTCCLKSource_LSE ((u32)0x00000100)\r
+#define RCC_RTCCLKSource_LSI ((u32)0x00000200)\r
+#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300)\r
+\r
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))\r
+\r
+/* AHB peripheral */\r
+#define RCC_AHBPeriph_DMA1 ((u32)0x00000001)\r
+#define RCC_AHBPeriph_DMA2 ((u32)0x00000002)\r
+#define RCC_AHBPeriph_SRAM ((u32)0x00000004)\r
+#define RCC_AHBPeriph_FLITF ((u32)0x00000010)\r
+#define RCC_AHBPeriph_CRC ((u32)0x00000040)\r
+#define RCC_AHBPeriph_FSMC ((u32)0x00000100)\r
+#define RCC_AHBPeriph_SDIO ((u32)0x00000400)\r
+\r
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/* APB2 peripheral */\r
+#define RCC_APB2Periph_AFIO ((u32)0x00000001)\r
+#define RCC_APB2Periph_GPIOA ((u32)0x00000004)\r
+#define RCC_APB2Periph_GPIOB ((u32)0x00000008)\r
+#define RCC_APB2Periph_GPIOC ((u32)0x00000010)\r
+#define RCC_APB2Periph_GPIOD ((u32)0x00000020)\r
+#define RCC_APB2Periph_GPIOE ((u32)0x00000040)\r
+#define RCC_APB2Periph_GPIOF ((u32)0x00000080)\r
+#define RCC_APB2Periph_GPIOG ((u32)0x00000100)\r
+#define RCC_APB2Periph_ADC1 ((u32)0x00000200)\r
+#define RCC_APB2Periph_ADC2 ((u32)0x00000400)\r
+#define RCC_APB2Periph_TIM1 ((u32)0x00000800)\r
+#define RCC_APB2Periph_SPI1 ((u32)0x00001000)\r
+#define RCC_APB2Periph_TIM8 ((u32)0x00002000)\r
+#define RCC_APB2Periph_USART1 ((u32)0x00004000)\r
+#define RCC_APB2Periph_ADC3 ((u32)0x00008000)\r
+#define RCC_APB2Periph_ALL ((u32)0x0000FFFD)\r
+\r
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/* APB1 peripheral */\r
+#define RCC_APB1Periph_TIM2 ((u32)0x00000001)\r
+#define RCC_APB1Periph_TIM3 ((u32)0x00000002)\r
+#define RCC_APB1Periph_TIM4 ((u32)0x00000004)\r
+#define RCC_APB1Periph_TIM5 ((u32)0x00000008)\r
+#define RCC_APB1Periph_TIM6 ((u32)0x00000010)\r
+#define RCC_APB1Periph_TIM7 ((u32)0x00000020)\r
+#define RCC_APB1Periph_WWDG ((u32)0x00000800)\r
+#define RCC_APB1Periph_SPI2 ((u32)0x00004000)\r
+#define RCC_APB1Periph_SPI3 ((u32)0x00008000)\r
+#define RCC_APB1Periph_USART2 ((u32)0x00020000)\r
+#define RCC_APB1Periph_USART3 ((u32)0x00040000)\r
+#define RCC_APB1Periph_UART4 ((u32)0x00080000)\r
+#define RCC_APB1Periph_UART5 ((u32)0x00100000)\r
+#define RCC_APB1Periph_I2C1 ((u32)0x00200000)\r
+#define RCC_APB1Periph_I2C2 ((u32)0x00400000)\r
+#define RCC_APB1Periph_USB ((u32)0x00800000)\r
+#define RCC_APB1Periph_CAN ((u32)0x02000000)\r
+#define RCC_APB1Periph_BKP ((u32)0x08000000)\r
+#define RCC_APB1Periph_PWR ((u32)0x10000000)\r
+#define RCC_APB1Periph_DAC ((u32)0x20000000)\r
+#define RCC_APB1Periph_ALL ((u32)0x3AFEC83F)\r
+\r
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/* Clock source to output on MCO pin */\r
+#define RCC_MCO_NoClock ((u8)0x00)\r
+#define RCC_MCO_SYSCLK ((u8)0x04)\r
+#define RCC_MCO_HSI ((u8)0x05)\r
+#define RCC_MCO_HSE ((u8)0x06)\r
+#define RCC_MCO_PLLCLK_Div2 ((u8)0x07)\r
+\r
+#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \\r
+ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \\r
+ ((MCO) == RCC_MCO_PLLCLK_Div2))\r
+\r
+/* RCC Flag */\r
+#define RCC_FLAG_HSIRDY ((u8)0x20)\r
+#define RCC_FLAG_HSERDY ((u8)0x31)\r
+#define RCC_FLAG_PLLRDY ((u8)0x39)\r
+#define RCC_FLAG_LSERDY ((u8)0x41)\r
+#define RCC_FLAG_LSIRDY ((u8)0x61)\r
+#define RCC_FLAG_PINRST ((u8)0x7A)\r
+#define RCC_FLAG_PORRST ((u8)0x7B)\r
+#define RCC_FLAG_SFTRST ((u8)0x7C)\r
+#define RCC_FLAG_IWDGRST ((u8)0x7D)\r
+#define RCC_FLAG_WWDGRST ((u8)0x7E)\r
+#define RCC_FLAG_LPWRRST ((u8)0x7F)\r
+\r
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \\r
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \\r
+ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \\r
+ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \\r
+ ((FLAG) == RCC_FLAG_LPWRRST))\r
+\r
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void RCC_DeInit(void);\r
+void RCC_HSEConfig(u32 RCC_HSE);\r
+ErrorStatus RCC_WaitForHSEStartUp(void);\r
+void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue);\r
+void RCC_HSICmd(FunctionalState NewState);\r
+void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul);\r
+void RCC_PLLCmd(FunctionalState NewState);\r
+void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource);\r
+u8 RCC_GetSYSCLKSource(void);\r
+void RCC_HCLKConfig(u32 RCC_SYSCLK);\r
+void RCC_PCLK1Config(u32 RCC_HCLK);\r
+void RCC_PCLK2Config(u32 RCC_HCLK);\r
+void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState);\r
+void RCC_USBCLKConfig(u32 RCC_USBCLKSource);\r
+void RCC_ADCCLKConfig(u32 RCC_PCLK2);\r
+void RCC_LSEConfig(u8 RCC_LSE);\r
+void RCC_LSICmd(FunctionalState NewState);\r
+void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource);\r
+void RCC_RTCCLKCmd(FunctionalState NewState);\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);\r
+void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState);\r
+void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState);\r
+void RCC_BackupResetCmd(FunctionalState NewState);\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);\r
+void RCC_MCOConfig(u8 RCC_MCO);\r
+FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG);\r
+void RCC_ClearFlag(void);\r
+ITStatus RCC_GetITStatus(u8 RCC_IT);\r
+void RCC_ClearITPendingBit(u8 RCC_IT);\r
+\r
+#endif /* __STM32F10x_RCC_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_rtc.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* RTC firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_RTC_H\r
+#define __STM32F10x_RTC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* RTC interrupts define -----------------------------------------------------*/\r
+#define RTC_IT_OW ((u16)0x0004) /* Overflow interrupt */\r
+#define RTC_IT_ALR ((u16)0x0002) /* Alarm interrupt */\r
+#define RTC_IT_SEC ((u16)0x0001) /* Second interrupt */\r
+\r
+#define IS_RTC_IT(IT) ((((IT) & (u16)0xFFF8) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \\r
+ ((IT) == RTC_IT_SEC))\r
+ \r
+/* RTC interrupts flags ------------------------------------------------------*/\r
+#define RTC_FLAG_RTOFF ((u16)0x0020) /* RTC Operation OFF flag */\r
+#define RTC_FLAG_RSF ((u16)0x0008) /* Registers Synchronized flag */\r
+#define RTC_FLAG_OW ((u16)0x0004) /* Overflow flag */\r
+#define RTC_FLAG_ALR ((u16)0x0002) /* Alarm flag */\r
+#define RTC_FLAG_SEC ((u16)0x0001) /* Second flag */\r
+\r
+#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0xFFF0) == 0x00) && ((FLAG) != 0x00))\r
+\r
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \\r
+ ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \\r
+ ((FLAG) == RTC_FLAG_SEC))\r
+\r
+#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState);\r
+void RTC_EnterConfigMode(void);\r
+void RTC_ExitConfigMode(void);\r
+u32 RTC_GetCounter(void);\r
+void RTC_SetCounter(u32 CounterValue);\r
+void RTC_SetPrescaler(u32 PrescalerValue);\r
+void RTC_SetAlarm(u32 AlarmValue);\r
+u32 RTC_GetDivider(void);\r
+void RTC_WaitForLastTask(void);\r
+void RTC_WaitForSynchro(void);\r
+FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG);\r
+void RTC_ClearFlag(u16 RTC_FLAG);\r
+ITStatus RTC_GetITStatus(u16 RTC_IT);\r
+void RTC_ClearITPendingBit(u16 RTC_IT);\r
+\r
+#endif /* __STM32F10x_RTC_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_sdio.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* SDIO firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_SDIO_H\r
+#define __STM32F10x_SDIO_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ u8 SDIO_ClockDiv;\r
+ u32 SDIO_ClockEdge;\r
+ u32 SDIO_ClockBypass;\r
+ u32 SDIO_ClockPowerSave;\r
+ u32 SDIO_BusWide;\r
+ u32 SDIO_HardwareFlowControl;\r
+} SDIO_InitTypeDef;\r
+\r
+typedef struct\r
+{\r
+ u32 SDIO_Argument;\r
+ u32 SDIO_CmdIndex;\r
+ u32 SDIO_Response;\r
+ u32 SDIO_Wait;\r
+ u32 SDIO_CPSM;\r
+} SDIO_CmdInitTypeDef;\r
+\r
+typedef struct\r
+{\r
+ u32 SDIO_DataTimeOut;\r
+ u32 SDIO_DataLength;\r
+ u32 SDIO_DataBlockSize;\r
+ u32 SDIO_TransferDir;\r
+ u32 SDIO_TransferMode;\r
+ u32 SDIO_DPSM;\r
+} SDIO_DataInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* SDIO Clock Edge -----------------------------------------------------------*/\r
+#define SDIO_ClockEdge_Rising ((u32)0x00000000)\r
+#define SDIO_ClockEdge_Falling ((u32)0x00002000)\r
+\r
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \\r
+ ((EDGE) == SDIO_ClockEdge_Falling))\r
+/* SDIO Clock Bypass ----------------------------------------------------------*/ \r
+#define SDIO_ClockBypass_Disable ((u32)0x00000000)\r
+#define SDIO_ClockBypass_Enable ((u32)0x00000400) \r
+\r
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \\r
+ ((BYPASS) == SDIO_ClockBypass_Enable)) \r
+\r
+/* SDIO Clock Power Save ----------------------------------------------------*/ \r
+#define SDIO_ClockPowerSave_Disable ((u32)0x00000000)\r
+#define SDIO_ClockPowerSave_Enable ((u32)0x00000200) \r
+\r
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \\r
+ ((SAVE) == SDIO_ClockPowerSave_Enable))\r
+\r
+/* SDIO Bus Wide -------------------------------------------------------------*/\r
+#define SDIO_BusWide_1b ((u32)0x00000000)\r
+#define SDIO_BusWide_4b ((u32)0x00000800)\r
+#define SDIO_BusWide_8b ((u32)0x00001000)\r
+\r
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \\r
+ ((WIDE) == SDIO_BusWide_8b))\r
+ \r
+/* SDIO Hardware Flow Control -----------------------------------------------*/ \r
+#define SDIO_HardwareFlowControl_Disable ((u32)0x00000000)\r
+#define SDIO_HardwareFlowControl_Enable ((u32)0x00004000)\r
+\r
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \\r
+ ((CONTROL) == SDIO_HardwareFlowControl_Enable))\r
+ \r
+/* SDIO Power State ----------------------------------------------------------*/\r
+#define SDIO_PowerState_OFF ((u32)0x00000000)\r
+#define SDIO_PowerState_ON ((u32)0x00000003)\r
+\r
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) \r
+\r
+/* SDIO Interrupt soucres ----------------------------------------------------*/\r
+#define SDIO_IT_CCRCFAIL ((u32)0x00000001)\r
+#define SDIO_IT_DCRCFAIL ((u32)0x00000002)\r
+#define SDIO_IT_CTIMEOUT ((u32)0x00000004)\r
+#define SDIO_IT_DTIMEOUT ((u32)0x00000008)\r
+#define SDIO_IT_TXUNDERR ((u32)0x00000010)\r
+#define SDIO_IT_RXOVERR ((u32)0x00000020)\r
+#define SDIO_IT_CMDREND ((u32)0x00000040)\r
+#define SDIO_IT_CMDSENT ((u32)0x00000080)\r
+#define SDIO_IT_DATAEND ((u32)0x00000100)\r
+#define SDIO_IT_STBITERR ((u32)0x00000200)\r
+#define SDIO_IT_DBCKEND ((u32)0x00000400)\r
+#define SDIO_IT_CMDACT ((u32)0x00000800)\r
+#define SDIO_IT_TXACT ((u32)0x00001000)\r
+#define SDIO_IT_RXACT ((u32)0x00002000)\r
+#define SDIO_IT_TXFIFOHE ((u32)0x00004000)\r
+#define SDIO_IT_RXFIFOHF ((u32)0x00008000)\r
+#define SDIO_IT_TXFIFOF ((u32)0x00010000)\r
+#define SDIO_IT_RXFIFOF ((u32)0x00020000)\r
+#define SDIO_IT_TXFIFOE ((u32)0x00040000)\r
+#define SDIO_IT_RXFIFOE ((u32)0x00080000)\r
+#define SDIO_IT_TXDAVL ((u32)0x00100000)\r
+#define SDIO_IT_RXDAVL ((u32)0x00200000)\r
+#define SDIO_IT_SDIOIT ((u32)0x00400000)\r
+#define SDIO_IT_CEATAEND ((u32)0x00800000)\r
+\r
+#define IS_SDIO_IT(IT) ((((IT) & (u32)0xFF000000) == 0x00) && ((IT) != (u32)0x00))\r
+\r
+/* SDIO Command Index -------------------------------------------------------*/\r
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)\r
+\r
+/* SDIO Response Type --------------------------------------------------------*/\r
+#define SDIO_Response_No ((u32)0x00000000)\r
+#define SDIO_Response_Short ((u32)0x00000040)\r
+#define SDIO_Response_Long ((u32)0x000000C0)\r
+\r
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \\r
+ ((RESPONSE) == SDIO_Response_Short) || \\r
+ ((RESPONSE) == SDIO_Response_Long))\r
+\r
+/* SDIO Wait Interrupt State -------------------------------------------------*/\r
+#define SDIO_Wait_No ((u32)0x00000000) /* SDIO No Wait, TimeOut is enabled */\r
+#define SDIO_Wait_IT ((u32)0x00000100) /* SDIO Wait Interrupt Request */\r
+#define SDIO_Wait_Pend ((u32)0x00000200) /* SDIO Wait End of transfer */\r
+\r
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \\r
+ ((WAIT) == SDIO_Wait_Pend))\r
+\r
+/* SDIO CPSM State -----------------------------------------------------------*/\r
+#define SDIO_CPSM_Disable ((u32)0x00000000)\r
+#define SDIO_CPSM_Enable ((u32)0x00000400)\r
+\r
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))\r
+\r
+/* SDIO Response Registers ---------------------------------------------------*/\r
+#define SDIO_RESP1 ((u32)0x00000000)\r
+#define SDIO_RESP2 ((u32)0x00000004)\r
+#define SDIO_RESP3 ((u32)0x00000008)\r
+#define SDIO_RESP4 ((u32)0x0000000C)\r
+\r
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \\r
+ ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))\r
+\r
+/* SDIO Data Length ----------------------------------------------------------*/\r
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)\r
+\r
+/* SDIO Data Block Size ------------------------------------------------------*/\r
+#define SDIO_DataBlockSize_1b ((u32)0x00000000)\r
+#define SDIO_DataBlockSize_2b ((u32)0x00000010)\r
+#define SDIO_DataBlockSize_4b ((u32)0x00000020)\r
+#define SDIO_DataBlockSize_8b ((u32)0x00000030)\r
+#define SDIO_DataBlockSize_16b ((u32)0x00000040)\r
+#define SDIO_DataBlockSize_32b ((u32)0x00000050)\r
+#define SDIO_DataBlockSize_64b ((u32)0x00000060)\r
+#define SDIO_DataBlockSize_128b ((u32)0x00000070)\r
+#define SDIO_DataBlockSize_256b ((u32)0x00000080)\r
+#define SDIO_DataBlockSize_512b ((u32)0x00000090)\r
+#define SDIO_DataBlockSize_1024b ((u32)0x000000A0)\r
+#define SDIO_DataBlockSize_2048b ((u32)0x000000B0)\r
+#define SDIO_DataBlockSize_4096b ((u32)0x000000C0)\r
+#define SDIO_DataBlockSize_8192b ((u32)0x000000D0)\r
+#define SDIO_DataBlockSize_16384b ((u32)0x000000E0)\r
+\r
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_2b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_4b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_8b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_16b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_32b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_64b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_128b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_256b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_512b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_1024b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_2048b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_4096b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_8192b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_16384b)) \r
+\r
+/* SDIO Transfer Direction ---------------------------------------------------*/\r
+#define SDIO_TransferDir_ToCard ((u32)0x00000000)\r
+#define SDIO_TransferDir_ToSDIO ((u32)0x00000002)\r
+\r
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \\r
+ ((DIR) == SDIO_TransferDir_ToSDIO)) \r
+\r
+/* SDIO Transfer Type --------------------------------------------------------*/\r
+#define SDIO_TransferMode_Block ((u32)0x00000000)\r
+#define SDIO_TransferMode_Stream ((u32)0x00000004)\r
+\r
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \\r
+ ((MODE) == SDIO_TransferMode_Block)) \r
+\r
+/* SDIO DPSM State -----------------------------------------------------------*/\r
+#define SDIO_DPSM_Disable ((u32)0x00000000)\r
+#define SDIO_DPSM_Enable ((u32)0x00000001)\r
+\r
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))\r
+\r
+/* SDIO Flags ----------------------------------------------------------------*/\r
+#define SDIO_FLAG_CCRCFAIL ((u32)0x00000001)\r
+#define SDIO_FLAG_DCRCFAIL ((u32)0x00000002)\r
+#define SDIO_FLAG_CTIMEOUT ((u32)0x00000004)\r
+#define SDIO_FLAG_DTIMEOUT ((u32)0x00000008)\r
+#define SDIO_FLAG_TXUNDERR ((u32)0x00000010)\r
+#define SDIO_FLAG_RXOVERR ((u32)0x00000020)\r
+#define SDIO_FLAG_CMDREND ((u32)0x00000040)\r
+#define SDIO_FLAG_CMDSENT ((u32)0x00000080)\r
+#define SDIO_FLAG_DATAEND ((u32)0x00000100)\r
+#define SDIO_FLAG_STBITERR ((u32)0x00000200)\r
+#define SDIO_FLAG_DBCKEND ((u32)0x00000400)\r
+#define SDIO_FLAG_CMDACT ((u32)0x00000800)\r
+#define SDIO_FLAG_TXACT ((u32)0x00001000)\r
+#define SDIO_FLAG_RXACT ((u32)0x00002000)\r
+#define SDIO_FLAG_TXFIFOHE ((u32)0x00004000)\r
+#define SDIO_FLAG_RXFIFOHF ((u32)0x00008000)\r
+#define SDIO_FLAG_TXFIFOF ((u32)0x00010000)\r
+#define SDIO_FLAG_RXFIFOF ((u32)0x00020000)\r
+#define SDIO_FLAG_TXFIFOE ((u32)0x00040000)\r
+#define SDIO_FLAG_RXFIFOE ((u32)0x00080000)\r
+#define SDIO_FLAG_TXDAVL ((u32)0x00100000)\r
+#define SDIO_FLAG_RXDAVL ((u32)0x00200000)\r
+#define SDIO_FLAG_SDIOIT ((u32)0x00400000)\r
+#define SDIO_FLAG_CEATAEND ((u32)0x00800000)\r
+\r
+#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \\r
+ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \\r
+ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \\r
+ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \\r
+ ((FLAG) == SDIO_FLAG_TXUNDERR) || \\r
+ ((FLAG) == SDIO_FLAG_RXOVERR) || \\r
+ ((FLAG) == SDIO_FLAG_CMDREND) || \\r
+ ((FLAG) == SDIO_FLAG_CMDSENT) || \\r
+ ((FLAG) == SDIO_FLAG_DATAEND) || \\r
+ ((FLAG) == SDIO_FLAG_STBITERR) || \\r
+ ((FLAG) == SDIO_FLAG_DBCKEND) || \\r
+ ((FLAG) == SDIO_FLAG_CMDACT) || \\r
+ ((FLAG) == SDIO_FLAG_TXACT) || \\r
+ ((FLAG) == SDIO_FLAG_RXACT) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOF) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOF) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOE) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOE) || \\r
+ ((FLAG) == SDIO_FLAG_TXDAVL) || \\r
+ ((FLAG) == SDIO_FLAG_RXDAVL) || \\r
+ ((FLAG) == SDIO_FLAG_SDIOIT) || \\r
+ ((FLAG) == SDIO_FLAG_CEATAEND))\r
+\r
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFF3FF800) == 0x00) && ((FLAG) != (u32)0x00))\r
+\r
+#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \\r
+ ((IT) == SDIO_IT_DCRCFAIL) || \\r
+ ((IT) == SDIO_IT_CTIMEOUT) || \\r
+ ((IT) == SDIO_IT_DTIMEOUT) || \\r
+ ((IT) == SDIO_IT_TXUNDERR) || \\r
+ ((IT) == SDIO_IT_RXOVERR) || \\r
+ ((IT) == SDIO_IT_CMDREND) || \\r
+ ((IT) == SDIO_IT_CMDSENT) || \\r
+ ((IT) == SDIO_IT_DATAEND) || \\r
+ ((IT) == SDIO_IT_STBITERR) || \\r
+ ((IT) == SDIO_IT_DBCKEND) || \\r
+ ((IT) == SDIO_IT_CMDACT) || \\r
+ ((IT) == SDIO_IT_TXACT) || \\r
+ ((IT) == SDIO_IT_RXACT) || \\r
+ ((IT) == SDIO_IT_TXFIFOHE) || \\r
+ ((IT) == SDIO_IT_RXFIFOHF) || \\r
+ ((IT) == SDIO_IT_TXFIFOF) || \\r
+ ((IT) == SDIO_IT_RXFIFOF) || \\r
+ ((IT) == SDIO_IT_TXFIFOE) || \\r
+ ((IT) == SDIO_IT_RXFIFOE) || \\r
+ ((IT) == SDIO_IT_TXDAVL) || \\r
+ ((IT) == SDIO_IT_RXDAVL) || \\r
+ ((IT) == SDIO_IT_SDIOIT) || \\r
+ ((IT) == SDIO_IT_CEATAEND))\r
+\r
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (u32)0xFF3FF800) == 0x00) && ((IT) != (u32)0x00))\r
+ \r
+/* SDIO Read Wait Mode -------------------------------------------------------*/\r
+#define SDIO_ReadWaitMode_CLK ((u32)0x00000000)\r
+#define SDIO_ReadWaitMode_DATA2 ((u32)0x00000001)\r
+\r
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \\r
+ ((MODE) == SDIO_ReadWaitMode_DATA2)) \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void SDIO_DeInit(void);\r
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);\r
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);\r
+void SDIO_ClockCmd(FunctionalState NewState);\r
+void SDIO_SetPowerState(u32 SDIO_PowerState);\r
+u32 SDIO_GetPowerState(void);\r
+void SDIO_ITConfig(u32 SDIO_IT, FunctionalState NewState);\r
+void SDIO_DMACmd(FunctionalState NewState);\r
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);\r
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);\r
+u8 SDIO_GetCommandResponse(void);\r
+u32 SDIO_GetResponse(u32 SDIO_RESP);\r
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
+u32 SDIO_GetDataCounter(void);\r
+u32 SDIO_ReadData(void);\r
+void SDIO_WriteData(u32 Data);\r
+u32 SDIO_GetFIFOCount(void);\r
+void SDIO_StartSDIOReadWait(FunctionalState NewState);\r
+void SDIO_StopSDIOReadWait(FunctionalState NewState);\r
+void SDIO_SetSDIOReadWaitMode(u32 SDIO_ReadWaitMode);\r
+void SDIO_SetSDIOOperation(FunctionalState NewState);\r
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);\r
+void SDIO_CommandCompletionCmd(FunctionalState NewState);\r
+void SDIO_CEATAITCmd(FunctionalState NewState);\r
+void SDIO_SendCEATACmd(FunctionalState NewState);\r
+FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG);\r
+void SDIO_ClearFlag(u32 SDIO_FLAG);\r
+ITStatus SDIO_GetITStatus(u32 SDIO_IT);\r
+void SDIO_ClearITPendingBit(u32 SDIO_IT);\r
+\r
+#endif /* __STM32F10x_SDIO_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_spi.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* SPI firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_SPI_H\r
+#define __STM32F10x_SPI_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* SPI Init structure definition */\r
+typedef struct\r
+{\r
+ u16 SPI_Direction;\r
+ u16 SPI_Mode;\r
+ u16 SPI_DataSize;\r
+ u16 SPI_CPOL;\r
+ u16 SPI_CPHA;\r
+ u16 SPI_NSS;\r
+ u16 SPI_BaudRatePrescaler;\r
+ u16 SPI_FirstBit;\r
+ u16 SPI_CRCPolynomial;\r
+}SPI_InitTypeDef;\r
+\r
+/* I2S Init structure definition */\r
+typedef struct\r
+{\r
+ u16 I2S_Mode;\r
+ u16 I2S_Standard;\r
+ u16 I2S_DataFormat;\r
+ u16 I2S_MCLKOutput;\r
+ u16 I2S_AudioFreq;\r
+ u16 I2S_CPOL;\r
+}I2S_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+#define IS_SPI_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == SPI1_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == SPI2_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == SPI3_BASE))\r
+\r
+#define IS_SPI_23_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == SPI2_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == SPI3_BASE))\r
+\r
+/* SPI data direction mode */\r
+#define SPI_Direction_2Lines_FullDuplex ((u16)0x0000)\r
+#define SPI_Direction_2Lines_RxOnly ((u16)0x0400)\r
+#define SPI_Direction_1Line_Rx ((u16)0x8000)\r
+#define SPI_Direction_1Line_Tx ((u16)0xC000)\r
+\r
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \\r
+ ((MODE) == SPI_Direction_2Lines_RxOnly) || \\r
+ ((MODE) == SPI_Direction_1Line_Rx) || \\r
+ ((MODE) == SPI_Direction_1Line_Tx))\r
+\r
+/* SPI master/slave mode */\r
+#define SPI_Mode_Master ((u16)0x0104)\r
+#define SPI_Mode_Slave ((u16)0x0000)\r
+\r
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \\r
+ ((MODE) == SPI_Mode_Slave))\r
+\r
+/* SPI data size */\r
+#define SPI_DataSize_16b ((u16)0x0800)\r
+#define SPI_DataSize_8b ((u16)0x0000)\r
+\r
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \\r
+ ((DATASIZE) == SPI_DataSize_8b))\r
+\r
+/* SPI Clock Polarity */\r
+#define SPI_CPOL_Low ((u16)0x0000)\r
+#define SPI_CPOL_High ((u16)0x0002)\r
+\r
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \\r
+ ((CPOL) == SPI_CPOL_High))\r
+\r
+/* SPI Clock Phase */\r
+#define SPI_CPHA_1Edge ((u16)0x0000)\r
+#define SPI_CPHA_2Edge ((u16)0x0001)\r
+\r
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \\r
+ ((CPHA) == SPI_CPHA_2Edge))\r
+\r
+/* SPI Slave Select management */\r
+#define SPI_NSS_Soft ((u16)0x0200)\r
+#define SPI_NSS_Hard ((u16)0x0000)\r
+\r
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \\r
+ ((NSS) == SPI_NSS_Hard)) \r
+\r
+/* SPI BaudRate Prescaler */\r
+#define SPI_BaudRatePrescaler_2 ((u16)0x0000)\r
+#define SPI_BaudRatePrescaler_4 ((u16)0x0008)\r
+#define SPI_BaudRatePrescaler_8 ((u16)0x0010)\r
+#define SPI_BaudRatePrescaler_16 ((u16)0x0018)\r
+#define SPI_BaudRatePrescaler_32 ((u16)0x0020)\r
+#define SPI_BaudRatePrescaler_64 ((u16)0x0028)\r
+#define SPI_BaudRatePrescaler_128 ((u16)0x0030)\r
+#define SPI_BaudRatePrescaler_256 ((u16)0x0038)\r
+\r
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_256))\r
+\r
+/* SPI MSB/LSB transmission */\r
+#define SPI_FirstBit_MSB ((u16)0x0000)\r
+#define SPI_FirstBit_LSB ((u16)0x0080)\r
+\r
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \\r
+ ((BIT) == SPI_FirstBit_LSB))\r
+\r
+/* I2S Mode */\r
+#define I2S_Mode_SlaveTx ((u16)0x0000)\r
+#define I2S_Mode_SlaveRx ((u16)0x0100)\r
+#define I2S_Mode_MasterTx ((u16)0x0200)\r
+#define I2S_Mode_MasterRx ((u16)0x0300)\r
+\r
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \\r
+ ((MODE) == I2S_Mode_SlaveRx) || \\r
+ ((MODE) == I2S_Mode_MasterTx) || \\r
+ ((MODE) == I2S_Mode_MasterRx) )\r
+\r
+/* I2S Standard */\r
+#define I2S_Standard_Phillips ((u16)0x0000)\r
+#define I2S_Standard_MSB ((u16)0x0010)\r
+#define I2S_Standard_LSB ((u16)0x0020)\r
+#define I2S_Standard_PCMShort ((u16)0x0030)\r
+#define I2S_Standard_PCMLong ((u16)0x00B0)\r
+\r
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \\r
+ ((STANDARD) == I2S_Standard_MSB) || \\r
+ ((STANDARD) == I2S_Standard_LSB) || \\r
+ ((STANDARD) == I2S_Standard_PCMShort) || \\r
+ ((STANDARD) == I2S_Standard_PCMLong))\r
+\r
+/* I2S Data Format */\r
+#define I2S_DataFormat_16b ((u16)0x0000)\r
+#define I2S_DataFormat_16bextended ((u16)0x0001)\r
+#define I2S_DataFormat_24b ((u16)0x0003)\r
+#define I2S_DataFormat_32b ((u16)0x0005)\r
+\r
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \\r
+ ((FORMAT) == I2S_DataFormat_16bextended) || \\r
+ ((FORMAT) == I2S_DataFormat_24b) || \\r
+ ((FORMAT) == I2S_DataFormat_32b))\r
+\r
+/* I2S MCLK Output */ \r
+#define I2S_MCLKOutput_Enable ((u16)0x0200)\r
+#define I2S_MCLKOutput_Disable ((u16)0x0000)\r
+\r
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \\r
+ ((OUTPUT) == I2S_MCLKOutput_Disable))\r
+\r
+/* I2S Audio Frequency */\r
+#define I2S_AudioFreq_48k ((u16)48000)\r
+#define I2S_AudioFreq_44k ((u16)44100)\r
+#define I2S_AudioFreq_22k ((u16)22050)\r
+#define I2S_AudioFreq_16k ((u16)16000)\r
+#define I2S_AudioFreq_8k ((u16)8000)\r
+#define I2S_AudioFreq_Default ((u16)2)\r
+\r
+#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_48k) || \\r
+ ((FREQ) == I2S_AudioFreq_44k) || \\r
+ ((FREQ) == I2S_AudioFreq_22k) || \\r
+ ((FREQ) == I2S_AudioFreq_16k) || \\r
+ ((FREQ) == I2S_AudioFreq_8k) || \\r
+ ((FREQ) == I2S_AudioFreq_Default))\r
+\r
+/* I2S Clock Polarity */\r
+#define I2S_CPOL_Low ((u16)0x0000)\r
+#define I2S_CPOL_High ((u16)0x0008)\r
+\r
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \\r
+ ((CPOL) == I2S_CPOL_High))\r
+\r
+/* SPI_I2S DMA transfer requests */\r
+#define SPI_I2S_DMAReq_Tx ((u16)0x0002)\r
+#define SPI_I2S_DMAReq_Rx ((u16)0x0001)\r
+\r
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (u16)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))\r
+\r
+/* SPI NSS internal software mangement */\r
+#define SPI_NSSInternalSoft_Set ((u16)0x0100)\r
+#define SPI_NSSInternalSoft_Reset ((u16)0xFEFF)\r
+\r
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \\r
+ ((INTERNAL) == SPI_NSSInternalSoft_Reset))\r
+\r
+/* SPI CRC Transmit/Receive */\r
+#define SPI_CRC_Tx ((u8)0x00)\r
+#define SPI_CRC_Rx ((u8)0x01)\r
+\r
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))\r
+\r
+/* SPI direction transmit/receive */\r
+#define SPI_Direction_Rx ((u16)0xBFFF)\r
+#define SPI_Direction_Tx ((u16)0x4000)\r
+\r
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \\r
+ ((DIRECTION) == SPI_Direction_Tx))\r
+\r
+/* SPI_I2S interrupts definition */\r
+#define SPI_I2S_IT_TXE ((u8)0x71)\r
+#define SPI_I2S_IT_RXNE ((u8)0x60)\r
+#define SPI_I2S_IT_ERR ((u8)0x50)\r
+\r
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == SPI_I2S_IT_RXNE) || \\r
+ ((IT) == SPI_I2S_IT_ERR))\r
+\r
+#define SPI_I2S_IT_OVR ((u8)0x56)\r
+#define SPI_IT_MODF ((u8)0x55)\r
+#define SPI_IT_CRCERR ((u8)0x54)\r
+#define I2S_IT_UDR ((u8)0x53)\r
+\r
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_I2S_IT_OVR) || \\r
+ ((IT) == SPI_IT_MODF) || \\r
+ ((IT) == SPI_IT_CRCERR) || \\r
+ ((IT) == I2S_IT_UDR))\r
+\r
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \\r
+ ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))\r
+\r
+/* SPI_I2S flags definition */\r
+#define SPI_I2S_FLAG_RXNE ((u16)0x0001)\r
+#define SPI_I2S_FLAG_TXE ((u16)0x0002)\r
+#define I2S_FLAG_CHSIDE ((u16)0x0004)\r
+#define I2S_FLAG_UDR ((u16)0x0008)\r
+#define SPI_FLAG_CRCERR ((u16)0x0010)\r
+#define SPI_FLAG_MODF ((u16)0x0020)\r
+#define SPI_I2S_FLAG_OVR ((u16)0x0040)\r
+#define SPI_I2S_FLAG_BSY ((u16)0x0080)\r
+\r
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_OVR) || ((FLAG) == SPI_FLAG_MODF) || \\r
+ ((FLAG) == SPI_FLAG_CRCERR) || ((FLAG) == I2S_FLAG_UDR))\r
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \\r
+ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \\r
+ ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \\r
+ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))\r
+\r
+/* SPI CRC polynomial --------------------------------------------------------*/\r
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);\r
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);\r
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, u8 SPI_I2S_IT, FunctionalState NewState);\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, u16 SPI_I2S_DMAReq, FunctionalState NewState);\r
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, u16 Data);\r
+u16 SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft);\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize);\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC);\r
+u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction);\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG);\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG);\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_I2S_IT);\r
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_I2S_IT);\r
+\r
+#endif /*__STM32F10x_SPI_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_systick.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* SysTick firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_SYSTICK_H\r
+#define __STM32F10x_SYSTICK_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* SysTick clock source */\r
+#define SysTick_CLKSource_HCLK_Div8 ((u32)0xFFFFFFFB)\r
+#define SysTick_CLKSource_HCLK ((u32)0x00000004)\r
+\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\r
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r
+\r
+/* SysTick counter state */\r
+#define SysTick_Counter_Disable ((u32)0xFFFFFFFE)\r
+#define SysTick_Counter_Enable ((u32)0x00000001)\r
+#define SysTick_Counter_Clear ((u32)0x00000000)\r
+\r
+#define IS_SYSTICK_COUNTER(COUNTER) (((COUNTER) == SysTick_Counter_Disable) || \\r
+ ((COUNTER) == SysTick_Counter_Enable) || \\r
+ ((COUNTER) == SysTick_Counter_Clear))\r
+\r
+/* SysTick Flag */\r
+#define SysTick_FLAG_COUNT ((u32)0x00000010)\r
+#define SysTick_FLAG_SKEW ((u32)0x0000001E)\r
+#define SysTick_FLAG_NOREF ((u32)0x0000001F)\r
+\r
+#define IS_SYSTICK_FLAG(FLAG) (((FLAG) == SysTick_FLAG_COUNT) || \\r
+ ((FLAG) == SysTick_FLAG_SKEW) || \\r
+ ((FLAG) == SysTick_FLAG_NOREF))\r
+\r
+#define IS_SYSTICK_RELOAD(RELOAD) (((RELOAD) > 0) && ((RELOAD) <= 0xFFFFFF))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void SysTick_CLKSourceConfig(u32 SysTick_CLKSource);\r
+void SysTick_SetReload(u32 Reload);\r
+void SysTick_CounterCmd(u32 SysTick_Counter);\r
+void SysTick_ITConfig(FunctionalState NewState);\r
+u32 SysTick_GetCounter(void);\r
+FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG);\r
+\r
+#endif /* __STM32F10x_SYSTICK_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_tim.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the \r
+* TIM firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_TIM_H\r
+#define __STM32F10x_TIM_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/* TIM Time Base Init structure definition */\r
+typedef struct\r
+{\r
+ u16 TIM_Prescaler;\r
+ u16 TIM_CounterMode;\r
+ u16 TIM_Period;\r
+ u16 TIM_ClockDivision;\r
+ u8 TIM_RepetitionCounter;\r
+} TIM_TimeBaseInitTypeDef;\r
+\r
+/* TIM Output Compare Init structure definition */\r
+typedef struct\r
+{\r
+ u16 TIM_OCMode;\r
+ u16 TIM_OutputState;\r
+ u16 TIM_OutputNState;\r
+ u16 TIM_Pulse;\r
+ u16 TIM_OCPolarity;\r
+ u16 TIM_OCNPolarity;\r
+ u16 TIM_OCIdleState;\r
+ u16 TIM_OCNIdleState;\r
+} TIM_OCInitTypeDef;\r
+\r
+/* TIM Input Capture Init structure definition */\r
+typedef struct\r
+{\r
+ u16 TIM_Channel;\r
+ u16 TIM_ICPolarity;\r
+ u16 TIM_ICSelection;\r
+ u16 TIM_ICPrescaler;\r
+ u16 TIM_ICFilter;\r
+} TIM_ICInitTypeDef;\r
+\r
+/* BDTR structure definition */\r
+typedef struct\r
+{\r
+ u16 TIM_OSSRState;\r
+ u16 TIM_OSSIState;\r
+ u16 TIM_LOCKLevel; \r
+ u16 TIM_DeadTime;\r
+ u16 TIM_Break;\r
+ u16 TIM_BreakPolarity;\r
+ u16 TIM_AutomaticOutput;\r
+} TIM_BDTRInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/ \r
+\r
+#define IS_TIM_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == TIM2_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == TIM3_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == TIM4_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == TIM5_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == TIM6_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == TIM7_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == TIM8_BASE))\r
+\r
+#define IS_TIM_18_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == TIM8_BASE))\r
+\r
+#define IS_TIM_123458_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == TIM2_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == TIM3_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == TIM4_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == TIM5_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == TIM8_BASE))\r
+\r
+/* TIM Output Compare and PWM modes -----------------------------------------*/\r
+#define TIM_OCMode_Timing ((u16)0x0000)\r
+#define TIM_OCMode_Active ((u16)0x0010)\r
+#define TIM_OCMode_Inactive ((u16)0x0020)\r
+#define TIM_OCMode_Toggle ((u16)0x0030)\r
+#define TIM_OCMode_PWM1 ((u16)0x0060)\r
+#define TIM_OCMode_PWM2 ((u16)0x0070)\r
+\r
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2))\r
+\r
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2) || \\r
+ ((MODE) == TIM_ForcedAction_Active) || \\r
+ ((MODE) == TIM_ForcedAction_InActive))\r
+/* TIM One Pulse Mode -------------------------------------------------------*/\r
+#define TIM_OPMode_Single ((u16)0x0008)\r
+#define TIM_OPMode_Repetitive ((u16)0x0000)\r
+\r
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \\r
+ ((MODE) == TIM_OPMode_Repetitive))\r
+\r
+/* TIM Channel -------------------------------------------------------------*/\r
+#define TIM_Channel_1 ((u16)0x0000)\r
+#define TIM_Channel_2 ((u16)0x0004)\r
+#define TIM_Channel_3 ((u16)0x0008)\r
+#define TIM_Channel_4 ((u16)0x000C)\r
+\r
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2) || \\r
+ ((CHANNEL) == TIM_Channel_3) || \\r
+ ((CHANNEL) == TIM_Channel_4))\r
+\r
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2))\r
+\r
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2) || \\r
+ ((CHANNEL) == TIM_Channel_3))\r
+/* TIM Clock Division CKD --------------------------------------------------*/\r
+#define TIM_CKD_DIV1 ((u16)0x0000)\r
+#define TIM_CKD_DIV2 ((u16)0x0100)\r
+#define TIM_CKD_DIV4 ((u16)0x0200)\r
+\r
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \\r
+ ((DIV) == TIM_CKD_DIV2) || \\r
+ ((DIV) == TIM_CKD_DIV4))\r
+\r
+/* TIM Counter Mode --------------------------------------------------------*/\r
+#define TIM_CounterMode_Up ((u16)0x0000)\r
+#define TIM_CounterMode_Down ((u16)0x0010)\r
+#define TIM_CounterMode_CenterAligned1 ((u16)0x0020)\r
+#define TIM_CounterMode_CenterAligned2 ((u16)0x0040)\r
+#define TIM_CounterMode_CenterAligned3 ((u16)0x0060)\r
+\r
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \\r
+ ((MODE) == TIM_CounterMode_Down) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned3))\r
+\r
+/* TIM Output Compare Polarity ---------------------------------------------*/\r
+#define TIM_OCPolarity_High ((u16)0x0000)\r
+#define TIM_OCPolarity_Low ((u16)0x0002)\r
+\r
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \\r
+ ((POLARITY) == TIM_OCPolarity_Low))\r
+\r
+/* TIM Output Compare N Polarity -------------------------------------------*/\r
+#define TIM_OCNPolarity_High ((u16)0x0000)\r
+#define TIM_OCNPolarity_Low ((u16)0x0008)\r
+\r
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \\r
+ ((POLARITY) == TIM_OCNPolarity_Low))\r
+\r
+/* TIM Output Compare states -----------------------------------------------*/\r
+#define TIM_OutputState_Disable ((u16)0x0000)\r
+#define TIM_OutputState_Enable ((u16)0x0001)\r
+\r
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \\r
+ ((STATE) == TIM_OutputState_Enable))\r
+\r
+/* TIM Output Compare N States ---------------------------------------------*/\r
+#define TIM_OutputNState_Disable ((u16)0x0000)\r
+#define TIM_OutputNState_Enable ((u16)0x0004)\r
+\r
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \\r
+ ((STATE) == TIM_OutputNState_Enable))\r
+\r
+/* TIM Capture Compare States -----------------------------------------------*/\r
+#define TIM_CCx_Enable ((u16)0x0001)\r
+#define TIM_CCx_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \\r
+ ((CCX) == TIM_CCx_Disable))\r
+\r
+/* TIM Capture Compare N States --------------------------------------------*/\r
+#define TIM_CCxN_Enable ((u16)0x0004)\r
+#define TIM_CCxN_Disable ((u16)0x0000) \r
+\r
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \\r
+ ((CCXN) == TIM_CCxN_Disable))\r
+\r
+/* Break Input enable/disable -----------------------------------------------*/\r
+#define TIM_Break_Enable ((u16)0x1000)\r
+#define TIM_Break_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \\r
+ ((STATE) == TIM_Break_Disable))\r
+\r
+/* Break Polarity -----------------------------------------------------------*/\r
+#define TIM_BreakPolarity_Low ((u16)0x0000)\r
+#define TIM_BreakPolarity_High ((u16)0x2000)\r
+\r
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \\r
+ ((POLARITY) == TIM_BreakPolarity_High))\r
+\r
+/* TIM AOE Bit Set/Reset ---------------------------------------------------*/\r
+#define TIM_AutomaticOutput_Enable ((u16)0x4000)\r
+#define TIM_AutomaticOutput_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \\r
+ ((STATE) == TIM_AutomaticOutput_Disable))\r
+/* Lock levels --------------------------------------------------------------*/\r
+#define TIM_LOCKLevel_OFF ((u16)0x0000)\r
+#define TIM_LOCKLevel_1 ((u16)0x0100)\r
+#define TIM_LOCKLevel_2 ((u16)0x0200)\r
+#define TIM_LOCKLevel_3 ((u16)0x0300)\r
+\r
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \\r
+ ((LEVEL) == TIM_LOCKLevel_1) || \\r
+ ((LEVEL) == TIM_LOCKLevel_2) || \\r
+ ((LEVEL) == TIM_LOCKLevel_3))\r
+\r
+/* OSSI: Off-State Selection for Idle mode states ---------------------------*/\r
+#define TIM_OSSIState_Enable ((u16)0x0400)\r
+#define TIM_OSSIState_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \\r
+ ((STATE) == TIM_OSSIState_Disable))\r
+\r
+/* OSSR: Off-State Selection for Run mode states ----------------------------*/\r
+#define TIM_OSSRState_Enable ((u16)0x0800)\r
+#define TIM_OSSRState_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \\r
+ ((STATE) == TIM_OSSRState_Disable))\r
+\r
+/* TIM Output Compare Idle State -------------------------------------------*/\r
+#define TIM_OCIdleState_Set ((u16)0x0100)\r
+#define TIM_OCIdleState_Reset ((u16)0x0000)\r
+\r
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \\r
+ ((STATE) == TIM_OCIdleState_Reset))\r
+\r
+/* TIM Output Compare N Idle State -----------------------------------------*/\r
+#define TIM_OCNIdleState_Set ((u16)0x0200)\r
+#define TIM_OCNIdleState_Reset ((u16)0x0000)\r
+\r
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \\r
+ ((STATE) == TIM_OCNIdleState_Reset))\r
+\r
+/* TIM Input Capture Polarity ----------------------------------------------*/\r
+#define TIM_ICPolarity_Rising ((u16)0x0000)\r
+#define TIM_ICPolarity_Falling ((u16)0x0002)\r
+\r
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
+ ((POLARITY) == TIM_ICPolarity_Falling))\r
+\r
+/* TIM Input Capture Selection ---------------------------------------------*/\r
+#define TIM_ICSelection_DirectTI ((u16)0x0001)\r
+#define TIM_ICSelection_IndirectTI ((u16)0x0002)\r
+#define TIM_ICSelection_TRC ((u16)0x0003)\r
+\r
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_TRC))\r
+\r
+/* TIM Input Capture Prescaler ---------------------------------------------*/\r
+#define TIM_ICPSC_DIV1 ((u16)0x0000)\r
+#define TIM_ICPSC_DIV2 ((u16)0x0004)\r
+#define TIM_ICPSC_DIV4 ((u16)0x0008)\r
+#define TIM_ICPSC_DIV8 ((u16)0x000C)\r
+\r
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV8)) \r
+\r
+/* TIM interrupt sources ---------------------------------------------------*/\r
+#define TIM_IT_Update ((u16)0x0001)\r
+#define TIM_IT_CC1 ((u16)0x0002)\r
+#define TIM_IT_CC2 ((u16)0x0004)\r
+#define TIM_IT_CC3 ((u16)0x0008)\r
+#define TIM_IT_CC4 ((u16)0x0010)\r
+#define TIM_IT_COM ((u16)0x0020)\r
+#define TIM_IT_Trigger ((u16)0x0040)\r
+#define TIM_IT_Break ((u16)0x0080)\r
+\r
+#define IS_TIM_IT(IT) ((((IT) & (u16)0xFF00) == 0x0000) && ((IT) != 0x0000))\r
+\r
+#define IS_TIM_PERIPH_IT(PERIPH, TIM_IT) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\\r
+ (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \\r
+ (((TIM_IT) & (u16)0xFFA0) == 0x0000) && ((TIM_IT) != 0x0000)) ||\\r
+ (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \\r
+ (((TIM_IT) & (u16)0xFF00) == 0x0000) && ((TIM_IT) != 0x0000)) ||\\r
+ (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \\r
+ (((TIM_IT) & (u16)0xFFFE) == 0x0000) && ((TIM_IT) != 0x0000)))\r
+\r
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \\r
+ ((IT) == TIM_IT_CC1) || \\r
+ ((IT) == TIM_IT_CC2) || \\r
+ ((IT) == TIM_IT_CC3) || \\r
+ ((IT) == TIM_IT_CC4) || \\r
+ ((IT) == TIM_IT_COM) || \\r
+ ((IT) == TIM_IT_Trigger) || \\r
+ ((IT) == TIM_IT_Break))\r
+\r
+/* TIM DMA Base address ----------------------------------------------------*/\r
+#define TIM_DMABase_CR1 ((u16)0x0000)\r
+#define TIM_DMABase_CR2 ((u16)0x0001)\r
+#define TIM_DMABase_SMCR ((u16)0x0002)\r
+#define TIM_DMABase_DIER ((u16)0x0003)\r
+#define TIM_DMABase_SR ((u16)0x0004)\r
+#define TIM_DMABase_EGR ((u16)0x0005)\r
+#define TIM_DMABase_CCMR1 ((u16)0x0006)\r
+#define TIM_DMABase_CCMR2 ((u16)0x0007)\r
+#define TIM_DMABase_CCER ((u16)0x0008)\r
+#define TIM_DMABase_CNT ((u16)0x0009)\r
+#define TIM_DMABase_PSC ((u16)0x000A)\r
+#define TIM_DMABase_ARR ((u16)0x000B)\r
+#define TIM_DMABase_RCR ((u16)0x000C)\r
+#define TIM_DMABase_CCR1 ((u16)0x000D)\r
+#define TIM_DMABase_CCR2 ((u16)0x000E)\r
+#define TIM_DMABase_CCR3 ((u16)0x000F)\r
+#define TIM_DMABase_CCR4 ((u16)0x0010)\r
+#define TIM_DMABase_BDTR ((u16)0x0011)\r
+#define TIM_DMABase_DCR ((u16)0x0012)\r
+\r
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \\r
+ ((BASE) == TIM_DMABase_CR2) || \\r
+ ((BASE) == TIM_DMABase_SMCR) || \\r
+ ((BASE) == TIM_DMABase_DIER) || \\r
+ ((BASE) == TIM_DMABase_SR) || \\r
+ ((BASE) == TIM_DMABase_EGR) || \\r
+ ((BASE) == TIM_DMABase_CCMR1) || \\r
+ ((BASE) == TIM_DMABase_CCMR2) || \\r
+ ((BASE) == TIM_DMABase_CCER) || \\r
+ ((BASE) == TIM_DMABase_CNT) || \\r
+ ((BASE) == TIM_DMABase_PSC) || \\r
+ ((BASE) == TIM_DMABase_ARR) || \\r
+ ((BASE) == TIM_DMABase_RCR) || \\r
+ ((BASE) == TIM_DMABase_CCR1) || \\r
+ ((BASE) == TIM_DMABase_CCR2) || \\r
+ ((BASE) == TIM_DMABase_CCR3) || \\r
+ ((BASE) == TIM_DMABase_CCR4) || \\r
+ ((BASE) == TIM_DMABase_BDTR) || \\r
+ ((BASE) == TIM_DMABase_DCR))\r
+\r
+/* TIM DMA Burst Length ----------------------------------------------------*/\r
+#define TIM_DMABurstLength_1Byte ((u16)0x0000)\r
+#define TIM_DMABurstLength_2Bytes ((u16)0x0100)\r
+#define TIM_DMABurstLength_3Bytes ((u16)0x0200)\r
+#define TIM_DMABurstLength_4Bytes ((u16)0x0300)\r
+#define TIM_DMABurstLength_5Bytes ((u16)0x0400)\r
+#define TIM_DMABurstLength_6Bytes ((u16)0x0500)\r
+#define TIM_DMABurstLength_7Bytes ((u16)0x0600)\r
+#define TIM_DMABurstLength_8Bytes ((u16)0x0700)\r
+#define TIM_DMABurstLength_9Bytes ((u16)0x0800)\r
+#define TIM_DMABurstLength_10Bytes ((u16)0x0900)\r
+#define TIM_DMABurstLength_11Bytes ((u16)0x0A00)\r
+#define TIM_DMABurstLength_12Bytes ((u16)0x0B00)\r
+#define TIM_DMABurstLength_13Bytes ((u16)0x0C00)\r
+#define TIM_DMABurstLength_14Bytes ((u16)0x0D00)\r
+#define TIM_DMABurstLength_15Bytes ((u16)0x0E00)\r
+#define TIM_DMABurstLength_16Bytes ((u16)0x0F00)\r
+#define TIM_DMABurstLength_17Bytes ((u16)0x1000)\r
+#define TIM_DMABurstLength_18Bytes ((u16)0x1100)\r
+\r
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \\r
+ ((LENGTH) == TIM_DMABurstLength_2Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_3Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_4Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_5Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_6Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_7Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_8Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_9Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_10Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_11Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_12Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_13Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_14Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_15Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_16Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_17Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_18Bytes))\r
+\r
+/* TIM DMA sources ---------------------------------------------------------*/\r
+#define TIM_DMA_Update ((u16)0x0100)\r
+#define TIM_DMA_CC1 ((u16)0x0200)\r
+#define TIM_DMA_CC2 ((u16)0x0400)\r
+#define TIM_DMA_CC3 ((u16)0x0800)\r
+#define TIM_DMA_CC4 ((u16)0x1000)\r
+#define TIM_DMA_COM ((u16)0x2000)\r
+#define TIM_DMA_Trigger ((u16)0x4000)\r
+\r
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (u16)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))\r
+\r
+#define IS_TIM_PERIPH_DMA(PERIPH, SOURCE) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\\r
+ (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \\r
+ (((SOURCE) & (u16)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\\r
+ (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \\r
+ (((SOURCE) & (u16)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\\r
+ (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \\r
+ (((SOURCE) & (u16)0xFEFF) == 0x0000) && ((SOURCE) != 0x0000)))\r
+\r
+/* TIM External Trigger Prescaler ------------------------------------------*/\r
+#define TIM_ExtTRGPSC_OFF ((u16)0x0000)\r
+#define TIM_ExtTRGPSC_DIV2 ((u16)0x1000)\r
+#define TIM_ExtTRGPSC_DIV4 ((u16)0x2000)\r
+#define TIM_ExtTRGPSC_DIV8 ((u16)0x3000)\r
+\r
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))\r
+\r
+/* TIM Internal Trigger Selection ------------------------------------------*/\r
+#define TIM_TS_ITR0 ((u16)0x0000)\r
+#define TIM_TS_ITR1 ((u16)0x0010)\r
+#define TIM_TS_ITR2 ((u16)0x0020)\r
+#define TIM_TS_ITR3 ((u16)0x0030)\r
+#define TIM_TS_TI1F_ED ((u16)0x0040)\r
+#define TIM_TS_TI1FP1 ((u16)0x0050)\r
+#define TIM_TS_TI2FP2 ((u16)0x0060)\r
+#define TIM_TS_ETRF ((u16)0x0070)\r
+\r
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3) || \\r
+ ((SELECTION) == TIM_TS_TI1F_ED) || \\r
+ ((SELECTION) == TIM_TS_TI1FP1) || \\r
+ ((SELECTION) == TIM_TS_TI2FP2) || \\r
+ ((SELECTION) == TIM_TS_ETRF))\r
+\r
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3))\r
+\r
+/* TIM TIx External Clock Source -------------------------------------------*/\r
+#define TIM_TIxExternalCLK1Source_TI1 ((u16)0x0050)\r
+#define TIM_TIxExternalCLK1Source_TI2 ((u16)0x0060)\r
+#define TIM_TIxExternalCLK1Source_TI1ED ((u16)0x0040)\r
+\r
+#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \\r
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \\r
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))\r
+\r
+/* TIM External Trigger Polarity -------------------------------------------*/\r
+#define TIM_ExtTRGPolarity_Inverted ((u16)0x8000)\r
+#define TIM_ExtTRGPolarity_NonInverted ((u16)0x0000)\r
+\r
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \\r
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))\r
+\r
+/* TIM Prescaler Reload Mode -----------------------------------------------*/\r
+#define TIM_PSCReloadMode_Update ((u16)0x0000)\r
+#define TIM_PSCReloadMode_Immediate ((u16)0x0001)\r
+\r
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \\r
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))\r
+\r
+/* TIM Forced Action -------------------------------------------------------*/\r
+#define TIM_ForcedAction_Active ((u16)0x0050)\r
+#define TIM_ForcedAction_InActive ((u16)0x0040)\r
+\r
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \\r
+ ((ACTION) == TIM_ForcedAction_InActive))\r
+\r
+/* TIM Encoder Mode --------------------------------------------------------*/ \r
+#define TIM_EncoderMode_TI1 ((u16)0x0001)\r
+#define TIM_EncoderMode_TI2 ((u16)0x0002)\r
+#define TIM_EncoderMode_TI12 ((u16)0x0003)\r
+\r
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \\r
+ ((MODE) == TIM_EncoderMode_TI2) || \\r
+ ((MODE) == TIM_EncoderMode_TI12))\r
+\r
+/* TIM Event Source --------------------------------------------------------*/\r
+#define TIM_EventSource_Update ((u16)0x0001)\r
+#define TIM_EventSource_CC1 ((u16)0x0002)\r
+#define TIM_EventSource_CC2 ((u16)0x0004)\r
+#define TIM_EventSource_CC3 ((u16)0x0008)\r
+#define TIM_EventSource_CC4 ((u16)0x0010)\r
+#define TIM_EventSource_COM ((u16)0x0020)\r
+#define TIM_EventSource_Trigger ((u16)0x0040)\r
+#define TIM_EventSource_Break ((u16)0x0080)\r
+\r
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (u16)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))\r
+\r
+#define IS_TIM_PERIPH_EVENT(PERIPH, EVENT) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\\r
+ (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \\r
+ (((EVENT) & (u16)0xFFA0) == 0x0000) && ((EVENT) != 0x0000)) ||\\r
+ (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \\r
+ (((EVENT) & (u16)0xFF00) == 0x0000) && ((EVENT) != 0x0000)) ||\\r
+ (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \\r
+ (((EVENT) & (u16)0xFFFE) == 0x0000) && ((EVENT) != 0x0000)))\r
+\r
+/* TIM Update Source --------------------------------------------------------*/\r
+#define TIM_UpdateSource_Global ((u16)0x0000)\r
+#define TIM_UpdateSource_Regular ((u16)0x0001)\r
+\r
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \\r
+ ((SOURCE) == TIM_UpdateSource_Regular))\r
+\r
+/* TIM Ouput Compare Preload State ------------------------------------------*/\r
+#define TIM_OCPreload_Enable ((u16)0x0008)\r
+#define TIM_OCPreload_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \\r
+ ((STATE) == TIM_OCPreload_Disable))\r
+\r
+/* TIM Ouput Compare Fast State ---------------------------------------------*/\r
+#define TIM_OCFast_Enable ((u16)0x0004)\r
+#define TIM_OCFast_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \\r
+ ((STATE) == TIM_OCFast_Disable))\r
+ \r
+/* TIM Ouput Compare Clear State --------------------------------------------*/\r
+#define TIM_OCClear_Enable ((u16)0x0080)\r
+#define TIM_OCClear_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \\r
+ ((STATE) == TIM_OCClear_Disable)) \r
+\r
+/* TIM Trigger Output Source ------------------------------------------------*/ \r
+#define TIM_TRGOSource_Reset ((u16)0x0000)\r
+#define TIM_TRGOSource_Enable ((u16)0x0010)\r
+#define TIM_TRGOSource_Update ((u16)0x0020)\r
+#define TIM_TRGOSource_OC1 ((u16)0x0030)\r
+#define TIM_TRGOSource_OC1Ref ((u16)0x0040)\r
+#define TIM_TRGOSource_OC2Ref ((u16)0x0050)\r
+#define TIM_TRGOSource_OC3Ref ((u16)0x0060)\r
+#define TIM_TRGOSource_OC4Ref ((u16)0x0070)\r
+\r
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \\r
+ ((SOURCE) == TIM_TRGOSource_Enable) || \\r
+ ((SOURCE) == TIM_TRGOSource_Update) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))\r
+\r
+#define IS_TIM_PERIPH_TRGO(PERIPH, TRGO) (((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\\r
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \\r
+ (((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \\r
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \\r
+ ((TRGO) == TIM_TRGOSource_Reset)) ||\\r
+ ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\\r
+ (((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \\r
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \\r
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \\r
+ ((TRGO) == TIM_TRGOSource_Enable)) ||\\r
+ ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\\r
+ (((*(u32*)&(PERIPH)) == TIM6_BASE))||(((*(u32*)&(PERIPH)) == TIM7_BASE))|| \\r
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \\r
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \\r
+ ((TRGO) == TIM_TRGOSource_Update)) ||\\r
+ ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\\r
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \\r
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \\r
+ ((TRGO) == TIM_TRGOSource_OC1)) ||\\r
+ ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\\r
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \\r
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \\r
+ ((TRGO) == TIM_TRGOSource_OC1Ref)) ||\\r
+ ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\\r
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \\r
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \\r
+ ((TRGO) == TIM_TRGOSource_OC2Ref)) ||\\r
+ ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\\r
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \\r
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \\r
+ ((TRGO) == TIM_TRGOSource_OC3Ref)) ||\\r
+ ((((*(u32*)&(PERIPH)) == TIM2_BASE)||(((*(u32*)&(PERIPH)) == TIM1_BASE))||\\r
+ (((*(u32*)&(PERIPH)) == TIM3_BASE))||(((*(u32*)&(PERIPH)) == TIM4_BASE))|| \\r
+ (((*(u32*)&(PERIPH)) == TIM5_BASE))||(((*(u32*)&(PERIPH)) == TIM8_BASE))) && \\r
+ ((TRGO) == TIM_TRGOSource_OC4Ref)))\r
+\r
+/* TIM Slave Mode ----------------------------------------------------------*/\r
+#define TIM_SlaveMode_Reset ((u16)0x0004)\r
+#define TIM_SlaveMode_Gated ((u16)0x0005)\r
+#define TIM_SlaveMode_Trigger ((u16)0x0006)\r
+#define TIM_SlaveMode_External1 ((u16)0x0007)\r
+\r
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \\r
+ ((MODE) == TIM_SlaveMode_Gated) || \\r
+ ((MODE) == TIM_SlaveMode_Trigger) || \\r
+ ((MODE) == TIM_SlaveMode_External1))\r
+\r
+/* TIM Master Slave Mode ---------------------------------------------------*/\r
+#define TIM_MasterSlaveMode_Enable ((u16)0x0080)\r
+#define TIM_MasterSlaveMode_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \\r
+ ((STATE) == TIM_MasterSlaveMode_Disable))\r
+\r
+/* TIM Flags ---------------------------------------------------------------*/\r
+#define TIM_FLAG_Update ((u16)0x0001)\r
+#define TIM_FLAG_CC1 ((u16)0x0002)\r
+#define TIM_FLAG_CC2 ((u16)0x0004)\r
+#define TIM_FLAG_CC3 ((u16)0x0008)\r
+#define TIM_FLAG_CC4 ((u16)0x0010)\r
+#define TIM_FLAG_COM ((u16)0x0020)\r
+#define TIM_FLAG_Trigger ((u16)0x0040)\r
+#define TIM_FLAG_Break ((u16)0x0080)\r
+#define TIM_FLAG_CC1OF ((u16)0x0200)\r
+#define TIM_FLAG_CC2OF ((u16)0x0400)\r
+#define TIM_FLAG_CC3OF ((u16)0x0800)\r
+#define TIM_FLAG_CC4OF ((u16)0x1000)\r
+\r
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \\r
+ ((FLAG) == TIM_FLAG_CC1) || \\r
+ ((FLAG) == TIM_FLAG_CC2) || \\r
+ ((FLAG) == TIM_FLAG_CC3) || \\r
+ ((FLAG) == TIM_FLAG_CC4) || \\r
+ ((FLAG) == TIM_FLAG_COM) || \\r
+ ((FLAG) == TIM_FLAG_Trigger) || \\r
+ ((FLAG) == TIM_FLAG_Break) || \\r
+ ((FLAG) == TIM_FLAG_CC1OF) || \\r
+ ((FLAG) == TIM_FLAG_CC2OF) || \\r
+ ((FLAG) == TIM_FLAG_CC3OF) || \\r
+ ((FLAG) == TIM_FLAG_CC4OF))\r
+\r
+#define IS_TIM_CLEAR_FLAG(PERIPH, TIM_FLAG) ((((((*(u32*)&(PERIPH)) == TIM2_BASE) || (((*(u32*)&(PERIPH)) == TIM3_BASE))||\\r
+ (((*(u32*)&(PERIPH)) == TIM4_BASE)) || (((*(u32*)&(PERIPH)) == TIM5_BASE))))&& \\r
+ (((TIM_FLAG) & (u16)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\\r
+ (((((*(u32*)&(PERIPH)) == TIM1_BASE) || (((*(u32*)&(PERIPH)) == TIM8_BASE))))&& \\r
+ (((TIM_FLAG) & (u16)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\\r
+ (((((*(u32*)&(PERIPH)) == TIM6_BASE) || (((*(u32*)&(PERIPH)) == TIM7_BASE))))&& \\r
+ (((TIM_FLAG) & (u16)0xFFFE) == 0x0000) && ((TIM_FLAG) != 0x0000)))\r
+\r
+#define IS_TIM_PERIPH_FLAG(PERIPH, TIM_FLAG) (((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) ||\\r
+ ((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) || \\r
+ ((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH))==TIM8_BASE)) &&\\r
+ (((TIM_FLAG) == TIM_FLAG_CC1) || ((TIM_FLAG) == TIM_FLAG_CC2) ||\\r
+ ((TIM_FLAG) == TIM_FLAG_CC3) || ((TIM_FLAG) == TIM_FLAG_CC4) || \\r
+ ((TIM_FLAG) == TIM_FLAG_Trigger))) ||\\r
+ ((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) ||\\r
+ ((*(u32*)&(PERIPH))==TIM1_BASE)|| ((*(u32*)&(PERIPH))==TIM8_BASE) || \\r
+ ((*(u32*)&(PERIPH))==TIM7_BASE) || ((*(u32*)&(PERIPH))==TIM6_BASE)) && \\r
+ (((TIM_FLAG) == TIM_FLAG_Update))) ||\\r
+ ((((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH)) == TIM8_BASE)) &&\\r
+ (((TIM_FLAG) == TIM_FLAG_COM) || ((TIM_FLAG) == TIM_FLAG_Break))) ||\\r
+ ((((*(u32*)&(PERIPH))==TIM2_BASE) || ((*(u32*)&(PERIPH)) == TIM3_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == TIM4_BASE) || ((*(u32*)&(PERIPH))==TIM5_BASE) || \\r
+ ((*(u32*)&(PERIPH))==TIM1_BASE) || ((*(u32*)&(PERIPH))==TIM8_BASE)) &&\\r
+ (((TIM_FLAG) == TIM_FLAG_CC1OF) || ((TIM_FLAG) == TIM_FLAG_CC2OF) ||\\r
+ ((TIM_FLAG) == TIM_FLAG_CC3OF) || ((TIM_FLAG) == TIM_FLAG_CC4OF)))) \r
+ \r
+/* TIM Input Capture Filer Value ---------------------------------------------*/\r
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r
+\r
+/* TIM External Trigger Filter -----------------------------------------------*/\r
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+void TIM_DeInit(TIM_TypeDef* TIMx);\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState);\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource);\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength);\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState NewState);\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource,\r
+ u16 TIM_ICPolarity, u16 ICFilter); \r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,\r
+ u16 ExtTRGFilter);\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, \r
+ u16 TIM_ExtTRGPolarity, u16 ExtTRGFilter);\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,\r
+ u16 ExtTRGFilter);\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode);\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode);\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);\r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode,\r
+ u16 TIM_IC1Polarity, u16 TIM_IC2Polarity);\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear);\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);\r
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity);\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);\r
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity);\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);\r
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCNPolarity);\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCx);\r
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCxN);\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_OCMode);\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource);\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode);\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource);\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode);\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode);\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, u16 Counter);\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload);\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1);\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2);\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3);\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4);\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_ICPSC);\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD);\r
+u16 TIM_GetCapture1(TIM_TypeDef* TIMx);\r
+u16 TIM_GetCapture2(TIM_TypeDef* TIMx);\r
+u16 TIM_GetCapture3(TIM_TypeDef* TIMx);\r
+u16 TIM_GetCapture4(TIM_TypeDef* TIMx);\r
+u16 TIM_GetCounter(TIM_TypeDef* TIMx);\r
+u16 TIM_GetPrescaler(TIM_TypeDef* TIMx);\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG);\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG);\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT);\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT);\r
+ \r
+#endif /*__STM32F10x_TIM_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_type.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the common data types used for the\r
+* STM32F10x firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_TYPE_H\r
+#define __STM32F10x_TYPE_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Exported types ------------------------------------------------------------*/\r
+typedef signed long s32;\r
+typedef signed short s16;\r
+typedef signed char s8;\r
+\r
+typedef signed long const sc32; /* Read Only */\r
+typedef signed short const sc16; /* Read Only */\r
+typedef signed char const sc8; /* Read Only */\r
+\r
+typedef volatile signed long vs32;\r
+typedef volatile signed short vs16;\r
+typedef volatile signed char vs8;\r
+\r
+typedef volatile signed long const vsc32; /* Read Only */\r
+typedef volatile signed short const vsc16; /* Read Only */\r
+typedef volatile signed char const vsc8; /* Read Only */\r
+\r
+typedef unsigned long u32;\r
+typedef unsigned short u16;\r
+typedef unsigned char u8;\r
+\r
+typedef unsigned long const uc32; /* Read Only */\r
+typedef unsigned short const uc16; /* Read Only */\r
+typedef unsigned char const uc8; /* Read Only */\r
+\r
+typedef volatile unsigned long vu32;\r
+typedef volatile unsigned short vu16;\r
+typedef volatile unsigned char vu8;\r
+\r
+typedef volatile unsigned long const vuc32; /* Read Only */\r
+typedef volatile unsigned short const vuc16; /* Read Only */\r
+typedef volatile unsigned char const vuc8; /* Read Only */\r
+\r
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;\r
+\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
+\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
+\r
+#define U8_MAX ((u8)255)\r
+#define S8_MAX ((s8)127)\r
+#define S8_MIN ((s8)-128)\r
+#define U16_MAX ((u16)65535u)\r
+#define S16_MAX ((s16)32767)\r
+#define S16_MIN ((s16)-32768)\r
+#define U32_MAX ((u32)4294967295uL)\r
+#define S32_MAX ((s32)2147483647)\r
+#define S32_MIN ((s32)-2147483648)\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+#endif /* __STM32F10x_TYPE_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_usart.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* USART firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_USART_H\r
+#define __STM32F10x_USART_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* USART Init Structure definition */\r
+typedef struct\r
+{\r
+ u32 USART_BaudRate;\r
+ u16 USART_WordLength;\r
+ u16 USART_StopBits;\r
+ u16 USART_Parity;\r
+ u16 USART_Mode;\r
+ u16 USART_HardwareFlowControl; \r
+} USART_InitTypeDef;\r
+\r
+/* USART Clock Init Structure definition */\r
+typedef struct\r
+{\r
+ u16 USART_Clock;\r
+ u16 USART_CPOL;\r
+ u16 USART_CPHA;\r
+ u16 USART_LastBit;\r
+} USART_ClockInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+#define IS_USART_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == USART2_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == USART3_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == UART4_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == UART5_BASE))\r
+\r
+#define IS_USART_123_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == USART2_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == USART3_BASE))\r
+\r
+#define IS_USART_1234_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == USART2_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == USART3_BASE) || \\r
+ ((*(u32*)&(PERIPH)) == UART4_BASE))\r
+\r
+/* USART Word Length ---------------------------------------------------------*/\r
+#define USART_WordLength_8b ((u16)0x0000)\r
+#define USART_WordLength_9b ((u16)0x1000)\r
+ \r
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \\r
+ ((LENGTH) == USART_WordLength_9b))\r
+\r
+/* USART Stop Bits -----------------------------------------------------------*/\r
+#define USART_StopBits_1 ((u16)0x0000)\r
+#define USART_StopBits_0_5 ((u16)0x1000)\r
+#define USART_StopBits_2 ((u16)0x2000)\r
+#define USART_StopBits_1_5 ((u16)0x3000)\r
+\r
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \\r
+ ((STOPBITS) == USART_StopBits_0_5) || \\r
+ ((STOPBITS) == USART_StopBits_2) || \\r
+ ((STOPBITS) == USART_StopBits_1_5))\r
+/* USART Parity --------------------------------------------------------------*/\r
+#define USART_Parity_No ((u16)0x0000)\r
+#define USART_Parity_Even ((u16)0x0400)\r
+#define USART_Parity_Odd ((u16)0x0600) \r
+\r
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \\r
+ ((PARITY) == USART_Parity_Even) || \\r
+ ((PARITY) == USART_Parity_Odd))\r
+\r
+/* USART Mode ----------------------------------------------------------------*/\r
+#define USART_Mode_Rx ((u16)0x0004)\r
+#define USART_Mode_Tx ((u16)0x0008)\r
+\r
+#define IS_USART_MODE(MODE) ((((MODE) & (u16)0xFFF3) == 0x00) && ((MODE) != (u16)0x00))\r
+\r
+/* USART Hardware Flow Control -----------------------------------------------*/\r
+#define USART_HardwareFlowControl_None ((u16)0x0000)\r
+#define USART_HardwareFlowControl_RTS ((u16)0x0100)\r
+#define USART_HardwareFlowControl_CTS ((u16)0x0200)\r
+#define USART_HardwareFlowControl_RTS_CTS ((u16)0x0300)\r
+\r
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
+ (((CONTROL) == USART_HardwareFlowControl_None) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_CTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))\r
+\r
+#define IS_USART_PERIPH_HFC(PERIPH, HFC) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \\r
+ ((*(u32*)&(PERIPH)) != UART5_BASE)) \\r
+ || ((HFC) == USART_HardwareFlowControl_None)) \r
+\r
+/* USART Clock ---------------------------------------------------------------*/\r
+#define USART_Clock_Disable ((u16)0x0000)\r
+#define USART_Clock_Enable ((u16)0x0800)\r
+\r
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \\r
+ ((CLOCK) == USART_Clock_Enable))\r
+\r
+/* USART Clock Polarity ------------------------------------------------------*/\r
+#define USART_CPOL_Low ((u16)0x0000)\r
+#define USART_CPOL_High ((u16)0x0400)\r
+\r
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))\r
+ \r
+/* USART Clock Phase ---------------------------------------------------------*/\r
+#define USART_CPHA_1Edge ((u16)0x0000)\r
+#define USART_CPHA_2Edge ((u16)0x0200)\r
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))\r
+\r
+/* USART Last Bit ------------------------------------------------------------*/\r
+#define USART_LastBit_Disable ((u16)0x0000)\r
+#define USART_LastBit_Enable ((u16)0x0100)\r
+\r
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \\r
+ ((LASTBIT) == USART_LastBit_Enable))\r
+\r
+/* USART Interrupt definition ------------------------------------------------*/\r
+#define USART_IT_PE ((u16)0x0028)\r
+#define USART_IT_TXE ((u16)0x0727)\r
+#define USART_IT_TC ((u16)0x0626)\r
+#define USART_IT_RXNE ((u16)0x0525)\r
+#define USART_IT_IDLE ((u16)0x0424)\r
+#define USART_IT_LBD ((u16)0x0846)\r
+#define USART_IT_CTS ((u16)0x096A)\r
+#define USART_IT_ERR ((u16)0x0060)\r
+#define USART_IT_ORE ((u16)0x0360)\r
+#define USART_IT_NE ((u16)0x0260)\r
+#define USART_IT_FE ((u16)0x0160)\r
+\r
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))\r
+\r
+#define IS_USART_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \\r
+ ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))\r
+\r
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TC) || \\r
+ ((IT) == USART_IT_RXNE) || ((IT) == USART_IT_IDLE) || \\r
+ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \\r
+ ((IT) == USART_IT_ORE) || ((IT) == USART_IT_NE) || \\r
+ ((IT) == USART_IT_FE))\r
+\r
+#define IS_USART_PERIPH_IT(PERIPH, USART_IT) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \\r
+ ((*(u32*)&(PERIPH)) != UART5_BASE)) \\r
+ || ((USART_IT) != USART_IT_CTS)) \r
+\r
+/* USART DMA Requests --------------------------------------------------------*/\r
+#define USART_DMAReq_Tx ((u16)0x0080)\r
+#define USART_DMAReq_Rx ((u16)0x0040)\r
+\r
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (u16)0xFF3F) == 0x00) && ((DMAREQ) != (u16)0x00))\r
+\r
+/* USART WakeUp methods ------------------------------------------------------*/\r
+#define USART_WakeUp_IdleLine ((u16)0x0000)\r
+#define USART_WakeUp_AddressMark ((u16)0x0800)\r
+\r
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \\r
+ ((WAKEUP) == USART_WakeUp_AddressMark))\r
+\r
+/* USART LIN Break Detection Length ------------------------------------------*/\r
+#define USART_LINBreakDetectLength_10b ((u16)0x0000)\r
+#define USART_LINBreakDetectLength_11b ((u16)0x0020)\r
+\r
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \\r
+ (((LENGTH) == USART_LINBreakDetectLength_10b) || \\r
+ ((LENGTH) == USART_LINBreakDetectLength_11b))\r
+\r
+/* USART IrDA Low Power ------------------------------------------------------*/\r
+#define USART_IrDAMode_LowPower ((u16)0x0004)\r
+#define USART_IrDAMode_Normal ((u16)0x0000)\r
+\r
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \\r
+ ((MODE) == USART_IrDAMode_Normal))\r
+\r
+/* USART Flags ---------------------------------------------------------------*/\r
+#define USART_FLAG_CTS ((u16)0x0200)\r
+#define USART_FLAG_LBD ((u16)0x0100)\r
+#define USART_FLAG_TXE ((u16)0x0080)\r
+#define USART_FLAG_TC ((u16)0x0040)\r
+#define USART_FLAG_RXNE ((u16)0x0020)\r
+#define USART_FLAG_IDLE ((u16)0x0010)\r
+#define USART_FLAG_ORE ((u16)0x0008)\r
+#define USART_FLAG_NE ((u16)0x0004)\r
+#define USART_FLAG_FE ((u16)0x0002)\r
+#define USART_FLAG_PE ((u16)0x0001)\r
+\r
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \\r
+ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \\r
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \\r
+ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \\r
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))\r
+ \r
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0xFC80) == 0x00) && ((FLAG) != (u16)0x00))\r
+\r
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(u32*)&(PERIPH)) != UART4_BASE) &&\\r
+ ((*(u32*)&(PERIPH)) != UART5_BASE)) \\r
+ || ((USART_FLAG) != USART_FLAG_CTS)) \r
+\r
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))\r
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)\r
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void USART_DeInit(USART_TypeDef* USARTx);\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState);\r
+void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState);\r
+void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address);\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp);\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength);\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SendData(USART_TypeDef* USARTx, u16 Data);\r
+u16 USART_ReceiveData(USART_TypeDef* USARTx);\r
+void USART_SendBreak(USART_TypeDef* USARTx);\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime);\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler);\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode);\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG);\r
+void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG);\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT);\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT);\r
+\r
+#endif /* __STM32F10x_USART_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_wwdg.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains all the functions prototypes for the\r
+* WWDG firmware library.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_WWDG_H\r
+#define __STM32F10x_WWDG_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* WWDG Prescaler */\r
+#define WWDG_Prescaler_1 ((u32)0x00000000)\r
+#define WWDG_Prescaler_2 ((u32)0x00000080)\r
+#define WWDG_Prescaler_4 ((u32)0x00000100)\r
+#define WWDG_Prescaler_8 ((u32)0x00000180)\r
+\r
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \\r
+ ((PRESCALER) == WWDG_Prescaler_2) || \\r
+ ((PRESCALER) == WWDG_Prescaler_4) || \\r
+ ((PRESCALER) == WWDG_Prescaler_8))\r
+\r
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)\r
+\r
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void WWDG_DeInit(void);\r
+void WWDG_SetPrescaler(u32 WWDG_Prescaler);\r
+void WWDG_SetWindowValue(u8 WindowValue);\r
+void WWDG_EnableIT(void);\r
+void WWDG_SetCounter(u8 Counter);\r
+void WWDG_Enable(u8 Counter);\r
+FlagStatus WWDG_GetFlagStatus(void);\r
+void WWDG_ClearFlag(void);\r
+\r
+#endif /* __STM32F10x_WWDG_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_can.c\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file provides all the CAN firmware functions.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_can.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+/* CAN Master Control Register bits */\r
+#define CAN_MCR_INRQ ((u32)0x00000001) /* Initialization request */\r
+#define CAN_MCR_SLEEP ((u32)0x00000002) /* Sleep mode request */\r
+#define CAN_MCR_TXFP ((u32)0x00000004) /* Transmit FIFO priority */\r
+#define CAN_MCR_RFLM ((u32)0x00000008) /* Receive FIFO locked mode */\r
+#define CAN_MCR_NART ((u32)0x00000010) /* No automatic retransmission */\r
+#define CAN_MCR_AWUM ((u32)0x00000020) /* Automatic wake up mode */\r
+#define CAN_MCR_ABOM ((u32)0x00000040) /* Automatic bus-off management */\r
+#define CAN_MCR_TTCM ((u32)0x00000080) /* time triggered communication */\r
+\r
+/* CAN Master Status Register bits */\r
+#define CAN_MSR_INAK ((u32)0x00000001) /* Initialization acknowledge */\r
+#define CAN_MSR_WKUI ((u32)0x00000008) /* Wake-up interrupt */\r
+#define CAN_MSR_SLAKI ((u32)0x00000010) /* Sleep acknowledge interrupt */\r
+\r
+/* CAN Transmit Status Register bits */\r
+#define CAN_TSR_RQCP0 ((u32)0x00000001) /* Request completed mailbox0 */\r
+#define CAN_TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of mailbox0 */\r
+#define CAN_TSR_ABRQ0 ((u32)0x00000080) /* Abort request for mailbox0 */\r
+#define CAN_TSR_RQCP1 ((u32)0x00000100) /* Request completed mailbox1 */\r
+#define CAN_TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of mailbox1 */\r
+#define CAN_TSR_ABRQ1 ((u32)0x00008000) /* Abort request for mailbox1 */\r
+#define CAN_TSR_RQCP2 ((u32)0x00010000) /* Request completed mailbox2 */\r
+#define CAN_TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of mailbox2 */\r
+#define CAN_TSR_ABRQ2 ((u32)0x00800000) /* Abort request for mailbox2 */\r
+#define CAN_TSR_TME0 ((u32)0x04000000) /* Transmit mailbox 0 empty */\r
+#define CAN_TSR_TME1 ((u32)0x08000000) /* Transmit mailbox 1 empty */\r
+#define CAN_TSR_TME2 ((u32)0x10000000) /* Transmit mailbox 2 empty */\r
+\r
+/* CAN Receive FIFO 0 Register bits */\r
+#define CAN_RF0R_FULL0 ((u32)0x00000008) /* FIFO 0 full */\r
+#define CAN_RF0R_FOVR0 ((u32)0x00000010) /* FIFO 0 overrun */\r
+#define CAN_RF0R_RFOM0 ((u32)0x00000020) /* Release FIFO 0 output mailbox */\r
+\r
+/* CAN Receive FIFO 1 Register bits */\r
+#define CAN_RF1R_FULL1 ((u32)0x00000008) /* FIFO 1 full */\r
+#define CAN_RF1R_FOVR1 ((u32)0x00000010) /* FIFO 1 overrun */\r
+#define CAN_RF1R_RFOM1 ((u32)0x00000020) /* Release FIFO 1 output mailbox */\r
+\r
+/* CAN Error Status Register bits */\r
+#define CAN_ESR_EWGF ((u32)0x00000001) /* Error warning flag */\r
+#define CAN_ESR_EPVF ((u32)0x00000002) /* Error passive flag */\r
+#define CAN_ESR_BOFF ((u32)0x00000004) /* Bus-off flag */\r
+\r
+/* CAN Mailbox Transmit Request */\r
+#define CAN_TMIDxR_TXRQ ((u32)0x00000001) /* Transmit mailbox request */\r
+\r
+/* CAN Filter Master Register bits */\r
+#define CAN_FMR_FINIT ((u32)0x00000001) /* Filter init mode */\r
+\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit);\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/*******************************************************************************\r
+* Function Name : CAN_DeInit\r
+* Description : Deinitializes the CAN peripheral registers to their default\r
+* reset values.\r
+* Input : None.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_DeInit(void)\r
+{\r
+ /* Enable CAN reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE);\r
+ /* Release CAN from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_Init\r
+* Description : Initializes the CAN peripheral according to the specified\r
+* parameters in the CAN_InitStruct.\r
+* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that\r
+ contains the configuration information for the CAN peripheral.\r
+* Output : None.\r
+* Return : Constant indicates initialization succeed which will be \r
+* CANINITFAILED or CANINITOK.\r
+*******************************************************************************/\r
+u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct)\r
+{\r
+ u8 InitStatus = 0;\r
+ u16 WaitAck;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));\r
+ assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));\r
+ assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));\r
+ assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));\r
+ assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));\r
+ assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));\r
+\r
+ /* Request initialisation */\r
+ CAN->MCR = CAN_MCR_INRQ;\r
+\r
+ /* ...and check acknowledged */\r
+ if ((CAN->MSR & CAN_MSR_INAK) == 0)\r
+ {\r
+ InitStatus = CANINITFAILED;\r
+ }\r
+ else\r
+ {\r
+ /* Set the time triggered communication mode */\r
+ if (CAN_InitStruct->CAN_TTCM == ENABLE)\r
+ {\r
+ CAN->MCR |= CAN_MCR_TTCM;\r
+ }\r
+ else\r
+ {\r
+ CAN->MCR &= ~CAN_MCR_TTCM;\r
+ }\r
+\r
+ /* Set the automatic bus-off management */\r
+ if (CAN_InitStruct->CAN_ABOM == ENABLE)\r
+ {\r
+ CAN->MCR |= CAN_MCR_ABOM;\r
+ }\r
+ else\r
+ {\r
+ CAN->MCR &= ~CAN_MCR_ABOM;\r
+ }\r
+\r
+ /* Set the automatic wake-up mode */\r
+ if (CAN_InitStruct->CAN_AWUM == ENABLE)\r
+ {\r
+ CAN->MCR |= CAN_MCR_AWUM;\r
+ }\r
+ else\r
+ {\r
+ CAN->MCR &= ~CAN_MCR_AWUM;\r
+ }\r
+\r
+ /* Set the no automatic retransmission */\r
+ if (CAN_InitStruct->CAN_NART == ENABLE)\r
+ {\r
+ CAN->MCR |= CAN_MCR_NART;\r
+ }\r
+ else\r
+ {\r
+ CAN->MCR &= ~CAN_MCR_NART;\r
+ }\r
+\r
+ /* Set the receive FIFO locked mode */\r
+ if (CAN_InitStruct->CAN_RFLM == ENABLE)\r
+ {\r
+ CAN->MCR |= CAN_MCR_RFLM;\r
+ }\r
+ else\r
+ {\r
+ CAN->MCR &= ~CAN_MCR_RFLM;\r
+ }\r
+\r
+ /* Set the transmit FIFO priority */\r
+ if (CAN_InitStruct->CAN_TXFP == ENABLE)\r
+ {\r
+ CAN->MCR |= CAN_MCR_TXFP;\r
+ }\r
+ else\r
+ {\r
+ CAN->MCR &= ~CAN_MCR_TXFP;\r
+ }\r
+\r
+ /* Set the bit timing register */\r
+ CAN->BTR = (u32)((u32)CAN_InitStruct->CAN_Mode << 30) | ((u32)CAN_InitStruct->CAN_SJW << 24) |\r
+ ((u32)CAN_InitStruct->CAN_BS1 << 16) | ((u32)CAN_InitStruct->CAN_BS2 << 20) |\r
+ ((u32)CAN_InitStruct->CAN_Prescaler - 1);\r
+\r
+ InitStatus = CANINITOK;\r
+\r
+ /* Request leave initialisation */\r
+ CAN->MCR &= ~CAN_MCR_INRQ;\r
+\r
+ /* Wait the acknowledge */\r
+ for(WaitAck = 0x400; WaitAck > 0x0; WaitAck--)\r
+ {\r
+ }\r
+ \r
+ /* ...and check acknowledged */\r
+ if ((CAN->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)\r
+ {\r
+ InitStatus = CANINITFAILED;\r
+ }\r
+ }\r
+\r
+ /* At this step, return the status of initialization */\r
+ return InitStatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_FilterInit\r
+* Description : Initializes the CAN peripheral according to the specified\r
+* parameters in the CAN_FilterInitStruct.\r
+* Input : CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef\r
+* structure that contains the configuration information.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)\r
+{\r
+ u16 FilterNumber_BitPos = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));\r
+ assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));\r
+ assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));\r
+ assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));\r
+\r
+ FilterNumber_BitPos = \r
+ (u16)((u16)0x0001 << ((u16)CAN_FilterInitStruct->CAN_FilterNumber));\r
+\r
+ /* Initialisation mode for the filter */\r
+ CAN->FMR |= CAN_FMR_FINIT;\r
+\r
+ /* Filter Deactivation */\r
+ CAN->FA1R &= ~(u32)FilterNumber_BitPos;\r
+\r
+ /* Filter Scale */\r
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)\r
+ {\r
+ /* 16-bit scale for the filter */\r
+ CAN->FS1R &= ~(u32)FilterNumber_BitPos;\r
+\r
+ /* First 16-bit identifier and First 16-bit mask */\r
+ /* Or First 16-bit identifier and Second 16-bit identifier */\r
+ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = \r
+ ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |\r
+ ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow);\r
+\r
+ /* Second 16-bit identifier and Second 16-bit mask */\r
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */\r
+ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = \r
+ ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r
+ ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh);\r
+ }\r
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)\r
+ {\r
+ /* 32-bit scale for the filter */\r
+ CAN->FS1R |= FilterNumber_BitPos;\r
+\r
+ /* 32-bit identifier or First 32-bit identifier */\r
+ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = \r
+ ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |\r
+ ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow);\r
+\r
+ /* 32-bit mask or Second 32-bit identifier */\r
+ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = \r
+ ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r
+ ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow);\r
+\r
+ }\r
+\r
+ /* Filter Mode */\r
+ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)\r
+ {\r
+ /*Id/Mask mode for the filter*/\r
+ CAN->FM1R &= ~(u32)FilterNumber_BitPos;\r
+ }\r
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */\r
+ {\r
+ /*Identifier list mode for the filter*/\r
+ CAN->FM1R |= (u32)FilterNumber_BitPos;\r
+ }\r
+\r
+ /* Filter FIFO assignment */\r
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0)\r
+ {\r
+ /* FIFO 0 assignation for the filter */\r
+ CAN->FFA1R &= ~(u32)FilterNumber_BitPos;\r
+ }\r
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1)\r
+ {\r
+ /* FIFO 1 assignation for the filter */\r
+ CAN->FFA1R |= (u32)FilterNumber_BitPos;\r
+ }\r
+ \r
+ /* Filter activation */\r
+ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)\r
+ {\r
+ CAN->FA1R |= FilterNumber_BitPos;\r
+ }\r
+\r
+ /* Leave the initialisation mode for the filter */\r
+ CAN->FMR &= ~CAN_FMR_FINIT;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_StructInit\r
+* Description : Fills each CAN_InitStruct member with its default value.\r
+* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure which\r
+* will be initialized.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)\r
+{\r
+ /* Reset CAN init structure parameters values */\r
+\r
+ /* Initialize the time triggered communication mode */\r
+ CAN_InitStruct->CAN_TTCM = DISABLE;\r
+\r
+ /* Initialize the automatic bus-off management */\r
+ CAN_InitStruct->CAN_ABOM = DISABLE;\r
+\r
+ /* Initialize the automatic wake-up mode */\r
+ CAN_InitStruct->CAN_AWUM = DISABLE;\r
+\r
+ /* Initialize the no automatic retransmission */\r
+ CAN_InitStruct->CAN_NART = DISABLE;\r
+\r
+ /* Initialize the receive FIFO locked mode */\r
+ CAN_InitStruct->CAN_RFLM = DISABLE;\r
+\r
+ /* Initialize the transmit FIFO priority */\r
+ CAN_InitStruct->CAN_TXFP = DISABLE;\r
+\r
+ /* Initialize the CAN_Mode member */\r
+ CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;\r
+\r
+ /* Initialize the CAN_SJW member */\r
+ CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;\r
+\r
+ /* Initialize the CAN_BS1 member */\r
+ CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;\r
+\r
+ /* Initialize the CAN_BS2 member */\r
+ CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;\r
+\r
+ /* Initialize the CAN_Prescaler member */\r
+ CAN_InitStruct->CAN_Prescaler = 1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_ITConfig\r
+* Description : Enables or disables the specified CAN interrupts.\r
+* Input : - CAN_IT: specifies the CAN interrupt sources to be enabled or\r
+* disabled.\r
+* This parameter can be: CAN_IT_TME, CAN_IT_FMP0, CAN_IT_FF0,\r
+* CAN_IT_FOV0, CAN_IT_FMP1, CAN_IT_FF1,\r
+* CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV,\r
+* CAN_IT_LEC, CAN_IT_ERR, CAN_IT_WKU or\r
+* CAN_IT_SLK.\r
+* - NewState: new state of the CAN interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ITConfig(CAN_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected CAN interrupt */\r
+ CAN->IER |= CAN_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected CAN interrupt */\r
+ CAN->IER &= ~CAN_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_Transmit\r
+* Description : Initiates the transmission of a message.\r
+* Input : TxMessage: pointer to a structure which contains CAN Id, CAN\r
+* DLC and CAN datas.\r
+* Output : None.\r
+* Return : The number of the mailbox that is used for transmission\r
+* or CAN_NO_MB if there is no empty mailbox.\r
+*******************************************************************************/\r
+u8 CAN_Transmit(CanTxMsg* TxMessage)\r
+{\r
+ u8 TransmitMailbox = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_STDID(TxMessage->StdId));\r
+ assert_param(IS_CAN_EXTID(TxMessage->StdId));\r
+ assert_param(IS_CAN_IDTYPE(TxMessage->IDE));\r
+ assert_param(IS_CAN_RTR(TxMessage->RTR));\r
+ assert_param(IS_CAN_DLC(TxMessage->DLC));\r
+\r
+ /* Select one empty transmit mailbox */\r
+ if ((CAN->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)\r
+ {\r
+ TransmitMailbox = 0;\r
+ }\r
+ else if ((CAN->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)\r
+ {\r
+ TransmitMailbox = 1;\r
+ }\r
+ else if ((CAN->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)\r
+ {\r
+ TransmitMailbox = 2;\r
+ }\r
+ else\r
+ {\r
+ TransmitMailbox = CAN_NO_MB;\r
+ }\r
+\r
+ if (TransmitMailbox != CAN_NO_MB)\r
+ {\r
+ /* Set up the Id */\r
+ CAN->sTxMailBox[TransmitMailbox].TIR &= CAN_TMIDxR_TXRQ;\r
+ if (TxMessage->IDE == CAN_ID_STD)\r
+ {\r
+ TxMessage->StdId &= (u32)0x000007FF;\r
+ TxMessage->StdId = TxMessage->StdId << 21;\r
+ \r
+ CAN->sTxMailBox[TransmitMailbox].TIR |= (TxMessage->StdId | TxMessage->IDE |\r
+ TxMessage->RTR);\r
+ }\r
+ else\r
+ {\r
+ TxMessage->ExtId &= (u32)0x1FFFFFFF;\r
+ TxMessage->ExtId <<= 3;\r
+\r
+ CAN->sTxMailBox[TransmitMailbox].TIR |= (TxMessage->ExtId | TxMessage->IDE | \r
+ TxMessage->RTR);\r
+ }\r
+ \r
+ /* Set up the DLC */\r
+ TxMessage->DLC &= (u8)0x0000000F;\r
+ CAN->sTxMailBox[TransmitMailbox].TDTR &= (u32)0xFFFFFFF0;\r
+ CAN->sTxMailBox[TransmitMailbox].TDTR |= TxMessage->DLC;\r
+\r
+ /* Set up the data field */\r
+ CAN->sTxMailBox[TransmitMailbox].TDLR = (((u32)TxMessage->Data[3] << 24) | \r
+ ((u32)TxMessage->Data[2] << 16) |\r
+ ((u32)TxMessage->Data[1] << 8) | \r
+ ((u32)TxMessage->Data[0]));\r
+ CAN->sTxMailBox[TransmitMailbox].TDHR = (((u32)TxMessage->Data[7] << 24) | \r
+ ((u32)TxMessage->Data[6] << 16) |\r
+ ((u32)TxMessage->Data[5] << 8) |\r
+ ((u32)TxMessage->Data[4]));\r
+\r
+ /* Request transmission */\r
+ CAN->sTxMailBox[TransmitMailbox].TIR |= CAN_TMIDxR_TXRQ;\r
+ }\r
+\r
+ return TransmitMailbox;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_TransmitStatus\r
+* Description : Checks the transmission of a message.\r
+* Input : TransmitMailbox: the number of the mailbox that is used for\r
+* transmission.\r
+* Output : None.\r
+* Return : CANTXOK if the CAN driver transmits the message, CANTXFAILED\r
+* in an other case.\r
+*******************************************************************************/\r
+u8 CAN_TransmitStatus(u8 TransmitMailbox)\r
+{\r
+ /* RQCP, TXOK and TME bits */\r
+ u8 State = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));\r
+\r
+ switch (TransmitMailbox)\r
+ {\r
+ case (0): State |= (u8)((CAN->TSR & CAN_TSR_RQCP0) << 2);\r
+ State |= (u8)((CAN->TSR & CAN_TSR_TXOK0) >> 0);\r
+ State |= (u8)((CAN->TSR & CAN_TSR_TME0) >> 26);\r
+ break;\r
+ case (1): State |= (u8)((CAN->TSR & CAN_TSR_RQCP1) >> 6);\r
+ State |= (u8)((CAN->TSR & CAN_TSR_TXOK1) >> 8);\r
+ State |= (u8)((CAN->TSR & CAN_TSR_TME1) >> 27);\r
+ break;\r
+ case (2): State |= (u8)((CAN->TSR & CAN_TSR_RQCP2) >> 14);\r
+ State |= (u8)((CAN->TSR & CAN_TSR_TXOK2) >> 16);\r
+ State |= (u8)((CAN->TSR & CAN_TSR_TME2) >> 28);\r
+ break;\r
+ default:\r
+ State = CANTXFAILED;\r
+ break;\r
+ }\r
+\r
+ switch (State)\r
+ {\r
+ /* transmit pending */\r
+ case (0x0): State = CANTXPENDING;\r
+ break;\r
+ /* transmit failed */\r
+ case (0x5): State = CANTXFAILED;\r
+ break;\r
+ /* transmit succedeed */\r
+ case (0x7): State = CANTXOK;\r
+ break;\r
+ default:\r
+ State = CANTXFAILED;\r
+ break;\r
+ }\r
+\r
+ return State;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_CancelTransmit\r
+* Description : Cancels a transmit request.\r
+* Input : Mailbox number.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_CancelTransmit(u8 Mailbox)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));\r
+\r
+ /* abort transmission */\r
+ switch (Mailbox)\r
+ {\r
+ case (0): CAN->TSR |= CAN_TSR_ABRQ0;\r
+ break;\r
+ case (1): CAN->TSR |= CAN_TSR_ABRQ1;\r
+ break;\r
+ case (2): CAN->TSR |= CAN_TSR_ABRQ2;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_FIFORelease\r
+* Description : Releases a FIFO.\r
+* Input : FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_FIFORelease(u8 FIFONumber)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+\r
+ /* Release FIFO0 */\r
+ if (FIFONumber == CAN_FIFO0)\r
+ {\r
+ CAN->RF0R = CAN_RF0R_RFOM0;\r
+ }\r
+ /* Release FIFO1 */\r
+ else /* FIFONumber == CAN_FIFO1 */\r
+ {\r
+ CAN->RF1R = CAN_RF1R_RFOM1;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_MessagePending\r
+* Description : Returns the number of pending messages.\r
+* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
+* Output : None.\r
+* Return : NbMessage which is the number of pending message.\r
+*******************************************************************************/\r
+u8 CAN_MessagePending(u8 FIFONumber)\r
+{\r
+ u8 MessagePending=0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+\r
+ if (FIFONumber == CAN_FIFO0)\r
+ {\r
+ MessagePending = (u8)(CAN->RF0R&(u32)0x03);\r
+ }\r
+ else if (FIFONumber == CAN_FIFO1)\r
+ {\r
+ MessagePending = (u8)(CAN->RF1R&(u32)0x03);\r
+ }\r
+ else\r
+ {\r
+ MessagePending = 0;\r
+ }\r
+ return MessagePending;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_Receive\r
+* Description : Receives a message.\r
+* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
+* Output : RxMessage: pointer to a structure which contains CAN Id,\r
+* CAN DLC, CAN datas and FMI number.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+\r
+ /* Get the Id */\r
+ RxMessage->IDE = (u8)0x04 & CAN->sFIFOMailBox[FIFONumber].RIR;\r
+ if (RxMessage->IDE == CAN_ID_STD)\r
+ {\r
+ RxMessage->StdId = (u32)0x000007FF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 21);\r
+ }\r
+ else\r
+ {\r
+ RxMessage->ExtId = (u32)0x1FFFFFFF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 3);\r
+ }\r
+ \r
+ RxMessage->RTR = (u8)0x02 & CAN->sFIFOMailBox[FIFONumber].RIR;\r
+\r
+ /* Get the DLC */\r
+ RxMessage->DLC = (u8)0x0F & CAN->sFIFOMailBox[FIFONumber].RDTR;\r
+\r
+ /* Get the FMI */\r
+ RxMessage->FMI = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDTR >> 8);\r
+\r
+ /* Get the data field */\r
+ RxMessage->Data[0] = (u8)0xFF & CAN->sFIFOMailBox[FIFONumber].RDLR;\r
+ RxMessage->Data[1] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 8);\r
+ RxMessage->Data[2] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 16);\r
+ RxMessage->Data[3] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 24);\r
+\r
+ RxMessage->Data[4] = (u8)0xFF & CAN->sFIFOMailBox[FIFONumber].RDHR;\r
+ RxMessage->Data[5] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 8);\r
+ RxMessage->Data[6] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 16);\r
+ RxMessage->Data[7] = (u8)0xFF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 24);\r
+\r
+ /* Release the FIFO */\r
+ CAN_FIFORelease(FIFONumber);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_Sleep\r
+* Description : Enters the low power mode.\r
+* Input : None.\r
+* Output : None.\r
+* Return : CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case.\r
+*******************************************************************************/\r
+u8 CAN_Sleep(void)\r
+{\r
+ u8 SleepStatus = 0;\r
+\r
+ /* Sleep mode entering request */\r
+ CAN->MCR |= CAN_MCR_SLEEP;\r
+ SleepStatus = CANSLEEPOK;\r
+\r
+ /* Sleep mode status */\r
+ if ((CAN->MCR&CAN_MCR_SLEEP) == 0)\r
+ {\r
+ /* Sleep mode not entered */\r
+ SleepStatus = CANSLEEPFAILED;\r
+ }\r
+\r
+ /* At this step, sleep mode status */\r
+ return SleepStatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_WakeUp\r
+* Description : Wakes the CAN up.\r
+* Input : None.\r
+* Output : None.\r
+* Return : CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other\r
+* case.\r
+*******************************************************************************/\r
+u8 CAN_WakeUp(void)\r
+{\r
+ u8 WakeUpStatus = 0;\r
+\r
+ /* Wake up request */\r
+ CAN->MCR &= ~CAN_MCR_SLEEP;\r
+ WakeUpStatus = CANWAKEUPFAILED;\r
+\r
+ /* Sleep mode status */\r
+ if ((CAN->MCR&CAN_MCR_SLEEP) == 0)\r
+ {\r
+ /* Sleep mode exited */\r
+ WakeUpStatus = CANWAKEUPOK;\r
+ }\r
+\r
+ /* At this step, sleep mode status */\r
+ return WakeUpStatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_GetFlagStatus\r
+* Description : Checks whether the specified CAN flag is set or not.\r
+* Input : CAN_FLAG: specifies the flag to check.\r
+* This parameter can be: CAN_FLAG_EWG, CAN_FLAG_EPV or\r
+* CAN_FLAG_BOF.\r
+* Output : None.\r
+* Return : The new state of CAN_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FLAG(CAN_FLAG));\r
+\r
+ /* Check the status of the specified CAN flag */\r
+ if ((CAN->ESR & CAN_FLAG) != (u32)RESET)\r
+ {\r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the CAN_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_ClearFlag\r
+* Description : Clears the CAN's pending flags.\r
+* Input : CAN_FLAG: specifies the flag to clear.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_ClearFlag(u32 CAN_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FLAG(CAN_FLAG));\r
+\r
+ /* Clear the selected CAN flags */\r
+ CAN->ESR &= ~CAN_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_GetITStatus\r
+* Description : Checks whether the specified CAN interrupt has occurred or \r
+* not.\r
+* Input : CAN_IT: specifies the CAN interrupt source to check.\r
+* This parameter can be: CAN_IT_RQCP0, CAN_IT_RQCP1, CAN_IT_RQCP2,\r
+* CAN_IT_FF0, CAN_IT_FOV0, CAN_IT_FF1,\r
+* CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, \r
+* CAN_IT_BOF, CAN_IT_WKU or CAN_IT_SLK.\r
+* Output : None.\r
+* Return : The new state of CAN_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus CAN_GetITStatus(u32 CAN_IT)\r
+{\r
+ ITStatus pendingbitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ITStatus(CAN_IT));\r
+\r
+ switch (CAN_IT)\r
+ {\r
+ case CAN_IT_RQCP0:\r
+ pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP0);\r
+ break;\r
+ case CAN_IT_RQCP1:\r
+ pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP1);\r
+ break;\r
+ case CAN_IT_RQCP2:\r
+ pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP2);\r
+ break;\r
+ case CAN_IT_FF0:\r
+ pendingbitstatus = CheckITStatus(CAN->RF0R, CAN_RF0R_FULL0);\r
+ break;\r
+ case CAN_IT_FOV0:\r
+ pendingbitstatus = CheckITStatus(CAN->RF0R, CAN_RF0R_FOVR0);\r
+ break;\r
+ case CAN_IT_FF1:\r
+ pendingbitstatus = CheckITStatus(CAN->RF1R, CAN_RF1R_FULL1);\r
+ break;\r
+ case CAN_IT_FOV1:\r
+ pendingbitstatus = CheckITStatus(CAN->RF1R, CAN_RF1R_FOVR1);\r
+ break;\r
+ case CAN_IT_EWG:\r
+ pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_EWGF);\r
+ break;\r
+ case CAN_IT_EPV:\r
+ pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_EPVF);\r
+ break;\r
+ case CAN_IT_BOF:\r
+ pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_BOFF);\r
+ break;\r
+ case CAN_IT_SLK:\r
+ pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_SLAKI);\r
+ break;\r
+ case CAN_IT_WKU:\r
+ pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_WKUI);\r
+ break;\r
+\r
+ default :\r
+ pendingbitstatus = RESET;\r
+ break;\r
+ }\r
+\r
+ /* Return the CAN_IT status */\r
+ return pendingbitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_ClearITPendingBit\r
+* Description : Clears the CAN\92s interrupt pending bits.\r
+* Input : CAN_IT: specifies the interrupt pending bit to clear.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_ClearITPendingBit(u32 CAN_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ITStatus(CAN_IT));\r
+\r
+ switch (CAN_IT)\r
+ {\r
+ case CAN_IT_RQCP0:\r
+ CAN->TSR = CAN_TSR_RQCP0; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_RQCP1:\r
+ CAN->TSR = CAN_TSR_RQCP1; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_RQCP2:\r
+ CAN->TSR = CAN_TSR_RQCP2; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_FF0:\r
+ CAN->RF0R = CAN_RF0R_FULL0; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_FOV0:\r
+ CAN->RF0R = CAN_RF0R_FOVR0; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_FF1:\r
+ CAN->RF1R = CAN_RF1R_FULL1; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_FOV1:\r
+ CAN->RF1R = CAN_RF1R_FOVR1; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_EWG:\r
+ CAN->ESR &= ~ CAN_ESR_EWGF; /* rw */\r
+ break;\r
+ case CAN_IT_EPV:\r
+ CAN->ESR &= ~ CAN_ESR_EPVF; /* rw */\r
+ break;\r
+ case CAN_IT_BOF:\r
+ CAN->ESR &= ~ CAN_ESR_BOFF; /* rw */\r
+ break;\r
+ case CAN_IT_WKU:\r
+ CAN->MSR = CAN_MSR_WKUI; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_SLK:\r
+ CAN->MSR = CAN_MSR_SLAKI; /* rc_w1*/\r
+ break;\r
+ default :\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CheckITStatus\r
+* Description : Checks whether the CAN interrupt has occurred or not.\r
+* Input : CAN_Reg: specifies the CAN interrupt register to check.\r
+* It_Bit: specifies the interrupt source bit to check.\r
+* Output : None.\r
+* Return : The new state of the CAN Interrupt (SET or RESET).\r
+*******************************************************************************/\r
+static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit)\r
+{\r
+ ITStatus pendingbitstatus = RESET;\r
+\r
+ if ((CAN_Reg & It_Bit) != (u32)RESET)\r
+ {\r
+ /* CAN_IT is set */\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAN_IT is reset */\r
+ pendingbitstatus = RESET;\r
+ }\r
+\r
+ return pendingbitstatus;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_gpio.c\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file provides all the GPIO firmware functions.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_gpio.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ------------ RCC registers bit address in the alias region ----------- */\r
+#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)\r
+\r
+/* --- EVENTCR Register ---*/\r
+/* Alias word address of EVOE bit */\r
+#define EVCR_OFFSET (AFIO_OFFSET + 0x00)\r
+#define EVOE_BitNumber ((u8)0x07)\r
+#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))\r
+\r
+#define EVCR_PORTPINCONFIG_MASK ((u16)0xFF80)\r
+#define LSB_MASK ((u16)0xFFFF)\r
+#define DBGAFR_POSITION_MASK ((u32)0x000F0000)\r
+#define DBGAFR_SWJCFG_MASK ((u32)0xF0FFFFFF)\r
+#define DBGAFR_LOCATION_MASK ((u32)0x00200000)\r
+#define DBGAFR_NUMBITS_MASK ((u32)0x00100000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_DeInit\r
+* Description : Deinitializes the GPIOx peripheral registers to their default\r
+* reset values.\r
+* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ switch (*(u32*)&GPIOx)\r
+ {\r
+ case GPIOA_BASE:\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);\r
+ break;\r
+\r
+ case GPIOB_BASE:\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);\r
+ break;\r
+\r
+ case GPIOC_BASE:\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);\r
+ break;\r
+\r
+ case GPIOD_BASE:\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);\r
+ break;\r
+ \r
+ case GPIOE_BASE:\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);\r
+ break; \r
+\r
+ case GPIOF_BASE:\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);\r
+ break;\r
+\r
+ case GPIOG_BASE:\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);\r
+ break; \r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_AFIODeInit\r
+* Description : Deinitializes the Alternate Functions (remap, event control\r
+* and EXTI configuration) registers to their default reset\r
+* values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_AFIODeInit(void)\r
+{\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_Init\r
+* Description : Initializes the GPIOx peripheral according to the specified\r
+* parameters in the GPIO_InitStruct.\r
+* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that\r
+* contains the configuration information for the specified GPIO\r
+* peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;\r
+ u32 tmpreg = 0x00, pinmask = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));\r
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); \r
+ \r
+/*---------------------------- GPIO Mode Configuration -----------------------*/\r
+ currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F);\r
+\r
+ if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00)\r
+ { \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));\r
+ /* Output mode */\r
+ currentmode |= (u32)GPIO_InitStruct->GPIO_Speed;\r
+ }\r
+\r
+/*---------------------------- GPIO CRL Configuration ------------------------*/\r
+ /* Configure the eight low port pins */\r
+ if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00)\r
+ {\r
+ tmpreg = GPIOx->CRL;\r
+\r
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)\r
+ {\r
+ pos = ((u32)0x01) << pinpos;\r
+ /* Get the port pins position */\r
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;\r
+\r
+ if (currentpin == pos)\r
+ {\r
+ pos = pinpos << 2;\r
+ /* Clear the corresponding low control register bits */\r
+ pinmask = ((u32)0x0F) << pos;\r
+ tmpreg &= ~pinmask;\r
+\r
+ /* Write the mode configuration in the corresponding bits */\r
+ tmpreg |= (currentmode << pos);\r
+\r
+ /* Reset the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)\r
+ {\r
+ GPIOx->BRR = (((u32)0x01) << pinpos);\r
+ }\r
+ /* Set the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)\r
+ {\r
+ GPIOx->BSRR = (((u32)0x01) << pinpos);\r
+ }\r
+ }\r
+ }\r
+ GPIOx->CRL = tmpreg;\r
+ }\r
+\r
+/*---------------------------- GPIO CRH Configuration ------------------------*/\r
+ /* Configure the eight high port pins */\r
+ if (GPIO_InitStruct->GPIO_Pin > 0x00FF)\r
+ {\r
+ tmpreg = GPIOx->CRH;\r
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)\r
+ {\r
+ pos = (((u32)0x01) << (pinpos + 0x08));\r
+ /* Get the port pins position */\r
+ currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);\r
+ if (currentpin == pos)\r
+ {\r
+ pos = pinpos << 2;\r
+ /* Clear the corresponding high control register bits */\r
+ pinmask = ((u32)0x0F) << pos;\r
+ tmpreg &= ~pinmask;\r
+\r
+ /* Write the mode configuration in the corresponding bits */\r
+ tmpreg |= (currentmode << pos);\r
+\r
+ /* Reset the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)\r
+ {\r
+ GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08));\r
+ }\r
+ /* Set the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)\r
+ {\r
+ GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08));\r
+ }\r
+ }\r
+ }\r
+ GPIOx->CRH = tmpreg;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_StructInit\r
+* Description : Fills each GPIO_InitStruct member with its default value.\r
+* Input : - GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ /* Reset GPIO init structure parameters values */\r
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;\r
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_ReadInputDataBit\r
+* Description : Reads the specified input port pin.\r
+* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+* : - GPIO_Pin: specifies the port bit to read.\r
+* This parameter can be GPIO_Pin_x where x can be (0..15).\r
+* Output : None\r
+* Return : The input port pin value.\r
+*******************************************************************************/\r
+u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)\r
+{\r
+ u8 bitstatus = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); \r
+ \r
+ if ((GPIOx->IDR & GPIO_Pin) != (u32)Bit_RESET)\r
+ {\r
+ bitstatus = (u8)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (u8)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_ReadInputData\r
+* Description : Reads the specified GPIO input data port.\r
+* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+* Output : None\r
+* Return : GPIO input data port value.\r
+*******************************************************************************/\r
+u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ return ((u16)GPIOx->IDR);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_ReadOutputDataBit\r
+* Description : Reads the specified output data port bit.\r
+* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+* : - GPIO_Pin: specifies the port bit to read.\r
+* This parameter can be GPIO_Pin_x where x can be (0..15).\r
+* Output : None\r
+* Return : The output port pin value.\r
+*******************************************************************************/\r
+u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)\r
+{\r
+ u8 bitstatus = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); \r
+ \r
+ if ((GPIOx->ODR & GPIO_Pin) != (u32)Bit_RESET)\r
+ {\r
+ bitstatus = (u8)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (u8)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_ReadOutputData\r
+* Description : Reads the specified GPIO output data port.\r
+* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+* Output : None\r
+* Return : GPIO output data port value.\r
+*******************************************************************************/\r
+u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ return ((u16)GPIOx->ODR);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_SetBits\r
+* Description : Sets the selected data port bits.\r
+* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+* - GPIO_Pin: specifies the port bits to be written.\r
+* This parameter can be any combination of GPIO_Pin_x where \r
+* x can be (0..15).\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ GPIOx->BSRR = GPIO_Pin;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_ResetBits\r
+* Description : Clears the selected data port bits.\r
+* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+* - GPIO_Pin: specifies the port bits to be written.\r
+* This parameter can be any combination of GPIO_Pin_x where \r
+* x can be (0..15).\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ GPIOx->BRR = GPIO_Pin;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_WriteBit\r
+* Description : Sets or clears the selected data port bit.\r
+* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+* - GPIO_Pin: specifies the port bit to be written.\r
+* This parameter can be one of GPIO_Pin_x where x can be (0..15).\r
+* - BitVal: specifies the value to be written to the selected bit.\r
+* This parameter can be one of the BitAction enum values:\r
+* - Bit_RESET: to clear the port pin\r
+* - Bit_SET: to set the port pin\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+ assert_param(IS_GPIO_BIT_ACTION(BitVal)); \r
+ \r
+ if (BitVal != Bit_RESET)\r
+ {\r
+ GPIOx->BSRR = GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BRR = GPIO_Pin;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_Write\r
+* Description : Writes data to the specified GPIO data port.\r
+* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+* - PortVal: specifies the value to be written to the port output\r
+* data register.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ GPIOx->ODR = PortVal;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_PinLockConfig\r
+* Description : Locks GPIO Pins configuration registers.\r
+* Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+* - GPIO_Pin: specifies the port bit to be written.\r
+* This parameter can be any combination of GPIO_Pin_x where \r
+* x can be (0..15).\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)\r
+{\r
+ u32 tmp = 0x00010000;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ tmp |= GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Reset LCKK bit */\r
+ GPIOx->LCKR = GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_EventOutputConfig\r
+* Description : Selects the GPIO pin used as Event output.\r
+* Input : - GPIO_PortSource: selects the GPIO port to be used as source\r
+* for Event output.\r
+* This parameter can be GPIO_PortSourceGPIOx where x can be\r
+* (A..E).\r
+* - GPIO_PinSource: specifies the pin for the Event output.\r
+* This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)\r
+{\r
+ u32 tmpreg = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));\r
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+ \r
+ tmpreg = AFIO->EVCR;\r
+ /* Clear the PORT[6:4] and PIN[3:0] bits */\r
+ tmpreg &= EVCR_PORTPINCONFIG_MASK;\r
+ tmpreg |= (u32)GPIO_PortSource << 0x04;\r
+ tmpreg |= GPIO_PinSource;\r
+\r
+ AFIO->EVCR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_EventOutputCmd\r
+* Description : Enables or disables the Event Output.\r
+* Input : - NewState: new state of the Event output.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_EventOutputCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(vu32 *) EVCR_EVOE_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_PinRemapConfig\r
+* Description : Changes the mapping of the specified pin.\r
+* Input : - GPIO_Remap: selects the pin to remap.\r
+* This parameter can be one of the following values:\r
+* - GPIO_Remap_SPI1\r
+* - GPIO_Remap_I2C1\r
+* - GPIO_Remap_USART1\r
+* - GPIO_Remap_USART2\r
+* - GPIO_PartialRemap_USART3\r
+* - GPIO_FullRemap_USART3\r
+* - GPIO_PartialRemap_TIM1\r
+* - GPIO_FullRemap_TIM1\r
+* - GPIO_PartialRemap1_TIM2\r
+* - GPIO_PartialRemap2_TIM2\r
+* - GPIO_FullRemap_TIM2\r
+* - GPIO_PartialRemap_TIM3\r
+* - GPIO_FullRemap_TIM3\r
+* - GPIO_Remap_TIM4\r
+* - GPIO_Remap1_CAN\r
+* - GPIO_Remap2_CAN\r
+* - GPIO_Remap_PD01\r
+* - GPIO_Remap_TIM5CH4_LSI\r
+* - GPIO_Remap_ADC1_ETRGINJ\r
+* - GPIO_Remap_ADC1_ETRGREG\r
+* - GPIO_Remap_ADC2_ETRGINJ\r
+* - GPIO_Remap_ADC2_ETRGREG\r
+* - GPIO_Remap_SWJ_NoJTRST\r
+* - GPIO_Remap_SWJ_JTAGDisable\r
+* - GPIO_Remap_SWJ_Disable\r
+* - NewState: new state of the port pin remapping.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState)\r
+{\r
+ u32 tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_REMAP(GPIO_Remap));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ tmpreg = AFIO->MAPR;\r
+\r
+ tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;\r
+ tmp = GPIO_Remap & LSB_MASK;\r
+\r
+ if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))\r
+ {\r
+ tmpreg &= DBGAFR_SWJCFG_MASK;\r
+ AFIO->MAPR &= DBGAFR_SWJCFG_MASK;\r
+ }\r
+ else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)\r
+ {\r
+ tmp1 = ((u32)0x03) << tmpmask;\r
+ tmpreg &= ~tmp1;\r
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;\r
+ }\r
+ else\r
+ {\r
+ tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));\r
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;\r
+ }\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));\r
+ }\r
+\r
+ AFIO->MAPR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_EXTILineConfig\r
+* Description : Selects the GPIO pin used as EXTI Line.\r
+* Input : - GPIO_PortSource: selects the GPIO port to be used as\r
+* source for EXTI lines.\r
+* This parameter can be GPIO_PortSourceGPIOx where x can be\r
+* (A..G).\r
+* - GPIO_PinSource: specifies the EXTI line to be configured.\r
+* This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)\r
+{\r
+ u32 tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));\r
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+ \r
+ tmp = ((u32)0x0F) << (0x04 * (GPIO_PinSource & (u8)0x03));\r
+\r
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;\r
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((u32)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (u8)0x03)));\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_i2c.c\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file provides all the I2C firmware functions.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_i2c.h"\r
+#include "stm32f10x_rcc.h"\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* I2C SPE mask */\r
+#define CR1_PE_Set ((u16)0x0001)\r
+#define CR1_PE_Reset ((u16)0xFFFE)\r
+\r
+/* I2C START mask */\r
+#define CR1_START_Set ((u16)0x0100)\r
+#define CR1_START_Reset ((u16)0xFEFF)\r
+\r
+/* I2C STOP mask */\r
+#define CR1_STOP_Set ((u16)0x0200)\r
+#define CR1_STOP_Reset ((u16)0xFDFF)\r
+\r
+/* I2C ACK mask */\r
+#define CR1_ACK_Set ((u16)0x0400)\r
+#define CR1_ACK_Reset ((u16)0xFBFF)\r
+\r
+/* I2C ENGC mask */\r
+#define CR1_ENGC_Set ((u16)0x0040)\r
+#define CR1_ENGC_Reset ((u16)0xFFBF)\r
+\r
+/* I2C SWRST mask */\r
+#define CR1_SWRST_Set ((u16)0x8000)\r
+#define CR1_SWRST_Reset ((u16)0x7FFF)\r
+\r
+/* I2C PEC mask */\r
+#define CR1_PEC_Set ((u16)0x1000)\r
+#define CR1_PEC_Reset ((u16)0xEFFF)\r
+\r
+/* I2C ENPEC mask */\r
+#define CR1_ENPEC_Set ((u16)0x0020)\r
+#define CR1_ENPEC_Reset ((u16)0xFFDF)\r
+\r
+/* I2C ENARP mask */\r
+#define CR1_ENARP_Set ((u16)0x0010)\r
+#define CR1_ENARP_Reset ((u16)0xFFEF)\r
+\r
+/* I2C NOSTRETCH mask */\r
+#define CR1_NOSTRETCH_Set ((u16)0x0080)\r
+#define CR1_NOSTRETCH_Reset ((u16)0xFF7F)\r
+\r
+/* I2C registers Masks */\r
+#define CR1_CLEAR_Mask ((u16)0xFBF5)\r
+\r
+/* I2C DMAEN mask */\r
+#define CR2_DMAEN_Set ((u16)0x0800)\r
+#define CR2_DMAEN_Reset ((u16)0xF7FF)\r
+\r
+/* I2C LAST mask */\r
+#define CR2_LAST_Set ((u16)0x1000)\r
+#define CR2_LAST_Reset ((u16)0xEFFF)\r
+\r
+/* I2C FREQ mask */\r
+#define CR2_FREQ_Reset ((u16)0xFFC0)\r
+\r
+/* I2C ADD0 mask */\r
+#define OAR1_ADD0_Set ((u16)0x0001)\r
+#define OAR1_ADD0_Reset ((u16)0xFFFE)\r
+\r
+/* I2C ENDUAL mask */\r
+#define OAR2_ENDUAL_Set ((u16)0x0001)\r
+#define OAR2_ENDUAL_Reset ((u16)0xFFFE)\r
+\r
+/* I2C ADD2 mask */\r
+#define OAR2_ADD2_Reset ((u16)0xFF01)\r
+\r
+/* I2C F/S mask */\r
+#define CCR_FS_Set ((u16)0x8000)\r
+\r
+/* I2C CCR mask */\r
+#define CCR_CCR_Set ((u16)0x0FFF)\r
+\r
+/* I2C FLAG mask */\r
+#define FLAG_Mask ((u32)0x00FFFFFF)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_DeInit\r
+* Description : Deinitializes the I2Cx peripheral registers to their default\r
+* reset values.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_DeInit(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ switch (*(u32*)&I2Cx)\r
+ {\r
+ case I2C1_BASE:\r
+ /* Enable I2C1 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);\r
+ /* Release I2C1 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);\r
+ break;\r
+\r
+ case I2C2_BASE:\r
+ /* Enable I2C2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);\r
+ /* Release I2C2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_Init\r
+* Description : Initializes the I2Cx peripheral according to the specified \r
+* parameters in the I2C_InitStruct.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_InitStruct: pointer to a I2C_InitTypeDef structure that\r
+* contains the configuration information for the specified\r
+* I2C peripheral.\r
+* Output : None\r
+* Return : None\r
+******************************************************************************/\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+ u16 tmpreg = 0, freqrange = 0;\r
+ u16 result = 0x04;\r
+ u32 pclk1 = 8000000;\r
+ RCC_ClocksTypeDef rcc_clocks;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));\r
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));\r
+ assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));\r
+ assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));\r
+ assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));\r
+ assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));\r
+\r
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/\r
+ /* Get the I2Cx CR2 value */\r
+ tmpreg = I2Cx->CR2;\r
+ /* Clear frequency FREQ[5:0] bits */\r
+ tmpreg &= CR2_FREQ_Reset;\r
+ /* Get pclk1 frequency value */\r
+ RCC_GetClocksFreq(&rcc_clocks);\r
+ pclk1 = rcc_clocks.PCLK1_Frequency;\r
+ /* Set frequency bits depending on pclk1 value */\r
+ freqrange = (u16)(pclk1 / 1000000);\r
+ tmpreg |= freqrange;\r
+ /* Write to I2Cx CR2 */\r
+ I2Cx->CR2 = tmpreg;\r
+\r
+/*---------------------------- I2Cx CCR Configuration ------------------------*/\r
+ /* Disable the selected I2C peripheral to configure TRISE */\r
+ I2Cx->CR1 &= CR1_PE_Reset;\r
+\r
+ /* Reset tmpreg value */\r
+ /* Clear F/S, DUTY and CCR[11:0] bits */\r
+ tmpreg = 0;\r
+\r
+ /* Configure speed in standard mode */\r
+ if (I2C_InitStruct->I2C_ClockSpeed <= 100000)\r
+ {\r
+ /* Standard mode speed calculate */\r
+ result = (u16)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));\r
+ /* Test if CCR value is under 0x4*/\r
+ if (result < 0x04)\r
+ {\r
+ /* Set minimum allowed value */\r
+ result = 0x04; \r
+ }\r
+ /* Set speed value for standard mode */\r
+ tmpreg |= result; \r
+ /* Set Maximum Rise Time for standard mode */\r
+ I2Cx->TRISE = freqrange + 1; \r
+ }\r
+ /* Configure speed in fast mode */\r
+ else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/\r
+ {\r
+ if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */\r
+ result = (u16)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));\r
+ }\r
+ else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */\r
+ result = (u16)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));\r
+ /* Set DUTY bit */\r
+ result |= I2C_DutyCycle_16_9;\r
+ }\r
+ /* Test if CCR value is under 0x1*/\r
+ if ((result & CCR_CCR_Set) == 0)\r
+ {\r
+ /* Set minimum allowed value */\r
+ result |= (u16)0x0001; \r
+ }\r
+ /* Set speed value and set F/S bit for fast mode */\r
+ tmpreg |= result | CCR_FS_Set;\r
+ /* Set Maximum Rise Time for fast mode */\r
+ I2Cx->TRISE = (u16)(((freqrange * 300) / 1000) + 1); \r
+ }\r
+ /* Write to I2Cx CCR */\r
+ I2Cx->CCR = tmpreg;\r
+\r
+ /* Enable the selected I2C peripheral */\r
+ I2Cx->CR1 |= CR1_PE_Set;\r
+\r
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/\r
+ /* Get the I2Cx CR1 value */\r
+ tmpreg = I2Cx->CR1;\r
+ /* Clear ACK, SMBTYPE and SMBUS bits */\r
+ tmpreg &= CR1_CLEAR_Mask;\r
+ /* Configure I2Cx: mode and acknowledgement */\r
+ /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */\r
+ /* Set ACK bit according to I2C_Ack value */\r
+ tmpreg |= (u16)((u32)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);\r
+ /* Write to I2Cx CR1 */\r
+ I2Cx->CR1 = tmpreg;\r
+\r
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/\r
+ /* Set I2Cx Own Address1 and acknowledged address */\r
+ I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_StructInit\r
+* Description : Fills each I2C_InitStruct member with its default value.\r
+* Input : - I2C_InitStruct: pointer to an I2C_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+/*---------------- Reset I2C init structure parameters values ----------------*/\r
+ /* Initialize the I2C_Mode member */\r
+ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;\r
+\r
+ /* Initialize the I2C_DutyCycle member */\r
+ I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;\r
+\r
+ /* Initialize the I2C_OwnAddress1 member */\r
+ I2C_InitStruct->I2C_OwnAddress1 = 0;\r
+\r
+ /* Initialize the I2C_Ack member */\r
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;\r
+\r
+ /* Initialize the I2C_AcknowledgedAddress member */\r
+ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;\r
+\r
+ /* initialize the I2C_ClockSpeed member */\r
+ I2C_InitStruct->I2C_ClockSpeed = 5000;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_Cmd\r
+* Description : Enables or disables the specified I2C peripheral.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2Cx peripheral. This parameter\r
+* can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C peripheral */\r
+ I2Cx->CR1 |= CR1_PE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C peripheral */\r
+ I2Cx->CR1 &= CR1_PE_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_DMACmd\r
+* Description : Enables or disables the specified I2C DMA requests.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C DMA transfer.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C DMA requests */\r
+ I2Cx->CR2 |= CR2_DMAEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C DMA requests */\r
+ I2Cx->CR2 &= CR2_DMAEN_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_DMALastTransferCmd\r
+* Description : Specifies that the next DMA transfer is the last one.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C DMA last transfer.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Next DMA transfer is the last transfer */\r
+ I2Cx->CR2 |= CR2_LAST_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Next DMA transfer is not the last transfer */\r
+ I2Cx->CR2 &= CR2_LAST_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GenerateSTART\r
+* Description : Generates I2Cx communication START condition.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C START condition generation.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a START condition */\r
+ I2Cx->CR1 |= CR1_START_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the START condition generation */\r
+ I2Cx->CR1 &= CR1_START_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GenerateSTOP\r
+* Description : Generates I2Cx communication STOP condition.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C STOP condition generation.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a STOP condition */\r
+ I2Cx->CR1 |= CR1_STOP_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the STOP condition generation */\r
+ I2Cx->CR1 &= CR1_STOP_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_AcknowledgeConfig\r
+* Description : Enables or disables the specified I2C acknowledge feature.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C Acknowledgement.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the acknowledgement */\r
+ I2Cx->CR1 |= CR1_ACK_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the acknowledgement */\r
+ I2Cx->CR1 &= CR1_ACK_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_OwnAddress2Config\r
+* Description : Configures the specified I2C own address2.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - Address: specifies the 7bit I2C own address2.\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address)\r
+{\r
+ u16 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = I2Cx->OAR2;\r
+ /* Reset I2Cx Own address2 bit [7:1] */\r
+ tmpreg &= OAR2_ADD2_Reset;\r
+ /* Set I2Cx Own address2 */\r
+ tmpreg |= (u16)(Address & (u16)0x00FE);\r
+ /* Store the new register value */\r
+ I2Cx->OAR2 = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_DualAddressCmd\r
+* Description : Enables or disables the specified I2C dual addressing mode.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C dual addressing mode.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable dual addressing mode */\r
+ I2Cx->OAR2 |= OAR2_ENDUAL_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable dual addressing mode */\r
+ I2Cx->OAR2 &= OAR2_ENDUAL_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GeneralCallCmd\r
+* Description : Enables or disables the specified I2C general call feature.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C General call.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable generall call */\r
+ I2Cx->CR1 |= CR1_ENGC_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable generall call */\r
+ I2Cx->CR1 &= CR1_ENGC_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ITConfig\r
+* Description : Enables or disables the specified I2C interrupts.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_IT: specifies the I2C interrupts sources to be enabled\r
+* or disabled. \r
+* This parameter can be any combination of the following values:\r
+* - I2C_IT_BUF: Buffer interrupt mask\r
+* - I2C_IT_EVT: Event interrupt mask\r
+* - I2C_IT_ERR: Error interrupt mask\r
+* - NewState: new state of the specified I2C interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_I2C_CONFIG_IT(I2C_IT));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C interrupts */\r
+ I2Cx->CR2 |= I2C_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C interrupts */\r
+ I2Cx->CR2 &= (u16)~I2C_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_SendData\r
+* Description : Sends a data byte through the I2Cx peripheral.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - Data: Byte to be transmitted..\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Write in the DR register the data to be sent */\r
+ I2Cx->DR = Data;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ReceiveData\r
+* Description : Returns the most recent received data by the I2Cx peripheral.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* Output : None\r
+* Return : The value of the received data.\r
+*******************************************************************************/\r
+u8 I2C_ReceiveData(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Return the data in the DR register */\r
+ return (u8)I2Cx->DR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_Send7bitAddress\r
+* Description : Transmits the address byte to select the slave device.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - Address: specifies the slave address which will be transmitted\r
+* - I2C_Direction: specifies whether the I2C device will be a\r
+* Transmitter or a Receiver. \r
+* This parameter can be one of the following values\r
+* - I2C_Direction_Transmitter: Transmitter mode\r
+* - I2C_Direction_Receiver: Receiver mode\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));\r
+\r
+ /* Test on the direction to set/reset the read/write bit */\r
+ if (I2C_Direction != I2C_Direction_Transmitter)\r
+ {\r
+ /* Set the address bit0 for read */\r
+ Address |= OAR1_ADD0_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the address bit0 for write */\r
+ Address &= OAR1_ADD0_Reset;\r
+ }\r
+ /* Send the address */\r
+ I2Cx->DR = Address;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ReadRegister\r
+* Description : Reads the specified I2C register and returns its value.\r
+* Input1 : - I2C_Register: specifies the register to read.\r
+* This parameter can be one of the following values:\r
+* - I2C_Register_CR1: CR1 register.\r
+* - I2C_Register_CR2: CR2 register.\r
+* - I2C_Register_OAR1: OAR1 register.\r
+* - I2C_Register_OAR2: OAR2 register.\r
+* - I2C_Register_DR: DR register.\r
+* - I2C_Register_SR1: SR1 register.\r
+* - I2C_Register_SR2: SR2 register.\r
+* - I2C_Register_CCR: CCR register.\r
+* - I2C_Register_TRISE: TRISE register.\r
+* Output : None\r
+* Return : The value of the read register.\r
+*******************************************************************************/\r
+u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_REGISTER(I2C_Register));\r
+\r
+ /* Return the selected register value */\r
+ return (*(vu16 *)(*((vu32 *)&I2Cx) + I2C_Register));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_SoftwareResetCmd\r
+* Description : Enables or disables the specified I2C software reset.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C software reset.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Peripheral under reset */\r
+ I2Cx->CR1 |= CR1_SWRST_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Peripheral not under reset */\r
+ I2Cx->CR1 &= CR1_SWRST_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_SMBusAlertConfig\r
+* Description : Drives the SMBusAlert pin high or low for the specified I2C.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_SMBusAlert: specifies SMBAlert pin level. \r
+* This parameter can be one of the following values:\r
+* - I2C_SMBusAlert_Low: SMBAlert pin driven low\r
+* - I2C_SMBusAlert_High: SMBAlert pin driven high\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));\r
+\r
+ if (I2C_SMBusAlert == I2C_SMBusAlert_Low)\r
+ {\r
+ /* Drive the SMBusAlert pin Low */\r
+ I2Cx->CR1 |= I2C_SMBusAlert_Low;\r
+ }\r
+ else\r
+ {\r
+ /* Drive the SMBusAlert pin High */\r
+ I2Cx->CR1 &= I2C_SMBusAlert_High;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_TransmitPEC\r
+* Description : Enables or disables the specified I2C PEC transfer.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C PEC transmission.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C PEC transmission */\r
+ I2Cx->CR1 |= CR1_PEC_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C PEC transmission */\r
+ I2Cx->CR1 &= CR1_PEC_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_PECPositionConfig\r
+* Description : Selects the specified I2C PEC position.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_PECPosition: specifies the PEC position. \r
+* This parameter can be one of the following values:\r
+* - I2C_PECPosition_Next: indicates that the next\r
+* byte is PEC\r
+* - I2C_PECPosition_Current: indicates that current\r
+* byte is PEC\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));\r
+\r
+ if (I2C_PECPosition == I2C_PECPosition_Next)\r
+ {\r
+ /* Next byte in shift register is PEC */\r
+ I2Cx->CR1 |= I2C_PECPosition_Next;\r
+ }\r
+ else\r
+ {\r
+ /* Current byte in shift register is PEC */\r
+ I2Cx->CR1 &= I2C_PECPosition_Current;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_CalculatePEC\r
+* Description : Enables or disables the PEC value calculation of the\r
+* transfered bytes.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2Cx PEC value calculation.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C PEC calculation */\r
+ I2Cx->CR1 |= CR1_ENPEC_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C PEC calculation */\r
+ I2Cx->CR1 &= CR1_ENPEC_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GetPEC\r
+* Description : Returns the PEC value for the specified I2C.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* Output : None\r
+* Return : The PEC value.\r
+*******************************************************************************/\r
+u8 I2C_GetPEC(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Return the selected I2C PEC value */\r
+ return ((I2Cx->SR2) >> 8);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ARPCmd\r
+* Description : Enables or disables the specified I2C ARP.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2Cx ARP. \r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C ARP */\r
+ I2Cx->CR1 |= CR1_ENARP_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C ARP */\r
+ I2Cx->CR1 &= CR1_ENARP_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_StretchClockCmd\r
+* Description : Enables or disables the specified I2C Clock stretching.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2Cx Clock stretching.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState == DISABLE)\r
+ {\r
+ /* Enable the selected I2C Clock stretching */\r
+ I2Cx->CR1 |= CR1_NOSTRETCH_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C Clock stretching */\r
+ I2Cx->CR1 &= CR1_NOSTRETCH_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_FastModeDutyCycleConfig\r
+* Description : Selects the specified I2C fast mode duty cycle.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_DutyCycle: specifies the fast mode duty cycle.\r
+* This parameter can be one of the following values:\r
+* - I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2\r
+* - I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));\r
+\r
+ if (I2C_DutyCycle != I2C_DutyCycle_16_9)\r
+ {\r
+ /* I2C fast mode Tlow/Thigh=2 */\r
+ I2Cx->CCR &= I2C_DutyCycle_2;\r
+ }\r
+ else\r
+ {\r
+ /* I2C fast mode Tlow/Thigh=16/9 */\r
+ I2Cx->CCR |= I2C_DutyCycle_16_9;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GetLastEvent\r
+* Description : Returns the last I2Cx Event.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* Output : None\r
+* Return : The last event\r
+*******************************************************************************/\r
+u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx)\r
+{\r
+ u32 lastevent = 0;\r
+ u32 flag1 = 0, flag2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Read the I2Cx status register */\r
+ flag1 = I2Cx->SR1;\r
+ flag2 = I2Cx->SR2;\r
+ flag2 = flag2 << 16;\r
+\r
+ /* Get the last event value from I2C status register */\r
+ lastevent = (flag1 | flag2) & FLAG_Mask;\r
+\r
+ /* Return status */\r
+ return lastevent;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_CheckEvent\r
+* Description : Checks whether the last I2Cx Event is equal to the one passed\r
+* as parameter.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_EVENT: specifies the event to be checked. \r
+* This parameter can be one of the following values:\r
+* - I2C_EVENT_SLAVE_ADDRESS_MATCHED : EV1\r
+* - I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2\r
+* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3\r
+* - I2C_EVENT_SLAVE_ACK_FAILURE : EV3-2\r
+* - I2C_EVENT_MASTER_MODE_SELECT : EV5\r
+* - I2C_EVENT_MASTER_MODE_SELECTED : EV6\r
+* - I2C_EVENT_MASTER_BYTE_RECEIVED : EV7\r
+* - I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8\r
+* - I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9\r
+* - I2C_EVENT_SLAVE_STOP_DETECTED : EV4\r
+* Output : None\r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Last event is equal to the I2C_EVENT\r
+* - ERROR: Last event is different from the I2C_EVENT\r
+*******************************************************************************/\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT)\r
+{\r
+ u32 lastevent = 0;\r
+ u32 flag1 = 0, flag2 = 0;\r
+ ErrorStatus status = ERROR;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_EVENT(I2C_EVENT));\r
+\r
+ /* Read the I2Cx status register */\r
+ flag1 = I2Cx->SR1;\r
+ flag2 = I2Cx->SR2;\r
+ flag2 = flag2 << 16;\r
+\r
+ /* Get the last event value from I2C status register */\r
+ lastevent = (flag1 | flag2) & FLAG_Mask;\r
+\r
+ /* Check whether the last event is equal to I2C_EVENT */\r
+ if (lastevent == I2C_EVENT )\r
+ {\r
+ /* SUCCESS: last event is equal to I2C_EVENT */\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ /* ERROR: last event is different from I2C_EVENT */\r
+ status = ERROR;\r
+ }\r
+\r
+ /* Return status */\r
+ return status;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GetFlagStatus\r
+* Description : Checks whether the specified I2C flag is set or not.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_FLAG: specifies the flag to check. \r
+* This parameter can be one of the following values:\r
+* - I2C_FLAG_DUALF: Dual flag (Slave mode)\r
+* - I2C_FLAG_SMBHOST: SMBus host header (Slave mode)\r
+* - I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)\r
+* - I2C_FLAG_GENCALL: General call header flag (Slave mode)\r
+* - I2C_FLAG_TRA: Transmitter/Receiver flag\r
+* - I2C_FLAG_BUSY: Bus busy flag\r
+* - I2C_FLAG_MSL: Master/Slave flag\r
+* - I2C_FLAG_SMBALERT: SMBus Alert flag\r
+* - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
+* - I2C_FLAG_PECERR: PEC error in reception flag\r
+* - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
+* - I2C_FLAG_AF: Acknowledge failure flag\r
+* - I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
+* - I2C_FLAG_BERR: Bus error flag\r
+* - I2C_FLAG_TXE: Data register empty flag (Transmitter)\r
+* - I2C_FLAG_RXNE: Data register not empty (Receiver) flag\r
+* - I2C_FLAG_STOPF: Stop detection flag (Slave mode)\r
+* - I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)\r
+* - I2C_FLAG_BTF: Byte transfer finished flag\r
+* - I2C_FLAG_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+* Address matched flag (Slave mode)\94ENDAD\94\r
+* - I2C_FLAG_SB: Start bit flag (Master mode)\r
+* Output : None\r
+* Return : The new state of I2C_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ u32 i2cstatus = 0;\r
+ u32 flag1 = 0, flag2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));\r
+\r
+ /* Read the I2Cx status register */\r
+ flag1 = I2Cx->SR1;\r
+ flag2 = I2Cx->SR2;\r
+ flag2 = (flag2 & FLAG_Mask) << 16;\r
+\r
+ /* Get the I2C status value */\r
+ i2cstatus = flag1 | flag2;\r
+\r
+ /* Get bit[23:0] of the flag */\r
+ I2C_FLAG &= FLAG_Mask;\r
+\r
+ /* Check the status of the specified I2C flag */\r
+ if ((i2cstatus & I2C_FLAG) != (u32)RESET)\r
+ {\r
+ /* I2C_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the I2C_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ClearFlag\r
+* Description : Clears the I2Cx's pending flags.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_FLAG: specifies the flag to clear. \r
+* This parameter can be one of the following values:\r
+* - I2C_FLAG_SMBALERT: SMBus Alert flag\r
+* - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
+* - I2C_FLAG_PECERR: PEC error in reception flag\r
+* - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
+* - I2C_FLAG_AF: Acknowledge failure flag\r
+* - I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
+* - I2C_FLAG_BERR: Bus error flag\r
+* - I2C_FLAG_STOPF: Stop detection flag (Slave mode)\r
+* - I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)\r
+* - I2C_FLAG_BTF: Byte transfer finished flag\r
+* - I2C_FLAG_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+* Address matched flag (Slave mode)\94ENDAD\94\r
+* - I2C_FLAG_SB: Start bit flag (Master mode)\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG)\r
+{\r
+ u32 flagpos = 0;\r
+ u32 flagindex = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));\r
+\r
+ /* Get the I2C flag position */\r
+ flagpos = I2C_FLAG & FLAG_Mask;\r
+\r
+ /* Get the I2C flag index */\r
+ flagindex = I2C_FLAG >> 28;\r
+\r
+ /* Clear the flag by writing 0 */\r
+ if (flagindex == 1)\r
+ {\r
+ /* Clear the selected I2C flag */\r
+ I2Cx->SR1 = (u16)~flagpos;\r
+ }\r
+ /* Flags that need a read of the SR1 register to be cleared */\r
+ else if (flagindex == 2)\r
+ {\r
+ /* Read the SR1 register */\r
+ (void)I2Cx->SR1;\r
+ }\r
+ /* Flags that need a read of SR1 and a write on CR1 registers to be cleared */\r
+ else if (flagindex == 6)\r
+ {\r
+ /* Read the SR1 register */\r
+ (void)I2Cx->SR1;\r
+\r
+ /* Write on the CR1 register */\r
+ I2Cx->CR1 |= CR1_PE_Set;\r
+ }\r
+ /* Flags that need a read of SR1 and SR2 registers to be cleared */\r
+ else /*flagindex == 0xA*/\r
+ {\r
+ /* Read the SR1 register */\r
+ (void)I2Cx->SR1;\r
+\r
+ /* Read the SR2 register */\r
+ (void)I2Cx->SR2;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GetITStatus\r
+* Description : Checks whether the specified I2C interrupt has occurred or not.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_IT: specifies the interrupt source to check. \r
+* This parameter can be one of the following values:\r
+* - I2C_IT_SMBALERT: SMBus Alert flag\r
+* - I2C_IT_TIMEOUT: Timeout or Tlow error flag\r
+* - I2C_IT_PECERR: PEC error in reception flag\r
+* - I2C_IT_OVR: Overrun/Underrun flag (Slave mode)\r
+* - I2C_IT_AF: Acknowledge failure flag\r
+* - I2C_IT_ARLO: Arbitration lost flag (Master mode)\r
+* - I2C_IT_BERR: Bus error flag\r
+* - I2C_IT_TXE: Data register empty flag (Transmitter)\r
+* - I2C_IT_RXNE: Data register not empty (Receiver) flag\r
+* - I2C_IT_STOPF: Stop detection flag (Slave mode)\r
+* - I2C_IT_ADD10: 10-bit header sent flag (Master mode)\r
+* - I2C_IT_BTF: Byte transfer finished flag\r
+* - I2C_IT_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+* Address matched flag (Slave mode)\94ENDAD\94\r
+* - I2C_IT_SB: Start bit flag (Master mode)\r
+* Output : None\r
+* Return : The new state of I2C_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ u32 i2cstatus = 0;\r
+ u32 flag1 = 0, flag2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_GET_IT(I2C_IT));\r
+\r
+ /* Read the I2Cx status register */\r
+ flag1 = I2Cx->SR1;\r
+ flag2 = I2Cx->SR2;\r
+ flag2 = (flag2 & FLAG_Mask) << 16;\r
+\r
+ /* Get the I2C status value */\r
+ i2cstatus = flag1 | flag2;\r
+\r
+ /* Get bit[23:0] of the flag */\r
+ I2C_IT &= FLAG_Mask;\r
+\r
+ /* Check the status of the specified I2C flag */\r
+ if ((i2cstatus & I2C_IT) != (u32)RESET)\r
+ {\r
+ /* I2C_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the I2C_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ClearITPendingBit\r
+* Description : Clears the I2Cx\92s interrupt pending bits.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_IT: specifies the interrupt pending bit to clear. \r
+* This parameter can be one of the following values:\r
+* - I2C_IT_SMBALERT: SMBus Alert flag\r
+* - I2C_IT_TIMEOUT: Timeout or Tlow error flag\r
+* - I2C_IT_PECERR: PEC error in reception flag\r
+* - I2C_IT_OVR: Overrun/Underrun flag (Slave mode)\r
+* - I2C_IT_AF: Acknowledge failure flag\r
+* - I2C_IT_ARLO: Arbitration lost flag (Master mode)\r
+* - I2C_IT_BERR: Bus error flag\r
+* - I2C_IT_STOPF: Stop detection flag (Slave mode)\r
+* - I2C_IT_ADD10: 10-bit header sent flag (Master mode)\r
+* - I2C_IT_BTF: Byte transfer finished flag\r
+* - I2C_IT_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+* Address matched flag (Slave mode)\94ENDAD\94\r
+* - I2C_IT_SB: Start bit flag (Master mode)\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT)\r
+{\r
+ u32 flagpos = 0;\r
+ u32 flagindex = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLEAR_IT(I2C_IT));\r
+\r
+ /* Get the I2C flag position */\r
+ flagpos = I2C_IT & FLAG_Mask;\r
+\r
+ /* Get the I2C flag index */\r
+ flagindex = I2C_IT >> 28;\r
+\r
+ /* Clear the flag by writing 0 */\r
+ if (flagindex == 1)\r
+ {\r
+ /* Clear the selected I2C flag */\r
+ I2Cx->SR1 = (u16)~flagpos;\r
+ }\r
+ /* Flags that need a read of the SR1 register to be cleared */\r
+ else if (flagindex == 2)\r
+ {\r
+ /* Read the SR1 register */\r
+ (void)I2Cx->SR1;\r
+ }\r
+ /* Flags that need a read of SR1 and a write on CR1 registers to be cleared */\r
+ else if (flagindex == 6)\r
+ {\r
+ /* Read the SR1 register */\r
+ (void)I2Cx->SR1;\r
+\r
+ /* Write on the CR1 register */\r
+ I2Cx->CR1 |= CR1_PE_Set;\r
+ }\r
+ /* Flags that need a read of SR1 and SR2 registers to be cleared */\r
+ else /*flagindex == 0xA*/\r
+ {\r
+ /* Read the SR1 register */\r
+ (void)I2Cx->SR1;\r
+\r
+ /* Read the SR2 register */\r
+ (void)I2Cx->SR2;\r
+ }\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_lib.c\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file provides all peripherals pointers initialization.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+#define EXT\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_lib.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+#ifdef DEBUG\r
+/*******************************************************************************\r
+* Function Name : debug\r
+* Description : This function initialize peripherals pointers.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void debug(void)\r
+{\r
+\r
+/************************************* ADC ************************************/\r
+#ifdef _ADC1\r
+ ADC1 = (ADC_TypeDef *) ADC1_BASE;\r
+#endif /*_ADC1 */\r
+\r
+#ifdef _ADC2\r
+ ADC2 = (ADC_TypeDef *) ADC2_BASE;\r
+#endif /*_ADC2 */\r
+\r
+#ifdef _ADC3\r
+ ADC3 = (ADC_TypeDef *) ADC3_BASE;\r
+#endif /*_ADC3 */\r
+\r
+/************************************* BKP ************************************/\r
+#ifdef _BKP\r
+ BKP = (BKP_TypeDef *) BKP_BASE;\r
+#endif /*_BKP */\r
+\r
+/************************************* CAN ************************************/\r
+#ifdef _CAN\r
+ CAN = (CAN_TypeDef *) CAN_BASE;\r
+#endif /*_CAN */\r
+\r
+/************************************* CRC ************************************/\r
+#ifdef _CRC\r
+ CRC = (CRC_TypeDef *) CRC_BASE;\r
+#endif /*_CRC */\r
+\r
+/************************************* DAC ************************************/\r
+#ifdef _DAC\r
+ DAC = (DAC_TypeDef *) DAC_BASE;\r
+#endif /*_DAC */\r
+\r
+/************************************* DBGMCU**********************************/\r
+#ifdef _DBGMCU\r
+ DBGMCU = (DBGMCU_TypeDef *) DBGMCU_BASE;\r
+#endif /*_DBGMCU */\r
+\r
+/************************************* DMA ************************************/\r
+#ifdef _DMA\r
+ DMA1 = (DMA_TypeDef *) DMA1_BASE;\r
+ DMA2 = (DMA_TypeDef *) DMA2_BASE;\r
+#endif /*_DMA */\r
+\r
+#ifdef _DMA1_Channel1\r
+ DMA1_Channel1 = (DMA_Channel_TypeDef *) DMA1_Channel1_BASE;\r
+#endif /*_DMA1_Channel1 */\r
+\r
+#ifdef _DMA1_Channel2\r
+ DMA1_Channel2 = (DMA_Channel_TypeDef *) DMA1_Channel2_BASE;\r
+#endif /*_DMA1_Channel2 */\r
+\r
+#ifdef _DMA1_Channel3\r
+ DMA1_Channel3 = (DMA_Channel_TypeDef *) DMA1_Channel3_BASE;\r
+#endif /*_DMA1_Channel3 */\r
+\r
+#ifdef _DMA1_Channel4\r
+ DMA1_Channel4 = (DMA_Channel_TypeDef *) DMA1_Channel4_BASE;\r
+#endif /*_DMA1_Channel4 */\r
+\r
+#ifdef _DMA1_Channel5\r
+ DMA1_Channel5 = (DMA_Channel_TypeDef *) DMA1_Channel5_BASE;\r
+#endif /*_DMA1_Channel5 */\r
+\r
+#ifdef _DMA1_Channel6\r
+ DMA1_Channel6 = (DMA_Channel_TypeDef *) DMA1_Channel6_BASE;\r
+#endif /*_DMA1_Channel6 */\r
+\r
+#ifdef _DMA1_Channel7\r
+ DMA1_Channel7 = (DMA_Channel_TypeDef *) DMA1_Channel7_BASE;\r
+#endif /*_DMA1_Channel7 */\r
+\r
+#ifdef _DMA2_Channel1\r
+ DMA2_Channel1 = (DMA_Channel_TypeDef *) DMA2_Channel1_BASE;\r
+#endif /*_DMA2_Channel1 */\r
+\r
+#ifdef _DMA2_Channel2\r
+ DMA2_Channel2 = (DMA_Channel_TypeDef *) DMA2_Channel2_BASE;\r
+#endif /*_DMA2_Channel2 */\r
+\r
+#ifdef _DMA2_Channel3\r
+ DMA2_Channel3 = (DMA_Channel_TypeDef *) DMA2_Channel3_BASE;\r
+#endif /*_DMA2_Channel3 */\r
+\r
+#ifdef _DMA2_Channel4\r
+ DMA2_Channel4 = (DMA_Channel_TypeDef *) DMA2_Channel4_BASE;\r
+#endif /*_DMA2_Channel4 */\r
+\r
+#ifdef _DMA2_Channel5\r
+ DMA2_Channel5 = (DMA_Channel_TypeDef *) DMA2_Channel5_BASE;\r
+#endif /*_DMA2_Channel5 */\r
+\r
+/************************************* EXTI ***********************************/\r
+#ifdef _EXTI\r
+ EXTI = (EXTI_TypeDef *) EXTI_BASE;\r
+#endif /*_EXTI */\r
+\r
+/************************************* FLASH and Option Bytes *****************/\r
+#ifdef _FLASH\r
+ FLASH = (FLASH_TypeDef *) FLASH_R_BASE;\r
+ OB = (OB_TypeDef *) OB_BASE;\r
+#endif /*_FLASH */\r
+\r
+/************************************* FSMC ***********************************/\r
+#ifdef _FSMC\r
+ FSMC_Bank1 = (FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE;\r
+ FSMC_Bank1E = (FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE; \r
+ FSMC_Bank2 = (FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE; \r
+ FSMC_Bank3 = (FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE;\r
+ FSMC_Bank4 = (FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE;\r
+#endif /*_FSMC */\r
+\r
+/************************************* GPIO ***********************************/\r
+#ifdef _GPIOA\r
+ GPIOA = (GPIO_TypeDef *) GPIOA_BASE;\r
+#endif /*_GPIOA */\r
+\r
+#ifdef _GPIOB\r
+ GPIOB = (GPIO_TypeDef *) GPIOB_BASE;\r
+#endif /*_GPIOB */\r
+\r
+#ifdef _GPIOC\r
+ GPIOC = (GPIO_TypeDef *) GPIOC_BASE;\r
+#endif /*_GPIOC */\r
+\r
+#ifdef _GPIOD\r
+ GPIOD = (GPIO_TypeDef *) GPIOD_BASE;\r
+#endif /*_GPIOD */\r
+\r
+#ifdef _GPIOE\r
+ GPIOE = (GPIO_TypeDef *) GPIOE_BASE;\r
+#endif /*_GPIOE */\r
+\r
+#ifdef _GPIOF\r
+ GPIOF = (GPIO_TypeDef *) GPIOF_BASE;\r
+#endif /*_GPIOF */\r
+\r
+#ifdef _GPIOG\r
+ GPIOG = (GPIO_TypeDef *) GPIOG_BASE;\r
+#endif /*_GPIOG */\r
+\r
+#ifdef _AFIO\r
+ AFIO = (AFIO_TypeDef *) AFIO_BASE;\r
+#endif /*_AFIO */\r
+\r
+/************************************* I2C ************************************/\r
+#ifdef _I2C1\r
+ I2C1 = (I2C_TypeDef *) I2C1_BASE;\r
+#endif /*_I2C1 */\r
+\r
+#ifdef _I2C2\r
+ I2C2 = (I2C_TypeDef *) I2C2_BASE;\r
+#endif /*_I2C2 */\r
+\r
+/************************************* IWDG ***********************************/\r
+#ifdef _IWDG\r
+ IWDG = (IWDG_TypeDef *) IWDG_BASE;\r
+#endif /*_IWDG */\r
+\r
+/************************************* NVIC ***********************************/\r
+#ifdef _NVIC\r
+ NVIC = (NVIC_TypeDef *) NVIC_BASE;\r
+ SCB = (SCB_TypeDef *) SCB_BASE;\r
+#endif /*_NVIC */\r
+\r
+/************************************* PWR ************************************/\r
+#ifdef _PWR\r
+ PWR = (PWR_TypeDef *) PWR_BASE;\r
+#endif /*_PWR */\r
+\r
+/************************************* RCC ************************************/\r
+#ifdef _RCC\r
+ RCC = (RCC_TypeDef *) RCC_BASE;\r
+#endif /*_RCC */\r
+\r
+/************************************* RTC ************************************/\r
+#ifdef _RTC\r
+ RTC = (RTC_TypeDef *) RTC_BASE;\r
+#endif /*_RTC */\r
+\r
+/************************************* SDIO ***********************************/\r
+#ifdef _SDIO\r
+ SDIO = (SDIO_TypeDef *) SDIO_BASE;\r
+#endif /*_SDIO */\r
+\r
+/************************************* SPI ************************************/\r
+#ifdef _SPI1\r
+ SPI1 = (SPI_TypeDef *) SPI1_BASE;\r
+#endif /*_SPI1 */\r
+\r
+#ifdef _SPI2\r
+ SPI2 = (SPI_TypeDef *) SPI2_BASE;\r
+#endif /*_SPI2 */\r
+\r
+#ifdef _SPI3\r
+ SPI3 = (SPI_TypeDef *) SPI3_BASE;\r
+#endif /*_SPI3 */\r
+\r
+/************************************* SysTick ********************************/\r
+#ifdef _SysTick\r
+ SysTick = (SysTick_TypeDef *) SysTick_BASE;\r
+#endif /*_SysTick */\r
+\r
+/************************************* TIM ************************************/\r
+#ifdef _TIM1\r
+ TIM1 = (TIM_TypeDef *) TIM1_BASE;\r
+#endif /*_TIM1 */\r
+\r
+#ifdef _TIM2\r
+ TIM2 = (TIM_TypeDef *) TIM2_BASE;\r
+#endif /*_TIM2 */\r
+\r
+#ifdef _TIM3\r
+ TIM3 = (TIM_TypeDef *) TIM3_BASE;\r
+#endif /*_TIM3 */\r
+\r
+#ifdef _TIM4\r
+ TIM4 = (TIM_TypeDef *) TIM4_BASE;\r
+#endif /*_TIM4 */\r
+\r
+#ifdef _TIM5\r
+ TIM5 = (TIM_TypeDef *) TIM5_BASE;\r
+#endif /*_TIM5 */\r
+\r
+#ifdef _TIM6\r
+ TIM6 = (TIM_TypeDef *) TIM6_BASE;\r
+#endif /*_TIM6 */\r
+\r
+#ifdef _TIM7\r
+ TIM7 = (TIM_TypeDef *) TIM7_BASE;\r
+#endif /*_TIM7 */\r
+\r
+#ifdef _TIM8\r
+ TIM8 = (TIM_TypeDef *) TIM8_BASE;\r
+#endif /*_TIM8 */\r
+\r
+/************************************* USART **********************************/\r
+#ifdef _USART1\r
+ USART1 = (USART_TypeDef *) USART1_BASE;\r
+#endif /*_USART1 */\r
+\r
+#ifdef _USART2\r
+ USART2 = (USART_TypeDef *) USART2_BASE;\r
+#endif /*_USART2 */\r
+\r
+#ifdef _USART3\r
+ USART3 = (USART_TypeDef *) USART3_BASE;\r
+#endif /*_USART3 */\r
+\r
+#ifdef _UART4\r
+ UART4 = (USART_TypeDef *) UART4_BASE;\r
+#endif /*_UART4 */\r
+\r
+#ifdef _UART5\r
+ UART5 = (USART_TypeDef *) UART5_BASE;\r
+#endif /*_UART5 */\r
+\r
+/************************************* WWDG ***********************************/\r
+#ifdef _WWDG\r
+ WWDG = (WWDG_TypeDef *) WWDG_BASE;\r
+#endif /*_WWDG */\r
+}\r
+#endif /* DEBUG*/\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_nvic.c\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file provides all the NVIC firmware functions.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_nvic.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define AIRCR_VECTKEY_MASK ((u32)0x05FA0000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_DeInit\r
+* Description : Deinitializes the NVIC peripheral registers to their default\r
+* reset values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_DeInit(void)\r
+{\r
+ u32 index = 0;\r
+ \r
+ NVIC->ICER[0] = 0xFFFFFFFF;\r
+ NVIC->ICER[1] = 0x0FFFFFFF;\r
+ NVIC->ICPR[0] = 0xFFFFFFFF;\r
+ NVIC->ICPR[1] = 0x0FFFFFFF;\r
+ \r
+ for(index = 0; index < 0x0F; index++)\r
+ {\r
+ NVIC->IPR[index] = 0x00000000;\r
+ } \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SCBDeInit\r
+* Description : Deinitializes the SCB peripheral registers to their default \r
+* reset values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SCBDeInit(void)\r
+{\r
+ u32 index = 0x00;\r
+ \r
+ SCB->ICSR = 0x0A000000;\r
+ SCB->VTOR = 0x00000000;\r
+ SCB->AIRCR = AIRCR_VECTKEY_MASK;\r
+ SCB->SCR = 0x00000000;\r
+ SCB->CCR = 0x00000000;\r
+ for(index = 0; index < 0x03; index++)\r
+ {\r
+ SCB->SHPR[index] = 0;\r
+ }\r
+ SCB->SHCSR = 0x00000000;\r
+ SCB->CFSR = 0xFFFFFFFF;\r
+ SCB->HFSR = 0xFFFFFFFF;\r
+ SCB->DFSR = 0xFFFFFFFF;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_PriorityGroupConfig\r
+* Description : Configures the priority grouping: pre-emption priority\r
+* and subpriority.\r
+* Input : - NVIC_PriorityGroup: specifies the priority grouping bits\r
+* length. This parameter can be one of the following values:\r
+* - NVIC_PriorityGroup_0: 0 bits for pre-emption priority\r
+* 4 bits for subpriority\r
+* - NVIC_PriorityGroup_1: 1 bits for pre-emption priority\r
+* 3 bits for subpriority\r
+* - NVIC_PriorityGroup_2: 2 bits for pre-emption priority\r
+* 2 bits for subpriority\r
+* - NVIC_PriorityGroup_3: 3 bits for pre-emption priority\r
+* 1 bits for subpriority\r
+* - NVIC_PriorityGroup_4: 4 bits for pre-emption priority\r
+* 0 bits for subpriority\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r
+ \r
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_Init\r
+* Description : Initializes the NVIC peripheral according to the specified\r
+* parameters in the NVIC_InitStruct.\r
+* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure\r
+* that contains the configuration information for the\r
+* specified NVIC peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
+{\r
+ u32 tmppriority = 0x00, tmpreg = 0x00, tmpmask = 0x00;\r
+ u32 tmppre = 0, tmpsub = 0x0F;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
+ assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_InitStruct->NVIC_IRQChannel));\r
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); \r
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r
+ \r
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
+ {\r
+ /* Compute the Corresponding IRQ Priority --------------------------------*/ \r
+ tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08;\r
+ tmppre = (0x4 - tmppriority);\r
+ tmpsub = tmpsub >> tmppriority;\r
+ \r
+ tmppriority = (u32)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;\r
+\r
+ tmppriority = tmppriority << 0x04;\r
+ tmppriority = ((u32)tmppriority) << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);\r
+ \r
+ tmpreg = NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)];\r
+ tmpmask = (u32)0xFF << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);\r
+ tmpreg &= ~tmpmask;\r
+ tmppriority &= tmpmask; \r
+ tmpreg |= tmppriority;\r
+\r
+ NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)] = tmpreg;\r
+ \r
+ /* Enable the Selected IRQ Channels --------------------------------------*/\r
+ NVIC->ISER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =\r
+ (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Selected IRQ Channels -------------------------------------*/\r
+ NVIC->ICER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =\r
+ (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_StructInit\r
+* Description : Fills each NVIC_InitStruct member with its default value.\r
+* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure which\r
+* will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct)\r
+{\r
+ /* NVIC_InitStruct members default value */\r
+ NVIC_InitStruct->NVIC_IRQChannel = 0x00;\r
+ NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00;\r
+ NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00;\r
+ NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SETPRIMASK\r
+* Description : Enables the PRIMASK priority: Raises the execution priority to 0.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SETPRIMASK(void)\r
+{\r
+ __SETPRIMASK();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_RESETPRIMASK\r
+* Description : Disables the PRIMASK priority.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_RESETPRIMASK(void)\r
+{\r
+ __RESETPRIMASK();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SETFAULTMASK\r
+* Description : Enables the FAULTMASK priority: Raises the execution priority to -1.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SETFAULTMASK(void)\r
+{\r
+ __SETFAULTMASK();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_RESETFAULTMASK\r
+* Description : Disables the FAULTMASK priority.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_RESETFAULTMASK(void)\r
+{\r
+ __RESETFAULTMASK();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_BASEPRICONFIG\r
+* Description : The execution priority can be changed from 15 (lowest \r
+ configurable priority) to 1. Writing a zero value will disable \r
+* the mask of execution priority.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_BASEPRICONFIG(u32 NewPriority)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_BASE_PRI(NewPriority));\r
+ \r
+ __BASEPRICONFIG(NewPriority << 0x04);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetBASEPRI\r
+* Description : Returns the BASEPRI mask value.\r
+* Input : None\r
+* Output : None\r
+* Return : BASEPRI register value\r
+*******************************************************************************/\r
+u32 NVIC_GetBASEPRI(void)\r
+{\r
+ return (__GetBASEPRI());\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetCurrentPendingIRQChannel\r
+* Description : Returns the current pending IRQ channel identifier.\r
+* Input : None\r
+* Output : None\r
+* Return : Pending IRQ Channel Identifier.\r
+*******************************************************************************/\r
+u16 NVIC_GetCurrentPendingIRQChannel(void)\r
+{\r
+ return ((u16)((SCB->ICSR & (u32)0x003FF000) >> 0x0C));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetIRQChannelPendingBitStatus\r
+* Description : Checks whether the specified IRQ Channel pending bit is set\r
+* or not.\r
+* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to check.\r
+* Output : None\r
+* Return : The new state of IRQ Channel pending bit(SET or RESET).\r
+*******************************************************************************/\r
+ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel)\r
+{\r
+ ITStatus pendingirqstatus = RESET;\r
+ u32 tmp = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));\r
+ \r
+ tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));\r
+\r
+ if (((NVIC->ISPR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp)\r
+ {\r
+ pendingirqstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ pendingirqstatus = RESET;\r
+ }\r
+ return pendingirqstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SetIRQChannelPendingBit\r
+* Description : Sets the NVIC\92s interrupt pending bit.\r
+* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to Set.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));\r
+ \r
+ *(vu32*) 0xE000EF00 = (u32)NVIC_IRQChannel;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_ClearIRQChannelPendingBit\r
+* Description : Clears the NVIC\92s interrupt pending bit.\r
+* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to clear.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));\r
+ \r
+ NVIC->ICPR[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetCurrentActiveHandler\r
+* Description : Returns the current active Handler (IRQ Channel and\r
+* SystemHandler) identifier.\r
+* Input : None\r
+* Output : None\r
+* Return : Active Handler Identifier.\r
+*******************************************************************************/\r
+u16 NVIC_GetCurrentActiveHandler(void)\r
+{\r
+ return ((u16)(SCB->ICSR & (u32)0x3FF));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetIRQChannelActiveBitStatus\r
+* Description : Checks whether the specified IRQ Channel active bit is set\r
+* or not.\r
+* Input : - NVIC_IRQChannel: specifies the interrupt active bit to check.\r
+* Output : None\r
+* Return : The new state of IRQ Channel active bit(SET or RESET).\r
+*******************************************************************************/\r
+ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel)\r
+{\r
+ ITStatus activeirqstatus = RESET;\r
+ u32 tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));\r
+ \r
+ tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));\r
+\r
+ if (((NVIC->IABR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp )\r
+ {\r
+ activeirqstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ activeirqstatus = RESET;\r
+ }\r
+ return activeirqstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetCPUID\r
+* Description : Returns the ID number, the version number and the implementation\r
+* details of the Cortex-M3 core.\r
+* Input : None\r
+* Output : None\r
+* Return : CPU ID.\r
+*******************************************************************************/\r
+u32 NVIC_GetCPUID(void)\r
+{\r
+ return (SCB->CPUID);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SetVectorTable\r
+* Description : Sets the vector table location and Offset.\r
+* Input : - NVIC_VectTab: specifies if the vector table is in RAM or\r
+* FLASH memory.\r
+* This parameter can be one of the following values:\r
+* - NVIC_VectTab_RAM\r
+* - NVIC_VectTab_FLASH\r
+* - Offset: Vector Table base offset field. \r
+* This value must be a multiple of 0x100.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));\r
+ assert_param(IS_NVIC_OFFSET(Offset)); \r
+ \r
+ SCB->VTOR = NVIC_VectTab | (Offset & (u32)0x1FFFFF80);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GenerateSystemReset\r
+* Description : Generates a system reset.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_GenerateSystemReset(void)\r
+{\r
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x04;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GenerateCoreReset\r
+* Description : Generates a Core (Core + NVIC) reset.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_GenerateCoreReset(void)\r
+{\r
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x01;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SystemLPConfig\r
+* Description : Selects the condition for the system to enter low power mode.\r
+* Input : - LowPowerMode: Specifies the new mode for the system to enter\r
+* low power mode.\r
+* This parameter can be one of the following values:\r
+* - NVIC_LP_SEVONPEND\r
+* - NVIC_LP_SLEEPDEEP\r
+* - NVIC_LP_SLEEPONEXIT\r
+* - NewState: new state of LP condition.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_LP(LowPowerMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ SCB->SCR |= LowPowerMode;\r
+ }\r
+ else\r
+ {\r
+ SCB->SCR &= (u32)(~(u32)LowPowerMode);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SystemHandlerConfig\r
+* Description : Enables or disables the specified System Handlers.\r
+* Input : - SystemHandler: specifies the system handler to be enabled\r
+* or disabled.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_MemoryManage\r
+* - SystemHandler_BusFault\r
+* - SystemHandler_UsageFault\r
+* - NewState: new state of specified System Handlers.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState)\r
+{\r
+ u32 tmpreg = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CONFIG_SYSTEM_HANDLER(SystemHandler));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ tmpreg = (u32)0x01 << (SystemHandler & (u32)0x1F);\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ SCB->SHCSR |= tmpreg;\r
+ }\r
+ else\r
+ {\r
+ SCB->SHCSR &= ~tmpreg;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SystemHandlerPriorityConfig\r
+* Description : Configures the specified System Handlers priority.\r
+* Input : - SystemHandler: specifies the system handler to be\r
+* enabled or disabled.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_MemoryManage\r
+* - SystemHandler_BusFault\r
+* - SystemHandler_UsageFault\r
+* - SystemHandler_SVCall\r
+* - SystemHandler_DebugMonitor\r
+* - SystemHandler_PSV\r
+* - SystemHandler_SysTick\r
+* - SystemHandlerPreemptionPriority: new priority group of the\r
+* specified system handlers.\r
+* - SystemHandlerSubPriority: new sub priority of the specified\r
+* system handlers.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,\r
+ u8 SystemHandlerSubPriority)\r
+{\r
+ u32 tmp1 = 0x00, tmp2 = 0xFF, handlermask = 0x00;\r
+ u32 tmppriority = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_PRIORITY_SYSTEM_HANDLER(SystemHandler));\r
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(SystemHandlerPreemptionPriority)); \r
+ assert_param(IS_NVIC_SUB_PRIORITY(SystemHandlerSubPriority));\r
+ \r
+ tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08;\r
+ tmp1 = (0x4 - tmppriority);\r
+ tmp2 = tmp2 >> tmppriority;\r
+ \r
+ tmppriority = (u32)SystemHandlerPreemptionPriority << tmp1;\r
+ tmppriority |= SystemHandlerSubPriority & tmp2;\r
+\r
+ tmppriority = tmppriority << 0x04;\r
+ tmp1 = SystemHandler & (u32)0xC0;\r
+ tmp1 = tmp1 >> 0x06; \r
+ tmp2 = (SystemHandler >> 0x08) & (u32)0x03;\r
+ tmppriority = tmppriority << (tmp2 * 0x08);\r
+ handlermask = (u32)0xFF << (tmp2 * 0x08);\r
+ \r
+ SCB->SHPR[tmp1] &= ~handlermask;\r
+ SCB->SHPR[tmp1] |= tmppriority;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetSystemHandlerPendingBitStatus\r
+* Description : Checks whether the specified System handlers pending bit is\r
+* set or not.\r
+* Input : - SystemHandler: specifies the system handler pending bit to\r
+* check.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_MemoryManage\r
+* - SystemHandler_BusFault\r
+* - SystemHandler_SVCall\r
+* Output : None\r
+* Return : The new state of System Handler pending bit(SET or RESET).\r
+*******************************************************************************/\r
+ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ u32 tmp = 0x00, tmppos = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_PENDING_SYSTEM_HANDLER(SystemHandler));\r
+ \r
+ tmppos = (SystemHandler >> 0x0A);\r
+ tmppos &= (u32)0x0F;\r
+\r
+ tmppos = (u32)0x01 << tmppos;\r
+\r
+ tmp = SCB->SHCSR & tmppos;\r
+\r
+ if (tmp == tmppos)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SetSystemHandlerPendingBit\r
+* Description : Sets System Handler pending bit.\r
+* Input : - SystemHandler: specifies the system handler pending bit\r
+* to be set.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_NMI\r
+* - SystemHandler_PSV\r
+* - SystemHandler_SysTick\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler)\r
+{\r
+ u32 tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SET_PENDING_SYSTEM_HANDLER(SystemHandler));\r
+ \r
+ /* Get the System Handler pending bit position */\r
+ tmp = SystemHandler & (u32)0x1F;\r
+ /* Set the corresponding System Handler pending bit */\r
+ SCB->ICSR |= ((u32)0x01 << tmp);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_ClearSystemHandlerPendingBit\r
+* Description : Clears System Handler pending bit.\r
+* Input : - SystemHandler: specifies the system handler pending bit to\r
+* be clear.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_PSV\r
+* - SystemHandler_SysTick\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler)\r
+{\r
+ u32 tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CLEAR_SYSTEM_HANDLER(SystemHandler));\r
+ \r
+ /* Get the System Handler pending bit position */\r
+ tmp = SystemHandler & (u32)0x1F;\r
+ /* Clear the corresponding System Handler pending bit */\r
+ SCB->ICSR |= ((u32)0x01 << (tmp - 0x01));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetSystemHandlerActiveBitStatus\r
+* Description : Checks whether the specified System handlers active bit is\r
+* set or not.\r
+* Input : - SystemHandler: specifies the system handler active bit to\r
+* check.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_MemoryManage\r
+* - SystemHandler_BusFault\r
+* - SystemHandler_UsageFault\r
+* - SystemHandler_SVCall\r
+* - SystemHandler_DebugMonitor\r
+* - SystemHandler_PSV\r
+* - SystemHandler_SysTick\r
+* Output : None\r
+* Return : The new state of System Handler active bit(SET or RESET).\r
+*******************************************************************************/\r
+ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+\r
+ u32 tmp = 0x00, tmppos = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_ACTIVE_SYSTEM_HANDLER(SystemHandler));\r
+ \r
+ tmppos = (SystemHandler >> 0x0E) & (u32)0x0F;\r
+\r
+ tmppos = (u32)0x01 << tmppos;\r
+\r
+ tmp = SCB->SHCSR & tmppos;\r
+\r
+ if (tmp == tmppos)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetFaultHandlerSources\r
+* Description : Returns the system fault handlers sources.\r
+* Input : - SystemHandler: specifies the system handler to get its fault\r
+* sources.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_HardFault\r
+* - SystemHandler_MemoryManage\r
+* - SystemHandler_BusFault\r
+* - SystemHandler_UsageFault\r
+* - SystemHandler_DebugMonitor\r
+* Output : None\r
+* Return : Source of the fault handler.\r
+*******************************************************************************/\r
+u32 NVIC_GetFaultHandlerSources(u32 SystemHandler)\r
+{\r
+ u32 faultsources = 0x00;\r
+ u32 tmpreg = 0x00, tmppos = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FAULT_SOURCE_SYSTEM_HANDLER(SystemHandler));\r
+ \r
+ tmpreg = (SystemHandler >> 0x12) & (u32)0x03;\r
+ tmppos = (SystemHandler >> 0x14) & (u32)0x03;\r
+\r
+ if (tmpreg == 0x00)\r
+ {\r
+ faultsources = SCB->HFSR;\r
+ }\r
+ else if (tmpreg == 0x01)\r
+ {\r
+ faultsources = SCB->CFSR >> (tmppos * 0x08);\r
+ if (tmppos != 0x02)\r
+ {\r
+ faultsources &= (u32)0x0F;\r
+ }\r
+ else\r
+ {\r
+ faultsources &= (u32)0xFF;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ faultsources = SCB->DFSR;\r
+ }\r
+ return faultsources;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetFaultAddress\r
+* Description : Returns the address of the location that generated a fault\r
+* handler.\r
+* Input : - SystemHandler: specifies the system handler to get its\r
+* fault address.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_MemoryManage\r
+* - SystemHandler_BusFault\r
+* Output : None\r
+* Return : Fault address.\r
+*******************************************************************************/\r
+u32 NVIC_GetFaultAddress(u32 SystemHandler)\r
+{\r
+ u32 faultaddress = 0x00;\r
+ u32 tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FAULT_ADDRESS_SYSTEM_HANDLER(SystemHandler));\r
+ \r
+ tmp = (SystemHandler >> 0x16) & (u32)0x01;\r
+\r
+ if (tmp == 0x00)\r
+ {\r
+ faultaddress = SCB->MMFAR;\r
+ }\r
+ else\r
+ {\r
+ faultaddress = SCB->BFAR;\r
+ }\r
+ return faultaddress;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_rcc.c\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file provides all the RCC firmware functions.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ------------ RCC registers bit address in the alias region ----------- */\r
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+/* Alias word address of HSION bit */\r
+#define CR_OFFSET (RCC_OFFSET + 0x00)\r
+#define HSION_BitNumber 0x00\r
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))\r
+\r
+/* Alias word address of PLLON bit */\r
+#define PLLON_BitNumber 0x18\r
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))\r
+\r
+/* Alias word address of CSSON bit */\r
+#define CSSON_BitNumber 0x13\r
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))\r
+\r
+/* --- CFGR Register ---*/\r
+/* Alias word address of USBPRE bit */\r
+#define CFGR_OFFSET (RCC_OFFSET + 0x04)\r
+#define USBPRE_BitNumber 0x16\r
+#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))\r
+\r
+/* --- BDCR Register ---*/\r
+/* Alias word address of RTCEN bit */\r
+#define BDCR_OFFSET (RCC_OFFSET + 0x20)\r
+#define RTCEN_BitNumber 0x0F\r
+#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))\r
+\r
+/* Alias word address of BDRST bit */\r
+#define BDRST_BitNumber 0x10\r
+#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+/* Alias word address of LSION bit */\r
+#define CSR_OFFSET (RCC_OFFSET + 0x24)\r
+#define LSION_BitNumber 0x00\r
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))\r
+\r
+/* ---------------------- RCC registers bit mask ------------------------ */\r
+/* CR register bit mask */\r
+#define CR_HSEBYP_Reset ((u32)0xFFFBFFFF)\r
+#define CR_HSEBYP_Set ((u32)0x00040000)\r
+#define CR_HSEON_Reset ((u32)0xFFFEFFFF)\r
+#define CR_HSEON_Set ((u32)0x00010000)\r
+#define CR_HSITRIM_Mask ((u32)0xFFFFFF07)\r
+\r
+/* CFGR register bit mask */\r
+#define CFGR_PLL_Mask ((u32)0xFFC0FFFF)\r
+#define CFGR_PLLMull_Mask ((u32)0x003C0000)\r
+#define CFGR_PLLSRC_Mask ((u32)0x00010000)\r
+#define CFGR_PLLXTPRE_Mask ((u32)0x00020000)\r
+#define CFGR_SWS_Mask ((u32)0x0000000C)\r
+#define CFGR_SW_Mask ((u32)0xFFFFFFFC)\r
+#define CFGR_HPRE_Reset_Mask ((u32)0xFFFFFF0F)\r
+#define CFGR_HPRE_Set_Mask ((u32)0x000000F0)\r
+#define CFGR_PPRE1_Reset_Mask ((u32)0xFFFFF8FF)\r
+#define CFGR_PPRE1_Set_Mask ((u32)0x00000700)\r
+#define CFGR_PPRE2_Reset_Mask ((u32)0xFFFFC7FF)\r
+#define CFGR_PPRE2_Set_Mask ((u32)0x00003800)\r
+#define CFGR_ADCPRE_Reset_Mask ((u32)0xFFFF3FFF)\r
+#define CFGR_ADCPRE_Set_Mask ((u32)0x0000C000)\r
+\r
+/* CSR register bit mask */\r
+#define CSR_RMVF_Set ((u32)0x01000000)\r
+\r
+/* RCC Flag Mask */\r
+#define FLAG_Mask ((u8)0x1F)\r
+\r
+/* Typical Value of the HSI in Hz */\r
+#define HSI_Value ((u32)8000000)\r
+\r
+/* CIR register byte 2 (Bits[15:8]) base address */\r
+#define CIR_BYTE2_ADDRESS ((u32)0x40021009)\r
+/* CIR register byte 3 (Bits[23:16]) base address */\r
+#define CIR_BYTE3_ADDRESS ((u32)0x4002100A)\r
+\r
+/* CFGR register byte 4 (Bits[31:24]) base address */\r
+#define CFGR_BYTE4_ADDRESS ((u32)0x40021007)\r
+\r
+/* BDCR register base address */\r
+#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)\r
+\r
+/* Time out for HSE start up */\r
+#define HSEStartUp_TimeOut ((u16)0x01FF)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
+static uc8 ADCPrescTable[4] = {2, 4, 6, 8};\r
+\r
+static volatile FlagStatus HSEStatus;\r
+static vu32 StartUpCounter = 0;\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_DeInit\r
+* Description : Resets the RCC clock configuration to the default reset state.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_DeInit(void)\r
+{\r
+ /* Set HSION bit */\r
+ RCC->CR |= (u32)0x00000001;\r
+\r
+ /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */\r
+ RCC->CFGR &= (u32)0xF8FF0000;\r
+ \r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (u32)0xFEF6FFFF;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (u32)0xFFFBFFFF;\r
+\r
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */\r
+ RCC->CFGR &= (u32)0xFF80FFFF;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_HSEConfig\r
+* Description : Configures the External High Speed oscillator (HSE).\r
+* HSE can not be stopped if it is used directly or through the \r
+* PLL as system clock.\r
+* Input : - RCC_HSE: specifies the new state of the HSE.\r
+* This parameter can be one of the following values:\r
+* - RCC_HSE_OFF: HSE oscillator OFF\r
+* - RCC_HSE_ON: HSE oscillator ON\r
+* - RCC_HSE_Bypass: HSE oscillator bypassed with external\r
+* clock\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_HSEConfig(u32 RCC_HSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSE(RCC_HSE));\r
+\r
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r
+ /* Reset HSEON bit */\r
+ RCC->CR &= CR_HSEON_Reset;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= CR_HSEBYP_Reset;\r
+\r
+ /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */\r
+ switch(RCC_HSE)\r
+ {\r
+ case RCC_HSE_ON:\r
+ /* Set HSEON bit */\r
+ RCC->CR |= CR_HSEON_Set;\r
+ break;\r
+ \r
+ case RCC_HSE_Bypass:\r
+ /* Set HSEBYP and HSEON bits */\r
+ RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;\r
+ break; \r
+ \r
+ default:\r
+ break; \r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_WaitForHSEStartUp\r
+* Description : Waits for HSE start-up.\r
+* Input : None\r
+* Output : None\r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: HSE oscillator is stable and ready to use\r
+* - ERROR: HSE oscillator not yet ready\r
+*******************************************************************************/\r
+ErrorStatus RCC_WaitForHSEStartUp(void)\r
+{\r
+ ErrorStatus status = ERROR;\r
+\r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r
+ StartUpCounter++; \r
+ } while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+\r
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ } \r
+\r
+ return (status);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_AdjustHSICalibrationValue\r
+* Description : Adjusts the Internal High Speed oscillator (HSI) calibration\r
+* value.\r
+* Input : - HSICalibrationValue: specifies the calibration trimming value.\r
+* This parameter must be a number between 0 and 0x1F.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));\r
+\r
+ tmpreg = RCC->CR;\r
+\r
+ /* Clear HSITRIM[4:0] bits */\r
+ tmpreg &= CR_HSITRIM_Mask;\r
+\r
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r
+ tmpreg |= (u32)HSICalibrationValue << 3;\r
+\r
+ /* Store the new value */\r
+ RCC->CR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_HSICmd\r
+* Description : Enables or disables the Internal High Speed oscillator (HSI).\r
+* HSI can not be stopped if it is used directly or through the \r
+* PLL as system clock.\r
+* Input : - NewState: new state of the HSI.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_HSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) CR_HSION_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_PLLConfig\r
+* Description : Configures the PLL clock source and multiplication factor.\r
+* This function must be used only when the PLL is disabled.\r
+* Input : - RCC_PLLSource: specifies the PLL entry clock source.\r
+* This parameter can be one of the following values:\r
+* - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided\r
+* by 2 selected as PLL clock entry\r
+* - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected\r
+* as PLL clock entry\r
+* - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided\r
+* by 2 selected as PLL clock entry\r
+* - RCC_PLLMul: specifies the PLL multiplication factor.\r
+* This parameter can be RCC_PLLMul_x where x:[2,16]\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */\r
+ tmpreg &= CFGR_PLL_Mask;\r
+\r
+ /* Set the PLL configuration bits */\r
+ tmpreg |= RCC_PLLSource | RCC_PLLMul;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_PLLCmd\r
+* Description : Enables or disables the PLL.\r
+* The PLL can not be disabled if it is used as system clock.\r
+* Input : - NewState: new state of the PLL.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_PLLCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) CR_PLLON_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_SYSCLKConfig\r
+* Description : Configures the system clock (SYSCLK).\r
+* Input : - RCC_SYSCLKSource: specifies the clock source used as system\r
+* clock. This parameter can be one of the following values:\r
+* - RCC_SYSCLKSource_HSI: HSI selected as system clock\r
+* - RCC_SYSCLKSource_HSE: HSE selected as system clock\r
+* - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear SW[1:0] bits */\r
+ tmpreg &= CFGR_SW_Mask;\r
+\r
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
+ tmpreg |= RCC_SYSCLKSource;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_GetSYSCLKSource\r
+* Description : Returns the clock source used as system clock.\r
+* Input : None\r
+* Output : None\r
+* Return : The clock source used as system clock. The returned value can\r
+* be one of the following:\r
+* - 0x00: HSI used as system clock\r
+* - 0x04: HSE used as system clock\r
+* - 0x08: PLL used as system clock\r
+*******************************************************************************/\r
+u8 RCC_GetSYSCLKSource(void)\r
+{\r
+ return ((u8)(RCC->CFGR & CFGR_SWS_Mask));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_HCLKConfig\r
+* Description : Configures the AHB clock (HCLK).\r
+* Input : - RCC_SYSCLK: defines the AHB clock divider. This clock is\r
+* derived from the system clock (SYSCLK).\r
+* This parameter can be one of the following values:\r
+* - RCC_SYSCLK_Div1: AHB clock = SYSCLK\r
+* - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2\r
+* - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4\r
+* - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8\r
+* - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16\r
+* - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64\r
+* - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r
+* - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r
+* - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_HCLKConfig(u32 RCC_SYSCLK)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear HPRE[3:0] bits */\r
+ tmpreg &= CFGR_HPRE_Reset_Mask;\r
+\r
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r
+ tmpreg |= RCC_SYSCLK;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_PCLK1Config\r
+* Description : Configures the Low Speed APB clock (PCLK1).\r
+* Input : - RCC_HCLK: defines the APB1 clock divider. This clock is\r
+* derived from the AHB clock (HCLK).\r
+* This parameter can be one of the following values:\r
+* - RCC_HCLK_Div1: APB1 clock = HCLK\r
+* - RCC_HCLK_Div2: APB1 clock = HCLK/2\r
+* - RCC_HCLK_Div4: APB1 clock = HCLK/4\r
+* - RCC_HCLK_Div8: APB1 clock = HCLK/8\r
+* - RCC_HCLK_Div16: APB1 clock = HCLK/16\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_PCLK1Config(u32 RCC_HCLK)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear PPRE1[2:0] bits */\r
+ tmpreg &= CFGR_PPRE1_Reset_Mask;\r
+\r
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_PCLK2Config\r
+* Description : Configures the High Speed APB clock (PCLK2).\r
+* Input : - RCC_HCLK: defines the APB2 clock divider. This clock is\r
+* derived from the AHB clock (HCLK).\r
+* This parameter can be one of the following values:\r
+* - RCC_HCLK_Div1: APB2 clock = HCLK\r
+* - RCC_HCLK_Div2: APB2 clock = HCLK/2\r
+* - RCC_HCLK_Div4: APB2 clock = HCLK/4\r
+* - RCC_HCLK_Div8: APB2 clock = HCLK/8\r
+* - RCC_HCLK_Div16: APB2 clock = HCLK/16\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_PCLK2Config(u32 RCC_HCLK)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear PPRE2[2:0] bits */\r
+ tmpreg &= CFGR_PPRE2_Reset_Mask;\r
+\r
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK << 3;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_ITConfig\r
+* Description : Enables or disables the specified RCC interrupts.\r
+* Input : - RCC_IT: specifies the RCC interrupt sources to be enabled\r
+* or disabled.\r
+* This parameter can be any combination of the following values:\r
+* - RCC_IT_LSIRDY: LSI ready interrupt\r
+* - RCC_IT_LSERDY: LSE ready interrupt\r
+* - RCC_IT_HSIRDY: HSI ready interrupt\r
+* - RCC_IT_HSERDY: HSE ready interrupt\r
+* - RCC_IT_PLLRDY: PLL ready interrupt\r
+* - NewState: new state of the specified RCC interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_IT(RCC_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */\r
+ *(vu8 *) CIR_BYTE2_ADDRESS |= RCC_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */\r
+ *(vu8 *) CIR_BYTE2_ADDRESS &= (u8)~RCC_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_USBCLKConfig\r
+* Description : Configures the USB clock (USBCLK).\r
+* Input : - RCC_USBCLKSource: specifies the USB clock source. This clock\r
+* is derived from the PLL output.\r
+* This parameter can be one of the following values:\r
+* - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5\r
+* selected as USB clock source\r
+* - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB\r
+* clock source\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_USBCLKConfig(u32 RCC_USBCLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));\r
+\r
+ *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_ADCCLKConfig\r
+* Description : Configures the ADC clock (ADCCLK).\r
+* Input : - RCC_PCLK2: defines the ADC clock divider. This clock is\r
+* derived from the APB2 clock (PCLK2).\r
+* This parameter can be one of the following values:\r
+* - RCC_PCLK2_Div2: ADC clock = PCLK2/2\r
+* - RCC_PCLK2_Div4: ADC clock = PCLK2/4\r
+* - RCC_PCLK2_Div6: ADC clock = PCLK2/6\r
+* - RCC_PCLK2_Div8: ADC clock = PCLK2/8\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_ADCCLKConfig(u32 RCC_PCLK2)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_ADCCLK(RCC_PCLK2));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear ADCPRE[1:0] bits */\r
+ tmpreg &= CFGR_ADCPRE_Reset_Mask;\r
+\r
+ /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */\r
+ tmpreg |= RCC_PCLK2;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_LSEConfig\r
+* Description : Configures the External Low Speed oscillator (LSE).\r
+* Input : - RCC_LSE: specifies the new state of the LSE.\r
+* This parameter can be one of the following values:\r
+* - RCC_LSE_OFF: LSE oscillator OFF\r
+* - RCC_LSE_ON: LSE oscillator ON\r
+* - RCC_LSE_Bypass: LSE oscillator bypassed with external\r
+* clock\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_LSEConfig(u8 RCC_LSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE(RCC_LSE));\r
+\r
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
+ /* Reset LSEON bit */\r
+ *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;\r
+\r
+ /* Reset LSEBYP bit */\r
+ *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;\r
+\r
+ /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */\r
+ switch(RCC_LSE)\r
+ {\r
+ case RCC_LSE_ON:\r
+ /* Set LSEON bit */\r
+ *(vu8 *) BDCR_ADDRESS = RCC_LSE_ON;\r
+ break;\r
+ \r
+ case RCC_LSE_Bypass:\r
+ /* Set LSEBYP and LSEON bits */\r
+ *(vu8 *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;\r
+ break; \r
+ \r
+ default:\r
+ break; \r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_LSICmd\r
+* Description : Enables or disables the Internal Low Speed oscillator (LSI).\r
+* LSI can not be disabled if the IWDG is running.\r
+* Input : - NewState: new state of the LSI.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_LSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) CSR_LSION_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_RTCCLKConfig\r
+* Description : Configures the RTC clock (RTCCLK).\r
+* Once the RTC clock is selected it can\92t be changed unless the\r
+* Backup domain is reset.\r
+* Input : - RCC_RTCCLKSource: specifies the RTC clock source.\r
+* This parameter can be one of the following values:\r
+* - RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r
+* - RCC_RTCCLKSource_LSI: LSI selected as RTC clock\r
+* - RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128\r
+* selected as RTC clock\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
+\r
+ /* Select the RTC clock source */\r
+ RCC->BDCR |= RCC_RTCCLKSource;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_RTCCLKCmd\r
+* Description : Enables or disables the RTC clock.\r
+* This function must be used only after the RTC clock was\r
+* selected using the RCC_RTCCLKConfig function.\r
+* Input : - NewState: new state of the RTC clock.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_RTCCLKCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_GetClocksFreq\r
+* Description : Returns the frequencies of different on chip clocks.\r
+* Input : - RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which\r
+* will hold the clocks frequencies.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
+{\r
+ u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & CFGR_SWS_Mask;\r
+\r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_Value;\r
+ break;\r
+\r
+ case 0x04: /* HSE used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSE_Value;\r
+ break;\r
+\r
+ case 0x08: /* PLL used as system clock */\r
+ /* Get PLL clock source and multiplication factor ----------------------*/\r
+ pllmull = RCC->CFGR & CFGR_PLLMull_Mask;\r
+ pllmull = ( pllmull >> 18) + 2;\r
+\r
+ pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;\r
+\r
+ if (pllsource == 0x00)\r
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;\r
+ }\r
+ else\r
+ {/* HSE selected as PLL clock entry */\r
+\r
+ if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)\r
+ {/* HSE oscillator clock divided by 2 */\r
+\r
+ RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;\r
+ }\r
+ else\r
+ {\r
+ RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;\r
+ }\r
+ }\r
+ break;\r
+\r
+ default:\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_Value;\r
+ break;\r
+ }\r
+\r
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;\r
+ tmp = tmp >> 4;\r
+ presc = APBAHBPrescTable[tmp];\r
+\r
+ /* HCLK clock frequency */\r
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
+\r
+ /* Get PCLK1 prescaler */\r
+ tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;\r
+ tmp = tmp >> 8;\r
+ presc = APBAHBPrescTable[tmp];\r
+\r
+ /* PCLK1 clock frequency */\r
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+\r
+ /* Get PCLK2 prescaler */\r
+ tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;\r
+ tmp = tmp >> 11;\r
+ presc = APBAHBPrescTable[tmp];\r
+\r
+ /* PCLK2 clock frequency */\r
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+\r
+ /* Get ADCCLK prescaler */\r
+ tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;\r
+ tmp = tmp >> 14;\r
+ presc = ADCPrescTable[tmp];\r
+\r
+ /* ADCCLK clock frequency */\r
+ RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_AHBPeriphClockCmd\r
+* Description : Enables or disables the AHB peripheral clock.\r
+* Input : - RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+* This parameter can be any combination of the following values:\r
+* - RCC_AHBPeriph_DMA1\r
+* - RCC_AHBPeriph_DMA2\r
+* - RCC_AHBPeriph_SRAM\r
+* - RCC_AHBPeriph_FLITF\r
+* - RCC_AHBPeriph_CRC\r
+* - RCC_AHBPeriph_FSMC\r
+* - RCC_AHBPeriph_SDIO\r
+* SRAM and FLITF clock can be disabled only during sleep mode.\r
+* - NewState: new state of the specified peripheral clock.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBENR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBENR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_APB2PeriphClockCmd\r
+* Description : Enables or disables the High Speed APB (APB2) peripheral clock.\r
+* Input : - RCC_APB2Periph: specifies the APB2 peripheral to gates its\r
+* clock.\r
+* This parameter can be any combination of the following values:\r
+* - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,\r
+* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,\r
+* RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,\r
+* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,\r
+* RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,\r
+* RCC_APB2Periph_ALL\r
+* - NewState: new state of the specified peripheral clock.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2ENR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2ENR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_APB1PeriphClockCmd\r
+* Description : Enables or disables the Low Speed APB (APB1) peripheral clock.\r
+* Input : - RCC_APB1Periph: specifies the APB1 peripheral to gates its\r
+* clock.\r
+* This parameter can be any combination of the following values:\r
+* - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,\r
+* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,\r
+* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,\r
+* RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, \r
+* RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,\r
+* RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP,\r
+* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL\r
+* - NewState: new state of the specified peripheral clock.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1ENR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1ENR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_APB2PeriphResetCmd\r
+* Description : Forces or releases High Speed APB (APB2) peripheral reset.\r
+* Input : - RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
+* This parameter can be any combination of the following values:\r
+* - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,\r
+* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,\r
+* RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,\r
+* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,\r
+* RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,\r
+* RCC_APB2Periph_ALL\r
+* - NewState: new state of the specified peripheral reset.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2RSTR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2RSTR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_APB1PeriphResetCmd\r
+* Description : Forces or releases Low Speed APB (APB1) peripheral reset.\r
+* Input : - RCC_APB1Periph: specifies the APB1 peripheral to reset.\r
+* This parameter can be any combination of the following values:\r
+* - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,\r
+* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,\r
+* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,\r
+* RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, \r
+* RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,\r
+* RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP,\r
+* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL\r
+* - NewState: new state of the specified peripheral clock.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1RSTR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1RSTR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_BackupResetCmd\r
+* Description : Forces or releases the Backup domain reset.\r
+* Input : - NewState: new state of the Backup domain reset.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_BackupResetCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) BDCR_BDRST_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_ClockSecuritySystemCmd\r
+* Description : Enables or disables the Clock Security System.\r
+* Input : - NewState: new state of the Clock Security System..\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) CR_CSSON_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_MCOConfig\r
+* Description : Selects the clock source to output on MCO pin.\r
+* Input : - RCC_MCO: specifies the clock source to output.\r
+* This parameter can be one of the following values:\r
+* - RCC_MCO_NoClock: No clock selected\r
+* - RCC_MCO_SYSCLK: System clock selected\r
+* - RCC_MCO_HSI: HSI oscillator clock selected\r
+* - RCC_MCO_HSE: HSE oscillator clock selected\r
+* - RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_MCOConfig(u8 RCC_MCO)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MCO(RCC_MCO));\r
+\r
+ /* Perform Byte access to MCO[2:0] bits to select the MCO source */\r
+ *(vu8 *) CFGR_BYTE4_ADDRESS = RCC_MCO;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_GetFlagStatus\r
+* Description : Checks whether the specified RCC flag is set or not.\r
+* Input : - RCC_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+* - RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+* - RCC_FLAG_PLLRDY: PLL clock ready\r
+* - RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+* - RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+* - RCC_FLAG_PINRST: Pin reset\r
+* - RCC_FLAG_PORRST: POR/PDR reset\r
+* - RCC_FLAG_SFTRST: Software reset\r
+* - RCC_FLAG_IWDGRST: Independent Watchdog reset\r
+* - RCC_FLAG_WWDGRST: Window Watchdog reset\r
+* - RCC_FLAG_LPWRRST: Low Power reset\r
+* Output : None\r
+* Return : The new state of RCC_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG)\r
+{\r
+ u32 tmp = 0;\r
+ u32 statusreg = 0;\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_FLAG(RCC_FLAG));\r
+\r
+ /* Get the RCC register index */\r
+ tmp = RCC_FLAG >> 5;\r
+\r
+ if (tmp == 1) /* The flag to check is in CR register */\r
+ {\r
+ statusreg = RCC->CR;\r
+ }\r
+ else if (tmp == 2) /* The flag to check is in BDCR register */\r
+ {\r
+ statusreg = RCC->BDCR;\r
+ }\r
+ else /* The flag to check is in CSR register */\r
+ {\r
+ statusreg = RCC->CSR;\r
+ }\r
+\r
+ /* Get the flag position */\r
+ tmp = RCC_FLAG & FLAG_Mask;\r
+\r
+ if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_ClearFlag\r
+* Description : Clears the RCC reset flags.\r
+* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,\r
+* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,\r
+* RCC_FLAG_LPWRRST\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_ClearFlag(void)\r
+{\r
+ /* Set RMVF bit to clear the reset flags */\r
+ RCC->CSR |= CSR_RMVF_Set;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_GetITStatus\r
+* Description : Checks whether the specified RCC interrupt has occurred or not.\r
+* Input : - RCC_IT: specifies the RCC interrupt source to check.\r
+* This parameter can be one of the following values:\r
+* - RCC_IT_LSIRDY: LSI ready interrupt\r
+* - RCC_IT_LSERDY: LSE ready interrupt\r
+* - RCC_IT_HSIRDY: HSI ready interrupt\r
+* - RCC_IT_HSERDY: HSE ready interrupt\r
+* - RCC_IT_PLLRDY: PLL ready interrupt\r
+* - RCC_IT_CSS: Clock Security System interrupt\r
+* Output : None\r
+* Return : The new state of RCC_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus RCC_GetITStatus(u8 RCC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_GET_IT(RCC_IT));\r
+\r
+ /* Check the status of the specified RCC interrupt */\r
+ if ((RCC->CIR & RCC_IT) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the RCC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_ClearITPendingBit\r
+* Description : Clears the RCC\92s interrupt pending bits.\r
+* Input : - RCC_IT: specifies the interrupt pending bit to clear.\r
+* This parameter can be any combination of the following values:\r
+* - RCC_IT_LSIRDY: LSI ready interrupt\r
+* - RCC_IT_LSERDY: LSE ready interrupt\r
+* - RCC_IT_HSIRDY: HSI ready interrupt\r
+* - RCC_IT_HSERDY: HSE ready interrupt\r
+* - RCC_IT_PLLRDY: PLL ready interrupt\r
+* - RCC_IT_CSS: Clock Security System interrupt\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_ClearITPendingBit(u8 RCC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r
+\r
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
+ pending bits */\r
+ *(vu8 *) CIR_BYTE3_ADDRESS = RCC_IT;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_spi.c\r
+* Author : MCD Application Team\r
+* Version : V2.0.1 \r
+* Date : 06/13/2008\r
+* Description : This file provides all the SPI firmware functions.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_spi.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* SPI SPE mask */\r
+#define CR1_SPE_Set ((u16)0x0040)\r
+#define CR1_SPE_Reset ((u16)0xFFBF)\r
+\r
+/* I2S I2SE mask */\r
+#define I2SCFGR_I2SE_Set ((u16)0x0400)\r
+#define I2SCFGR_I2SE_Reset ((u16)0xFBFF)\r
+\r
+/* SPI CRCNext mask */\r
+#define CR1_CRCNext_Set ((u16)0x1000)\r
+\r
+/* SPI CRCEN mask */\r
+#define CR1_CRCEN_Set ((u16)0x2000)\r
+#define CR1_CRCEN_Reset ((u16)0xDFFF)\r
+\r
+/* SPI SSOE mask */\r
+#define CR2_SSOE_Set ((u16)0x0004)\r
+#define CR2_SSOE_Reset ((u16)0xFFFB)\r
+\r
+/* SPI registers Masks */\r
+#define CR1_CLEAR_Mask ((u16)0x3040)\r
+#define I2SCFGR_CLEAR_Mask ((u16)0xF040)\r
+\r
+/* SPI or I2S mode selection masks */\r
+#define SPI_Mode_Select ((u16)0xF7FF)\r
+#define I2S_Mode_Select ((u16)0x0800) \r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_I2S_DeInit\r
+* Description : Deinitializes the SPIx peripheral registers to their default\r
+* reset values (Affects also the I2Ss).\r
+* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ switch (*(u32*)&SPIx)\r
+ {\r
+ case SPI1_BASE:\r
+ /* Enable SPI1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);\r
+ /* Release SPI1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);\r
+ break;\r
+\r
+ case SPI2_BASE:\r
+ /* Enable SPI2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);\r
+ /* Release SPI2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);\r
+ break;\r
+\r
+ case SPI3_BASE:\r
+ /* Enable SPI3 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);\r
+ /* Release SPI3 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_Init\r
+* Description : Initializes the SPIx peripheral according to the specified \r
+* parameters in the SPI_InitStruct.\r
+* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+* - SPI_InitStruct: pointer to a SPI_InitTypeDef structure that\r
+* contains the configuration information for the specified\r
+* SPI peripheral.\r
+* Output : None\r
+* Return : None\r
+******************************************************************************/\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+ u16 tmpreg = 0;\r
+ \r
+ /* check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx)); \r
+ \r
+ /* Check the SPI parameters */\r
+ assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));\r
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));\r
+ assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));\r
+ assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));\r
+ assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));\r
+ assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));\r
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));\r
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));\r
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));\r
+\r
+/*---------------------------- SPIx CR1 Configuration ------------------------*/\r
+ /* Get the SPIx CR1 value */\r
+ tmpreg = SPIx->CR1;\r
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */\r
+ tmpreg &= CR1_CLEAR_Mask;\r
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler\r
+ master/salve mode, CPOL and CPHA */\r
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */\r
+ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */\r
+ /* Set LSBFirst bit according to SPI_FirstBit value */\r
+ /* Set BR bits according to SPI_BaudRatePrescaler value */\r
+ /* Set CPOL bit according to SPI_CPOL value */\r
+ /* Set CPHA bit according to SPI_CPHA value */\r
+ tmpreg |= (u16)((u32)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |\r
+ SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | \r
+ SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | \r
+ SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);\r
+ /* Write to SPIx CR1 */\r
+ SPIx->CR1 = tmpreg;\r
+ \r
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */\r
+ SPIx->I2SCFGR &= SPI_Mode_Select; \r
+\r
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
+ /* Write to SPIx CRCPOLY */\r
+ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2S_Init\r
+* Description : Initializes the SPIx peripheral according to the specified \r
+* parameters in the I2S_InitStruct.\r
+* Input : - SPIx: where x can be 2 or 3 to select the SPI peripheral\r
+* (configured in I2S mode).\r
+* - I2S_InitStruct: pointer to an I2S_InitTypeDef structure that\r
+* contains the configuration information for the specified\r
+* SPI peripheral configured in I2S mode.\r
+* Output : None\r
+* Return : None\r
+******************************************************************************/\r
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)\r
+{\r
+ u16 tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;\r
+ u32 tmp = 0;\r
+ RCC_ClocksTypeDef RCC_Clocks;\r
+ \r
+ /* Check the I2S parameters */\r
+ assert_param(IS_SPI_23_PERIPH(SPIx));\r
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));\r
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));\r
+ assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));\r
+ assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));\r
+ assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));\r
+ assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); \r
+\r
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r
+\r
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r
+ SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; \r
+ SPIx->I2SPR = 0x0002;\r
+ \r
+ /* Get the I2SCFGR register value */\r
+ tmpreg = SPIx->I2SCFGR;\r
+ \r
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/\r
+ if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)\r
+ {\r
+ i2sodd = (u16)0;\r
+ i2sdiv = (u16)2; \r
+ }\r
+ /* If the requested audio frequency is not the default, compute the prescaler */\r
+ else\r
+ {\r
+ /* Check the frame length (For the Prescaler computing) */\r
+ if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)\r
+ {\r
+ /* Packet length is 16 bits */\r
+ packetlength = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Packet length is 32 bits */\r
+ packetlength = 2;\r
+ }\r
+ /* Get System Clock frequency */\r
+ RCC_GetClocksFreq(&RCC_Clocks);\r
+ \r
+ /* Compute the Real divider depending on the MCLK output state with a flaoting point */\r
+ if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)\r
+ {\r
+ /* MCLK output is enabled */\r
+ tmp = (u16)(((10 * RCC_Clocks.SYSCLK_Frequency) / (256 * I2S_InitStruct->I2S_AudioFreq)) + 5);\r
+ }\r
+ else\r
+ {\r
+ /* MCLK output is disabled */\r
+ tmp = (u16)(((10 * RCC_Clocks.SYSCLK_Frequency) / (32 * packetlength * I2S_InitStruct->I2S_AudioFreq)) + 5);\r
+ }\r
+ \r
+ /* Remove the flaoting point */\r
+ tmp = tmp/10; \r
+ \r
+ /* Check the parity of the divider */\r
+ i2sodd = (u16)(tmp & (u16)0x0001);\r
+ \r
+ /* Compute the i2sdiv prescaler */\r
+ i2sdiv = (u16)((tmp - i2sodd) / 2);\r
+ \r
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */\r
+ i2sodd = (u16) (i2sodd << 8);\r
+ }\r
+ \r
+ /* Test if the divider is 1 or 0 */\r
+ if ((i2sdiv < 2) || (i2sdiv > 0xFF))\r
+ {\r
+ /* Set the default values */\r
+ i2sdiv = 2;\r
+ i2sodd = 0;\r
+ }\r
+\r
+ /* Write to SPIx I2SPR register the computed value */\r
+ SPIx->I2SPR = (u16)(i2sdiv | i2sodd | I2S_InitStruct->I2S_MCLKOutput); \r
+ \r
+ /* Configure the I2S with the SPI_InitStruct values */\r
+ tmpreg |= (u16)(I2S_Mode_Select | I2S_InitStruct->I2S_Mode | \\r
+ I2S_InitStruct->I2S_Standard | I2S_InitStruct->I2S_DataFormat | \\r
+ I2S_InitStruct->I2S_CPOL);\r
+ \r
+ /* Write to SPIx I2SCFGR */ \r
+ SPIx->I2SCFGR = tmpreg; \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_StructInit\r
+* Description : Fills each SPI_InitStruct member with its default value.\r
+* Input : - SPI_InitStruct : pointer to a SPI_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+/*--------------- Reset SPI init structure parameters values -----------------*/\r
+ /* Initialize the SPI_Direction member */\r
+ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+\r
+ /* initialize the SPI_Mode member */\r
+ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;\r
+\r
+ /* initialize the SPI_DataSize member */\r
+ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;\r
+\r
+ /* Initialize the SPI_CPOL member */\r
+ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;\r
+\r
+ /* Initialize the SPI_CPHA member */\r
+ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;\r
+\r
+ /* Initialize the SPI_NSS member */\r
+ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;\r
+\r
+ /* Initialize the SPI_BaudRatePrescaler member */\r
+ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+\r
+ /* Initialize the SPI_FirstBit member */\r
+ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;\r
+\r
+ /* Initialize the SPI_CRCPolynomial member */\r
+ SPI_InitStruct->SPI_CRCPolynomial = 7;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2S_StructInit\r
+* Description : Fills each I2S_InitStruct member with its default value.\r
+* Input : - I2S_InitStruct : pointer to a I2S_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)\r
+{\r
+/*--------------- Reset I2S init structure parameters values -----------------*/\r
+ /* Initialize the I2S_Mode member */\r
+ I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;\r
+ \r
+ /* Initialize the I2S_Standard member */\r
+ I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;\r
+ \r
+ /* Initialize the I2S_DataFormat member */\r
+ I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;\r
+ \r
+ /* Initialize the I2S_MCLKOutput member */\r
+ I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;\r
+ \r
+ /* Initialize the I2S_AudioFreq member */\r
+ I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;\r
+ \r
+ /* Initialize the I2S_CPOL member */\r
+ I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_Cmd\r
+* Description : Enables or disables the specified SPI peripheral.\r
+* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+* - NewState: new state of the SPIx peripheral. \r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI peripheral */\r
+ SPIx->CR1 |= CR1_SPE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI peripheral */\r
+ SPIx->CR1 &= CR1_SPE_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2S_Cmd\r
+* Description : Enables or disables the specified SPI peripheral (in I2S mode).\r
+* Input : - SPIx: where x can be 2 or 3 to select the SPI peripheral.\r
+* - NewState: new state of the SPIx peripheral. \r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_23_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI peripheral (in I2S mode) */\r
+ SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI peripheral (in I2S mode) */\r
+ SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_I2S_ITConfig\r
+* Description : Enables or disables the specified SPI/I2S interrupts.\r
+* Input : - SPIx: where x can be :\r
+* - 1, 2 or 3 in SPI mode \r
+* - 2 or 3 in I2S mode\r
+* - SPI_I2S_IT: specifies the SPI/I2S interrupt source to be \r
+* enabled or disabled. \r
+* This parameter can be one of the following values:\r
+* - SPI_I2S_IT_TXE: Tx buffer empty interrupt mask\r
+* - SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask\r
+* - SPI_I2S_IT_ERR: Error interrupt mask\r
+* - NewState: new state of the specified SPI/I2S interrupt.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, u8 SPI_I2S_IT, FunctionalState NewState)\r
+{\r
+ u16 itpos = 0, itmask = 0 ;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI/I2S IT index */\r
+ itpos = SPI_I2S_IT >> 4;\r
+ /* Set the IT mask */\r
+ itmask = (u16)((u16)1 << itpos);\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI/I2S interrupt */\r
+ SPIx->CR2 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI/I2S interrupt */\r
+ SPIx->CR2 &= (u16)~itmask;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_I2S_DMACmd\r
+* Description : Enables or disables the SPIx/I2Sx DMA interface.\r
+* Input : - SPIx: where x can be :\r
+* - 1, 2 or 3 in SPI mode \r
+* - 2 or 3 in I2S mode\r
+* - SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request \r
+* to be enabled or disabled. \r
+* This parameter can be any combination of the following values:\r
+* - SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request\r
+* - SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request\r
+* - NewState: new state of the selected SPI/I2S DMA transfer \r
+* request.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, u16 SPI_I2S_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI/I2S DMA requests */\r
+ SPIx->CR2 |= SPI_I2S_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI/I2S DMA requests */\r
+ SPIx->CR2 &= (u16)~SPI_I2S_DMAReq;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_I2S_SendData\r
+* Description : Transmits a Data through the SPIx/I2Sx peripheral.\r
+* Input : - SPIx: where x can be :\r
+* - 1, 2 or 3 in SPI mode \r
+* - 2 or 3 in I2S mode\r
+* - Data : Data to be transmitted..\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, u16 Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Write in the DR register the data to be sent */\r
+ SPIx->DR = Data;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_I2S_ReceiveData\r
+* Description : Returns the most recent received data by the SPIx/I2Sx peripheral. \r
+* Input : - SPIx: where x can be :\r
+* - 1, 2 or 3 in SPI mode \r
+* - 2 or 3 in I2S mode\r
+* Output : None\r
+* Return : The value of the received data.\r
+*******************************************************************************/\r
+u16 SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Return the data in the DR register */\r
+ return SPIx->DR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_NSSInternalSoftwareConfig\r
+* Description : Configures internally by software the NSS pin for the selected \r
+* SPI.\r
+* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+* - SPI_NSSInternalSoft: specifies the SPI NSS internal state.\r
+* This parameter can be one of the following values:\r
+* - SPI_NSSInternalSoft_Set: Set NSS pin internally\r
+* - SPI_NSSInternalSoft_Reset: Reset NSS pin internally\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));\r
+\r
+ if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)\r
+ {\r
+ /* Set NSS pin internally by software */\r
+ SPIx->CR1 |= SPI_NSSInternalSoft_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset NSS pin internally by software */\r
+ SPIx->CR1 &= SPI_NSSInternalSoft_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_SSOutputCmd\r
+* Description : Enables or disables the SS output for the selected SPI.\r
+* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+* - NewState: new state of the SPIx SS output. \r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI SS output */\r
+ SPIx->CR2 |= CR2_SSOE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI SS output */\r
+ SPIx->CR2 &= CR2_SSOE_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_DataSizeConfig\r
+* Description : Configures the data size for the selected SPI.\r
+* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+* - SPI_DataSize: specifies the SPI data size.\r
+* This parameter can be one of the following values:\r
+* - SPI_DataSize_16b: Set data frame format to 16bit\r
+* - SPI_DataSize_8b: Set data frame format to 8bit\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DATASIZE(SPI_DataSize));\r
+\r
+ /* Clear DFF bit */\r
+ SPIx->CR1 &= (u16)~SPI_DataSize_16b;\r
+ /* Set new DFF bit value */\r
+ SPIx->CR1 |= SPI_DataSize;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_TransmitCRC\r
+* Description : Transmit the SPIx CRC value.\r
+* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Enable the selected SPI CRC transmission */\r
+ SPIx->CR1 |= CR1_CRCNext_Set;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_CalculateCRC\r
+* Description : Enables or disables the CRC value calculation of the\r
+* transfered bytes.\r
+* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+* - NewState: new state of the SPIx CRC value calculation.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI CRC calculation */\r
+ SPIx->CR1 |= CR1_CRCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI CRC calculation */\r
+ SPIx->CR1 &= CR1_CRCEN_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_GetCRC\r
+* Description : Returns the transmit or the receive CRC register value for\r
+* the specified SPI.\r
+* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+* - SPI_CRC: specifies the CRC register to be read.\r
+* This parameter can be one of the following values:\r
+* - SPI_CRC_Tx: Selects Tx CRC register\r
+* - SPI_CRC_Rx: Selects Rx CRC register\r
+* Output : None\r
+* Return : The selected CRC register value..\r
+*******************************************************************************/\r
+u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC)\r
+{\r
+ u16 crcreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_CRC(SPI_CRC));\r
+\r
+ if (SPI_CRC != SPI_CRC_Rx)\r
+ {\r
+ /* Get the Tx CRC register */\r
+ crcreg = SPIx->TXCRCR;\r
+ }\r
+ else\r
+ {\r
+ /* Get the Rx CRC register */\r
+ crcreg = SPIx->RXCRCR;\r
+ }\r
+\r
+ /* Return the selected CRC register */\r
+ return crcreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_GetCRCPolynomial\r
+* Description : Returns the CRC Polynomial register value for the specified SPI.\r
+* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+* Output : None\r
+* Return : The CRC Polynomial register value.\r
+*******************************************************************************/\r
+u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Return the CRC polynomial register */\r
+ return SPIx->CRCPR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_BiDirectionalLineConfig\r
+* Description : Selects the data transfer direction in bi-directional mode\r
+* for the specified SPI.\r
+* Input : - SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+* - SPI_Direction: specifies the data transfer direction in\r
+* bi-directional mode. \r
+* This parameter can be one of the following values:\r
+* - SPI_Direction_Tx: Selects Tx transmission direction\r
+* - SPI_Direction_Rx: Selects Rx receive direction\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DIRECTION(SPI_Direction));\r
+\r
+ if (SPI_Direction == SPI_Direction_Tx)\r
+ {\r
+ /* Set the Tx only mode */\r
+ SPIx->CR1 |= SPI_Direction_Tx;\r
+ }\r
+ else\r
+ {\r
+ /* Set the Rx only mode */\r
+ SPIx->CR1 &= SPI_Direction_Rx;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_I2S_GetFlagStatus\r
+* Description : Checks whether the specified SPI/I2S flag is set or not.\r
+* Input : - SPIx: where x can be :\r
+* - 1, 2 or 3 in SPI mode \r
+* - 2 or 3 in I2S mode\r
+* - SPI_I2S_FLAG: specifies the SPI/I2S flag to check. \r
+* This parameter can be one of the following values:\r
+* - SPI_I2S_FLAG_TXE: Transmit buffer empty flag.\r
+* - SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.\r
+* - SPI_I2S_FLAG_BSY: Busy flag.\r
+* - SPI_I2S_FLAG_OVR: Overrun flag.\r
+* - SPI_FLAG_MODF: Mode Fault flag.\r
+* - SPI_FLAG_CRCERR: CRC Error flag.\r
+* - I2S_FLAG_UDR: Underrun Error flag.\r
+* - I2S_FLAG_CHSIDE: Channel Side flag.\r
+* Output : None\r
+* Return : The new state of SPI_I2S_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));\r
+\r
+ /* Check the status of the specified SPI/I2S flag */\r
+ if ((SPIx->SR & SPI_I2S_FLAG) != (u16)RESET)\r
+ {\r
+ /* SPI_I2S_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_I2S_ClearFlag\r
+* Description : Clears the SPIx/I2Sx pending flags.\r
+* Input : - SPIx: where x can be :\r
+* - 1, 2 or 3 in SPI mode \r
+* - 2 or 3 in I2S mode\r
+* - SPI_I2S_FLAG: specifies the SPI/I2S flag to clear. \r
+* This parameter can be one of the following values:\r
+* - SPI_I2S_FLAG_OVR: Overrun flag \r
+* - SPI_FLAG_MODF: Mode Fault flag.\r
+* - SPI_FLAG_CRCERR: CRC Error flag.\r
+* - I2S_FLAG_UDR: Underrun Error flag.\r
+* Note: Before clearing OVR flag, it is mandatory to read \r
+* SPI_I2S_DR register, so that the last data is not lost.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));\r
+ \r
+ /* SPI_FLAG_MODF flag clear */\r
+ if(SPI_I2S_FLAG == SPI_FLAG_MODF)\r
+ {\r
+ /* Read SR register */\r
+ (void)SPIx->SR;\r
+ \r
+ /* Write on CR1 register */\r
+ SPIx->CR1 |= CR1_SPE_Set; \r
+ }\r
+ /* SPI_I2S_FLAG_OVR flag or I2S_FLAG_UDR flag clear */\r
+ else if ((SPI_I2S_FLAG == SPI_I2S_FLAG_OVR) || (SPI_I2S_FLAG == I2S_FLAG_UDR)) \r
+ {\r
+ /* Read SR register (Before clearing OVR flag, it is mandatory to read \r
+ SPI_I2S_DR register)*/\r
+ (void)SPIx->SR;\r
+ }\r
+ else /* SPI_FLAG_CRCERR flag clear */\r
+ {\r
+ /* Clear the selected SPI flag */\r
+ SPIx->SR = (u16)~SPI_I2S_FLAG;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_I2S_GetITStatus\r
+* Description : Checks whether the specified SPI/I2S interrupt has occurred or not.\r
+* Input : - SPIx: where x can be :\r
+* - 1, 2 or 3 in SPI mode \r
+* - 2 or 3 in I2S mode\r
+* - SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. \r
+* This parameter can be one of the following values:\r
+* - SPI_I2S_IT_TXE: Transmit buffer empty interrupt.\r
+* - SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.\r
+* - SPI_I2S_IT_OVR: Overrun interrupt.\r
+* - SPI_IT_MODF: Mode Fault interrupt.\r
+* - SPI_IT_CRCERR: CRC Error interrupt.\r
+* - I2S_IT_UDR: Underrun Error interrupt.\r
+* Output : None\r
+* Return : The new state of SPI_I2S_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_I2S_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ u16 itpos = 0, itmask = 0, enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI/I2S IT index */\r
+ itpos = (u16)((u16)0x01 << (SPI_I2S_IT & (u8)0x0F));\r
+\r
+ /* Get the SPI/I2S IT mask */\r
+ itmask = SPI_I2S_IT >> 4;\r
+ /* Set the IT mask */\r
+ itmask = (u16)((u16)0x01 << itmask);\r
+ /* Get the SPI_I2S_IT enable bit status */\r
+ enablestatus = (SPIx->CR2 & itmask) ;\r
+\r
+ /* Check the status of the specified SPI/I2S interrupt */\r
+ if (((SPIx->SR & itpos) != (u16)RESET) && enablestatus)\r
+ {\r
+ /* SPI_I2S_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_I2S_ClearITPendingBit\r
+* Description : Clears the SPIx/I2Sx interrupt pending bits.\r
+* Input : - SPIx: where x can be :\r
+* - 1, 2 or 3 in SPI mode \r
+* - 2 or 3 in I2S mode\r
+* - SPI_I2S_IT: specifies the SPI/I2S interrupt pending bit to clear.\r
+* This parameter can be one of the following values:\r
+* - SPI_I2S_IT_OVR: Overrun interrupt.\r
+* - SPI_IT_MODF: Mode Fault interrupt.\r
+* - SPI_IT_CRCERR: CRC Error interrupt.\r
+* - I2S_IT_UDR: Underrun Error interrupt.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_I2S_IT)\r
+{\r
+ u16 itpos = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));\r
+\r
+ /* SPI_IT_MODF pending bit clear */\r
+ if(SPI_I2S_IT == SPI_IT_MODF)\r
+ {\r
+ /* Read SR register */\r
+ (void)SPIx->SR;\r
+ /* Write on CR1 register */\r
+ SPIx->CR1 |= CR1_SPE_Set; \r
+ }\r
+ /* SPI_I2S_IT_OVR or I2S_IT_UDR pending bit clear */ \r
+ else if((SPI_I2S_IT == SPI_I2S_IT_OVR) || (SPI_I2S_IT == I2S_IT_UDR)) \r
+ {\r
+ /* Read SR register */\r
+ (void)(SPIx->SR);\r
+ } \r
+ else /* SPI_IT_CRCERR pending bit clear */\r
+ {\r
+ /* Get the SPI/I2S IT index */\r
+ itpos = (u16)((u16)0x01 << (SPI_I2S_IT & (u8)0x0F));\r
+ /* Clear the selected SPI/I2S interrupt pending bits */\r
+ SPIx->SR = (u16)~itpos;\r
+ }\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_systick.c\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file provides all the SysTick firmware functions.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_systick.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ---------------------- SysTick registers bit mask -------------------- */\r
+/* CTRL TICKINT Mask */\r
+#define CTRL_TICKINT_Set ((u32)0x00000002)\r
+#define CTRL_TICKINT_Reset ((u32)0xFFFFFFFD)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : SysTick_CLKSourceConfig\r
+* Description : Configures the SysTick clock source.\r
+* Input : - SysTick_CLKSource: specifies the SysTick clock source.\r
+* This parameter can be one of the following values:\r
+* - SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8\r
+* selected as SysTick clock source.\r
+* - SysTick_CLKSource_HCLK: AHB clock selected as\r
+* SysTick clock source.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SysTick_CLKSourceConfig(u32 SysTick_CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
+\r
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
+ {\r
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SysTick_SetReload\r
+* Description : Sets SysTick Reload value.\r
+* Input : - Reload: SysTick Reload new value.\r
+* This parameter must be a number between 1 and 0xFFFFFF.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SysTick_SetReload(u32 Reload)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_RELOAD(Reload));\r
+\r
+ SysTick->LOAD = Reload;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SysTick_CounterCmd\r
+* Description : Enables or disables the SysTick counter.\r
+* Input : - SysTick_Counter: new state of the SysTick counter.\r
+* This parameter can be one of the following values:\r
+* - SysTick_Counter_Disable: Disable counter\r
+* - SysTick_Counter_Enable: Enable counter\r
+* - SysTick_Counter_Clear: Clear counter value to 0\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SysTick_CounterCmd(u32 SysTick_Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_COUNTER(SysTick_Counter));\r
+\r
+ if (SysTick_Counter == SysTick_Counter_Enable)\r
+ {\r
+ SysTick->CTRL |= SysTick_Counter_Enable;\r
+ }\r
+ else if (SysTick_Counter == SysTick_Counter_Disable) \r
+ {\r
+ SysTick->CTRL &= SysTick_Counter_Disable;\r
+ }\r
+ else /* SysTick_Counter == SysTick_Counter_Clear */\r
+ {\r
+ SysTick->VAL = SysTick_Counter_Clear;\r
+ } \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SysTick_ITConfig\r
+* Description : Enables or disables the SysTick Interrupt.\r
+* Input : - NewState: new state of the SysTick Interrupt.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SysTick_ITConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ SysTick->CTRL |= CTRL_TICKINT_Set;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= CTRL_TICKINT_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SysTick_GetCounter\r
+* Description : Gets SysTick counter value.\r
+* Input : None\r
+* Output : None\r
+* Return : SysTick current value\r
+*******************************************************************************/\r
+u32 SysTick_GetCounter(void)\r
+{\r
+ return(SysTick->VAL);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SysTick_GetFlagStatus\r
+* Description : Checks whether the specified SysTick flag is set or not.\r
+* Input : - SysTick_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - SysTick_FLAG_COUNT\r
+* - SysTick_FLAG_SKEW\r
+* - SysTick_FLAG_NOREF\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG)\r
+{\r
+ u32 statusreg = 0, tmp = 0 ;\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_FLAG(SysTick_FLAG));\r
+\r
+ /* Get the SysTick register index */\r
+ tmp = SysTick_FLAG >> 3;\r
+\r
+ if (tmp == 2) /* The flag to check is in CTRL register */\r
+ {\r
+ statusreg = SysTick->CTRL;\r
+ }\r
+ else /* The flag to check is in CALIB register */\r
+ {\r
+ statusreg = SysTick->CALIB;\r
+ }\r
+\r
+ if ((statusreg & ((u32)1 << SysTick_FLAG)) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_usart.c\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file provides all the USART firmware functions.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_usart.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* USART UE Mask */\r
+#define CR1_UE_Set ((u16)0x2000) /* USART Enable Mask */\r
+#define CR1_UE_Reset ((u16)0xDFFF) /* USART Disable Mask */\r
+\r
+/* USART WakeUp Method */\r
+#define CR1_WAKE_Mask ((u16)0xF7FF) /* USART WakeUp Method Mask */\r
+\r
+/* USART RWU Mask */\r
+#define CR1_RWU_Set ((u16)0x0002) /* USART mute mode Enable Mask */\r
+#define CR1_RWU_Reset ((u16)0xFFFD) /* USART mute mode Enable Mask */\r
+\r
+#define CR1_SBK_Set ((u16)0x0001) /* USART Break Character send Mask */\r
+\r
+#define CR1_CLEAR_Mask ((u16)0xE9F3) /* USART CR1 Mask */\r
+\r
+#define CR2_Address_Mask ((u16)0xFFF0) /* USART address Mask */\r
+\r
+/* USART LIN Mask */\r
+#define CR2_LINEN_Set ((u16)0x4000) /* USART LIN Enable Mask */\r
+#define CR2_LINEN_Reset ((u16)0xBFFF) /* USART LIN Disable Mask */\r
+\r
+/* USART LIN Break detection */\r
+#define CR2_LBDL_Mask ((u16)0xFFDF) /* USART LIN Break detection Mask */\r
+\r
+#define CR2_STOP_CLEAR_Mask ((u16)0xCFFF) /* USART CR2 STOP Bits Mask */\r
+#define CR2_CLOCK_CLEAR_Mask ((u16)0xF0FF) /* USART CR2 Clock Mask */\r
+\r
+/* USART SC Mask */\r
+#define CR3_SCEN_Set ((u16)0x0020) /* USART SC Enable Mask */\r
+#define CR3_SCEN_Reset ((u16)0xFFDF) /* USART SC Disable Mask */\r
+\r
+/* USART SC NACK Mask */\r
+#define CR3_NACK_Set ((u16)0x0010) /* USART SC NACK Enable Mask */\r
+#define CR3_NACK_Reset ((u16)0xFFEF) /* USART SC NACK Disable Mask */\r
+\r
+/* USART Half-Duplex Mask */\r
+#define CR3_HDSEL_Set ((u16)0x0008) /* USART Half-Duplex Enable Mask */\r
+#define CR3_HDSEL_Reset ((u16)0xFFF7) /* USART Half-Duplex Disable Mask */\r
+\r
+/* USART IrDA Mask */\r
+#define CR3_IRLP_Mask ((u16)0xFFFB) /* USART IrDA LowPower mode Mask */\r
+\r
+#define CR3_CLEAR_Mask ((u16)0xFCFF) /* USART CR3 Mask */\r
+\r
+/* USART IrDA Mask */\r
+#define CR3_IREN_Set ((u16)0x0002) /* USART IrDA Enable Mask */\r
+#define CR3_IREN_Reset ((u16)0xFFFD) /* USART IrDA Disable Mask */\r
+\r
+#define GTPR_LSB_Mask ((u16)0x00FF) /* Guard Time Register LSB Mask */\r
+#define GTPR_MSB_Mask ((u16)0xFF00) /* Guard Time Register MSB Mask */\r
+\r
+#define IT_Mask ((u16)0x001F) /* USART Interrupt Mask */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_DeInit\r
+* Description : Deinitializes the USARTx peripheral registers to their\r
+* default reset values.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_DeInit(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+\r
+ switch (*(u32*)&USARTx)\r
+ {\r
+ case USART1_BASE:\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);\r
+ break;\r
+\r
+ case USART2_BASE:\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);\r
+ break;\r
+\r
+ case USART3_BASE:\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);\r
+ break;\r
+ \r
+ case UART4_BASE:\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);\r
+ break;\r
+ \r
+ case UART5_BASE:\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);\r
+ break; \r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_Init\r
+* Description : Initializes the USARTx peripheral according to the specified\r
+* parameters in the USART_InitStruct .\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* - USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+* that contains the configuration information for the\r
+* specified USART peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ u32 tmpreg = 0x00, apbclock = 0x00;\r
+ u32 integerdivider = 0x00;\r
+ u32 fractionaldivider = 0x00;\r
+ u32 usartxbase = 0;\r
+ RCC_ClocksTypeDef RCC_ClocksStatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); \r
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));\r
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));\r
+ assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));\r
+ assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));\r
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));\r
+ /* The hardware flow control is available only for USART1, USART2 and USART3 */ \r
+ assert_param(IS_USART_PERIPH_HFC(USARTx, USART_InitStruct->USART_HardwareFlowControl));\r
+ \r
+ usartxbase = (*(u32*)&USARTx);\r
+\r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR2;\r
+ /* Clear STOP[13:12] bits */\r
+ tmpreg &= CR2_STOP_CLEAR_Mask;\r
+\r
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/\r
+ /* Set STOP[13:12] bits according to USART_StopBits value */\r
+ tmpreg |= (u32)USART_InitStruct->USART_StopBits;\r
+ \r
+ /* Write to USART CR2 */\r
+ USARTx->CR2 = (u16)tmpreg;\r
+\r
+/*---------------------------- USART CR1 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR1;\r
+ /* Clear M, PCE, PS, TE and RE bits */\r
+ tmpreg &= CR1_CLEAR_Mask;\r
+\r
+ /* Configure the USART Word Length, Parity and mode ----------------------- */\r
+ /* Set the M bits according to USART_WordLength value */\r
+ /* Set PCE and PS bits according to USART_Parity value */\r
+ /* Set TE and RE bits according to USART_Mode value */\r
+ tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |\r
+ USART_InitStruct->USART_Mode;\r
+\r
+ /* Write to USART CR1 */\r
+ USARTx->CR1 = (u16)tmpreg;\r
+\r
+/*---------------------------- USART CR3 Configuration -----------------------*/ \r
+ tmpreg = USARTx->CR3;\r
+ /* Clear CTSE and RTSE bits */\r
+ tmpreg &= CR3_CLEAR_Mask;\r
+\r
+ /* Configure the USART HFC -------------------------------------------------*/\r
+ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */\r
+ tmpreg |= USART_InitStruct->USART_HardwareFlowControl;\r
+\r
+ /* Write to USART CR3 */\r
+ USARTx->CR3 = (u16)tmpreg;\r
+\r
+/*---------------------------- USART BRR Configuration -----------------------*/\r
+ /* Configure the USART Baud Rate -------------------------------------------*/\r
+ RCC_GetClocksFreq(&RCC_ClocksStatus);\r
+ if (usartxbase == USART1_BASE)\r
+ {\r
+ apbclock = RCC_ClocksStatus.PCLK2_Frequency;\r
+ }\r
+ else\r
+ {\r
+ apbclock = RCC_ClocksStatus.PCLK1_Frequency;\r
+ }\r
+\r
+ /* Determine the integer part */\r
+ integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));\r
+ tmpreg = (integerdivider / 0x64) << 0x04;\r
+\r
+ /* Determine the fractional part */\r
+ fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));\r
+ tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F);\r
+\r
+ /* Write to USART BRR */\r
+ USARTx->BRR = (u16)tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_StructInit\r
+* Description : Fills each USART_InitStruct member with its default value.\r
+* Input : - USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ /* USART_InitStruct members default value */\r
+ USART_InitStruct->USART_BaudRate = 9600;\r
+ USART_InitStruct->USART_WordLength = USART_WordLength_8b;\r
+ USART_InitStruct->USART_StopBits = USART_StopBits_1;\r
+ USART_InitStruct->USART_Parity = USART_Parity_No ;\r
+ USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
+ USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_ClockInit\r
+* Description : Initializes the USARTx peripheral Clock according to the \r
+* specified parameters in the USART_ClockInitStruct .\r
+* Input : - USARTx: where x can be 1, 2, 3 to select the USART peripheral.\r
+* Note: The Smart Card mode is not available for UART4 and UART5.\r
+* - USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+* structure that contains the configuration information for \r
+* the specified USART peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+ u32 tmpreg = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));\r
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));\r
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));\r
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); \r
+ \r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR2;\r
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */\r
+ tmpreg &= CR2_CLOCK_CLEAR_Mask;\r
+\r
+ /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/\r
+ /* Set CLKEN bit according to USART_Clock value */\r
+ /* Set CPOL bit according to USART_CPOL value */\r
+ /* Set CPHA bit according to USART_CPHA value */\r
+ /* Set LBCL bit according to USART_LastBit value */\r
+ tmpreg |= (u32)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | \r
+ USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;\r
+\r
+ /* Write to USART CR2 */\r
+ USARTx->CR2 = (u16)tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_ClockStructInit\r
+* Description : Fills each USART_ClockInitStruct member with its default value.\r
+* Input : - USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+* structure which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+ /* USART_ClockInitStruct members default value */\r
+ USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;\r
+ USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;\r
+ USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;\r
+ USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_Cmd\r
+* Description : Enables or disables the specified USART peripheral.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* : - NewState: new state of the USARTx peripheral.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected USART by setting the UE bit in the CR1 register */\r
+ USARTx->CR1 |= CR1_UE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected USART by clearing the UE bit in the CR1 register */\r
+ USARTx->CR1 &= CR1_UE_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_ITConfig\r
+* Description : Enables or disables the specified USART interrupts.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* - USART_IT: specifies the USART interrupt sources to be\r
+* enabled or disabled.\r
+* This parameter can be one of the following values:\r
+* - USART_IT_CTS: CTS change interrupt (not available for\r
+* UART4 and UART5)\r
+* - USART_IT_LBD: LIN Break detection interrupt\r
+* - USART_IT_TXE: Tansmit Data Register empty interrupt\r
+* - USART_IT_TC: Transmission complete interrupt\r
+* - USART_IT_RXNE: Receive Data register not empty \r
+* interrupt\r
+* - USART_IT_IDLE: Idle line detection interrupt\r
+* - USART_IT_PE: Parity Error interrupt\r
+* - USART_IT_ERR: Error interrupt(Frame error, noise\r
+* error, overrun error)\r
+* - NewState: new state of the specified USARTx interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState)\r
+{\r
+ u32 usartreg = 0x00, itpos = 0x00, itmask = 0x00;\r
+ u32 usartxbase = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CONFIG_IT(USART_IT));\r
+ assert_param(IS_USART_PERIPH_IT(USARTx, USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */ \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ usartxbase = (*(u32*)&(USARTx));\r
+\r
+ /* Get the USART register index */\r
+ usartreg = (((u8)USART_IT) >> 0x05);\r
+\r
+ /* Get the interrupt position */\r
+ itpos = USART_IT & IT_Mask;\r
+\r
+ itmask = (((u32)0x01) << itpos);\r
+ \r
+ if (usartreg == 0x01) /* The IT is in CR1 register */\r
+ {\r
+ usartxbase += 0x0C;\r
+ }\r
+ else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ usartxbase += 0x10;\r
+ }\r
+ else /* The IT is in CR3 register */\r
+ {\r
+ usartxbase += 0x14; \r
+ }\r
+ if (NewState != DISABLE)\r
+ {\r
+ *(vu32*)usartxbase |= itmask;\r
+ }\r
+ else\r
+ {\r
+ *(vu32*)usartxbase &= ~itmask;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_DMACmd\r
+* Description : Enables or disables the USART\92s DMA interface.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3 or UART4.\r
+* Note: The DMA mode is not available for UART5.\r
+* - USART_DMAReq: specifies the DMA request.\r
+* This parameter can be any combination of the following values:\r
+* - USART_DMAReq_Tx: USART DMA transmit request\r
+* - USART_DMAReq_Rx: USART DMA receive request\r
+* - NewState: new state of the DMA Request sources.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_1234_PERIPH(USARTx));\r
+ assert_param(IS_USART_DMAREQ(USART_DMAReq)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 |= USART_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 &= (u16)~USART_DMAReq;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_SetAddress\r
+* Description : Sets the address of the USART node.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* - USART_Address: Indicates the address of the USART node.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_ADDRESS(USART_Address)); \r
+ \r
+ /* Clear the USART address */\r
+ USARTx->CR2 &= CR2_Address_Mask;\r
+ /* Set the USART address node */\r
+ USARTx->CR2 |= USART_Address;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_WakeUpConfig\r
+* Description : Selects the USART WakeUp method.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* - USART_WakeUp: specifies the USART wakeup method.\r
+* This parameter can be one of the following values:\r
+* - USART_WakeUp_IdleLine: WakeUp by an idle line detection\r
+* - USART_WakeUp_AddressMark: WakeUp by an address mark\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_WAKEUP(USART_WakeUp));\r
+ \r
+ USARTx->CR1 &= CR1_WAKE_Mask;\r
+ USARTx->CR1 |= USART_WakeUp;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_ReceiverWakeUpCmd\r
+* Description : Determines if the USART is in mute mode or not.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* - NewState: new state of the USART mute mode.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the USART mute mode by setting the RWU bit in the CR1 register */\r
+ USARTx->CR1 |= CR1_RWU_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */\r
+ USARTx->CR1 &= CR1_RWU_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_LINBreakDetectLengthConfig\r
+* Description : Sets the USART LIN Break detection length.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* - USART_LINBreakDetectLength: specifies the LIN break\r
+* detection length.\r
+* This parameter can be one of the following values:\r
+* - USART_LINBreakDetectLength_10b: 10-bit break detection\r
+* - USART_LINBreakDetectLength_11b: 11-bit break detection\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));\r
+ \r
+ USARTx->CR2 &= CR2_LBDL_Mask;\r
+ USARTx->CR2 |= USART_LINBreakDetectLength; \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_LINCmd\r
+* Description : Enables or disables the USART\92s LIN mode.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* - NewState: new state of the USART LIN mode.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
+ USARTx->CR2 |= CR2_LINEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */\r
+ USARTx->CR2 &= CR2_LINEN_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_SendData\r
+* Description : Transmits single data through the USARTx peripheral.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* - Data: the data to transmit.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_SendData(USART_TypeDef* USARTx, u16 Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DATA(Data)); \r
+ \r
+ /* Transmit Data */\r
+ USARTx->DR = (Data & (u16)0x01FF);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_ReceiveData\r
+* Description : Returns the most recent received data by the USARTx peripheral.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* Output : None\r
+* Return : The received data.\r
+*******************************************************************************/\r
+u16 USART_ReceiveData(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Receive Data */\r
+ return (u16)(USARTx->DR & (u16)0x01FF);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_SendBreak\r
+* Description : Transmits break characters.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_SendBreak(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Send break characters */\r
+ USARTx->CR1 |= CR1_SBK_Set;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_SetGuardTime\r
+* Description : Sets the specified USART guard time.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* Note: The guard time bits are not available for UART4 and UART5.\r
+* - USART_GuardTime: specifies the guard time.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ \r
+ /* Clear the USART Guard time */\r
+ USARTx->GTPR &= GTPR_LSB_Mask;\r
+ /* Set the USART guard time */\r
+ USARTx->GTPR |= (u16)((u16)USART_GuardTime << 0x08);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_SetPrescaler\r
+* Description : Sets the system clock prescaler.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* Note: The function is used for IrDA mode with UART4 and UART5.\r
+* - USART_Prescaler: specifies the prescaler clock.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Clear the USART prescaler */\r
+ USARTx->GTPR &= GTPR_MSB_Mask;\r
+ /* Set the USART prescaler */\r
+ USARTx->GTPR |= USART_Prescaler;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_SmartCardCmd\r
+* Description : Enables or disables the USART\92s Smart Card mode.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral. \r
+* Note: The Smart Card mode is not available for UART4 and UART5.\r
+* - NewState: new state of the Smart Card mode.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_SCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SC mode by clearing the SCEN bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_SCEN_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_SmartCardNACKCmd\r
+* Description : Enables or disables NACK transmission.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral. \r
+* Note: The Smart Card mode is not available for UART4 and UART5.\r
+* - NewState: new state of the NACK transmission.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the NACK transmission by setting the NACK bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_NACK_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_NACK_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_HalfDuplexCmd\r
+* Description : Enables or disables the USART\92s Half Duplex communication.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* - NewState: new state of the USART Communication.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_HDSEL_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_HDSEL_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_IrDAConfig\r
+* Description : Configures the USART\92s IrDA interface.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* - USART_IrDAMode: specifies the IrDA mode.\r
+* This parameter can be one of the following values:\r
+* - USART_IrDAMode_LowPower\r
+* - USART_IrDAMode_Normal\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));\r
+ \r
+ USARTx->CR3 &= CR3_IRLP_Mask;\r
+ USARTx->CR3 |= USART_IrDAMode;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_IrDACmd\r
+* Description : Enables or disables the USART\92s IrDA interface.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* - NewState: new state of the IrDA mode.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_IREN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_IREN_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_GetFlagStatus\r
+* Description : Checks whether the specified USART flag is set or not.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* - USART_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - USART_FLAG_CTS: CTS Change flag (not available for \r
+* UART4 and UART5)\r
+* - USART_FLAG_LBD: LIN Break detection flag\r
+* - USART_FLAG_TXE: Transmit data register empty flag\r
+* - USART_FLAG_TC: Transmission Complete flag\r
+* - USART_FLAG_RXNE: Receive data register not empty flag\r
+* - USART_FLAG_IDLE: Idle Line detection flag\r
+* - USART_FLAG_ORE: OverRun Error flag\r
+* - USART_FLAG_NE: Noise Error flag\r
+* - USART_FLAG_FE: Framing Error flag\r
+* - USART_FLAG_PE: Parity Error flag\r
+* Output : None\r
+* Return : The new state of USART_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_FLAG(USART_FLAG));\r
+ assert_param(IS_USART_PERIPH_FLAG(USARTx, USART_FLAG)); /* The CTS flag is not available for UART4 and UART5 */ \r
+\r
+ if ((USARTx->SR & USART_FLAG) != (u16)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_ClearFlag\r
+* Description : Clears the USARTx's pending flags.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* - USART_FLAG: specifies the flag to clear.\r
+* This parameter can be any combination of the following values:\r
+* - USART_FLAG_CTS: CTS Change flag (not available for\r
+* UART4 and UART5).\r
+* - USART_FLAG_LBD: LIN Break detection flag.\r
+* - USART_FLAG_TC: Transmission Complete flag.\r
+* - USART_FLAG_RXNE: Receive data register not empty flag.\r
+* - USART_FLAG_IDLE: Idle Line detection flag.\r
+* - USART_FLAG_ORE: OverRun Error flag.\r
+* - USART_FLAG_NE: Noise Error flag.\r
+* - USART_FLAG_FE: Framing Error flag.\r
+* - USART_FLAG_PE: Parity Error flag.\r
+*\r
+* Note: - For IDLE, ORE, NE, FE and PE flags user has to read \r
+* the USART DR register after calling this function.\r
+* - TXE flag can't be cleared by this function, it's\r
+* cleared only by a write to the USART DR register. \r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));\r
+ assert_param(IS_USART_PERIPH_FLAG(USARTx, USART_FLAG)); /* The CTS flag is not available for UART4 and UART5 */ \r
+ \r
+ USARTx->SR = (u16)~USART_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_GetITStatus\r
+* Description : Checks whether the specified USART interrupt has occurred or not.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* - USART_IT: specifies the USART interrupt source to check.\r
+* This parameter can be one of the following values:\r
+* - USART_IT_CTS: CTS change interrupt (not available for \r
+* UART4 and UART5)\r
+* - USART_IT_LBD: LIN Break detection interrupt\r
+* - USART_IT_TXE: Tansmit Data Register empty interrupt\r
+* - USART_IT_TC: Transmission complete interrupt\r
+* - USART_IT_RXNE: Receive Data register not empty \r
+* interrupt\r
+* - USART_IT_IDLE: Idle line detection interrupt\r
+* - USART_IT_ORE: OverRun Error interrupt\r
+* - USART_IT_NE: Noise Error interrupt\r
+* - USART_IT_FE: Framing Error interrupt\r
+* - USART_IT_PE: Parity Error interrupt\r
+* Output : None\r
+* Return : The new state of USART_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT)\r
+{\r
+ u32 bitpos = 0x00, itmask = 0x00, usartreg = 0x00;\r
+ ITStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_IT(USART_IT));\r
+ assert_param(IS_USART_PERIPH_IT(USARTx, USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */ \r
+ \r
+ /* Get the USART register index */\r
+ usartreg = (((u8)USART_IT) >> 0x05);\r
+\r
+ /* Get the interrupt position */\r
+ itmask = USART_IT & IT_Mask;\r
+\r
+ itmask = (u32)0x01 << itmask;\r
+ \r
+ if (usartreg == 0x01) /* The IT is in CR1 register */\r
+ {\r
+ itmask &= USARTx->CR1;\r
+ }\r
+ else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ itmask &= USARTx->CR2;\r
+ }\r
+ else /* The IT is in CR3 register */\r
+ {\r
+ itmask &= USARTx->CR3;\r
+ }\r
+ \r
+ bitpos = USART_IT >> 0x08;\r
+\r
+ bitpos = (u32)0x01 << bitpos;\r
+ bitpos &= USARTx->SR;\r
+\r
+ if ((itmask != (u16)RESET)&&(bitpos != (u16)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ return bitstatus; \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_ClearITPendingBit\r
+* Description : Clears the USARTx\92s interrupt pending bits.\r
+* Input : - USARTx: Select the USART or the UART peripheral. \r
+* This parameter can be one of the following values:\r
+* - USART1, USART2, USART3, UART4 or UART5.\r
+* - USART_IT: specifies the interrupt pending bit to clear.\r
+* This parameter can be one of the following values:\r
+* - USART_IT_CTS: CTS change interrupt (not available for \r
+* UART4 and UART5)\r
+* - USART_IT_LBD: LIN Break detection interrupt\r
+* - USART_IT_TC: Transmission complete interrupt. \r
+* - USART_IT_RXNE: Receive Data register not empty interrupt.\r
+* - USART_IT_IDLE: Idle line detection interrupt.\r
+* - USART_IT_ORE: OverRun Error interrupt.\r
+* - USART_IT_NE: Noise Error interrupt.\r
+* - USART_IT_FE: Framing Error interrupt.\r
+* - USART_IT_PE: Parity Error interrupt.\r
+*\r
+* Note: - For IDLE, ORE, NE, FE and PE pending bits user has to \r
+* read the USART DR register after calling this function.\r
+* - TXE pending bit can't be cleared by this function, it's\r
+* cleared only by a write to the USART DR register.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT)\r
+{\r
+ u16 bitpos = 0x00, itmask = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLEAR_IT(USART_IT));\r
+ assert_param(IS_USART_PERIPH_IT(USARTx, USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */\r
+ \r
+ bitpos = USART_IT >> 0x08;\r
+\r
+ itmask = (u16)((u16)0x01 << bitpos);\r
+ USARTx->SR = (u16)~itmask;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*****************************************************************************\r
+ * Copyright (c) 2007 Rowley Associates Limited. *\r
+ * *\r
+ * This file may be distributed under the terms of the License Agreement *\r
+ * provided with this software. *\r
+ * *\r
+ * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *\r
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *\r
+ *****************************************************************************/\r
+\r
+/*****************************************************************************\r
+ * Preprocessor Definitions\r
+ * ------------------------\r
+ *\r
+ * STARTUP_FROM_RESET\r
+ *\r
+ * If defined, the program will startup from power-on/reset. If not defined\r
+ * the program will just loop endlessly from power-on/reset.\r
+ *\r
+ * This definition is not defined by default on this target because the\r
+ * debugger is unable to reset this target and maintain control of it over the\r
+ * JTAG interface. The advantage of doing this is that it allows the debugger\r
+ * to reset the CPU and run programs from a known reset CPU state on each run.\r
+ * It also acts as a safety net if you accidently download a program in FLASH\r
+ * that crashes and prevents the debugger from taking control over JTAG\r
+ * rendering the target unusable over JTAG. The obvious disadvantage of doing\r
+ * this is that your application will not startup without the debugger.\r
+ *\r
+ * We advise that on this target you keep STARTUP_FROM_RESET undefined whilst\r
+ * you are developing and only define STARTUP_FROM_RESET when development is\r
+ * complete.\r
+ *\r
+ *****************************************************************************/\r
+\r
+.extern xPortPendSVHandler\r
+.extern xPortSysTickHandler\r
+.extern vPortSVCHandler\r
+\r
+ .global reset_handler\r
+\r
+ .section .vectors, "ax"\r
+ .code 16\r
+ .align 0\r
+ .global _vectors\r
+\r
+.macro DEFAULT_ISR_HANDLER name=\r
+ .thumb_func\r
+ .weak \name\r
+\name:\r
+1: b 1b /* endless loop */\r
+.endm\r
+\r
+_vectors:\r
+ .word __stack_end__\r
+#ifdef STARTUP_FROM_RESET\r
+ .word reset_handler\r
+#else\r
+ .word reset_wait\r
+#endif /* STARTUP_FROM_RESET */\r
+ .word NMIException\r
+ .word HardFaultException\r
+ .word MemManageException \r
+ .word BusFaultException\r
+ .word UsageFaultException\r
+ .word 0 // Reserved\r
+ .word 0 // Reserved\r
+ .word 0 // Reserved\r
+ .word 0 // Reserved\r
+ .word vPortSVCHandler\r
+ .word DebugMonitor\r
+ .word 0 // Reserved\r
+ .word xPortPendSVHandler\r
+ .word xPortSysTickHandler\r
+ .word WWDG_IRQHandler\r
+ .word PVD_IRQHandler\r
+ .word TAMPER_IRQHandler\r
+ .word RTC_IRQHandler\r
+ .word FLASH_IRQHandler\r
+ .word RCC_IRQHandler\r
+ .word EXTI0_IRQHandler\r
+ .word EXTI1_IRQHandler\r
+ .word EXTI2_IRQHandler\r
+ .word EXTI3_IRQHandler\r
+ .word EXTI4_IRQHandler\r
+ .word DMAChannel1_IRQHandler\r
+ .word DMAChannel2_IRQHandler\r
+ .word DMAChannel3_IRQHandler\r
+ .word DMAChannel4_IRQHandler\r
+ .word DMAChannel5_IRQHandler\r
+ .word DMAChannel6_IRQHandler\r
+ .word DMAChannel7_IRQHandler\r
+ .word ADC_IRQHandler\r
+ .word USB_HP_CAN_TX_IRQHandler\r
+ .word USB_LP_CAN_RX0_IRQHandler\r
+ .word CAN_RX1_IRQHandler\r
+ .word CAN_SCE_IRQHandler\r
+ .word EXTI9_5_IRQHandler\r
+ .word TIM1_BRK_IRQHandler\r
+ .word TIM1_UP_IRQHandler\r
+ .word TIM1_TRG_COM_IRQHandler\r
+ .word TIM1_CC_IRQHandler\r
+ .word TIM2_IRQHandler\r
+ .word TIM3_IRQHandler\r
+ .word TIM4_IRQHandler \r
+ .word I2C1_EV_IRQHandler\r
+ .word I2C1_ER_IRQHandler\r
+ .word I2C2_EV_IRQHandler\r
+ .word I2C2_ER_IRQHandler\r
+ .word SPI1_IRQHandler\r
+ .word SPI2_IRQHandler\r
+ .word USART1_IRQHandler\r
+ .word USART2_IRQHandler\r
+ .word USART3_IRQHandler\r
+ .word EXTI15_10_IRQHandler\r
+ .word RTCAlarm_IRQHandler\r
+ .word USBWakeUp_IRQHandler\r
+ .word TIM8_BRK_IRQHandler\r
+ .word TIM8_UP_IRQHandler\r
+ .word TIM8_TRG_COM_IRQHandler\r
+ .word TIM8_CC_IRQHandler\r
+ .word ADC3_IRQHandler\r
+ .word FSMC_IRQHandler\r
+ .word SDIO_IRQHandler\r
+ .word TIM5_IRQHandler\r
+ .word SPI3_IRQHandler\r
+ .word UART4_IRQHandler\r
+ .word UART5_IRQHandler\r
+ .word TIM6_IRQHandler\r
+ .word TIM7_IRQHandler\r
+ .word DMA2_Channel1_IRQHandler\r
+ .word DMA2_Channel2_IRQHandler\r
+ .word DMA2_Channel3_IRQHandler\r
+ .word DMA2_Channel4_5_IRQHandler\r
+\r
+ .section .init, "ax"\r
+ .thumb_func\r
+\r
+ reset_handler:\r
+#ifndef __FLASH_BUILD\r
+ /* If this is a RAM build, configure vector table offset register to point \r
+ to the RAM vector table. */\r
+ ldr r0, =0xE000ED08\r
+ ldr r1, =_vectors\r
+ str r1, [r0]\r
+#endif\r
+ b _start\r
+\r
+DEFAULT_ISR_HANDLER NMIException\r
+DEFAULT_ISR_HANDLER HardFaultException \r
+DEFAULT_ISR_HANDLER MemManageException \r
+DEFAULT_ISR_HANDLER BusFaultException \r
+DEFAULT_ISR_HANDLER UsageFaultException \r
+DEFAULT_ISR_HANDLER SVCHandler \r
+DEFAULT_ISR_HANDLER DebugMonitor \r
+DEFAULT_ISR_HANDLER PendSV \r
+DEFAULT_ISR_HANDLER SysTickHandler \r
+DEFAULT_ISR_HANDLER WWDG_IRQHandler \r
+DEFAULT_ISR_HANDLER PVD_IRQHandler \r
+DEFAULT_ISR_HANDLER TAMPER_IRQHandler \r
+DEFAULT_ISR_HANDLER RTC_IRQHandler \r
+DEFAULT_ISR_HANDLER FLASH_IRQHandler \r
+DEFAULT_ISR_HANDLER RCC_IRQHandler \r
+DEFAULT_ISR_HANDLER EXTI0_IRQHandler \r
+DEFAULT_ISR_HANDLER EXTI1_IRQHandler \r
+DEFAULT_ISR_HANDLER EXTI2_IRQHandler \r
+DEFAULT_ISR_HANDLER EXTI3_IRQHandler \r
+DEFAULT_ISR_HANDLER EXTI4_IRQHandler \r
+DEFAULT_ISR_HANDLER DMAChannel1_IRQHandler \r
+DEFAULT_ISR_HANDLER DMAChannel2_IRQHandler \r
+DEFAULT_ISR_HANDLER DMAChannel3_IRQHandler \r
+DEFAULT_ISR_HANDLER DMAChannel4_IRQHandler \r
+DEFAULT_ISR_HANDLER DMAChannel5_IRQHandler \r
+DEFAULT_ISR_HANDLER DMAChannel6_IRQHandler \r
+DEFAULT_ISR_HANDLER DMAChannel7_IRQHandler \r
+DEFAULT_ISR_HANDLER ADC_IRQHandler \r
+DEFAULT_ISR_HANDLER USB_HP_CAN_TX_IRQHandler \r
+DEFAULT_ISR_HANDLER USB_LP_CAN_RX0_IRQHandler \r
+DEFAULT_ISR_HANDLER CAN_RX1_IRQHandler \r
+DEFAULT_ISR_HANDLER CAN_SCE_IRQHandler \r
+DEFAULT_ISR_HANDLER EXTI9_5_IRQHandler \r
+DEFAULT_ISR_HANDLER TIM1_BRK_IRQHandler \r
+DEFAULT_ISR_HANDLER TIM1_UP_IRQHandler \r
+DEFAULT_ISR_HANDLER TIM1_TRG_COM_IRQHandler \r
+DEFAULT_ISR_HANDLER TIM1_CC_IRQHandler \r
+DEFAULT_ISR_HANDLER TIM2_IRQHandler \r
+DEFAULT_ISR_HANDLER TIM3_IRQHandler \r
+DEFAULT_ISR_HANDLER TIM4_IRQHandler \r
+DEFAULT_ISR_HANDLER I2C1_EV_IRQHandler \r
+DEFAULT_ISR_HANDLER I2C1_ER_IRQHandler \r
+DEFAULT_ISR_HANDLER I2C2_EV_IRQHandler \r
+DEFAULT_ISR_HANDLER I2C2_ER_IRQHandler \r
+DEFAULT_ISR_HANDLER SPI1_IRQHandler \r
+DEFAULT_ISR_HANDLER SPI2_IRQHandler \r
+DEFAULT_ISR_HANDLER USART1_IRQHandler \r
+DEFAULT_ISR_HANDLER USART2_IRQHandler \r
+DEFAULT_ISR_HANDLER USART3_IRQHandler \r
+DEFAULT_ISR_HANDLER EXTI15_10_IRQHandler \r
+DEFAULT_ISR_HANDLER RTCAlarm_IRQHandler \r
+DEFAULT_ISR_HANDLER USBWakeUp_IRQHandler \r
+DEFAULT_ISR_HANDLER TIM8_BRK_IRQHandler\r
+DEFAULT_ISR_HANDLER TIM8_UP_IRQHandler\r
+DEFAULT_ISR_HANDLER TIM8_TRG_COM_IRQHandler\r
+DEFAULT_ISR_HANDLER TIM8_CC_IRQHandler\r
+DEFAULT_ISR_HANDLER ADC3_IRQHandler\r
+DEFAULT_ISR_HANDLER FSMC_IRQHandler\r
+DEFAULT_ISR_HANDLER SDIO_IRQHandler\r
+DEFAULT_ISR_HANDLER TIM5_IRQHandler\r
+DEFAULT_ISR_HANDLER SPI3_IRQHandler\r
+DEFAULT_ISR_HANDLER UART4_IRQHandler\r
+DEFAULT_ISR_HANDLER UART5_IRQHandler\r
+DEFAULT_ISR_HANDLER TIM6_IRQHandler\r
+DEFAULT_ISR_HANDLER TIM7_IRQHandler\r
+DEFAULT_ISR_HANDLER DMA2_Channel1_IRQHandler\r
+DEFAULT_ISR_HANDLER DMA2_Channel2_IRQHandler\r
+DEFAULT_ISR_HANDLER DMA2_Channel3_IRQHandler\r
+DEFAULT_ISR_HANDLER DMA2_Channel4_5_IRQHandler\r
+\r
+#ifndef STARTUP_FROM_RESET\r
+DEFAULT_ISR_HANDLER reset_wait\r
+#endif /* STARTUP_FROM_RESET */\r
+\r
+ // STM32 library requires these\r
+ .global __WFI\r
+ .global __WFE\r
+ .global __SEV\r
+ .global __ISB\r
+ .global __DSB\r
+ .global __DMB\r
+ .global __SVC\r
+ .global __MRS_CONTROL\r
+ .global __MSR_CONTROL\r
+ .global __MRS_PSP\r
+ .global __MSR_PSP\r
+ .global __MRS_MSP\r
+ .global __MSR_MSP \r
+ .global __SETPRIMASK\r
+ .global __RESETPRIMASK\r
+ .global __SETFAULTMASK\r
+ .global __RESETFAULTMASK\r
+ .global __BASEPRICONFIG\r
+ .global __GetBASEPRI\r
+ .global __REV_HalfWord\r
+ .global __REV_Word\r
+\r
+.thumb_func\r
+__WFI: \r
+ wfi\r
+ bx r14\r
+.thumb_func\r
+__WFE:\r
+ wfe\r
+ bx r14\r
+.thumb_func\r
+__SEV:\r
+ sev\r
+ bx r14\r
+.thumb_func\r
+__ISB:\r
+ isb\r
+ bx r14\r
+.thumb_func\r
+__DSB:\r
+ dsb\r
+ bx r14\r
+.thumb_func\r
+__DMB:\r
+ dmb\r
+ bx r14\r
+.thumb_func\r
+__SVC:\r
+ svc 0x01\r
+ bx r14\r
+.thumb_func\r
+__MRS_CONTROL:\r
+ mrs r0, control\r
+ bx r14\r
+.thumb_func\r
+__MSR_CONTROL:\r
+ msr control, r0\r
+ isb\r
+ bx r14\r
+.thumb_func\r
+__MRS_PSP:\r
+ mrs r0, psp\r
+ bx r14\r
+.thumb_func\r
+__MSR_PSP: \r
+ msr psp, r0\r
+ bx r14\r
+.thumb_func\r
+__MRS_MSP:\r
+ mrs r0, msp\r
+ bx r14\r
+.thumb_func\r
+__MSR_MSP: \r
+ msr msp, r0\r
+ bx r14\r
+.thumb_func\r
+__SETPRIMASK:\r
+ cpsid i\r
+ bx r14\r
+.thumb_func\r
+__RESETPRIMASK:\r
+ cpsie i\r
+ bx r14\r
+.thumb_func\r
+__SETFAULTMASK:\r
+ cpsid f\r
+ bx r14\r
+.thumb_func\r
+__RESETFAULTMASK:\r
+ cpsie f\r
+ bx r14\r
+.thumb_func\r
+__BASEPRICONFIG:\r
+ msr basepri, r0\r
+ bx r14\r
+.thumb_func\r
+__GetBASEPRI:\r
+ mrs r0, basepri_max\r
+ bx r14\r
+.thumb_func\r
+__REV_HalfWord:\r
+ rev16 r0, r0\r
+ bx r14\r
+.thumb_func\r
+__REV_Word: \r
+ rev r0, r0\r
+ bx r14\r
+ \r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * If you are: *\r
+ * *\r
+ * + New to FreeRTOS, *\r
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *\r
+ * + Looking for basic training, *\r
+ * + Wanting to improve your FreeRTOS skills and productivity *\r
+ * *\r
+ * then take a look at the FreeRTOS eBook *\r
+ * *\r
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * A pdf reference manual is also available. Both are usually delivered *\r
+ * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+ * and 8pm GMT (although please allow up to 24 hours in case of *\r
+ * exceptional circumstances). Thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+ a combined work that includes FreeRTOS without being obliged to provide the\r
+ source code for proprietary components outside of the FreeRTOS kernel.\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public \r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it \r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained \r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the standard demo application tasks\r
+ * (which just exist to test the kernel port and provide an example of how to use\r
+ * each FreeRTOS API function).\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Check" task - This only executes every five seconds but has the highest\r
+ * priority so is guaranteed to get processor time. Its main function is to \r
+ * check that all the standard demo tasks are still operational. The check task\r
+ * will toggle LED 7 (PB15) every five seconds so long as no errors have been\r
+ * detected. The toggle rate will increase to half a second if an error has \r
+ * been found in any task.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Library includes. */\r
+#include "stm32f10x_it.h"\r
+#include "stm32f10x_tim.h"\r
+\r
+/* Demo app includes. */\r
+#include "BlockQ.h"\r
+#include "integer.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "semtest.h"\r
+#include "GenQTest.h"\r
+#include "QPeek.h"\r
+#include "recmutex.h"\r
+\r
+\r
+/* The time between cycles of the 'check' task - which depends on whether the\r
+check task has detected an error or not. */\r
+#define mainCHECK_DELAY_NO_ERROR ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+#define mainCHECK_DELAY_ERROR ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+\r
+/* The LED controlled by the 'check' task. */\r
+#define mainCHECK_LED ( 7 )\r
+\r
+/* Task priorities. */\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The WEB server has a larger stack as it utilises stack hungry string\r
+handling library calls. */\r
+#define mainBASIC_WEB_STACK_SIZE ( configMINIMAL_STACK_SIZE * 4 )\r
+\r
+/* The length of the queue used to send messages to the LCD task. */\r
+#define mainQUEUE_SIZE ( 3 )\r
+\r
+/* The period of the system clock in nano seconds. This is used to calculate\r
+the jitter time in nano seconds. */\r
+#define mainNS_PER_CLOCK ( ( unsigned long ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Configure the hardware for the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/* The 'check' task as described at the top of this file. */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+#ifdef DEBUG\r
+ debug();\r
+#endif\r
+\r
+ /* Set up the clocks and memory interface. */\r
+ prvSetupHardware();\r
+\r
+ /* Start the standard demo tasks. These are just here to exercise the\r
+ kernel port and provide examples of how the FreeRTOS API can be used. */\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );\r
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+ vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );\r
+ vStartQueuePeekTasks();\r
+ vStartRecursiveMutexTasks();\r
+\r
+ /* Create the 'check' task, which is defined within this file. */\r
+ xTaskCreate( prvCheckTask, ( signed char * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only get here if there was insufficient memory to create the idle\r
+ task. The idle task is created within vTaskStartScheduler(). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+portTickType xLastExecutionTime;\r
+unsigned long ulTicksToWait = mainCHECK_DELAY_NO_ERROR;\r
+\r
+ /* Just to remove the compiler warning about the unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise the variable used to control our iteration rate prior to\r
+ its first use. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time to run the tests again. */\r
+ vTaskDelayUntil( &xLastExecutionTime, ulTicksToWait );\r
+\r
+ /* Has an error been found in any task? */\r
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ /* Reduce the time between cycles of this task - which has the\r
+ effect of increasing the rate at which the 'check' LED toggles to\r
+ indicate the existence of an error to an observer. */\r
+ ulTicksToWait = mainCHECK_DELAY_ERROR;\r
+ }\r
+ else if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainCHECK_DELAY_ERROR;\r
+ }\r
+ else if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainCHECK_DELAY_ERROR;\r
+ }\r
+ else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainCHECK_DELAY_ERROR;\r
+ }\r
+ else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainCHECK_DELAY_ERROR;\r
+ }\r
+ else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulTicksToWait = mainCHECK_DELAY_ERROR;\r
+ }\r
+\r
+ vParTestToggleLED( mainCHECK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* RCC system reset(for debug purpose). */\r
+ RCC_DeInit (); \r
+\r
+ /* Enable HSE. */\r
+ RCC_HSEConfig (RCC_HSE_ON); \r
+ \r
+ /* Wait till HSE is ready. */\r
+ while (RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET);\r
+ \r
+ /* HCLK = SYSCLK. */\r
+ RCC_HCLKConfig (RCC_SYSCLK_Div1); \r
+\r
+ /* PCLK2 = HCLK. */\r
+ RCC_PCLK2Config (RCC_HCLK_Div1); \r
+\r
+ /* PCLK1 = HCLK/2. */\r
+ RCC_PCLK1Config (RCC_HCLK_Div2); \r
+\r
+ /* ADCCLK = PCLK2/4. */\r
+ RCC_ADCCLKConfig (RCC_PCLK2_Div4); \r
+ \r
+ /* Flash 2 wait state. */\r
+ *( volatile unsigned long * )0x40022000 = 0x01; \r
+ \r
+ /* PLLCLK = 8MHz * 9 = 72 MHz */\r
+ RCC_PLLConfig (RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);\r
+ \r
+ /* Enable PLL. */\r
+ RCC_PLLCmd (ENABLE); \r
+ \r
+ /* Wait till PLL is ready. */\r
+ while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);\r
+ \r
+ /* Select PLL as system clock source. */\r
+ RCC_SYSCLKConfig (RCC_SYSCLKSource_PLLCLK);\r
+ \r
+ /* Wait till PLL is used as system clock source. */\r
+ while (RCC_GetSYSCLKSource() != 0x08);\r
+\r
+ /* Enable GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and AFIO clocks */\r
+ RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |RCC_APB2Periph_GPIOC\r
+ | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO, ENABLE );\r
+\r
+ /* Set the Vector Table base address at 0x08000000. */\r
+ NVIC_SetVectorTable( NVIC_VectTab_FLASH, 0x0 );\r
+\r
+ NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 );\r
+\r
+ /* Configure HCLK clock as SysTick clock source. */\r
+ SysTick_CLKSourceConfig( SysTick_CLKSource_HCLK );\r
+\r
+ /* Initialise the IO used for the LED outputs. */\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )\r
+{\r
+ /* This function will get called if a task overflows its stack. If the\r
+ parameters are corrupt then inspect pxCurrentTCB to find which was the\r
+ offending task. */\r
+\r
+ ( void ) pxTask;\r
+ ( void ) pcTaskName;\r
+\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void assert_failed( unsigned char *pucFile, unsigned long ulLine )\r
+{\r
+ ( void ) pucFile;\r
+ ( void ) ulLine;\r
+\r
+ for( ;; );\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * If you are: *\r
+ * *\r
+ * + New to FreeRTOS, *\r
+ * + Wanting to learn FreeRTOS or multitasking in general quickly *\r
+ * + Looking for basic training, *\r
+ * + Wanting to improve your FreeRTOS skills and productivity *\r
+ * *\r
+ * then take a look at the FreeRTOS eBook *\r
+ * *\r
+ * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * A pdf reference manual is also available. Both are usually delivered *\r
+ * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+ * and 8pm GMT (although please allow up to 24 hours in case of *\r
+ * exceptional circumstances). Thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+ a combined work that includes FreeRTOS without being obliged to provide the\r
+ source code for proprietary components outside of the FreeRTOS kernel.\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public \r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it \r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained \r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*\r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Library includes. */\r
+#include "stm32f10x_lib.h"\r
+\r
+/* Demo application includes. */\r
+#include "serial.h"\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Misc defines. */\r
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+#define serTX_BLOCK_TIME ( 40 / portTICK_RATE_MS )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to hold received characters. */\r
+static xQueueHandle xRxedChars;\r
+static xQueueHandle xCharsForTx;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* UART interrupt handler. */\r
+void vUARTInterruptHandler( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See the serial2.h header file.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+xComPortHandle xReturn;\r
+USART_InitTypeDef USART_InitStructure;\r
+NVIC_InitTypeDef NVIC_InitStructure;\r
+GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+ /* Create the queues used to hold Rx/Tx characters. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ \r
+ /* If the queue/semaphore was created correctly then setup the serial port\r
+ hardware. */\r
+ if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )\r
+ {\r
+ /* Enable USART1 clock */\r
+ RCC_APB2PeriphClockCmd( RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE ); \r
+\r
+ /* Configure USART1 Rx (PA10) as input floating */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;\r
+ GPIO_Init( GPIOA, &GPIO_InitStructure );\r
+ \r
+ /* Configure USART1 Tx (PA9) as alternate function push-pull */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;\r
+ GPIO_Init( GPIOA, &GPIO_InitStructure );\r
+\r
+ USART_InitStructure.USART_BaudRate = ulWantedBaud;\r
+ USART_InitStructure.USART_WordLength = USART_WordLength_8b;\r
+ USART_InitStructure.USART_StopBits = USART_StopBits_1;\r
+ USART_InitStructure.USART_Parity = USART_Parity_No;\r
+ USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;\r
+ USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
+ \r
+ USART_Init( USART1, &USART_InitStructure );\r
+ \r
+ USART_ITConfig( USART1, USART_IT_RXNE, ENABLE );\r
+ \r
+ NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQChannel;\r
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_KERNEL_INTERRUPT_PRIORITY;\r
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;\r
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+ NVIC_Init( &NVIC_InitStructure );\r
+ \r
+ USART_Cmd( USART1, ENABLE ); \r
+ }\r
+ else\r
+ {\r
+ xReturn = ( xComPortHandle ) 0;\r
+ }\r
+\r
+ /* This demo file only supports a single port but we have to return\r
+ something to comply with the standard demo header file. */\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports one port. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )\r
+{\r
+signed portCHAR *pxNext;\r
+\r
+ /* A couple of parameters that this port does not use. */\r
+ ( void ) usStringLength;\r
+ ( void ) pxPort;\r
+\r
+ /* NOTE: This implementation does not handle the queue being full as no\r
+ block time is used! */\r
+\r
+ /* The port handle is not required as this driver only supports UART1. */\r
+ ( void ) pxPort;\r
+\r
+ /* Send each character in the string, one at a time. */\r
+ pxNext = ( signed portCHAR * ) pcString;\r
+ while( *pxNext )\r
+ {\r
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+ pxNext++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* Just to remove the compiler warning. */\r
+ ( void ) pxPort;\r
+\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )\r
+ {\r
+ xReturn = pdPASS;\r
+ USART_ITConfig( USART1, USART_IT_TXE, ENABLE );\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUARTInterruptHandler( void )\r
+{\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+portCHAR cChar;\r
+\r
+ if( USART_GetITStatus( USART1, USART_IT_TXE ) == SET )\r
+ {\r
+ /* The interrupt was caused by the THR becoming empty. Are there any\r
+ more characters to transmit? */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )\r
+ {\r
+ /* A character was retrieved from the queue so can be sent to the\r
+ THR now. */\r
+ USART_SendData( USART1, cChar );\r
+ }\r
+ else\r
+ {\r
+ USART_ITConfig( USART1, USART_IT_TXE, DISABLE ); \r
+ } \r
+ }\r
+ \r
+ if( USART_GetITStatus( USART1, USART_IT_RXNE ) == SET )\r
+ {\r
+ cChar = USART_ReceiveData( USART1 );\r
+ xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );\r
+ } \r
+ \r
+ portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
+\r
+\r
+\r
+\r
+\r
+ \r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_conf.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : Library configuration file.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_CONF_H\r
+#define __STM32F10x_CONF_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_type.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Uncomment the line below to compile the library in DEBUG mode, this will expanse\r
+ the "assert_param" macro in the firmware library code (see "Exported macro"\r
+ section below) */\r
+/*#define DEBUG 1*/\r
+\r
+/* Comment the line below to disable the specific peripheral inclusion */\r
+/************************************* ADC ************************************/\r
+//#define _ADC\r
+//#define _ADC1\r
+//#define _ADC2\r
+//#define _ADC3\r
+\r
+/************************************* BKP ************************************/\r
+//#define _BKP \r
+\r
+/************************************* CAN ************************************/\r
+#define _CAN\r
+\r
+/************************************* CRC ************************************/\r
+//#define _CRC\r
+\r
+/************************************* DAC ************************************/\r
+//#define _DAC\r
+\r
+/************************************* DBGMCU *********************************/\r
+//#define _DBGMCU\r
+\r
+/************************************* DMA ************************************/\r
+//#define _DMA\r
+//#define _DMA1_Channel1\r
+//#define _DMA1_Channel2\r
+//#define _DMA1_Channel3\r
+//#define _DMA1_Channel4\r
+//#define _DMA1_Channel5\r
+//#define _DMA1_Channel6\r
+//#define _DMA1_Channel7\r
+//#define _DMA2_Channel1\r
+//#define _DMA2_Channel2\r
+//#define _DMA2_Channel3\r
+//#define _DMA2_Channel4\r
+//#define _DMA2_Channel5\r
+\r
+/************************************* EXTI ***********************************/\r
+//#define _EXTI\r
+\r
+/************************************* FLASH and Option Bytes *****************/\r
+#define _FLASH\r
+/* Uncomment the line below to enable FLASH program/erase/protections functions,\r
+ otherwise only FLASH configuration (latency, prefetch, half cycle) functions\r
+ are enabled */\r
+/* #define _FLASH_PROG */\r
+\r
+/************************************* FSMC ***********************************/\r
+//#define _FSMC\r
+\r
+/************************************* GPIO ***********************************/\r
+#define _GPIO\r
+#define _GPIOA\r
+#define _GPIOB\r
+//#define _GPIOC\r
+#define _GPIOD\r
+#define _GPIOE\r
+//#define _GPIOF\r
+//#define _GPIOG\r
+#define _AFIO\r
+\r
+/************************************* I2C ************************************/\r
+#define _I2C\r
+#define _I2C1\r
+//#define _I2C2\r
+\r
+/************************************* IWDG ***********************************/\r
+//#define _IWDG\r
+\r
+/************************************* NVIC ***********************************/\r
+#define _NVIC\r
+\r
+/************************************* PWR ************************************/\r
+//#define _PWR\r
+\r
+/************************************* RCC ************************************/\r
+#define _RCC\r
+\r
+/************************************* RTC ************************************/\r
+//#define _RTC\r
+\r
+/************************************* SDIO ***********************************/\r
+//#define _SDIO\r
+\r
+/************************************* SPI ************************************/\r
+#define _SPI\r
+#define _SPI1\r
+//#define _SPI2\r
+//#define _SPI3\r
+\r
+/************************************* SysTick ********************************/\r
+#define _SysTick\r
+\r
+/************************************* TIM ************************************/\r
+//#define _TIM\r
+//#define _TIM1\r
+//#define _TIM2\r
+//#define _TIM3\r
+//#define _TIM4\r
+//#define _TIM5\r
+//#define _TIM6\r
+//#define _TIM7\r
+//#define _TIM8\r
+\r
+/************************************* USART **********************************/\r
+#define _USART\r
+#define _USART1\r
+//#define _USART2\r
+//#define _USART3\r
+//#define _UART4\r
+//#define _UART5\r
+\r
+/************************************* WWDG ***********************************/\r
+//#define _WWDG\r
+\r
+/* In the following line adjust the value of External High Speed oscillator (HSE)\r
+ used in your application */\r
+#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef DEBUG\r
+/*******************************************************************************\r
+* Macro Name : assert_param\r
+* Description : The assert_param macro is used for function's parameters check.\r
+* It is used only if the library is compiled in DEBUG mode. \r
+* Input : - expr: If expr is false, it calls assert_failed function\r
+* which reports the name of the source file and the source\r
+* line number of the call that failed. \r
+* If expr is true, it returns no value.\r
+* Return : None\r
+*******************************************************************************/ \r
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+ void assert_failed(u8* file, u32 line);\r
+#else\r
+ #define assert_param(expr) ((void)0)\r
+#endif /* DEBUG */\r
+\r
+#endif /* __STM32F10x_CONF_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************\r
+* File Name : stm32f10x_it.h\r
+* Author : MCD Application Team\r
+* Version : V2.0.1\r
+* Date : 06/13/2008\r
+* Description : This file contains the headers of the interrupt handlers.\r
+********************************************************************************\r
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_IT_H\r
+#define __STM32F10x_IT_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_lib.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void NMIException(void);\r
+void HardFaultException(void);\r
+void MemManageException(void);\r
+void BusFaultException(void);\r
+void UsageFaultException(void);\r
+void DebugMonitor(void);\r
+void SVCHandler(void);\r
+void PendSVC(void);\r
+void SysTickHandler(void);\r
+void WWDG_IRQHandler(void);\r
+void PVD_IRQHandler(void);\r
+void TAMPER_IRQHandler(void);\r
+void RTC_IRQHandler(void);\r
+void FLASH_IRQHandler(void);\r
+void RCC_IRQHandler(void);\r
+void EXTI0_IRQHandler(void);\r
+void EXTI1_IRQHandler(void);\r
+void EXTI2_IRQHandler(void);\r
+void EXTI3_IRQHandler(void);\r
+void EXTI4_IRQHandler(void);\r
+void DMA1_Channel1_IRQHandler(void);\r
+void DMA1_Channel2_IRQHandler(void);\r
+void DMA1_Channel3_IRQHandler(void);\r
+void DMA1_Channel4_IRQHandler(void);\r
+void DMA1_Channel5_IRQHandler(void);\r
+void DMA1_Channel6_IRQHandler(void);\r
+void DMA1_Channel7_IRQHandler(void);\r
+void ADC1_2_IRQHandler(void);\r
+void USB_HP_CAN_TX_IRQHandler(void);\r
+void USB_LP_CAN_RX0_IRQHandler(void);\r
+void CAN_RX1_IRQHandler(void);\r
+void CAN_SCE_IRQHandler(void);\r
+void EXTI9_5_IRQHandler(void);\r
+void TIM1_BRK_IRQHandler(void);\r
+void TIM1_UP_IRQHandler(void);\r
+void TIM1_TRG_COM_IRQHandler(void);\r
+void TIM1_CC_IRQHandler(void);\r
+void TIM2_IRQHandler(void);\r
+void TIM3_IRQHandler(void);\r
+void TIM4_IRQHandler(void);\r
+void I2C1_EV_IRQHandler(void);\r
+void I2C1_ER_IRQHandler(void);\r
+void I2C2_EV_IRQHandler(void);\r
+void I2C2_ER_IRQHandler(void);\r
+void SPI1_IRQHandler(void);\r
+void SPI2_IRQHandler(void);\r
+void USART1_IRQHandler(void);\r
+void USART2_IRQHandler(void);\r
+void USART3_IRQHandler(void);\r
+void EXTI15_10_IRQHandler(void);\r
+void RTCAlarm_IRQHandler(void);\r
+void USBWakeUp_IRQHandler(void);\r
+void TIM8_BRK_IRQHandler(void);\r
+void TIM8_UP_IRQHandler(void);\r
+void TIM8_TRG_COM_IRQHandler(void);\r
+void TIM8_CC_IRQHandler(void);\r
+void ADC3_IRQHandler(void);\r
+void FSMC_IRQHandler(void);\r
+void SDIO_IRQHandler(void);\r
+void TIM5_IRQHandler(void);\r
+void SPI3_IRQHandler(void);\r
+void UART4_IRQHandler(void);\r
+void UART5_IRQHandler(void);\r
+void TIM6_IRQHandler(void);\r
+void TIM7_IRQHandler(void);\r
+void DMA2_Channel1_IRQHandler(void);\r
+void DMA2_Channel2_IRQHandler(void);\r
+void DMA2_Channel3_IRQHandler(void);\r
+void DMA2_Channel4_5_IRQHandler(void);\r
+ \r
+#endif /* __STM32F10x_IT_H */\r
+\r
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/\r
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