};
struct davinci_nand {
- struct target *target;
-
uint8_t chipsel; /* chipselect 0..3 == CS2..CS5 */
uint8_t eccmode;
static int davinci_init(struct nand_device *nand)
{
struct davinci_nand *info = nand->controller_priv;
- struct target *target = info->target;
+ struct target *target = nand->target;
uint32_t nandfcr;
if (!halted(target, "init"))
static int davinci_nand_ready(struct nand_device *nand, int timeout)
{
struct davinci_nand *info = nand->controller_priv;
- struct target *target = info->target;
+ struct target *target = nand->target;
uint32_t nandfsr;
/* NOTE: return code is zero/error, else success; not ERROR_* */
static int davinci_command(struct nand_device *nand, uint8_t command)
{
struct davinci_nand *info = nand->controller_priv;
- struct target *target = info->target;
+ struct target *target = nand->target;
if (!halted(target, "command"))
return ERROR_NAND_OPERATION_FAILED;
static int davinci_address(struct nand_device *nand, uint8_t address)
{
struct davinci_nand *info = nand->controller_priv;
- struct target *target = info->target;
+ struct target *target = nand->target;
if (!halted(target, "address"))
return ERROR_NAND_OPERATION_FAILED;
static int davinci_write_data(struct nand_device *nand, uint16_t data)
{
struct davinci_nand *info = nand->controller_priv;
- struct target *target = info->target;
+ struct target *target = nand->target;
if (!halted(target, "write_data"))
return ERROR_NAND_OPERATION_FAILED;
static int davinci_read_data(struct nand_device *nand, void *data)
{
struct davinci_nand *info = nand->controller_priv;
- struct target *target = info->target;
+ struct target *target = nand->target;
if (!halted(target, "read_data"))
return ERROR_NAND_OPERATION_FAILED;
uint8_t *data, int data_size)
{
struct davinci_nand *info = nand->controller_priv;
- struct target *target = info->target;
+ struct target *target = nand->target;
uint32_t nfdata = info->data;
uint32_t tmp;
uint8_t *data, int data_size)
{
struct davinci_nand *info = nand->controller_priv;
- struct target *target = info->target;
+ struct target *target = nand->target;
uint32_t nfdata = info->data;
uint32_t tmp;
int status;
if (!nand->device)
return ERROR_NAND_DEVICE_NOT_PROBED;
- if (!halted(info->target, "write_page"))
+ if (!halted(nand->target, "write_page"))
return ERROR_NAND_OPERATION_FAILED;
/* Always write both data and OOB ... we are not "raw" I/O! */
if (!nand->device)
return ERROR_NAND_DEVICE_NOT_PROBED;
- if (!halted(info->target, "read_page"))
+ if (!halted(nand->target, "read_page"))
return ERROR_NAND_OPERATION_FAILED;
return info->read_page(nand, page, data, data_size, oob, oob_size);
static void davinci_write_pagecmd(struct nand_device *nand, uint8_t cmd, uint32_t page)
{
struct davinci_nand *info = nand->controller_priv;
- struct target *target = info->target;
+ struct target *target = nand->target;
int page3 = nand->address_cycles - (nand->page_size == 512);
/* write command ({page,otp}x{read,program} */
static int davinci_seek_column(struct nand_device *nand, uint16_t column)
{
struct davinci_nand *info = nand->controller_priv;
- struct target *target = info->target;
+ struct target *target = nand->target;
/* Random read, we must have issued a page read already */
target_write_u8(target, info->cmd, NAND_CMD_RNDOUT);
uint8_t *oob, uint32_t oob_size)
{
struct davinci_nand *info = nand->controller_priv;
- struct target *target = info->target;
+ struct target *target = nand->target;
uint8_t status;
if (oob_size)
{
unsigned oob_offset;
struct davinci_nand *info = nand->controller_priv;
- struct target *target = info->target;
+ struct target *target = nand->target;
const uint32_t fcr_addr = info->aemif + NANDFCR;
const uint32_t ecc1_addr = info->aemif + NANDFECC + (4 * info->chipsel);
uint32_t fcr, ecc1;
struct davinci_nand *info = nand->controller_priv;
const uint8_t *l;
- struct target *target = info->target;
+ struct target *target = nand->target;
const uint32_t fcr_addr = info->aemif + NANDFCR;
const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
uint32_t fcr, ecc4;
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
{
struct davinci_nand *info = nand->controller_priv;
- struct target *target = info->target;
+ struct target *target = nand->target;
const uint32_t fcr_addr = info->aemif + NANDFCR;
const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
uint32_t fcr, ecc4;
NAND_DEVICE_COMMAND_HANDLER(davinci_nand_device_command)
{
struct davinci_nand *info;
- struct target *target;
unsigned long chip, aemif;
enum ecc eccmode;
int chipsel;
goto fail;
}
- target = get_target(CMD_ARGV[1]);
- if (!target) {
- LOG_ERROR("invalid target %s", CMD_ARGV[1]);
- goto fail;
- }
-
COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], chip);
if (chip == 0) {
LOG_ERROR("Invalid NAND chip address %s", CMD_ARGV[2]);
if (info == NULL)
goto fail;
- info->target = target;
info->eccmode = eccmode;
info->chipsel = chipsel;
info->aemif = aemif;
nand->controller_priv = info;
- info->io.target = target;
+ info->io.target = nand->target;
info->io.data = info->data;
info->io.op = ARM_NAND_NONE;