--- /dev/null
+/**************************************************************************//**\r
+ * @file\r
+ * @brief CMSIS Cortex-M3 Peripheral Access Layer for EFM EFM32G890F128\r
+ * @author Energy Micro AS\r
+ * @version 1.0.2\r
+ ******************************************************************************\r
+ * @section License\r
+ * <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>\r
+ ******************************************************************************\r
+ *\r
+ * This source code is the property of Energy Micro AS. The source and compiled\r
+ * code may only be used on Energy Micro "EFM32" microcontrollers.\r
+ *\r
+ * This copyright notice may not be removed from the source code nor changed.\r
+ *\r
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no\r
+ * obligation to support this Software. Energy Micro AS is providing the\r
+ * Software "AS IS", with no express or implied warranties of any kind,\r
+ * including, but not limited to, any implied warranties of merchantability\r
+ * or fitness for any particular purpose or warranties against infringement\r
+ * of any proprietary rights of a third party.\r
+ *\r
+ * Energy Micro AS will not be liable for any consequential, incidental, or\r
+ * special damages, or any other relief, or for any claim by any third party,\r
+ * arising from your use of this Software.\r
+ *\r
+ *****************************************************************************/\r
+\r
+#ifndef __EFM32G890F128_H\r
+#define __EFM32G890F128_H\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @defgroup EFM32G890F128 EFM32G890F128\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
+\r
+/****** EFM32G Peripheral Interrupt Numbers **************************************************/\r
+ DMA_IRQn = 0, /*!< DMA Interrupt */\r
+ GPIO_EVEN_IRQn = 1, /*!< GPIO_EVEN Interrupt */\r
+ TIMER0_IRQn = 2, /*!< TIMER0 Interrupt */\r
+ USART0_RX_IRQn = 3, /*!< USART0_RX Interrupt */\r
+ USART0_TX_IRQn = 4, /*!< USART0_TX Interrupt */\r
+ ACMP0_IRQn = 5, /*!< ACMP0 Interrupt */\r
+ ADC0_IRQn = 6, /*!< ADC0 Interrupt */\r
+ DAC0_IRQn = 7, /*!< DAC0 Interrupt */\r
+ I2C0_IRQn = 8, /*!< I2C0 Interrupt */\r
+ GPIO_ODD_IRQn = 9, /*!< GPIO_ODD Interrupt */\r
+ TIMER1_IRQn = 10, /*!< TIMER1 Interrupt */\r
+ TIMER2_IRQn = 11, /*!< TIMER2 Interrupt */\r
+ USART1_RX_IRQn = 12, /*!< USART1_RX Interrupt */\r
+ USART1_TX_IRQn = 13, /*!< USART1_TX Interrupt */\r
+ USART2_RX_IRQn = 14, /*!< USART2_RX Interrupt */\r
+ USART2_TX_IRQn = 15, /*!< USART2_TX Interrupt */\r
+ UART0_RX_IRQn = 16, /*!< UART0_RX Interrupt */\r
+ UART0_TX_IRQn = 17, /*!< UART0_TX Interrupt */\r
+ LEUART0_IRQn = 18, /*!< LEUART0 Interrupt */\r
+ LEUART1_IRQn = 19, /*!< LEUART1 Interrupt */\r
+ LETIMER0_IRQn = 20, /*!< LETIMER0 Interrupt */\r
+ PCNT0_IRQn = 21, /*!< PCNT0 Interrupt */\r
+ PCNT1_IRQn = 22, /*!< PCNT1 Interrupt */\r
+ PCNT2_IRQn = 23, /*!< PCNT2 Interrupt */\r
+ RTC_IRQn = 24, /*!< RTC Interrupt */\r
+ CMU_IRQn = 25, /*!< CMU Interrupt */\r
+ VCMP_IRQn = 26, /*!< VCMP Interrupt */\r
+ LCD_IRQn = 27, /*!< LCD Interrupt */\r
+ MSC_IRQn = 28, /*!< MSC Interrupt */\r
+ AES_IRQn = 29, /*!< AES Interrupt */\r
+} IRQn_Type;\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32G890F128_Core EFM32G890F128 Core\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define __MPU_PRESENT 1 /**< Presence of MPU */\r
+#define __NVIC_PRIO_BITS 3 /**< NVIC intterupt priority bits */\r
+#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**************************************************************************//**\r
+* @defgroup EFM32G890F128_Part EFM32G890F128 Part\r
+* @{\r
+******************************************************************************/\r
+\r
+#if !defined(EFM32G890F128)\r
+#define EFM32G890F128\r
+#endif\r
+\r
+/** Configure part number */\r
+#define PART_NUMBER "EFM32G890F128" /**< Part Number */\r
+\r
+/** Memory Base addresses and limits */\r
+#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
+#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */\r
+#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */\r
+#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */\r
+#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
+#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
+#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
+#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
+#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
+#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
+#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
+#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
+#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
+#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */\r
+#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */\r
+#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */\r
+#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
+#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */\r
+#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */\r
+#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */\r
+#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
+#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
+#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
+#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
+\r
+/** Flash and SRAM limits for EFM32G890F128 */\r
+#define FLASH_SIZE 0x00020000UL /**< Available flash memory */\r
+#define SRAM_SIZE 0x00004000UL /**< Available sram memory */\r
+#define __CM3_REV 0x200 /**< Cortex-M3 Core revision r2p0 */\r
+#define DPI_CHAN_COUNT 8 /**< Number of DPI channels */\r
+#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */\r
+/* Part number capabilities */\r
+#define TIMER_PRESENT\r
+#define TIMER_COUNT 3\r
+#define TIMER_PARAM_DTI(i) (i == 0 ? 1 : i == 1 ? 0 : i == 2 ? 0 : 0)\r
+#define TIMER_PARAM_CCNUM(i) (i == 0 ? 3 : i == 1 ? 3 : i == 2 ? 3 : 0)\r
+#define USART_PRESENT\r
+#define USART_COUNT 3\r
+#define USART_PARAM_SC_AVAILABLE(i) (i == 0 ? 1 : i == 1 ? 1 : i == 2 ? 1 : 0)\r
+#define USART_PARAM_IRDA_AVAILABLE(i) (i == 0 ? 1 : i == 1 ? 0 : i == 2 ? 0 : 0)\r
+#define USART_PARAM_FULL_DATABIT_RANGE(i) (i == 0 ? 1 : i == 1 ? 1 : i == 2 ? 1 : 0)\r
+#define USART_PARAM_SYNC_AVAILABLE(i) (i == 0 ? 1 : i == 1 ? 1 : i == 2 ? 1 : 0)\r
+#define UART_PRESENT\r
+#define UART_COUNT 1\r
+#define UART_PARAM_SC_AVAILABLE(i) (i == 0 ? 0 : 0)\r
+#define UART_PARAM_IRDA_AVAILABLE(i) (i == 0 ? 0 : 0)\r
+#define UART_PARAM_FULL_DATABIT_RANGE(i) (i == 0 ? 0 : 0)\r
+#define UART_PARAM_SYNC_AVAILABLE(i) (i == 0 ? 0 : 0)\r
+#define LEUART_PRESENT\r
+#define LEUART_COUNT 2\r
+#define LETIMER_PRESENT\r
+#define LETIMER_COUNT 1\r
+#define PCNT_PRESENT\r
+#define PCNT_COUNT 3\r
+#define PCNT_PARAM_PCNT_WIDTH(i) (i == 0 ? 16 : i == 1 ? 8 : i == 2 ? 8 : 0)\r
+#define I2C_PRESENT\r
+#define I2C_COUNT 1\r
+#define ADC_PRESENT\r
+#define ADC_COUNT 1\r
+#define ADC_PARAM_RES(i) (i == 0 ? 12 : 0)\r
+#define DAC_PRESENT\r
+#define DAC_COUNT 1\r
+#define DAC_PARAM_RES(i) (i == 0 ? 12 : 0)\r
+#define ACMP_PRESENT\r
+#define ACMP_COUNT 2\r
+#define CM3_PRESENT\r
+#define CM3_COUNT 1\r
+#define CM3_FREE_PRESENT\r
+#define CM3_FREE_COUNT 1\r
+#define BUSMATRIX_PRESENT\r
+#define BUSMATRIX_COUNT 1\r
+#define DMEM_PRESENT\r
+#define DMEM_COUNT 1\r
+#define AHB2APB_PRESENT\r
+#define AHB2APB_COUNT 1\r
+#define LE_PRESENT\r
+#define LE_COUNT 1\r
+#define MSC_PRESENT\r
+#define MSC_COUNT 1\r
+#define EMU_PRESENT\r
+#define EMU_COUNT 1\r
+#define RMU_PRESENT\r
+#define RMU_COUNT 1\r
+#define CMU_PRESENT\r
+#define CMU_COUNT 1\r
+#define AES_PRESENT\r
+#define AES_COUNT 1\r
+#define EBI_PRESENT\r
+#define EBI_COUNT 1\r
+#define GPIO_PRESENT\r
+#define GPIO_COUNT 1\r
+#define PRS_PRESENT\r
+#define PRS_COUNT 1\r
+#define DMA_PRESENT\r
+#define DMA_COUNT 1\r
+#define VCMP_PRESENT\r
+#define VCMP_COUNT 1\r
+#define LCD_PRESENT\r
+#define LCD_COUNT 1\r
+#define LCD_PARAM_SEG_NUM 40\r
+#define LCD_PARAM_COM_NUM 4\r
+#define RTC_PRESENT\r
+#define RTC_COUNT 1\r
+#define HFXTAL_PRESENT\r
+#define HFXTAL_COUNT 1\r
+#define LFXTAL_PRESENT\r
+#define LFXTAL_COUNT 1\r
+#define WDOG_PRESENT\r
+#define WDOG_COUNT 1\r
+#define DBG_PRESENT\r
+#define DBG_COUNT 1\r
+#define TMODE_PRESENT\r
+#define TMODE_COUNT 1\r
+#define SCAN_PRESENT\r
+#define SCAN_COUNT 1\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include CMSIS core functionality */\r
+#include "core_cm3.h"\r
+#include "system_efm32.h"\r
+#include <stdint.h>\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @defgroup EFM32G890F128_Peripheral_TypeDefs EFM32G890F128 Peripheral TypeDefs\r
+ * @{\r
+ *\r
+ *****************************************************************************/\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_MSC\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Memory System Control Register */\r
+ __IO uint32_t READCTRL; /**< Read Control Register */\r
+ __IO uint32_t WRITECTRL; /**< Write Control Register */\r
+ __O uint32_t WRITECMD; /**< Write Command Register */\r
+ __IO uint32_t ADDRB; /**< Page Erase/Write Address Buffer */\r
+\r
+ uint32_t RESERVED0[1]; /**< Reserved for future use **/\r
+ __IO uint32_t WDATA; /**< Write Data Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+\r
+ uint32_t RESERVED1[3]; /**< Reserved for future use **/\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __IO uint32_t LOCK; /**< Configuration Lock Register */\r
+} MSC_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_EMU\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t MEMCTRL; /**< Memory Control Register */\r
+ __IO uint32_t LOCK; /**< Configuration Lock Register */\r
+\r
+ uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
+ __IO uint32_t ATESTCTRL; /**< Analog Test Control Register */\r
+\r
+ uint32_t RESERVED1[2]; /**< Reserved for future use **/\r
+ __IO uint32_t AUXCTRL; /**< Auxiliary Control Register */\r
+} EMU_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_RMU\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __I uint32_t RSTCAUSE; /**< Reset Cause Register */\r
+ __O uint32_t CMD; /**< Command Register */\r
+} RMU_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_CMU\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< CMU Control Register */\r
+ __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
+ __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
+ __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
+ __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
+ __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
+ __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
+ __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
+ __O uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
+ __O uint32_t CMD; /**< Command Register */\r
+ __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
+ __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
+ uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
+ __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
+ __IO uint32_t FREEZE; /**< Freeze Register */\r
+ __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 */\r
+ uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
+ __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 */\r
+ uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
+ __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 */\r
+ uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
+ __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 */\r
+ uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
+ __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
+ __IO uint32_t LCDCTRL; /**< LCD Control Register */\r
+ __IO uint32_t ROUTE; /**< I/O Routing Register */\r
+ __IO uint32_t LOCK; /**< Configuration Lock Register */\r
+} CMU_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_AES\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __O uint32_t CMD; /**< Command Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t DATA; /**< DATA Register */\r
+ __IO uint32_t XORDATA; /**< XORDATA Register */\r
+ uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
+ __IO uint32_t KEYLA; /**< KEY Low Register */\r
+ __IO uint32_t KEYLB; /**< KEY Low Register */\r
+ __IO uint32_t KEYLC; /**< KEY Low Register */\r
+ __IO uint32_t KEYLD; /**< KEY Low Register */\r
+ __IO uint32_t KEYHA; /**< KEY High Register */\r
+ __IO uint32_t KEYHB; /**< KEY High Register */\r
+ __IO uint32_t KEYHC; /**< KEY High Register */\r
+ __IO uint32_t KEYHD; /**< KEY High Register */\r
+} AES_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_EBI\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t ADDRTIMING; /**< Address Timing Register */\r
+ __IO uint32_t RDTIMING; /**< Read Timing Register */\r
+ __IO uint32_t WRTIMING; /**< Write Timing Register */\r
+ __IO uint32_t POLARITY; /**< Polarity Register */\r
+ __IO uint32_t ROUTE; /**< I/O Routing Register */\r
+} EBI_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * P\r
+ *\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Port Control Register */\r
+ __IO uint32_t MODEL; /**< Port Pin Mode Low Register */\r
+ __IO uint32_t MODEH; /**< Port Pin Mode High Register */\r
+ __IO uint32_t DOUT; /**< Port Data Out Register */\r
+ __O uint32_t DOUTSET; /**< Port Data Out Set Register */\r
+ __O uint32_t DOUTCLR; /**< Port Data Out Clear Register */\r
+ __O uint32_t DOUTTGL; /**< Port Data Out Toggle Register */\r
+ __I uint32_t DIN; /**< Port Data In Register */\r
+ __IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register */\r
+} GPIO_P_TypeDef;\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_GPIO\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ GPIO_P_TypeDef P[6]; /**< Port configuration bits */\r
+\r
+ uint32_t RESERVED0[10]; /**< Reserved for future use **/\r
+ __IO uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */\r
+ __IO uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */\r
+ __IO uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */\r
+ __IO uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+\r
+ __IO uint32_t ROUTE; /**< I/O Routing Register */\r
+ __IO uint32_t INSENSE; /**< Input Sense Register */\r
+ __IO uint32_t LOCK; /**< Configuration Lock Register */\r
+} GPIO_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * CH\r
+ *\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Channel Control Register */\r
+} PRS_CH_TypeDef;\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_PRS\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __O uint32_t SWPULSE; /**< Software Pulse Register */\r
+ __IO uint32_t SWLEVEL; /**< Software Level Register */\r
+\r
+ uint32_t RESERVED0[2]; /**< Reserved registers */\r
+\r
+ PRS_CH_TypeDef CH[8]; /**< Channel registers */\r
+} PRS_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * CH\r
+ *\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Channel Control Register */\r
+} DMA_CH_TypeDef;\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_DMA\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __I uint32_t STATUS; /**< DMA Status Registers */\r
+ __IO uint32_t CONFIG; /**< DMA Configuration Register */\r
+ __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
+ __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
+ __I uint32_t WAITSTATUS; /**< Channel Wait on Request Status Register */\r
+ __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
+ __O uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
+ __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
+ __O uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
+ __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
+ __O uint32_t CHENS; /**< Channel Enable Set Register */\r
+ __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
+ __O uint32_t CHALTS; /**< Channel Alternate Set Register */\r
+ __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
+ __O uint32_t CHPRIS; /**< Channel Priority Set Register */\r
+ __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
+ uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
+ __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
+\r
+ uint32_t RESERVED1[1004]; /**< Reserved for future use **/\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable register */\r
+\r
+ uint32_t RESERVED2[60]; /**< Reserved registers */\r
+\r
+ DMA_CH_TypeDef CH[8]; /**< Channel registers */\r
+} DMA_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * CC\r
+ *\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< CC Channel Control Register */\r
+ __IO uint32_t CCV; /**< CC Channel Value Register */\r
+ __I uint32_t CCVP; /**< CC Channel Value Peek Register */\r
+ __IO uint32_t CCVB; /**< CC Channel Buffer Register */\r
+} TIMER_CC_TypeDef;\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_TIMER\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __O uint32_t CMD; /**< Command Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t TOP; /**< Counter Top Value Register */\r
+ __IO uint32_t TOPB; /**< Counter Top Value Buffer Register */\r
+ __IO uint32_t CNT; /**< Counter Value Register */\r
+ __IO uint32_t ROUTE; /**< I/O Routing Register */\r
+\r
+ uint32_t RESERVED0[1]; /**< Reserved registers */\r
+\r
+ TIMER_CC_TypeDef CC[3]; /**< Compare/Capture Channel */\r
+\r
+ uint32_t RESERVED1[4]; /**< Reserved for future use **/\r
+ __IO uint32_t DTCTRL; /**< DTI Control Register */\r
+ __IO uint32_t DTTIME; /**< DTI Time Control Register */\r
+ __IO uint32_t DTFC; /**< DTI Fault Configuration Register */\r
+ __IO uint32_t DTOGEN; /**< DTI Output Generation Enable Register */\r
+ __IO uint32_t DTFAULT; /**< DTI Fault Register */\r
+ __O uint32_t DTFAULTC; /**< DTI Fault Clear Register */\r
+ __IO uint32_t DTLOCK; /**< DTI Configuration Lock Register */\r
+} TIMER_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_USART\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t FRAME; /**< USART Frame Format Register */\r
+ __IO uint32_t TRIGCTRL; /**< USART Trigger Control register */\r
+ __O uint32_t CMD; /**< Command Register */\r
+ __I uint32_t STATUS; /**< USART Status Register */\r
+ __IO uint32_t CLKDIV; /**< Clock Control Register */\r
+ __I uint32_t RXDATAX; /**< RX Buffer Data Extended Register */\r
+ __I uint32_t RXDATA; /**< RX Buffer Data Register */\r
+ __I uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */\r
+ __I uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */\r
+ __I uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */\r
+ __I uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */\r
+ __O uint32_t TXDATAX; /**< TX Buffer Data Extended Register */\r
+ __O uint32_t TXDATA; /**< TX Buffer Data Register */\r
+ __O uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */\r
+ __O uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __IO uint32_t IRCTRL; /**< IrDA Control Register */\r
+ __IO uint32_t ROUTE; /**< I/O Routing Register */\r
+} USART_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_LEUART\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __O uint32_t CMD; /**< Command Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __IO uint32_t CLKDIV; /**< Clock Control Register */\r
+ __IO uint32_t STARTFRAME; /**< Start Frame Register */\r
+ __IO uint32_t SIGFRAME; /**< Signal Frame Register */\r
+ __I uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */\r
+ __I uint32_t RXDATA; /**< Receive Buffer Data Register */\r
+ __I uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */\r
+ __O uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */\r
+ __O uint32_t TXDATA; /**< Transmit Buffer Data Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __IO uint32_t PULSECTRL; /**< Pulse Control Register */\r
+\r
+ __IO uint32_t FREEZE; /**< Freeze Register */\r
+ __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
+\r
+ uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
+ __IO uint32_t ROUTE; /**< I/O Routing Register */\r
+} LEUART_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_LETIMER\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __O uint32_t CMD; /**< Command Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __I uint32_t CNT; /**< Counter Value Register */\r
+ __IO uint32_t COMP0; /**< Compare Value Register 0 */\r
+ __IO uint32_t COMP1; /**< Compare Value Register 1 */\r
+ __IO uint32_t REP0; /**< Repeat Counter Register 0 */\r
+ __IO uint32_t REP1; /**< Repeat Counter Register 1 */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+\r
+ __IO uint32_t FREEZE; /**< Freeze Register */\r
+ __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
+\r
+ uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
+ __IO uint32_t ROUTE; /**< I/O Routing Register */\r
+} LETIMER_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_PCNT\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __O uint32_t CMD; /**< Command Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __I uint32_t CNT; /**< Counter Value Register */\r
+ __I uint32_t TOP; /**< Top Value Register */\r
+ __IO uint32_t TOPB; /**< Top Value Buffer Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __IO uint32_t ROUTE; /**< I/O Routing Register */\r
+\r
+ __IO uint32_t FREEZE; /**< Freeze Register */\r
+ __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
+} PCNT_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_I2C\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __O uint32_t CMD; /**< Command Register */\r
+ __I uint32_t STATE; /**< State Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __IO uint32_t CLKDIV; /**< Clock Division Register */\r
+ __IO uint32_t SADDR; /**< Slave Address Register */\r
+ __IO uint32_t SADDRMASK; /**< Slave Address Mask Register */\r
+ __I uint32_t RXDATA; /**< Receive Buffer Data Register */\r
+ __I uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */\r
+ __O uint32_t TXDATA; /**< Transmit Buffer Data Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __IO uint32_t ROUTE; /**< I/O Routing Register */\r
+} I2C_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_ADC\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __O uint32_t CMD; /**< Command Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __IO uint32_t SINGLECTRL; /**< Single Sample Control Register */\r
+ __IO uint32_t SCANCTRL; /**< Scan Control Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __I uint32_t SINGLEDATA; /**< Single Conversion Result Data */\r
+ __I uint32_t SCANDATA; /**< Scan Conversion Result Data */\r
+ __I uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */\r
+ __I uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */\r
+ __IO uint32_t CAL; /**< Calibration Register */\r
+ __IO uint32_t ROUTE; /**< I/O Routing Register */\r
+ __IO uint32_t BIASPROG; /**< Bias Programming Register */\r
+} ADC_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_DAC\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __IO uint32_t CH0CTRL; /**< Channel 0 Control Register */\r
+ __IO uint32_t CH1CTRL; /**< Channel 1 Control Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t CH0DATA; /**< Channel 0 Data Register */\r
+ __IO uint32_t CH1DATA; /**< Channel 1 Data Register */\r
+ __O uint32_t COMBDATA; /**< Combined Data Register */\r
+ __IO uint32_t CAL; /**< Calibration Register */\r
+ __IO uint32_t BIASPROG; /**< Bias Programming Register */\r
+} DAC_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_ACMP\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t INPUTSEL; /**< Input Selection Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t ROUTE; /**< I/O Routing Register */\r
+} ACMP_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_VCMP\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t INPUTSEL; /**< Input Selection Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+} VCMP_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_LCD\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __IO uint32_t DISPCTRL; /**< Display Control Register */\r
+ __IO uint32_t SEGEN; /**< Segment Enable Register */\r
+ __IO uint32_t BACTRL; /**< Blink and Animation Control Register */\r
+ __I uint32_t STATUS; /**< Status Register */\r
+ __IO uint32_t AREGA; /**< Animation Register A */\r
+ __IO uint32_t AREGB; /**< Animation Register B */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+\r
+ uint32_t RESERVED0[5]; /**< Reserved for future use **/\r
+ __IO uint32_t SEGD0L; /**< Segment Data Low Register 0 */\r
+ __IO uint32_t SEGD1L; /**< Segment Data Low Register 1 */\r
+ __IO uint32_t SEGD2L; /**< Segment Data Low Register 2 */\r
+ __IO uint32_t SEGD3L; /**< Segment Data Low Register 3 */\r
+ __IO uint32_t SEGD0H; /**< Segment Data High Register 0 */\r
+ __IO uint32_t SEGD1H; /**< Segment Data High Register 1 */\r
+ __IO uint32_t SEGD2H; /**< Segment Data High Register 2 */\r
+ __IO uint32_t SEGD3H; /**< Segment Data High Register 3 */\r
+\r
+ __IO uint32_t FREEZE; /**< Freeze Register */\r
+ __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
+} LCD_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_RTC\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __I uint32_t CNT; /**< Counter Value Register */\r
+ __IO uint32_t COMP0; /**< Compare Value Register 0 */\r
+ __IO uint32_t COMP1; /**< Compare Value Register 1 */\r
+ __I uint32_t IF; /**< Interrupt Flag Register */\r
+ __O uint32_t IFS; /**< Interrupt Flag Set Register */\r
+ __O uint32_t IFC; /**< Interrupt Flag Clear Register */\r
+ __IO uint32_t IEN; /**< Interrupt Enable Register */\r
+\r
+ __IO uint32_t FREEZE; /**< Freeze Register */\r
+ __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
+} RTC_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_WDOG\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /**< Control Register */\r
+ __O uint32_t CMD; /**< Command Register */\r
+\r
+ __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
+} WDOG_TypeDef; /** @} */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_DEVINFO\r
+ * @{\r
+ *****************************************************************************/\r
+typedef struct\r
+{\r
+ __I uint32_t UNIQUEL; /**< Low 32 bits of device unique number */\r
+ __I uint32_t UNIQUEH; /**< High 32 bits of device unique number */\r
+ __I uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */\r
+ __I uint32_t PART; /**< Part description */\r
+} DEVINFO_TypeDef; /** @} */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_CALIBRATE\r
+ * @{\r
+ *****************************************************************************/\r
+#define CALIBRATE_MAX_REGISTERS 50 /**< Max number of address/value pairs for calibration */\r
+\r
+typedef struct\r
+{\r
+ __I uint32_t ADDRESS; /**< Address of calibration register */\r
+ __I uint32_t VALUE; /**< Default value for calibration register */\r
+} CALIBRATE_TypeDef; /** @} */\r
+\r
+/** Special calibration registers */\r
+#define HFRCO_CALIBH (*(volatile uint32_t *) 0x0FE081DCUL) /**< Calibration value for HFRCO 28 Mhz */\r
+#define HFRCO_CALIBL (*(volatile uint32_t *) 0x0FE081E0UL) /**< Calibration value for HFRCO 1/7/11/21 Mhz */\r
+#define ADC_CALIB (*(volatile uint32_t *) 0x0FE081E4UL) /**< ADC temperature for calibration and result */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @defgroup EFM32G890F128_Peripheral_Base EFM32G890F128 Peripheral Base Addresses\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define MSC_BASE (0x400C0000) /**< MSC base address */\r
+#define EMU_BASE (0x400C6000) /**< EMU base address */\r
+#define RMU_BASE (0x400CA000) /**< RMU base address */\r
+#define CMU_BASE (0x400C8000) /**< CMU base address */\r
+#define AES_BASE (0x400E0000) /**< AES base address */\r
+#define EBI_BASE (0x40008000) /**< EBI base address */\r
+#define GPIO_BASE (0x40006000) /**< GPIO base address */\r
+#define PRS_BASE (0x400CC000) /**< PRS base address */\r
+#define DMA_BASE (0x400C2000) /**< DMA base address */\r
+#define TIMER0_BASE (0x40010000) /**< TIMER0 base address */\r
+#define TIMER1_BASE (0x40010400) /**< TIMER1 base address */\r
+#define TIMER2_BASE (0x40010800) /**< TIMER2 base address */\r
+#define USART0_BASE (0x4000C000) /**< USART0 base address */\r
+#define USART1_BASE (0x4000C400) /**< USART1 base address */\r
+#define USART2_BASE (0x4000C800) /**< USART2 base address */\r
+#define UART0_BASE (0x4000E000) /**< UART0 base address */\r
+#define LEUART0_BASE (0x40084000) /**< LEUART0 base address */\r
+#define LEUART1_BASE (0x40084400) /**< LEUART1 base address */\r
+#define LETIMER0_BASE (0x40082000) /**< LETIMER0 base address */\r
+#define PCNT0_BASE (0x40086000) /**< PCNT0 base address */\r
+#define PCNT1_BASE (0x40086400) /**< PCNT1 base address */\r
+#define PCNT2_BASE (0x40086800) /**< PCNT2 base address */\r
+#define I2C0_BASE (0x4000A000) /**< I2C0 base address */\r
+#define ADC0_BASE (0x40002000) /**< ADC0 base address */\r
+#define DAC0_BASE (0x40004000) /**< DAC0 base address */\r
+#define ACMP0_BASE (0x40001000) /**< ACMP0 base address */\r
+#define ACMP1_BASE (0x40001400) /**< ACMP1 base address */\r
+#define VCMP_BASE (0x40000000) /**< VCMP base address */\r
+#define LCD_BASE (0x4008A000) /**< LCD base address */\r
+#define RTC_BASE (0x40080000) /**< RTC base address */\r
+#define WDOG_BASE (0x40088000) /**< WDOG base address */\r
+#define DEVINFO_BASE (0x0FE081F0UL) /**< DEVINFO base address */\r
+#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @defgroup EFM32G890F128_Peripheral_Declaration EFM32G890F128 Peripheral Declaration\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
+#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
+#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
+#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
+#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
+#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
+#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
+#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
+#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
+#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
+#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
+#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
+#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
+#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
+#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
+#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
+#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
+#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
+#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
+#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
+#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
+#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
+#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
+#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
+#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
+#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
+#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
+#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
+#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
+#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @defgroup EFM32G890F128_BitFields EFM32G890F128 Bit Fields\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @addtogroup EFM32G890F128_PRS\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
+#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
+#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
+#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
+#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
+#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
+#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
+#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
+#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
+#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
+#define PRS_USART1_IRTX ((17 << 16) + 0) /**< PRS USART 1 IRDA out */\r
+#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
+#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
+#define PRS_USART2_IRTX ((18 << 16) + 0) /**< PRS USART 2 IRDA out */\r
+#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
+#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
+#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
+#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
+#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
+#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
+#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
+#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
+#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
+#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
+#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
+#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
+#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
+#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
+#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
+#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
+#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
+#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
+#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
+#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
+#define PRS_UART0_IRTX ((41 << 16) + 0) /**< PRS USART 0 IRDA out */\r
+#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */\r
+#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
+#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
+#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
+#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
+#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
+#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
+#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
+#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
+#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
+#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
+#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
+#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
+#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
+#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
+#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
+#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
+#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @defgroup EFM32G890F128_DMA_Channel_Select EFM32G890F128 DMA Channel Select\r
+ * @{\r
+ *****************************************************************************/\r
+#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */\r
+#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */\r
+#define DMAREQ_DAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for DAC0_CH0 */\r
+#define DMAREQ_DAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for DAC0_CH1 */\r
+#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */\r
+#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */\r
+#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */\r
+#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */\r
+#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */\r
+#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */\r
+#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */\r
+#define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */\r
+#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */\r
+#define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */\r
+#define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */\r
+#define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */\r
+#define DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */\r
+#define DMAREQ_LEUART1_TXBL ((17 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */\r
+#define DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */\r
+#define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */\r
+#define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */\r
+#define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */\r
+#define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */\r
+#define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */\r
+#define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */\r
+#define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */\r
+#define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */\r
+#define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */\r
+#define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */\r
+#define DMAREQ_TIMER2_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */\r
+#define DMAREQ_TIMER2_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */\r
+#define DMAREQ_TIMER2_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */\r
+#define DMAREQ_TIMER2_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */\r
+#define DMAREQ_UART0_RXDATAV ((44 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */\r
+#define DMAREQ_UART0_TXBL ((44 << 16) + 1) /**< DMA channel select for UART0_TXBL */\r
+#define DMAREQ_UART0_TXEMPTY ((44 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */\r
+#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */\r
+#define DMAREQ_AES_DATAWR ((49 << 16) + 0) /**< DMA channel select for AES_DATAWR */\r
+#define DMAREQ_AES_XORDATAWR ((49 << 16) + 1) /**< DMA channel select for AES_XORDATAWR */\r
+#define DMAREQ_AES_DATARD ((49 << 16) + 2) /**< DMA channel select for AES_DATARD */\r
+#define DMAREQ_AES_KEYWR ((49 << 16) + 3) /**< DMA channel select for AES_KEYWR */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_TIMER\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for TIMER CTRL */\r
+#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */\r
+#define _TIMER_CTRL_MASK 0x0F030FFBUL /**< Mask for TIMER_CTRL */\r
+#define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */\r
+#define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */\r
+#define TIMER_CTRL_MODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_MODE_UP (0x00000000UL << 0) /**< Shifted mode UP for TIMER_CTRL */\r
+#define TIMER_CTRL_MODE_DOWN (0x00000001UL << 0) /**< Shifted mode DOWN for TIMER_CTRL */\r
+#define TIMER_CTRL_MODE_UPDOWN (0x00000002UL << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */\r
+#define TIMER_CTRL_MODE_QDEC (0x00000003UL << 0) /**< Shifted mode QDEC for TIMER_CTRL */\r
+#define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */\r
+#define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */\r
+#define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */\r
+#define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */\r
+#define TIMER_CTRL_SYNC (1 << 3) /**< Timer Start/Stop/Reload Synchronization */\r
+#define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */\r
+#define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */\r
+#define TIMER_CTRL_SYNC_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_OSMEN (1 << 4) /**< One-shot Mode Enable */\r
+#define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */\r
+#define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */\r
+#define TIMER_CTRL_OSMEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_QEM (1 << 5) /**< Quadrature Decoder Mode Selection */\r
+#define _TIMER_CTRL_QEM_SHIFT 5 /**< Shift value for TIMER_QEM */\r
+#define _TIMER_CTRL_QEM_MASK 0x20UL /**< Bit mask for TIMER_QEM */\r
+#define TIMER_CTRL_QEM_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_QEM_X2 (0x00000000UL << 5) /**< Shifted mode X2 for TIMER_CTRL */\r
+#define TIMER_CTRL_QEM_X4 (0x00000001UL << 5) /**< Shifted mode X4 for TIMER_CTRL */\r
+#define _TIMER_CTRL_QEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_QEM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */\r
+#define _TIMER_CTRL_QEM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */\r
+#define TIMER_CTRL_DEBUGRUN (1 << 6) /**< Debug Mode Run Enable */\r
+#define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */\r
+#define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */\r
+#define TIMER_CTRL_DEBUGRUN_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_DMACLRACT (1 << 7) /**< DMA Request Clear on Active */\r
+#define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */\r
+#define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */\r
+#define TIMER_CTRL_DMACLRACT_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */\r
+#define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */\r
+#define TIMER_CTRL_RISEA_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_RISEA_NONE (0x00000000UL << 8) /**< Shifted mode NONE for TIMER_CTRL */\r
+#define TIMER_CTRL_RISEA_START (0x00000001UL << 8) /**< Shifted mode START for TIMER_CTRL */\r
+#define TIMER_CTRL_RISEA_STOP (0x00000002UL << 8) /**< Shifted mode STOP for TIMER_CTRL */\r
+#define TIMER_CTRL_RISEA_RELOADSTART (0x00000003UL << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */\r
+#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */\r
+#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */\r
+#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */\r
+#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */\r
+#define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */\r
+#define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */\r
+#define TIMER_CTRL_FALLA_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_FALLA_NONE (0x00000000UL << 10) /**< Shifted mode NONE for TIMER_CTRL */\r
+#define TIMER_CTRL_FALLA_START (0x00000001UL << 10) /**< Shifted mode START for TIMER_CTRL */\r
+#define TIMER_CTRL_FALLA_STOP (0x00000002UL << 10) /**< Shifted mode STOP for TIMER_CTRL */\r
+#define TIMER_CTRL_FALLA_RELOADSTART (0x00000003UL << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */\r
+#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */\r
+#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */\r
+#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */\r
+#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */\r
+#define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */\r
+#define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */\r
+#define TIMER_CTRL_CLKSEL_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (0x00000000UL << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */\r
+#define TIMER_CTRL_CLKSEL_CC1 (0x00000001UL << 16) /**< Shifted mode CC1 for TIMER_CTRL */\r
+#define TIMER_CTRL_CLKSEL_TIMEROUF (0x00000002UL << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */\r
+#define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */\r
+#define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */\r
+#define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */\r
+#define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */\r
+#define TIMER_CTRL_PRESC_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV1 (0x00000000UL << 24) /**< Shifted mode DIV1 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV2 (0x00000001UL << 24) /**< Shifted mode DIV2 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV4 (0x00000002UL << 24) /**< Shifted mode DIV4 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV8 (0x00000003UL << 24) /**< Shifted mode DIV8 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV16 (0x00000004UL << 24) /**< Shifted mode DIV16 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV32 (0x00000005UL << 24) /**< Shifted mode DIV32 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV64 (0x00000006UL << 24) /**< Shifted mode DIV64 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV128 (0x00000007UL << 24) /**< Shifted mode DIV128 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV256 (0x00000008UL << 24) /**< Shifted mode DIV256 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV512 (0x00000009UL << 24) /**< Shifted mode DIV512 for TIMER_CTRL */\r
+#define TIMER_CTRL_PRESC_DIV1024 (0x0000000AUL << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */\r
+#define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */\r
+\r
+/** Bit fields for TIMER CMD */\r
+#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */\r
+#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */\r
+#define TIMER_CMD_START (1 << 0) /**< Start Timer */\r
+#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */\r
+#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */\r
+#define TIMER_CMD_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CMD */\r
+#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */\r
+#define TIMER_CMD_STOP (1 << 1) /**< Stop Timer */\r
+#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */\r
+#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */\r
+#define TIMER_CMD_STOP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_CMD */\r
+#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */\r
+\r
+/** Bit fields for TIMER STATUS */\r
+#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */\r
+#define _TIMER_STATUS_MASK 0x07070707UL /**< Mask for TIMER_STATUS */\r
+#define TIMER_STATUS_RUNNING (1 << 0) /**< Running */\r
+#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */\r
+#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */\r
+#define TIMER_STATUS_RUNNING_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_DIR (1 << 1) /**< Direction */\r
+#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */\r
+#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */\r
+#define TIMER_STATUS_DIR_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_DIR_UP (0x00000000UL << 1) /**< Shifted mode UP for TIMER_STATUS */\r
+#define TIMER_STATUS_DIR_DOWN (0x00000001UL << 1) /**< Shifted mode DOWN for TIMER_STATUS */\r
+#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */\r
+#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */\r
+#define TIMER_STATUS_TOPBV (1 << 2) /**< TOPB Valid */\r
+#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */\r
+#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */\r
+#define TIMER_STATUS_TOPBV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCVBV0 (1 << 8) /**< CC0 CCVB Valid */\r
+#define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */\r
+#define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */\r
+#define TIMER_STATUS_CCVBV0_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCVBV1 (1 << 9) /**< CC1 CCVB Valid */\r
+#define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */\r
+#define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */\r
+#define TIMER_STATUS_CCVBV1_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCVBV2 (1 << 10) /**< CC2 CCVB Valid */\r
+#define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */\r
+#define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */\r
+#define TIMER_STATUS_CCVBV2_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_ICV0 (1 << 16) /**< CC0 Input Capture Valid */\r
+#define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */\r
+#define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */\r
+#define TIMER_STATUS_ICV0_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_ICV1 (1 << 17) /**< CC1 Input Capture Valid */\r
+#define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */\r
+#define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */\r
+#define TIMER_STATUS_ICV1_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_ICV2 (1 << 18) /**< CC2 Input Capture Valid */\r
+#define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */\r
+#define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */\r
+#define TIMER_STATUS_ICV2_DEFAULT (0x00000000UL << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL0 (1 << 24) /**< CC0 Polarity */\r
+#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */\r
+#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */\r
+#define TIMER_STATUS_CCPOL0_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL0_LOWRISE (0x00000000UL << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL0_HIGHFALL (0x00000001UL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL1 (1 << 25) /**< CC1 Polarity */\r
+#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */\r
+#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */\r
+#define TIMER_STATUS_CCPOL1_DEFAULT (0x00000000UL << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL1_LOWRISE (0x00000000UL << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL1_HIGHFALL (0x00000001UL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL2 (1 << 26) /**< CC2 Polarity */\r
+#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */\r
+#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */\r
+#define TIMER_STATUS_CCPOL2_DEFAULT (0x00000000UL << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL2_LOWRISE (0x00000000UL << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */\r
+#define TIMER_STATUS_CCPOL2_HIGHFALL (0x00000001UL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */\r
+#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */\r
+\r
+/** Bit fields for TIMER IEN */\r
+#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */\r
+#define _TIMER_IEN_MASK 0x00000773UL /**< Mask for TIMER_IEN */\r
+#define TIMER_IEN_OF (1 << 0) /**< Overflow Interrupt Enable */\r
+#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */\r
+#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */\r
+#define TIMER_IEN_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_UF (1 << 1) /**< Underflow Interrupt Enable */\r
+#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */\r
+#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */\r
+#define TIMER_IEN_UF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_CC0 (1 << 4) /**< CC Channel 0 Interrupt Enable */\r
+#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */\r
+#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */\r
+#define TIMER_IEN_CC0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_CC1 (1 << 5) /**< CC Channel 1 Interrupt Enable */\r
+#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */\r
+#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */\r
+#define TIMER_IEN_CC1_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_CC2 (1 << 6) /**< CC Channel 2 Interrupt Enable */\r
+#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */\r
+#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */\r
+#define TIMER_IEN_CC2_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_ICBOF0 (1 << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Enable */\r
+#define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */\r
+#define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */\r
+#define TIMER_IEN_ICBOF0_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_ICBOF1 (1 << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Enable */\r
+#define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */\r
+#define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */\r
+#define TIMER_IEN_ICBOF1_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+#define TIMER_IEN_ICBOF2 (1 << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Enable */\r
+#define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */\r
+#define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */\r
+#define TIMER_IEN_ICBOF2_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_IEN */\r
+#define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */\r
+\r
+/** Bit fields for TIMER IF */\r
+#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */\r
+#define _TIMER_IF_MASK 0x00000773UL /**< Mask for TIMER_IF */\r
+#define TIMER_IF_OF (1 << 0) /**< Overflow Interrupt Flag */\r
+#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */\r
+#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */\r
+#define TIMER_IF_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_UF (1 << 1) /**< Underflow Interrupt Flag */\r
+#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */\r
+#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */\r
+#define TIMER_IF_UF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_CC0 (1 << 4) /**< CC Channel 0 Interrupt Flag */\r
+#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */\r
+#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */\r
+#define TIMER_IF_CC0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_CC1 (1 << 5) /**< CC Channel 1 Interrupt Flag */\r
+#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */\r
+#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */\r
+#define TIMER_IF_CC1_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_CC2 (1 << 6) /**< CC Channel 2 Interrupt Flag */\r
+#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */\r
+#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */\r
+#define TIMER_IF_CC2_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_ICBOF0 (1 << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */\r
+#define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */\r
+#define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */\r
+#define TIMER_IF_ICBOF0_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_ICBOF1 (1 << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */\r
+#define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */\r
+#define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */\r
+#define TIMER_IF_ICBOF1_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+#define TIMER_IF_ICBOF2 (1 << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */\r
+#define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */\r
+#define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */\r
+#define TIMER_IF_ICBOF2_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_IF */\r
+#define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */\r
+\r
+/** Bit fields for TIMER IFS */\r
+#define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */\r
+#define _TIMER_IFS_MASK 0x00000773UL /**< Mask for TIMER_IFS */\r
+#define TIMER_IFS_OF (1 << 0) /**< Overflow Interrupt Flag Set */\r
+#define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */\r
+#define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */\r
+#define TIMER_IFS_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_UF (1 << 1) /**< Underflow Interrupt Flag Set */\r
+#define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */\r
+#define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */\r
+#define TIMER_IFS_UF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_CC0 (1 << 4) /**< CC Channel 0 Interrupt Flag Set */\r
+#define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */\r
+#define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */\r
+#define TIMER_IFS_CC0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_CC1 (1 << 5) /**< CC Channel 1 Interrupt Flag Set */\r
+#define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */\r
+#define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */\r
+#define TIMER_IFS_CC1_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_CC2 (1 << 6) /**< CC Channel 2 Interrupt Flag Set */\r
+#define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */\r
+#define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */\r
+#define TIMER_IFS_CC2_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_ICBOF0 (1 << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set */\r
+#define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */\r
+#define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */\r
+#define TIMER_IFS_ICBOF0_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_ICBOF1 (1 << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set */\r
+#define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */\r
+#define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */\r
+#define TIMER_IFS_ICBOF1_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+#define TIMER_IFS_ICBOF2 (1 << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set */\r
+#define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */\r
+#define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */\r
+#define TIMER_IFS_ICBOF2_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_IFS */\r
+#define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */\r
+\r
+/** Bit fields for TIMER IFC */\r
+#define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */\r
+#define _TIMER_IFC_MASK 0x00000773UL /**< Mask for TIMER_IFC */\r
+#define TIMER_IFC_OF (1 << 0) /**< Overflow Interrupt Flag Clear */\r
+#define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */\r
+#define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */\r
+#define TIMER_IFC_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_UF (1 << 1) /**< Underflow Interrupt Flag Clear */\r
+#define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */\r
+#define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */\r
+#define TIMER_IFC_UF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_CC0 (1 << 4) /**< CC Channel 0 Interrupt Flag Clear */\r
+#define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */\r
+#define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */\r
+#define TIMER_IFC_CC0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_CC1 (1 << 5) /**< CC Channel 1 Interrupt Flag Clear */\r
+#define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */\r
+#define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */\r
+#define TIMER_IFC_CC1_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_CC2 (1 << 6) /**< CC Channel 2 Interrupt Flag Clear */\r
+#define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */\r
+#define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */\r
+#define TIMER_IFC_CC2_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_ICBOF0 (1 << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Clear */\r
+#define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */\r
+#define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */\r
+#define TIMER_IFC_ICBOF0_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_ICBOF1 (1 << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear */\r
+#define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */\r
+#define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */\r
+#define TIMER_IFC_ICBOF1_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+#define TIMER_IFC_ICBOF2 (1 << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear */\r
+#define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */\r
+#define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */\r
+#define TIMER_IFC_ICBOF2_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_IFC */\r
+#define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */\r
+\r
+/** Bit fields for TIMER TOP */\r
+#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */\r
+#define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */\r
+#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */\r
+#define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */\r
+#define TIMER_TOP_TOP_DEFAULT (0x0000FFFFUL << 0) /**< Shifted mode DEFAULT for TIMER_TOP */\r
+#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */\r
+\r
+/** Bit fields for TIMER TOPB */\r
+#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */\r
+#define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */\r
+#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */\r
+#define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */\r
+#define TIMER_TOPB_TOPB_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */\r
+#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */\r
+\r
+/** Bit fields for TIMER CNT */\r
+#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */\r
+#define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */\r
+#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */\r
+#define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */\r
+#define TIMER_CNT_CNT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CNT */\r
+#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */\r
+\r
+/** Bit fields for TIMER ROUTE */\r
+#define _TIMER_ROUTE_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTE */\r
+#define _TIMER_ROUTE_MASK 0x00030707UL /**< Mask for TIMER_ROUTE */\r
+#define _TIMER_ROUTE_CCPEN_SHIFT 0 /**< Shift value for TIMER_CCPEN */\r
+#define _TIMER_ROUTE_CCPEN_MASK 0x7UL /**< Bit mask for TIMER_CCPEN */\r
+#define TIMER_ROUTE_CCPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_ROUTE */\r
+#define _TIMER_ROUTE_CCPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */\r
+#define _TIMER_ROUTE_CDTIPEN_SHIFT 8 /**< Shift value for TIMER_CDTIPEN */\r
+#define _TIMER_ROUTE_CDTIPEN_MASK 0x700UL /**< Bit mask for TIMER_CDTIPEN */\r
+#define TIMER_ROUTE_CDTIPEN_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_ROUTE */\r
+#define _TIMER_ROUTE_CDTIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */\r
+#define _TIMER_ROUTE_LOCATION_SHIFT 16 /**< Shift value for TIMER_LOCATION */\r
+#define _TIMER_ROUTE_LOCATION_MASK 0x30000UL /**< Bit mask for TIMER_LOCATION */\r
+#define TIMER_ROUTE_LOCATION_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_ROUTE */\r
+#define TIMER_ROUTE_LOCATION_LOC0 (0x00000000UL << 16) /**< Shifted mode LOC0 for TIMER_ROUTE */\r
+#define TIMER_ROUTE_LOCATION_LOC1 (0x00000001UL << 16) /**< Shifted mode LOC1 for TIMER_ROUTE */\r
+#define TIMER_ROUTE_LOCATION_LOC2 (0x00000002UL << 16) /**< Shifted mode LOC2 for TIMER_ROUTE */\r
+#define TIMER_ROUTE_LOCATION_LOC3 (0x00000003UL << 16) /**< Shifted mode LOC3 for TIMER_ROUTE */\r
+#define _TIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */\r
+#define _TIMER_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTE */\r
+#define _TIMER_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTE */\r
+#define _TIMER_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTE */\r
+#define _TIMER_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTE */\r
+\r
+/** Bit fields for TIMER CC_CTRL */\r
+#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_MASK 0x0F373F17UL /**< Mask for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */\r
+#define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */\r
+#define TIMER_CC_CTRL_MODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_MODE_OFF (0x00000000UL << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_MODE_INPUTCAPTURE (0x00000001UL << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (0x00000002UL << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_MODE_PWM (0x00000003UL << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_OUTINV (1 << 2) /**< Output Invert */\r
+#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */\r
+#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */\r
+#define TIMER_CC_CTRL_OUTINV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_COIST (1 << 4) /**< Compare Output Initial State */\r
+#define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */\r
+#define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */\r
+#define TIMER_CC_CTRL_COIST_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */\r
+#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */\r
+#define TIMER_CC_CTRL_CMOA_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CMOA_NONE (0x00000000UL << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CMOA_TOGGLE (0x00000001UL << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CMOA_CLEAR (0x00000002UL << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CMOA_SET (0x00000003UL << 8) /**< Shifted mode SET for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */\r
+#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */\r
+#define TIMER_CC_CTRL_COFOA_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_COFOA_NONE (0x00000000UL << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_COFOA_TOGGLE (0x00000001UL << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_COFOA_CLEAR (0x00000002UL << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_COFOA_SET (0x00000003UL << 10) /**< Shifted mode SET for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */\r
+#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */\r
+#define TIMER_CC_CTRL_CUFOA_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CUFOA_NONE (0x00000000UL << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CUFOA_TOGGLE (0x00000001UL << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CUFOA_CLEAR (0x00000002UL << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_CUFOA_SET (0x00000003UL << 12) /**< Shifted mode SET for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */\r
+#define _TIMER_CC_CTRL_PRSSEL_MASK 0x70000UL /**< Bit mask for TIMER_PRSSEL */\r
+#define TIMER_CC_CTRL_PRSSEL_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH0 (0x00000000UL << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH1 (0x00000001UL << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH2 (0x00000002UL << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH3 (0x00000003UL << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH4 (0x00000004UL << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH5 (0x00000005UL << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH6 (0x00000006UL << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_PRSSEL_PRSCH7 (0x00000007UL << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_INSEL (1 << 20) /**< Input Selection */\r
+#define _TIMER_CC_CTRL_INSEL_SHIFT 20 /**< Shift value for TIMER_INSEL */\r
+#define _TIMER_CC_CTRL_INSEL_MASK 0x100000UL /**< Bit mask for TIMER_INSEL */\r
+#define TIMER_CC_CTRL_INSEL_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_INSEL_PIN (0x00000000UL << 20) /**< Shifted mode PIN for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_INSEL_PRS (0x00000001UL << 20) /**< Shifted mode PRS for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_FILT (1 << 21) /**< Digital Filter */\r
+#define _TIMER_CC_CTRL_FILT_SHIFT 21 /**< Shift value for TIMER_FILT */\r
+#define _TIMER_CC_CTRL_FILT_MASK 0x200000UL /**< Bit mask for TIMER_FILT */\r
+#define TIMER_CC_CTRL_FILT_DEFAULT (0x00000000UL << 21) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_FILT_DISABLE (0x00000000UL << 21) /**< Shifted mode DISABLE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_FILT_ENABLE (0x00000001UL << 21) /**< Shifted mode ENABLE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */\r
+#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */\r
+#define TIMER_CC_CTRL_ICEDGE_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEDGE_RISING (0x00000000UL << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEDGE_FALLING (0x00000001UL << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEDGE_BOTH (0x00000002UL << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEDGE_NONE (0x00000003UL << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */\r
+#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */\r
+#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (0x00000000UL << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (0x00000000UL << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (0x00000001UL << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEVCTRL_RISING (0x00000002UL << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */\r
+#define TIMER_CC_CTRL_ICEVCTRL_FALLING (0x00000003UL << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */\r
+#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */\r
+\r
+/** Bit fields for TIMER CC_CCV */\r
+#define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */\r
+#define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */\r
+#define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */\r
+#define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */\r
+#define TIMER_CC_CCV_CCV_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */\r
+#define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */\r
+\r
+/** Bit fields for TIMER CC_CCVP */\r
+#define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */\r
+#define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */\r
+#define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */\r
+#define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */\r
+#define TIMER_CC_CCVP_CCVP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */\r
+#define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */\r
+\r
+/** Bit fields for TIMER CC_CCVB */\r
+#define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */\r
+#define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */\r
+#define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */\r
+#define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */\r
+#define TIMER_CC_CCVB_CCVB_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */\r
+#define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */\r
+\r
+/** Bit fields for TIMER DTCTRL */\r
+#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_MASK 0x0100007FUL /**< Mask for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTEN (1 << 0) /**< DTI Enable */\r
+#define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */\r
+#define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */\r
+#define TIMER_DTCTRL_DTEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTDAS (1 << 1) /**< DTI Automatic Start-up Functionality */\r
+#define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */\r
+#define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */\r
+#define TIMER_DTCTRL_DTDAS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTDAS_NORESTART (0x00000000UL << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTDAS_RESTART (0x00000001UL << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTIPOL (1 << 2) /**< DTI Inactive Polarity */\r
+#define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */\r
+#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */\r
+#define TIMER_DTCTRL_DTIPOL_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTCINV (1 << 3) /**< DTI Complementary Output Invert. */\r
+#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */\r
+#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */\r
+#define TIMER_DTCTRL_DTCINV_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_MASK 0x70UL /**< Bit mask for TIMER_DTPRSSEL */\r
+#define TIMER_DTCTRL_DTPRSSEL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (0x00000000UL << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (0x00000001UL << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (0x00000002UL << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (0x00000003UL << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (0x00000004UL << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (0x00000005UL << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (0x00000006UL << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (0x00000007UL << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */\r
+#define TIMER_DTCTRL_DTPRSEN (1 << 24) /**< DTI PRS Source Enable */\r
+#define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */\r
+#define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */\r
+#define TIMER_DTCTRL_DTPRSEN_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */\r
+#define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */\r
+\r
+/** Bit fields for TIMER DTTIME */\r
+#define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */\r
+#define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */\r
+#define TIMER_DTTIME_DTPRESC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV1 (0x00000000UL << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV2 (0x00000001UL << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV4 (0x00000002UL << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV8 (0x00000003UL << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV16 (0x00000004UL << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV32 (0x00000005UL << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV64 (0x00000006UL << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV128 (0x00000007UL << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV256 (0x00000008UL << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV512 (0x00000009UL << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */\r
+#define TIMER_DTTIME_DTPRESC_DIV1024 (0x0000000AUL << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */\r
+#define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */\r
+#define TIMER_DTTIME_DTRISET_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */\r
+#define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */\r
+#define TIMER_DTTIME_DTFALLT_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */\r
+#define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */\r
+\r
+/** Bit fields for TIMER DTFC */\r
+#define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */\r
+#define _TIMER_DTFC_MASK 0x0F030707UL /**< Mask for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL0_SHIFT 0 /**< Shift value for TIMER_DTPRSFSEL0 */\r
+#define _TIMER_DTFC_DTPRSFSEL0_MASK 0x7UL /**< Bit mask for TIMER_DTPRSFSEL0 */\r
+#define TIMER_DTFC_DTPRSFSEL0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL0_PRSCH0 (0x00000000UL << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL0_PRSCH1 (0x00000001UL << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL0_PRSCH2 (0x00000002UL << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL0_PRSCH3 (0x00000003UL << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL0_PRSCH4 (0x00000004UL << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL0_PRSCH5 (0x00000005UL << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL0_PRSCH6 (0x00000006UL << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL0_PRSCH7 (0x00000007UL << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL0_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL0_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL0_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL0_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL0_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL0_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL0_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL0_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL1_SHIFT 8 /**< Shift value for TIMER_DTPRSFSEL1 */\r
+#define _TIMER_DTFC_DTPRSFSEL1_MASK 0x700UL /**< Bit mask for TIMER_DTPRSFSEL1 */\r
+#define TIMER_DTFC_DTPRSFSEL1_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL1_PRSCH0 (0x00000000UL << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL1_PRSCH1 (0x00000001UL << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL1_PRSCH2 (0x00000002UL << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL1_PRSCH3 (0x00000003UL << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL1_PRSCH4 (0x00000004UL << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL1_PRSCH5 (0x00000005UL << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL1_PRSCH6 (0x00000006UL << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTPRSFSEL1_PRSCH7 (0x00000007UL << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL1_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL1_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL1_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL1_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL1_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL1_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL1_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTPRSFSEL1_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */\r
+#define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */\r
+#define TIMER_DTFC_DTFA_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */\r
+#define TIMER_DTFC_DTFA_NONE (0x00000000UL << 16) /**< Shifted mode NONE for TIMER_DTFC */\r
+#define TIMER_DTFC_DTFA_INACTIVE (0x00000001UL << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */\r
+#define TIMER_DTFC_DTFA_CLEAR (0x00000002UL << 16) /**< Shifted mode CLEAR for TIMER_DTFC */\r
+#define TIMER_DTFC_DTFA_TRISTATE (0x00000003UL << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFSEN_SHIFT 24 /**< Shift value for TIMER_DTFSEN */\r
+#define _TIMER_DTFC_DTFSEN_MASK 0xF000000UL /**< Bit mask for TIMER_DTFSEN */\r
+#define TIMER_DTFC_DTFSEN_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */\r
+#define TIMER_DTFC_DTFSEN_PRS0 (0x00000001UL << 24) /**< Shifted mode PRS0 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTFSEN_PRS1 (0x00000002UL << 24) /**< Shifted mode PRS1 for TIMER_DTFC */\r
+#define TIMER_DTFC_DTFSEN_DEBUG (0x00000004UL << 24) /**< Shifted mode DEBUG for TIMER_DTFC */\r
+#define TIMER_DTFC_DTFSEN_LOCKUP (0x00000008UL << 24) /**< Shifted mode LOCKUP for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFSEN_PRS0 0x00000001UL /**< Mode PRS0 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFSEN_PRS1 0x00000002UL /**< Mode PRS1 for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFSEN_DEBUG 0x00000004UL /**< Mode DEBUG for TIMER_DTFC */\r
+#define _TIMER_DTFC_DTFSEN_LOCKUP 0x00000008UL /**< Mode LOCKUP for TIMER_DTFC */\r
+\r
+/** Bit fields for TIMER DTOGEN */\r
+#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */\r
+#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */\r
+#define _TIMER_DTOGEN_DTOGEN_SHIFT 0 /**< Shift value for TIMER_DTOGEN */\r
+#define _TIMER_DTOGEN_DTOGEN_MASK 0x3FUL /**< Bit mask for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGEN_CC0 (0x00000001UL << 0) /**< Shifted mode CC0 for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGEN_CC1 (0x00000002UL << 0) /**< Shifted mode CC1 for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGEN_CC2 (0x00000004UL << 0) /**< Shifted mode CC2 for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGEN_CDTI0 (0x00000008UL << 0) /**< Shifted mode CDTI0 for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGEN_CDTI1 (0x00000010UL << 0) /**< Shifted mode CDTI1 for TIMER_DTOGEN */\r
+#define TIMER_DTOGEN_DTOGEN_CDTI2 (0x00000020UL << 0) /**< Shifted mode CDTI2 for TIMER_DTOGEN */\r
+#define _TIMER_DTOGEN_DTOGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */\r
+#define _TIMER_DTOGEN_DTOGEN_CC0 0x00000001UL /**< Mode CC0 for TIMER_DTOGEN */\r
+#define _TIMER_DTOGEN_DTOGEN_CC1 0x00000002UL /**< Mode CC1 for TIMER_DTOGEN */\r
+#define _TIMER_DTOGEN_DTOGEN_CC2 0x00000004UL /**< Mode CC2 for TIMER_DTOGEN */\r
+#define _TIMER_DTOGEN_DTOGEN_CDTI0 0x00000008UL /**< Mode CDTI0 for TIMER_DTOGEN */\r
+#define _TIMER_DTOGEN_DTOGEN_CDTI1 0x00000010UL /**< Mode CDTI1 for TIMER_DTOGEN */\r
+#define _TIMER_DTOGEN_DTOGEN_CDTI2 0x00000020UL /**< Mode CDTI2 for TIMER_DTOGEN */\r
+\r
+/** Bit fields for TIMER DTFAULT */\r
+#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */\r
+#define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */\r
+#define _TIMER_DTFAULT_DTFS_SHIFT 0 /**< Shift value for TIMER_DTFS */\r
+#define _TIMER_DTFAULT_DTFS_MASK 0xFUL /**< Bit mask for TIMER_DTFS */\r
+#define TIMER_DTFAULT_DTFS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */\r
+#define TIMER_DTFAULT_DTFS_PRS0 (0x00000001UL << 0) /**< Shifted mode PRS0 for TIMER_DTFAULT */\r
+#define TIMER_DTFAULT_DTFS_PRS1 (0x00000002UL << 0) /**< Shifted mode PRS1 for TIMER_DTFAULT */\r
+#define TIMER_DTFAULT_DTFS_DEBUG (0x00000004UL << 0) /**< Shifted mode DEBUG for TIMER_DTFAULT */\r
+#define TIMER_DTFAULT_DTFS_LOCKUP (0x00000008UL << 0) /**< Shifted mode LOCKUP for TIMER_DTFAULT */\r
+#define _TIMER_DTFAULT_DTFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */\r
+#define _TIMER_DTFAULT_DTFS_PRS0 0x00000001UL /**< Mode PRS0 for TIMER_DTFAULT */\r
+#define _TIMER_DTFAULT_DTFS_PRS1 0x00000002UL /**< Mode PRS1 for TIMER_DTFAULT */\r
+#define _TIMER_DTFAULT_DTFS_DEBUG 0x00000004UL /**< Mode DEBUG for TIMER_DTFAULT */\r
+#define _TIMER_DTFAULT_DTFS_LOCKUP 0x00000008UL /**< Mode LOCKUP for TIMER_DTFAULT */\r
+\r
+/** Bit fields for TIMER DTFAULTC */\r
+#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */\r
+#define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */\r
+#define _TIMER_DTFAULTC_DTFSC_SHIFT 0 /**< Shift value for TIMER_DTFSC */\r
+#define _TIMER_DTFAULTC_DTFSC_MASK 0xFUL /**< Bit mask for TIMER_DTFSC */\r
+#define TIMER_DTFAULTC_DTFSC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */\r
+#define TIMER_DTFAULTC_DTFSC_PRS0 (0x00000001UL << 0) /**< Shifted mode PRS0 for TIMER_DTFAULTC */\r
+#define TIMER_DTFAULTC_DTFSC_PRS1 (0x00000002UL << 0) /**< Shifted mode PRS1 for TIMER_DTFAULTC */\r
+#define TIMER_DTFAULTC_DTFSC_DEBUG (0x00000004UL << 0) /**< Shifted mode DEBUG for TIMER_DTFAULTC */\r
+#define TIMER_DTFAULTC_DTFSC_LOCKUP (0x00000008UL << 0) /**< Shifted mode LOCKUP for TIMER_DTFAULTC */\r
+#define _TIMER_DTFAULTC_DTFSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */\r
+#define _TIMER_DTFAULTC_DTFSC_PRS0 0x00000001UL /**< Mode PRS0 for TIMER_DTFAULTC */\r
+#define _TIMER_DTFAULTC_DTFSC_PRS1 0x00000002UL /**< Mode PRS1 for TIMER_DTFAULTC */\r
+#define _TIMER_DTFAULTC_DTFSC_DEBUG 0x00000004UL /**< Mode DEBUG for TIMER_DTFAULTC */\r
+#define _TIMER_DTFAULTC_DTFSC_LOCKUP 0x00000008UL /**< Mode LOCKUP for TIMER_DTFAULTC */\r
+\r
+/** Bit fields for TIMER DTLOCK */\r
+#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */\r
+#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */\r
+#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */\r
+#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */\r
+#define TIMER_DTLOCK_LOCKKEY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */\r
+#define TIMER_DTLOCK_LOCKKEY_LOCK (0x00000000UL << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */\r
+#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (0x00000000UL << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */\r
+#define TIMER_DTLOCK_LOCKKEY_LOCKED (0x00000001UL << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */\r
+#define TIMER_DTLOCK_LOCKKEY_UNLOCK (0x0000CE80UL << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */\r
+#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */\r
+#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */\r
+#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */\r
+#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */\r
+#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_USART\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for USART CTRL */\r
+#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */\r
+#define _USART_CTRL_MASK 0x1DFFFF7FUL /**< Mask for USART_CTRL */\r
+#define USART_CTRL_SYNC (1 << 0) /**< USART Synchronous Mode */\r
+#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */\r
+#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */\r
+#define USART_CTRL_SYNC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_LOOPBK (1 << 1) /**< Loopback Enable */\r
+#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */\r
+#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */\r
+#define USART_CTRL_LOOPBK_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_CCEN (1 << 2) /**< Collision Check Enable */\r
+#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */\r
+#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */\r
+#define USART_CTRL_CCEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_MPM (1 << 3) /**< Multi-Processor Mode */\r
+#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */\r
+#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */\r
+#define USART_CTRL_MPM_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_MPAB (1 << 4) /**< Multi-Processor Address-Bit */\r
+#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */\r
+#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */\r
+#define USART_CTRL_MPAB_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */\r
+#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */\r
+#define USART_CTRL_OVS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_OVS_X16 (0x00000000UL << 5) /**< Shifted mode X16 for USART_CTRL */\r
+#define USART_CTRL_OVS_X8 (0x00000001UL << 5) /**< Shifted mode X8 for USART_CTRL */\r
+#define USART_CTRL_OVS_X6 (0x00000002UL << 5) /**< Shifted mode X6 for USART_CTRL */\r
+#define USART_CTRL_OVS_X4 (0x00000003UL << 5) /**< Shifted mode X4 for USART_CTRL */\r
+#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */\r
+#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */\r
+#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */\r
+#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */\r
+#define USART_CTRL_CLKPOL (1 << 8) /**< Clock Polarity */\r
+#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */\r
+#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */\r
+#define USART_CTRL_CLKPOL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_CLKPOL_IDLELOW (0x00000000UL << 8) /**< Shifted mode IDLELOW for USART_CTRL */\r
+#define USART_CTRL_CLKPOL_IDLEHIGH (0x00000001UL << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */\r
+#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */\r
+#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */\r
+#define USART_CTRL_CLKPHA (1 << 9) /**< Clock Edge For Setup/Sample */\r
+#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */\r
+#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */\r
+#define USART_CTRL_CLKPHA_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_CLKPHA_SAMPLELEADING (0x00000000UL << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */\r
+#define USART_CTRL_CLKPHA_SAMPLETRAILING (0x00000001UL << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */\r
+#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */\r
+#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */\r
+#define USART_CTRL_MSBF (1 << 10) /**< Most Significant Bit First */\r
+#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */\r
+#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */\r
+#define USART_CTRL_MSBF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_CSMA (1 << 11) /**< Action On Slave-Select In Master Mode */\r
+#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */\r
+#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */\r
+#define USART_CTRL_CSMA_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_CSMA_NOACTION (0x00000000UL << 11) /**< Shifted mode NOACTION for USART_CTRL */\r
+#define USART_CTRL_CSMA_GOTOSLAVEMODE (0x00000001UL << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */\r
+#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */\r
+#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */\r
+#define USART_CTRL_TXBIL (1 << 12) /**< TX Buffer Interrupt Level */\r
+#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */\r
+#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */\r
+#define USART_CTRL_TXBIL_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_TXBIL_EMPTY (0x00000000UL << 12) /**< Shifted mode EMPTY for USART_CTRL */\r
+#define USART_CTRL_TXBIL_HALFFULL (0x00000001UL << 12) /**< Shifted mode HALFFULL for USART_CTRL */\r
+#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */\r
+#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */\r
+#define USART_CTRL_RXINV (1 << 13) /**< Receiver Input Invert */\r
+#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */\r
+#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */\r
+#define USART_CTRL_RXINV_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_TXINV (1 << 14) /**< Transmitter output Invert */\r
+#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */\r
+#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */\r
+#define USART_CTRL_TXINV_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_CSINV (1 << 15) /**< Chip Select Invert */\r
+#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */\r
+#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */\r
+#define USART_CTRL_CSINV_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_AUTOCS (1 << 16) /**< Automatic Chip Select */\r
+#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */\r
+#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */\r
+#define USART_CTRL_AUTOCS_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_AUTOTRI (1 << 17) /**< Automatic TX Tristate */\r
+#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */\r
+#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */\r
+#define USART_CTRL_AUTOTRI_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_SCMODE (1 << 18) /**< SmartCard Mode */\r
+#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */\r
+#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */\r
+#define USART_CTRL_SCMODE_DEFAULT (0x00000000UL << 18) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_SCRETRANS (1 << 19) /**< SmartCard Retransmit */\r
+#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */\r
+#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */\r
+#define USART_CTRL_SCRETRANS_DEFAULT (0x00000000UL << 19) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_SKIPPERRF (1 << 20) /**< Skip Parity Error Frames */\r
+#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */\r
+#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */\r
+#define USART_CTRL_SKIPPERRF_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_BIT8DV (1 << 21) /**< Bit 8 Default Value */\r
+#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */\r
+#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */\r
+#define USART_CTRL_BIT8DV_DEFAULT (0x00000000UL << 21) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_ERRSDMA (1 << 22) /**< Halt DMA On Error */\r
+#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */\r
+#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */\r
+#define USART_CTRL_ERRSDMA_DEFAULT (0x00000000UL << 22) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_ERRSRX (1 << 23) /**< Disable RX On Error */\r
+#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */\r
+#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */\r
+#define USART_CTRL_ERRSRX_DEFAULT (0x00000000UL << 23) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_ERRSTX (1 << 24) /**< Disable TX On Error */\r
+#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */\r
+#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */\r
+#define USART_CTRL_ERRSTX_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_TXDELAY_SHIFT 26 /**< Shift value for USART_TXDELAY */\r
+#define _USART_CTRL_TXDELAY_MASK 0xC000000UL /**< Bit mask for USART_TXDELAY */\r
+#define USART_CTRL_TXDELAY_DEFAULT (0x00000000UL << 26) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define USART_CTRL_TXDELAY_NONE (0x00000000UL << 26) /**< Shifted mode NONE for USART_CTRL */\r
+#define USART_CTRL_TXDELAY_SINGLE (0x00000001UL << 26) /**< Shifted mode SINGLE for USART_CTRL */\r
+#define USART_CTRL_TXDELAY_DOUBLE (0x00000002UL << 26) /**< Shifted mode DOUBLE for USART_CTRL */\r
+#define USART_CTRL_TXDELAY_TRIPLE (0x00000003UL << 26) /**< Shifted mode TRIPLE for USART_CTRL */\r
+#define _USART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for USART_CTRL */\r
+#define _USART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for USART_CTRL */\r
+#define _USART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for USART_CTRL */\r
+#define _USART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for USART_CTRL */\r
+#define USART_CTRL_BYTESWAP (1 << 28) /**< Byteswap In Double Accesses */\r
+#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */\r
+#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */\r
+#define USART_CTRL_BYTESWAP_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for USART_CTRL */\r
+#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */\r
+\r
+/** Bit fields for USART FRAME */\r
+#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */\r
+#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */\r
+#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */\r
+#define USART_FRAME_DATABITS_FOUR (0x00000001UL << 0) /**< Shifted mode FOUR for USART_FRAME */\r
+#define USART_FRAME_DATABITS_FIVE (0x00000002UL << 0) /**< Shifted mode FIVE for USART_FRAME */\r
+#define USART_FRAME_DATABITS_SIX (0x00000003UL << 0) /**< Shifted mode SIX for USART_FRAME */\r
+#define USART_FRAME_DATABITS_SEVEN (0x00000004UL << 0) /**< Shifted mode SEVEN for USART_FRAME */\r
+#define USART_FRAME_DATABITS_DEFAULT (0x00000005UL << 0) /**< Shifted mode DEFAULT for USART_FRAME */\r
+#define USART_FRAME_DATABITS_EIGHT (0x00000005UL << 0) /**< Shifted mode EIGHT for USART_FRAME */\r
+#define USART_FRAME_DATABITS_NINE (0x00000006UL << 0) /**< Shifted mode NINE for USART_FRAME */\r
+#define USART_FRAME_DATABITS_TEN (0x00000007UL << 0) /**< Shifted mode TEN for USART_FRAME */\r
+#define USART_FRAME_DATABITS_ELEVEN (0x00000008UL << 0) /**< Shifted mode ELEVEN for USART_FRAME */\r
+#define USART_FRAME_DATABITS_TWELVE (0x00000009UL << 0) /**< Shifted mode TWELVE for USART_FRAME */\r
+#define USART_FRAME_DATABITS_THIRTEEN (0x0000000AUL << 0) /**< Shifted mode THIRTEEN for USART_FRAME */\r
+#define USART_FRAME_DATABITS_FOURTEEN (0x0000000BUL << 0) /**< Shifted mode FOURTEEN for USART_FRAME */\r
+#define USART_FRAME_DATABITS_FIFTEEN (0x0000000CUL << 0) /**< Shifted mode FIFTEEN for USART_FRAME */\r
+#define USART_FRAME_DATABITS_SIXTEEN (0x0000000DUL << 0) /**< Shifted mode SIXTEEN for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */\r
+#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */\r
+#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */\r
+#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */\r
+#define USART_FRAME_PARITY_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_FRAME */\r
+#define USART_FRAME_PARITY_NONE (0x00000000UL << 8) /**< Shifted mode NONE for USART_FRAME */\r
+#define USART_FRAME_PARITY_EVEN (0x00000002UL << 8) /**< Shifted mode EVEN for USART_FRAME */\r
+#define USART_FRAME_PARITY_ODD (0x00000003UL << 8) /**< Shifted mode ODD for USART_FRAME */\r
+#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */\r
+#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */\r
+#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */\r
+#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */\r
+#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */\r
+#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */\r
+#define USART_FRAME_STOPBITS_HALF (0x00000000UL << 12) /**< Shifted mode HALF for USART_FRAME */\r
+#define USART_FRAME_STOPBITS_DEFAULT (0x00000001UL << 12) /**< Shifted mode DEFAULT for USART_FRAME */\r
+#define USART_FRAME_STOPBITS_ONE (0x00000001UL << 12) /**< Shifted mode ONE for USART_FRAME */\r
+#define USART_FRAME_STOPBITS_ONEANDAHALF (0x00000002UL << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */\r
+#define USART_FRAME_STOPBITS_TWO (0x00000003UL << 12) /**< Shifted mode TWO for USART_FRAME */\r
+#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */\r
+#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */\r
+#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */\r
+#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */\r
+#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */\r
+\r
+/** Bit fields for USART TRIGCTRL */\r
+#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_MASK 0x00000037UL /**< Mask for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_SHIFT 0 /**< Shift value for USART_TSEL */\r
+#define _USART_TRIGCTRL_TSEL_MASK 0x7UL /**< Bit mask for USART_TSEL */\r
+#define USART_TRIGCTRL_TSEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH0 (0x00000000UL << 0) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH1 (0x00000001UL << 0) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH2 (0x00000002UL << 0) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH3 (0x00000003UL << 0) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH4 (0x00000004UL << 0) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH5 (0x00000005UL << 0) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH6 (0x00000006UL << 0) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TSEL_PRSCH7 (0x00000007UL << 0) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_RXTEN (1 << 4) /**< Receive Trigger Enable */\r
+#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */\r
+#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */\r
+#define USART_TRIGCTRL_RXTEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */\r
+#define USART_TRIGCTRL_TXTEN (1 << 5) /**< Transmit Trigger Enable */\r
+#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */\r
+#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */\r
+#define USART_TRIGCTRL_TXTEN_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */\r
+#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */\r
+\r
+/** Bit fields for USART CMD */\r
+#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */\r
+#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */\r
+#define USART_CMD_RXEN (1 << 0) /**< Receiver Enable */\r
+#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */\r
+#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */\r
+#define USART_CMD_RXEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_RXDIS (1 << 1) /**< Receiver Disable */\r
+#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */\r
+#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */\r
+#define USART_CMD_RXDIS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_TXEN (1 << 2) /**< Transmitter Enable */\r
+#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */\r
+#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */\r
+#define USART_CMD_TXEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_TXDIS (1 << 3) /**< Transmitter Disable */\r
+#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */\r
+#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */\r
+#define USART_CMD_TXDIS_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_MASTEREN (1 << 4) /**< Master Enable */\r
+#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */\r
+#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */\r
+#define USART_CMD_MASTEREN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_MASTERDIS (1 << 5) /**< Master Disable */\r
+#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */\r
+#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */\r
+#define USART_CMD_MASTERDIS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_RXBLOCKEN (1 << 6) /**< Receiver Block Enable */\r
+#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */\r
+#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */\r
+#define USART_CMD_RXBLOCKEN_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_RXBLOCKDIS (1 << 7) /**< Receiver Block Disable */\r
+#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */\r
+#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */\r
+#define USART_CMD_RXBLOCKDIS_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_TXTRIEN (1 << 8) /**< Transmitter Tristate Enable */\r
+#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */\r
+#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */\r
+#define USART_CMD_TXTRIEN_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_TXTRIDIS (1 << 9) /**< Transmitter Tristate Disable */\r
+#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */\r
+#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */\r
+#define USART_CMD_TXTRIDIS_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_CLEARTX (1 << 10) /**< Clear TX */\r
+#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */\r
+#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */\r
+#define USART_CMD_CLEARTX_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+#define USART_CMD_CLEARRX (1 << 11) /**< Clear RX */\r
+#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */\r
+#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */\r
+#define USART_CMD_CLEARRX_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_CMD */\r
+#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */\r
+\r
+/** Bit fields for USART STATUS */\r
+#define _USART_STATUS_RESETVALUE 0x00000040UL /**< Default value for USART_STATUS */\r
+#define _USART_STATUS_MASK 0x000001FFUL /**< Mask for USART_STATUS */\r
+#define USART_STATUS_RXENS (1 << 0) /**< Receiver Enable Status */\r
+#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */\r
+#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */\r
+#define USART_STATUS_RXENS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXENS (1 << 1) /**< Transmitter Enable Status */\r
+#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */\r
+#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */\r
+#define USART_STATUS_TXENS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_MASTER (1 << 2) /**< SPI Master Mode */\r
+#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */\r
+#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */\r
+#define USART_STATUS_MASTER_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_RXBLOCK (1 << 3) /**< Block Incoming Data */\r
+#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */\r
+#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */\r
+#define USART_STATUS_RXBLOCK_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXTRI (1 << 4) /**< Transmitter Tristated */\r
+#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */\r
+#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */\r
+#define USART_STATUS_TXTRI_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXC (1 << 5) /**< TX Complete */\r
+#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */\r
+#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */\r
+#define USART_STATUS_TXC_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_TXBL (1 << 6) /**< TX Buffer Level */\r
+#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */\r
+#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */\r
+#define USART_STATUS_TXBL_DEFAULT (0x00000001UL << 6) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_RXDATAV (1 << 7) /**< RX Data Valid */\r
+#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */\r
+#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */\r
+#define USART_STATUS_RXDATAV_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+#define USART_STATUS_RXFULL (1 << 8) /**< RX FIFO Full */\r
+#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */\r
+#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */\r
+#define USART_STATUS_RXFULL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_STATUS */\r
+#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */\r
+\r
+/** Bit fields for USART CLKDIV */\r
+#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */\r
+#define _USART_CLKDIV_MASK 0x001FFFC0UL /**< Mask for USART_CLKDIV */\r
+#define _USART_CLKDIV_DIV_SHIFT 6 /**< Shift value for USART_DIV */\r
+#define _USART_CLKDIV_DIV_MASK 0x1FFFC0UL /**< Bit mask for USART_DIV */\r
+#define USART_CLKDIV_DIV_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for USART_CLKDIV */\r
+#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */\r
+\r
+/** Bit fields for USART RXDATAX */\r
+#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */\r
+#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */\r
+#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */\r
+#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */\r
+#define USART_RXDATAX_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */\r
+#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */\r
+#define USART_RXDATAX_PERR (1 << 14) /**< Data Parity Error */\r
+#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */\r
+#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */\r
+#define USART_RXDATAX_PERR_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */\r
+#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */\r
+#define USART_RXDATAX_FERR (1 << 15) /**< Data Framing Error */\r
+#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */\r
+#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */\r
+#define USART_RXDATAX_FERR_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */\r
+#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */\r
+\r
+/** Bit fields for USART RXDATA */\r
+#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */\r
+#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */\r
+#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */\r
+#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */\r
+#define USART_RXDATA_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDATA */\r
+#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */\r
+\r
+/** Bit fields for USART RXDOUBLEX */\r
+#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */\r
+#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */\r
+#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */\r
+#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */\r
+#define USART_RXDOUBLEX_RXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */\r
+#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */\r
+#define USART_RXDOUBLEX_PERR0 (1 << 14) /**< Data Parity Error 0 */\r
+#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */\r
+#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */\r
+#define USART_RXDOUBLEX_PERR0_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */\r
+#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */\r
+#define USART_RXDOUBLEX_FERR0 (1 << 15) /**< Data Framing Error 0 */\r
+#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */\r
+#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */\r
+#define USART_RXDOUBLEX_FERR0_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */\r
+#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */\r
+#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */\r
+#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */\r
+#define USART_RXDOUBLEX_RXDATA1_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */\r
+#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */\r
+#define USART_RXDOUBLEX_PERR1 (1 << 30) /**< Data Parity Error 1 */\r
+#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */\r
+#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */\r
+#define USART_RXDOUBLEX_PERR1_DEFAULT (0x00000000UL << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */\r
+#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */\r
+#define USART_RXDOUBLEX_FERR1 (1 << 31) /**< Data Framing Error 1 */\r
+#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */\r
+#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */\r
+#define USART_RXDOUBLEX_FERR1_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */\r
+#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */\r
+\r
+/** Bit fields for USART RXDOUBLE */\r
+#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */\r
+#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */\r
+#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */\r
+#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */\r
+#define USART_RXDOUBLE_RXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */\r
+#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */\r
+#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */\r
+#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */\r
+#define USART_RXDOUBLE_RXDATA1_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */\r
+#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */\r
+\r
+/** Bit fields for USART RXDATAXP */\r
+#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */\r
+#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */\r
+#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */\r
+#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */\r
+#define USART_RXDATAXP_RXDATAP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */\r
+#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */\r
+#define USART_RXDATAXP_PERRP (1 << 14) /**< Data Parity Error Peek */\r
+#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */\r
+#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */\r
+#define USART_RXDATAXP_PERRP_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */\r
+#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */\r
+#define USART_RXDATAXP_FERRP (1 << 15) /**< Data Framing Error Peek */\r
+#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */\r
+#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */\r
+#define USART_RXDATAXP_FERRP_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */\r
+#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */\r
+\r
+/** Bit fields for USART RXDOUBLEXP */\r
+#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */\r
+#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */\r
+#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */\r
+#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */\r
+#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */\r
+#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */\r
+#define USART_RXDOUBLEXP_PERRP0 (1 << 14) /**< Data Parity Error 0 Peek */\r
+#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */\r
+#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */\r
+#define USART_RXDOUBLEXP_PERRP0_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */\r
+#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */\r
+#define USART_RXDOUBLEXP_FERRP0 (1 << 15) /**< Data Framing Error 0 Peek */\r
+#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */\r
+#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */\r
+#define USART_RXDOUBLEXP_FERRP0_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */\r
+#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */\r
+#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */\r
+#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */\r
+#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */\r
+#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */\r
+#define USART_RXDOUBLEXP_PERRP1 (1 << 30) /**< Data Parity Error 1 Peek */\r
+#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */\r
+#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */\r
+#define USART_RXDOUBLEXP_PERRP1_DEFAULT (0x00000000UL << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */\r
+#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */\r
+#define USART_RXDOUBLEXP_FERRP1 (1 << 31) /**< Data Framing Error 1 Peek */\r
+#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */\r
+#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */\r
+#define USART_RXDOUBLEXP_FERRP1_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */\r
+#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */\r
+\r
+/** Bit fields for USART TXDATAX */\r
+#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */\r
+#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */\r
+#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */\r
+#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */\r
+#define USART_TXDATAX_TXDATAX_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */\r
+#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_UBRXAT (1 << 11) /**< Unblock RX After Transmission */\r
+#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */\r
+#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */\r
+#define USART_TXDATAX_UBRXAT_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */\r
+#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_TXTRIAT (1 << 12) /**< Set TXTRI After Transmission */\r
+#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */\r
+#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */\r
+#define USART_TXDATAX_TXTRIAT_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */\r
+#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_TXBREAK (1 << 13) /**< Transmit Data As Break */\r
+#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */\r
+#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */\r
+#define USART_TXDATAX_TXBREAK_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */\r
+#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_TXDISAT (1 << 14) /**< Clear TXEN After Transmission */\r
+#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */\r
+#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */\r
+#define USART_TXDATAX_TXDISAT_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */\r
+#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */\r
+#define USART_TXDATAX_RXENAT (1 << 15) /**< Enable RX After Transmission */\r
+#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */\r
+#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */\r
+#define USART_TXDATAX_RXENAT_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */\r
+#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */\r
+\r
+/** Bit fields for USART TXDATA */\r
+#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */\r
+#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */\r
+#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */\r
+#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */\r
+#define USART_TXDATA_TXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_TXDATA */\r
+#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */\r
+\r
+/** Bit fields for USART TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */\r
+#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */\r
+#define USART_TXDOUBLEX_TXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_UBRXAT0 (1 << 11) /**< Unblock RX After Transmission */\r
+#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */\r
+#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */\r
+#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXTRIAT0 (1 << 12) /**< Set TXTRI After Transmission */\r
+#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */\r
+#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */\r
+#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXBREAK0 (1 << 13) /**< Transmit Data As Break */\r
+#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */\r
+#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */\r
+#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXDISAT0 (1 << 14) /**< Clear TXEN After Transmission */\r
+#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */\r
+#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */\r
+#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_RXENAT0 (1 << 15) /**< Enable RX After Transmission */\r
+#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */\r
+#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */\r
+#define USART_TXDOUBLEX_RXENAT0_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */\r
+#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */\r
+#define USART_TXDOUBLEX_TXDATA1_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_UBRXAT1 (1 << 27) /**< Unblock RX After Transmission */\r
+#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */\r
+#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */\r
+#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (0x00000000UL << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXTRIAT1 (1 << 28) /**< Set TXTRI After Transmission */\r
+#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */\r
+#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */\r
+#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXBREAK1 (1 << 29) /**< Transmit Data As Break */\r
+#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */\r
+#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */\r
+#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (0x00000000UL << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_TXDISAT1 (1 << 30) /**< Clear TXEN After Transmission */\r
+#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */\r
+#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */\r
+#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (0x00000000UL << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+#define USART_TXDOUBLEX_RXENAT1 (1 << 31) /**< Enable RX After Transmission */\r
+#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */\r
+#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */\r
+#define USART_TXDOUBLEX_RXENAT1_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */\r
+#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */\r
+\r
+/** Bit fields for USART TXDOUBLE */\r
+#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */\r
+#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */\r
+#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */\r
+#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */\r
+#define USART_TXDOUBLE_TXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */\r
+#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */\r
+#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */\r
+#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */\r
+#define USART_TXDOUBLE_TXDATA1_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */\r
+#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */\r
+\r
+/** Bit fields for USART IF */\r
+#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */\r
+#define _USART_IF_MASK 0x00001FFFUL /**< Mask for USART_IF */\r
+#define USART_IF_TXC (1 << 0) /**< TX Complete Interrupt Flag */\r
+#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */\r
+#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */\r
+#define USART_IF_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_IF */\r
+#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_TXBL (1 << 1) /**< TX Buffer Level Interrupt Flag */\r
+#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */\r
+#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */\r
+#define USART_IF_TXBL_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for USART_IF */\r
+#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_RXDATAV (1 << 2) /**< RX Data Valid Interrupt Flag */\r
+#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */\r
+#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */\r
+#define USART_IF_RXDATAV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for USART_IF */\r
+#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_RXFULL (1 << 3) /**< RX Buffer Full Interrupt Flag */\r
+#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */\r
+#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */\r
+#define USART_IF_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_IF */\r
+#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_RXOF (1 << 4) /**< RX Overflow Interrupt Flag */\r
+#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */\r
+#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */\r
+#define USART_IF_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_IF */\r
+#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_RXUF (1 << 5) /**< RX Underflow Interrupt Flag */\r
+#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */\r
+#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */\r
+#define USART_IF_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_IF */\r
+#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_TXOF (1 << 6) /**< TX Overflow Interrupt Flag */\r
+#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */\r
+#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */\r
+#define USART_IF_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for USART_IF */\r
+#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_TXUF (1 << 7) /**< TX Underflow Interrupt Flag */\r
+#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */\r
+#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */\r
+#define USART_IF_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_IF */\r
+#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_PERR (1 << 8) /**< Parity Error Interrupt Flag */\r
+#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */\r
+#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */\r
+#define USART_IF_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_IF */\r
+#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_FERR (1 << 9) /**< Framing Error Interrupt Flag */\r
+#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */\r
+#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */\r
+#define USART_IF_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for USART_IF */\r
+#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_MPAF (1 << 10) /**< Multi-Processor Address Frame Interrupt Flag */\r
+#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */\r
+#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */\r
+#define USART_IF_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for USART_IF */\r
+#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_SSM (1 << 11) /**< Slave-Select In Master Mode Interrupt Flag */\r
+#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */\r
+#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */\r
+#define USART_IF_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_IF */\r
+#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+#define USART_IF_CCF (1 << 12) /**< Collision Check Fail Interrupt Flag */\r
+#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */\r
+#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */\r
+#define USART_IF_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for USART_IF */\r
+#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */\r
+\r
+/** Bit fields for USART IFS */\r
+#define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */\r
+#define _USART_IFS_MASK 0x00001FF9UL /**< Mask for USART_IFS */\r
+#define USART_IFS_TXC (1 << 0) /**< Set TX Complete Interrupt Flag */\r
+#define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */\r
+#define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */\r
+#define USART_IFS_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_RXFULL (1 << 3) /**< Set RX Buffer Full Interrupt Flag */\r
+#define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */\r
+#define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */\r
+#define USART_IFS_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_RXOF (1 << 4) /**< Set RX Overflow Interrupt Flag */\r
+#define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */\r
+#define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */\r
+#define USART_IFS_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_RXUF (1 << 5) /**< Set RX Underflow Interrupt Flag */\r
+#define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */\r
+#define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */\r
+#define USART_IFS_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_TXOF (1 << 6) /**< Set TX Overflow Interrupt Flag */\r
+#define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */\r
+#define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */\r
+#define USART_IFS_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_TXUF (1 << 7) /**< Set TX Underflow Interrupt Flag */\r
+#define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */\r
+#define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */\r
+#define USART_IFS_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_PERR (1 << 8) /**< Set Parity Error Interrupt Flag */\r
+#define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */\r
+#define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */\r
+#define USART_IFS_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_FERR (1 << 9) /**< Set Framing Error Interrupt Flag */\r
+#define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */\r
+#define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */\r
+#define USART_IFS_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_MPAF (1 << 10) /**< Set Multi-Processor Address Frame Interrupt Flag */\r
+#define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */\r
+#define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */\r
+#define USART_IFS_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_SSM (1 << 11) /**< Set Slave-Select in Master mode Interrupt Flag */\r
+#define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */\r
+#define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */\r
+#define USART_IFS_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+#define USART_IFS_CCF (1 << 12) /**< Set Collision Check Fail Interrupt Flag */\r
+#define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */\r
+#define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */\r
+#define USART_IFS_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for USART_IFS */\r
+#define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */\r
+\r
+/** Bit fields for USART IFC */\r
+#define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */\r
+#define _USART_IFC_MASK 0x00001FF9UL /**< Mask for USART_IFC */\r
+#define USART_IFC_TXC (1 << 0) /**< Clear TX Complete Interrupt Flag */\r
+#define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */\r
+#define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */\r
+#define USART_IFC_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_RXFULL (1 << 3) /**< Clear RX Buffer Full Interrupt Flag */\r
+#define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */\r
+#define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */\r
+#define USART_IFC_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_RXOF (1 << 4) /**< Clear RX Overflow Interrupt Flag */\r
+#define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */\r
+#define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */\r
+#define USART_IFC_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_RXUF (1 << 5) /**< Clear RX Underflow Interrupt Flag */\r
+#define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */\r
+#define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */\r
+#define USART_IFC_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_TXOF (1 << 6) /**< Clear TX Overflow Interrupt Flag */\r
+#define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */\r
+#define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */\r
+#define USART_IFC_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_TXUF (1 << 7) /**< Clear TX Underflow Interrupt Flag */\r
+#define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */\r
+#define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */\r
+#define USART_IFC_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_PERR (1 << 8) /**< Clear Parity Error Interrupt Flag */\r
+#define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */\r
+#define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */\r
+#define USART_IFC_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_FERR (1 << 9) /**< Clear Framing Error Interrupt Flag */\r
+#define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */\r
+#define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */\r
+#define USART_IFC_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_MPAF (1 << 10) /**< Clear Multi-Processor Address Frame Interrupt Flag */\r
+#define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */\r
+#define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */\r
+#define USART_IFC_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_SSM (1 << 11) /**< Clear Slave-Select In Master Mode Interrupt Flag */\r
+#define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */\r
+#define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */\r
+#define USART_IFC_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+#define USART_IFC_CCF (1 << 12) /**< Clear Collision Check Fail Interrupt Flag */\r
+#define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */\r
+#define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */\r
+#define USART_IFC_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for USART_IFC */\r
+#define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */\r
+\r
+/** Bit fields for USART IEN */\r
+#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */\r
+#define _USART_IEN_MASK 0x00001FFFUL /**< Mask for USART_IEN */\r
+#define USART_IEN_TXC (1 << 0) /**< TX Complete Interrupt Enable */\r
+#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */\r
+#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */\r
+#define USART_IEN_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TXBL (1 << 1) /**< TX Buffer Level Interrupt Enable */\r
+#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */\r
+#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */\r
+#define USART_IEN_TXBL_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_RXDATAV (1 << 2) /**< RX Data Valid Interrupt Enable */\r
+#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */\r
+#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */\r
+#define USART_IEN_RXDATAV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_RXFULL (1 << 3) /**< RX Buffer Full Interrupt Enable */\r
+#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */\r
+#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */\r
+#define USART_IEN_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_RXOF (1 << 4) /**< RX Overflow Interrupt Enable */\r
+#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */\r
+#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */\r
+#define USART_IEN_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_RXUF (1 << 5) /**< RX Underflow Interrupt Enable */\r
+#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */\r
+#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */\r
+#define USART_IEN_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TXOF (1 << 6) /**< TX Overflow Interrupt Enable */\r
+#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */\r
+#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */\r
+#define USART_IEN_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_TXUF (1 << 7) /**< TX Underflow Interrupt Enable */\r
+#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */\r
+#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */\r
+#define USART_IEN_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_PERR (1 << 8) /**< Parity Error Interrupt Enable */\r
+#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */\r
+#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */\r
+#define USART_IEN_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_FERR (1 << 9) /**< Framing Error Interrupt Enable */\r
+#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */\r
+#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */\r
+#define USART_IEN_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_MPAF (1 << 10) /**< Multi-Processor Address Frame Interrupt Enable */\r
+#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */\r
+#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */\r
+#define USART_IEN_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_SSM (1 << 11) /**< Slave-Select In Master Mode Interrupt Enable */\r
+#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */\r
+#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */\r
+#define USART_IEN_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+#define USART_IEN_CCF (1 << 12) /**< Collision Check Fail Interrupt Enable */\r
+#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */\r
+#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */\r
+#define USART_IEN_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for USART_IEN */\r
+#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */\r
+\r
+/** Bit fields for USART IRCTRL */\r
+#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */\r
+#define _USART_IRCTRL_MASK 0x000000FFUL /**< Mask for USART_IRCTRL */\r
+#define USART_IRCTRL_IREN (1 << 0) /**< Enable IrDA Module */\r
+#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */\r
+#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */\r
+#define USART_IRCTRL_IREN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */\r
+#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */\r
+#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */\r
+#define USART_IRCTRL_IRPW_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPW_ONE (0x00000000UL << 1) /**< Shifted mode ONE for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPW_TWO (0x00000001UL << 1) /**< Shifted mode TWO for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPW_THREE (0x00000002UL << 1) /**< Shifted mode THREE for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPW_FOUR (0x00000003UL << 1) /**< Shifted mode FOUR for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */\r
+#define USART_IRCTRL_IRFILT (1 << 3) /**< IrDA RX Filter */\r
+#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */\r
+#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */\r
+#define USART_IRCTRL_IRFILT_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_SHIFT 4 /**< Shift value for USART_IRPRSSEL */\r
+#define _USART_IRCTRL_IRPRSSEL_MASK 0x70UL /**< Bit mask for USART_IRPRSSEL */\r
+#define USART_IRCTRL_IRPRSSEL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH0 (0x00000000UL << 4) /**< Shifted mode PRSCH0 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH1 (0x00000001UL << 4) /**< Shifted mode PRSCH1 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH2 (0x00000002UL << 4) /**< Shifted mode PRSCH2 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH3 (0x00000003UL << 4) /**< Shifted mode PRSCH3 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH4 (0x00000004UL << 4) /**< Shifted mode PRSCH4 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH5 (0x00000005UL << 4) /**< Shifted mode PRSCH5 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH6 (0x00000006UL << 4) /**< Shifted mode PRSCH6 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSSEL_PRSCH7 (0x00000007UL << 4) /**< Shifted mode PRSCH7 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */\r
+#define USART_IRCTRL_IRPRSEN (1 << 7) /**< IrDA PRS Channel Enable */\r
+#define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */\r
+#define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */\r
+#define USART_IRCTRL_IRPRSEN_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */\r
+#define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */\r
+\r
+/** Bit fields for USART ROUTE */\r
+#define _USART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTE */\r
+#define _USART_ROUTE_MASK 0x0000030FUL /**< Mask for USART_ROUTE */\r
+#define USART_ROUTE_RXPEN (1 << 0) /**< RX Pin Enable */\r
+#define _USART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */\r
+#define _USART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */\r
+#define USART_ROUTE_RXPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for USART_ROUTE */\r
+#define _USART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */\r
+#define USART_ROUTE_TXPEN (1 << 1) /**< TX Pin Enable */\r
+#define _USART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */\r
+#define _USART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */\r
+#define USART_ROUTE_TXPEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for USART_ROUTE */\r
+#define _USART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */\r
+#define USART_ROUTE_CSPEN (1 << 2) /**< CS Pin Enable */\r
+#define _USART_ROUTE_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */\r
+#define _USART_ROUTE_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */\r
+#define USART_ROUTE_CSPEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for USART_ROUTE */\r
+#define _USART_ROUTE_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */\r
+#define USART_ROUTE_CLKPEN (1 << 3) /**< RX Pin Enable */\r
+#define _USART_ROUTE_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */\r
+#define _USART_ROUTE_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */\r
+#define USART_ROUTE_CLKPEN_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for USART_ROUTE */\r
+#define _USART_ROUTE_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */\r
+#define _USART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for USART_LOCATION */\r
+#define _USART_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for USART_LOCATION */\r
+#define USART_ROUTE_LOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for USART_ROUTE */\r
+#define USART_ROUTE_LOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for USART_ROUTE */\r
+#define USART_ROUTE_LOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for USART_ROUTE */\r
+#define USART_ROUTE_LOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for USART_ROUTE */\r
+#define USART_ROUTE_LOCATION_LOC3 (0x00000003UL << 8) /**< Shifted mode LOC3 for USART_ROUTE */\r
+#define _USART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */\r
+#define _USART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTE */\r
+#define _USART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTE */\r
+#define _USART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTE */\r
+#define _USART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_UART\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for UART CTRL */\r
+#define _UART_CTRL_RESETVALUE 0x00000000UL /**< Default value for UART_CTRL */\r
+#define _UART_CTRL_MASK 0x1DFFFF7FUL /**< Mask for UART_CTRL */\r
+#define UART_CTRL_SYNC (1 << 0) /**< USART Synchronous Mode */\r
+#define _UART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */\r
+#define _UART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */\r
+#define UART_CTRL_SYNC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_LOOPBK (1 << 1) /**< Loopback Enable */\r
+#define _UART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */\r
+#define _UART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */\r
+#define UART_CTRL_LOOPBK_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_CCEN (1 << 2) /**< Collision Check Enable */\r
+#define _UART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */\r
+#define _UART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */\r
+#define UART_CTRL_CCEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_MPM (1 << 3) /**< Multi-Processor Mode */\r
+#define _UART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */\r
+#define _UART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */\r
+#define UART_CTRL_MPM_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_MPAB (1 << 4) /**< Multi-Processor Address-Bit */\r
+#define _UART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */\r
+#define _UART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */\r
+#define UART_CTRL_MPAB_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */\r
+#define _UART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */\r
+#define UART_CTRL_OVS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_OVS_X16 (0x00000000UL << 5) /**< Shifted mode X16 for UART_CTRL */\r
+#define UART_CTRL_OVS_X8 (0x00000001UL << 5) /**< Shifted mode X8 for UART_CTRL */\r
+#define UART_CTRL_OVS_X6 (0x00000002UL << 5) /**< Shifted mode X6 for UART_CTRL */\r
+#define UART_CTRL_OVS_X4 (0x00000003UL << 5) /**< Shifted mode X4 for UART_CTRL */\r
+#define _UART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for UART_CTRL */\r
+#define _UART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for UART_CTRL */\r
+#define _UART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for UART_CTRL */\r
+#define _UART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for UART_CTRL */\r
+#define UART_CTRL_CLKPOL (1 << 8) /**< Clock Polarity */\r
+#define _UART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */\r
+#define _UART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */\r
+#define UART_CTRL_CLKPOL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_CLKPOL_IDLELOW (0x00000000UL << 8) /**< Shifted mode IDLELOW for UART_CTRL */\r
+#define UART_CTRL_CLKPOL_IDLEHIGH (0x00000001UL << 8) /**< Shifted mode IDLEHIGH for UART_CTRL */\r
+#define _UART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for UART_CTRL */\r
+#define _UART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for UART_CTRL */\r
+#define UART_CTRL_CLKPHA (1 << 9) /**< Clock Edge For Setup/Sample */\r
+#define _UART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */\r
+#define _UART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */\r
+#define UART_CTRL_CLKPHA_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_CLKPHA_SAMPLELEADING (0x00000000UL << 9) /**< Shifted mode SAMPLELEADING for UART_CTRL */\r
+#define UART_CTRL_CLKPHA_SAMPLETRAILING (0x00000001UL << 9) /**< Shifted mode SAMPLETRAILING for UART_CTRL */\r
+#define _UART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for UART_CTRL */\r
+#define _UART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for UART_CTRL */\r
+#define UART_CTRL_MSBF (1 << 10) /**< Most Significant Bit First */\r
+#define _UART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */\r
+#define _UART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */\r
+#define UART_CTRL_MSBF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_CSMA (1 << 11) /**< Action On Slave-Select In Master Mode */\r
+#define _UART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */\r
+#define _UART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */\r
+#define UART_CTRL_CSMA_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_CSMA_NOACTION (0x00000000UL << 11) /**< Shifted mode NOACTION for UART_CTRL */\r
+#define UART_CTRL_CSMA_GOTOSLAVEMODE (0x00000001UL << 11) /**< Shifted mode GOTOSLAVEMODE for UART_CTRL */\r
+#define _UART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for UART_CTRL */\r
+#define _UART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for UART_CTRL */\r
+#define UART_CTRL_TXBIL (1 << 12) /**< TX Buffer Interrupt Level */\r
+#define _UART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */\r
+#define _UART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */\r
+#define UART_CTRL_TXBIL_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_TXBIL_EMPTY (0x00000000UL << 12) /**< Shifted mode EMPTY for UART_CTRL */\r
+#define UART_CTRL_TXBIL_HALFFULL (0x00000001UL << 12) /**< Shifted mode HALFFULL for UART_CTRL */\r
+#define _UART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for UART_CTRL */\r
+#define _UART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for UART_CTRL */\r
+#define UART_CTRL_RXINV (1 << 13) /**< Receiver Input Invert */\r
+#define _UART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */\r
+#define _UART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */\r
+#define UART_CTRL_RXINV_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_TXINV (1 << 14) /**< Transmitter output Invert */\r
+#define _UART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */\r
+#define _UART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */\r
+#define UART_CTRL_TXINV_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_CSINV (1 << 15) /**< Chip Select Invert */\r
+#define _UART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */\r
+#define _UART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */\r
+#define UART_CTRL_CSINV_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_AUTOCS (1 << 16) /**< Automatic Chip Select */\r
+#define _UART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */\r
+#define _UART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */\r
+#define UART_CTRL_AUTOCS_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_AUTOTRI (1 << 17) /**< Automatic TX Tristate */\r
+#define _UART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */\r
+#define _UART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */\r
+#define UART_CTRL_AUTOTRI_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_SCMODE (1 << 18) /**< SmartCard Mode */\r
+#define _UART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */\r
+#define _UART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */\r
+#define UART_CTRL_SCMODE_DEFAULT (0x00000000UL << 18) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_SCRETRANS (1 << 19) /**< SmartCard Retransmit */\r
+#define _UART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */\r
+#define _UART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */\r
+#define UART_CTRL_SCRETRANS_DEFAULT (0x00000000UL << 19) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_SKIPPERRF (1 << 20) /**< Skip Parity Error Frames */\r
+#define _UART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */\r
+#define _UART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */\r
+#define UART_CTRL_SKIPPERRF_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_BIT8DV (1 << 21) /**< Bit 8 Default Value */\r
+#define _UART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */\r
+#define _UART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */\r
+#define UART_CTRL_BIT8DV_DEFAULT (0x00000000UL << 21) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_ERRSDMA (1 << 22) /**< Halt DMA On Error */\r
+#define _UART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */\r
+#define _UART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */\r
+#define UART_CTRL_ERRSDMA_DEFAULT (0x00000000UL << 22) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_ERRSRX (1 << 23) /**< Disable RX On Error */\r
+#define _UART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */\r
+#define _UART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */\r
+#define UART_CTRL_ERRSRX_DEFAULT (0x00000000UL << 23) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_ERRSTX (1 << 24) /**< Disable TX On Error */\r
+#define _UART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */\r
+#define _UART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */\r
+#define UART_CTRL_ERRSTX_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_TXDELAY_SHIFT 26 /**< Shift value for USART_TXDELAY */\r
+#define _UART_CTRL_TXDELAY_MASK 0xC000000UL /**< Bit mask for USART_TXDELAY */\r
+#define UART_CTRL_TXDELAY_DEFAULT (0x00000000UL << 26) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define UART_CTRL_TXDELAY_NONE (0x00000000UL << 26) /**< Shifted mode NONE for UART_CTRL */\r
+#define UART_CTRL_TXDELAY_SINGLE (0x00000001UL << 26) /**< Shifted mode SINGLE for UART_CTRL */\r
+#define UART_CTRL_TXDELAY_DOUBLE (0x00000002UL << 26) /**< Shifted mode DOUBLE for UART_CTRL */\r
+#define UART_CTRL_TXDELAY_TRIPLE (0x00000003UL << 26) /**< Shifted mode TRIPLE for UART_CTRL */\r
+#define _UART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for UART_CTRL */\r
+#define _UART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for UART_CTRL */\r
+#define _UART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for UART_CTRL */\r
+#define _UART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for UART_CTRL */\r
+#define UART_CTRL_BYTESWAP (1 << 28) /**< Byteswap In Double Accesses */\r
+#define _UART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */\r
+#define _UART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */\r
+#define UART_CTRL_BYTESWAP_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for UART_CTRL */\r
+#define _UART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */\r
+\r
+/** Bit fields for UART FRAME */\r
+#define _UART_FRAME_RESETVALUE 0x00001005UL /**< Default value for UART_FRAME */\r
+#define _UART_FRAME_MASK 0x0000330FUL /**< Mask for UART_FRAME */\r
+#define _UART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */\r
+#define _UART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */\r
+#define UART_FRAME_DATABITS_FOUR (0x00000001UL << 0) /**< Shifted mode FOUR for UART_FRAME */\r
+#define UART_FRAME_DATABITS_FIVE (0x00000002UL << 0) /**< Shifted mode FIVE for UART_FRAME */\r
+#define UART_FRAME_DATABITS_SIX (0x00000003UL << 0) /**< Shifted mode SIX for UART_FRAME */\r
+#define UART_FRAME_DATABITS_SEVEN (0x00000004UL << 0) /**< Shifted mode SEVEN for UART_FRAME */\r
+#define UART_FRAME_DATABITS_DEFAULT (0x00000005UL << 0) /**< Shifted mode DEFAULT for UART_FRAME */\r
+#define UART_FRAME_DATABITS_EIGHT (0x00000005UL << 0) /**< Shifted mode EIGHT for UART_FRAME */\r
+#define UART_FRAME_DATABITS_NINE (0x00000006UL << 0) /**< Shifted mode NINE for UART_FRAME */\r
+#define UART_FRAME_DATABITS_TEN (0x00000007UL << 0) /**< Shifted mode TEN for UART_FRAME */\r
+#define UART_FRAME_DATABITS_ELEVEN (0x00000008UL << 0) /**< Shifted mode ELEVEN for UART_FRAME */\r
+#define UART_FRAME_DATABITS_TWELVE (0x00000009UL << 0) /**< Shifted mode TWELVE for UART_FRAME */\r
+#define UART_FRAME_DATABITS_THIRTEEN (0x0000000AUL << 0) /**< Shifted mode THIRTEEN for UART_FRAME */\r
+#define UART_FRAME_DATABITS_FOURTEEN (0x0000000BUL << 0) /**< Shifted mode FOURTEEN for UART_FRAME */\r
+#define UART_FRAME_DATABITS_FIFTEEN (0x0000000CUL << 0) /**< Shifted mode FIFTEEN for UART_FRAME */\r
+#define UART_FRAME_DATABITS_SIXTEEN (0x0000000DUL << 0) /**< Shifted mode SIXTEEN for UART_FRAME */\r
+#define _UART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for UART_FRAME */\r
+#define _UART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for UART_FRAME */\r
+#define _UART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for UART_FRAME */\r
+#define _UART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for UART_FRAME */\r
+#define _UART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for UART_FRAME */\r
+#define _UART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for UART_FRAME */\r
+#define _UART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for UART_FRAME */\r
+#define _UART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for UART_FRAME */\r
+#define _UART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for UART_FRAME */\r
+#define _UART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for UART_FRAME */\r
+#define _UART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for UART_FRAME */\r
+#define _UART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for UART_FRAME */\r
+#define _UART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for UART_FRAME */\r
+#define _UART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for UART_FRAME */\r
+#define _UART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */\r
+#define _UART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */\r
+#define UART_FRAME_PARITY_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_FRAME */\r
+#define UART_FRAME_PARITY_NONE (0x00000000UL << 8) /**< Shifted mode NONE for UART_FRAME */\r
+#define UART_FRAME_PARITY_EVEN (0x00000002UL << 8) /**< Shifted mode EVEN for UART_FRAME */\r
+#define UART_FRAME_PARITY_ODD (0x00000003UL << 8) /**< Shifted mode ODD for UART_FRAME */\r
+#define _UART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_FRAME */\r
+#define _UART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for UART_FRAME */\r
+#define _UART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for UART_FRAME */\r
+#define _UART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for UART_FRAME */\r
+#define _UART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */\r
+#define _UART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */\r
+#define UART_FRAME_STOPBITS_HALF (0x00000000UL << 12) /**< Shifted mode HALF for UART_FRAME */\r
+#define UART_FRAME_STOPBITS_DEFAULT (0x00000001UL << 12) /**< Shifted mode DEFAULT for UART_FRAME */\r
+#define UART_FRAME_STOPBITS_ONE (0x00000001UL << 12) /**< Shifted mode ONE for UART_FRAME */\r
+#define UART_FRAME_STOPBITS_ONEANDAHALF (0x00000002UL << 12) /**< Shifted mode ONEANDAHALF for UART_FRAME */\r
+#define UART_FRAME_STOPBITS_TWO (0x00000003UL << 12) /**< Shifted mode TWO for UART_FRAME */\r
+#define _UART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for UART_FRAME */\r
+#define _UART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_FRAME */\r
+#define _UART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for UART_FRAME */\r
+#define _UART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for UART_FRAME */\r
+#define _UART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for UART_FRAME */\r
+\r
+/** Bit fields for UART TRIGCTRL */\r
+#define _UART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_TRIGCTRL */\r
+#define _UART_TRIGCTRL_MASK 0x00000037UL /**< Mask for UART_TRIGCTRL */\r
+#define _UART_TRIGCTRL_TSEL_SHIFT 0 /**< Shift value for USART_TSEL */\r
+#define _UART_TRIGCTRL_TSEL_MASK 0x7UL /**< Bit mask for USART_TSEL */\r
+#define UART_TRIGCTRL_TSEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_TRIGCTRL */\r
+#define UART_TRIGCTRL_TSEL_PRSCH0 (0x00000000UL << 0) /**< Shifted mode PRSCH0 for UART_TRIGCTRL */\r
+#define UART_TRIGCTRL_TSEL_PRSCH1 (0x00000001UL << 0) /**< Shifted mode PRSCH1 for UART_TRIGCTRL */\r
+#define UART_TRIGCTRL_TSEL_PRSCH2 (0x00000002UL << 0) /**< Shifted mode PRSCH2 for UART_TRIGCTRL */\r
+#define UART_TRIGCTRL_TSEL_PRSCH3 (0x00000003UL << 0) /**< Shifted mode PRSCH3 for UART_TRIGCTRL */\r
+#define UART_TRIGCTRL_TSEL_PRSCH4 (0x00000004UL << 0) /**< Shifted mode PRSCH4 for UART_TRIGCTRL */\r
+#define UART_TRIGCTRL_TSEL_PRSCH5 (0x00000005UL << 0) /**< Shifted mode PRSCH5 for UART_TRIGCTRL */\r
+#define UART_TRIGCTRL_TSEL_PRSCH6 (0x00000006UL << 0) /**< Shifted mode PRSCH6 for UART_TRIGCTRL */\r
+#define UART_TRIGCTRL_TSEL_PRSCH7 (0x00000007UL << 0) /**< Shifted mode PRSCH7 for UART_TRIGCTRL */\r
+#define _UART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */\r
+#define _UART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_TRIGCTRL */\r
+#define _UART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_TRIGCTRL */\r
+#define _UART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_TRIGCTRL */\r
+#define _UART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_TRIGCTRL */\r
+#define _UART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_TRIGCTRL */\r
+#define _UART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_TRIGCTRL */\r
+#define _UART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_TRIGCTRL */\r
+#define _UART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_TRIGCTRL */\r
+#define UART_TRIGCTRL_RXTEN (1 << 4) /**< Receive Trigger Enable */\r
+#define _UART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */\r
+#define _UART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */\r
+#define UART_TRIGCTRL_RXTEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_TRIGCTRL */\r
+#define _UART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */\r
+#define UART_TRIGCTRL_TXTEN (1 << 5) /**< Transmit Trigger Enable */\r
+#define _UART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */\r
+#define _UART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */\r
+#define UART_TRIGCTRL_TXTEN_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_TRIGCTRL */\r
+#define _UART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */\r
+\r
+/** Bit fields for UART CMD */\r
+#define _UART_CMD_RESETVALUE 0x00000000UL /**< Default value for UART_CMD */\r
+#define _UART_CMD_MASK 0x00000FFFUL /**< Mask for UART_CMD */\r
+#define UART_CMD_RXEN (1 << 0) /**< Receiver Enable */\r
+#define _UART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */\r
+#define _UART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */\r
+#define UART_CMD_RXEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_CMD */\r
+#define _UART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */\r
+#define UART_CMD_RXDIS (1 << 1) /**< Receiver Disable */\r
+#define _UART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */\r
+#define _UART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */\r
+#define UART_CMD_RXDIS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for UART_CMD */\r
+#define _UART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */\r
+#define UART_CMD_TXEN (1 << 2) /**< Transmitter Enable */\r
+#define _UART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */\r
+#define _UART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */\r
+#define UART_CMD_TXEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for UART_CMD */\r
+#define _UART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */\r
+#define UART_CMD_TXDIS (1 << 3) /**< Transmitter Disable */\r
+#define _UART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */\r
+#define _UART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */\r
+#define UART_CMD_TXDIS_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_CMD */\r
+#define _UART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */\r
+#define UART_CMD_MASTEREN (1 << 4) /**< Master Enable */\r
+#define _UART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */\r
+#define _UART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */\r
+#define UART_CMD_MASTEREN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_CMD */\r
+#define _UART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */\r
+#define UART_CMD_MASTERDIS (1 << 5) /**< Master Disable */\r
+#define _UART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */\r
+#define _UART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */\r
+#define UART_CMD_MASTERDIS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_CMD */\r
+#define _UART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */\r
+#define UART_CMD_RXBLOCKEN (1 << 6) /**< Receiver Block Enable */\r
+#define _UART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */\r
+#define _UART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */\r
+#define UART_CMD_RXBLOCKEN_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for UART_CMD */\r
+#define _UART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */\r
+#define UART_CMD_RXBLOCKDIS (1 << 7) /**< Receiver Block Disable */\r
+#define _UART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */\r
+#define _UART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */\r
+#define UART_CMD_RXBLOCKDIS_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for UART_CMD */\r
+#define _UART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */\r
+#define UART_CMD_TXTRIEN (1 << 8) /**< Transmitter Tristate Enable */\r
+#define _UART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */\r
+#define _UART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */\r
+#define UART_CMD_TXTRIEN_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_CMD */\r
+#define _UART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */\r
+#define UART_CMD_TXTRIDIS (1 << 9) /**< Transmitter Tristate Disable */\r
+#define _UART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */\r
+#define _UART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */\r
+#define UART_CMD_TXTRIDIS_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for UART_CMD */\r
+#define _UART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */\r
+#define UART_CMD_CLEARTX (1 << 10) /**< Clear TX */\r
+#define _UART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */\r
+#define _UART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */\r
+#define UART_CMD_CLEARTX_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for UART_CMD */\r
+#define _UART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */\r
+#define UART_CMD_CLEARRX (1 << 11) /**< Clear RX */\r
+#define _UART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */\r
+#define _UART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */\r
+#define UART_CMD_CLEARRX_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_CMD */\r
+#define _UART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */\r
+\r
+/** Bit fields for UART STATUS */\r
+#define _UART_STATUS_RESETVALUE 0x00000040UL /**< Default value for UART_STATUS */\r
+#define _UART_STATUS_MASK 0x000001FFUL /**< Mask for UART_STATUS */\r
+#define UART_STATUS_RXENS (1 << 0) /**< Receiver Enable Status */\r
+#define _UART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */\r
+#define _UART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */\r
+#define UART_STATUS_RXENS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_STATUS */\r
+#define _UART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */\r
+#define UART_STATUS_TXENS (1 << 1) /**< Transmitter Enable Status */\r
+#define _UART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */\r
+#define _UART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */\r
+#define UART_STATUS_TXENS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for UART_STATUS */\r
+#define _UART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */\r
+#define UART_STATUS_MASTER (1 << 2) /**< SPI Master Mode */\r
+#define _UART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */\r
+#define _UART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */\r
+#define UART_STATUS_MASTER_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for UART_STATUS */\r
+#define _UART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */\r
+#define UART_STATUS_RXBLOCK (1 << 3) /**< Block Incoming Data */\r
+#define _UART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */\r
+#define _UART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */\r
+#define UART_STATUS_RXBLOCK_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_STATUS */\r
+#define _UART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */\r
+#define UART_STATUS_TXTRI (1 << 4) /**< Transmitter Tristated */\r
+#define _UART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */\r
+#define _UART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */\r
+#define UART_STATUS_TXTRI_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_STATUS */\r
+#define _UART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */\r
+#define UART_STATUS_TXC (1 << 5) /**< TX Complete */\r
+#define _UART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */\r
+#define _UART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */\r
+#define UART_STATUS_TXC_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_STATUS */\r
+#define _UART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */\r
+#define UART_STATUS_TXBL (1 << 6) /**< TX Buffer Level */\r
+#define _UART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */\r
+#define _UART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */\r
+#define UART_STATUS_TXBL_DEFAULT (0x00000001UL << 6) /**< Shifted mode DEFAULT for UART_STATUS */\r
+#define _UART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_STATUS */\r
+#define UART_STATUS_RXDATAV (1 << 7) /**< RX Data Valid */\r
+#define _UART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */\r
+#define _UART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */\r
+#define UART_STATUS_RXDATAV_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for UART_STATUS */\r
+#define _UART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */\r
+#define UART_STATUS_RXFULL (1 << 8) /**< RX FIFO Full */\r
+#define _UART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */\r
+#define _UART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */\r
+#define UART_STATUS_RXFULL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_STATUS */\r
+#define _UART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */\r
+\r
+/** Bit fields for UART CLKDIV */\r
+#define _UART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for UART_CLKDIV */\r
+#define _UART_CLKDIV_MASK 0x001FFFC0UL /**< Mask for UART_CLKDIV */\r
+#define _UART_CLKDIV_DIV_SHIFT 6 /**< Shift value for USART_DIV */\r
+#define _UART_CLKDIV_DIV_MASK 0x1FFFC0UL /**< Bit mask for USART_DIV */\r
+#define UART_CLKDIV_DIV_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for UART_CLKDIV */\r
+#define _UART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CLKDIV */\r
+\r
+/** Bit fields for UART RXDATAX */\r
+#define _UART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAX */\r
+#define _UART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAX */\r
+#define _UART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */\r
+#define _UART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */\r
+#define UART_RXDATAX_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_RXDATAX */\r
+#define _UART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */\r
+#define UART_RXDATAX_PERR (1 << 14) /**< Data Parity Error */\r
+#define _UART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */\r
+#define _UART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */\r
+#define UART_RXDATAX_PERR_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for UART_RXDATAX */\r
+#define _UART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */\r
+#define UART_RXDATAX_FERR (1 << 15) /**< Data Framing Error */\r
+#define _UART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */\r
+#define _UART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */\r
+#define UART_RXDATAX_FERR_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for UART_RXDATAX */\r
+#define _UART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */\r
+\r
+/** Bit fields for UART RXDATA */\r
+#define _UART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATA */\r
+#define _UART_RXDATA_MASK 0x000000FFUL /**< Mask for UART_RXDATA */\r
+#define _UART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */\r
+#define _UART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */\r
+#define UART_RXDATA_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_RXDATA */\r
+#define _UART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATA */\r
+\r
+/** Bit fields for UART RXDOUBLEX */\r
+#define _UART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEX */\r
+#define _UART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEX */\r
+#define _UART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */\r
+#define _UART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */\r
+#define UART_RXDOUBLEX_RXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */\r
+#define _UART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */\r
+#define UART_RXDOUBLEX_PERR0 (1 << 14) /**< Data Parity Error 0 */\r
+#define _UART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */\r
+#define _UART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */\r
+#define UART_RXDOUBLEX_PERR0_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */\r
+#define _UART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */\r
+#define UART_RXDOUBLEX_FERR0 (1 << 15) /**< Data Framing Error 0 */\r
+#define _UART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */\r
+#define _UART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */\r
+#define UART_RXDOUBLEX_FERR0_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */\r
+#define _UART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */\r
+#define _UART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */\r
+#define _UART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */\r
+#define UART_RXDOUBLEX_RXDATA1_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */\r
+#define _UART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */\r
+#define UART_RXDOUBLEX_PERR1 (1 << 30) /**< Data Parity Error 1 */\r
+#define _UART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */\r
+#define _UART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */\r
+#define UART_RXDOUBLEX_PERR1_DEFAULT (0x00000000UL << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */\r
+#define _UART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */\r
+#define UART_RXDOUBLEX_FERR1 (1 << 31) /**< Data Framing Error 1 */\r
+#define _UART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */\r
+#define _UART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */\r
+#define UART_RXDOUBLEX_FERR1_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */\r
+#define _UART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */\r
+\r
+/** Bit fields for UART RXDOUBLE */\r
+#define _UART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLE */\r
+#define _UART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_RXDOUBLE */\r
+#define _UART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */\r
+#define _UART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */\r
+#define UART_RXDOUBLE_RXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLE */\r
+#define _UART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */\r
+#define _UART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */\r
+#define _UART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */\r
+#define UART_RXDOUBLE_RXDATA1_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_RXDOUBLE */\r
+#define _UART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */\r
+\r
+/** Bit fields for UART RXDATAXP */\r
+#define _UART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAXP */\r
+#define _UART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAXP */\r
+#define _UART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */\r
+#define _UART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */\r
+#define UART_RXDATAXP_RXDATAP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_RXDATAXP */\r
+#define _UART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */\r
+#define UART_RXDATAXP_PERRP (1 << 14) /**< Data Parity Error Peek */\r
+#define _UART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */\r
+#define _UART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */\r
+#define UART_RXDATAXP_PERRP_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for UART_RXDATAXP */\r
+#define _UART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */\r
+#define UART_RXDATAXP_FERRP (1 << 15) /**< Data Framing Error Peek */\r
+#define _UART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */\r
+#define _UART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */\r
+#define UART_RXDATAXP_FERRP_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for UART_RXDATAXP */\r
+#define _UART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */\r
+\r
+/** Bit fields for UART RXDOUBLEXP */\r
+#define _UART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEXP */\r
+#define _UART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEXP */\r
+#define _UART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */\r
+#define _UART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */\r
+#define UART_RXDOUBLEXP_RXDATAP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */\r
+#define _UART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */\r
+#define UART_RXDOUBLEXP_PERRP0 (1 << 14) /**< Data Parity Error 0 Peek */\r
+#define _UART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */\r
+#define _UART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */\r
+#define UART_RXDOUBLEXP_PERRP0_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */\r
+#define _UART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */\r
+#define UART_RXDOUBLEXP_FERRP0 (1 << 15) /**< Data Framing Error 0 Peek */\r
+#define _UART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */\r
+#define _UART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */\r
+#define UART_RXDOUBLEXP_FERRP0_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */\r
+#define _UART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */\r
+#define _UART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */\r
+#define _UART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */\r
+#define UART_RXDOUBLEXP_RXDATAP1_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */\r
+#define _UART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */\r
+#define UART_RXDOUBLEXP_PERRP1 (1 << 30) /**< Data Parity Error 1 Peek */\r
+#define _UART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */\r
+#define _UART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */\r
+#define UART_RXDOUBLEXP_PERRP1_DEFAULT (0x00000000UL << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */\r
+#define _UART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */\r
+#define UART_RXDOUBLEXP_FERRP1 (1 << 31) /**< Data Framing Error 1 Peek */\r
+#define _UART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */\r
+#define _UART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */\r
+#define UART_RXDOUBLEXP_FERRP1_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */\r
+#define _UART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */\r
+\r
+/** Bit fields for UART TXDATAX */\r
+#define _UART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATAX */\r
+#define _UART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for UART_TXDATAX */\r
+#define _UART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */\r
+#define _UART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */\r
+#define UART_TXDATAX_TXDATAX_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_TXDATAX */\r
+#define _UART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */\r
+#define UART_TXDATAX_UBRXAT (1 << 11) /**< Unblock RX After Transmission */\r
+#define _UART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */\r
+#define _UART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */\r
+#define UART_TXDATAX_UBRXAT_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_TXDATAX */\r
+#define _UART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */\r
+#define UART_TXDATAX_TXTRIAT (1 << 12) /**< Set TXTRI After Transmission */\r
+#define _UART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */\r
+#define _UART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */\r
+#define UART_TXDATAX_TXTRIAT_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for UART_TXDATAX */\r
+#define _UART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */\r
+#define UART_TXDATAX_TXBREAK (1 << 13) /**< Transmit Data As Break */\r
+#define _UART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */\r
+#define _UART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */\r
+#define UART_TXDATAX_TXBREAK_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for UART_TXDATAX */\r
+#define _UART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */\r
+#define UART_TXDATAX_TXDISAT (1 << 14) /**< Clear TXEN After Transmission */\r
+#define _UART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */\r
+#define _UART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */\r
+#define UART_TXDATAX_TXDISAT_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for UART_TXDATAX */\r
+#define _UART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */\r
+#define UART_TXDATAX_RXENAT (1 << 15) /**< Enable RX After Transmission */\r
+#define _UART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */\r
+#define _UART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */\r
+#define UART_TXDATAX_RXENAT_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for UART_TXDATAX */\r
+#define _UART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */\r
+\r
+/** Bit fields for UART TXDATA */\r
+#define _UART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATA */\r
+#define _UART_TXDATA_MASK 0x000000FFUL /**< Mask for UART_TXDATA */\r
+#define _UART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */\r
+#define _UART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */\r
+#define UART_TXDATA_TXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_TXDATA */\r
+#define _UART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATA */\r
+\r
+/** Bit fields for UART TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for UART_TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */\r
+#define _UART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */\r
+#define UART_TXDOUBLEX_TXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */\r
+#define UART_TXDOUBLEX_UBRXAT0 (1 << 11) /**< Unblock RX After Transmission */\r
+#define _UART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */\r
+#define _UART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */\r
+#define UART_TXDOUBLEX_UBRXAT0_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */\r
+#define UART_TXDOUBLEX_TXTRIAT0 (1 << 12) /**< Set TXTRI After Transmission */\r
+#define _UART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */\r
+#define _UART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */\r
+#define UART_TXDOUBLEX_TXTRIAT0_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */\r
+#define UART_TXDOUBLEX_TXBREAK0 (1 << 13) /**< Transmit Data As Break */\r
+#define _UART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */\r
+#define _UART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */\r
+#define UART_TXDOUBLEX_TXBREAK0_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */\r
+#define UART_TXDOUBLEX_TXDISAT0 (1 << 14) /**< Clear TXEN After Transmission */\r
+#define _UART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */\r
+#define _UART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */\r
+#define UART_TXDOUBLEX_TXDISAT0_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */\r
+#define UART_TXDOUBLEX_RXENAT0 (1 << 15) /**< Enable RX After Transmission */\r
+#define _UART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */\r
+#define _UART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */\r
+#define UART_TXDOUBLEX_RXENAT0_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */\r
+#define _UART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */\r
+#define UART_TXDOUBLEX_TXDATA1_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */\r
+#define UART_TXDOUBLEX_UBRXAT1 (1 << 27) /**< Unblock RX After Transmission */\r
+#define _UART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */\r
+#define _UART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */\r
+#define UART_TXDOUBLEX_UBRXAT1_DEFAULT (0x00000000UL << 27) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */\r
+#define UART_TXDOUBLEX_TXTRIAT1 (1 << 28) /**< Set TXTRI After Transmission */\r
+#define _UART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */\r
+#define _UART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */\r
+#define UART_TXDOUBLEX_TXTRIAT1_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */\r
+#define UART_TXDOUBLEX_TXBREAK1 (1 << 29) /**< Transmit Data As Break */\r
+#define _UART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */\r
+#define _UART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */\r
+#define UART_TXDOUBLEX_TXBREAK1_DEFAULT (0x00000000UL << 29) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */\r
+#define UART_TXDOUBLEX_TXDISAT1 (1 << 30) /**< Clear TXEN After Transmission */\r
+#define _UART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */\r
+#define _UART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */\r
+#define UART_TXDOUBLEX_TXDISAT1_DEFAULT (0x00000000UL << 30) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */\r
+#define UART_TXDOUBLEX_RXENAT1 (1 << 31) /**< Enable RX After Transmission */\r
+#define _UART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */\r
+#define _UART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */\r
+#define UART_TXDOUBLEX_RXENAT1_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */\r
+#define _UART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */\r
+\r
+/** Bit fields for UART TXDOUBLE */\r
+#define _UART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLE */\r
+#define _UART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_TXDOUBLE */\r
+#define _UART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */\r
+#define _UART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */\r
+#define UART_TXDOUBLE_TXDATA0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLE */\r
+#define _UART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */\r
+#define _UART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */\r
+#define _UART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */\r
+#define UART_TXDOUBLE_TXDATA1_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_TXDOUBLE */\r
+#define _UART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */\r
+\r
+/** Bit fields for UART IF */\r
+#define _UART_IF_RESETVALUE 0x00000002UL /**< Default value for UART_IF */\r
+#define _UART_IF_MASK 0x00001FFFUL /**< Mask for UART_IF */\r
+#define UART_IF_TXC (1 << 0) /**< TX Complete Interrupt Flag */\r
+#define _UART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */\r
+#define _UART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */\r
+#define UART_IF_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_IF */\r
+#define _UART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */\r
+#define UART_IF_TXBL (1 << 1) /**< TX Buffer Level Interrupt Flag */\r
+#define _UART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */\r
+#define _UART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */\r
+#define UART_IF_TXBL_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for UART_IF */\r
+#define _UART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_IF */\r
+#define UART_IF_RXDATAV (1 << 2) /**< RX Data Valid Interrupt Flag */\r
+#define _UART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */\r
+#define _UART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */\r
+#define UART_IF_RXDATAV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for UART_IF */\r
+#define _UART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */\r
+#define UART_IF_RXFULL (1 << 3) /**< RX Buffer Full Interrupt Flag */\r
+#define _UART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */\r
+#define _UART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */\r
+#define UART_IF_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_IF */\r
+#define _UART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */\r
+#define UART_IF_RXOF (1 << 4) /**< RX Overflow Interrupt Flag */\r
+#define _UART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */\r
+#define _UART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */\r
+#define UART_IF_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_IF */\r
+#define _UART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */\r
+#define UART_IF_RXUF (1 << 5) /**< RX Underflow Interrupt Flag */\r
+#define _UART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */\r
+#define _UART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */\r
+#define UART_IF_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_IF */\r
+#define _UART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */\r
+#define UART_IF_TXOF (1 << 6) /**< TX Overflow Interrupt Flag */\r
+#define _UART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */\r
+#define _UART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */\r
+#define UART_IF_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for UART_IF */\r
+#define _UART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */\r
+#define UART_IF_TXUF (1 << 7) /**< TX Underflow Interrupt Flag */\r
+#define _UART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */\r
+#define _UART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */\r
+#define UART_IF_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for UART_IF */\r
+#define _UART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */\r
+#define UART_IF_PERR (1 << 8) /**< Parity Error Interrupt Flag */\r
+#define _UART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */\r
+#define _UART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */\r
+#define UART_IF_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_IF */\r
+#define _UART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */\r
+#define UART_IF_FERR (1 << 9) /**< Framing Error Interrupt Flag */\r
+#define _UART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */\r
+#define _UART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */\r
+#define UART_IF_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for UART_IF */\r
+#define _UART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */\r
+#define UART_IF_MPAF (1 << 10) /**< Multi-Processor Address Frame Interrupt Flag */\r
+#define _UART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */\r
+#define _UART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */\r
+#define UART_IF_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for UART_IF */\r
+#define _UART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */\r
+#define UART_IF_SSM (1 << 11) /**< Slave-Select In Master Mode Interrupt Flag */\r
+#define _UART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */\r
+#define _UART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */\r
+#define UART_IF_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_IF */\r
+#define _UART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */\r
+#define UART_IF_CCF (1 << 12) /**< Collision Check Fail Interrupt Flag */\r
+#define _UART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */\r
+#define _UART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */\r
+#define UART_IF_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for UART_IF */\r
+#define _UART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */\r
+\r
+/** Bit fields for UART IFS */\r
+#define _UART_IFS_RESETVALUE 0x00000000UL /**< Default value for UART_IFS */\r
+#define _UART_IFS_MASK 0x00001FF9UL /**< Mask for UART_IFS */\r
+#define UART_IFS_TXC (1 << 0) /**< Set TX Complete Interrupt Flag */\r
+#define _UART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */\r
+#define _UART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */\r
+#define UART_IFS_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_IFS */\r
+#define _UART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */\r
+#define UART_IFS_RXFULL (1 << 3) /**< Set RX Buffer Full Interrupt Flag */\r
+#define _UART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */\r
+#define _UART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */\r
+#define UART_IFS_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_IFS */\r
+#define _UART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */\r
+#define UART_IFS_RXOF (1 << 4) /**< Set RX Overflow Interrupt Flag */\r
+#define _UART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */\r
+#define _UART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */\r
+#define UART_IFS_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_IFS */\r
+#define _UART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */\r
+#define UART_IFS_RXUF (1 << 5) /**< Set RX Underflow Interrupt Flag */\r
+#define _UART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */\r
+#define _UART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */\r
+#define UART_IFS_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_IFS */\r
+#define _UART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */\r
+#define UART_IFS_TXOF (1 << 6) /**< Set TX Overflow Interrupt Flag */\r
+#define _UART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */\r
+#define _UART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */\r
+#define UART_IFS_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for UART_IFS */\r
+#define _UART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */\r
+#define UART_IFS_TXUF (1 << 7) /**< Set TX Underflow Interrupt Flag */\r
+#define _UART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */\r
+#define _UART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */\r
+#define UART_IFS_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for UART_IFS */\r
+#define _UART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */\r
+#define UART_IFS_PERR (1 << 8) /**< Set Parity Error Interrupt Flag */\r
+#define _UART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */\r
+#define _UART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */\r
+#define UART_IFS_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_IFS */\r
+#define _UART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */\r
+#define UART_IFS_FERR (1 << 9) /**< Set Framing Error Interrupt Flag */\r
+#define _UART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */\r
+#define _UART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */\r
+#define UART_IFS_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for UART_IFS */\r
+#define _UART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */\r
+#define UART_IFS_MPAF (1 << 10) /**< Set Multi-Processor Address Frame Interrupt Flag */\r
+#define _UART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */\r
+#define _UART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */\r
+#define UART_IFS_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for UART_IFS */\r
+#define _UART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */\r
+#define UART_IFS_SSM (1 << 11) /**< Set Slave-Select in Master mode Interrupt Flag */\r
+#define _UART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */\r
+#define _UART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */\r
+#define UART_IFS_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_IFS */\r
+#define _UART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */\r
+#define UART_IFS_CCF (1 << 12) /**< Set Collision Check Fail Interrupt Flag */\r
+#define _UART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */\r
+#define _UART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */\r
+#define UART_IFS_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for UART_IFS */\r
+#define _UART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */\r
+\r
+/** Bit fields for UART IFC */\r
+#define _UART_IFC_RESETVALUE 0x00000000UL /**< Default value for UART_IFC */\r
+#define _UART_IFC_MASK 0x00001FF9UL /**< Mask for UART_IFC */\r
+#define UART_IFC_TXC (1 << 0) /**< Clear TX Complete Interrupt Flag */\r
+#define _UART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */\r
+#define _UART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */\r
+#define UART_IFC_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_IFC */\r
+#define _UART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */\r
+#define UART_IFC_RXFULL (1 << 3) /**< Clear RX Buffer Full Interrupt Flag */\r
+#define _UART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */\r
+#define _UART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */\r
+#define UART_IFC_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_IFC */\r
+#define _UART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */\r
+#define UART_IFC_RXOF (1 << 4) /**< Clear RX Overflow Interrupt Flag */\r
+#define _UART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */\r
+#define _UART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */\r
+#define UART_IFC_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_IFC */\r
+#define _UART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */\r
+#define UART_IFC_RXUF (1 << 5) /**< Clear RX Underflow Interrupt Flag */\r
+#define _UART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */\r
+#define _UART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */\r
+#define UART_IFC_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_IFC */\r
+#define _UART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */\r
+#define UART_IFC_TXOF (1 << 6) /**< Clear TX Overflow Interrupt Flag */\r
+#define _UART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */\r
+#define _UART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */\r
+#define UART_IFC_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for UART_IFC */\r
+#define _UART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */\r
+#define UART_IFC_TXUF (1 << 7) /**< Clear TX Underflow Interrupt Flag */\r
+#define _UART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */\r
+#define _UART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */\r
+#define UART_IFC_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for UART_IFC */\r
+#define _UART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */\r
+#define UART_IFC_PERR (1 << 8) /**< Clear Parity Error Interrupt Flag */\r
+#define _UART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */\r
+#define _UART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */\r
+#define UART_IFC_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_IFC */\r
+#define _UART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */\r
+#define UART_IFC_FERR (1 << 9) /**< Clear Framing Error Interrupt Flag */\r
+#define _UART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */\r
+#define _UART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */\r
+#define UART_IFC_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for UART_IFC */\r
+#define _UART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */\r
+#define UART_IFC_MPAF (1 << 10) /**< Clear Multi-Processor Address Frame Interrupt Flag */\r
+#define _UART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */\r
+#define _UART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */\r
+#define UART_IFC_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for UART_IFC */\r
+#define _UART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */\r
+#define UART_IFC_SSM (1 << 11) /**< Clear Slave-Select In Master Mode Interrupt Flag */\r
+#define _UART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */\r
+#define _UART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */\r
+#define UART_IFC_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_IFC */\r
+#define _UART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */\r
+#define UART_IFC_CCF (1 << 12) /**< Clear Collision Check Fail Interrupt Flag */\r
+#define _UART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */\r
+#define _UART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */\r
+#define UART_IFC_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for UART_IFC */\r
+#define _UART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */\r
+\r
+/** Bit fields for UART IEN */\r
+#define _UART_IEN_RESETVALUE 0x00000000UL /**< Default value for UART_IEN */\r
+#define _UART_IEN_MASK 0x00001FFFUL /**< Mask for UART_IEN */\r
+#define UART_IEN_TXC (1 << 0) /**< TX Complete Interrupt Enable */\r
+#define _UART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */\r
+#define _UART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */\r
+#define UART_IEN_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_IEN */\r
+#define _UART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */\r
+#define UART_IEN_TXBL (1 << 1) /**< TX Buffer Level Interrupt Enable */\r
+#define _UART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */\r
+#define _UART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */\r
+#define UART_IEN_TXBL_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for UART_IEN */\r
+#define _UART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */\r
+#define UART_IEN_RXDATAV (1 << 2) /**< RX Data Valid Interrupt Enable */\r
+#define _UART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */\r
+#define _UART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */\r
+#define UART_IEN_RXDATAV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for UART_IEN */\r
+#define _UART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */\r
+#define UART_IEN_RXFULL (1 << 3) /**< RX Buffer Full Interrupt Enable */\r
+#define _UART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */\r
+#define _UART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */\r
+#define UART_IEN_RXFULL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_IEN */\r
+#define _UART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */\r
+#define UART_IEN_RXOF (1 << 4) /**< RX Overflow Interrupt Enable */\r
+#define _UART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */\r
+#define _UART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */\r
+#define UART_IEN_RXOF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_IEN */\r
+#define _UART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */\r
+#define UART_IEN_RXUF (1 << 5) /**< RX Underflow Interrupt Enable */\r
+#define _UART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */\r
+#define _UART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */\r
+#define UART_IEN_RXUF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for UART_IEN */\r
+#define _UART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */\r
+#define UART_IEN_TXOF (1 << 6) /**< TX Overflow Interrupt Enable */\r
+#define _UART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */\r
+#define _UART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */\r
+#define UART_IEN_TXOF_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for UART_IEN */\r
+#define _UART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */\r
+#define UART_IEN_TXUF (1 << 7) /**< TX Underflow Interrupt Enable */\r
+#define _UART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */\r
+#define _UART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */\r
+#define UART_IEN_TXUF_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for UART_IEN */\r
+#define _UART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */\r
+#define UART_IEN_PERR (1 << 8) /**< Parity Error Interrupt Enable */\r
+#define _UART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */\r
+#define _UART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */\r
+#define UART_IEN_PERR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_IEN */\r
+#define _UART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */\r
+#define UART_IEN_FERR (1 << 9) /**< Framing Error Interrupt Enable */\r
+#define _UART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */\r
+#define _UART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */\r
+#define UART_IEN_FERR_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for UART_IEN */\r
+#define _UART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */\r
+#define UART_IEN_MPAF (1 << 10) /**< Multi-Processor Address Frame Interrupt Enable */\r
+#define _UART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */\r
+#define _UART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */\r
+#define UART_IEN_MPAF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for UART_IEN */\r
+#define _UART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */\r
+#define UART_IEN_SSM (1 << 11) /**< Slave-Select In Master Mode Interrupt Enable */\r
+#define _UART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */\r
+#define _UART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */\r
+#define UART_IEN_SSM_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for UART_IEN */\r
+#define _UART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */\r
+#define UART_IEN_CCF (1 << 12) /**< Collision Check Fail Interrupt Enable */\r
+#define _UART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */\r
+#define _UART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */\r
+#define UART_IEN_CCF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for UART_IEN */\r
+#define _UART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */\r
+\r
+/** Bit fields for UART IRCTRL */\r
+#define _UART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_IRCTRL */\r
+#define _UART_IRCTRL_MASK 0x000000FFUL /**< Mask for UART_IRCTRL */\r
+#define UART_IRCTRL_IREN (1 << 0) /**< Enable IrDA Module */\r
+#define _UART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */\r
+#define _UART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */\r
+#define UART_IRCTRL_IREN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_IRCTRL */\r
+#define _UART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */\r
+#define _UART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */\r
+#define UART_IRCTRL_IRPW_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for UART_IRCTRL */\r
+#define UART_IRCTRL_IRPW_ONE (0x00000000UL << 1) /**< Shifted mode ONE for UART_IRCTRL */\r
+#define UART_IRCTRL_IRPW_TWO (0x00000001UL << 1) /**< Shifted mode TWO for UART_IRCTRL */\r
+#define UART_IRCTRL_IRPW_THREE (0x00000002UL << 1) /**< Shifted mode THREE for UART_IRCTRL */\r
+#define UART_IRCTRL_IRPW_FOUR (0x00000003UL << 1) /**< Shifted mode FOUR for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for UART_IRCTRL */\r
+#define UART_IRCTRL_IRFILT (1 << 3) /**< IrDA RX Filter */\r
+#define _UART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */\r
+#define _UART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */\r
+#define UART_IRCTRL_IRFILT_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPRSSEL_SHIFT 4 /**< Shift value for USART_IRPRSSEL */\r
+#define _UART_IRCTRL_IRPRSSEL_MASK 0x70UL /**< Bit mask for USART_IRPRSSEL */\r
+#define UART_IRCTRL_IRPRSSEL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for UART_IRCTRL */\r
+#define UART_IRCTRL_IRPRSSEL_PRSCH0 (0x00000000UL << 4) /**< Shifted mode PRSCH0 for UART_IRCTRL */\r
+#define UART_IRCTRL_IRPRSSEL_PRSCH1 (0x00000001UL << 4) /**< Shifted mode PRSCH1 for UART_IRCTRL */\r
+#define UART_IRCTRL_IRPRSSEL_PRSCH2 (0x00000002UL << 4) /**< Shifted mode PRSCH2 for UART_IRCTRL */\r
+#define UART_IRCTRL_IRPRSSEL_PRSCH3 (0x00000003UL << 4) /**< Shifted mode PRSCH3 for UART_IRCTRL */\r
+#define UART_IRCTRL_IRPRSSEL_PRSCH4 (0x00000004UL << 4) /**< Shifted mode PRSCH4 for UART_IRCTRL */\r
+#define UART_IRCTRL_IRPRSSEL_PRSCH5 (0x00000005UL << 4) /**< Shifted mode PRSCH5 for UART_IRCTRL */\r
+#define UART_IRCTRL_IRPRSSEL_PRSCH6 (0x00000006UL << 4) /**< Shifted mode PRSCH6 for UART_IRCTRL */\r
+#define UART_IRCTRL_IRPRSSEL_PRSCH7 (0x00000007UL << 4) /**< Shifted mode PRSCH7 for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_IRCTRL */\r
+#define UART_IRCTRL_IRPRSEN (1 << 7) /**< IrDA PRS Channel Enable */\r
+#define _UART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */\r
+#define _UART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */\r
+#define UART_IRCTRL_IRPRSEN_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for UART_IRCTRL */\r
+#define _UART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */\r
+\r
+/** Bit fields for UART ROUTE */\r
+#define _UART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for UART_ROUTE */\r
+#define _UART_ROUTE_MASK 0x0000030FUL /**< Mask for UART_ROUTE */\r
+#define UART_ROUTE_RXPEN (1 << 0) /**< RX Pin Enable */\r
+#define _UART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */\r
+#define _UART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */\r
+#define UART_ROUTE_RXPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for UART_ROUTE */\r
+#define _UART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */\r
+#define UART_ROUTE_TXPEN (1 << 1) /**< TX Pin Enable */\r
+#define _UART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */\r
+#define _UART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */\r
+#define UART_ROUTE_TXPEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for UART_ROUTE */\r
+#define _UART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */\r
+#define UART_ROUTE_CSPEN (1 << 2) /**< CS Pin Enable */\r
+#define _UART_ROUTE_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */\r
+#define _UART_ROUTE_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */\r
+#define UART_ROUTE_CSPEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for UART_ROUTE */\r
+#define _UART_ROUTE_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */\r
+#define UART_ROUTE_CLKPEN (1 << 3) /**< RX Pin Enable */\r
+#define _UART_ROUTE_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */\r
+#define _UART_ROUTE_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */\r
+#define UART_ROUTE_CLKPEN_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for UART_ROUTE */\r
+#define _UART_ROUTE_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */\r
+#define _UART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for USART_LOCATION */\r
+#define _UART_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for USART_LOCATION */\r
+#define UART_ROUTE_LOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for UART_ROUTE */\r
+#define UART_ROUTE_LOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for UART_ROUTE */\r
+#define UART_ROUTE_LOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for UART_ROUTE */\r
+#define UART_ROUTE_LOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for UART_ROUTE */\r
+#define UART_ROUTE_LOCATION_LOC3 (0x00000003UL << 8) /**< Shifted mode LOC3 for UART_ROUTE */\r
+#define _UART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */\r
+#define _UART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTE */\r
+#define _UART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTE */\r
+#define _UART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTE */\r
+#define _UART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_LEUART\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for LEUART CTRL */\r
+#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */\r
+#define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */\r
+#define LEUART_CTRL_AUTOTRI (1 << 0) /**< Automatic Transmitter Tristate */\r
+#define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */\r
+#define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */\r
+#define LEUART_CTRL_AUTOTRI_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_DATABITS (1 << 1) /**< Data-Bit Mode */\r
+#define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */\r
+#define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */\r
+#define LEUART_CTRL_DATABITS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_DATABITS_EIGHT (0x00000000UL << 1) /**< Shifted mode EIGHT for LEUART_CTRL */\r
+#define LEUART_CTRL_DATABITS_NINE (0x00000001UL << 1) /**< Shifted mode NINE for LEUART_CTRL */\r
+#define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */\r
+#define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */\r
+#define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */\r
+#define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */\r
+#define LEUART_CTRL_PARITY_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_PARITY_NONE (0x00000000UL << 2) /**< Shifted mode NONE for LEUART_CTRL */\r
+#define LEUART_CTRL_PARITY_EVEN (0x00000002UL << 2) /**< Shifted mode EVEN for LEUART_CTRL */\r
+#define LEUART_CTRL_PARITY_ODD (0x00000003UL << 2) /**< Shifted mode ODD for LEUART_CTRL */\r
+#define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */\r
+#define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */\r
+#define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */\r
+#define LEUART_CTRL_STOPBITS (1 << 4) /**< Stop-Bit Mode */\r
+#define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */\r
+#define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */\r
+#define LEUART_CTRL_STOPBITS_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_STOPBITS_ONE (0x00000000UL << 4) /**< Shifted mode ONE for LEUART_CTRL */\r
+#define LEUART_CTRL_STOPBITS_TWO (0x00000001UL << 4) /**< Shifted mode TWO for LEUART_CTRL */\r
+#define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */\r
+#define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */\r
+#define LEUART_CTRL_INV (1 << 5) /**< Invert Input And Output */\r
+#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */\r
+#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */\r
+#define LEUART_CTRL_INV_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_ERRSDMA (1 << 6) /**< Halt RX DMA On Error */\r
+#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */\r
+#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */\r
+#define LEUART_CTRL_ERRSDMA_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_LOOPBK (1 << 7) /**< Loopback Enable */\r
+#define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */\r
+#define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */\r
+#define LEUART_CTRL_LOOPBK_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_SFUBRX (1 << 8) /**< Start-Frame UnBlock RX */\r
+#define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */\r
+#define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */\r
+#define LEUART_CTRL_SFUBRX_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_MPM (1 << 9) /**< Multi-Processor Mode */\r
+#define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */\r
+#define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */\r
+#define LEUART_CTRL_MPM_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_MPAB (1 << 10) /**< Multi-Processor Address-Bit */\r
+#define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */\r
+#define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */\r
+#define LEUART_CTRL_MPAB_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_BIT8DV (1 << 11) /**< Bit 8 Default Value */\r
+#define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */\r
+#define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */\r
+#define LEUART_CTRL_BIT8DV_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_RXDMAWU (1 << 12) /**< RX DMA Wakeup */\r
+#define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */\r
+#define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */\r
+#define LEUART_CTRL_RXDMAWU_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_TXDMAWU (1 << 13) /**< TX DMA Wakeup */\r
+#define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */\r
+#define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */\r
+#define LEUART_CTRL_TXDMAWU_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */\r
+#define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */\r
+#define LEUART_CTRL_TXDELAY_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */\r
+#define LEUART_CTRL_TXDELAY_NONE (0x00000000UL << 14) /**< Shifted mode NONE for LEUART_CTRL */\r
+#define LEUART_CTRL_TXDELAY_SINGLE (0x00000001UL << 14) /**< Shifted mode SINGLE for LEUART_CTRL */\r
+#define LEUART_CTRL_TXDELAY_DOUBLE (0x00000002UL << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */\r
+#define LEUART_CTRL_TXDELAY_TRIPLE (0x00000003UL << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */\r
+#define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */\r
+#define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */\r
+#define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */\r
+#define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */\r
+#define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */\r
+\r
+/** Bit fields for LEUART CMD */\r
+#define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */\r
+#define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */\r
+#define LEUART_CMD_RXEN (1 << 0) /**< Receiver Enable */\r
+#define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */\r
+#define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */\r
+#define LEUART_CMD_RXEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+#define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_RXDIS (1 << 1) /**< Receiver Disable */\r
+#define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */\r
+#define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */\r
+#define LEUART_CMD_RXDIS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+#define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_TXEN (1 << 2) /**< Transmitter Enable */\r
+#define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */\r
+#define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */\r
+#define LEUART_CMD_TXEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+#define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_TXDIS (1 << 3) /**< Transmitter Disable */\r
+#define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */\r
+#define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */\r
+#define LEUART_CMD_TXDIS_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+#define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_RXBLOCKEN (1 << 4) /**< Receiver Block Enable */\r
+#define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */\r
+#define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */\r
+#define LEUART_CMD_RXBLOCKEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+#define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_RXBLOCKDIS (1 << 5) /**< Receiver Block Disable */\r
+#define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */\r
+#define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */\r
+#define LEUART_CMD_RXBLOCKDIS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+#define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_CLEARTX (1 << 6) /**< Clear TX */\r
+#define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */\r
+#define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */\r
+#define LEUART_CMD_CLEARTX_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+#define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+#define LEUART_CMD_CLEARRX (1 << 7) /**< Clear RX */\r
+#define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */\r
+#define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */\r
+#define LEUART_CMD_CLEARRX_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LEUART_CMD */\r
+#define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */\r
+\r
+/** Bit fields for LEUART STATUS */\r
+#define _LEUART_STATUS_RESETVALUE 0x00000010UL /**< Default value for LEUART_STATUS */\r
+#define _LEUART_STATUS_MASK 0x0000003FUL /**< Mask for LEUART_STATUS */\r
+#define LEUART_STATUS_RXENS (1 << 0) /**< Receiver Enable Status */\r
+#define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */\r
+#define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */\r
+#define LEUART_STATUS_RXENS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */\r
+#define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_TXENS (1 << 1) /**< Transmitter Enable Status */\r
+#define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */\r
+#define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */\r
+#define LEUART_STATUS_TXENS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */\r
+#define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_RXBLOCK (1 << 2) /**< Block Incoming Data */\r
+#define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */\r
+#define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */\r
+#define LEUART_STATUS_RXBLOCK_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */\r
+#define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_TXC (1 << 3) /**< TX Complete */\r
+#define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */\r
+#define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */\r
+#define LEUART_STATUS_TXC_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */\r
+#define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_TXBL (1 << 4) /**< TX Buffer Level */\r
+#define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */\r
+#define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */\r
+#define LEUART_STATUS_TXBL_DEFAULT (0x00000001UL << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */\r
+#define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */\r
+#define LEUART_STATUS_RXDATAV (1 << 5) /**< RX Data Valid */\r
+#define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */\r
+#define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */\r
+#define LEUART_STATUS_RXDATAV_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */\r
+#define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */\r
+\r
+/** Bit fields for LEUART CLKDIV */\r
+#define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */\r
+#define _LEUART_CLKDIV_MASK 0x00007FF8UL /**< Mask for LEUART_CLKDIV */\r
+#define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */\r
+#define _LEUART_CLKDIV_DIV_MASK 0x7FF8UL /**< Bit mask for LEUART_DIV */\r
+#define LEUART_CLKDIV_DIV_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */\r
+#define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */\r
+\r
+/** Bit fields for LEUART STARTFRAME */\r
+#define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */\r
+#define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */\r
+#define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */\r
+#define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */\r
+#define LEUART_STARTFRAME_STARTFRAME_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */\r
+#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */\r
+\r
+/** Bit fields for LEUART SIGFRAME */\r
+#define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */\r
+#define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */\r
+#define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */\r
+#define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */\r
+#define LEUART_SIGFRAME_SIGFRAME_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */\r
+#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */\r
+\r
+/** Bit fields for LEUART RXDATAX */\r
+#define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */\r
+#define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */\r
+#define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */\r
+#define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */\r
+#define LEUART_RXDATAX_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */\r
+#define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */\r
+#define LEUART_RXDATAX_PERR (1 << 14) /**< Receive Data Parity Error */\r
+#define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */\r
+#define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */\r
+#define LEUART_RXDATAX_PERR_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */\r
+#define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */\r
+#define LEUART_RXDATAX_FERR (1 << 15) /**< Receive Data Framing Error */\r
+#define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */\r
+#define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */\r
+#define LEUART_RXDATAX_FERR_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */\r
+#define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */\r
+\r
+/** Bit fields for LEUART RXDATA */\r
+#define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */\r
+#define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */\r
+#define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */\r
+#define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */\r
+#define LEUART_RXDATA_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */\r
+#define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */\r
+\r
+/** Bit fields for LEUART RXDATAXP */\r
+#define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */\r
+#define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */\r
+#define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */\r
+#define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */\r
+#define LEUART_RXDATAXP_RXDATAP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */\r
+#define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */\r
+#define LEUART_RXDATAXP_PERRP (1 << 14) /**< Receive Data Parity Error Peek */\r
+#define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */\r
+#define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */\r
+#define LEUART_RXDATAXP_PERRP_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */\r
+#define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */\r
+#define LEUART_RXDATAXP_FERRP (1 << 15) /**< Receive Data Framing Error Peek */\r
+#define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */\r
+#define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */\r
+#define LEUART_RXDATAXP_FERRP_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */\r
+#define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */\r
+\r
+/** Bit fields for LEUART TXDATAX */\r
+#define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */\r
+#define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */\r
+#define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */\r
+#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */\r
+#define LEUART_TXDATAX_TXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */\r
+#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */\r
+#define LEUART_TXDATAX_TXBREAK (1 << 13) /**< Transmit Data As Break */\r
+#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */\r
+#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */\r
+#define LEUART_TXDATAX_TXBREAK_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */\r
+#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */\r
+#define LEUART_TXDATAX_TXDISAT (1 << 14) /**< Disable TX After Transmission */\r
+#define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */\r
+#define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */\r
+#define LEUART_TXDATAX_TXDISAT_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */\r
+#define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */\r
+#define LEUART_TXDATAX_RXENAT (1 << 15) /**< Enable RX After Transmission */\r
+#define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */\r
+#define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */\r
+#define LEUART_TXDATAX_RXENAT_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */\r
+#define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */\r
+\r
+/** Bit fields for LEUART TXDATA */\r
+#define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */\r
+#define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */\r
+#define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */\r
+#define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */\r
+#define LEUART_TXDATA_TXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */\r
+#define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */\r
+\r
+/** Bit fields for LEUART IF */\r
+#define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */\r
+#define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */\r
+#define LEUART_IF_TXC (1 << 0) /**< TX Complete Interrupt Flag */\r
+#define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */\r
+#define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */\r
+#define LEUART_IF_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_TXBL (1 << 1) /**< TX Buffer Level Interrupt Flag */\r
+#define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */\r
+#define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */\r
+#define LEUART_IF_TXBL_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_RXDATAV (1 << 2) /**< RX Data Valid Interrupt Flag */\r
+#define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */\r
+#define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */\r
+#define LEUART_IF_RXDATAV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_RXOF (1 << 3) /**< RX Overflow Interrupt Flag */\r
+#define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */\r
+#define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */\r
+#define LEUART_IF_RXOF_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_RXUF (1 << 4) /**< RX Underflow Interrupt Flag */\r
+#define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */\r
+#define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */\r
+#define LEUART_IF_RXUF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_TXOF (1 << 5) /**< TX Overflow Interrupt Flag */\r
+#define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */\r
+#define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */\r
+#define LEUART_IF_TXOF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_PERR (1 << 6) /**< Parity Error Interrupt Flag */\r
+#define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */\r
+#define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */\r
+#define LEUART_IF_PERR_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_FERR (1 << 7) /**< Framing Error Interrupt Flag */\r
+#define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */\r
+#define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */\r
+#define LEUART_IF_FERR_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_MPAF (1 << 8) /**< Multi-Processor Address Frame Interrupt Flag */\r
+#define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */\r
+#define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */\r
+#define LEUART_IF_MPAF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_STARTF (1 << 9) /**< Start Frame Interrupt Flag */\r
+#define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */\r
+#define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */\r
+#define LEUART_IF_STARTF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+#define LEUART_IF_SIGF (1 << 10) /**< Signal Frame Interrupt Flag */\r
+#define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */\r
+#define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */\r
+#define LEUART_IF_SIGF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for LEUART_IF */\r
+#define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */\r
+\r
+/** Bit fields for LEUART IFS */\r
+#define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */\r
+#define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */\r
+#define LEUART_IFS_TXC (1 << 0) /**< Set TX Complete Interrupt Flag */\r
+#define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */\r
+#define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */\r
+#define LEUART_IFS_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_RXOF (1 << 3) /**< Set RX Overflow Interrupt Flag */\r
+#define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */\r
+#define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */\r
+#define LEUART_IFS_RXOF_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_RXUF (1 << 4) /**< Set RX Underflow Interrupt Flag */\r
+#define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */\r
+#define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */\r
+#define LEUART_IFS_RXUF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_TXOF (1 << 5) /**< Set TX Overflow Interrupt Flag */\r
+#define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */\r
+#define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */\r
+#define LEUART_IFS_TXOF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_PERR (1 << 6) /**< Set Parity Error Interrupt Flag */\r
+#define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */\r
+#define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */\r
+#define LEUART_IFS_PERR_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_FERR (1 << 7) /**< Set Framing Error Interrupt Flag */\r
+#define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */\r
+#define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */\r
+#define LEUART_IFS_FERR_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_MPAF (1 << 8) /**< Set Multi-Processor Address Frame Interrupt Flag */\r
+#define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */\r
+#define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */\r
+#define LEUART_IFS_MPAF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_STARTF (1 << 9) /**< Set Start Frame Interrupt Flag */\r
+#define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */\r
+#define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */\r
+#define LEUART_IFS_STARTF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+#define LEUART_IFS_SIGF (1 << 10) /**< Set Signal Frame Interrupt Flag */\r
+#define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */\r
+#define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */\r
+#define LEUART_IFS_SIGF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for LEUART_IFS */\r
+#define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */\r
+\r
+/** Bit fields for LEUART IFC */\r
+#define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */\r
+#define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */\r
+#define LEUART_IFC_TXC (1 << 0) /**< Clear TX Complete Interrupt Flag */\r
+#define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */\r
+#define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */\r
+#define LEUART_IFC_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_RXOF (1 << 3) /**< Clear RX Overflow Interrupt Flag */\r
+#define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */\r
+#define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */\r
+#define LEUART_IFC_RXOF_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_RXUF (1 << 4) /**< Clear RX Underflow Interrupt Flag */\r
+#define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */\r
+#define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */\r
+#define LEUART_IFC_RXUF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_TXOF (1 << 5) /**< Clear TX Overflow Interrupt Flag */\r
+#define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */\r
+#define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */\r
+#define LEUART_IFC_TXOF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_PERR (1 << 6) /**< Clear Parity Error Interrupt Flag */\r
+#define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */\r
+#define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */\r
+#define LEUART_IFC_PERR_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_FERR (1 << 7) /**< Clear Framing Error Interrupt Flag */\r
+#define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */\r
+#define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */\r
+#define LEUART_IFC_FERR_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_MPAF (1 << 8) /**< Clear Multi-Processor Address Frame Interrupt Flag */\r
+#define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */\r
+#define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */\r
+#define LEUART_IFC_MPAF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_STARTF (1 << 9) /**< Clear Start-Frame Interrupt Flag */\r
+#define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */\r
+#define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */\r
+#define LEUART_IFC_STARTF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+#define LEUART_IFC_SIGF (1 << 10) /**< Clear Signal-Frame Interrupt Flag */\r
+#define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */\r
+#define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */\r
+#define LEUART_IFC_SIGF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for LEUART_IFC */\r
+#define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */\r
+\r
+/** Bit fields for LEUART IEN */\r
+#define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */\r
+#define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */\r
+#define LEUART_IEN_TXC (1 << 0) /**< TX Complete Interrupt Enable */\r
+#define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */\r
+#define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */\r
+#define LEUART_IEN_TXC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_TXBL (1 << 1) /**< TX Buffer Level Interrupt Enable */\r
+#define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */\r
+#define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */\r
+#define LEUART_IEN_TXBL_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_RXDATAV (1 << 2) /**< RX Data Valid Interrupt Enable */\r
+#define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */\r
+#define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */\r
+#define LEUART_IEN_RXDATAV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_RXOF (1 << 3) /**< RX Overflow Interrupt Enable */\r
+#define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */\r
+#define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */\r
+#define LEUART_IEN_RXOF_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_RXUF (1 << 4) /**< RX Underflow Interrupt Enable */\r
+#define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */\r
+#define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */\r
+#define LEUART_IEN_RXUF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_TXOF (1 << 5) /**< TX Overflow Interrupt Enable */\r
+#define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */\r
+#define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */\r
+#define LEUART_IEN_TXOF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_PERR (1 << 6) /**< Parity Error Interrupt Enable */\r
+#define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */\r
+#define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */\r
+#define LEUART_IEN_PERR_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_FERR (1 << 7) /**< Framing Error Interrupt Enable */\r
+#define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */\r
+#define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */\r
+#define LEUART_IEN_FERR_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_MPAF (1 << 8) /**< Multi-Processor Address Frame Interrupt Enable */\r
+#define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */\r
+#define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */\r
+#define LEUART_IEN_MPAF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_STARTF (1 << 9) /**< Start Frame Interrupt Enable */\r
+#define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */\r
+#define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */\r
+#define LEUART_IEN_STARTF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+#define LEUART_IEN_SIGF (1 << 10) /**< Signal Frame Interrupt Enable */\r
+#define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */\r
+#define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */\r
+#define LEUART_IEN_SIGF_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for LEUART_IEN */\r
+#define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */\r
+\r
+/** Bit fields for LEUART PULSECTRL */\r
+#define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */\r
+#define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */\r
+#define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */\r
+#define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */\r
+#define LEUART_PULSECTRL_PULSEW_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */\r
+#define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */\r
+#define LEUART_PULSECTRL_PULSEEN (1 << 4) /**< Pulse Generator/Extender Enable */\r
+#define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */\r
+#define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */\r
+#define LEUART_PULSECTRL_PULSEEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */\r
+#define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */\r
+#define LEUART_PULSECTRL_PULSEFILT (1 << 5) /**< Pulse Filter */\r
+#define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */\r
+#define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */\r
+#define LEUART_PULSECTRL_PULSEFILT_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */\r
+#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */\r
+\r
+/** Bit fields for LEUART FREEZE */\r
+#define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */\r
+#define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */\r
+#define LEUART_FREEZE_REGFREEZE (1 << 0) /**< Register Update Freeze */\r
+#define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */\r
+#define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */\r
+#define LEUART_FREEZE_REGFREEZE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */\r
+#define LEUART_FREEZE_REGFREEZE_UPDATE (0x00000000UL << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */\r
+#define LEUART_FREEZE_REGFREEZE_FREEZE (0x00000001UL << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */\r
+#define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */\r
+#define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */\r
+#define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */\r
+\r
+/** Bit fields for LEUART SYNCBUSY */\r
+#define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */\r
+#define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_CTRL (1 << 0) /**< LEUARTn_CTRL Register Busy */\r
+#define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */\r
+#define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */\r
+#define LEUART_SYNCBUSY_CTRL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+#define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_CMD (1 << 1) /**< LEUARTn_CMD Register Busy */\r
+#define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */\r
+#define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */\r
+#define LEUART_SYNCBUSY_CMD_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+#define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_CLKDIV (1 << 2) /**< LEUARTn_CLKDIV Register Busy */\r
+#define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */\r
+#define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */\r
+#define LEUART_SYNCBUSY_CLKDIV_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_STARTFRAME (1 << 3) /**< LEUARTn_STARTFRAME Register Busy */\r
+#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */\r
+#define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */\r
+#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_SIGFRAME (1 << 4) /**< LEUARTn_SIGFRAME Register Busy */\r
+#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */\r
+#define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */\r
+#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_TXDATAX (1 << 5) /**< LEUARTn_TXDATAX Register Busy */\r
+#define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */\r
+#define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */\r
+#define LEUART_SYNCBUSY_TXDATAX_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_TXDATA (1 << 6) /**< LEUARTn_TXDATA Register Busy */\r
+#define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */\r
+#define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */\r
+#define LEUART_SYNCBUSY_TXDATA_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+#define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+#define LEUART_SYNCBUSY_PULSECTRL (1 << 7) /**< LEUARTn_PULSECTRL Register Busy */\r
+#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */\r
+#define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */\r
+#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */\r
+#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */\r
+\r
+/** Bit fields for LEUART ROUTE */\r
+#define _LEUART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTE */\r
+#define _LEUART_ROUTE_MASK 0x00000303UL /**< Mask for LEUART_ROUTE */\r
+#define LEUART_ROUTE_RXPEN (1 << 0) /**< RX Pin Enable */\r
+#define _LEUART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */\r
+#define _LEUART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */\r
+#define LEUART_ROUTE_RXPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LEUART_ROUTE */\r
+#define _LEUART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */\r
+#define LEUART_ROUTE_TXPEN (1 << 1) /**< TX Pin Enable */\r
+#define _LEUART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */\r
+#define _LEUART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */\r
+#define LEUART_ROUTE_TXPEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LEUART_ROUTE */\r
+#define _LEUART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */\r
+#define _LEUART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for LEUART_LOCATION */\r
+#define _LEUART_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for LEUART_LOCATION */\r
+#define LEUART_ROUTE_LOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LEUART_ROUTE */\r
+#define LEUART_ROUTE_LOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for LEUART_ROUTE */\r
+#define LEUART_ROUTE_LOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for LEUART_ROUTE */\r
+#define LEUART_ROUTE_LOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for LEUART_ROUTE */\r
+#define LEUART_ROUTE_LOCATION_LOC3 (0x00000003UL << 8) /**< Shifted mode LOC3 for LEUART_ROUTE */\r
+#define _LEUART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */\r
+#define _LEUART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTE */\r
+#define _LEUART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTE */\r
+#define _LEUART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTE */\r
+#define _LEUART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_LETIMER\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for LETIMER CTRL */\r
+#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_MASK 0x00001FFFUL /**< Mask for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */\r
+#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */\r
+#define LETIMER_CTRL_REPMODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_REPMODE_FREE (0x00000000UL << 0) /**< Shifted mode FREE for LETIMER_CTRL */\r
+#define LETIMER_CTRL_REPMODE_ONESHOT (0x00000001UL << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_REPMODE_BUFFERED (0x00000002UL << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */\r
+#define LETIMER_CTRL_REPMODE_DOUBLE (0x00000003UL << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */\r
+#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */\r
+#define LETIMER_CTRL_UFOA0_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA0_NONE (0x00000000UL << 2) /**< Shifted mode NONE for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA0_TOGGLE (0x00000001UL << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA0_PULSE (0x00000002UL << 2) /**< Shifted mode PULSE for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA0_PWM (0x00000003UL << 2) /**< Shifted mode PWM for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */\r
+#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */\r
+#define LETIMER_CTRL_UFOA1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA1_NONE (0x00000000UL << 4) /**< Shifted mode NONE for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA1_TOGGLE (0x00000001UL << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA1_PULSE (0x00000002UL << 4) /**< Shifted mode PULSE for LETIMER_CTRL */\r
+#define LETIMER_CTRL_UFOA1_PWM (0x00000003UL << 4) /**< Shifted mode PWM for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */\r
+#define LETIMER_CTRL_OPOL0 (1 << 6) /**< Output 0 Polarity */\r
+#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */\r
+#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */\r
+#define LETIMER_CTRL_OPOL0_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_OPOL1 (1 << 7) /**< Output 1 Polarity */\r
+#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */\r
+#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */\r
+#define LETIMER_CTRL_OPOL1_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_BUFTOP (1 << 8) /**< Buffered Top */\r
+#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */\r
+#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */\r
+#define LETIMER_CTRL_BUFTOP_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_COMP0TOP (1 << 9) /**< Compare Value 0 Is Top Value */\r
+#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */\r
+#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */\r
+#define LETIMER_CTRL_COMP0TOP_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_RTCC0TEN (1 << 10) /**< RTC Compare 0 Trigger Enable */\r
+#define _LETIMER_CTRL_RTCC0TEN_SHIFT 10 /**< Shift value for LETIMER_RTCC0TEN */\r
+#define _LETIMER_CTRL_RTCC0TEN_MASK 0x400UL /**< Bit mask for LETIMER_RTCC0TEN */\r
+#define LETIMER_CTRL_RTCC0TEN_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_RTCC0TEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_RTCC1TEN (1 << 11) /**< RTC Compare 1 Trigger Enable */\r
+#define _LETIMER_CTRL_RTCC1TEN_SHIFT 11 /**< Shift value for LETIMER_RTCC1TEN */\r
+#define _LETIMER_CTRL_RTCC1TEN_MASK 0x800UL /**< Bit mask for LETIMER_RTCC1TEN */\r
+#define LETIMER_CTRL_RTCC1TEN_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_RTCC1TEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+#define LETIMER_CTRL_DEBUGRUN (1 << 12) /**< Debug Mode Run Enable */\r
+#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */\r
+#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */\r
+#define LETIMER_CTRL_DEBUGRUN_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */\r
+#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */\r
+\r
+/** Bit fields for LETIMER CMD */\r
+#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */\r
+#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */\r
+#define LETIMER_CMD_START (1 << 0) /**< Start LETIMER */\r
+#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */\r
+#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */\r
+#define LETIMER_CMD_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */\r
+#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */\r
+#define LETIMER_CMD_STOP (1 << 1) /**< Stop LETIMER */\r
+#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */\r
+#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */\r
+#define LETIMER_CMD_STOP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */\r
+#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */\r
+#define LETIMER_CMD_CLEAR (1 << 2) /**< Clear LETIMER */\r
+#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */\r
+#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */\r
+#define LETIMER_CMD_CLEAR_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */\r
+#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */\r
+#define LETIMER_CMD_CTO0 (1 << 3) /**< Clear Toggle Output 0 */\r
+#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */\r
+#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */\r
+#define LETIMER_CMD_CTO0_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */\r
+#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */\r
+#define LETIMER_CMD_CTO1 (1 << 4) /**< Clear Toggle Output 1 */\r
+#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */\r
+#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */\r
+#define LETIMER_CMD_CTO1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */\r
+#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */\r
+\r
+/** Bit fields for LETIMER STATUS */\r
+#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */\r
+#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */\r
+#define LETIMER_STATUS_RUNNING (1 << 0) /**< LETIMER Running */\r
+#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */\r
+#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */\r
+#define LETIMER_STATUS_RUNNING_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */\r
+#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */\r
+\r
+/** Bit fields for LETIMER CNT */\r
+#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */\r
+#define _LETIMER_CNT_MASK 0x0000FFFFUL /**< Mask for LETIMER_CNT */\r
+#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */\r
+#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for LETIMER_CNT */\r
+#define LETIMER_CNT_CNT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */\r
+#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */\r
+\r
+/** Bit fields for LETIMER COMP0 */\r
+#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */\r
+#define _LETIMER_COMP0_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP0 */\r
+#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */\r
+#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP0 */\r
+#define LETIMER_COMP0_COMP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */\r
+#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */\r
+\r
+/** Bit fields for LETIMER COMP1 */\r
+#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */\r
+#define _LETIMER_COMP1_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP1 */\r
+#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */\r
+#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP1 */\r
+#define LETIMER_COMP1_COMP1_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */\r
+#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */\r
+\r
+/** Bit fields for LETIMER REP0 */\r
+#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */\r
+#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */\r
+#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */\r
+#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */\r
+#define LETIMER_REP0_REP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */\r
+#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */\r
+\r
+/** Bit fields for LETIMER REP1 */\r
+#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */\r
+#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */\r
+#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */\r
+#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */\r
+#define LETIMER_REP1_REP1_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */\r
+#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */\r
+\r
+/** Bit fields for LETIMER IF */\r
+#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */\r
+#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */\r
+#define LETIMER_IF_COMP0 (1 << 0) /**< Compare Match 0 Interrupt Flag */\r
+#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */\r
+#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */\r
+#define LETIMER_IF_COMP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_IF */\r
+#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */\r
+#define LETIMER_IF_COMP1 (1 << 1) /**< Compare Match 1 Interrupt Flag */\r
+#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */\r
+#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */\r
+#define LETIMER_IF_COMP1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LETIMER_IF */\r
+#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */\r
+#define LETIMER_IF_UF (1 << 2) /**< Underflow Interrupt Flag */\r
+#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */\r
+#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */\r
+#define LETIMER_IF_UF_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LETIMER_IF */\r
+#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */\r
+#define LETIMER_IF_REP0 (1 << 3) /**< Repeat Counter 0 Interrupt Flag */\r
+#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */\r
+#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */\r
+#define LETIMER_IF_REP0_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LETIMER_IF */\r
+#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */\r
+#define LETIMER_IF_REP1 (1 << 4) /**< Repeat Counter 1 Interrupt Flag */\r
+#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */\r
+#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */\r
+#define LETIMER_IF_REP1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LETIMER_IF */\r
+#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */\r
+\r
+/** Bit fields for LETIMER IFS */\r
+#define _LETIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFS */\r
+#define _LETIMER_IFS_MASK 0x0000001FUL /**< Mask for LETIMER_IFS */\r
+#define LETIMER_IFS_COMP0 (1 << 0) /**< Set Compare Match 0 Interrupt Flag */\r
+#define _LETIMER_IFS_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */\r
+#define _LETIMER_IFS_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */\r
+#define LETIMER_IFS_COMP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */\r
+#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */\r
+#define LETIMER_IFS_COMP1 (1 << 1) /**< Set Compare Match 1 Interrupt Flag */\r
+#define _LETIMER_IFS_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */\r
+#define _LETIMER_IFS_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */\r
+#define LETIMER_IFS_COMP1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */\r
+#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */\r
+#define LETIMER_IFS_UF (1 << 2) /**< Set Underflow Interrupt Flag */\r
+#define _LETIMER_IFS_UF_SHIFT 2 /**< Shift value for LETIMER_UF */\r
+#define _LETIMER_IFS_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */\r
+#define LETIMER_IFS_UF_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LETIMER_IFS */\r
+#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */\r
+#define LETIMER_IFS_REP0 (1 << 3) /**< Set Repeat Counter 0 Interrupt Flag */\r
+#define _LETIMER_IFS_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */\r
+#define _LETIMER_IFS_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */\r
+#define LETIMER_IFS_REP0_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LETIMER_IFS */\r
+#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */\r
+#define LETIMER_IFS_REP1 (1 << 4) /**< Set Repeat Counter 1 Interrupt Flag */\r
+#define _LETIMER_IFS_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */\r
+#define _LETIMER_IFS_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */\r
+#define LETIMER_IFS_REP1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LETIMER_IFS */\r
+#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */\r
+\r
+/** Bit fields for LETIMER IFC */\r
+#define _LETIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFC */\r
+#define _LETIMER_IFC_MASK 0x0000001FUL /**< Mask for LETIMER_IFC */\r
+#define LETIMER_IFC_COMP0 (1 << 0) /**< Clear Compare Match 0 Interrupt Flag */\r
+#define _LETIMER_IFC_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */\r
+#define _LETIMER_IFC_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */\r
+#define LETIMER_IFC_COMP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */\r
+#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */\r
+#define LETIMER_IFC_COMP1 (1 << 1) /**< Clear Compare Match 1 Interrupt Flag */\r
+#define _LETIMER_IFC_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */\r
+#define _LETIMER_IFC_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */\r
+#define LETIMER_IFC_COMP1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */\r
+#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */\r
+#define LETIMER_IFC_UF (1 << 2) /**< Clear Underflow Interrupt Flag */\r
+#define _LETIMER_IFC_UF_SHIFT 2 /**< Shift value for LETIMER_UF */\r
+#define _LETIMER_IFC_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */\r
+#define LETIMER_IFC_UF_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LETIMER_IFC */\r
+#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */\r
+#define LETIMER_IFC_REP0 (1 << 3) /**< Clear Repeat Counter 0 Interrupt Flag */\r
+#define _LETIMER_IFC_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */\r
+#define _LETIMER_IFC_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */\r
+#define LETIMER_IFC_REP0_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LETIMER_IFC */\r
+#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */\r
+#define LETIMER_IFC_REP1 (1 << 4) /**< Clear Repeat Counter 1 Interrupt Flag */\r
+#define _LETIMER_IFC_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */\r
+#define _LETIMER_IFC_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */\r
+#define LETIMER_IFC_REP1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LETIMER_IFC */\r
+#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */\r
+\r
+/** Bit fields for LETIMER IEN */\r
+#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */\r
+#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */\r
+#define LETIMER_IEN_COMP0 (1 << 0) /**< Compare Match 0 Interrupt Enable */\r
+#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */\r
+#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */\r
+#define LETIMER_IEN_COMP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */\r
+#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */\r
+#define LETIMER_IEN_COMP1 (1 << 1) /**< Compare Match 1 Interrupt Enable */\r
+#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */\r
+#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */\r
+#define LETIMER_IEN_COMP1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */\r
+#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */\r
+#define LETIMER_IEN_UF (1 << 2) /**< Underflow Interrupt Enable */\r
+#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */\r
+#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */\r
+#define LETIMER_IEN_UF_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */\r
+#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */\r
+#define LETIMER_IEN_REP0 (1 << 3) /**< Repeat Counter 0 Interrupt Enable */\r
+#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */\r
+#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */\r
+#define LETIMER_IEN_REP0_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */\r
+#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */\r
+#define LETIMER_IEN_REP1 (1 << 4) /**< Repeat Counter 1 Interrupt Enable */\r
+#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */\r
+#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */\r
+#define LETIMER_IEN_REP1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */\r
+#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */\r
+\r
+/** Bit fields for LETIMER FREEZE */\r
+#define _LETIMER_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_FREEZE */\r
+#define _LETIMER_FREEZE_MASK 0x00000001UL /**< Mask for LETIMER_FREEZE */\r
+#define LETIMER_FREEZE_REGFREEZE (1 << 0) /**< Register Update Freeze */\r
+#define _LETIMER_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LETIMER_REGFREEZE */\r
+#define _LETIMER_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LETIMER_REGFREEZE */\r
+#define LETIMER_FREEZE_REGFREEZE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_FREEZE */\r
+#define LETIMER_FREEZE_REGFREEZE_UPDATE (0x00000000UL << 0) /**< Shifted mode UPDATE for LETIMER_FREEZE */\r
+#define LETIMER_FREEZE_REGFREEZE_FREEZE (0x00000001UL << 0) /**< Shifted mode FREEZE for LETIMER_FREEZE */\r
+#define _LETIMER_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_FREEZE */\r
+#define _LETIMER_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LETIMER_FREEZE */\r
+#define _LETIMER_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LETIMER_FREEZE */\r
+\r
+/** Bit fields for LETIMER SYNCBUSY */\r
+#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */\r
+#define _LETIMER_SYNCBUSY_MASK 0x0000003FUL /**< Mask for LETIMER_SYNCBUSY */\r
+#define LETIMER_SYNCBUSY_CTRL (1 << 0) /**< LETIMERn_CTRL Register Busy */\r
+#define _LETIMER_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LETIMER_CTRL */\r
+#define _LETIMER_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LETIMER_CTRL */\r
+#define LETIMER_SYNCBUSY_CTRL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */\r
+#define _LETIMER_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */\r
+#define LETIMER_SYNCBUSY_CMD (1 << 1) /**< LETIMERn_CMD Register Busy */\r
+#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LETIMER_CMD */\r
+#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LETIMER_CMD */\r
+#define LETIMER_SYNCBUSY_CMD_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */\r
+#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */\r
+#define LETIMER_SYNCBUSY_COMP0 (1 << 2) /**< LETIMERn_COMP0 Register Busy */\r
+#define _LETIMER_SYNCBUSY_COMP0_SHIFT 2 /**< Shift value for LETIMER_COMP0 */\r
+#define _LETIMER_SYNCBUSY_COMP0_MASK 0x4UL /**< Bit mask for LETIMER_COMP0 */\r
+#define LETIMER_SYNCBUSY_COMP0_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */\r
+#define _LETIMER_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */\r
+#define LETIMER_SYNCBUSY_COMP1 (1 << 3) /**< LETIMERn_COMP1 Register Busy */\r
+#define _LETIMER_SYNCBUSY_COMP1_SHIFT 3 /**< Shift value for LETIMER_COMP1 */\r
+#define _LETIMER_SYNCBUSY_COMP1_MASK 0x8UL /**< Bit mask for LETIMER_COMP1 */\r
+#define LETIMER_SYNCBUSY_COMP1_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */\r
+#define _LETIMER_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */\r
+#define LETIMER_SYNCBUSY_REP0 (1 << 4) /**< LETIMERn_REP0 Register Busy */\r
+#define _LETIMER_SYNCBUSY_REP0_SHIFT 4 /**< Shift value for LETIMER_REP0 */\r
+#define _LETIMER_SYNCBUSY_REP0_MASK 0x10UL /**< Bit mask for LETIMER_REP0 */\r
+#define LETIMER_SYNCBUSY_REP0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */\r
+#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */\r
+#define LETIMER_SYNCBUSY_REP1 (1 << 5) /**< LETIMERn_REP1 Register Busy */\r
+#define _LETIMER_SYNCBUSY_REP1_SHIFT 5 /**< Shift value for LETIMER_REP1 */\r
+#define _LETIMER_SYNCBUSY_REP1_MASK 0x20UL /**< Bit mask for LETIMER_REP1 */\r
+#define LETIMER_SYNCBUSY_REP1_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */\r
+#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */\r
+\r
+/** Bit fields for LETIMER ROUTE */\r
+#define _LETIMER_ROUTE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTE */\r
+#define _LETIMER_ROUTE_MASK 0x00000303UL /**< Mask for LETIMER_ROUTE */\r
+#define LETIMER_ROUTE_OUT0PEN (1 << 0) /**< Output 0 Pin Enable */\r
+#define _LETIMER_ROUTE_OUT0PEN_SHIFT 0 /**< Shift value for LETIMER_OUT0PEN */\r
+#define _LETIMER_ROUTE_OUT0PEN_MASK 0x1UL /**< Bit mask for LETIMER_OUT0PEN */\r
+#define LETIMER_ROUTE_OUT0PEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTE */\r
+#define _LETIMER_ROUTE_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTE */\r
+#define LETIMER_ROUTE_OUT1PEN (1 << 1) /**< Output 1 Pin Enable */\r
+#define _LETIMER_ROUTE_OUT1PEN_SHIFT 1 /**< Shift value for LETIMER_OUT1PEN */\r
+#define _LETIMER_ROUTE_OUT1PEN_MASK 0x2UL /**< Bit mask for LETIMER_OUT1PEN */\r
+#define LETIMER_ROUTE_OUT1PEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTE */\r
+#define _LETIMER_ROUTE_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTE */\r
+#define _LETIMER_ROUTE_LOCATION_SHIFT 8 /**< Shift value for LETIMER_LOCATION */\r
+#define _LETIMER_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for LETIMER_LOCATION */\r
+#define LETIMER_ROUTE_LOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTE */\r
+#define LETIMER_ROUTE_LOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for LETIMER_ROUTE */\r
+#define LETIMER_ROUTE_LOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for LETIMER_ROUTE */\r
+#define LETIMER_ROUTE_LOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for LETIMER_ROUTE */\r
+#define LETIMER_ROUTE_LOCATION_LOC3 (0x00000003UL << 8) /**< Shifted mode LOC3 for LETIMER_ROUTE */\r
+#define _LETIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTE */\r
+#define _LETIMER_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTE */\r
+#define _LETIMER_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTE */\r
+#define _LETIMER_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTE */\r
+#define _LETIMER_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_PCNT\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for PCNT CTRL */\r
+#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */\r
+#define _PCNT_CTRL_MASK 0x0000003FUL /**< Mask for PCNT_CTRL */\r
+#define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */\r
+#define _PCNT_CTRL_MODE_MASK 0x3UL /**< Bit mask for PCNT_MODE */\r
+#define PCNT_CTRL_MODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_MODE_DISABLE (0x00000000UL << 0) /**< Shifted mode DISABLE for PCNT_CTRL */\r
+#define PCNT_CTRL_MODE_OVRSINGLE (0x00000001UL << 0) /**< Shifted mode OVRSINGLE for PCNT_CTRL */\r
+#define PCNT_CTRL_MODE_EXTCLKSINGLE (0x00000002UL << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */\r
+#define PCNT_CTRL_MODE_EXTCLKQUAD (0x00000003UL << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */\r
+#define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */\r
+#define _PCNT_CTRL_MODE_OVRSINGLE 0x00000001UL /**< Mode OVRSINGLE for PCNT_CTRL */\r
+#define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */\r
+#define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */\r
+#define PCNT_CTRL_CNTDIR (1 << 2) /**< Non-Quadrature Mode Counter Direction Control */\r
+#define _PCNT_CTRL_CNTDIR_SHIFT 2 /**< Shift value for PCNT_CNTDIR */\r
+#define _PCNT_CTRL_CNTDIR_MASK 0x4UL /**< Bit mask for PCNT_CNTDIR */\r
+#define PCNT_CTRL_CNTDIR_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_CNTDIR_UP (0x00000000UL << 2) /**< Shifted mode UP for PCNT_CTRL */\r
+#define PCNT_CTRL_CNTDIR_DOWN (0x00000001UL << 2) /**< Shifted mode DOWN for PCNT_CTRL */\r
+#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */\r
+#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */\r
+#define PCNT_CTRL_EDGE (1 << 3) /**< Edge Select */\r
+#define _PCNT_CTRL_EDGE_SHIFT 3 /**< Shift value for PCNT_EDGE */\r
+#define _PCNT_CTRL_EDGE_MASK 0x8UL /**< Bit mask for PCNT_EDGE */\r
+#define PCNT_CTRL_EDGE_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_EDGE_POS (0x00000000UL << 3) /**< Shifted mode POS for PCNT_CTRL */\r
+#define PCNT_CTRL_EDGE_NEG (0x00000001UL << 3) /**< Shifted mode NEG for PCNT_CTRL */\r
+#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */\r
+#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */\r
+#define PCNT_CTRL_FILT (1 << 4) /**< Enable Digital Pulse Width Filter */\r
+#define _PCNT_CTRL_FILT_SHIFT 4 /**< Shift value for PCNT_FILT */\r
+#define _PCNT_CTRL_FILT_MASK 0x10UL /**< Bit mask for PCNT_FILT */\r
+#define PCNT_CTRL_FILT_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+#define PCNT_CTRL_RSTEN (1 << 5) /**< Enable PCNT Clock Domain Reset */\r
+#define _PCNT_CTRL_RSTEN_SHIFT 5 /**< Shift value for PCNT_RSTEN */\r
+#define _PCNT_CTRL_RSTEN_MASK 0x20UL /**< Bit mask for PCNT_RSTEN */\r
+#define PCNT_CTRL_RSTEN_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */\r
+#define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */\r
+\r
+/** Bit fields for PCNT CMD */\r
+#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */\r
+#define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */\r
+#define PCNT_CMD_LCNTIM (1 << 0) /**< Load CNT Immediately */\r
+#define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */\r
+#define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */\r
+#define PCNT_CMD_LCNTIM_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_CMD */\r
+#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */\r
+#define PCNT_CMD_LTOPBIM (1 << 1) /**< Load TOPB Immediately */\r
+#define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */\r
+#define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */\r
+#define PCNT_CMD_LTOPBIM_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for PCNT_CMD */\r
+#define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */\r
+\r
+/** Bit fields for PCNT STATUS */\r
+#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */\r
+#define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */\r
+#define PCNT_STATUS_DIR (1 << 0) /**< Current Counter Direction */\r
+#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */\r
+#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */\r
+#define PCNT_STATUS_DIR_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */\r
+#define PCNT_STATUS_DIR_UP (0x00000000UL << 0) /**< Shifted mode UP for PCNT_STATUS */\r
+#define PCNT_STATUS_DIR_DOWN (0x00000001UL << 0) /**< Shifted mode DOWN for PCNT_STATUS */\r
+#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */\r
+#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */\r
+#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */\r
+\r
+/** Bit fields for PCNT CNT */\r
+#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */\r
+#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */\r
+#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */\r
+#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */\r
+#define PCNT_CNT_CNT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_CNT */\r
+#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */\r
+\r
+/** Bit fields for PCNT TOP */\r
+#define _PCNT_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for PCNT_TOP */\r
+#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */\r
+#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */\r
+#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */\r
+#define PCNT_TOP_TOP_DEFAULT (0x0000FFFFUL << 0) /**< Shifted mode DEFAULT for PCNT_TOP */\r
+#define _PCNT_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for PCNT_TOP */\r
+\r
+/** Bit fields for PCNT TOPB */\r
+#define _PCNT_TOPB_RESETVALUE 0x0000FFFFUL /**< Default value for PCNT_TOPB */\r
+#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */\r
+#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */\r
+#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */\r
+#define PCNT_TOPB_TOPB_DEFAULT (0x0000FFFFUL << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */\r
+#define _PCNT_TOPB_TOPB_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for PCNT_TOPB */\r
+\r
+/** Bit fields for PCNT IF */\r
+#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */\r
+#define _PCNT_IF_MASK 0x00000007UL /**< Mask for PCNT_IF */\r
+#define PCNT_IF_UF (1 << 0) /**< Underflow Interrupt Read Flag */\r
+#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */\r
+#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */\r
+#define PCNT_IF_UF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_IF */\r
+#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */\r
+#define PCNT_IF_OF (1 << 1) /**< Overflow Interrupt Read Flag */\r
+#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */\r
+#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */\r
+#define PCNT_IF_OF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for PCNT_IF */\r
+#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */\r
+#define PCNT_IF_DIRCNG (1 << 2) /**< Direction Change Detect Interrupt Flag */\r
+#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */\r
+#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */\r
+#define PCNT_IF_DIRCNG_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for PCNT_IF */\r
+#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */\r
+\r
+/** Bit fields for PCNT IFS */\r
+#define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */\r
+#define _PCNT_IFS_MASK 0x00000007UL /**< Mask for PCNT_IFS */\r
+#define PCNT_IFS_UF (1 << 0) /**< Underflow interrupt set */\r
+#define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */\r
+#define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */\r
+#define PCNT_IFS_UF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_IFS */\r
+#define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */\r
+#define PCNT_IFS_OF (1 << 1) /**< Overflow Interrupt Set */\r
+#define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */\r
+#define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */\r
+#define PCNT_IFS_OF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for PCNT_IFS */\r
+#define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */\r
+#define PCNT_IFS_DIRCNG (1 << 2) /**< Direction Change Detect Interrupt Set */\r
+#define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */\r
+#define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */\r
+#define PCNT_IFS_DIRCNG_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for PCNT_IFS */\r
+#define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */\r
+\r
+/** Bit fields for PCNT IFC */\r
+#define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */\r
+#define _PCNT_IFC_MASK 0x00000007UL /**< Mask for PCNT_IFC */\r
+#define PCNT_IFC_UF (1 << 0) /**< Underflow Interrupt Clear */\r
+#define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */\r
+#define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */\r
+#define PCNT_IFC_UF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_IFC */\r
+#define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */\r
+#define PCNT_IFC_OF (1 << 1) /**< Overflow Interrupt Clear */\r
+#define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */\r
+#define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */\r
+#define PCNT_IFC_OF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for PCNT_IFC */\r
+#define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */\r
+#define PCNT_IFC_DIRCNG (1 << 2) /**< Direction Change Detect Interrupt Clear */\r
+#define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */\r
+#define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */\r
+#define PCNT_IFC_DIRCNG_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for PCNT_IFC */\r
+#define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */\r
+\r
+/** Bit fields for PCNT IEN */\r
+#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */\r
+#define _PCNT_IEN_MASK 0x00000007UL /**< Mask for PCNT_IEN */\r
+#define PCNT_IEN_UF (1 << 0) /**< Underflow Interrupt Enable */\r
+#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */\r
+#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */\r
+#define PCNT_IEN_UF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_IEN */\r
+#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */\r
+#define PCNT_IEN_OF (1 << 1) /**< Overflow Interrupt Enable */\r
+#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */\r
+#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */\r
+#define PCNT_IEN_OF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for PCNT_IEN */\r
+#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */\r
+#define PCNT_IEN_DIRCNG (1 << 2) /**< Direction Change Detect Interrupt Enable */\r
+#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */\r
+#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */\r
+#define PCNT_IEN_DIRCNG_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for PCNT_IEN */\r
+#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */\r
+\r
+/** Bit fields for PCNT ROUTE */\r
+#define _PCNT_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTE */\r
+#define _PCNT_ROUTE_MASK 0x00000300UL /**< Mask for PCNT_ROUTE */\r
+#define _PCNT_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PCNT_LOCATION */\r
+#define _PCNT_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for PCNT_LOCATION */\r
+#define PCNT_ROUTE_LOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for PCNT_ROUTE */\r
+#define PCNT_ROUTE_LOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for PCNT_ROUTE */\r
+#define PCNT_ROUTE_LOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for PCNT_ROUTE */\r
+#define PCNT_ROUTE_LOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for PCNT_ROUTE */\r
+#define _PCNT_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTE */\r
+#define _PCNT_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTE */\r
+#define _PCNT_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTE */\r
+#define _PCNT_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTE */\r
+\r
+/** Bit fields for PCNT FREEZE */\r
+#define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */\r
+#define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */\r
+#define PCNT_FREEZE_REGFREEZE (1 << 0) /**< Register Update Freeze */\r
+#define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */\r
+#define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */\r
+#define PCNT_FREEZE_REGFREEZE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */\r
+#define PCNT_FREEZE_REGFREEZE_UPDATE (0x00000000UL << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */\r
+#define PCNT_FREEZE_REGFREEZE_FREEZE (0x00000001UL << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */\r
+#define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */\r
+#define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */\r
+#define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */\r
+\r
+/** Bit fields for PCNT SYNCBUSY */\r
+#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */\r
+#define _PCNT_SYNCBUSY_MASK 0x00000007UL /**< Mask for PCNT_SYNCBUSY */\r
+#define PCNT_SYNCBUSY_CTRL (1 << 0) /**< PCNTn_CTRL Register Busy */\r
+#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */\r
+#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */\r
+#define PCNT_SYNCBUSY_CTRL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */\r
+#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */\r
+#define PCNT_SYNCBUSY_CMD (1 << 1) /**< PCNTn_CMD Register Busy */\r
+#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */\r
+#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */\r
+#define PCNT_SYNCBUSY_CMD_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */\r
+#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */\r
+#define PCNT_SYNCBUSY_TOPB (1 << 2) /**< PCNTn_TOPB Register Busy */\r
+#define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */\r
+#define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */\r
+#define PCNT_SYNCBUSY_TOPB_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */\r
+#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_I2C\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for I2C CTRL */\r
+#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */\r
+#define _I2C_CTRL_MASK 0x0007B37FUL /**< Mask for I2C_CTRL */\r
+#define I2C_CTRL_EN (1 << 0) /**< I2C Enable */\r
+#define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */\r
+#define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */\r
+#define I2C_CTRL_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_SLAVE (1 << 1) /**< Addressable as Slave */\r
+#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */\r
+#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */\r
+#define I2C_CTRL_SLAVE_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_SLAVE_DISABLE (0x00000000UL << 1) /**< Shifted mode DISABLE for I2C_CTRL */\r
+#define I2C_CTRL_SLAVE_ENABLE (0x00000001UL << 1) /**< Shifted mode ENABLE for I2C_CTRL */\r
+#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */\r
+#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */\r
+#define I2C_CTRL_AUTOACK (1 << 2) /**< Automatic Acknowledge */\r
+#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */\r
+#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */\r
+#define I2C_CTRL_AUTOACK_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_AUTOACK_DISABLE (0x00000000UL << 2) /**< Shifted mode DISABLE for I2C_CTRL */\r
+#define I2C_CTRL_AUTOACK_ENABLE (0x00000001UL << 2) /**< Shifted mode ENABLE for I2C_CTRL */\r
+#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */\r
+#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */\r
+#define I2C_CTRL_AUTOSE (1 << 3) /**< Automatic STOP when Empty */\r
+#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */\r
+#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */\r
+#define I2C_CTRL_AUTOSE_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_AUTOSE_DISABLE (0x00000000UL << 3) /**< Shifted mode DISABLE for I2C_CTRL */\r
+#define I2C_CTRL_AUTOSE_ENABLE (0x00000001UL << 3) /**< Shifted mode ENABLE for I2C_CTRL */\r
+#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */\r
+#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */\r
+#define I2C_CTRL_AUTOSN (1 << 4) /**< Automatic STOP on NACK */\r
+#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */\r
+#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */\r
+#define I2C_CTRL_AUTOSN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_AUTOSN_DISABLE (0x00000000UL << 4) /**< Shifted mode DISABLE for I2C_CTRL */\r
+#define I2C_CTRL_AUTOSN_ENABLE (0x00000001UL << 4) /**< Shifted mode ENABLE for I2C_CTRL */\r
+#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */\r
+#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */\r
+#define I2C_CTRL_ARBDIS (1 << 5) /**< Arbitration Disable */\r
+#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */\r
+#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */\r
+#define I2C_CTRL_ARBDIS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_GCAMEN (1 << 6) /**< General Call Address Match Enable */\r
+#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */\r
+#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */\r
+#define I2C_CTRL_GCAMEN_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */\r
+#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */\r
+#define I2C_CTRL_CLHR_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_CLHR_STANDARD (0x00000000UL << 8) /**< Shifted mode STANDARD for I2C_CTRL */\r
+#define I2C_CTRL_CLHR_ASYMMETRIC (0x00000001UL << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */\r
+#define I2C_CTRL_CLHR_FAST (0x00000002UL << 8) /**< Shifted mode FAST for I2C_CTRL */\r
+#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */\r
+#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */\r
+#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */\r
+#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */\r
+#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */\r
+#define I2C_CTRL_BITO_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_BITO_OFF (0x00000000UL << 12) /**< Shifted mode OFF for I2C_CTRL */\r
+#define I2C_CTRL_BITO_40PCC (0x00000001UL << 12) /**< Shifted mode 40PCC for I2C_CTRL */\r
+#define I2C_CTRL_BITO_80PCC (0x00000002UL << 12) /**< Shifted mode 80PCC for I2C_CTRL */\r
+#define I2C_CTRL_BITO_160PCC (0x00000003UL << 12) /**< Shifted mode 160PCC for I2C_CTRL */\r
+#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */\r
+#define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */\r
+#define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */\r
+#define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */\r
+#define I2C_CTRL_GIBITO (1 << 15) /**< Go Idle on Bus Idle Timeout */\r
+#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */\r
+#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */\r
+#define I2C_CTRL_GIBITO_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_GIBITO_DISABLE (0x00000000UL << 15) /**< Shifted mode DISABLE for I2C_CTRL */\r
+#define I2C_CTRL_GIBITO_ENABLE (0x00000001UL << 15) /**< Shifted mode ENABLE for I2C_CTRL */\r
+#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */\r
+#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */\r
+#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */\r
+#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */\r
+#define I2C_CTRL_CLTO_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for I2C_CTRL */\r
+#define I2C_CTRL_CLTO_OFF (0x00000000UL << 16) /**< Shifted mode OFF for I2C_CTRL */\r
+#define I2C_CTRL_CLTO_40PCC (0x00000001UL << 16) /**< Shifted mode 40PCC for I2C_CTRL */\r
+#define I2C_CTRL_CLTO_80PCC (0x00000002UL << 16) /**< Shifted mode 80PCC for I2C_CTRL */\r
+#define I2C_CTRL_CLTO_160PCC (0x00000003UL << 16) /**< Shifted mode 160PCC for I2C_CTRL */\r
+#define I2C_CTRL_CLTO_320PPC (0x00000004UL << 16) /**< Shifted mode 320PPC for I2C_CTRL */\r
+#define I2C_CTRL_CLTO_1024PPC (0x00000005UL << 16) /**< Shifted mode 1024PPC for I2C_CTRL */\r
+#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */\r
+#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */\r
+#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */\r
+#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */\r
+#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */\r
+#define _I2C_CTRL_CLTO_320PPC 0x00000004UL /**< Mode 320PPC for I2C_CTRL */\r
+#define _I2C_CTRL_CLTO_1024PPC 0x00000005UL /**< Mode 1024PPC for I2C_CTRL */\r
+\r
+/** Bit fields for I2C CMD */\r
+#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */\r
+#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */\r
+#define I2C_CMD_START (1 << 0) /**< Send start condition */\r
+#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */\r
+#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */\r
+#define I2C_CMD_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_CMD */\r
+#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_STOP (1 << 1) /**< Send stop condition */\r
+#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */\r
+#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */\r
+#define I2C_CMD_STOP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_CMD */\r
+#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_ACK (1 << 2) /**< Send ACK */\r
+#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */\r
+#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */\r
+#define I2C_CMD_ACK_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_CMD */\r
+#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_NACK (1 << 3) /**< Send NACK */\r
+#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */\r
+#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */\r
+#define I2C_CMD_NACK_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_CMD */\r
+#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_CONT (1 << 4) /**< Continue transmission */\r
+#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */\r
+#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */\r
+#define I2C_CMD_CONT_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_CMD */\r
+#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_ABORT (1 << 5) /**< Abort transmission */\r
+#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */\r
+#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */\r
+#define I2C_CMD_ABORT_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_CMD */\r
+#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_CLEARTX (1 << 6) /**< Clear TX */\r
+#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */\r
+#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */\r
+#define I2C_CMD_CLEARTX_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for I2C_CMD */\r
+#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+#define I2C_CMD_CLEARPC (1 << 7) /**< Clear Pending Commands */\r
+#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */\r
+#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */\r
+#define I2C_CMD_CLEARPC_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for I2C_CMD */\r
+#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */\r
+\r
+/** Bit fields for I2C STATE */\r
+#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */\r
+#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */\r
+#define I2C_STATE_BUSY (1 << 0) /**< Bus Busy */\r
+#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */\r
+#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */\r
+#define I2C_STATE_BUSY_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for I2C_STATE */\r
+#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */\r
+#define I2C_STATE_MASTER (1 << 1) /**< Master */\r
+#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */\r
+#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */\r
+#define I2C_STATE_MASTER_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_STATE */\r
+#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */\r
+#define I2C_STATE_TRANSMITTER (1 << 2) /**< Transmitter */\r
+#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */\r
+#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */\r
+#define I2C_STATE_TRANSMITTER_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_STATE */\r
+#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */\r
+#define I2C_STATE_NACKED (1 << 3) /**< Nack Received */\r
+#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */\r
+#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */\r
+#define I2C_STATE_NACKED_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_STATE */\r
+#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */\r
+#define I2C_STATE_BUSHOLD (1 << 4) /**< Bus Held */\r
+#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */\r
+#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */\r
+#define I2C_STATE_BUSHOLD_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_STATE */\r
+#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */\r
+#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */\r
+#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */\r
+#define I2C_STATE_STATE_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_STATE */\r
+#define I2C_STATE_STATE_IDLE (0x00000000UL << 5) /**< Shifted mode IDLE for I2C_STATE */\r
+#define I2C_STATE_STATE_WAIT (0x00000001UL << 5) /**< Shifted mode WAIT for I2C_STATE */\r
+#define I2C_STATE_STATE_START (0x00000002UL << 5) /**< Shifted mode START for I2C_STATE */\r
+#define I2C_STATE_STATE_ADDR (0x00000003UL << 5) /**< Shifted mode ADDR for I2C_STATE */\r
+#define I2C_STATE_STATE_ADDRACK (0x00000004UL << 5) /**< Shifted mode ADDRACK for I2C_STATE */\r
+#define I2C_STATE_STATE_DATA (0x00000005UL << 5) /**< Shifted mode DATA for I2C_STATE */\r
+#define I2C_STATE_STATE_DATAACK (0x00000006UL << 5) /**< Shifted mode DATAACK for I2C_STATE */\r
+#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */\r
+#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */\r
+#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */\r
+#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */\r
+#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */\r
+#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */\r
+#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */\r
+#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */\r
+\r
+/** Bit fields for I2C STATUS */\r
+#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */\r
+#define _I2C_STATUS_MASK 0x000001FFUL /**< Mask for I2C_STATUS */\r
+#define I2C_STATUS_PSTART (1 << 0) /**< Pending START */\r
+#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */\r
+#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */\r
+#define I2C_STATUS_PSTART_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PSTOP (1 << 1) /**< Pending STOP */\r
+#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */\r
+#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */\r
+#define I2C_STATUS_PSTOP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PACK (1 << 2) /**< Pending ACK */\r
+#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */\r
+#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */\r
+#define I2C_STATUS_PACK_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PNACK (1 << 3) /**< Pending NACK */\r
+#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */\r
+#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */\r
+#define I2C_STATUS_PNACK_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PCONT (1 << 4) /**< Pending continue */\r
+#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */\r
+#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */\r
+#define I2C_STATUS_PCONT_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_PABORT (1 << 5) /**< Pending abort */\r
+#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */\r
+#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */\r
+#define I2C_STATUS_PABORT_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_TXC (1 << 6) /**< TX Complete */\r
+#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */\r
+#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */\r
+#define I2C_STATUS_TXC_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_TXBL (1 << 7) /**< TX Buffer Level */\r
+#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */\r
+#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */\r
+#define I2C_STATUS_TXBL_DEFAULT (0x00000001UL << 7) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */\r
+#define I2C_STATUS_RXDATAV (1 << 8) /**< RX Data Valid */\r
+#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */\r
+#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */\r
+#define I2C_STATUS_RXDATAV_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for I2C_STATUS */\r
+#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */\r
+\r
+/** Bit fields for I2C CLKDIV */\r
+#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */\r
+#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */\r
+#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */\r
+#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */\r
+#define I2C_CLKDIV_DIV_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */\r
+#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */\r
+\r
+/** Bit fields for I2C SADDR */\r
+#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */\r
+#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */\r
+#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */\r
+#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */\r
+#define I2C_SADDR_ADDR_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_SADDR */\r
+#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */\r
+\r
+/** Bit fields for I2C SADDRMASK */\r
+#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */\r
+#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */\r
+#define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */\r
+#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */\r
+#define I2C_SADDRMASK_MASK_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */\r
+#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */\r
+\r
+/** Bit fields for I2C RXDATA */\r
+#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */\r
+#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */\r
+#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */\r
+#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */\r
+#define I2C_RXDATA_RXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */\r
+#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */\r
+\r
+/** Bit fields for I2C RXDATAP */\r
+#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */\r
+#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */\r
+#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */\r
+#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */\r
+#define I2C_RXDATAP_RXDATAP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */\r
+#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */\r
+\r
+/** Bit fields for I2C TXDATA */\r
+#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */\r
+#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */\r
+#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */\r
+#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */\r
+#define I2C_TXDATA_TXDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */\r
+#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */\r
+\r
+/** Bit fields for I2C IF */\r
+#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */\r
+#define _I2C_IF_MASK 0x0001FFFFUL /**< Mask for I2C_IF */\r
+#define I2C_IF_START (1 << 0) /**< START condition Interrupt Flag */\r
+#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */\r
+#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */\r
+#define I2C_IF_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_RSTART (1 << 1) /**< Repeated START condition Interrupt Flag */\r
+#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */\r
+#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */\r
+#define I2C_IF_RSTART_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_ADDR (1 << 2) /**< Address Interrupt Flag */\r
+#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */\r
+#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */\r
+#define I2C_IF_ADDR_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_TXC (1 << 3) /**< Transfer Completed Interrupt Flag */\r
+#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */\r
+#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */\r
+#define I2C_IF_TXC_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_TXBL (1 << 4) /**< Transmit Buffer Level Interrupt Flag */\r
+#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */\r
+#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */\r
+#define I2C_IF_TXBL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_RXDATAV (1 << 5) /**< Receive Data Valid Interrupt Flag */\r
+#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */\r
+#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */\r
+#define I2C_IF_RXDATAV_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_ACK (1 << 6) /**< Acknowledge Received Interrupt Flag */\r
+#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */\r
+#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */\r
+#define I2C_IF_ACK_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_NACK (1 << 7) /**< Not Acknowledge Received Interrupt Flag */\r
+#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */\r
+#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */\r
+#define I2C_IF_NACK_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_MSTOP (1 << 8) /**< Master STOP Condition Interrupt Flag */\r
+#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */\r
+#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */\r
+#define I2C_IF_MSTOP_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_ARBLOST (1 << 9) /**< Arbitration Lost Interrupt Flag */\r
+#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */\r
+#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */\r
+#define I2C_IF_ARBLOST_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_BUSERR (1 << 10) /**< Bus Error Interrupt Flag */\r
+#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */\r
+#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */\r
+#define I2C_IF_BUSERR_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_BUSHOLD (1 << 11) /**< Bus Held Interrupt Flag */\r
+#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */\r
+#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */\r
+#define I2C_IF_BUSHOLD_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_TXOF (1 << 12) /**< Transmit Buffer Overflow Interrupt Flag */\r
+#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */\r
+#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */\r
+#define I2C_IF_TXOF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_RXUF (1 << 13) /**< Receive Buffer Underflow Interrupt Flag */\r
+#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */\r
+#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */\r
+#define I2C_IF_RXUF_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_BITO (1 << 14) /**< Bus Idle Timeout Interrupt Flag */\r
+#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */\r
+#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */\r
+#define I2C_IF_BITO_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_CLTO (1 << 15) /**< Clock Low Interrupt Flag */\r
+#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */\r
+#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */\r
+#define I2C_IF_CLTO_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+#define I2C_IF_SSTOP (1 << 16) /**< Slave STOP condition Interrupt Flag */\r
+#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */\r
+#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */\r
+#define I2C_IF_SSTOP_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for I2C_IF */\r
+#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */\r
+\r
+/** Bit fields for I2C IFS */\r
+#define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */\r
+#define _I2C_IFS_MASK 0x0001FFFFUL /**< Mask for I2C_IFS */\r
+#define I2C_IFS_START (1 << 0) /**< Set START Interrupt Flag */\r
+#define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */\r
+#define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */\r
+#define I2C_IFS_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_RSTART (1 << 1) /**< Set Repeated START Interrupt Flag */\r
+#define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */\r
+#define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */\r
+#define I2C_IFS_RSTART_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_ADDR (1 << 2) /**< Set Address Interrupt Flag */\r
+#define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */\r
+#define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */\r
+#define I2C_IFS_ADDR_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_TXC (1 << 3) /**< Set Transfer Completed Interrupt Flag */\r
+#define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */\r
+#define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */\r
+#define I2C_IFS_TXC_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_TXBL (1 << 4) /**< Set Transmit Buffer level Interrupt Flag */\r
+#define _I2C_IFS_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */\r
+#define _I2C_IFS_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */\r
+#define I2C_IFS_TXBL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_RXDATAV (1 << 5) /**< Set Receive Data Valid Interrupt Flag */\r
+#define _I2C_IFS_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */\r
+#define _I2C_IFS_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */\r
+#define I2C_IFS_RXDATAV_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_ACK (1 << 6) /**< Set Acknowledge Received Interrupt Flag */\r
+#define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */\r
+#define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */\r
+#define I2C_IFS_ACK_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_NACK (1 << 7) /**< Set Not Acknowledge Received Interrupt Flag */\r
+#define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */\r
+#define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */\r
+#define I2C_IFS_NACK_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_MSTOP (1 << 8) /**< Set MSTOP Interrupt Flag */\r
+#define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */\r
+#define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */\r
+#define I2C_IFS_MSTOP_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_ARBLOST (1 << 9) /**< Set Arbitration Lost Interrupt Flag */\r
+#define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */\r
+#define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */\r
+#define I2C_IFS_ARBLOST_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_BUSERR (1 << 10) /**< Set Bus Error Interrupt Flag */\r
+#define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */\r
+#define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */\r
+#define I2C_IFS_BUSERR_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_BUSHOLD (1 << 11) /**< Set Bus Held Interrupt Flag */\r
+#define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */\r
+#define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */\r
+#define I2C_IFS_BUSHOLD_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_TXOF (1 << 12) /**< Set Transmit Buffer Overflow Interrupt Flag */\r
+#define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */\r
+#define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */\r
+#define I2C_IFS_TXOF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_RXUF (1 << 13) /**< Set Receive Buffer Underflow Interrupt Flag */\r
+#define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */\r
+#define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */\r
+#define I2C_IFS_RXUF_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_BITO (1 << 14) /**< Set Bus Idle Timeout Interrupt Flag */\r
+#define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */\r
+#define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */\r
+#define I2C_IFS_BITO_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_CLTO (1 << 15) /**< Set Clock Low Interrupt Flag */\r
+#define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */\r
+#define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */\r
+#define I2C_IFS_CLTO_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+#define I2C_IFS_SSTOP (1 << 16) /**< Set SSTOP Interrupt Flag */\r
+#define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */\r
+#define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */\r
+#define I2C_IFS_SSTOP_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for I2C_IFS */\r
+#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */\r
+\r
+/** Bit fields for I2C IFC */\r
+#define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */\r
+#define _I2C_IFC_MASK 0x0001FFFFUL /**< Mask for I2C_IFC */\r
+#define I2C_IFC_START (1 << 0) /**< Clear START Interrupt Flag */\r
+#define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */\r
+#define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */\r
+#define I2C_IFC_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_RSTART (1 << 1) /**< Clear Repeated START Interrupt Flag */\r
+#define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */\r
+#define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */\r
+#define I2C_IFC_RSTART_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_ADDR (1 << 2) /**< Clear Address Interrupt Flag */\r
+#define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */\r
+#define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */\r
+#define I2C_IFC_ADDR_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_TXC (1 << 3) /**< Clear Transfer Completed Interrupt Flag */\r
+#define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */\r
+#define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */\r
+#define I2C_IFC_TXC_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_TXBL (1 << 4) /**< Clear Transmit Buffer level Interrupt Flag */\r
+#define _I2C_IFC_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */\r
+#define _I2C_IFC_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */\r
+#define I2C_IFC_TXBL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_RXDATAV (1 << 5) /**< Clear Receive Data Valid Interrupt Flag */\r
+#define _I2C_IFC_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */\r
+#define _I2C_IFC_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */\r
+#define I2C_IFC_RXDATAV_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_ACK (1 << 6) /**< Clear Acknowledge Received Interrupt Flag */\r
+#define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */\r
+#define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */\r
+#define I2C_IFC_ACK_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_NACK (1 << 7) /**< Clear Not Acknowledge Received Interrupt Flag */\r
+#define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */\r
+#define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */\r
+#define I2C_IFC_NACK_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_MSTOP (1 << 8) /**< Clear MSTOP Interrupt Flag */\r
+#define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */\r
+#define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */\r
+#define I2C_IFC_MSTOP_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_ARBLOST (1 << 9) /**< Clear Arbitration Lost Interrupt Flag */\r
+#define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */\r
+#define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */\r
+#define I2C_IFC_ARBLOST_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_BUSERR (1 << 10) /**< Clear Bus Error Interrupt Flag */\r
+#define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */\r
+#define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */\r
+#define I2C_IFC_BUSERR_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_BUSHOLD (1 << 11) /**< Clear Bus Held Interrupt Flag */\r
+#define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */\r
+#define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */\r
+#define I2C_IFC_BUSHOLD_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_TXOF (1 << 12) /**< Clear Transmit Buffer Overflow Interrupt Flag */\r
+#define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */\r
+#define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */\r
+#define I2C_IFC_TXOF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_RXUF (1 << 13) /**< Clear Receive Buffer Underflow Interrupt Flag */\r
+#define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */\r
+#define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */\r
+#define I2C_IFC_RXUF_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_BITO (1 << 14) /**< Clear Bus Idle Timeout Interrupt Flag */\r
+#define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */\r
+#define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */\r
+#define I2C_IFC_BITO_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_CLTO (1 << 15) /**< Clear Clock Low Interrupt Flag */\r
+#define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */\r
+#define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */\r
+#define I2C_IFC_CLTO_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+#define I2C_IFC_SSTOP (1 << 16) /**< Clear SSTOP Interrupt Flag */\r
+#define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */\r
+#define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */\r
+#define I2C_IFC_SSTOP_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for I2C_IFC */\r
+#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */\r
+\r
+/** Bit fields for I2C IEN */\r
+#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */\r
+#define _I2C_IEN_MASK 0x0001FFFFUL /**< Mask for I2C_IEN */\r
+#define I2C_IEN_START (1 << 0) /**< START Condition Interrupt Enable */\r
+#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */\r
+#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */\r
+#define I2C_IEN_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_RSTART (1 << 1) /**< Repeated START condition Interrupt Enable */\r
+#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */\r
+#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */\r
+#define I2C_IEN_RSTART_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_ADDR (1 << 2) /**< Address Interrupt Enable */\r
+#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */\r
+#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */\r
+#define I2C_IEN_ADDR_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_TXC (1 << 3) /**< Transfer Completed Interrupt Enable */\r
+#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */\r
+#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */\r
+#define I2C_IEN_TXC_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_TXBL (1 << 4) /**< Transmit Buffer level Interrupt Enable */\r
+#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */\r
+#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */\r
+#define I2C_IEN_TXBL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_RXDATAV (1 << 5) /**< Receive Data Valid Interrupt Enable */\r
+#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */\r
+#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */\r
+#define I2C_IEN_RXDATAV_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_ACK (1 << 6) /**< Acknowledge Received Interrupt Enable */\r
+#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */\r
+#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */\r
+#define I2C_IEN_ACK_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_NACK (1 << 7) /**< Not Acknowledge Received Interrupt Enable */\r
+#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */\r
+#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */\r
+#define I2C_IEN_NACK_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_MSTOP (1 << 8) /**< MSTOP Interrupt Enable */\r
+#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */\r
+#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */\r
+#define I2C_IEN_MSTOP_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_ARBLOST (1 << 9) /**< Arbitration Lost Interrupt Enable */\r
+#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */\r
+#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */\r
+#define I2C_IEN_ARBLOST_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_BUSERR (1 << 10) /**< Bus Error Interrupt Enable */\r
+#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */\r
+#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */\r
+#define I2C_IEN_BUSERR_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_BUSHOLD (1 << 11) /**< Bus Held Interrupt Enable */\r
+#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */\r
+#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */\r
+#define I2C_IEN_BUSHOLD_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_TXOF (1 << 12) /**< Transmit Buffer Overflow Interrupt Enable */\r
+#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */\r
+#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */\r
+#define I2C_IEN_TXOF_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_RXUF (1 << 13) /**< Receive Buffer Underflow Interrupt Enable */\r
+#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */\r
+#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */\r
+#define I2C_IEN_RXUF_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_BITO (1 << 14) /**< Bus Idle Timeout Interrupt Enable */\r
+#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */\r
+#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */\r
+#define I2C_IEN_BITO_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_CLTO (1 << 15) /**< Clock Low Interrupt Enable */\r
+#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */\r
+#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */\r
+#define I2C_IEN_CLTO_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+#define I2C_IEN_SSTOP (1 << 16) /**< SSTOP Interrupt Enable */\r
+#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */\r
+#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */\r
+#define I2C_IEN_SSTOP_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for I2C_IEN */\r
+#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */\r
+\r
+/** Bit fields for I2C ROUTE */\r
+#define _I2C_ROUTE_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTE */\r
+#define _I2C_ROUTE_MASK 0x00000303UL /**< Mask for I2C_ROUTE */\r
+#define I2C_ROUTE_SDAPEN (1 << 0) /**< SDA Pin Enable */\r
+#define _I2C_ROUTE_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */\r
+#define _I2C_ROUTE_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */\r
+#define I2C_ROUTE_SDAPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for I2C_ROUTE */\r
+#define _I2C_ROUTE_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */\r
+#define I2C_ROUTE_SCLPEN (1 << 1) /**< SCL Pin Enable */\r
+#define _I2C_ROUTE_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */\r
+#define _I2C_ROUTE_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */\r
+#define I2C_ROUTE_SCLPEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for I2C_ROUTE */\r
+#define _I2C_ROUTE_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */\r
+#define _I2C_ROUTE_LOCATION_SHIFT 8 /**< Shift value for I2C_LOCATION */\r
+#define _I2C_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for I2C_LOCATION */\r
+#define I2C_ROUTE_LOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for I2C_ROUTE */\r
+#define I2C_ROUTE_LOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for I2C_ROUTE */\r
+#define I2C_ROUTE_LOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for I2C_ROUTE */\r
+#define I2C_ROUTE_LOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for I2C_ROUTE */\r
+#define I2C_ROUTE_LOCATION_LOC3 (0x00000003UL << 8) /**< Shifted mode LOC3 for I2C_ROUTE */\r
+#define _I2C_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */\r
+#define _I2C_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTE */\r
+#define _I2C_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTE */\r
+#define _I2C_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTE */\r
+#define _I2C_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_ADC\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for ADC CTRL */\r
+#define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */\r
+#define _ADC_CTRL_MASK 0x0F1F7F3BUL /**< Mask for ADC_CTRL */\r
+#define _ADC_CTRL_ENERGYMODE_SHIFT 0 /**< Shift value for ADC_ENERGYMODE */\r
+#define _ADC_CTRL_ENERGYMODE_MASK 0x3UL /**< Bit mask for ADC_ENERGYMODE */\r
+#define ADC_CTRL_ENERGYMODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_ENERGYMODE_NORMAL (0x00000000UL << 0) /**< Shifted mode NORMAL for ADC_CTRL */\r
+#define ADC_CTRL_ENERGYMODE_FASTBG (0x00000001UL << 0) /**< Shifted mode FASTBG for ADC_CTRL */\r
+#define ADC_CTRL_ENERGYMODE_KEEPSCANREFWARM (0x00000002UL << 0) /**< Shifted mode KEEPSCANREFWARM for ADC_CTRL */\r
+#define ADC_CTRL_ENERGYMODE_KEEPADCWARM (0x00000003UL << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */\r
+#define _ADC_CTRL_ENERGYMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */\r
+#define _ADC_CTRL_ENERGYMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */\r
+#define _ADC_CTRL_ENERGYMODE_FASTBG 0x00000001UL /**< Mode FASTBG for ADC_CTRL */\r
+#define _ADC_CTRL_ENERGYMODE_KEEPSCANREFWARM 0x00000002UL /**< Mode KEEPSCANREFWARM for ADC_CTRL */\r
+#define _ADC_CTRL_ENERGYMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */\r
+#define ADC_CTRL_TAILGATE (1 << 3) /**< Conversion Tailgating */\r
+#define _ADC_CTRL_TAILGATE_SHIFT 3 /**< Shift value for ADC_TAILGATE */\r
+#define _ADC_CTRL_TAILGATE_MASK 0x8UL /**< Bit mask for ADC_TAILGATE */\r
+#define ADC_CTRL_TAILGATE_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */\r
+#define _ADC_CTRL_LPFMODE_SHIFT 4 /**< Shift value for ADC_LPFMODE */\r
+#define _ADC_CTRL_LPFMODE_MASK 0x30UL /**< Bit mask for ADC_LPFMODE */\r
+#define ADC_CTRL_LPFMODE_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_LPFMODE_BYPASS (0x00000000UL << 4) /**< Shifted mode BYPASS for ADC_CTRL */\r
+#define ADC_CTRL_LPFMODE_RCFILT (0x00000001UL << 4) /**< Shifted mode RCFILT for ADC_CTRL */\r
+#define ADC_CTRL_LPFMODE_DECAP (0x00000002UL << 4) /**< Shifted mode DECAP for ADC_CTRL */\r
+#define _ADC_CTRL_LPFMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */\r
+#define _ADC_CTRL_LPFMODE_BYPASS 0x00000000UL /**< Mode BYPASS for ADC_CTRL */\r
+#define _ADC_CTRL_LPFMODE_RCFILT 0x00000001UL /**< Mode RCFILT for ADC_CTRL */\r
+#define _ADC_CTRL_LPFMODE_DECAP 0x00000002UL /**< Mode DECAP for ADC_CTRL */\r
+#define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */\r
+#define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */\r
+#define ADC_CTRL_PRESC_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_PRESC_NODIVISION (0x00000000UL << 8) /**< Shifted mode NODIVISION for ADC_CTRL */\r
+#define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */\r
+#define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */\r
+#define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */\r
+#define _ADC_CTRL_TIMEBASE_MASK 0x1F0000UL /**< Bit mask for ADC_TIMEBASE */\r
+#define ADC_CTRL_TIMEBASE_DEFAULT (0x0000001FUL << 16) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */\r
+#define _ADC_CTRL_OSRSEL_SHIFT 24 /**< Shift value for ADC_OSRSEL */\r
+#define _ADC_CTRL_OSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OSRSEL */\r
+#define ADC_CTRL_OSRSEL_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for ADC_CTRL */\r
+#define ADC_CTRL_OSRSEL_OSR2 (0x00000000UL << 24) /**< Shifted mode OSR2 for ADC_CTRL */\r
+#define ADC_CTRL_OSRSEL_OSR4 (0x00000001UL << 24) /**< Shifted mode OSR4 for ADC_CTRL */\r
+#define ADC_CTRL_OSRSEL_OSR8 (0x00000002UL << 24) /**< Shifted mode OSR8 for ADC_CTRL */\r
+#define ADC_CTRL_OSRSEL_OSR16 (0x00000003UL << 24) /**< Shifted mode OSR16 for ADC_CTRL */\r
+#define ADC_CTRL_OSRSEL_OSR32 (0x00000004UL << 24) /**< Shifted mode OSR32 for ADC_CTRL */\r
+#define ADC_CTRL_OSRSEL_OSR64 (0x00000005UL << 24) /**< Shifted mode OSR64 for ADC_CTRL */\r
+#define ADC_CTRL_OSRSEL_OSR128 (0x00000006UL << 24) /**< Shifted mode OSR128 for ADC_CTRL */\r
+#define ADC_CTRL_OSRSEL_OSR256 (0x00000007UL << 24) /**< Shifted mode OSR256 for ADC_CTRL */\r
+#define ADC_CTRL_OSRSEL_OSR512 (0x00000008UL << 24) /**< Shifted mode OSR512 for ADC_CTRL */\r
+#define ADC_CTRL_OSRSEL_OSR1024 (0x00000009UL << 24) /**< Shifted mode OSR1024 for ADC_CTRL */\r
+#define ADC_CTRL_OSRSEL_OSR2048 (0x0000000AUL << 24) /**< Shifted mode OSR2048 for ADC_CTRL */\r
+#define ADC_CTRL_OSRSEL_OSR4096 (0x0000000BUL << 24) /**< Shifted mode OSR4096 for ADC_CTRL */\r
+#define _ADC_CTRL_OSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */\r
+#define _ADC_CTRL_OSRSEL_OSR2 0x00000000UL /**< Mode OSR2 for ADC_CTRL */\r
+#define _ADC_CTRL_OSRSEL_OSR4 0x00000001UL /**< Mode OSR4 for ADC_CTRL */\r
+#define _ADC_CTRL_OSRSEL_OSR8 0x00000002UL /**< Mode OSR8 for ADC_CTRL */\r
+#define _ADC_CTRL_OSRSEL_OSR16 0x00000003UL /**< Mode OSR16 for ADC_CTRL */\r
+#define _ADC_CTRL_OSRSEL_OSR32 0x00000004UL /**< Mode OSR32 for ADC_CTRL */\r
+#define _ADC_CTRL_OSRSEL_OSR64 0x00000005UL /**< Mode OSR64 for ADC_CTRL */\r
+#define _ADC_CTRL_OSRSEL_OSR128 0x00000006UL /**< Mode OSR128 for ADC_CTRL */\r
+#define _ADC_CTRL_OSRSEL_OSR256 0x00000007UL /**< Mode OSR256 for ADC_CTRL */\r
+#define _ADC_CTRL_OSRSEL_OSR512 0x00000008UL /**< Mode OSR512 for ADC_CTRL */\r
+#define _ADC_CTRL_OSRSEL_OSR1024 0x00000009UL /**< Mode OSR1024 for ADC_CTRL */\r
+#define _ADC_CTRL_OSRSEL_OSR2048 0x0000000AUL /**< Mode OSR2048 for ADC_CTRL */\r
+#define _ADC_CTRL_OSRSEL_OSR4096 0x0000000BUL /**< Mode OSR4096 for ADC_CTRL */\r
+\r
+/** Bit fields for ADC CMD */\r
+#define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */\r
+#define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */\r
+#define ADC_CMD_SINGLESTART (1 << 0) /**< Single Conversion Start */\r
+#define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */\r
+#define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */\r
+#define ADC_CMD_SINGLESTART_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_CMD */\r
+#define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */\r
+#define ADC_CMD_SINGLESTOP (1 << 1) /**< Single Conversion Stop */\r
+#define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */\r
+#define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */\r
+#define ADC_CMD_SINGLESTOP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_CMD */\r
+#define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */\r
+#define ADC_CMD_SCANSTART (1 << 2) /**< Scan Sequence Start */\r
+#define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */\r
+#define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */\r
+#define ADC_CMD_SCANSTART_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for ADC_CMD */\r
+#define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */\r
+#define ADC_CMD_SCANSTOP (1 << 3) /**< Scan Sequence Stop */\r
+#define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */\r
+#define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */\r
+#define ADC_CMD_SCANSTOP_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for ADC_CMD */\r
+#define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */\r
+\r
+/** Bit fields for ADC STATUS */\r
+#define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */\r
+#define _ADC_STATUS_MASK 0x07031303UL /**< Mask for ADC_STATUS */\r
+#define ADC_STATUS_SINGLEACT (1 << 0) /**< Single Conversion Active */\r
+#define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */\r
+#define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */\r
+#define ADC_STATUS_SINGLEACT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+#define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SCANACT (1 << 1) /**< Scan Conversion Active */\r
+#define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */\r
+#define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */\r
+#define ADC_STATUS_SCANACT_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+#define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SINGLEREFWARM (1 << 8) /**< Single Reference Warmed Up */\r
+#define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */\r
+#define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */\r
+#define ADC_STATUS_SINGLEREFWARM_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+#define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SCANREFWARM (1 << 9) /**< Scan Reference Warmed Up */\r
+#define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */\r
+#define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */\r
+#define ADC_STATUS_SCANREFWARM_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+#define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_WARM (1 << 12) /**< ADC Warmed Up */\r
+#define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */\r
+#define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */\r
+#define ADC_STATUS_WARM_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+#define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SINGLEDV (1 << 16) /**< Single Sample Data Valid */\r
+#define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */\r
+#define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */\r
+#define ADC_STATUS_SINGLEDV_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+#define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SCANDV (1 << 17) /**< Scan Data Valid */\r
+#define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */\r
+#define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */\r
+#define ADC_STATUS_SCANDV_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+#define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define _ADC_STATUS_SCANDATASRC_SHIFT 24 /**< Shift value for ADC_SCANDATASRC */\r
+#define _ADC_STATUS_SCANDATASRC_MASK 0x7000000UL /**< Bit mask for ADC_SCANDATASRC */\r
+#define ADC_STATUS_SCANDATASRC_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for ADC_STATUS */\r
+#define ADC_STATUS_SCANDATASRC_CHANNEL0 (0x00000000UL << 24) /**< Shifted mode CHANNEL0 for ADC_STATUS */\r
+#define ADC_STATUS_SCANDATASRC_CHANNEL1 (0x00000001UL << 24) /**< Shifted mode CHANNEL1 for ADC_STATUS */\r
+#define ADC_STATUS_SCANDATASRC_CHANNEL2 (0x00000002UL << 24) /**< Shifted mode CHANNEL2 for ADC_STATUS */\r
+#define ADC_STATUS_SCANDATASRC_CHANNEL3 (0x00000003UL << 24) /**< Shifted mode CHANNEL3 for ADC_STATUS */\r
+#define ADC_STATUS_SCANDATASRC_CHANNEL4 (0x00000004UL << 24) /**< Shifted mode CHANNEL4 for ADC_STATUS */\r
+#define ADC_STATUS_SCANDATASRC_CHANNEL5 (0x00000005UL << 24) /**< Shifted mode CHANNEL5 for ADC_STATUS */\r
+#define ADC_STATUS_SCANDATASRC_CHANNEL6 (0x00000006UL << 24) /**< Shifted mode CHANNEL6 for ADC_STATUS */\r
+#define ADC_STATUS_SCANDATASRC_CHANNEL7 (0x00000007UL << 24) /**< Shifted mode CHANNEL7 for ADC_STATUS */\r
+#define _ADC_STATUS_SCANDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */\r
+#define _ADC_STATUS_SCANDATASRC_CHANNEL0 0x00000000UL /**< Mode CHANNEL0 for ADC_STATUS */\r
+#define _ADC_STATUS_SCANDATASRC_CHANNEL1 0x00000001UL /**< Mode CHANNEL1 for ADC_STATUS */\r
+#define _ADC_STATUS_SCANDATASRC_CHANNEL2 0x00000002UL /**< Mode CHANNEL2 for ADC_STATUS */\r
+#define _ADC_STATUS_SCANDATASRC_CHANNEL3 0x00000003UL /**< Mode CHANNEL3 for ADC_STATUS */\r
+#define _ADC_STATUS_SCANDATASRC_CHANNEL4 0x00000004UL /**< Mode CHANNEL4 for ADC_STATUS */\r
+#define _ADC_STATUS_SCANDATASRC_CHANNEL5 0x00000005UL /**< Mode CHANNEL5 for ADC_STATUS */\r
+#define _ADC_STATUS_SCANDATASRC_CHANNEL6 0x00000006UL /**< Mode CHANNEL6 for ADC_STATUS */\r
+#define _ADC_STATUS_SCANDATASRC_CHANNEL7 0x00000007UL /**< Mode CHANNEL7 for ADC_STATUS */\r
+\r
+/** Bit fields for ADC SINGLECTRL */\r
+#define _ADC_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_MASK 0x71F70F37UL /**< Mask for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEREP (1 << 0) /**< Single Sample Repetitive Mode */\r
+#define _ADC_SINGLECTRL_SINGLEREP_SHIFT 0 /**< Shift value for ADC_SINGLEREP */\r
+#define _ADC_SINGLECTRL_SINGLEREP_MASK 0x1UL /**< Bit mask for ADC_SINGLEREP */\r
+#define ADC_SINGLECTRL_SINGLEREP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEREP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEDIFF (1 << 1) /**< Single Sample Differential Mode */\r
+#define _ADC_SINGLECTRL_SINGLEDIFF_SHIFT 1 /**< Shift value for ADC_SINGLEDIFF */\r
+#define _ADC_SINGLECTRL_SINGLEDIFF_MASK 0x2UL /**< Bit mask for ADC_SINGLEDIFF */\r
+#define ADC_SINGLECTRL_SINGLEDIFF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEDIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEADJ (1 << 2) /**< Single Sample Result Adjustment */\r
+#define _ADC_SINGLECTRL_SINGLEADJ_SHIFT 2 /**< Shift value for ADC_SINGLEADJ */\r
+#define _ADC_SINGLECTRL_SINGLEADJ_MASK 0x4UL /**< Bit mask for ADC_SINGLEADJ */\r
+#define ADC_SINGLECTRL_SINGLEADJ_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEADJ_RIGHT (0x00000000UL << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEADJ_LEFT (0x00000001UL << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLERES_SHIFT 4 /**< Shift value for ADC_SINGLERES */\r
+#define _ADC_SINGLECTRL_SINGLERES_MASK 0x30UL /**< Bit mask for ADC_SINGLERES */\r
+#define ADC_SINGLECTRL_SINGLERES_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLERES_12BIT (0x00000000UL << 4) /**< Shifted mode 12BIT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLERES_8BIT (0x00000001UL << 4) /**< Shifted mode 8BIT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLERES_6BIT (0x00000002UL << 4) /**< Shifted mode 6BIT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLERES_OS (0x00000003UL << 4) /**< Shifted mode OS for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLERES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLERES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLERES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLERES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLERES_OS 0x00000003UL /**< Mode OS for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_SHIFT 8 /**< Shift value for ADC_SINGLESEL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_MASK 0xF00UL /**< Bit mask for ADC_SINGLESEL */\r
+#define ADC_SINGLECTRL_SINGLESEL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLESEL_CHANNEL0 (0x00000000UL << 8) /**< Shifted mode CHANNEL0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLESEL_CHANNEL1 (0x00000001UL << 8) /**< Shifted mode CHANNEL1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLESEL_CHANNEL2 (0x00000002UL << 8) /**< Shifted mode CHANNEL2 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLESEL_CHANNEL3 (0x00000003UL << 8) /**< Shifted mode CHANNEL3 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLESEL_CHANNEL4 (0x00000004UL << 8) /**< Shifted mode CHANNEL4 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLESEL_CHANNEL5 (0x00000005UL << 8) /**< Shifted mode CHANNEL5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLESEL_CHANNEL6 (0x00000006UL << 8) /**< Shifted mode CHANNEL6 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLESEL_CHANNEL7 (0x00000007UL << 8) /**< Shifted mode CHANNEL7 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLESEL_CHANNEL8 (0x00000008UL << 8) /**< Shifted mode CHANNEL8 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLESEL_CHANNEL9 (0x00000009UL << 8) /**< Shifted mode CHANNEL9 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLESEL_CHANNEL10 (0x0000000AUL << 8) /**< Shifted mode CHANNEL10 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLESEL_CHANNEL11 (0x0000000BUL << 8) /**< Shifted mode CHANNEL11 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLESEL_CHANNEL12 (0x0000000CUL << 8) /**< Shifted mode CHANNEL12 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLESEL_CHANNEL13 (0x0000000DUL << 8) /**< Shifted mode CHANNEL13 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLESEL_CHANNEL14 (0x0000000EUL << 8) /**< Shifted mode CHANNEL14 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL0 0x00000000UL /**< Mode CHANNEL0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL1 0x00000001UL /**< Mode CHANNEL1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL2 0x00000002UL /**< Mode CHANNEL2 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL3 0x00000003UL /**< Mode CHANNEL3 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL4 0x00000004UL /**< Mode CHANNEL4 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL5 0x00000005UL /**< Mode CHANNEL5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL6 0x00000006UL /**< Mode CHANNEL6 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL7 0x00000007UL /**< Mode CHANNEL7 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL8 0x00000008UL /**< Mode CHANNEL8 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL9 0x00000009UL /**< Mode CHANNEL9 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL10 0x0000000AUL /**< Mode CHANNEL10 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL11 0x0000000BUL /**< Mode CHANNEL11 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL12 0x0000000CUL /**< Mode CHANNEL12 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL13 0x0000000DUL /**< Mode CHANNEL13 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLESEL_CHANNEL14 0x0000000EUL /**< Mode CHANNEL14 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEREF_SHIFT 16 /**< Shift value for ADC_SINGLEREF */\r
+#define _ADC_SINGLECTRL_SINGLEREF_MASK 0x70000UL /**< Bit mask for ADC_SINGLEREF */\r
+#define ADC_SINGLECTRL_SINGLEREF_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEREF_1V25 (0x00000000UL << 16) /**< Shifted mode 1V25 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEREF_2V5 (0x00000001UL << 16) /**< Shifted mode 2V5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEREF_VDD (0x00000002UL << 16) /**< Shifted mode VDD for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEREF_5VDIFF (0x00000003UL << 16) /**< Shifted mode 5VDIFF for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEREF_EXTSINGLE (0x00000004UL << 16) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEREF_EXTDIFF (0x00000005UL << 16) /**< Shifted mode EXTDIFF for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEREF_2XVDDVSS (0x00000006UL << 16) /**< Shifted mode 2XVDDVSS for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEREF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEREF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEREF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEREF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEREF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEREF_EXTDIFF 0x00000005UL /**< Mode EXTDIFF for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEREF_2XVDDVSS 0x00000006UL /**< Mode 2XVDDVSS for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEAT_SHIFT 20 /**< Shift value for ADC_SINGLEAT */\r
+#define _ADC_SINGLECTRL_SINGLEAT_MASK 0xF00000UL /**< Bit mask for ADC_SINGLEAT */\r
+#define ADC_SINGLECTRL_SINGLEAT_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEAT_1CYCLE (0x00000000UL << 20) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEAT_2CYCLES (0x00000001UL << 20) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEAT_4CYCLES (0x00000002UL << 20) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEAT_8CYCLES (0x00000003UL << 20) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEAT_16CYCLES (0x00000004UL << 20) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEAT_32CYCLES (0x00000005UL << 20) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEAT_64CYCLES (0x00000006UL << 20) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEAT_128CYCLES (0x00000007UL << 20) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEAT_256CYCLES (0x00000008UL << 20) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEAT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEAT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEAT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEAT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEAT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEAT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEAT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEAT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEAT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEPRSEN (1 << 24) /**< Single Sample PRS Trigger Enable */\r
+#define _ADC_SINGLECTRL_SINGLEPRSEN_SHIFT 24 /**< Shift value for ADC_SINGLEPRSEN */\r
+#define _ADC_SINGLECTRL_SINGLEPRSEN_MASK 0x1000000UL /**< Bit mask for ADC_SINGLEPRSEN */\r
+#define ADC_SINGLECTRL_SINGLEPRSEN_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEPRSSEL_SHIFT 28 /**< Shift value for ADC_SINGLEPRSSEL */\r
+#define _ADC_SINGLECTRL_SINGLEPRSSEL_MASK 0x70000000UL /**< Bit mask for ADC_SINGLEPRSSEL */\r
+#define ADC_SINGLECTRL_SINGLEPRSSEL_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH0 (0x00000000UL << 28) /**< Shifted mode PRSCH0 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH1 (0x00000001UL << 28) /**< Shifted mode PRSCH1 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH2 (0x00000002UL << 28) /**< Shifted mode PRSCH2 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH3 (0x00000003UL << 28) /**< Shifted mode PRSCH3 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH4 (0x00000004UL << 28) /**< Shifted mode PRSCH4 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH5 (0x00000005UL << 28) /**< Shifted mode PRSCH5 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH6 (0x00000006UL << 28) /**< Shifted mode PRSCH6 for ADC_SINGLECTRL */\r
+#define ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH7 (0x00000007UL << 28) /**< Shifted mode PRSCH7 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRL */\r
+#define _ADC_SINGLECTRL_SINGLEPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRL */\r
+\r
+/** Bit fields for ADC SCANCTRL */\r
+#define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_MASK 0x71F7FF37UL /**< Mask for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANREP (1 << 0) /**< Scan Sequence Repetitive Mode */\r
+#define _ADC_SCANCTRL_SCANREP_SHIFT 0 /**< Shift value for ADC_SCANREP */\r
+#define _ADC_SCANCTRL_SCANREP_MASK 0x1UL /**< Bit mask for ADC_SCANREP */\r
+#define ADC_SCANCTRL_SCANREP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANREP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANDIFF (1 << 1) /**< Scan Sequence Differential Mode */\r
+#define _ADC_SCANCTRL_SCANDIFF_SHIFT 1 /**< Shift value for ADC_SCANDIFF */\r
+#define _ADC_SCANCTRL_SCANDIFF_MASK 0x2UL /**< Bit mask for ADC_SCANDIFF */\r
+#define ADC_SCANCTRL_SCANDIFF_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANDIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANADJ (1 << 2) /**< Scan Sequence Result Adjustment */\r
+#define _ADC_SCANCTRL_SCANADJ_SHIFT 2 /**< Shift value for ADC_SCANADJ */\r
+#define _ADC_SCANCTRL_SCANADJ_MASK 0x4UL /**< Bit mask for ADC_SCANADJ */\r
+#define ADC_SCANCTRL_SCANADJ_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANADJ_RIGHT (0x00000000UL << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANADJ_LEFT (0x00000001UL << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANRES_SHIFT 4 /**< Shift value for ADC_SCANRES */\r
+#define _ADC_SCANCTRL_SCANRES_MASK 0x30UL /**< Bit mask for ADC_SCANRES */\r
+#define ADC_SCANCTRL_SCANRES_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANRES_12BIT (0x00000000UL << 4) /**< Shifted mode 12BIT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANRES_8BIT (0x00000001UL << 4) /**< Shifted mode 8BIT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANRES_6BIT (0x00000002UL << 4) /**< Shifted mode 6BIT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANRES_OS (0x00000003UL << 4) /**< Shifted mode OS for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANRES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANRES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANRES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANRES_OS 0x00000003UL /**< Mode OS for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANMASK_SHIFT 8 /**< Shift value for ADC_SCANMASK */\r
+#define _ADC_SCANCTRL_SCANMASK_MASK 0xFF00UL /**< Bit mask for ADC_SCANMASK */\r
+#define ADC_SCANCTRL_SCANMASK_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANMASK_CHANNEL0 (0x00000000UL << 8) /**< Shifted mode CHANNEL0 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANMASK_CHANNEL1 (0x00000001UL << 8) /**< Shifted mode CHANNEL1 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANMASK_CHANNEL2 (0x00000002UL << 8) /**< Shifted mode CHANNEL2 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANMASK_CHANNEL3 (0x00000003UL << 8) /**< Shifted mode CHANNEL3 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANMASK_CHANNEL4 (0x00000004UL << 8) /**< Shifted mode CHANNEL4 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANMASK_CHANNEL5 (0x00000005UL << 8) /**< Shifted mode CHANNEL5 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANMASK_CHANNEL6 (0x00000006UL << 8) /**< Shifted mode CHANNEL6 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANMASK_CHANNEL7 (0x00000007UL << 8) /**< Shifted mode CHANNEL7 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANMASK_CHANNEL0 0x00000000UL /**< Mode CHANNEL0 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANMASK_CHANNEL1 0x00000001UL /**< Mode CHANNEL1 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANMASK_CHANNEL2 0x00000002UL /**< Mode CHANNEL2 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANMASK_CHANNEL3 0x00000003UL /**< Mode CHANNEL3 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANMASK_CHANNEL4 0x00000004UL /**< Mode CHANNEL4 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANMASK_CHANNEL5 0x00000005UL /**< Mode CHANNEL5 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANMASK_CHANNEL6 0x00000006UL /**< Mode CHANNEL6 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANMASK_CHANNEL7 0x00000007UL /**< Mode CHANNEL7 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANREF_SHIFT 16 /**< Shift value for ADC_SCANREF */\r
+#define _ADC_SCANCTRL_SCANREF_MASK 0x70000UL /**< Bit mask for ADC_SCANREF */\r
+#define ADC_SCANCTRL_SCANREF_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANREF_1V25 (0x00000000UL << 16) /**< Shifted mode 1V25 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANREF_2V5 (0x00000001UL << 16) /**< Shifted mode 2V5 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANREF_VDD (0x00000002UL << 16) /**< Shifted mode VDD for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANREF_5VDIFF (0x00000003UL << 16) /**< Shifted mode 5VDIFF for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANREF_EXTSINGLE (0x00000004UL << 16) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANREF_EXTDIFF (0x00000005UL << 16) /**< Shifted mode EXTDIFF for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANREF_2XVDDVSS (0x00000006UL << 16) /**< Shifted mode 2XVDDVSS for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANREF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANREF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANREF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANREF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANREF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANREF_EXTDIFF 0x00000005UL /**< Mode EXTDIFF for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANREF_2XVDDVSS 0x00000006UL /**< Mode 2XVDDVSS for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANAT_SHIFT 20 /**< Shift value for ADC_SCANAT */\r
+#define _ADC_SCANCTRL_SCANAT_MASK 0xF00000UL /**< Bit mask for ADC_SCANAT */\r
+#define ADC_SCANCTRL_SCANAT_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANAT_1CYCLE (0x00000000UL << 20) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANAT_2CYCLES (0x00000001UL << 20) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANAT_4CYCLES (0x00000002UL << 20) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANAT_8CYCLES (0x00000003UL << 20) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANAT_16CYCLES (0x00000004UL << 20) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANAT_32CYCLES (0x00000005UL << 20) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANAT_64CYCLES (0x00000006UL << 20) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANAT_128CYCLES (0x00000007UL << 20) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANAT_256CYCLES (0x00000008UL << 20) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANAT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANAT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANAT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANAT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANAT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANAT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANAT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANAT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANAT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANPRSEN (1 << 24) /**< Scan Sequence PRS Trigger Enable */\r
+#define _ADC_SCANCTRL_SCANPRSEN_SHIFT 24 /**< Shift value for ADC_SCANPRSEN */\r
+#define _ADC_SCANCTRL_SCANPRSEN_MASK 0x1000000UL /**< Bit mask for ADC_SCANPRSEN */\r
+#define ADC_SCANCTRL_SCANPRSEN_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANPRSSEL_SHIFT 28 /**< Shift value for ADC_SCANPRSSEL */\r
+#define _ADC_SCANCTRL_SCANPRSSEL_MASK 0x70000000UL /**< Bit mask for ADC_SCANPRSSEL */\r
+#define ADC_SCANCTRL_SCANPRSSEL_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANPRSSEL_PRSCH0 (0x00000000UL << 28) /**< Shifted mode PRSCH0 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANPRSSEL_PRSCH1 (0x00000001UL << 28) /**< Shifted mode PRSCH1 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANPRSSEL_PRSCH2 (0x00000002UL << 28) /**< Shifted mode PRSCH2 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANPRSSEL_PRSCH3 (0x00000003UL << 28) /**< Shifted mode PRSCH3 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANPRSSEL_PRSCH4 (0x00000004UL << 28) /**< Shifted mode PRSCH4 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANPRSSEL_PRSCH5 (0x00000005UL << 28) /**< Shifted mode PRSCH5 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANPRSSEL_PRSCH6 (0x00000006UL << 28) /**< Shifted mode PRSCH6 for ADC_SCANCTRL */\r
+#define ADC_SCANCTRL_SCANPRSSEL_PRSCH7 (0x00000007UL << 28) /**< Shifted mode PRSCH7 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRL */\r
+#define _ADC_SCANCTRL_SCANPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRL */\r
+\r
+/** Bit fields for ADC IEN */\r
+#define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */\r
+#define _ADC_IEN_MASK 0x00000303UL /**< Mask for ADC_IEN */\r
+#define ADC_IEN_SINGLE (1 << 0) /**< Single Conversion Complete Interrupt Enable */\r
+#define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */\r
+#define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */\r
+#define ADC_IEN_SINGLE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_IEN */\r
+#define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SCAN (1 << 1) /**< Scan Conversion Complete Interrupt Enable */\r
+#define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */\r
+#define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */\r
+#define ADC_IEN_SCAN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_IEN */\r
+#define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SINGLEOF (1 << 8) /**< Single Result Overflow Interrupt Enable */\r
+#define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */\r
+#define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */\r
+#define ADC_IEN_SINGLEOF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_IEN */\r
+#define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */\r
+#define ADC_IEN_SCANOF (1 << 9) /**< Scan Result Overflow Interrupt Enable */\r
+#define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */\r
+#define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */\r
+#define ADC_IEN_SCANOF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for ADC_IEN */\r
+#define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */\r
+\r
+/** Bit fields for ADC IF */\r
+#define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */\r
+#define _ADC_IF_MASK 0x00000303UL /**< Mask for ADC_IF */\r
+#define ADC_IF_SINGLE (1 << 0) /**< Single Conversion Complete Interrupt Flag */\r
+#define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */\r
+#define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */\r
+#define ADC_IF_SINGLE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_IF */\r
+#define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SCAN (1 << 1) /**< Scan Conversion Complete Interrupt Flag */\r
+#define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */\r
+#define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */\r
+#define ADC_IF_SCAN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_IF */\r
+#define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SINGLEOF (1 << 8) /**< Single Result Overflow Interrupt Flag */\r
+#define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */\r
+#define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */\r
+#define ADC_IF_SINGLEOF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_IF */\r
+#define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */\r
+#define ADC_IF_SCANOF (1 << 9) /**< Scan Result Overflow Interrupt Flag */\r
+#define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */\r
+#define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */\r
+#define ADC_IF_SCANOF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for ADC_IF */\r
+#define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */\r
+\r
+/** Bit fields for ADC IFS */\r
+#define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */\r
+#define _ADC_IFS_MASK 0x00000303UL /**< Mask for ADC_IFS */\r
+#define ADC_IFS_SINGLE (1 << 0) /**< Single Conversion Complete Interrupt Flag Set */\r
+#define _ADC_IFS_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */\r
+#define _ADC_IFS_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */\r
+#define ADC_IFS_SINGLE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_IFS */\r
+#define _ADC_IFS_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_SCAN (1 << 1) /**< Scan Conversion Complete Interrupt Flag Set */\r
+#define _ADC_IFS_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */\r
+#define _ADC_IFS_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */\r
+#define ADC_IFS_SCAN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_IFS */\r
+#define _ADC_IFS_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_SINGLEOF (1 << 8) /**< Single Result Overflow Interrupt Flag Set */\r
+#define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */\r
+#define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */\r
+#define ADC_IFS_SINGLEOF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_IFS */\r
+#define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */\r
+#define ADC_IFS_SCANOF (1 << 9) /**< Scan Result Overflow Interrupt Flag Set */\r
+#define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */\r
+#define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */\r
+#define ADC_IFS_SCANOF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for ADC_IFS */\r
+#define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */\r
+\r
+/** Bit fields for ADC IFC */\r
+#define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */\r
+#define _ADC_IFC_MASK 0x00000303UL /**< Mask for ADC_IFC */\r
+#define ADC_IFC_SINGLE (1 << 0) /**< Single Conversion Complete Interrupt Flag Clear */\r
+#define _ADC_IFC_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */\r
+#define _ADC_IFC_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */\r
+#define ADC_IFC_SINGLE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_IFC */\r
+#define _ADC_IFC_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_SCAN (1 << 1) /**< Scan Conversion Complete Interrupt Flag Clear */\r
+#define _ADC_IFC_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */\r
+#define _ADC_IFC_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */\r
+#define ADC_IFC_SCAN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ADC_IFC */\r
+#define _ADC_IFC_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_SINGLEOF (1 << 8) /**< Single Result Overflow Interrupt Flag Clear */\r
+#define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */\r
+#define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */\r
+#define ADC_IFC_SINGLEOF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ADC_IFC */\r
+#define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */\r
+#define ADC_IFC_SCANOF (1 << 9) /**< Scan Result Overflow Interrupt Flag Clear */\r
+#define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */\r
+#define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */\r
+#define ADC_IFC_SCANOF_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for ADC_IFC */\r
+#define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */\r
+\r
+/** Bit fields for ADC SINGLEDATA */\r
+#define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */\r
+#define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */\r
+#define _ADC_SINGLEDATA_SINGLEDATA_SHIFT 0 /**< Shift value for ADC_SINGLEDATA */\r
+#define _ADC_SINGLEDATA_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SINGLEDATA */\r
+#define ADC_SINGLEDATA_SINGLEDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */\r
+#define _ADC_SINGLEDATA_SINGLEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */\r
+\r
+/** Bit fields for ADC SCANDATA */\r
+#define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */\r
+#define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */\r
+#define _ADC_SCANDATA_SCANDATA_SHIFT 0 /**< Shift value for ADC_SCANDATA */\r
+#define _ADC_SCANDATA_SCANDATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANDATA */\r
+#define ADC_SCANDATA_SCANDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */\r
+#define _ADC_SCANDATA_SCANDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */\r
+\r
+/** Bit fields for ADC SINGLEDATAP */\r
+#define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */\r
+#define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */\r
+#define _ADC_SINGLEDATAP_SINGLEDATA_SHIFT 0 /**< Shift value for ADC_SINGLEDATA */\r
+#define _ADC_SINGLEDATAP_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SINGLEDATA */\r
+#define ADC_SINGLEDATAP_SINGLEDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */\r
+#define _ADC_SINGLEDATAP_SINGLEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */\r
+\r
+/** Bit fields for ADC SCANDATAP */\r
+#define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */\r
+#define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */\r
+#define _ADC_SCANDATAP_SCANDATAP_SHIFT 0 /**< Shift value for ADC_SCANDATAP */\r
+#define _ADC_SCANDATAP_SCANDATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANDATAP */\r
+#define ADC_SCANDATAP_SCANDATAP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */\r
+#define _ADC_SCANDATAP_SCANDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */\r
+\r
+/** Bit fields for ADC CAL */\r
+#define _ADC_CAL_RESETVALUE 0x3F003F00UL /**< Default value for ADC_CAL */\r
+#define _ADC_CAL_MASK 0x7F7F7F7FUL /**< Mask for ADC_CAL */\r
+#define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */\r
+#define _ADC_CAL_SINGLEOFFSET_MASK 0x7FUL /**< Bit mask for ADC_SINGLEOFFSET */\r
+#define ADC_CAL_SINGLEOFFSET_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_CAL */\r
+#define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */\r
+#define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */\r
+#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */\r
+#define ADC_CAL_SINGLEGAIN_DEFAULT (0x0000003FUL << 8) /**< Shifted mode DEFAULT for ADC_CAL */\r
+#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */\r
+#define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */\r
+#define _ADC_CAL_SCANOFFSET_MASK 0x7F0000UL /**< Bit mask for ADC_SCANOFFSET */\r
+#define ADC_CAL_SCANOFFSET_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for ADC_CAL */\r
+#define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */\r
+#define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */\r
+#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */\r
+#define ADC_CAL_SCANGAIN_DEFAULT (0x0000003FUL << 24) /**< Shifted mode DEFAULT for ADC_CAL */\r
+#define _ADC_CAL_SCANGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */\r
+\r
+/** Bit fields for ADC ROUTE */\r
+#define _ADC_ROUTE_RESETVALUE 0x00000000UL /**< Default value for ADC_ROUTE */\r
+#define _ADC_ROUTE_MASK 0x00000001UL /**< Mask for ADC_ROUTE */\r
+#define ADC_ROUTE_VCMPEN (1 << 0) /**< VCM Pin Output Enable */\r
+#define _ADC_ROUTE_VCMPEN_SHIFT 0 /**< Shift value for ADC_VCMPEN */\r
+#define _ADC_ROUTE_VCMPEN_MASK 0x1UL /**< Bit mask for ADC_VCMPEN */\r
+#define ADC_ROUTE_VCMPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ADC_ROUTE */\r
+#define _ADC_ROUTE_VCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_ROUTE */\r
+\r
+/** Bit fields for ADC BIASPROG */\r
+#define _ADC_BIASPROG_RESETVALUE 0x00000747UL /**< Default value for ADC_BIASPROG */\r
+#define _ADC_BIASPROG_MASK 0x00000F4FUL /**< Mask for ADC_BIASPROG */\r
+#define _ADC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for ADC_BIASPROG */\r
+#define _ADC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for ADC_BIASPROG */\r
+#define ADC_BIASPROG_BIASPROG_DEFAULT (0x00000007UL << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */\r
+#define _ADC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */\r
+#define ADC_BIASPROG_HALFBIAS (1 << 6) /**< Half Bias Current */\r
+#define _ADC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for ADC_HALFBIAS */\r
+#define _ADC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for ADC_HALFBIAS */\r
+#define ADC_BIASPROG_HALFBIAS_DEFAULT (0x00000001UL << 6) /**< Shifted mode DEFAULT for ADC_BIASPROG */\r
+#define _ADC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_BIASPROG */\r
+#define _ADC_BIASPROG_COMPBIAS_SHIFT 8 /**< Shift value for ADC_COMPBIAS */\r
+#define _ADC_BIASPROG_COMPBIAS_MASK 0xF00UL /**< Bit mask for ADC_COMPBIAS */\r
+#define ADC_BIASPROG_COMPBIAS_DEFAULT (0x00000007UL << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */\r
+#define _ADC_BIASPROG_COMPBIAS_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_DAC\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for DAC CTRL */\r
+#define _DAC_CTRL_RESETVALUE 0x00000010UL /**< Default value for DAC_CTRL */\r
+#define _DAC_CTRL_MASK 0x0037D3FFUL /**< Mask for DAC_CTRL */\r
+#define DAC_CTRL_DIFF (1 << 0) /**< Differential Mode */\r
+#define _DAC_CTRL_DIFF_SHIFT 0 /**< Shift value for DAC_DIFF */\r
+#define _DAC_CTRL_DIFF_MASK 0x1UL /**< Bit mask for DAC_DIFF */\r
+#define DAC_CTRL_DIFF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_CTRL */\r
+#define _DAC_CTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */\r
+#define DAC_CTRL_SINEMODE (1 << 1) /**< Sine Mode */\r
+#define _DAC_CTRL_SINEMODE_SHIFT 1 /**< Shift value for DAC_SINEMODE */\r
+#define _DAC_CTRL_SINEMODE_MASK 0x2UL /**< Bit mask for DAC_SINEMODE */\r
+#define DAC_CTRL_SINEMODE_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_CTRL */\r
+#define _DAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */\r
+#define _DAC_CTRL_CONVMODE_SHIFT 2 /**< Shift value for DAC_CONVMODE */\r
+#define _DAC_CTRL_CONVMODE_MASK 0xCUL /**< Bit mask for DAC_CONVMODE */\r
+#define DAC_CTRL_CONVMODE_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for DAC_CTRL */\r
+#define DAC_CTRL_CONVMODE_CONTINUOUS (0x00000000UL << 2) /**< Shifted mode CONTINUOUS for DAC_CTRL */\r
+#define DAC_CTRL_CONVMODE_SAMPLEHOLD (0x00000001UL << 2) /**< Shifted mode SAMPLEHOLD for DAC_CTRL */\r
+#define DAC_CTRL_CONVMODE_SAMPLEOFF (0x00000002UL << 2) /**< Shifted mode SAMPLEOFF for DAC_CTRL */\r
+#define _DAC_CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */\r
+#define _DAC_CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for DAC_CTRL */\r
+#define _DAC_CTRL_CONVMODE_SAMPLEHOLD 0x00000001UL /**< Mode SAMPLEHOLD for DAC_CTRL */\r
+#define _DAC_CTRL_CONVMODE_SAMPLEOFF 0x00000002UL /**< Mode SAMPLEOFF for DAC_CTRL */\r
+#define _DAC_CTRL_OUTMODE_SHIFT 4 /**< Shift value for DAC_OUTMODE */\r
+#define _DAC_CTRL_OUTMODE_MASK 0x30UL /**< Bit mask for DAC_OUTMODE */\r
+#define DAC_CTRL_OUTMODE_DISABLE (0x00000000UL << 4) /**< Shifted mode DISABLE for DAC_CTRL */\r
+#define DAC_CTRL_OUTMODE_DEFAULT (0x00000001UL << 4) /**< Shifted mode DEFAULT for DAC_CTRL */\r
+#define DAC_CTRL_OUTMODE_PIN (0x00000001UL << 4) /**< Shifted mode PIN for DAC_CTRL */\r
+#define DAC_CTRL_OUTMODE_ADC (0x00000002UL << 4) /**< Shifted mode ADC for DAC_CTRL */\r
+#define DAC_CTRL_OUTMODE_PINADC (0x00000003UL << 4) /**< Shifted mode PINADC for DAC_CTRL */\r
+#define _DAC_CTRL_OUTMODE_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_CTRL */\r
+#define _DAC_CTRL_OUTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_CTRL */\r
+#define _DAC_CTRL_OUTMODE_PIN 0x00000001UL /**< Mode PIN for DAC_CTRL */\r
+#define _DAC_CTRL_OUTMODE_ADC 0x00000002UL /**< Mode ADC for DAC_CTRL */\r
+#define _DAC_CTRL_OUTMODE_PINADC 0x00000003UL /**< Mode PINADC for DAC_CTRL */\r
+#define DAC_CTRL_OUTENPRS (1 << 6) /**< PRS Controlled Output Enable */\r
+#define _DAC_CTRL_OUTENPRS_SHIFT 6 /**< Shift value for DAC_OUTENPRS */\r
+#define _DAC_CTRL_OUTENPRS_MASK 0x40UL /**< Bit mask for DAC_OUTENPRS */\r
+#define DAC_CTRL_OUTENPRS_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for DAC_CTRL */\r
+#define _DAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */\r
+#define DAC_CTRL_CH0PRESCRST (1 << 7) /**< Channel 0 Start Reset Prescaler */\r
+#define _DAC_CTRL_CH0PRESCRST_SHIFT 7 /**< Shift value for DAC_CH0PRESCRST */\r
+#define _DAC_CTRL_CH0PRESCRST_MASK 0x80UL /**< Bit mask for DAC_CH0PRESCRST */\r
+#define DAC_CTRL_CH0PRESCRST_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for DAC_CTRL */\r
+#define _DAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */\r
+#define _DAC_CTRL_REFSEL_SHIFT 8 /**< Shift value for DAC_REFSEL */\r
+#define _DAC_CTRL_REFSEL_MASK 0x300UL /**< Bit mask for DAC_REFSEL */\r
+#define DAC_CTRL_REFSEL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for DAC_CTRL */\r
+#define DAC_CTRL_REFSEL_1V25 (0x00000000UL << 8) /**< Shifted mode 1V25 for DAC_CTRL */\r
+#define DAC_CTRL_REFSEL_2V5 (0x00000001UL << 8) /**< Shifted mode 2V5 for DAC_CTRL */\r
+#define DAC_CTRL_REFSEL_VDD (0x00000002UL << 8) /**< Shifted mode VDD for DAC_CTRL */\r
+#define _DAC_CTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */\r
+#define _DAC_CTRL_REFSEL_1V25 0x00000000UL /**< Mode 1V25 for DAC_CTRL */\r
+#define _DAC_CTRL_REFSEL_2V5 0x00000001UL /**< Mode 2V5 for DAC_CTRL */\r
+#define _DAC_CTRL_REFSEL_VDD 0x00000002UL /**< Mode VDD for DAC_CTRL */\r
+#define DAC_CTRL_LPFEN (1 << 12) /**< Low Pass Filter Enable */\r
+#define _DAC_CTRL_LPFEN_SHIFT 12 /**< Shift value for DAC_LPFEN */\r
+#define _DAC_CTRL_LPFEN_MASK 0x1000UL /**< Bit mask for DAC_LPFEN */\r
+#define DAC_CTRL_LPFEN_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for DAC_CTRL */\r
+#define _DAC_CTRL_LPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */\r
+#define _DAC_CTRL_LPFFREQ_SHIFT 14 /**< Shift value for DAC_LPFFREQ */\r
+#define _DAC_CTRL_LPFFREQ_MASK 0xC000UL /**< Bit mask for DAC_LPFFREQ */\r
+#define DAC_CTRL_LPFFREQ_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for DAC_CTRL */\r
+#define DAC_CTRL_LPFFREQ_FREQ0 (0x00000000UL << 14) /**< Shifted mode FREQ0 for DAC_CTRL */\r
+#define DAC_CTRL_LPFFREQ_FREQ1 (0x00000001UL << 14) /**< Shifted mode FREQ1 for DAC_CTRL */\r
+#define DAC_CTRL_LPFFREQ_FREQ2 (0x00000002UL << 14) /**< Shifted mode FREQ2 for DAC_CTRL */\r
+#define DAC_CTRL_LPFFREQ_FREQ3 (0x00000003UL << 14) /**< Shifted mode FREQ3 for DAC_CTRL */\r
+#define _DAC_CTRL_LPFFREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */\r
+#define _DAC_CTRL_LPFFREQ_FREQ0 0x00000000UL /**< Mode FREQ0 for DAC_CTRL */\r
+#define _DAC_CTRL_LPFFREQ_FREQ1 0x00000001UL /**< Mode FREQ1 for DAC_CTRL */\r
+#define _DAC_CTRL_LPFFREQ_FREQ2 0x00000002UL /**< Mode FREQ2 for DAC_CTRL */\r
+#define _DAC_CTRL_LPFFREQ_FREQ3 0x00000003UL /**< Mode FREQ3 for DAC_CTRL */\r
+#define _DAC_CTRL_PRESC_SHIFT 16 /**< Shift value for DAC_PRESC */\r
+#define _DAC_CTRL_PRESC_MASK 0x70000UL /**< Bit mask for DAC_PRESC */\r
+#define DAC_CTRL_PRESC_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for DAC_CTRL */\r
+#define DAC_CTRL_PRESC_NODIVISION (0x00000000UL << 16) /**< Shifted mode NODIVISION for DAC_CTRL */\r
+#define _DAC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */\r
+#define _DAC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for DAC_CTRL */\r
+#define _DAC_CTRL_REFRSEL_SHIFT 20 /**< Shift value for DAC_REFRSEL */\r
+#define _DAC_CTRL_REFRSEL_MASK 0x300000UL /**< Bit mask for DAC_REFRSEL */\r
+#define DAC_CTRL_REFRSEL_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for DAC_CTRL */\r
+#define DAC_CTRL_REFRSEL_8CYCLES (0x00000000UL << 20) /**< Shifted mode 8CYCLES for DAC_CTRL */\r
+#define DAC_CTRL_REFRSEL_16CYCLES (0x00000001UL << 20) /**< Shifted mode 16CYCLES for DAC_CTRL */\r
+#define DAC_CTRL_REFRSEL_32CYCLES (0x00000002UL << 20) /**< Shifted mode 32CYCLES for DAC_CTRL */\r
+#define DAC_CTRL_REFRSEL_64CYCLES (0x00000003UL << 20) /**< Shifted mode 64CYCLES for DAC_CTRL */\r
+#define _DAC_CTRL_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */\r
+#define _DAC_CTRL_REFRSEL_8CYCLES 0x00000000UL /**< Mode 8CYCLES for DAC_CTRL */\r
+#define _DAC_CTRL_REFRSEL_16CYCLES 0x00000001UL /**< Mode 16CYCLES for DAC_CTRL */\r
+#define _DAC_CTRL_REFRSEL_32CYCLES 0x00000002UL /**< Mode 32CYCLES for DAC_CTRL */\r
+#define _DAC_CTRL_REFRSEL_64CYCLES 0x00000003UL /**< Mode 64CYCLES for DAC_CTRL */\r
+\r
+/** Bit fields for DAC STATUS */\r
+#define _DAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DAC_STATUS */\r
+#define _DAC_STATUS_MASK 0x00000003UL /**< Mask for DAC_STATUS */\r
+#define DAC_STATUS_CH0DV (1 << 0) /**< Channel 0 Data Valid */\r
+#define _DAC_STATUS_CH0DV_SHIFT 0 /**< Shift value for DAC_CH0DV */\r
+#define _DAC_STATUS_CH0DV_MASK 0x1UL /**< Bit mask for DAC_CH0DV */\r
+#define DAC_STATUS_CH0DV_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_STATUS */\r
+#define _DAC_STATUS_CH0DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_STATUS */\r
+#define DAC_STATUS_CH1DV (1 << 1) /**< Channel 1 Data Valid */\r
+#define _DAC_STATUS_CH1DV_SHIFT 1 /**< Shift value for DAC_CH1DV */\r
+#define _DAC_STATUS_CH1DV_MASK 0x2UL /**< Bit mask for DAC_CH1DV */\r
+#define DAC_STATUS_CH1DV_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_STATUS */\r
+#define _DAC_STATUS_CH1DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_STATUS */\r
+\r
+/** Bit fields for DAC CH0CTRL */\r
+#define _DAC_CH0CTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_CH0CTRL */\r
+#define _DAC_CH0CTRL_MASK 0x00000077UL /**< Mask for DAC_CH0CTRL */\r
+#define DAC_CH0CTRL_CH0EN (1 << 0) /**< Channel 0 Enable */\r
+#define _DAC_CH0CTRL_CH0EN_SHIFT 0 /**< Shift value for DAC_CH0EN */\r
+#define _DAC_CH0CTRL_CH0EN_MASK 0x1UL /**< Bit mask for DAC_CH0EN */\r
+#define DAC_CH0CTRL_CH0EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_CH0CTRL */\r
+#define _DAC_CH0CTRL_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */\r
+#define DAC_CH0CTRL_CH0REFREN (1 << 1) /**< Channel 0 Automatic Refresh Enable */\r
+#define _DAC_CH0CTRL_CH0REFREN_SHIFT 1 /**< Shift value for DAC_CH0REFREN */\r
+#define _DAC_CH0CTRL_CH0REFREN_MASK 0x2UL /**< Bit mask for DAC_CH0REFREN */\r
+#define DAC_CH0CTRL_CH0REFREN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_CH0CTRL */\r
+#define _DAC_CH0CTRL_CH0REFREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */\r
+#define DAC_CH0CTRL_CH0PRSEN (1 << 2) /**< Channel 0 PRS Trigger Enable */\r
+#define _DAC_CH0CTRL_CH0PRSEN_SHIFT 2 /**< Shift value for DAC_CH0PRSEN */\r
+#define _DAC_CH0CTRL_CH0PRSEN_MASK 0x4UL /**< Bit mask for DAC_CH0PRSEN */\r
+#define DAC_CH0CTRL_CH0PRSEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for DAC_CH0CTRL */\r
+#define _DAC_CH0CTRL_CH0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */\r
+#define _DAC_CH0CTRL_CH0PRSSEL_SHIFT 4 /**< Shift value for DAC_CH0PRSSEL */\r
+#define _DAC_CH0CTRL_CH0PRSSEL_MASK 0x70UL /**< Bit mask for DAC_CH0PRSSEL */\r
+#define DAC_CH0CTRL_CH0PRSSEL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for DAC_CH0CTRL */\r
+#define DAC_CH0CTRL_CH0PRSSEL_PRSCH0 (0x00000000UL << 4) /**< Shifted mode PRSCH0 for DAC_CH0CTRL */\r
+#define DAC_CH0CTRL_CH0PRSSEL_PRSCH1 (0x00000001UL << 4) /**< Shifted mode PRSCH1 for DAC_CH0CTRL */\r
+#define DAC_CH0CTRL_CH0PRSSEL_PRSCH2 (0x00000002UL << 4) /**< Shifted mode PRSCH2 for DAC_CH0CTRL */\r
+#define DAC_CH0CTRL_CH0PRSSEL_PRSCH3 (0x00000003UL << 4) /**< Shifted mode PRSCH3 for DAC_CH0CTRL */\r
+#define DAC_CH0CTRL_CH0PRSSEL_PRSCH4 (0x00000004UL << 4) /**< Shifted mode PRSCH4 for DAC_CH0CTRL */\r
+#define DAC_CH0CTRL_CH0PRSSEL_PRSCH5 (0x00000005UL << 4) /**< Shifted mode PRSCH5 for DAC_CH0CTRL */\r
+#define DAC_CH0CTRL_CH0PRSSEL_PRSCH6 (0x00000006UL << 4) /**< Shifted mode PRSCH6 for DAC_CH0CTRL */\r
+#define DAC_CH0CTRL_CH0PRSSEL_PRSCH7 (0x00000007UL << 4) /**< Shifted mode PRSCH7 for DAC_CH0CTRL */\r
+#define _DAC_CH0CTRL_CH0PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */\r
+#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for DAC_CH0CTRL */\r
+#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for DAC_CH0CTRL */\r
+#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for DAC_CH0CTRL */\r
+#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for DAC_CH0CTRL */\r
+#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for DAC_CH0CTRL */\r
+#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for DAC_CH0CTRL */\r
+#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for DAC_CH0CTRL */\r
+#define _DAC_CH0CTRL_CH0PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for DAC_CH0CTRL */\r
+\r
+/** Bit fields for DAC CH1CTRL */\r
+#define _DAC_CH1CTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_CH1CTRL */\r
+#define _DAC_CH1CTRL_MASK 0x00000077UL /**< Mask for DAC_CH1CTRL */\r
+#define DAC_CH1CTRL_CH1EN (1 << 0) /**< Channel 1 Enable */\r
+#define _DAC_CH1CTRL_CH1EN_SHIFT 0 /**< Shift value for DAC_CH1EN */\r
+#define _DAC_CH1CTRL_CH1EN_MASK 0x1UL /**< Bit mask for DAC_CH1EN */\r
+#define DAC_CH1CTRL_CH1EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_CH1CTRL */\r
+#define _DAC_CH1CTRL_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */\r
+#define DAC_CH1CTRL_CH1REFREN (1 << 1) /**< Channel 1 Automatic Refresh Enable */\r
+#define _DAC_CH1CTRL_CH1REFREN_SHIFT 1 /**< Shift value for DAC_CH1REFREN */\r
+#define _DAC_CH1CTRL_CH1REFREN_MASK 0x2UL /**< Bit mask for DAC_CH1REFREN */\r
+#define DAC_CH1CTRL_CH1REFREN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_CH1CTRL */\r
+#define _DAC_CH1CTRL_CH1REFREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */\r
+#define DAC_CH1CTRL_CH1PRSEN (1 << 2) /**< Channel 1 PRS Trigger Enable */\r
+#define _DAC_CH1CTRL_CH1PRSEN_SHIFT 2 /**< Shift value for DAC_CH1PRSEN */\r
+#define _DAC_CH1CTRL_CH1PRSEN_MASK 0x4UL /**< Bit mask for DAC_CH1PRSEN */\r
+#define DAC_CH1CTRL_CH1PRSEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for DAC_CH1CTRL */\r
+#define _DAC_CH1CTRL_CH1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */\r
+#define _DAC_CH1CTRL_CH1PRSSEL_SHIFT 4 /**< Shift value for DAC_CH1PRSSEL */\r
+#define _DAC_CH1CTRL_CH1PRSSEL_MASK 0x70UL /**< Bit mask for DAC_CH1PRSSEL */\r
+#define DAC_CH1CTRL_CH1PRSSEL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for DAC_CH1CTRL */\r
+#define DAC_CH1CTRL_CH1PRSSEL_PRSCH0 (0x00000000UL << 4) /**< Shifted mode PRSCH0 for DAC_CH1CTRL */\r
+#define DAC_CH1CTRL_CH1PRSSEL_PRSCH1 (0x00000001UL << 4) /**< Shifted mode PRSCH1 for DAC_CH1CTRL */\r
+#define DAC_CH1CTRL_CH1PRSSEL_PRSCH2 (0x00000002UL << 4) /**< Shifted mode PRSCH2 for DAC_CH1CTRL */\r
+#define DAC_CH1CTRL_CH1PRSSEL_PRSCH3 (0x00000003UL << 4) /**< Shifted mode PRSCH3 for DAC_CH1CTRL */\r
+#define DAC_CH1CTRL_CH1PRSSEL_PRSCH4 (0x00000004UL << 4) /**< Shifted mode PRSCH4 for DAC_CH1CTRL */\r
+#define DAC_CH1CTRL_CH1PRSSEL_PRSCH5 (0x00000005UL << 4) /**< Shifted mode PRSCH5 for DAC_CH1CTRL */\r
+#define DAC_CH1CTRL_CH1PRSSEL_PRSCH6 (0x00000006UL << 4) /**< Shifted mode PRSCH6 for DAC_CH1CTRL */\r
+#define DAC_CH1CTRL_CH1PRSSEL_PRSCH7 (0x00000007UL << 4) /**< Shifted mode PRSCH7 for DAC_CH1CTRL */\r
+#define _DAC_CH1CTRL_CH1PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */\r
+#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for DAC_CH1CTRL */\r
+#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for DAC_CH1CTRL */\r
+#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for DAC_CH1CTRL */\r
+#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for DAC_CH1CTRL */\r
+#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for DAC_CH1CTRL */\r
+#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for DAC_CH1CTRL */\r
+#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for DAC_CH1CTRL */\r
+#define _DAC_CH1CTRL_CH1PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for DAC_CH1CTRL */\r
+\r
+/** Bit fields for DAC IEN */\r
+#define _DAC_IEN_RESETVALUE 0x00000000UL /**< Default value for DAC_IEN */\r
+#define _DAC_IEN_MASK 0x00000033UL /**< Mask for DAC_IEN */\r
+#define DAC_IEN_CH0 (1 << 0) /**< Channel 0 Conversion Complete Interrupt Enable */\r
+#define _DAC_IEN_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */\r
+#define _DAC_IEN_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */\r
+#define DAC_IEN_CH0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_IEN */\r
+#define _DAC_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */\r
+#define DAC_IEN_CH1 (1 << 1) /**< Channel 1 Conversion Complete Interrupt Enable */\r
+#define _DAC_IEN_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */\r
+#define _DAC_IEN_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */\r
+#define DAC_IEN_CH1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_IEN */\r
+#define _DAC_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */\r
+#define DAC_IEN_CH0UF (1 << 4) /**< Channel 0 Conversion Data Underflow Interrupt Enable */\r
+#define _DAC_IEN_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */\r
+#define _DAC_IEN_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */\r
+#define DAC_IEN_CH0UF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for DAC_IEN */\r
+#define _DAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */\r
+#define DAC_IEN_CH1UF (1 << 5) /**< Channel 1 Conversion Data Underflow Interrupt Enable */\r
+#define _DAC_IEN_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */\r
+#define _DAC_IEN_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */\r
+#define DAC_IEN_CH1UF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for DAC_IEN */\r
+#define _DAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */\r
+\r
+/** Bit fields for DAC IF */\r
+#define _DAC_IF_RESETVALUE 0x00000000UL /**< Default value for DAC_IF */\r
+#define _DAC_IF_MASK 0x00000033UL /**< Mask for DAC_IF */\r
+#define DAC_IF_CH0 (1 << 0) /**< Channel 0 Conversion Complete Interrupt Flag */\r
+#define _DAC_IF_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */\r
+#define _DAC_IF_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */\r
+#define DAC_IF_CH0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_IF */\r
+#define _DAC_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */\r
+#define DAC_IF_CH1 (1 << 1) /**< Channel 1 Conversion Complete Interrupt Flag */\r
+#define _DAC_IF_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */\r
+#define _DAC_IF_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */\r
+#define DAC_IF_CH1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_IF */\r
+#define _DAC_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */\r
+#define DAC_IF_CH0UF (1 << 4) /**< Channel 0 Data Underflow Interrupt Flag */\r
+#define _DAC_IF_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */\r
+#define _DAC_IF_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */\r
+#define DAC_IF_CH0UF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for DAC_IF */\r
+#define _DAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */\r
+#define DAC_IF_CH1UF (1 << 5) /**< Channel 1 Data Underflow Interrupt Flag */\r
+#define _DAC_IF_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */\r
+#define _DAC_IF_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */\r
+#define DAC_IF_CH1UF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for DAC_IF */\r
+#define _DAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */\r
+\r
+/** Bit fields for DAC IFS */\r
+#define _DAC_IFS_RESETVALUE 0x00000000UL /**< Default value for DAC_IFS */\r
+#define _DAC_IFS_MASK 0x00000033UL /**< Mask for DAC_IFS */\r
+#define DAC_IFS_CH0 (1 << 0) /**< Channel 0 Conversion Complete Interrupt Flag Set */\r
+#define _DAC_IFS_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */\r
+#define _DAC_IFS_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */\r
+#define DAC_IFS_CH0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_IFS */\r
+#define _DAC_IFS_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */\r
+#define DAC_IFS_CH1 (1 << 1) /**< Channel 1 Conversion Complete Interrupt Flag Set */\r
+#define _DAC_IFS_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */\r
+#define _DAC_IFS_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */\r
+#define DAC_IFS_CH1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_IFS */\r
+#define _DAC_IFS_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */\r
+#define DAC_IFS_CH0UF (1 << 4) /**< Channel 0 Data Underflow Interrupt Flag Set */\r
+#define _DAC_IFS_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */\r
+#define _DAC_IFS_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */\r
+#define DAC_IFS_CH0UF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for DAC_IFS */\r
+#define _DAC_IFS_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */\r
+#define DAC_IFS_CH1UF (1 << 5) /**< Channel 1 Data Underflow Interrupt Flag Set */\r
+#define _DAC_IFS_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */\r
+#define _DAC_IFS_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */\r
+#define DAC_IFS_CH1UF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for DAC_IFS */\r
+#define _DAC_IFS_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */\r
+\r
+/** Bit fields for DAC IFC */\r
+#define _DAC_IFC_RESETVALUE 0x00000000UL /**< Default value for DAC_IFC */\r
+#define _DAC_IFC_MASK 0x00000033UL /**< Mask for DAC_IFC */\r
+#define DAC_IFC_CH0 (1 << 0) /**< Channel 0 Conversion Complete Interrupt Flag Clear */\r
+#define _DAC_IFC_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */\r
+#define _DAC_IFC_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */\r
+#define DAC_IFC_CH0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_IFC */\r
+#define _DAC_IFC_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */\r
+#define DAC_IFC_CH1 (1 << 1) /**< Channel 1 Conversion Complete Interrupt Flag Clear */\r
+#define _DAC_IFC_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */\r
+#define _DAC_IFC_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */\r
+#define DAC_IFC_CH1_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for DAC_IFC */\r
+#define _DAC_IFC_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */\r
+#define DAC_IFC_CH0UF (1 << 4) /**< Channel 0 Data Underflow Interrupt Flag Clear */\r
+#define _DAC_IFC_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */\r
+#define _DAC_IFC_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */\r
+#define DAC_IFC_CH0UF_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for DAC_IFC */\r
+#define _DAC_IFC_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */\r
+#define DAC_IFC_CH1UF (1 << 5) /**< Channel 1 Data Underflow Interrupt Flag Clear */\r
+#define _DAC_IFC_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */\r
+#define _DAC_IFC_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */\r
+#define DAC_IFC_CH1UF_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for DAC_IFC */\r
+#define _DAC_IFC_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */\r
+\r
+/** Bit fields for DAC CH0DATA */\r
+#define _DAC_CH0DATA_RESETVALUE 0x00000000UL /**< Default value for DAC_CH0DATA */\r
+#define _DAC_CH0DATA_MASK 0x00000FFFUL /**< Mask for DAC_CH0DATA */\r
+#define _DAC_CH0DATA_CH0DATA_SHIFT 0 /**< Shift value for DAC_CH0DATA */\r
+#define _DAC_CH0DATA_CH0DATA_MASK 0xFFFUL /**< Bit mask for DAC_CH0DATA */\r
+#define DAC_CH0DATA_CH0DATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_CH0DATA */\r
+#define _DAC_CH0DATA_CH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0DATA */\r
+\r
+/** Bit fields for DAC CH1DATA */\r
+#define _DAC_CH1DATA_RESETVALUE 0x00000000UL /**< Default value for DAC_CH1DATA */\r
+#define _DAC_CH1DATA_MASK 0x00000FFFUL /**< Mask for DAC_CH1DATA */\r
+#define _DAC_CH1DATA_CH1DATA_SHIFT 0 /**< Shift value for DAC_CH1DATA */\r
+#define _DAC_CH1DATA_CH1DATA_MASK 0xFFFUL /**< Bit mask for DAC_CH1DATA */\r
+#define DAC_CH1DATA_CH1DATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_CH1DATA */\r
+#define _DAC_CH1DATA_CH1DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1DATA */\r
+\r
+/** Bit fields for DAC COMBDATA */\r
+#define _DAC_COMBDATA_RESETVALUE 0x00000000UL /**< Default value for DAC_COMBDATA */\r
+#define _DAC_COMBDATA_MASK 0x0FFF0FFFUL /**< Mask for DAC_COMBDATA */\r
+#define _DAC_COMBDATA_CH0CDATA_SHIFT 0 /**< Shift value for DAC_CH0CDATA */\r
+#define _DAC_COMBDATA_CH0CDATA_MASK 0xFFFUL /**< Bit mask for DAC_CH0CDATA */\r
+#define DAC_COMBDATA_CH0CDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_COMBDATA */\r
+#define _DAC_COMBDATA_CH0CDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_COMBDATA */\r
+#define _DAC_COMBDATA_CH1CDATA_SHIFT 16 /**< Shift value for DAC_CH1CDATA */\r
+#define _DAC_COMBDATA_CH1CDATA_MASK 0xFFF0000UL /**< Bit mask for DAC_CH1CDATA */\r
+#define DAC_COMBDATA_CH1CDATA_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for DAC_COMBDATA */\r
+#define _DAC_COMBDATA_CH1CDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_COMBDATA */\r
+\r
+/** Bit fields for DAC CAL */\r
+#define _DAC_CAL_RESETVALUE 0x00400000UL /**< Default value for DAC_CAL */\r
+#define _DAC_CAL_MASK 0x007F7F7FUL /**< Mask for DAC_CAL */\r
+#define _DAC_CAL_CH0OFFSET_SHIFT 0 /**< Shift value for DAC_CH0OFFSET */\r
+#define _DAC_CAL_CH0OFFSET_MASK 0x7FUL /**< Bit mask for DAC_CH0OFFSET */\r
+#define DAC_CAL_CH0OFFSET_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DAC_CAL */\r
+#define _DAC_CAL_CH0OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CAL */\r
+#define _DAC_CAL_CH1OFFSET_SHIFT 8 /**< Shift value for DAC_CH1OFFSET */\r
+#define _DAC_CAL_CH1OFFSET_MASK 0x7F00UL /**< Bit mask for DAC_CH1OFFSET */\r
+#define DAC_CAL_CH1OFFSET_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for DAC_CAL */\r
+#define _DAC_CAL_CH1OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CAL */\r
+#define _DAC_CAL_GAIN_SHIFT 16 /**< Shift value for DAC_GAIN */\r
+#define _DAC_CAL_GAIN_MASK 0x7F0000UL /**< Bit mask for DAC_GAIN */\r
+#define DAC_CAL_GAIN_DEFAULT (0x00000040UL << 16) /**< Shifted mode DEFAULT for DAC_CAL */\r
+#define _DAC_CAL_GAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for DAC_CAL */\r
+\r
+/** Bit fields for DAC BIASPROG */\r
+#define _DAC_BIASPROG_RESETVALUE 0x00000047UL /**< Default value for DAC_BIASPROG */\r
+#define _DAC_BIASPROG_MASK 0x0000004FUL /**< Mask for DAC_BIASPROG */\r
+#define _DAC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for DAC_BIASPROG */\r
+#define _DAC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for DAC_BIASPROG */\r
+#define DAC_BIASPROG_BIASPROG_DEFAULT (0x00000007UL << 0) /**< Shifted mode DEFAULT for DAC_BIASPROG */\r
+#define _DAC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for DAC_BIASPROG */\r
+#define DAC_BIASPROG_HALFBIAS (1 << 6) /**< Half Bias Current */\r
+#define _DAC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for DAC_HALFBIAS */\r
+#define _DAC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for DAC_HALFBIAS */\r
+#define DAC_BIASPROG_HALFBIAS_DEFAULT (0x00000001UL << 6) /**< Shifted mode DEFAULT for DAC_BIASPROG */\r
+#define _DAC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_BIASPROG */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_ACMP\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for ACMP CTRL */\r
+#define _ACMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for ACMP_CTRL */\r
+#define _ACMP_CTRL_MASK 0xCF03077FUL /**< Mask for ACMP_CTRL */\r
+#define ACMP_CTRL_EN (1 << 0) /**< Analog Comparator Enable */\r
+#define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */\r
+#define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */\r
+#define ACMP_CTRL_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_MUXEN (1 << 1) /**< Input Mux Enable */\r
+#define _ACMP_CTRL_MUXEN_SHIFT 1 /**< Shift value for ACMP_MUXEN */\r
+#define _ACMP_CTRL_MUXEN_MASK 0x2UL /**< Bit mask for ACMP_MUXEN */\r
+#define ACMP_CTRL_MUXEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_MUXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_INACTVAL (1 << 2) /**< Inactive Value */\r
+#define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */\r
+#define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */\r
+#define ACMP_CTRL_INACTVAL_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_INACTVAL_LOW (0x00000000UL << 2) /**< Shifted mode LOW for ACMP_CTRL */\r
+#define ACMP_CTRL_INACTVAL_HIGH (0x00000001UL << 2) /**< Shifted mode HIGH for ACMP_CTRL */\r
+#define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */\r
+#define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */\r
+#define ACMP_CTRL_GPIOINV (1 << 3) /**< Comparator GPIO Output Invert */\r
+#define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */\r
+#define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */\r
+#define ACMP_CTRL_GPIOINV_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_GPIOINV_NOTINV (0x00000000UL << 3) /**< Shifted mode NOTINV for ACMP_CTRL */\r
+#define ACMP_CTRL_GPIOINV_INV (0x00000001UL << 3) /**< Shifted mode INV for ACMP_CTRL */\r
+#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */\r
+#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */\r
+#define _ACMP_CTRL_HYSTSEL_SHIFT 4 /**< Shift value for ACMP_HYSTSEL */\r
+#define _ACMP_CTRL_HYSTSEL_MASK 0x70UL /**< Bit mask for ACMP_HYSTSEL */\r
+#define ACMP_CTRL_HYSTSEL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_HYSTSEL_HYST0 (0x00000000UL << 4) /**< Shifted mode HYST0 for ACMP_CTRL */\r
+#define ACMP_CTRL_HYSTSEL_HYST1 (0x00000001UL << 4) /**< Shifted mode HYST1 for ACMP_CTRL */\r
+#define ACMP_CTRL_HYSTSEL_HYST2 (0x00000002UL << 4) /**< Shifted mode HYST2 for ACMP_CTRL */\r
+#define ACMP_CTRL_HYSTSEL_HYST3 (0x00000003UL << 4) /**< Shifted mode HYST3 for ACMP_CTRL */\r
+#define ACMP_CTRL_HYSTSEL_HYST4 (0x00000004UL << 4) /**< Shifted mode HYST4 for ACMP_CTRL */\r
+#define ACMP_CTRL_HYSTSEL_HYST5 (0x00000005UL << 4) /**< Shifted mode HYST5 for ACMP_CTRL */\r
+#define ACMP_CTRL_HYSTSEL_HYST6 (0x00000006UL << 4) /**< Shifted mode HYST6 for ACMP_CTRL */\r
+#define ACMP_CTRL_HYSTSEL_HYST7 (0x00000007UL << 4) /**< Shifted mode HYST7 for ACMP_CTRL */\r
+#define _ACMP_CTRL_HYSTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_HYSTSEL_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_CTRL */\r
+#define _ACMP_CTRL_HYSTSEL_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_CTRL */\r
+#define _ACMP_CTRL_HYSTSEL_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_CTRL */\r
+#define _ACMP_CTRL_HYSTSEL_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_CTRL */\r
+#define _ACMP_CTRL_HYSTSEL_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_CTRL */\r
+#define _ACMP_CTRL_HYSTSEL_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_CTRL */\r
+#define _ACMP_CTRL_HYSTSEL_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_CTRL */\r
+#define _ACMP_CTRL_HYSTSEL_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_CTRL */\r
+#define _ACMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for ACMP_WARMTIME */\r
+#define _ACMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for ACMP_WARMTIME */\r
+#define ACMP_CTRL_WARMTIME_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_WARMTIME_4CYCLES (0x00000000UL << 8) /**< Shifted mode 4CYCLES for ACMP_CTRL */\r
+#define ACMP_CTRL_WARMTIME_8CYCLES (0x00000001UL << 8) /**< Shifted mode 8CYCLES for ACMP_CTRL */\r
+#define ACMP_CTRL_WARMTIME_16CYCLES (0x00000002UL << 8) /**< Shifted mode 16CYCLES for ACMP_CTRL */\r
+#define ACMP_CTRL_WARMTIME_32CYCLES (0x00000003UL << 8) /**< Shifted mode 32CYCLES for ACMP_CTRL */\r
+#define ACMP_CTRL_WARMTIME_64CYCLES (0x00000004UL << 8) /**< Shifted mode 64CYCLES for ACMP_CTRL */\r
+#define ACMP_CTRL_WARMTIME_128CYCLES (0x00000005UL << 8) /**< Shifted mode 128CYCLES for ACMP_CTRL */\r
+#define ACMP_CTRL_WARMTIME_256CYCLES (0x00000006UL << 8) /**< Shifted mode 256CYCLES for ACMP_CTRL */\r
+#define ACMP_CTRL_WARMTIME_512CYCLES (0x00000007UL << 8) /**< Shifted mode 512CYCLES for ACMP_CTRL */\r
+#define _ACMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for ACMP_CTRL */\r
+#define _ACMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for ACMP_CTRL */\r
+#define _ACMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for ACMP_CTRL */\r
+#define _ACMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for ACMP_CTRL */\r
+#define _ACMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for ACMP_CTRL */\r
+#define _ACMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for ACMP_CTRL */\r
+#define _ACMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for ACMP_CTRL */\r
+#define _ACMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for ACMP_CTRL */\r
+#define ACMP_CTRL_IRISE (1 << 16) /**< Rising Edge Interrupt Sense */\r
+#define _ACMP_CTRL_IRISE_SHIFT 16 /**< Shift value for ACMP_IRISE */\r
+#define _ACMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for ACMP_IRISE */\r
+#define ACMP_CTRL_IRISE_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_IRISE_DISABLED (0x00000000UL << 16) /**< Shifted mode DISABLED for ACMP_CTRL */\r
+#define ACMP_CTRL_IRISE_ENABLED (0x00000001UL << 16) /**< Shifted mode ENABLED for ACMP_CTRL */\r
+#define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */\r
+#define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */\r
+#define ACMP_CTRL_IFALL (1 << 17) /**< Falling Edge Interrupt Sense */\r
+#define _ACMP_CTRL_IFALL_SHIFT 17 /**< Shift value for ACMP_IFALL */\r
+#define _ACMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for ACMP_IFALL */\r
+#define ACMP_CTRL_IFALL_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_IFALL_DISABLED (0x00000000UL << 17) /**< Shifted mode DISABLED for ACMP_CTRL */\r
+#define ACMP_CTRL_IFALL_ENABLED (0x00000001UL << 17) /**< Shifted mode ENABLED for ACMP_CTRL */\r
+#define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */\r
+#define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */\r
+#define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */\r
+#define _ACMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for ACMP_BIASPROG */\r
+#define ACMP_CTRL_BIASPROG_DEFAULT (0x00000007UL << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_HALFBIAS (1 << 30) /**< Half Bias Current */\r
+#define _ACMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for ACMP_HALFBIAS */\r
+#define _ACMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for ACMP_HALFBIAS */\r
+#define ACMP_CTRL_HALFBIAS_DEFAULT (0x00000001UL << 30) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_CTRL */\r
+#define ACMP_CTRL_FULLBIAS (1 << 31) /**< Full Bias Current */\r
+#define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */\r
+#define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */\r
+#define ACMP_CTRL_FULLBIAS_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */\r
+#define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */\r
+\r
+/** Bit fields for ACMP INPUTSEL */\r
+#define _ACMP_INPUTSEL_RESETVALUE 0x00010080UL /**< Default value for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_MASK 0x31013FF7UL /**< Mask for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_MASK 0x7UL /**< Bit mask for ACMP_POSSEL */\r
+#define ACMP_INPUTSEL_POSSEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_POSPIN0 (0x00000000UL << 0) /**< Shifted mode POSPIN0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_POSPIN1 (0x00000001UL << 0) /**< Shifted mode POSPIN1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_POSPIN2 (0x00000002UL << 0) /**< Shifted mode POSPIN2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_POSPIN3 (0x00000003UL << 0) /**< Shifted mode POSPIN3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_POSPIN4 (0x00000004UL << 0) /**< Shifted mode POSPIN4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_POSPIN5 (0x00000005UL << 0) /**< Shifted mode POSPIN5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_POSPIN6 (0x00000006UL << 0) /**< Shifted mode POSPIN6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_POSSEL_POSPIN7 (0x00000007UL << 0) /**< Shifted mode POSPIN7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_POSPIN0 0x00000000UL /**< Mode POSPIN0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_POSPIN1 0x00000001UL /**< Mode POSPIN1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_POSPIN2 0x00000002UL /**< Mode POSPIN2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_POSPIN3 0x00000003UL /**< Mode POSPIN3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_POSPIN4 0x00000004UL /**< Mode POSPIN4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_POSPIN5 0x00000005UL /**< Mode POSPIN5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_POSPIN6 0x00000006UL /**< Mode POSPIN6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_POSSEL_POSPIN7 0x00000007UL /**< Mode POSPIN7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_SHIFT 4 /**< Shift value for ACMP_NEGSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_MASK 0xF0UL /**< Bit mask for ACMP_NEGSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_NEGPIN0 (0x00000000UL << 4) /**< Shifted mode NEGPIN0 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_NEGPIN1 (0x00000001UL << 4) /**< Shifted mode NEGPIN1 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_NEGPIN2 (0x00000002UL << 4) /**< Shifted mode NEGPIN2 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_NEGPIN3 (0x00000003UL << 4) /**< Shifted mode NEGPIN3 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_NEGPIN4 (0x00000004UL << 4) /**< Shifted mode NEGPIN4 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_NEGPIN5 (0x00000005UL << 4) /**< Shifted mode NEGPIN5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_NEGPIN6 (0x00000006UL << 4) /**< Shifted mode NEGPIN6 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_NEGPIN7 (0x00000007UL << 4) /**< Shifted mode NEGPIN7 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_DEFAULT (0x00000008UL << 4) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_NEG1V25 (0x00000008UL << 4) /**< Shifted mode NEG1V25 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_NEG2V5 (0x00000009UL << 4) /**< Shifted mode NEG2V5 for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_NEGVDD (0x0000000AUL << 4) /**< Shifted mode NEGVDD for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_NEGSEL_CAPSENSE (0x0000000BUL << 4) /**< Shifted mode CAPSENSE for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_NEGPIN0 0x00000000UL /**< Mode NEGPIN0 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_NEGPIN1 0x00000001UL /**< Mode NEGPIN1 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_NEGPIN2 0x00000002UL /**< Mode NEGPIN2 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_NEGPIN3 0x00000003UL /**< Mode NEGPIN3 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_NEGPIN4 0x00000004UL /**< Mode NEGPIN4 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_NEGPIN5 0x00000005UL /**< Mode NEGPIN5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_NEGPIN6 0x00000006UL /**< Mode NEGPIN6 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_NEGPIN7 0x00000007UL /**< Mode NEGPIN7 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000008UL /**< Mode DEFAULT for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_NEG1V25 0x00000008UL /**< Mode NEG1V25 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_NEG2V5 0x00000009UL /**< Mode NEG2V5 for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_NEGVDD 0x0000000AUL /**< Mode NEGVDD for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_NEGSEL_CAPSENSE 0x0000000BUL /**< Mode CAPSENSE for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VDDLEVEL_SHIFT 8 /**< Shift value for ACMP_VDDLEVEL */\r
+#define _ACMP_INPUTSEL_VDDLEVEL_MASK 0x3F00UL /**< Bit mask for ACMP_VDDLEVEL */\r
+#define ACMP_INPUTSEL_VDDLEVEL_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_VDDLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_LPREF (1 << 16) /**< Low Power Reference Mode */\r
+#define _ACMP_INPUTSEL_LPREF_SHIFT 16 /**< Shift value for ACMP_LPREF */\r
+#define _ACMP_INPUTSEL_LPREF_MASK 0x10000UL /**< Bit mask for ACMP_LPREF */\r
+#define ACMP_INPUTSEL_LPREF_DEFAULT (0x00000001UL << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_LPREF_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESEN (1 << 24) /**< Capacitive Sense Mode Internal Resistor Enable */\r
+#define _ACMP_INPUTSEL_CSRESEN_SHIFT 24 /**< Shift value for ACMP_CSRESEN */\r
+#define _ACMP_INPUTSEL_CSRESEN_MASK 0x1000000UL /**< Bit mask for ACMP_CSRESEN */\r
+#define ACMP_INPUTSEL_CSRESEN_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_MASK 0x30000000UL /**< Bit mask for ACMP_CSRESSEL */\r
+#define ACMP_INPUTSEL_CSRESSEL_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESSEL_30KOHM (0x00000000UL << 28) /**< Shifted mode 30KOHM for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESSEL_60KOHM (0x00000001UL << 28) /**< Shifted mode 60KOHM for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESSEL_90KOHM (0x00000002UL << 28) /**< Shifted mode 90KOHM for ACMP_INPUTSEL */\r
+#define ACMP_INPUTSEL_CSRESSEL_120KOHM (0x00000003UL << 28) /**< Shifted mode 120KOHM for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_30KOHM 0x00000000UL /**< Mode 30KOHM for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_60KOHM 0x00000001UL /**< Mode 60KOHM for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_90KOHM 0x00000002UL /**< Mode 90KOHM for ACMP_INPUTSEL */\r
+#define _ACMP_INPUTSEL_CSRESSEL_120KOHM 0x00000003UL /**< Mode 120KOHM for ACMP_INPUTSEL */\r
+\r
+/** Bit fields for ACMP STATUS */\r
+#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */\r
+#define _ACMP_STATUS_MASK 0x00000003UL /**< Mask for ACMP_STATUS */\r
+#define ACMP_STATUS_ACMPACT (1 << 0) /**< Analog Comparator Active */\r
+#define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */\r
+#define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */\r
+#define ACMP_STATUS_ACMPACT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */\r
+#define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */\r
+#define ACMP_STATUS_ACMPOUT (1 << 1) /**< Analog Comparator Output */\r
+#define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */\r
+#define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */\r
+#define ACMP_STATUS_ACMPOUT_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */\r
+#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */\r
+\r
+/** Bit fields for ACMP IEN */\r
+#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */\r
+#define _ACMP_IEN_MASK 0x00000003UL /**< Mask for ACMP_IEN */\r
+#define ACMP_IEN_EDGE (1 << 0) /**< Edge Trigger Interrupt Enable */\r
+#define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */\r
+#define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */\r
+#define ACMP_IEN_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_IEN */\r
+#define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */\r
+#define ACMP_IEN_WARMUP (1 << 1) /**< Warm-up Interrupt Enable */\r
+#define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */\r
+#define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */\r
+#define ACMP_IEN_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ACMP_IEN */\r
+#define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */\r
+\r
+/** Bit fields for ACMP IF */\r
+#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */\r
+#define _ACMP_IF_MASK 0x00000003UL /**< Mask for ACMP_IF */\r
+#define ACMP_IF_EDGE (1 << 0) /**< Edge Triggered Interrupt Flag */\r
+#define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */\r
+#define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */\r
+#define ACMP_IF_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_IF */\r
+#define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */\r
+#define ACMP_IF_WARMUP (1 << 1) /**< Warm-up Interrupt Flag */\r
+#define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */\r
+#define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */\r
+#define ACMP_IF_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ACMP_IF */\r
+#define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */\r
+\r
+/** Bit fields for ACMP IFS */\r
+#define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */\r
+#define _ACMP_IFS_MASK 0x00000003UL /**< Mask for ACMP_IFS */\r
+#define ACMP_IFS_EDGE (1 << 0) /**< Edge Triggered Interrupt Flag Set */\r
+#define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */\r
+#define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */\r
+#define ACMP_IFS_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_IFS */\r
+#define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */\r
+#define ACMP_IFS_WARMUP (1 << 1) /**< Warm-up Interrupt Flag Set */\r
+#define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */\r
+#define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */\r
+#define ACMP_IFS_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ACMP_IFS */\r
+#define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */\r
+\r
+/** Bit fields for ACMP IFC */\r
+#define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */\r
+#define _ACMP_IFC_MASK 0x00000003UL /**< Mask for ACMP_IFC */\r
+#define ACMP_IFC_EDGE (1 << 0) /**< Edge Triggered Interrupt Flag Clear */\r
+#define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */\r
+#define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */\r
+#define ACMP_IFC_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_IFC */\r
+#define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */\r
+#define ACMP_IFC_WARMUP (1 << 1) /**< Warm-up Interrupt Flag Clear */\r
+#define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */\r
+#define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */\r
+#define ACMP_IFC_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for ACMP_IFC */\r
+#define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */\r
+\r
+/** Bit fields for ACMP ROUTE */\r
+#define _ACMP_ROUTE_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTE */\r
+#define _ACMP_ROUTE_MASK 0x00000301UL /**< Mask for ACMP_ROUTE */\r
+#define ACMP_ROUTE_ACMPPEN (1 << 0) /**< ACMP Output Pin Enable */\r
+#define _ACMP_ROUTE_ACMPPEN_SHIFT 0 /**< Shift value for ACMP_ACMPPEN */\r
+#define _ACMP_ROUTE_ACMPPEN_MASK 0x1UL /**< Bit mask for ACMP_ACMPPEN */\r
+#define ACMP_ROUTE_ACMPPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for ACMP_ROUTE */\r
+#define _ACMP_ROUTE_ACMPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTE */\r
+#define _ACMP_ROUTE_LOCATION_SHIFT 8 /**< Shift value for ACMP_LOCATION */\r
+#define _ACMP_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for ACMP_LOCATION */\r
+#define ACMP_ROUTE_LOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for ACMP_ROUTE */\r
+#define ACMP_ROUTE_LOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for ACMP_ROUTE */\r
+#define ACMP_ROUTE_LOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for ACMP_ROUTE */\r
+#define ACMP_ROUTE_LOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for ACMP_ROUTE */\r
+#define ACMP_ROUTE_LOCATION_LOC3 (0x00000003UL << 8) /**< Shifted mode LOC3 for ACMP_ROUTE */\r
+#define _ACMP_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTE */\r
+#define _ACMP_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTE */\r
+#define _ACMP_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTE */\r
+#define _ACMP_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTE */\r
+#define _ACMP_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for ACMP_ROUTE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_MSC\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for MSC CTRL */\r
+#define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */\r
+#define _MSC_CTRL_MASK 0x00000001UL /**< Mask for MSC_CTRL */\r
+#define MSC_CTRL_BUSFAULT (1 << 0) /**< Bus Fault Response Enable */\r
+#define _MSC_CTRL_BUSFAULT_SHIFT 0 /**< Shift value for MSC_BUSFAULT */\r
+#define _MSC_CTRL_BUSFAULT_MASK 0x1UL /**< Bit mask for MSC_BUSFAULT */\r
+#define MSC_CTRL_BUSFAULT_GENERATE (0x00000000UL << 0) /**< Shifted mode GENERATE for MSC_CTRL */\r
+#define MSC_CTRL_BUSFAULT_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for MSC_CTRL */\r
+#define MSC_CTRL_BUSFAULT_IGNORE (0x00000001UL << 0) /**< Shifted mode IGNORE for MSC_CTRL */\r
+#define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL /**< Mode GENERATE for MSC_CTRL */\r
+#define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */\r
+#define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL /**< Mode IGNORE for MSC_CTRL */\r
+\r
+/** Bit fields for MSC READCTRL */\r
+#define _MSC_READCTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_READCTRL */\r
+#define _MSC_READCTRL_MASK 0x00000007UL /**< Mask for MSC_READCTRL */\r
+#define _MSC_READCTRL_MODE_SHIFT 0 /**< Shift value for MSC_MODE */\r
+#define _MSC_READCTRL_MODE_MASK 0x7UL /**< Bit mask for MSC_MODE */\r
+#define MSC_READCTRL_MODE_WS0 (0x00000000UL << 0) /**< Shifted mode WS0 for MSC_READCTRL */\r
+#define MSC_READCTRL_MODE_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for MSC_READCTRL */\r
+#define MSC_READCTRL_MODE_WS1 (0x00000001UL << 0) /**< Shifted mode WS1 for MSC_READCTRL */\r
+#define MSC_READCTRL_MODE_WS0SCBTP (0x00000002UL << 0) /**< Shifted mode WS0SCBTP for MSC_READCTRL */\r
+#define MSC_READCTRL_MODE_WS1SCBTP (0x00000003UL << 0) /**< Shifted mode WS1SCBTP for MSC_READCTRL */\r
+#define MSC_READCTRL_MODE_RESERVED0 (0x00000004UL << 0) /**< Shifted mode RESERVED0 for MSC_READCTRL */\r
+#define MSC_READCTRL_MODE_RESERVED1 (0x00000005UL << 0) /**< Shifted mode RESERVED1 for MSC_READCTRL */\r
+#define MSC_READCTRL_MODE_RESERVED2 (0x00000006UL << 0) /**< Shifted mode RESERVED2 for MSC_READCTRL */\r
+#define MSC_READCTRL_MODE_RESERVED3 (0x00000007UL << 0) /**< Shifted mode RESERVED3 for MSC_READCTRL */\r
+#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */\r
+#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */\r
+#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */\r
+#define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL /**< Mode WS0SCBTP for MSC_READCTRL */\r
+#define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL /**< Mode WS1SCBTP for MSC_READCTRL */\r
+#define _MSC_READCTRL_MODE_RESERVED0 0x00000004UL /**< Mode RESERVED0 for MSC_READCTRL */\r
+#define _MSC_READCTRL_MODE_RESERVED1 0x00000005UL /**< Mode RESERVED1 for MSC_READCTRL */\r
+#define _MSC_READCTRL_MODE_RESERVED2 0x00000006UL /**< Mode RESERVED2 for MSC_READCTRL */\r
+#define _MSC_READCTRL_MODE_RESERVED3 0x00000007UL /**< Mode RESERVED3 for MSC_READCTRL */\r
+\r
+/** Bit fields for MSC WRITECTRL */\r
+#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */\r
+#define _MSC_WRITECTRL_MASK 0x00000003UL /**< Mask for MSC_WRITECTRL */\r
+#define MSC_WRITECTRL_WREN (1 << 0) /**< Enable Write/Erase Controller */\r
+#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */\r
+#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */\r
+#define MSC_WRITECTRL_WREN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */\r
+#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */\r
+#define MSC_WRITECTRL_IRQERASEABORT (1 << 1) /**< Abort Page Erase on Interrupt */\r
+#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */\r
+#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */\r
+#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */\r
+#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */\r
+\r
+/** Bit fields for MSC WRITECMD */\r
+#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */\r
+#define _MSC_WRITECMD_MASK 0x0000001FUL /**< Mask for MSC_WRITECMD */\r
+#define MSC_WRITECMD_LADDRIM (1 << 0) /**< Load MSC_ADDRB into ADDR */\r
+#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */\r
+#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */\r
+#define MSC_WRITECMD_LADDRIM_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */\r
+#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_ERASEPAGE (1 << 1) /**< Erase Page */\r
+#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */\r
+#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */\r
+#define MSC_WRITECMD_ERASEPAGE_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */\r
+#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_WRITEEND (1 << 2) /**< End Write Mode */\r
+#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */\r
+#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */\r
+#define MSC_WRITECMD_WRITEEND_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */\r
+#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_WRITEONCE (1 << 3) /**< Word Write-Once Trigger */\r
+#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */\r
+#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */\r
+#define MSC_WRITECMD_WRITEONCE_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */\r
+#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */\r
+#define MSC_WRITECMD_WRITETRIG (1 << 4) /**< Word Write Sequence Trigger */\r
+#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */\r
+#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */\r
+#define MSC_WRITECMD_WRITETRIG_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */\r
+#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */\r
+\r
+/** Bit fields for MSC ADDRB */\r
+#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */\r
+#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */\r
+#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */\r
+#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */\r
+#define MSC_ADDRB_ADDRB_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */\r
+#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */\r
+\r
+/** Bit fields for MSC WDATA */\r
+#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */\r
+#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */\r
+#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */\r
+#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */\r
+#define MSC_WDATA_WDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_WDATA */\r
+#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */\r
+\r
+/** Bit fields for MSC STATUS */\r
+#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */\r
+#define _MSC_STATUS_MASK 0x0000003FUL /**< Mask for MSC_STATUS */\r
+#define MSC_STATUS_BUSY (1 << 0) /**< Erase/Write Busy */\r
+#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */\r
+#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */\r
+#define MSC_STATUS_BUSY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_STATUS */\r
+#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_LOCKED (1 << 1) /**< Access Locked */\r
+#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */\r
+#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */\r
+#define MSC_STATUS_LOCKED_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for MSC_STATUS */\r
+#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_INVADDR (1 << 2) /**< Invalid Write Address or Erase Page */\r
+#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */\r
+#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */\r
+#define MSC_STATUS_INVADDR_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for MSC_STATUS */\r
+#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_WDATAREADY (1 << 3) /**< WDATA Write Ready */\r
+#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */\r
+#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */\r
+#define MSC_STATUS_WDATAREADY_DEFAULT (0x00000001UL << 3) /**< Shifted mode DEFAULT for MSC_STATUS */\r
+#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_WORDTIMEOUT (1 << 4) /**< Flash Write Word Timeout */\r
+#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */\r
+#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */\r
+#define MSC_STATUS_WORDTIMEOUT_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for MSC_STATUS */\r
+#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */\r
+#define MSC_STATUS_ERASEABORTED (1 << 5) /**< The Current Flash Erase Operation Aborted */\r
+#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */\r
+#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */\r
+#define MSC_STATUS_ERASEABORTED_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for MSC_STATUS */\r
+#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */\r
+\r
+/** Bit fields for MSC IF */\r
+#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */\r
+#define _MSC_IF_MASK 0x00000003UL /**< Mask for MSC_IF */\r
+#define MSC_IF_ERASE (1 << 0) /**< Erase Done Interrupt Read Flag */\r
+#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */\r
+#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */\r
+#define MSC_IF_ERASE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_IF */\r
+#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */\r
+#define MSC_IF_WRITE (1 << 1) /**< Write Done Interrupt Read Flag */\r
+#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */\r
+#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */\r
+#define MSC_IF_WRITE_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for MSC_IF */\r
+#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */\r
+\r
+/** Bit fields for MSC IFS */\r
+#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */\r
+#define _MSC_IFS_MASK 0x00000003UL /**< Mask for MSC_IFS */\r
+#define MSC_IFS_ERASE (1 << 0) /**< Erase Done Interrupt Set */\r
+#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */\r
+#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */\r
+#define MSC_IFS_ERASE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_IFS */\r
+#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */\r
+#define MSC_IFS_WRITE (1 << 1) /**< Write Done Interrupt Set */\r
+#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */\r
+#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */\r
+#define MSC_IFS_WRITE_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for MSC_IFS */\r
+#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */\r
+\r
+/** Bit fields for MSC IFC */\r
+#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */\r
+#define _MSC_IFC_MASK 0x00000003UL /**< Mask for MSC_IFC */\r
+#define MSC_IFC_ERASE (1 << 0) /**< Erase Done Interrupt Clear */\r
+#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */\r
+#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */\r
+#define MSC_IFC_ERASE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_IFC */\r
+#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */\r
+#define MSC_IFC_WRITE (1 << 1) /**< Write Done Interrupt Clear */\r
+#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */\r
+#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */\r
+#define MSC_IFC_WRITE_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for MSC_IFC */\r
+#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */\r
+\r
+/** Bit fields for MSC IEN */\r
+#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */\r
+#define _MSC_IEN_MASK 0x00000003UL /**< Mask for MSC_IEN */\r
+#define MSC_IEN_ERASE (1 << 0) /**< Erase Done Interrupt Enable */\r
+#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */\r
+#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */\r
+#define MSC_IEN_ERASE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_IEN */\r
+#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */\r
+#define MSC_IEN_WRITE (1 << 1) /**< Write Done Interrupt Enable */\r
+#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */\r
+#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */\r
+#define MSC_IEN_WRITE_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for MSC_IEN */\r
+#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */\r
+\r
+/** Bit fields for MSC LOCK */\r
+#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */\r
+#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */\r
+#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */\r
+#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */\r
+#define MSC_LOCK_LOCKKEY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for MSC_LOCK */\r
+#define MSC_LOCK_LOCKKEY_LOCK (0x00000000UL << 0) /**< Shifted mode LOCK for MSC_LOCK */\r
+#define MSC_LOCK_LOCKKEY_UNLOCKED (0x00000000UL << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */\r
+#define MSC_LOCK_LOCKKEY_LOCKED (0x00000001UL << 0) /**< Shifted mode LOCKED for MSC_LOCK */\r
+#define MSC_LOCK_LOCKKEY_UNLOCK (0x00001B71UL << 0) /**< Shifted mode UNLOCK for MSC_LOCK */\r
+#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */\r
+#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */\r
+#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */\r
+#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */\r
+#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_EMU\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for EMU CTRL */\r
+#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */\r
+#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */\r
+#define EMU_CTRL_EMVREG (1 << 0) /**< Energy Mode Voltage Regulator Control */\r
+#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */\r
+#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */\r
+#define EMU_CTRL_EMVREG_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EMU_CTRL */\r
+#define EMU_CTRL_EMVREG_OFF (0x00000000UL << 0) /**< Shifted mode OFF for EMU_CTRL */\r
+#define EMU_CTRL_EMVREG_ON (0x00000001UL << 0) /**< Shifted mode ON for EMU_CTRL */\r
+#define _EMU_CTRL_EMVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */\r
+#define _EMU_CTRL_EMVREG_OFF 0x00000000UL /**< Mode OFF for EMU_CTRL */\r
+#define _EMU_CTRL_EMVREG_ON 0x00000001UL /**< Mode ON for EMU_CTRL */\r
+#define EMU_CTRL_EM2BLOCK (1 << 1) /**< Energy Mode 2 Block */\r
+#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */\r
+#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */\r
+#define EMU_CTRL_EM2BLOCK_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for EMU_CTRL */\r
+#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */\r
+#define _EMU_CTRL_EM4CTRL_SHIFT 2 /**< Shift value for EMU_EM4CTRL */\r
+#define _EMU_CTRL_EM4CTRL_MASK 0xCUL /**< Bit mask for EMU_EM4CTRL */\r
+#define EMU_CTRL_EM4CTRL_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for EMU_CTRL */\r
+#define _EMU_CTRL_EM4CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */\r
+\r
+/** Bit fields for EMU MEMCTRL */\r
+#define _EMU_MEMCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_MEMCTRL */\r
+#define _EMU_MEMCTRL_MASK 0x00000007UL /**< Mask for EMU_MEMCTRL */\r
+#define _EMU_MEMCTRL_POWERDOWN_SHIFT 0 /**< Shift value for EMU_POWERDOWN */\r
+#define _EMU_MEMCTRL_POWERDOWN_MASK 0x7UL /**< Bit mask for EMU_POWERDOWN */\r
+#define EMU_MEMCTRL_POWERDOWN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EMU_MEMCTRL */\r
+#define EMU_MEMCTRL_POWERDOWN_BLK3 (0x00000004UL << 0) /**< Shifted mode BLK3 for EMU_MEMCTRL */\r
+#define EMU_MEMCTRL_POWERDOWN_BLK23 (0x00000006UL << 0) /**< Shifted mode BLK23 for EMU_MEMCTRL */\r
+#define EMU_MEMCTRL_POWERDOWN_BLK123 (0x00000007UL << 0) /**< Shifted mode BLK123 for EMU_MEMCTRL */\r
+#define _EMU_MEMCTRL_POWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_MEMCTRL */\r
+#define _EMU_MEMCTRL_POWERDOWN_BLK3 0x00000004UL /**< Mode BLK3 for EMU_MEMCTRL */\r
+#define _EMU_MEMCTRL_POWERDOWN_BLK23 0x00000006UL /**< Mode BLK23 for EMU_MEMCTRL */\r
+#define _EMU_MEMCTRL_POWERDOWN_BLK123 0x00000007UL /**< Mode BLK123 for EMU_MEMCTRL */\r
+\r
+/** Bit fields for EMU LOCK */\r
+#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */\r
+#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */\r
+#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */\r
+#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */\r
+#define EMU_LOCK_LOCKKEY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EMU_LOCK */\r
+#define EMU_LOCK_LOCKKEY_LOCK (0x00000000UL << 0) /**< Shifted mode LOCK for EMU_LOCK */\r
+#define EMU_LOCK_LOCKKEY_UNLOCKED (0x00000000UL << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */\r
+#define EMU_LOCK_LOCKKEY_LOCKED (0x00000001UL << 0) /**< Shifted mode LOCKED for EMU_LOCK */\r
+#define EMU_LOCK_LOCKKEY_UNLOCK (0x0000ADE8UL << 0) /**< Shifted mode UNLOCK for EMU_LOCK */\r
+#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */\r
+#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */\r
+#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */\r
+#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */\r
+#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */\r
+\r
+/** Bit fields for EMU ATESTCTRL */\r
+#define _EMU_ATESTCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_ATESTCTRL */\r
+#define _EMU_ATESTCTRL_MASK 0x07FFFF0FUL /**< Mask for EMU_ATESTCTRL */\r
+#define _EMU_ATESTCTRL_ATESTSEL_SHIFT 0 /**< Shift value for EMU_ATESTSEL */\r
+#define _EMU_ATESTCTRL_ATESTSEL_MASK 0xFUL /**< Bit mask for EMU_ATESTSEL */\r
+#define EMU_ATESTCTRL_ATESTSEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EMU_ATESTCTRL */\r
+#define _EMU_ATESTCTRL_ATESTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_ATESTCTRL */\r
+#define _EMU_ATESTCTRL_ATESTBUS_SHIFT 8 /**< Shift value for EMU_ATESTBUS */\r
+#define _EMU_ATESTCTRL_ATESTBUS_MASK 0xFFFF00UL /**< Bit mask for EMU_ATESTBUS */\r
+#define EMU_ATESTCTRL_ATESTBUS_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for EMU_ATESTCTRL */\r
+#define _EMU_ATESTCTRL_ATESTBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_ATESTCTRL */\r
+#define EMU_ATESTCTRL_DACATESTINEN (1 << 24) /**< DAC Test Input Enable */\r
+#define _EMU_ATESTCTRL_DACATESTINEN_SHIFT 24 /**< Shift value for EMU_DACATESTINEN */\r
+#define _EMU_ATESTCTRL_DACATESTINEN_MASK 0x1000000UL /**< Bit mask for EMU_DACATESTINEN */\r
+#define EMU_ATESTCTRL_DACATESTINEN_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for EMU_ATESTCTRL */\r
+#define _EMU_ATESTCTRL_DACATESTINEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_ATESTCTRL */\r
+#define EMU_ATESTCTRL_DAC_ATESTOUTEN (1 << 25) /**< DAC Test Output Enable */\r
+#define _EMU_ATESTCTRL_DAC_ATESTOUTEN_SHIFT 25 /**< Shift value for EMU_DAC_ATESTOUTEN */\r
+#define _EMU_ATESTCTRL_DAC_ATESTOUTEN_MASK 0x2000000UL /**< Bit mask for EMU_DAC_ATESTOUTEN */\r
+#define EMU_ATESTCTRL_DAC_ATESTOUTEN_DEFAULT (0x00000000UL << 25) /**< Shifted mode DEFAULT for EMU_ATESTCTRL */\r
+#define _EMU_ATESTCTRL_DAC_ATESTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_ATESTCTRL */\r
+#define EMU_ATESTCTRL_ANATESTINEN (1 << 26) /**< Analog Test Input Enable */\r
+#define _EMU_ATESTCTRL_ANATESTINEN_SHIFT 26 /**< Shift value for EMU_ANATESTINEN */\r
+#define _EMU_ATESTCTRL_ANATESTINEN_MASK 0x4000000UL /**< Bit mask for EMU_ANATESTINEN */\r
+#define EMU_ATESTCTRL_ANATESTINEN_DEFAULT (0x00000000UL << 26) /**< Shifted mode DEFAULT for EMU_ATESTCTRL */\r
+#define _EMU_ATESTCTRL_ANATESTINEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_ATESTCTRL */\r
+\r
+/** Bit fields for EMU AUXCTRL */\r
+#define _EMU_AUXCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_AUXCTRL */\r
+#define _EMU_AUXCTRL_MASK 0x000000FFUL /**< Mask for EMU_AUXCTRL */\r
+#define _EMU_AUXCTRL_AUX_SHIFT 0 /**< Shift value for EMU_AUX */\r
+#define _EMU_AUXCTRL_AUX_MASK 0xFFUL /**< Bit mask for EMU_AUX */\r
+#define EMU_AUXCTRL_AUX_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EMU_AUXCTRL */\r
+#define EMU_AUXCTRL_AUX_HRCCLR (0x00000001UL << 0) /**< Shifted mode HRCCLR for EMU_AUXCTRL */\r
+#define _EMU_AUXCTRL_AUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_AUXCTRL */\r
+#define _EMU_AUXCTRL_AUX_HRCCLR 0x00000001UL /**< Mode HRCCLR for EMU_AUXCTRL */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_RMU\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for RMU CTRL */\r
+#define _RMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for RMU_CTRL */\r
+#define _RMU_CTRL_MASK 0x00000001UL /**< Mask for RMU_CTRL */\r
+#define RMU_CTRL_LOCKUPRDIS (1 << 0) /**< Lockup Reset Disable */\r
+#define _RMU_CTRL_LOCKUPRDIS_SHIFT 0 /**< Shift value for RMU_LOCKUPRDIS */\r
+#define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL /**< Bit mask for RMU_LOCKUPRDIS */\r
+#define RMU_CTRL_LOCKUPRDIS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RMU_CTRL */\r
+#define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */\r
+\r
+/** Bit fields for RMU RSTCAUSE */\r
+#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */\r
+#define _RMU_RSTCAUSE_MASK 0x0000007FUL /**< Mask for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_PORST (1 << 0) /**< Power On Reset */\r
+#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */\r
+#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */\r
+#define RMU_RSTCAUSE_PORST_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_BODUNREGRST (1 << 1) /**< Brown Out Detector Unregulated Domain Reset */\r
+#define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1 /**< Shift value for RMU_BODUNREGRST */\r
+#define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL /**< Bit mask for RMU_BODUNREGRST */\r
+#define RMU_RSTCAUSE_BODUNREGRST_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+#define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_BODREGRST (1 << 2) /**< Brown Out Detector Regulated Domain Reset */\r
+#define _RMU_RSTCAUSE_BODREGRST_SHIFT 2 /**< Shift value for RMU_BODREGRST */\r
+#define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL /**< Bit mask for RMU_BODREGRST */\r
+#define RMU_RSTCAUSE_BODREGRST_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+#define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_EXTRST (1 << 3) /**< External Pin Reset */\r
+#define _RMU_RSTCAUSE_EXTRST_SHIFT 3 /**< Shift value for RMU_EXTRST */\r
+#define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL /**< Bit mask for RMU_EXTRST */\r
+#define RMU_RSTCAUSE_EXTRST_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_WDOGRST (1 << 4) /**< Watchdog Reset */\r
+#define _RMU_RSTCAUSE_WDOGRST_SHIFT 4 /**< Shift value for RMU_WDOGRST */\r
+#define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL /**< Bit mask for RMU_WDOGRST */\r
+#define RMU_RSTCAUSE_WDOGRST_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_LOCKUPRST (1 << 5) /**< LOCKUP Reset */\r
+#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5 /**< Shift value for RMU_LOCKUPRST */\r
+#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL /**< Bit mask for RMU_LOCKUPRST */\r
+#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+#define RMU_RSTCAUSE_SYSREQRST (1 << 6) /**< System Request Reset */\r
+#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6 /**< Shift value for RMU_SYSREQRST */\r
+#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL /**< Bit mask for RMU_SYSREQRST */\r
+#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */\r
+#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */\r
+\r
+/** Bit fields for RMU CMD */\r
+#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */\r
+#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */\r
+#define RMU_CMD_RCCLR (1 << 0) /**< Reset Cause Clear */\r
+#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */\r
+#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */\r
+#define RMU_CMD_RCCLR_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RMU_CMD */\r
+#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_CMU\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for CMU CTRL */\r
+#define _CMU_CTRL_RESETVALUE 0x000C262CUL /**< Default value for CMU_CTRL */\r
+#define _CMU_CTRL_MASK 0x00FE3EEFUL /**< Mask for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
+#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
+#define CMU_CTRL_HFXOMODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
+#define CMU_CTRL_HFXOMODE_XTAL (0x00000000UL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
+#define CMU_CTRL_HFXOMODE_BUFEXTCLK (0x00000001UL << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
+#define CMU_CTRL_HFXOMODE_DIGEXTCLK (0x00000002UL << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
+#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
+#define CMU_CTRL_HFXOBOOST_50PCENT (0x00000000UL << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
+#define CMU_CTRL_HFXOBOOST_70PCENT (0x00000001UL << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
+#define CMU_CTRL_HFXOBOOST_80PCENT (0x00000002UL << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
+#define CMU_CTRL_HFXOBOOST_DEFAULT (0x00000003UL << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
+#define CMU_CTRL_HFXOBOOST_100PCENT (0x00000003UL << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
+#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
+#define CMU_CTRL_HFXOBUFCUR_80PCENT (0x00000000UL << 5) /**< Shifted mode 80PCENT for CMU_CTRL */\r
+#define CMU_CTRL_HFXOBUFCUR_DEFAULT (0x00000001UL << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
+#define CMU_CTRL_HFXOBUFCUR_100PCENT (0x00000001UL << 5) /**< Shifted mode 100PCENT for CMU_CTRL */\r
+#define CMU_CTRL_HFXOBUFCUR_120PCENT (0x00000002UL << 5) /**< Shifted mode 120PCENT for CMU_CTRL */\r
+#define CMU_CTRL_HFXOBUFCUR_150PCENT (0x00000003UL << 5) /**< Shifted mode 150PCENT for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOBUFCUR_80PCENT 0x00000000UL /**< Mode 80PCENT for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOBUFCUR_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOBUFCUR_120PCENT 0x00000002UL /**< Mode 120PCENT for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOBUFCUR_150PCENT 0x00000003UL /**< Mode 150PCENT for CMU_CTRL */\r
+#define CMU_CTRL_HFXOGLITCHDETEN (1 << 7) /**< HFXO Glitch Detector Enable */\r
+#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
+#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
+#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
+#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
+#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (0x00000000UL << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
+#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (0x00000001UL << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
+#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (0x00000002UL << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
+#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (0x00000003UL << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
+#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (0x00000003UL << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
+#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
+#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
+#define CMU_CTRL_LFXOMODE_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
+#define CMU_CTRL_LFXOMODE_XTAL (0x00000000UL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
+#define CMU_CTRL_LFXOMODE_BUFEXTCLK (0x00000001UL << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
+#define CMU_CTRL_LFXOMODE_DIGEXTCLK (0x00000002UL << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
+#define CMU_CTRL_LFXOBOOST (1 << 13) /**< LFXO Start-up Boost Current */\r
+#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
+#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
+#define CMU_CTRL_LFXOBOOST_70PCENT (0x00000000UL << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
+#define CMU_CTRL_LFXOBOOST_DEFAULT (0x00000001UL << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
+#define CMU_CTRL_LFXOBOOST_100PCENT (0x00000001UL << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
+#define CMU_CTRL_LFXOBUFCUR (1 << 17) /**< LFXO Boost Buffer Current */\r
+#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
+#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
+#define CMU_CTRL_LFXOBUFCUR_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
+#define CMU_CTRL_LFXOBUFCUR_100PCENT (0x00000000UL << 17) /**< Shifted mode 100PCENT for CMU_CTRL */\r
+#define CMU_CTRL_LFXOBUFCUR_150PCENT (0x00000001UL << 17) /**< Shifted mode 150PCENT for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOBUFCUR_100PCENT 0x00000000UL /**< Mode 100PCENT for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOBUFCUR_150PCENT 0x00000001UL /**< Mode 150PCENT for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
+#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
+#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (0x00000000UL << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
+#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (0x00000001UL << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
+#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (0x00000002UL << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
+#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (0x00000003UL << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
+#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (0x00000003UL << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
+#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
+#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
+#define CMU_CTRL_CLKOUTSEL0_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_HFRCO (0x00000000UL << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_HFXO (0x00000001UL << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (0x00000002UL << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (0x00000003UL << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (0x00000004UL << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (0x00000005UL << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL0_ULFRCO (0x00000006UL << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1 (1 << 23) /**< Clock Output Select 1 */\r
+#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
+#define _CMU_CTRL_CLKOUTSEL1_MASK 0x800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
+#define CMU_CTRL_CLKOUTSEL1_DEFAULT (0x00000000UL << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_LFRCO (0x00000000UL << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
+#define CMU_CTRL_CLKOUTSEL1_LFXO (0x00000001UL << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
+#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
+\r
+/** Bit fields for CMU HFCORECLKDIV */\r
+#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
+#define _CMU_HFCORECLKDIV_MASK 0x0000000FUL /**< Mask for CMU_HFCORECLKDIV */\r
+#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
+#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (0x00000000UL << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (0x00000001UL << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (0x00000002UL << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (0x00000003UL << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (0x00000004UL << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (0x00000005UL << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (0x00000006UL << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (0x00000007UL << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (0x00000008UL << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
+#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (0x00000009UL << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
+#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
+#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
+#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
+#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
+#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
+#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
+#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
+#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
+#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
+#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
+#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
+\r
+/** Bit fields for CMU HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (0x00000000UL << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (0x00000001UL << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (0x00000002UL << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (0x00000003UL << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (0x00000004UL << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (0x00000005UL << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (0x00000006UL << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (0x00000007UL << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (0x00000008UL << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
+#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (0x00000009UL << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
+#define CMU_HFPERCLKDIV_HFPERCLKEN (1 << 8) /**< HFPERCLK Enable */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
+#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (0x00000001UL << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
+#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
+\r
+/** Bit fields for CMU HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
+#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
+#define CMU_HFRCOCTRL_TUNING_DEFAULT (0x00000080UL << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
+#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
+#define CMU_HFRCOCTRL_BAND_1MHZ (0x00000000UL << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_BAND_7MHZ (0x00000001UL << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_BAND_11MHZ (0x00000002UL << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_BAND_DEFAULT (0x00000003UL << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_BAND_14MHZ (0x00000003UL << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_BAND_21MHZ (0x00000004UL << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
+#define CMU_HFRCOCTRL_BAND_28MHZ (0x00000005UL << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
+#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
+#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
+#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
+\r
+/** Bit fields for CMU LFRCOCTRL */\r
+#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
+#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
+#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
+#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
+#define CMU_LFRCOCTRL_TUNING_DEFAULT (0x00000040UL << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
+#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
+\r
+/** Bit fields for CMU AUXHFRCOCTRL */\r
+#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
+#define _CMU_AUXHFRCOCTRL_MASK 0x000000FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
+#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
+#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
+#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (0x00000080UL << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
+\r
+/** Bit fields for CMU CALCTRL */\r
+#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_MASK 0x00000007UL /**< Mask for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_REFSEL_SHIFT 0 /**< Shift value for CMU_REFSEL */\r
+#define _CMU_CALCTRL_REFSEL_MASK 0x7UL /**< Bit mask for CMU_REFSEL */\r
+#define CMU_CALCTRL_REFSEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
+#define CMU_CALCTRL_REFSEL_HFXO (0x00000000UL << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
+#define CMU_CALCTRL_REFSEL_LFXO (0x00000001UL << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
+#define CMU_CALCTRL_REFSEL_HFRCO (0x00000002UL << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
+#define CMU_CALCTRL_REFSEL_LFRCO (0x00000003UL << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
+#define CMU_CALCTRL_REFSEL_AUXHFRCO (0x00000004UL << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_REFSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_REFSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
+#define _CMU_CALCTRL_REFSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
+\r
+/** Bit fields for CMU CALCNT */\r
+#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
+#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
+#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
+#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
+#define CMU_CALCNT_CALCNT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
+#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
+\r
+/** Bit fields for CMU OSCENCMD */\r
+#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
+#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_HFRCOEN (1 << 0) /**< HFRCO Enable */\r
+#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
+#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
+#define CMU_OSCENCMD_HFRCOEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_HFRCODIS (1 << 1) /**< HFRCO Disable */\r
+#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
+#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
+#define CMU_OSCENCMD_HFRCODIS_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_HFXOEN (1 << 2) /**< HFXO Enable */\r
+#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
+#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
+#define CMU_OSCENCMD_HFXOEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_HFXODIS (1 << 3) /**< HFXO Disable */\r
+#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
+#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
+#define CMU_OSCENCMD_HFXODIS_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_AUXHFRCOEN (1 << 4) /**< AUXHFRCO Enable */\r
+#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
+#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
+#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_AUXHFRCODIS (1 << 5) /**< AUXHFRCO Disable */\r
+#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
+#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
+#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_LFRCOEN (1 << 6) /**< LFRCO Enable */\r
+#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
+#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
+#define CMU_OSCENCMD_LFRCOEN_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_LFRCODIS (1 << 7) /**< LFRCO Disable */\r
+#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
+#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
+#define CMU_OSCENCMD_LFRCODIS_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_LFXOEN (1 << 8) /**< LFXO Enable */\r
+#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
+#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
+#define CMU_OSCENCMD_LFXOEN_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+#define CMU_OSCENCMD_LFXODIS (1 << 9) /**< LFXO Disable */\r
+#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
+#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
+#define CMU_OSCENCMD_LFXODIS_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
+#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
+\r
+/** Bit fields for CMU CMD */\r
+#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
+#define _CMU_CMD_MASK 0x0000000FUL /**< Mask for CMU_CMD */\r
+#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
+#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
+#define CMU_CMD_HFCLKSEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
+#define CMU_CMD_HFCLKSEL_HFRCO (0x00000001UL << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
+#define CMU_CMD_HFCLKSEL_HFXO (0x00000002UL << 0) /**< Shifted mode HFXO for CMU_CMD */\r
+#define CMU_CMD_HFCLKSEL_LFRCO (0x00000003UL << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
+#define CMU_CMD_HFCLKSEL_LFXO (0x00000004UL << 0) /**< Shifted mode LFXO for CMU_CMD */\r
+#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
+#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
+#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
+#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
+#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
+#define CMU_CMD_CALSTART (1 << 3) /**< Calibration Start */\r
+#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
+#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
+#define CMU_CMD_CALSTART_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
+#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
+\r
+/** Bit fields for CMU LFCLKSEL */\r
+#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
+#define _CMU_LFCLKSEL_MASK 0x0000000FUL /**< Mask for CMU_LFCLKSEL */\r
+#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
+#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
+#define CMU_LFCLKSEL_LFA_DISABLED (0x00000000UL << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
+#define CMU_LFCLKSEL_LFA_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
+#define CMU_LFCLKSEL_LFA_LFRCO (0x00000001UL << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
+#define CMU_LFCLKSEL_LFA_LFXO (0x00000002UL << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
+#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (0x00000003UL << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
+#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
+#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
+#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
+#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
+#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
+#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
+#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
+#define CMU_LFCLKSEL_LFB_DISABLED (0x00000000UL << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
+#define CMU_LFCLKSEL_LFB_DEFAULT (0x00000001UL << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
+#define CMU_LFCLKSEL_LFB_LFRCO (0x00000001UL << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
+#define CMU_LFCLKSEL_LFB_LFXO (0x00000002UL << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
+#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (0x00000003UL << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
+#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
+#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
+#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
+#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
+#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
+\r
+/** Bit fields for CMU STATUS */\r
+#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
+#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
+#define CMU_STATUS_HFRCOENS (1 << 0) /**< HFRCO Enable Status */\r
+#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
+#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
+#define CMU_STATUS_HFRCOENS_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFRCORDY (1 << 1) /**< HFRCO Ready */\r
+#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
+#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
+#define CMU_STATUS_HFRCORDY_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOENS (1 << 2) /**< HFXO Enable Status */\r
+#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
+#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
+#define CMU_STATUS_HFXOENS_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXORDY (1 << 3) /**< HFXO Ready */\r
+#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
+#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
+#define CMU_STATUS_HFXORDY_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_AUXHFRCOENS (1 << 4) /**< AUXHFRCO Enable Status */\r
+#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
+#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
+#define CMU_STATUS_AUXHFRCOENS_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_AUXHFRCORDY (1 << 5) /**< AUXHFRCO Ready */\r
+#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
+#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
+#define CMU_STATUS_AUXHFRCORDY_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_LFRCOENS (1 << 6) /**< LFRCO Enable Status */\r
+#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
+#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
+#define CMU_STATUS_LFRCOENS_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_LFRCORDY (1 << 7) /**< LFRCO Ready */\r
+#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
+#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
+#define CMU_STATUS_LFRCORDY_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_LFXOENS (1 << 8) /**< LFXO Enable Status */\r
+#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
+#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
+#define CMU_STATUS_LFXOENS_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_LFXORDY (1 << 9) /**< LFXO Ready */\r
+#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
+#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
+#define CMU_STATUS_LFXORDY_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFRCOSEL (1 << 10) /**< HFRCO Selected */\r
+#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
+#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
+#define CMU_STATUS_HFRCOSEL_DEFAULT (0x00000001UL << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_HFXOSEL (1 << 11) /**< HFXO Selected */\r
+#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
+#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
+#define CMU_STATUS_HFXOSEL_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_LFRCOSEL (1 << 12) /**< HFRCO Selected */\r
+#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
+#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
+#define CMU_STATUS_LFRCOSEL_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_LFXOSEL (1 << 13) /**< HFXO Selected */\r
+#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
+#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
+#define CMU_STATUS_LFXOSEL_DEFAULT (0x00000000UL << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+#define CMU_STATUS_CALBSY (1 << 14) /**< Calibration Busy */\r
+#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
+#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
+#define CMU_STATUS_CALBSY_DEFAULT (0x00000000UL << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
+#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
+\r
+/** Bit fields for CMU IF */\r
+#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
+#define _CMU_IF_MASK 0x0000003FUL /**< Mask for CMU_IF */\r
+#define CMU_IF_HFRCORDY (1 << 0) /**< HFRCO Ready Interrupt Flag */\r
+#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
+#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
+#define CMU_IF_HFRCORDY_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_HFXORDY (1 << 1) /**< HFXO Ready Interrupt Flag */\r
+#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
+#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
+#define CMU_IF_HFXORDY_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_LFRCORDY (1 << 2) /**< LFRCO Ready Interrupt Flag */\r
+#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
+#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
+#define CMU_IF_LFRCORDY_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_LFXORDY (1 << 3) /**< LFXO Ready Interrupt Flag */\r
+#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
+#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
+#define CMU_IF_LFXORDY_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_AUXHFRCORDY (1 << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
+#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
+#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
+#define CMU_IF_AUXHFRCORDY_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+#define CMU_IF_CALRDY (1 << 5) /**< Calibration Ready Interrupt Flag */\r
+#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
+#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
+#define CMU_IF_CALRDY_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
+#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
+\r
+/** Bit fields for CMU IFS */\r
+#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
+#define _CMU_IFS_MASK 0x0000003FUL /**< Mask for CMU_IFS */\r
+#define CMU_IFS_HFRCORDY (1 << 0) /**< HFRCO Ready Interrupt Flag Set */\r
+#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
+#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
+#define CMU_IFS_HFRCORDY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_HFXORDY (1 << 1) /**< HFXO Ready Interrupt Flag Set */\r
+#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
+#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
+#define CMU_IFS_HFXORDY_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_LFRCORDY (1 << 2) /**< LFRCO Ready Interrupt Flag Set */\r
+#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
+#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
+#define CMU_IFS_LFRCORDY_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_LFXORDY (1 << 3) /**< LFXO Ready Interrupt Flag Set */\r
+#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
+#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
+#define CMU_IFS_LFXORDY_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_AUXHFRCORDY (1 << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
+#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
+#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
+#define CMU_IFS_AUXHFRCORDY_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+#define CMU_IFS_CALRDY (1 << 5) /**< Calibration Ready Interrupt Flag Set */\r
+#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
+#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
+#define CMU_IFS_CALRDY_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
+#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
+\r
+/** Bit fields for CMU IFC */\r
+#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
+#define _CMU_IFC_MASK 0x0000003FUL /**< Mask for CMU_IFC */\r
+#define CMU_IFC_HFRCORDY (1 << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
+#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
+#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
+#define CMU_IFC_HFRCORDY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_HFXORDY (1 << 1) /**< HFXO Ready Interrupt Flag Clear */\r
+#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
+#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
+#define CMU_IFC_HFXORDY_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_LFRCORDY (1 << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
+#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
+#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
+#define CMU_IFC_LFRCORDY_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_LFXORDY (1 << 3) /**< LFXO Ready Interrupt Flag Clear */\r
+#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
+#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
+#define CMU_IFC_LFXORDY_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_AUXHFRCORDY (1 << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
+#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
+#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
+#define CMU_IFC_AUXHFRCORDY_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+#define CMU_IFC_CALRDY (1 << 5) /**< Calibration Ready Interrupt Flag Clear */\r
+#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
+#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
+#define CMU_IFC_CALRDY_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
+#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
+\r
+/** Bit fields for CMU IEN */\r
+#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
+#define _CMU_IEN_MASK 0x0000003FUL /**< Mask for CMU_IEN */\r
+#define CMU_IEN_HFRCORDY (1 << 0) /**< HFRCO Ready Interrupt Enable */\r
+#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
+#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
+#define CMU_IEN_HFRCORDY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_HFXORDY (1 << 1) /**< HFXO Ready Interrupt Enable */\r
+#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
+#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
+#define CMU_IEN_HFXORDY_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_LFRCORDY (1 << 2) /**< LFRCO Ready Interrupt Enable */\r
+#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
+#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
+#define CMU_IEN_LFRCORDY_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_LFXORDY (1 << 3) /**< LFXO Ready Interrupt Enable */\r
+#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
+#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
+#define CMU_IEN_LFXORDY_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_AUXHFRCORDY (1 << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
+#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
+#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
+#define CMU_IEN_AUXHFRCORDY_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+#define CMU_IEN_CALRDY (1 << 5) /**< Calibration Ready Interrupt Enable */\r
+#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
+#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
+#define CMU_IEN_CALRDY_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
+#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
+\r
+/** Bit fields for CMU HFCORECLKEN0 */\r
+#define _CMU_HFCORECLKEN0_RESETVALUE 0x0000000FUL /**< Default value for CMU_HFCORECLKEN0 */\r
+#define _CMU_HFCORECLKEN0_MASK 0x0000000FUL /**< Mask for CMU_HFCORECLKEN0 */\r
+#define CMU_HFCORECLKEN0_AES (1 << 0) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
+#define _CMU_HFCORECLKEN0_AES_SHIFT 0 /**< Shift value for CMU_AES */\r
+#define _CMU_HFCORECLKEN0_AES_MASK 0x1UL /**< Bit mask for CMU_AES */\r
+#define CMU_HFCORECLKEN0_AES_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
+#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
+#define CMU_HFCORECLKEN0_DMA (1 << 1) /**< Direct Memory Access Controller Clock Enable */\r
+#define _CMU_HFCORECLKEN0_DMA_SHIFT 1 /**< Shift value for CMU_DMA */\r
+#define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL /**< Bit mask for CMU_DMA */\r
+#define CMU_HFCORECLKEN0_DMA_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
+#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
+#define CMU_HFCORECLKEN0_LE (1 << 2) /**< Low Energy Peripheral Interface Clock Enable */\r
+#define _CMU_HFCORECLKEN0_LE_SHIFT 2 /**< Shift value for CMU_LE */\r
+#define _CMU_HFCORECLKEN0_LE_MASK 0x4UL /**< Bit mask for CMU_LE */\r
+#define CMU_HFCORECLKEN0_LE_DEFAULT (0x00000001UL << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
+#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
+#define CMU_HFCORECLKEN0_EBI (1 << 3) /**< External Bus Interface Clock Enable */\r
+#define _CMU_HFCORECLKEN0_EBI_SHIFT 3 /**< Shift value for CMU_EBI */\r
+#define _CMU_HFCORECLKEN0_EBI_MASK 0x8UL /**< Bit mask for CMU_EBI */\r
+#define CMU_HFCORECLKEN0_EBI_DEFAULT (0x00000001UL << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
+#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
+\r
+/** Bit fields for CMU HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_RESETVALUE 0x0000FFFFUL /**< Default value for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_MASK 0x0000FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_USART0 (1 << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
+#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
+#define CMU_HFPERCLKEN0_USART0_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_USART1 (1 << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
+#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
+#define CMU_HFPERCLKEN0_USART1_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_USART2 (1 << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
+#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
+#define CMU_HFPERCLKEN0_USART2_DEFAULT (0x00000001UL << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_UART0 (1 << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
+#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
+#define CMU_HFPERCLKEN0_UART0_DEFAULT (0x00000001UL << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_TIMER0 (1 << 4) /**< Timer 0 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */\r
+#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */\r
+#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (0x00000001UL << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_TIMER1 (1 << 5) /**< Timer 1 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */\r
+#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */\r
+#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (0x00000001UL << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_TIMER2 (1 << 6) /**< Timer 2 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */\r
+#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */\r
+#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (0x00000001UL << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_ACMP0 (1 << 7) /**< Analog Comparator 0 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 7 /**< Shift value for CMU_ACMP0 */\r
+#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x80UL /**< Bit mask for CMU_ACMP0 */\r
+#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (0x00000001UL << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_ACMP1 (1 << 8) /**< Analog Comparator 1 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 8 /**< Shift value for CMU_ACMP1 */\r
+#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x100UL /**< Bit mask for CMU_ACMP1 */\r
+#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (0x00000001UL << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_PRS (1 << 10) /**< Peripheral Reflex System Clock Enable */\r
+#define _CMU_HFPERCLKEN0_PRS_SHIFT 10 /**< Shift value for CMU_PRS */\r
+#define _CMU_HFPERCLKEN0_PRS_MASK 0x400UL /**< Bit mask for CMU_PRS */\r
+#define CMU_HFPERCLKEN0_PRS_DEFAULT (0x00000001UL << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_DAC0 (1 << 11) /**< Digital to Analog Converter 0 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_DAC0_SHIFT 11 /**< Shift value for CMU_DAC0 */\r
+#define _CMU_HFPERCLKEN0_DAC0_MASK 0x800UL /**< Bit mask for CMU_DAC0 */\r
+#define CMU_HFPERCLKEN0_DAC0_DEFAULT (0x00000001UL << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_GPIO (1 << 12) /**< General purpose Input/Output Clock Enable */\r
+#define _CMU_HFPERCLKEN0_GPIO_SHIFT 12 /**< Shift value for CMU_GPIO */\r
+#define _CMU_HFPERCLKEN0_GPIO_MASK 0x1000UL /**< Bit mask for CMU_GPIO */\r
+#define CMU_HFPERCLKEN0_GPIO_DEFAULT (0x00000001UL << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_VCMP (1 << 13) /**< Voltage Comparator Clock Enable */\r
+#define _CMU_HFPERCLKEN0_VCMP_SHIFT 13 /**< Shift value for CMU_VCMP */\r
+#define _CMU_HFPERCLKEN0_VCMP_MASK 0x2000UL /**< Bit mask for CMU_VCMP */\r
+#define CMU_HFPERCLKEN0_VCMP_DEFAULT (0x00000001UL << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_ADC0 (1 << 14) /**< Analog to Digital Converter 0 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_ADC0_SHIFT 14 /**< Shift value for CMU_ADC0 */\r
+#define _CMU_HFPERCLKEN0_ADC0_MASK 0x4000UL /**< Bit mask for CMU_ADC0 */\r
+#define CMU_HFPERCLKEN0_ADC0_DEFAULT (0x00000001UL << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define CMU_HFPERCLKEN0_I2C0 (1 << 15) /**< I2C 0 Clock Enable */\r
+#define _CMU_HFPERCLKEN0_I2C0_SHIFT 15 /**< Shift value for CMU_I2C0 */\r
+#define _CMU_HFPERCLKEN0_I2C0_MASK 0x8000UL /**< Bit mask for CMU_I2C0 */\r
+#define CMU_HFPERCLKEN0_I2C0_DEFAULT (0x00000001UL << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
+#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
+\r
+/** Bit fields for CMU SYNCBUSY */\r
+#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
+#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFACLKEN0 (1 << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
+#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
+#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
+#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFAPRESC0 (1 << 2) /**< Low Frequency A Prescaler 0 Busy */\r
+#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
+#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
+#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFBCLKEN0 (1 << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
+#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
+#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
+#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+#define CMU_SYNCBUSY_LFBPRESC0 (1 << 6) /**< Low Frequency B Prescaler 0 Busy */\r
+#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
+#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
+#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
+#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
+\r
+/** Bit fields for CMU FREEZE */\r
+#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
+#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
+#define CMU_FREEZE_REGFREEZE (1 << 0) /**< Register Update Freeze */\r
+#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
+#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
+#define CMU_FREEZE_REGFREEZE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
+#define CMU_FREEZE_REGFREEZE_UPDATE (0x00000000UL << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
+#define CMU_FREEZE_REGFREEZE_FREEZE (0x00000001UL << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
+#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
+#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
+#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
+\r
+/** Bit fields for CMU LFACLKEN0 */\r
+#define _CMU_LFACLKEN0_RESETVALUE 0x00000007UL /**< Default value for CMU_LFACLKEN0 */\r
+#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
+#define CMU_LFACLKEN0_RTC (1 << 0) /**< Real-Time Counter Clock Enable */\r
+#define _CMU_LFACLKEN0_RTC_SHIFT 0 /**< Shift value for CMU_RTC */\r
+#define _CMU_LFACLKEN0_RTC_MASK 0x1UL /**< Bit mask for CMU_RTC */\r
+#define CMU_LFACLKEN0_RTC_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
+#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
+#define CMU_LFACLKEN0_LETIMER0 (1 << 1) /**< Low Energy Timer 0 Clock Enable */\r
+#define _CMU_LFACLKEN0_LETIMER0_SHIFT 1 /**< Shift value for CMU_LETIMER0 */\r
+#define _CMU_LFACLKEN0_LETIMER0_MASK 0x2UL /**< Bit mask for CMU_LETIMER0 */\r
+#define CMU_LFACLKEN0_LETIMER0_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
+#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
+#define CMU_LFACLKEN0_LCD (1 << 2) /**< Liquid Crystal Display Controller Clock Enable */\r
+#define _CMU_LFACLKEN0_LCD_SHIFT 2 /**< Shift value for CMU_LCD */\r
+#define _CMU_LFACLKEN0_LCD_MASK 0x4UL /**< Bit mask for CMU_LCD */\r
+#define CMU_LFACLKEN0_LCD_DEFAULT (0x00000001UL << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
+#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
+\r
+/** Bit fields for CMU LFBCLKEN0 */\r
+#define _CMU_LFBCLKEN0_RESETVALUE 0x00000003UL /**< Default value for CMU_LFBCLKEN0 */\r
+#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
+#define CMU_LFBCLKEN0_LEUART0 (1 << 0) /**< Low Energy UART 0 Clock Enable */\r
+#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
+#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
+#define CMU_LFBCLKEN0_LEUART0_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
+#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
+#define CMU_LFBCLKEN0_LEUART1 (1 << 1) /**< Low Energy UART 1 Clock Enable */\r
+#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
+#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
+#define CMU_LFBCLKEN0_LEUART1_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
+#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
+\r
+/** Bit fields for CMU LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_MASK 0x000003FFUL /**< Mask for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_SHIFT 0 /**< Shift value for CMU_RTC */\r
+#define _CMU_LFAPRESC0_RTC_MASK 0xFUL /**< Bit mask for CMU_RTC */\r
+#define CMU_LFAPRESC0_RTC_DIV1 (0x00000000UL << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_RTC_DIV2 (0x00000001UL << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_RTC_DIV4 (0x00000002UL << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_RTC_DIV8 (0x00000003UL << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_RTC_DIV16 (0x00000004UL << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_RTC_DIV32 (0x00000005UL << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_RTC_DIV64 (0x00000006UL << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_RTC_DIV128 (0x00000007UL << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_RTC_DIV256 (0x00000008UL << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_RTC_DIV512 (0x00000009UL << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_RTC_DIV1024 (0x0000000AUL << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_RTC_DIV2048 (0x0000000BUL << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_RTC_DIV4096 (0x0000000CUL << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_RTC_DIV8192 (0x0000000DUL << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_RTC_DIV16384 (0x0000000EUL << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_RTC_DIV32768 (0x0000000FUL << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_SHIFT 4 /**< Shift value for CMU_LETIMER0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF0UL /**< Bit mask for CMU_LETIMER0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV1 (0x00000000UL << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV2 (0x00000001UL << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV4 (0x00000002UL << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV8 (0x00000003UL << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV16 (0x00000004UL << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV32 (0x00000005UL << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV64 (0x00000006UL << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV128 (0x00000007UL << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV256 (0x00000008UL << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV512 (0x00000009UL << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV1024 (0x0000000AUL << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV2048 (0x0000000BUL << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV4096 (0x0000000CUL << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV8192 (0x0000000DUL << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV16384 (0x0000000EUL << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LETIMER0_DIV32768 (0x0000000FUL << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LCD_SHIFT 8 /**< Shift value for CMU_LCD */\r
+#define _CMU_LFAPRESC0_LCD_MASK 0x300UL /**< Bit mask for CMU_LCD */\r
+#define CMU_LFAPRESC0_LCD_DIV16 (0x00000000UL << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LCD_DIV32 (0x00000001UL << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LCD_DIV64 (0x00000002UL << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
+#define CMU_LFAPRESC0_LCD_DIV128 (0x00000003UL << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
+#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
+\r
+/** Bit fields for CMU LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
+#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
+#define CMU_LFBPRESC0_LEUART0_DIV1 (0x00000000UL << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
+#define CMU_LFBPRESC0_LEUART0_DIV2 (0x00000001UL << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
+#define CMU_LFBPRESC0_LEUART0_DIV4 (0x00000002UL << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
+#define CMU_LFBPRESC0_LEUART0_DIV8 (0x00000003UL << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
+#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
+#define CMU_LFBPRESC0_LEUART1_DIV1 (0x00000000UL << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
+#define CMU_LFBPRESC0_LEUART1_DIV2 (0x00000001UL << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
+#define CMU_LFBPRESC0_LEUART1_DIV4 (0x00000002UL << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
+#define CMU_LFBPRESC0_LEUART1_DIV8 (0x00000003UL << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
+#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
+\r
+/** Bit fields for CMU PCNTCTRL */\r
+#define _CMU_PCNTCTRL_RESETVALUE 0x00000015UL /**< Default value for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT0CLKEN (1 << 0) /**< PCNT0 Clock Enable */\r
+#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
+#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
+#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT0CLKSEL (1 << 1) /**< PCNT0 Clock Select */\r
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
+#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (0x00000000UL << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (0x00000001UL << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT1CLKEN (1 << 2) /**< PCNT1 Clock Enable */\r
+#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
+#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
+#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (0x00000001UL << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT1CLKSEL (1 << 3) /**< PCNT1 Clock Select */\r
+#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
+#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
+#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (0x00000000UL << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (0x00000001UL << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT2CLKEN (1 << 4) /**< PCNT2 Clock Enable */\r
+#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
+#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
+#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (0x00000001UL << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT2CLKSEL (1 << 5) /**< PCNT2 Clock Select */\r
+#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
+#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
+#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (0x00000000UL << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
+#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (0x00000001UL << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
+#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
+\r
+/** Bit fields for CMU LCDCTRL */\r
+#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */\r
+#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */\r
+#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */\r
+#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */\r
+#define CMU_LCDCTRL_FDIV_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
+#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
+#define CMU_LCDCTRL_VBOOSTEN (1 << 3) /**< Voltage Boost Enable */\r
+#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */\r
+#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */\r
+#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
+#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
+#define _CMU_LCDCTRL_VBFREQ_SHIFT 4 /**< Shift value for CMU_VBFREQ */\r
+#define _CMU_LCDCTRL_VBFREQ_MASK 0x70UL /**< Bit mask for CMU_VBFREQ */\r
+#define CMU_LCDCTRL_VBFREQ_32KHZ (0x00000000UL << 4) /**< Shifted mode 32KHZ for CMU_LCDCTRL */\r
+#define CMU_LCDCTRL_VBFREQ_16KHZ (0x00000001UL << 4) /**< Shifted mode 16KHZ for CMU_LCDCTRL */\r
+#define CMU_LCDCTRL_VBFREQ_DEFAULT (0x00000002UL << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
+#define CMU_LCDCTRL_VBFREQ_8KHZ (0x00000002UL << 4) /**< Shifted mode 8KHZ for CMU_LCDCTRL */\r
+#define CMU_LCDCTRL_VBFREQ_4KHZ (0x00000003UL << 4) /**< Shifted mode 4KHZ for CMU_LCDCTRL */\r
+#define CMU_LCDCTRL_VBFREQ_2KHZ (0x00000004UL << 4) /**< Shifted mode 2KHZ for CMU_LCDCTRL */\r
+#define CMU_LCDCTRL_VBFREQ_1KHZ (0x00000005UL << 4) /**< Shifted mode 1KHZ for CMU_LCDCTRL */\r
+#define CMU_LCDCTRL_VBFREQ_512HZ (0x00000006UL << 4) /**< Shifted mode 512HZ for CMU_LCDCTRL */\r
+#define CMU_LCDCTRL_VBFREQ_256HZ (0x00000007UL << 4) /**< Shifted mode 256HZ for CMU_LCDCTRL */\r
+#define _CMU_LCDCTRL_VBFREQ_32KHZ 0x00000000UL /**< Mode 32KHZ for CMU_LCDCTRL */\r
+#define _CMU_LCDCTRL_VBFREQ_16KHZ 0x00000001UL /**< Mode 16KHZ for CMU_LCDCTRL */\r
+#define _CMU_LCDCTRL_VBFREQ_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
+#define _CMU_LCDCTRL_VBFREQ_8KHZ 0x00000002UL /**< Mode 8KHZ for CMU_LCDCTRL */\r
+#define _CMU_LCDCTRL_VBFREQ_4KHZ 0x00000003UL /**< Mode 4KHZ for CMU_LCDCTRL */\r
+#define _CMU_LCDCTRL_VBFREQ_2KHZ 0x00000004UL /**< Mode 2KHZ for CMU_LCDCTRL */\r
+#define _CMU_LCDCTRL_VBFREQ_1KHZ 0x00000005UL /**< Mode 1KHZ for CMU_LCDCTRL */\r
+#define _CMU_LCDCTRL_VBFREQ_512HZ 0x00000006UL /**< Mode 512HZ for CMU_LCDCTRL */\r
+#define _CMU_LCDCTRL_VBFREQ_256HZ 0x00000007UL /**< Mode 256HZ for CMU_LCDCTRL */\r
+\r
+/** Bit fields for CMU ROUTE */\r
+#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
+#define _CMU_ROUTE_MASK 0x00000007UL /**< Mask for CMU_ROUTE */\r
+#define CMU_ROUTE_CLKOUT0PEN (1 << 0) /**< CLKOUT0 Pin Enable */\r
+#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
+#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
+#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
+#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
+#define CMU_ROUTE_CLKOUT1PEN (1 << 1) /**< CLKOUT1 Pin Enable */\r
+#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
+#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
+#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
+#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
+#define CMU_ROUTE_LOCATION (1 << 2) /**< I/O Location */\r
+#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
+#define _CMU_ROUTE_LOCATION_MASK 0x4UL /**< Bit mask for CMU_LOCATION */\r
+#define CMU_ROUTE_LOCATION_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
+#define CMU_ROUTE_LOCATION_LOC0 (0x00000000UL << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
+#define CMU_ROUTE_LOCATION_LOC1 (0x00000001UL << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
+#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
+#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
+#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
+\r
+/** Bit fields for CMU LOCK */\r
+#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
+#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
+#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
+#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
+#define CMU_LOCK_LOCKKEY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
+#define CMU_LOCK_LOCKKEY_LOCK (0x00000000UL << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
+#define CMU_LOCK_LOCKKEY_UNLOCKED (0x00000000UL << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
+#define CMU_LOCK_LOCKKEY_LOCKED (0x00000001UL << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
+#define CMU_LOCK_LOCKKEY_UNLOCK (0x0000580EUL << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
+#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
+#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
+#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
+#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
+#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_AES\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for AES CTRL */\r
+#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */\r
+#define _AES_CTRL_MASK 0x00000037UL /**< Mask for AES_CTRL */\r
+#define AES_CTRL_DECRYPT (1 << 0) /**< Decryption/Encryption Mode */\r
+#define _AES_CTRL_DECRYPT_SHIFT 0 /**< Shift value for AES_DECRYPT */\r
+#define _AES_CTRL_DECRYPT_MASK 0x1UL /**< Bit mask for AES_DECRYPT */\r
+#define AES_CTRL_DECRYPT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_CTRL */\r
+#define _AES_CTRL_DECRYPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */\r
+#define AES_CTRL_AES256 (1 << 1) /**< AES-256 Mode */\r
+#define _AES_CTRL_AES256_SHIFT 1 /**< Shift value for AES_AES256 */\r
+#define _AES_CTRL_AES256_MASK 0x2UL /**< Bit mask for AES_AES256 */\r
+#define AES_CTRL_AES256_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for AES_CTRL */\r
+#define _AES_CTRL_AES256_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */\r
+#define AES_CTRL_KEYBUFEN (1 << 2) /**< Key Buffer Enable */\r
+#define _AES_CTRL_KEYBUFEN_SHIFT 2 /**< Shift value for AES_KEYBUFEN */\r
+#define _AES_CTRL_KEYBUFEN_MASK 0x4UL /**< Bit mask for AES_KEYBUFEN */\r
+#define AES_CTRL_KEYBUFEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for AES_CTRL */\r
+#define _AES_CTRL_KEYBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */\r
+#define AES_CTRL_DATASTART (1 << 4) /**< AES_DATA Write Start */\r
+#define _AES_CTRL_DATASTART_SHIFT 4 /**< Shift value for AES_DATASTART */\r
+#define _AES_CTRL_DATASTART_MASK 0x10UL /**< Bit mask for AES_DATASTART */\r
+#define AES_CTRL_DATASTART_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for AES_CTRL */\r
+#define _AES_CTRL_DATASTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */\r
+#define AES_CTRL_XORSTART (1 << 5) /**< AES_XORDATA Write Start */\r
+#define _AES_CTRL_XORSTART_SHIFT 5 /**< Shift value for AES_XORSTART */\r
+#define _AES_CTRL_XORSTART_MASK 0x20UL /**< Bit mask for AES_XORSTART */\r
+#define AES_CTRL_XORSTART_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for AES_CTRL */\r
+#define _AES_CTRL_XORSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */\r
+\r
+/** Bit fields for AES CMD */\r
+#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */\r
+#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */\r
+#define AES_CMD_START (1 << 0) /**< Encryption/Decryption Start */\r
+#define _AES_CMD_START_SHIFT 0 /**< Shift value for AES_START */\r
+#define _AES_CMD_START_MASK 0x1UL /**< Bit mask for AES_START */\r
+#define AES_CMD_START_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_CMD */\r
+#define _AES_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */\r
+#define AES_CMD_STOP (1 << 1) /**< Encryption/Decryption Stop */\r
+#define _AES_CMD_STOP_SHIFT 1 /**< Shift value for AES_STOP */\r
+#define _AES_CMD_STOP_MASK 0x2UL /**< Bit mask for AES_STOP */\r
+#define AES_CMD_STOP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for AES_CMD */\r
+#define _AES_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */\r
+\r
+/** Bit fields for AES STATUS */\r
+#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */\r
+#define _AES_STATUS_MASK 0x00000001UL /**< Mask for AES_STATUS */\r
+#define AES_STATUS_RUNNING (1 << 0) /**< AES Running */\r
+#define _AES_STATUS_RUNNING_SHIFT 0 /**< Shift value for AES_RUNNING */\r
+#define _AES_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for AES_RUNNING */\r
+#define AES_STATUS_RUNNING_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_STATUS */\r
+#define _AES_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */\r
+\r
+/** Bit fields for AES IEN */\r
+#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */\r
+#define _AES_IEN_MASK 0x00000001UL /**< Mask for AES_IEN */\r
+#define AES_IEN_DONE (1 << 0) /**< Encryption/Decryption Done Interrupt Enable */\r
+#define _AES_IEN_DONE_SHIFT 0 /**< Shift value for AES_DONE */\r
+#define _AES_IEN_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */\r
+#define AES_IEN_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_IEN */\r
+#define _AES_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */\r
+\r
+/** Bit fields for AES IF */\r
+#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */\r
+#define _AES_IF_MASK 0x00000001UL /**< Mask for AES_IF */\r
+#define AES_IF_DONE (1 << 0) /**< Encryption/Decryption Done Interrupt Flag */\r
+#define _AES_IF_DONE_SHIFT 0 /**< Shift value for AES_DONE */\r
+#define _AES_IF_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */\r
+#define AES_IF_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_IF */\r
+#define _AES_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */\r
+\r
+/** Bit fields for AES IFS */\r
+#define _AES_IFS_RESETVALUE 0x00000000UL /**< Default value for AES_IFS */\r
+#define _AES_IFS_MASK 0x00000001UL /**< Mask for AES_IFS */\r
+#define AES_IFS_DONE (1 << 0) /**< Encryption/Decryption Done Interrupt Flag Set */\r
+#define _AES_IFS_DONE_SHIFT 0 /**< Shift value for AES_DONE */\r
+#define _AES_IFS_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */\r
+#define AES_IFS_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_IFS */\r
+#define _AES_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFS */\r
+\r
+/** Bit fields for AES IFC */\r
+#define _AES_IFC_RESETVALUE 0x00000000UL /**< Default value for AES_IFC */\r
+#define _AES_IFC_MASK 0x00000001UL /**< Mask for AES_IFC */\r
+#define AES_IFC_DONE (1 << 0) /**< Encryption/Decryption Done Interrupt Flag Clear */\r
+#define _AES_IFC_DONE_SHIFT 0 /**< Shift value for AES_DONE */\r
+#define _AES_IFC_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */\r
+#define AES_IFC_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_IFC */\r
+#define _AES_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */\r
+\r
+/** Bit fields for AES DATA */\r
+#define _AES_DATA_RESETVALUE 0x00000000UL /**< Default value for AES_DATA */\r
+#define _AES_DATA_MASK 0xFFFFFFFFUL /**< Mask for AES_DATA */\r
+#define _AES_DATA_DATA_SHIFT 0 /**< Shift value for AES_DATA */\r
+#define _AES_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_DATA */\r
+#define AES_DATA_DATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_DATA */\r
+#define _AES_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_DATA */\r
+\r
+/** Bit fields for AES XORDATA */\r
+#define _AES_XORDATA_RESETVALUE 0x00000000UL /**< Default value for AES_XORDATA */\r
+#define _AES_XORDATA_MASK 0xFFFFFFFFUL /**< Mask for AES_XORDATA */\r
+#define _AES_XORDATA_XORDATA_SHIFT 0 /**< Shift value for AES_XORDATA */\r
+#define _AES_XORDATA_XORDATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_XORDATA */\r
+#define AES_XORDATA_XORDATA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_XORDATA */\r
+#define _AES_XORDATA_XORDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_XORDATA */\r
+\r
+/** Bit fields for AES KEYLA */\r
+#define _AES_KEYLA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLA */\r
+#define _AES_KEYLA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLA */\r
+#define _AES_KEYLA_KEYLA_SHIFT 0 /**< Shift value for AES_KEYLA */\r
+#define _AES_KEYLA_KEYLA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLA */\r
+#define AES_KEYLA_KEYLA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYLA */\r
+#define _AES_KEYLA_KEYLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLA */\r
+\r
+/** Bit fields for AES KEYLB */\r
+#define _AES_KEYLB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLB */\r
+#define _AES_KEYLB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLB */\r
+#define _AES_KEYLB_KEYLB_SHIFT 0 /**< Shift value for AES_KEYLB */\r
+#define _AES_KEYLB_KEYLB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLB */\r
+#define AES_KEYLB_KEYLB_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYLB */\r
+#define _AES_KEYLB_KEYLB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLB */\r
+\r
+/** Bit fields for AES KEYLC */\r
+#define _AES_KEYLC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLC */\r
+#define _AES_KEYLC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLC */\r
+#define _AES_KEYLC_KEYLC_SHIFT 0 /**< Shift value for AES_KEYLC */\r
+#define _AES_KEYLC_KEYLC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLC */\r
+#define AES_KEYLC_KEYLC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYLC */\r
+#define _AES_KEYLC_KEYLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLC */\r
+\r
+/** Bit fields for AES KEYLD */\r
+#define _AES_KEYLD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLD */\r
+#define _AES_KEYLD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLD */\r
+#define _AES_KEYLD_KEYLD_SHIFT 0 /**< Shift value for AES_KEYLD */\r
+#define _AES_KEYLD_KEYLD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLD */\r
+#define AES_KEYLD_KEYLD_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYLD */\r
+#define _AES_KEYLD_KEYLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLD */\r
+\r
+/** Bit fields for AES KEYHA */\r
+#define _AES_KEYHA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHA */\r
+#define _AES_KEYHA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHA */\r
+#define _AES_KEYHA_KEYHA_SHIFT 0 /**< Shift value for AES_KEYHA */\r
+#define _AES_KEYHA_KEYHA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHA */\r
+#define AES_KEYHA_KEYHA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYHA */\r
+#define _AES_KEYHA_KEYHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHA */\r
+\r
+/** Bit fields for AES KEYHB */\r
+#define _AES_KEYHB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHB */\r
+#define _AES_KEYHB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHB */\r
+#define _AES_KEYHB_KEYHB_SHIFT 0 /**< Shift value for AES_KEYHB */\r
+#define _AES_KEYHB_KEYHB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHB */\r
+#define AES_KEYHB_KEYHB_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYHB */\r
+#define _AES_KEYHB_KEYHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHB */\r
+\r
+/** Bit fields for AES KEYHC */\r
+#define _AES_KEYHC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHC */\r
+#define _AES_KEYHC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHC */\r
+#define _AES_KEYHC_KEYHC_SHIFT 0 /**< Shift value for AES_KEYHC */\r
+#define _AES_KEYHC_KEYHC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHC */\r
+#define AES_KEYHC_KEYHC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYHC */\r
+#define _AES_KEYHC_KEYHC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHC */\r
+\r
+/** Bit fields for AES KEYHD */\r
+#define _AES_KEYHD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHD */\r
+#define _AES_KEYHD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHD */\r
+#define _AES_KEYHD_KEYHD_SHIFT 0 /**< Shift value for AES_KEYHD */\r
+#define _AES_KEYHD_KEYHD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHD */\r
+#define AES_KEYHD_KEYHD_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for AES_KEYHD */\r
+#define _AES_KEYHD_KEYHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHD */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_EBI\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for EBI CTRL */\r
+#define _EBI_CTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_CTRL */\r
+#define _EBI_CTRL_MASK 0x00030F07UL /**< Mask for EBI_CTRL */\r
+#define _EBI_CTRL_MODE_SHIFT 0 /**< Shift value for EBI_MODE */\r
+#define _EBI_CTRL_MODE_MASK 0x7UL /**< Bit mask for EBI_MODE */\r
+#define EBI_CTRL_MODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EBI_CTRL */\r
+#define EBI_CTRL_MODE_D8A8 (0x00000000UL << 0) /**< Shifted mode D8A8 for EBI_CTRL */\r
+#define EBI_CTRL_MODE_D16A16ALE (0x00000001UL << 0) /**< Shifted mode D16A16ALE for EBI_CTRL */\r
+#define EBI_CTRL_MODE_D8A24ALE (0x00000002UL << 0) /**< Shifted mode D8A24ALE for EBI_CTRL */\r
+#define _EBI_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */\r
+#define _EBI_CTRL_MODE_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */\r
+#define _EBI_CTRL_MODE_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */\r
+#define _EBI_CTRL_MODE_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */\r
+#define EBI_CTRL_BANK0EN (1 << 8) /**< Bank 0 Enable */\r
+#define _EBI_CTRL_BANK0EN_SHIFT 8 /**< Shift value for EBI_BANK0EN */\r
+#define _EBI_CTRL_BANK0EN_MASK 0x100UL /**< Bit mask for EBI_BANK0EN */\r
+#define EBI_CTRL_BANK0EN_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for EBI_CTRL */\r
+#define _EBI_CTRL_BANK0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */\r
+#define EBI_CTRL_BANK1EN (1 << 9) /**< Bank 1 Enable */\r
+#define _EBI_CTRL_BANK1EN_SHIFT 9 /**< Shift value for EBI_BANK1EN */\r
+#define _EBI_CTRL_BANK1EN_MASK 0x200UL /**< Bit mask for EBI_BANK1EN */\r
+#define EBI_CTRL_BANK1EN_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for EBI_CTRL */\r
+#define _EBI_CTRL_BANK1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */\r
+#define EBI_CTRL_BANK2EN (1 << 10) /**< Bank 2 Enable */\r
+#define _EBI_CTRL_BANK2EN_SHIFT 10 /**< Shift value for EBI_BANK2EN */\r
+#define _EBI_CTRL_BANK2EN_MASK 0x400UL /**< Bit mask for EBI_BANK2EN */\r
+#define EBI_CTRL_BANK2EN_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for EBI_CTRL */\r
+#define _EBI_CTRL_BANK2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */\r
+#define EBI_CTRL_BANK3EN (1 << 11) /**< Bank 3 Enable */\r
+#define _EBI_CTRL_BANK3EN_SHIFT 11 /**< Shift value for EBI_BANK3EN */\r
+#define _EBI_CTRL_BANK3EN_MASK 0x800UL /**< Bit mask for EBI_BANK3EN */\r
+#define EBI_CTRL_BANK3EN_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for EBI_CTRL */\r
+#define _EBI_CTRL_BANK3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */\r
+#define EBI_CTRL_ARDYEN (1 << 16) /**< ARDY Enable */\r
+#define _EBI_CTRL_ARDYEN_SHIFT 16 /**< Shift value for EBI_ARDYEN */\r
+#define _EBI_CTRL_ARDYEN_MASK 0x10000UL /**< Bit mask for EBI_ARDYEN */\r
+#define EBI_CTRL_ARDYEN_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for EBI_CTRL */\r
+#define _EBI_CTRL_ARDYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */\r
+#define EBI_CTRL_ARDYTODIS (1 << 17) /**< ARDY Timeout Disable */\r
+#define _EBI_CTRL_ARDYTODIS_SHIFT 17 /**< Shift value for EBI_ARDYTODIS */\r
+#define _EBI_CTRL_ARDYTODIS_MASK 0x20000UL /**< Bit mask for EBI_ARDYTODIS */\r
+#define EBI_CTRL_ARDYTODIS_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for EBI_CTRL */\r
+#define _EBI_CTRL_ARDYTODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */\r
+\r
+/** Bit fields for EBI ADDRTIMING */\r
+#define _EBI_ADDRTIMING_RESETVALUE 0x00000100UL /**< Default value for EBI_ADDRTIMING */\r
+#define _EBI_ADDRTIMING_MASK 0x00000303UL /**< Mask for EBI_ADDRTIMING */\r
+#define _EBI_ADDRTIMING_ADDRSET_SHIFT 0 /**< Shift value for EBI_ADDRSET */\r
+#define _EBI_ADDRTIMING_ADDRSET_MASK 0x3UL /**< Bit mask for EBI_ADDRSET */\r
+#define EBI_ADDRTIMING_ADDRSET_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */\r
+#define _EBI_ADDRTIMING_ADDRSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING */\r
+#define _EBI_ADDRTIMING_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */\r
+#define _EBI_ADDRTIMING_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */\r
+#define EBI_ADDRTIMING_ADDRHOLD_DEFAULT (0x00000001UL << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */\r
+#define _EBI_ADDRTIMING_ADDRHOLD_DEFAULT 0x00000001UL /**< Mode DEFAULT for EBI_ADDRTIMING */\r
+\r
+/** Bit fields for EBI RDTIMING */\r
+#define _EBI_RDTIMING_RESETVALUE 0x00000000UL /**< Default value for EBI_RDTIMING */\r
+#define _EBI_RDTIMING_MASK 0x00030F03UL /**< Mask for EBI_RDTIMING */\r
+#define _EBI_RDTIMING_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */\r
+#define _EBI_RDTIMING_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */\r
+#define EBI_RDTIMING_RDSETUP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING */\r
+#define _EBI_RDTIMING_RDSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */\r
+#define _EBI_RDTIMING_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */\r
+#define _EBI_RDTIMING_RDSTRB_MASK 0xF00UL /**< Bit mask for EBI_RDSTRB */\r
+#define EBI_RDTIMING_RDSTRB_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING */\r
+#define _EBI_RDTIMING_RDSTRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */\r
+#define _EBI_RDTIMING_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */\r
+#define _EBI_RDTIMING_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */\r
+#define EBI_RDTIMING_RDHOLD_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING */\r
+#define _EBI_RDTIMING_RDHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */\r
+\r
+/** Bit fields for EBI WRTIMING */\r
+#define _EBI_WRTIMING_RESETVALUE 0x00010000UL /**< Default value for EBI_WRTIMING */\r
+#define _EBI_WRTIMING_MASK 0x00030F03UL /**< Mask for EBI_WRTIMING */\r
+#define _EBI_WRTIMING_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */\r
+#define _EBI_WRTIMING_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */\r
+#define EBI_WRTIMING_WRSETUP_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING */\r
+#define _EBI_WRTIMING_WRSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */\r
+#define _EBI_WRTIMING_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */\r
+#define _EBI_WRTIMING_WRSTRB_MASK 0xF00UL /**< Bit mask for EBI_WRSTRB */\r
+#define EBI_WRTIMING_WRSTRB_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING */\r
+#define _EBI_WRTIMING_WRSTRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */\r
+#define _EBI_WRTIMING_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */\r
+#define _EBI_WRTIMING_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */\r
+#define EBI_WRTIMING_WRHOLD_DEFAULT (0x00000001UL << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING */\r
+#define _EBI_WRTIMING_WRHOLD_DEFAULT 0x00000001UL /**< Mode DEFAULT for EBI_WRTIMING */\r
+\r
+/** Bit fields for EBI POLARITY */\r
+#define _EBI_POLARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY */\r
+#define _EBI_POLARITY_MASK 0x0000001FUL /**< Mask for EBI_POLARITY */\r
+#define EBI_POLARITY_CSPOL (1 << 0) /**< Chip Select Polarity */\r
+#define _EBI_POLARITY_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */\r
+#define _EBI_POLARITY_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */\r
+#define EBI_POLARITY_CSPOL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EBI_POLARITY */\r
+#define EBI_POLARITY_CSPOL_ACTIVELOW (0x00000000UL << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY */\r
+#define EBI_POLARITY_CSPOL_ACTIVEHIGH (0x00000001UL << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */\r
+#define _EBI_POLARITY_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */\r
+#define _EBI_POLARITY_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */\r
+#define _EBI_POLARITY_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */\r
+#define EBI_POLARITY_REPOL (1 << 1) /**< Read Enable Polarity */\r
+#define _EBI_POLARITY_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */\r
+#define _EBI_POLARITY_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */\r
+#define EBI_POLARITY_REPOL_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for EBI_POLARITY */\r
+#define EBI_POLARITY_REPOL_ACTIVELOW (0x00000000UL << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY */\r
+#define EBI_POLARITY_REPOL_ACTIVEHIGH (0x00000001UL << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */\r
+#define _EBI_POLARITY_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */\r
+#define _EBI_POLARITY_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */\r
+#define _EBI_POLARITY_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */\r
+#define EBI_POLARITY_WEPOL (1 << 2) /**< Write Enable Polarity */\r
+#define _EBI_POLARITY_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */\r
+#define _EBI_POLARITY_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */\r
+#define EBI_POLARITY_WEPOL_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for EBI_POLARITY */\r
+#define EBI_POLARITY_WEPOL_ACTIVELOW (0x00000000UL << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY */\r
+#define EBI_POLARITY_WEPOL_ACTIVEHIGH (0x00000001UL << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */\r
+#define _EBI_POLARITY_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */\r
+#define _EBI_POLARITY_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */\r
+#define _EBI_POLARITY_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */\r
+#define EBI_POLARITY_ALEPOL (1 << 3) /**< Address Latch Polarity */\r
+#define _EBI_POLARITY_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */\r
+#define _EBI_POLARITY_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */\r
+#define EBI_POLARITY_ALEPOL_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for EBI_POLARITY */\r
+#define EBI_POLARITY_ALEPOL_ACTIVELOW (0x00000000UL << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY */\r
+#define EBI_POLARITY_ALEPOL_ACTIVEHIGH (0x00000001UL << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */\r
+#define _EBI_POLARITY_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */\r
+#define _EBI_POLARITY_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */\r
+#define _EBI_POLARITY_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */\r
+#define EBI_POLARITY_ARDYPOL (1 << 4) /**< ARDY Polarity */\r
+#define _EBI_POLARITY_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */\r
+#define _EBI_POLARITY_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */\r
+#define EBI_POLARITY_ARDYPOL_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for EBI_POLARITY */\r
+#define EBI_POLARITY_ARDYPOL_ACTIVELOW (0x00000000UL << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY */\r
+#define EBI_POLARITY_ARDYPOL_ACTIVEHIGH (0x00000001UL << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */\r
+#define _EBI_POLARITY_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */\r
+#define _EBI_POLARITY_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */\r
+#define _EBI_POLARITY_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */\r
+\r
+/** Bit fields for EBI ROUTE */\r
+#define _EBI_ROUTE_RESETVALUE 0x00000000UL /**< Default value for EBI_ROUTE */\r
+#define _EBI_ROUTE_MASK 0x0000007FUL /**< Mask for EBI_ROUTE */\r
+#define EBI_ROUTE_EBIPEN (1 << 0) /**< EBI Pin Enable */\r
+#define _EBI_ROUTE_EBIPEN_SHIFT 0 /**< Shift value for EBI_EBIPEN */\r
+#define _EBI_ROUTE_EBIPEN_MASK 0x1UL /**< Bit mask for EBI_EBIPEN */\r
+#define EBI_ROUTE_EBIPEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for EBI_ROUTE */\r
+#define _EBI_ROUTE_EBIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */\r
+#define EBI_ROUTE_CS0PEN (1 << 1) /**< EBI_CS0 Pin Enable */\r
+#define _EBI_ROUTE_CS0PEN_SHIFT 1 /**< Shift value for EBI_CS0PEN */\r
+#define _EBI_ROUTE_CS0PEN_MASK 0x2UL /**< Bit mask for EBI_CS0PEN */\r
+#define EBI_ROUTE_CS0PEN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for EBI_ROUTE */\r
+#define _EBI_ROUTE_CS0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */\r
+#define EBI_ROUTE_CS1PEN (1 << 2) /**< EBI_CS1 Pin Enable */\r
+#define _EBI_ROUTE_CS1PEN_SHIFT 2 /**< Shift value for EBI_CS1PEN */\r
+#define _EBI_ROUTE_CS1PEN_MASK 0x4UL /**< Bit mask for EBI_CS1PEN */\r
+#define EBI_ROUTE_CS1PEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for EBI_ROUTE */\r
+#define _EBI_ROUTE_CS1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */\r
+#define EBI_ROUTE_CS2PEN (1 << 3) /**< EBI_CS2 Pin Enable */\r
+#define _EBI_ROUTE_CS2PEN_SHIFT 3 /**< Shift value for EBI_CS2PEN */\r
+#define _EBI_ROUTE_CS2PEN_MASK 0x8UL /**< Bit mask for EBI_CS2PEN */\r
+#define EBI_ROUTE_CS2PEN_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for EBI_ROUTE */\r
+#define _EBI_ROUTE_CS2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */\r
+#define EBI_ROUTE_CS3PEN (1 << 4) /**< EBI_CS3 Pin Enable */\r
+#define _EBI_ROUTE_CS3PEN_SHIFT 4 /**< Shift value for EBI_CS3PEN */\r
+#define _EBI_ROUTE_CS3PEN_MASK 0x10UL /**< Bit mask for EBI_CS3PEN */\r
+#define EBI_ROUTE_CS3PEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for EBI_ROUTE */\r
+#define _EBI_ROUTE_CS3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */\r
+#define EBI_ROUTE_ALEPEN (1 << 5) /**< EBI_ALE Pin Enable */\r
+#define _EBI_ROUTE_ALEPEN_SHIFT 5 /**< Shift value for EBI_ALEPEN */\r
+#define _EBI_ROUTE_ALEPEN_MASK 0x20UL /**< Bit mask for EBI_ALEPEN */\r
+#define EBI_ROUTE_ALEPEN_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for EBI_ROUTE */\r
+#define _EBI_ROUTE_ALEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */\r
+#define EBI_ROUTE_ARDYPEN (1 << 6) /**< EBI_ARDY Pin Enable */\r
+#define _EBI_ROUTE_ARDYPEN_SHIFT 6 /**< Shift value for EBI_ARDYPEN */\r
+#define _EBI_ROUTE_ARDYPEN_MASK 0x40UL /**< Bit mask for EBI_ARDYPEN */\r
+#define EBI_ROUTE_ARDYPEN_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for EBI_ROUTE */\r
+#define _EBI_ROUTE_ARDYPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_GPIO\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for GPIO P_CTRL */\r
+#define _GPIO_P_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_CTRL */\r
+#define _GPIO_P_CTRL_MASK 0x00000003UL /**< Mask for GPIO_P_CTRL */\r
+#define _GPIO_P_CTRL_DRIVEMODE_SHIFT 0 /**< Shift value for GPIO_DRIVEMODE */\r
+#define _GPIO_P_CTRL_DRIVEMODE_MASK 0x3UL /**< Bit mask for GPIO_DRIVEMODE */\r
+#define GPIO_P_CTRL_DRIVEMODE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DRIVEMODE_STANDARD (0x00000000UL << 0) /**< Shifted mode STANDARD for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DRIVEMODE_LOWEST (0x00000001UL << 0) /**< Shifted mode LOWEST for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DRIVEMODE_HIGH (0x00000002UL << 0) /**< Shifted mode HIGH for GPIO_P_CTRL */\r
+#define GPIO_P_CTRL_DRIVEMODE_LOW (0x00000003UL << 0) /**< Shifted mode LOW for GPIO_P_CTRL */\r
+#define _GPIO_P_CTRL_DRIVEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */\r
+#define _GPIO_P_CTRL_DRIVEMODE_STANDARD 0x00000000UL /**< Mode STANDARD for GPIO_P_CTRL */\r
+#define _GPIO_P_CTRL_DRIVEMODE_LOWEST 0x00000001UL /**< Mode LOWEST for GPIO_P_CTRL */\r
+#define _GPIO_P_CTRL_DRIVEMODE_HIGH 0x00000002UL /**< Mode HIGH for GPIO_P_CTRL */\r
+#define _GPIO_P_CTRL_DRIVEMODE_LOW 0x00000003UL /**< Mode LOW for GPIO_P_CTRL */\r
+\r
+/** Bit fields for GPIO P_MODEL */\r
+#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */\r
+#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */\r
+#define GPIO_P_MODEL_MODE0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_DISABLED (0x00000000UL << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_INPUT (0x00000001UL << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_INPUTPULL (0x00000002UL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (0x00000003UL << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_PUSHPULL (0x00000004UL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_PUSHPULLDRIVE (0x00000005UL << 0) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDOR (0x00000006UL << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (0x00000007UL << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDAND (0x00000008UL << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (0x00000009UL << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (0x0000000AUL << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (0x0000000BUL << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDANDDRIVE (0x0000000CUL << 0) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER (0x0000000DUL << 0) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP (0x0000000EUL << 0) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 0) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */\r
+#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */\r
+#define GPIO_P_MODEL_MODE1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_DISABLED (0x00000000UL << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_INPUT (0x00000001UL << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_INPUTPULL (0x00000002UL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (0x00000003UL << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_PUSHPULL (0x00000004UL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_PUSHPULLDRIVE (0x00000005UL << 4) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDOR (0x00000006UL << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (0x00000007UL << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDAND (0x00000008UL << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (0x00000009UL << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (0x0000000AUL << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (0x0000000BUL << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDANDDRIVE (0x0000000CUL << 4) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER (0x0000000DUL << 4) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP (0x0000000EUL << 4) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 4) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */\r
+#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */\r
+#define GPIO_P_MODEL_MODE2_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_DISABLED (0x00000000UL << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_INPUT (0x00000001UL << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_INPUTPULL (0x00000002UL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (0x00000003UL << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_PUSHPULL (0x00000004UL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_PUSHPULLDRIVE (0x00000005UL << 8) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDOR (0x00000006UL << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (0x00000007UL << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDAND (0x00000008UL << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (0x00000009UL << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (0x0000000AUL << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (0x0000000BUL << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDANDDRIVE (0x0000000CUL << 8) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER (0x0000000DUL << 8) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP (0x0000000EUL << 8) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 8) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */\r
+#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */\r
+#define GPIO_P_MODEL_MODE3_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_DISABLED (0x00000000UL << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_INPUT (0x00000001UL << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_INPUTPULL (0x00000002UL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (0x00000003UL << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_PUSHPULL (0x00000004UL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_PUSHPULLDRIVE (0x00000005UL << 12) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDOR (0x00000006UL << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (0x00000007UL << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDAND (0x00000008UL << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (0x00000009UL << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (0x0000000AUL << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (0x0000000BUL << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDANDDRIVE (0x0000000CUL << 12) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER (0x0000000DUL << 12) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP (0x0000000EUL << 12) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 12) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */\r
+#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */\r
+#define GPIO_P_MODEL_MODE4_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_DISABLED (0x00000000UL << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_INPUT (0x00000001UL << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_INPUTPULL (0x00000002UL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (0x00000003UL << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_PUSHPULL (0x00000004UL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_PUSHPULLDRIVE (0x00000005UL << 16) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDOR (0x00000006UL << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (0x00000007UL << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDAND (0x00000008UL << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (0x00000009UL << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (0x0000000AUL << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (0x0000000BUL << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDANDDRIVE (0x0000000CUL << 16) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER (0x0000000DUL << 16) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP (0x0000000EUL << 16) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 16) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */\r
+#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */\r
+#define GPIO_P_MODEL_MODE5_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_DISABLED (0x00000000UL << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_INPUT (0x00000001UL << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_INPUTPULL (0x00000002UL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (0x00000003UL << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_PUSHPULL (0x00000004UL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_PUSHPULLDRIVE (0x00000005UL << 20) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDOR (0x00000006UL << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (0x00000007UL << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDAND (0x00000008UL << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (0x00000009UL << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (0x0000000AUL << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (0x0000000BUL << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDANDDRIVE (0x0000000CUL << 20) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER (0x0000000DUL << 20) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP (0x0000000EUL << 20) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 20) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */\r
+#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */\r
+#define GPIO_P_MODEL_MODE6_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_DISABLED (0x00000000UL << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_INPUT (0x00000001UL << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_INPUTPULL (0x00000002UL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (0x00000003UL << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_PUSHPULL (0x00000004UL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_PUSHPULLDRIVE (0x00000005UL << 24) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDOR (0x00000006UL << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (0x00000007UL << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDAND (0x00000008UL << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (0x00000009UL << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (0x0000000AUL << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (0x0000000BUL << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDANDDRIVE (0x0000000CUL << 24) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER (0x0000000DUL << 24) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP (0x0000000EUL << 24) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 24) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */\r
+#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */\r
+#define GPIO_P_MODEL_MODE7_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_DISABLED (0x00000000UL << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_INPUT (0x00000001UL << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_INPUTPULL (0x00000002UL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (0x00000003UL << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_PUSHPULL (0x00000004UL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_PUSHPULLDRIVE (0x00000005UL << 28) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDOR (0x00000006UL << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (0x00000007UL << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDAND (0x00000008UL << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (0x00000009UL << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (0x0000000AUL << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (0x0000000BUL << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDANDDRIVE (0x0000000CUL << 28) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER (0x0000000DUL << 28) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP (0x0000000EUL << 28) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 28) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */\r
+#define _GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */\r
+\r
+/** Bit fields for GPIO P_MODEH */\r
+#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_SHIFT 0 /**< Shift value for GPIO_MODE8 */\r
+#define _GPIO_P_MODEH_MODE8_MASK 0xFUL /**< Bit mask for GPIO_MODE8 */\r
+#define GPIO_P_MODEH_MODE8_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_DISABLED (0x00000000UL << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_INPUT (0x00000001UL << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_INPUTPULL (0x00000002UL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_INPUTPULLFILTER (0x00000003UL << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_PUSHPULL (0x00000004UL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_PUSHPULLDRIVE (0x00000005UL << 0) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDOR (0x00000006UL << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDORPULLDOWN (0x00000007UL << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDAND (0x00000008UL << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDANDFILTER (0x00000009UL << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDANDPULLUP (0x0000000AUL << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER (0x0000000BUL << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDANDDRIVE (0x0000000CUL << 0) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER (0x0000000DUL << 0) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP (0x0000000EUL << 0) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 0) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_SHIFT 4 /**< Shift value for GPIO_MODE9 */\r
+#define _GPIO_P_MODEH_MODE9_MASK 0xF0UL /**< Bit mask for GPIO_MODE9 */\r
+#define GPIO_P_MODEH_MODE9_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_DISABLED (0x00000000UL << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_INPUT (0x00000001UL << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_INPUTPULL (0x00000002UL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_INPUTPULLFILTER (0x00000003UL << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_PUSHPULL (0x00000004UL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_PUSHPULLDRIVE (0x00000005UL << 4) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDOR (0x00000006UL << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDORPULLDOWN (0x00000007UL << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDAND (0x00000008UL << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDANDFILTER (0x00000009UL << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDANDPULLUP (0x0000000AUL << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER (0x0000000BUL << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDANDDRIVE (0x0000000CUL << 4) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER (0x0000000DUL << 4) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP (0x0000000EUL << 4) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 4) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_SHIFT 8 /**< Shift value for GPIO_MODE10 */\r
+#define _GPIO_P_MODEH_MODE10_MASK 0xF00UL /**< Bit mask for GPIO_MODE10 */\r
+#define GPIO_P_MODEH_MODE10_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_DISABLED (0x00000000UL << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_INPUT (0x00000001UL << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_INPUTPULL (0x00000002UL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_INPUTPULLFILTER (0x00000003UL << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_PUSHPULL (0x00000004UL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_PUSHPULLDRIVE (0x00000005UL << 8) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDOR (0x00000006UL << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDORPULLDOWN (0x00000007UL << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDAND (0x00000008UL << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDANDFILTER (0x00000009UL << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDANDPULLUP (0x0000000AUL << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER (0x0000000BUL << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDANDDRIVE (0x0000000CUL << 8) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER (0x0000000DUL << 8) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP (0x0000000EUL << 8) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 8) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_SHIFT 12 /**< Shift value for GPIO_MODE11 */\r
+#define _GPIO_P_MODEH_MODE11_MASK 0xF000UL /**< Bit mask for GPIO_MODE11 */\r
+#define GPIO_P_MODEH_MODE11_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_DISABLED (0x00000000UL << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_INPUT (0x00000001UL << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_INPUTPULL (0x00000002UL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_INPUTPULLFILTER (0x00000003UL << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_PUSHPULL (0x00000004UL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_PUSHPULLDRIVE (0x00000005UL << 12) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDOR (0x00000006UL << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDORPULLDOWN (0x00000007UL << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDAND (0x00000008UL << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDANDFILTER (0x00000009UL << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDANDPULLUP (0x0000000AUL << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER (0x0000000BUL << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDANDDRIVE (0x0000000CUL << 12) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER (0x0000000DUL << 12) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP (0x0000000EUL << 12) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 12) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_SHIFT 16 /**< Shift value for GPIO_MODE12 */\r
+#define _GPIO_P_MODEH_MODE12_MASK 0xF0000UL /**< Bit mask for GPIO_MODE12 */\r
+#define GPIO_P_MODEH_MODE12_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_DISABLED (0x00000000UL << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_INPUT (0x00000001UL << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_INPUTPULL (0x00000002UL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_INPUTPULLFILTER (0x00000003UL << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_PUSHPULL (0x00000004UL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_PUSHPULLDRIVE (0x00000005UL << 16) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDOR (0x00000006UL << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDORPULLDOWN (0x00000007UL << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDAND (0x00000008UL << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDANDFILTER (0x00000009UL << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDANDPULLUP (0x0000000AUL << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER (0x0000000BUL << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDANDDRIVE (0x0000000CUL << 16) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER (0x0000000DUL << 16) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP (0x0000000EUL << 16) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 16) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_SHIFT 20 /**< Shift value for GPIO_MODE13 */\r
+#define _GPIO_P_MODEH_MODE13_MASK 0xF00000UL /**< Bit mask for GPIO_MODE13 */\r
+#define GPIO_P_MODEH_MODE13_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_DISABLED (0x00000000UL << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_INPUT (0x00000001UL << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_INPUTPULL (0x00000002UL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_INPUTPULLFILTER (0x00000003UL << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_PUSHPULL (0x00000004UL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_PUSHPULLDRIVE (0x00000005UL << 20) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDOR (0x00000006UL << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDORPULLDOWN (0x00000007UL << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDAND (0x00000008UL << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDANDFILTER (0x00000009UL << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDANDPULLUP (0x0000000AUL << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER (0x0000000BUL << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDANDDRIVE (0x0000000CUL << 20) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER (0x0000000DUL << 20) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP (0x0000000EUL << 20) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 20) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_SHIFT 24 /**< Shift value for GPIO_MODE14 */\r
+#define _GPIO_P_MODEH_MODE14_MASK 0xF000000UL /**< Bit mask for GPIO_MODE14 */\r
+#define GPIO_P_MODEH_MODE14_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_DISABLED (0x00000000UL << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_INPUT (0x00000001UL << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_INPUTPULL (0x00000002UL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_INPUTPULLFILTER (0x00000003UL << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_PUSHPULL (0x00000004UL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_PUSHPULLDRIVE (0x00000005UL << 24) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDOR (0x00000006UL << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDORPULLDOWN (0x00000007UL << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDAND (0x00000008UL << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDANDFILTER (0x00000009UL << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDANDPULLUP (0x0000000AUL << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER (0x0000000BUL << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDANDDRIVE (0x0000000CUL << 24) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER (0x0000000DUL << 24) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP (0x0000000EUL << 24) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 24) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_SHIFT 28 /**< Shift value for GPIO_MODE15 */\r
+#define _GPIO_P_MODEH_MODE15_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE15 */\r
+#define GPIO_P_MODEH_MODE15_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_DISABLED (0x00000000UL << 28) /**< Shifted mode DISABLED for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_INPUT (0x00000001UL << 28) /**< Shifted mode INPUT for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_INPUTPULL (0x00000002UL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_INPUTPULLFILTER (0x00000003UL << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_PUSHPULL (0x00000004UL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_PUSHPULLDRIVE (0x00000005UL << 28) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDOR (0x00000006UL << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDORPULLDOWN (0x00000007UL << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDAND (0x00000008UL << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDANDFILTER (0x00000009UL << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDANDPULLUP (0x0000000AUL << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER (0x0000000BUL << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDANDDRIVE (0x0000000CUL << 28) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER (0x0000000DUL << 28) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP (0x0000000EUL << 28) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER (0x0000000FUL << 28) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */\r
+#define _GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */\r
+\r
+/** Bit fields for GPIO P_DOUT */\r
+#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */\r
+#define _GPIO_P_DOUT_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUT */\r
+#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */\r
+#define _GPIO_P_DOUT_DOUT_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUT */\r
+#define GPIO_P_DOUT_DOUT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */\r
+#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */\r
+\r
+/** Bit fields for GPIO P_DOUTSET */\r
+#define _GPIO_P_DOUTSET_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTSET */\r
+#define _GPIO_P_DOUTSET_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTSET */\r
+#define _GPIO_P_DOUTSET_DOUTSET_SHIFT 0 /**< Shift value for GPIO_DOUTSET */\r
+#define _GPIO_P_DOUTSET_DOUTSET_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTSET */\r
+#define GPIO_P_DOUTSET_DOUTSET_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTSET */\r
+#define _GPIO_P_DOUTSET_DOUTSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTSET */\r
+\r
+/** Bit fields for GPIO P_DOUTCLR */\r
+#define _GPIO_P_DOUTCLR_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTCLR */\r
+#define _GPIO_P_DOUTCLR_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTCLR */\r
+#define _GPIO_P_DOUTCLR_DOUTCLR_SHIFT 0 /**< Shift value for GPIO_DOUTCLR */\r
+#define _GPIO_P_DOUTCLR_DOUTCLR_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTCLR */\r
+#define GPIO_P_DOUTCLR_DOUTCLR_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTCLR */\r
+#define _GPIO_P_DOUTCLR_DOUTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTCLR */\r
+\r
+/** Bit fields for GPIO P_DOUTTGL */\r
+#define _GPIO_P_DOUTTGL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTTGL */\r
+#define _GPIO_P_DOUTTGL_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTTGL */\r
+#define _GPIO_P_DOUTTGL_DOUTTGL_SHIFT 0 /**< Shift value for GPIO_DOUTTGL */\r
+#define _GPIO_P_DOUTTGL_DOUTTGL_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTTGL */\r
+#define GPIO_P_DOUTTGL_DOUTTGL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTTGL */\r
+#define _GPIO_P_DOUTTGL_DOUTTGL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTTGL */\r
+\r
+/** Bit fields for GPIO P_DIN */\r
+#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */\r
+#define _GPIO_P_DIN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DIN */\r
+#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */\r
+#define _GPIO_P_DIN_DIN_MASK 0xFFFFUL /**< Bit mask for GPIO_DIN */\r
+#define GPIO_P_DIN_DIN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */\r
+#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */\r
+\r
+/** Bit fields for GPIO P_PINLOCKN */\r
+#define _GPIO_P_PINLOCKN_RESETVALUE 0x0000FFFFUL /**< Default value for GPIO_P_PINLOCKN */\r
+#define _GPIO_P_PINLOCKN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_PINLOCKN */\r
+#define _GPIO_P_PINLOCKN_PINLOCKN_SHIFT 0 /**< Shift value for GPIO_PINLOCKN */\r
+#define _GPIO_P_PINLOCKN_PINLOCKN_MASK 0xFFFFUL /**< Bit mask for GPIO_PINLOCKN */\r
+#define GPIO_P_PINLOCKN_PINLOCKN_DEFAULT (0x0000FFFFUL << 0) /**< Shifted mode DEFAULT for GPIO_P_PINLOCKN */\r
+#define _GPIO_P_PINLOCKN_PINLOCKN_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for GPIO_P_PINLOCKN */\r
+\r
+/** Bit fields for GPIO EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_MASK 0x77777777UL /**< Mask for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x7UL /**< Bit mask for GPIO_EXTIPSEL0 */\r
+#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (0x00000000UL << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (0x00000001UL << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (0x00000002UL << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (0x00000003UL << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTE (0x00000004UL << 0) /**< Shifted mode PORTE for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL0_PORTF (0x00000005UL << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x70UL /**< Bit mask for GPIO_EXTIPSEL1 */\r
+#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (0x00000000UL << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (0x00000001UL << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (0x00000002UL << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (0x00000003UL << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTE (0x00000004UL << 4) /**< Shifted mode PORTE for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL1_PORTF (0x00000005UL << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x700UL /**< Bit mask for GPIO_EXTIPSEL2 */\r
+#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (0x00000000UL << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (0x00000001UL << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (0x00000002UL << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (0x00000003UL << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTE (0x00000004UL << 8) /**< Shifted mode PORTE for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL2_PORTF (0x00000005UL << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x7000UL /**< Bit mask for GPIO_EXTIPSEL3 */\r
+#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (0x00000000UL << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (0x00000001UL << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (0x00000002UL << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (0x00000003UL << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTE (0x00000004UL << 12) /**< Shifted mode PORTE for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL3_PORTF (0x00000005UL << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x70000UL /**< Bit mask for GPIO_EXTIPSEL4 */\r
+#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (0x00000000UL << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (0x00000001UL << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (0x00000002UL << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (0x00000003UL << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTE (0x00000004UL << 16) /**< Shifted mode PORTE for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL4_PORTF (0x00000005UL << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x700000UL /**< Bit mask for GPIO_EXTIPSEL5 */\r
+#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (0x00000000UL << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (0x00000001UL << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (0x00000002UL << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (0x00000003UL << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTE (0x00000004UL << 20) /**< Shifted mode PORTE for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL5_PORTF (0x00000005UL << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x7000000UL /**< Bit mask for GPIO_EXTIPSEL6 */\r
+#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (0x00000000UL << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (0x00000001UL << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (0x00000002UL << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (0x00000003UL << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTE (0x00000004UL << 24) /**< Shifted mode PORTE for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL6_PORTF (0x00000005UL << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x70000000UL /**< Bit mask for GPIO_EXTIPSEL7 */\r
+#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (0x00000000UL << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (0x00000001UL << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (0x00000002UL << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (0x00000003UL << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTE (0x00000004UL << 28) /**< Shifted mode PORTE for GPIO_EXTIPSELL */\r
+#define GPIO_EXTIPSELL_EXTIPSEL7_PORTF (0x00000005UL << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */\r
+#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */\r
+\r
+/** Bit fields for GPIO EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_MASK 0x77777777UL /**< Mask for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL8 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_MASK 0x7UL /**< Bit mask for GPIO_EXTIPSEL8 */\r
+#define GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTA (0x00000000UL << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTB (0x00000001UL << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTC (0x00000002UL << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTD (0x00000003UL << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTE (0x00000004UL << 0) /**< Shifted mode PORTE for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL8_PORTF (0x00000005UL << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL9 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_MASK 0x70UL /**< Bit mask for GPIO_EXTIPSEL9 */\r
+#define GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTA (0x00000000UL << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTB (0x00000001UL << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTC (0x00000002UL << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTD (0x00000003UL << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTE (0x00000004UL << 4) /**< Shifted mode PORTE for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL9_PORTF (0x00000005UL << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL10 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_MASK 0x700UL /**< Bit mask for GPIO_EXTIPSEL10 */\r
+#define GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTA (0x00000000UL << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTB (0x00000001UL << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTC (0x00000002UL << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTD (0x00000003UL << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTE (0x00000004UL << 8) /**< Shifted mode PORTE for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL10_PORTF (0x00000005UL << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL11 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_MASK 0x7000UL /**< Bit mask for GPIO_EXTIPSEL11 */\r
+#define GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTA (0x00000000UL << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTB (0x00000001UL << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTC (0x00000002UL << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTD (0x00000003UL << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTE (0x00000004UL << 12) /**< Shifted mode PORTE for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL11_PORTF (0x00000005UL << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL12 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_MASK 0x70000UL /**< Bit mask for GPIO_EXTIPSEL12 */\r
+#define GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTA (0x00000000UL << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTB (0x00000001UL << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTC (0x00000002UL << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTD (0x00000003UL << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTE (0x00000004UL << 16) /**< Shifted mode PORTE for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL12_PORTF (0x00000005UL << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL13 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_MASK 0x700000UL /**< Bit mask for GPIO_EXTIPSEL13 */\r
+#define GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT (0x00000000UL << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTA (0x00000000UL << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTB (0x00000001UL << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTC (0x00000002UL << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTD (0x00000003UL << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTE (0x00000004UL << 20) /**< Shifted mode PORTE for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL13_PORTF (0x00000005UL << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL14 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_MASK 0x7000000UL /**< Bit mask for GPIO_EXTIPSEL14 */\r
+#define GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTA (0x00000000UL << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTB (0x00000001UL << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTC (0x00000002UL << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTD (0x00000003UL << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTE (0x00000004UL << 24) /**< Shifted mode PORTE for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL14_PORTF (0x00000005UL << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL16_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL16 */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL16_MASK 0x70000000UL /**< Bit mask for GPIO_EXTIPSEL16 */\r
+#define GPIO_EXTIPSELH_EXTIPSEL16_DEFAULT (0x00000000UL << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL16_PORTA (0x00000000UL << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL16_PORTB (0x00000001UL << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL16_PORTC (0x00000002UL << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL16_PORTD (0x00000003UL << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL16_PORTE (0x00000004UL << 28) /**< Shifted mode PORTE for GPIO_EXTIPSELH */\r
+#define GPIO_EXTIPSELH_EXTIPSEL16_PORTF (0x00000005UL << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL16_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL16_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL16_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL16_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL16_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL16_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */\r
+#define _GPIO_EXTIPSELH_EXTIPSEL16_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */\r
+\r
+/** Bit fields for GPIO EXTIRISE */\r
+#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */\r
+#define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */\r
+#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */\r
+#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */\r
+#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */\r
+#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */\r
+\r
+/** Bit fields for GPIO EXTIFALL */\r
+#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */\r
+#define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */\r
+#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */\r
+#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */\r
+#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */\r
+#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */\r
+\r
+/** Bit fields for GPIO IEN */\r
+#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */\r
+#define _GPIO_IEN_MASK 0x0000FFFFUL /**< Mask for GPIO_IEN */\r
+#define _GPIO_IEN_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */\r
+#define _GPIO_IEN_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */\r
+#define GPIO_IEN_EXT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_IEN */\r
+#define _GPIO_IEN_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */\r
+\r
+/** Bit fields for GPIO IF */\r
+#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */\r
+#define _GPIO_IF_MASK 0x0000FFFFUL /**< Mask for GPIO_IF */\r
+#define _GPIO_IF_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */\r
+#define _GPIO_IF_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */\r
+#define GPIO_IF_EXT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_IF */\r
+#define _GPIO_IF_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */\r
+\r
+/** Bit fields for GPIO IFS */\r
+#define _GPIO_IFS_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFS */\r
+#define _GPIO_IFS_MASK 0x0000FFFFUL /**< Mask for GPIO_IFS */\r
+#define _GPIO_IFS_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */\r
+#define _GPIO_IFS_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */\r
+#define GPIO_IFS_EXT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_IFS */\r
+#define _GPIO_IFS_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */\r
+\r
+/** Bit fields for GPIO IFC */\r
+#define _GPIO_IFC_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFC */\r
+#define _GPIO_IFC_MASK 0x0000FFFFUL /**< Mask for GPIO_IFC */\r
+#define _GPIO_IFC_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */\r
+#define _GPIO_IFC_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */\r
+#define GPIO_IFC_EXT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_IFC */\r
+#define _GPIO_IFC_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */\r
+\r
+/** Bit fields for GPIO ROUTE */\r
+#define _GPIO_ROUTE_RESETVALUE 0x00000003UL /**< Default value for GPIO_ROUTE */\r
+#define _GPIO_ROUTE_MASK 0x00000307UL /**< Mask for GPIO_ROUTE */\r
+#define GPIO_ROUTE_SWCLKPEN (1 << 0) /**< Serial Wire Clock Pin Enable */\r
+#define _GPIO_ROUTE_SWCLKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKPEN */\r
+#define _GPIO_ROUTE_SWCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKPEN */\r
+#define GPIO_ROUTE_SWCLKPEN_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for GPIO_ROUTE */\r
+#define _GPIO_ROUTE_SWCLKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTE */\r
+#define GPIO_ROUTE_SWDIOPEN (1 << 1) /**< Serial Wire Data Pin Enable */\r
+#define _GPIO_ROUTE_SWDIOPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOPEN */\r
+#define _GPIO_ROUTE_SWDIOPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOPEN */\r
+#define GPIO_ROUTE_SWDIOPEN_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for GPIO_ROUTE */\r
+#define _GPIO_ROUTE_SWDIOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTE */\r
+#define GPIO_ROUTE_SWVPEN (1 << 2) /**< Serial Wire Viewer Pin Enable */\r
+#define _GPIO_ROUTE_SWVPEN_SHIFT 2 /**< Shift value for GPIO_SWVPEN */\r
+#define _GPIO_ROUTE_SWVPEN_MASK 0x4UL /**< Bit mask for GPIO_SWVPEN */\r
+#define GPIO_ROUTE_SWVPEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for GPIO_ROUTE */\r
+#define _GPIO_ROUTE_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */\r
+#define _GPIO_ROUTE_SWLOCATION_SHIFT 8 /**< Shift value for GPIO_SWLOCATION */\r
+#define _GPIO_ROUTE_SWLOCATION_MASK 0x300UL /**< Bit mask for GPIO_SWLOCATION */\r
+#define GPIO_ROUTE_SWLOCATION_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for GPIO_ROUTE */\r
+#define GPIO_ROUTE_SWLOCATION_LOC0 (0x00000000UL << 8) /**< Shifted mode LOC0 for GPIO_ROUTE */\r
+#define GPIO_ROUTE_SWLOCATION_LOC1 (0x00000001UL << 8) /**< Shifted mode LOC1 for GPIO_ROUTE */\r
+#define GPIO_ROUTE_SWLOCATION_LOC2 (0x00000002UL << 8) /**< Shifted mode LOC2 for GPIO_ROUTE */\r
+#define GPIO_ROUTE_SWLOCATION_LOC3 (0x00000003UL << 8) /**< Shifted mode LOC3 for GPIO_ROUTE */\r
+#define _GPIO_ROUTE_SWLOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */\r
+#define _GPIO_ROUTE_SWLOCATION_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTE */\r
+#define _GPIO_ROUTE_SWLOCATION_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTE */\r
+#define _GPIO_ROUTE_SWLOCATION_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTE */\r
+#define _GPIO_ROUTE_SWLOCATION_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTE */\r
+\r
+/** Bit fields for GPIO INSENSE */\r
+#define _GPIO_INSENSE_RESETVALUE 0x00000003UL /**< Default value for GPIO_INSENSE */\r
+#define _GPIO_INSENSE_MASK 0x00000003UL /**< Mask for GPIO_INSENSE */\r
+#define GPIO_INSENSE_INTSENSE (1 << 0) /**< Interrupt Sense Enable */\r
+#define _GPIO_INSENSE_INTSENSE_SHIFT 0 /**< Shift value for GPIO_INTSENSE */\r
+#define _GPIO_INSENSE_INTSENSE_MASK 0x1UL /**< Bit mask for GPIO_INTSENSE */\r
+#define GPIO_INSENSE_INTSENSE_DEFAULT (0x00000001UL << 0) /**< Shifted mode DEFAULT for GPIO_INSENSE */\r
+#define _GPIO_INSENSE_INTSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */\r
+#define GPIO_INSENSE_PRSSENSE (1 << 1) /**< PRS Sense Enable */\r
+#define _GPIO_INSENSE_PRSSENSE_SHIFT 1 /**< Shift value for GPIO_PRSSENSE */\r
+#define _GPIO_INSENSE_PRSSENSE_MASK 0x2UL /**< Bit mask for GPIO_PRSSENSE */\r
+#define GPIO_INSENSE_PRSSENSE_DEFAULT (0x00000001UL << 1) /**< Shifted mode DEFAULT for GPIO_INSENSE */\r
+#define _GPIO_INSENSE_PRSSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */\r
+\r
+/** Bit fields for GPIO LOCK */\r
+#define _GPIO_LOCK_RESETVALUE 0x00000000UL /**< Default value for GPIO_LOCK */\r
+#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */\r
+#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */\r
+#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */\r
+#define GPIO_LOCK_LOCKKEY_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */\r
+#define GPIO_LOCK_LOCKKEY_LOCK (0x00000000UL << 0) /**< Shifted mode LOCK for GPIO_LOCK */\r
+#define GPIO_LOCK_LOCKKEY_UNLOCKED (0x00000000UL << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */\r
+#define GPIO_LOCK_LOCKKEY_LOCKED (0x00000001UL << 0) /**< Shifted mode LOCKED for GPIO_LOCK */\r
+#define GPIO_LOCK_LOCKKEY_UNLOCK (0x0000A534UL << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */\r
+#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */\r
+#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */\r
+#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */\r
+#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */\r
+#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_PRS\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for PRS SWPULSE */\r
+#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
+#define _PRS_SWPULSE_MASK 0x000000FFUL /**< Mask for PRS_SWPULSE */\r
+#define _PRS_SWPULSE_SWPULSE_SHIFT 0 /**< Shift value for PRS_SWPULSE */\r
+#define _PRS_SWPULSE_SWPULSE_MASK 0xFFUL /**< Bit mask for PRS_SWPULSE */\r
+#define PRS_SWPULSE_SWPULSE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
+#define _PRS_SWPULSE_SWPULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
+\r
+/** Bit fields for PRS SWLEVEL */\r
+#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
+#define _PRS_SWLEVEL_MASK 0x000000FFUL /**< Mask for PRS_SWLEVEL */\r
+#define _PRS_SWLEVEL_SWLEVEL_SHIFT 0 /**< Shift value for PRS_SWLEVEL */\r
+#define _PRS_SWLEVEL_SWLEVEL_MASK 0xFFUL /**< Bit mask for PRS_SWLEVEL */\r
+#define PRS_SWLEVEL_SWLEVEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
+#define _PRS_SWLEVEL_SWLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
+\r
+/** Bit fields for PRS CH_CTRL */\r
+#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_MASK 0x033F0007UL /**< Mask for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
+#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
+#define PRS_CH_CTRL_SIGSEL_VCMPOUT (0x00000000UL << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (0x00000000UL << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (0x00000000UL << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (0x00000000UL << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (0x00000000UL << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART0IRTX (0x00000000UL << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_RTCOF (0x00000000UL << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (0x00000000UL << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (0x00000000UL << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (0x00000001UL << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (0x00000001UL << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART0TXC (0x00000001UL << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART1TXC (0x00000001UL << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART2TXC (0x00000001UL << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (0x00000001UL << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_UART0TXC (0x00000001UL << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (0x00000001UL << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (0x00000001UL << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (0x00000002UL << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (0x00000002UL << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (0x00000002UL << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (0x00000002UL << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (0x00000002UL << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (0x00000002UL << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (0x00000002UL << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (0x00000003UL << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (0x00000003UL << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (0x00000004UL << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (0x00000004UL << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (0x00000005UL << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (0x00000005UL << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (0x00000006UL << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (0x00000006UL << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (0x00000007UL << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (0x00000007UL << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
+#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
+#define PRS_CH_CTRL_SOURCESEL_NONE (0x00000000UL << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_VCMP (0x00000001UL << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_ACMP0 (0x00000002UL << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_ACMP1 (0x00000003UL << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_DAC0 (0x00000006UL << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_ADC0 (0x00000008UL << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_USART0 (0x00000010UL << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_USART1 (0x00000011UL << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_USART2 (0x00000012UL << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_TIMER0 (0x0000001CUL << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_TIMER1 (0x0000001DUL << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_TIMER2 (0x0000001EUL << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_RTC (0x00000028UL << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_UART0 (0x00000029UL << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_GPIOL (0x00000030UL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_SOURCESEL_GPIOH (0x00000031UL << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
+#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
+#define PRS_CH_CTRL_EDSEL_DEFAULT (0x00000000UL << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_EDSEL_OFF (0x00000000UL << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_EDSEL_POSEDGE (0x00000001UL << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_EDSEL_NEGEDGE (0x00000002UL << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
+#define PRS_CH_CTRL_EDSEL_BOTHEDGES (0x00000003UL << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
+#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_DMA\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for DMA STATUS */\r
+#define _DMA_STATUS_RESETVALUE 0x10070000UL /**< Default value for DMA_STATUS */\r
+#define _DMA_STATUS_MASK 0xF01F00F1UL /**< Mask for DMA_STATUS */\r
+#define DMA_STATUS_EN (1 << 0) /**< DMA Enable Status */\r
+#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
+#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
+#define DMA_STATUS_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
+#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
+#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
+#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
+#define DMA_STATUS_STATE_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
+#define DMA_STATUS_STATE_IDLE (0x00000000UL << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
+#define DMA_STATUS_STATE_RDCHCTRLDATA (0x00000001UL << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
+#define DMA_STATUS_STATE_RDSRCENDPTR (0x00000002UL << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
+#define DMA_STATUS_STATE_RDDSTENDPTR (0x00000003UL << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
+#define DMA_STATUS_STATE_RDSRCDATA (0x00000004UL << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
+#define DMA_STATUS_STATE_WRDSTDATA (0x00000005UL << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
+#define DMA_STATUS_STATE_WAITREQCLR (0x00000006UL << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
+#define DMA_STATUS_STATE_WRCHCTRLDATA (0x00000007UL << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
+#define DMA_STATUS_STATE_STALLED (0x00000008UL << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
+#define DMA_STATUS_STATE_DONE (0x00000009UL << 4) /**< Shifted mode DONE for DMA_STATUS */\r
+#define DMA_STATUS_STATE_PERSCATTRANS (0x0000000AUL << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
+#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
+#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
+#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
+#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
+#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
+#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
+#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
+#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
+#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
+#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
+#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
+#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
+#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
+#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
+#define DMA_STATUS_CHNUM_DEFAULT (0x00000007UL << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
+#define _DMA_STATUS_CHNUM_DEFAULT 0x00000007UL /**< Mode DEFAULT for DMA_STATUS */\r
+#define _DMA_STATUS_TEST_SHIFT 28 /**< Shift value for DMA_TEST */\r
+#define _DMA_STATUS_TEST_MASK 0xF0000000UL /**< Bit mask for DMA_TEST */\r
+#define DMA_STATUS_TEST_DEFAULT (0x00000001UL << 28) /**< Shifted mode DEFAULT for DMA_STATUS */\r
+#define _DMA_STATUS_TEST_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_STATUS */\r
+\r
+/** Bit fields for DMA CONFIG */\r
+#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
+#define _DMA_CONFIG_MASK 0x000000E1UL /**< Mask for DMA_CONFIG */\r
+#define DMA_CONFIG_EN (1 << 0) /**< Enable DMA */\r
+#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
+#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
+#define DMA_CONFIG_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
+#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
+#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
+#define _DMA_CONFIG_CHPROT_MASK 0xE0UL /**< Bit mask for DMA_CHPROT */\r
+#define DMA_CONFIG_CHPROT_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
+#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
+\r
+/** Bit fields for DMA CTRLBASE */\r
+#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
+#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
+#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
+#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
+#define DMA_CTRLBASE_CTRLBASE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
+#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
+\r
+/** Bit fields for DMA ALTCTRLBASE */\r
+#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000080UL /**< Default value for DMA_ALTCTRLBASE */\r
+#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
+#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
+#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
+#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (0x00000080UL << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
+#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000080UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
+\r
+/** Bit fields for DMA WAITSTATUS */\r
+#define _DMA_WAITSTATUS_RESETVALUE 0x000000FFUL /**< Default value for DMA_WAITSTATUS */\r
+#define _DMA_WAITSTATUS_MASK 0xFFFFFFFFUL /**< Mask for DMA_WAITSTATUS */\r
+#define _DMA_WAITSTATUS_WAITSTATUS_SHIFT 0 /**< Shift value for DMA_WAITSTATUS */\r
+#define _DMA_WAITSTATUS_WAITSTATUS_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_WAITSTATUS */\r
+#define DMA_WAITSTATUS_WAITSTATUS_DEFAULT (0x000000FFUL << 0) /**< Shifted mode DEFAULT for DMA_WAITSTATUS */\r
+#define _DMA_WAITSTATUS_WAITSTATUS_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DMA_WAITSTATUS */\r
+\r
+/** Bit fields for DMA CHSWREQ */\r
+#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
+#define _DMA_CHSWREQ_MASK 0x000000FFUL /**< Mask for DMA_CHSWREQ */\r
+#define _DMA_CHSWREQ_CHSWREQ_SHIFT 0 /**< Shift value for DMA_CHSWREQ */\r
+#define _DMA_CHSWREQ_CHSWREQ_MASK 0xFFUL /**< Bit mask for DMA_CHSWREQ */\r
+#define DMA_CHSWREQ_CHSWREQ_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
+#define _DMA_CHSWREQ_CHSWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
+\r
+/** Bit fields for DMA CHUSEBURSTS */\r
+#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
+#define _DMA_CHUSEBURSTS_MASK 0x000000FFUL /**< Mask for DMA_CHUSEBURSTS */\r
+#define _DMA_CHUSEBURSTS_CHUSEBURSTS_SHIFT 0 /**< Shift value for DMA_CHUSEBURSTS */\r
+#define _DMA_CHUSEBURSTS_CHUSEBURSTS_MASK 0xFFUL /**< Bit mask for DMA_CHUSEBURSTS */\r
+#define DMA_CHUSEBURSTS_CHUSEBURSTS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
+#define DMA_CHUSEBURSTS_CHUSEBURSTS_SINGLEANDBURST (0x00000000UL << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
+#define DMA_CHUSEBURSTS_CHUSEBURSTS_BURSTONLY (0x00000001UL << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
+#define _DMA_CHUSEBURSTS_CHUSEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
+#define _DMA_CHUSEBURSTS_CHUSEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
+#define _DMA_CHUSEBURSTS_CHUSEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
+\r
+/** Bit fields for DMA CHUSEBURSTC */\r
+#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
+#define _DMA_CHUSEBURSTC_MASK 0x000000FFUL /**< Mask for DMA_CHUSEBURSTC */\r
+#define _DMA_CHUSEBURSTC_CHUSEBURSTC_SHIFT 0 /**< Shift value for DMA_CHUSEBURSTC */\r
+#define _DMA_CHUSEBURSTC_CHUSEBURSTC_MASK 0xFFUL /**< Bit mask for DMA_CHUSEBURSTC */\r
+#define DMA_CHUSEBURSTC_CHUSEBURSTC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
+#define _DMA_CHUSEBURSTC_CHUSEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
+\r
+/** Bit fields for DMA CHREQMASKS */\r
+#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
+#define _DMA_CHREQMASKS_MASK 0x000000FFUL /**< Mask for DMA_CHREQMASKS */\r
+#define _DMA_CHREQMASKS_CHREQMASKS_SHIFT 0 /**< Shift value for DMA_CHREQMASKS */\r
+#define _DMA_CHREQMASKS_CHREQMASKS_MASK 0xFFUL /**< Bit mask for DMA_CHREQMASKS */\r
+#define DMA_CHREQMASKS_CHREQMASKS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
+#define _DMA_CHREQMASKS_CHREQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
+\r
+/** Bit fields for DMA CHREQMASKC */\r
+#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
+#define _DMA_CHREQMASKC_MASK 0x000000FFUL /**< Mask for DMA_CHREQMASKC */\r
+#define _DMA_CHREQMASKC_CHREQMASKC_SHIFT 0 /**< Shift value for DMA_CHREQMASKC */\r
+#define _DMA_CHREQMASKC_CHREQMASKC_MASK 0xFFUL /**< Bit mask for DMA_CHREQMASKC */\r
+#define DMA_CHREQMASKC_CHREQMASKC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
+#define _DMA_CHREQMASKC_CHREQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
+\r
+/** Bit fields for DMA CHENS */\r
+#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
+#define _DMA_CHENS_MASK 0x000000FFUL /**< Mask for DMA_CHENS */\r
+#define _DMA_CHENS_CHENS_SHIFT 0 /**< Shift value for DMA_CHENS */\r
+#define _DMA_CHENS_CHENS_MASK 0xFFUL /**< Bit mask for DMA_CHENS */\r
+#define DMA_CHENS_CHENS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
+#define _DMA_CHENS_CHENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
+\r
+/** Bit fields for DMA CHENC */\r
+#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
+#define _DMA_CHENC_MASK 0x000000FFUL /**< Mask for DMA_CHENC */\r
+#define _DMA_CHENC_CHENC_SHIFT 0 /**< Shift value for DMA_CHENC */\r
+#define _DMA_CHENC_CHENC_MASK 0xFFUL /**< Bit mask for DMA_CHENC */\r
+#define DMA_CHENC_CHENC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
+#define _DMA_CHENC_CHENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
+\r
+/** Bit fields for DMA CHALTS */\r
+#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
+#define _DMA_CHALTS_MASK 0x000000FFUL /**< Mask for DMA_CHALTS */\r
+#define _DMA_CHALTS_CHALTS_SHIFT 0 /**< Shift value for DMA_CHALTS */\r
+#define _DMA_CHALTS_CHALTS_MASK 0xFFUL /**< Bit mask for DMA_CHALTS */\r
+#define DMA_CHALTS_CHALTS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
+#define _DMA_CHALTS_CHALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
+\r
+/** Bit fields for DMA CHALTC */\r
+#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
+#define _DMA_CHALTC_MASK 0x000000FFUL /**< Mask for DMA_CHALTC */\r
+#define _DMA_CHALTC_CHALTC_SHIFT 0 /**< Shift value for DMA_CHALTC */\r
+#define _DMA_CHALTC_CHALTC_MASK 0xFFUL /**< Bit mask for DMA_CHALTC */\r
+#define DMA_CHALTC_CHALTC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
+#define _DMA_CHALTC_CHALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
+\r
+/** Bit fields for DMA CHPRIS */\r
+#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
+#define _DMA_CHPRIS_MASK 0x000000FFUL /**< Mask for DMA_CHPRIS */\r
+#define _DMA_CHPRIS_CHPRIS_SHIFT 0 /**< Shift value for DMA_CHPRIS */\r
+#define _DMA_CHPRIS_CHPRIS_MASK 0xFFUL /**< Bit mask for DMA_CHPRIS */\r
+#define DMA_CHPRIS_CHPRIS_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
+#define _DMA_CHPRIS_CHPRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
+\r
+/** Bit fields for DMA CHPRIC */\r
+#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
+#define _DMA_CHPRIC_MASK 0x000000FFUL /**< Mask for DMA_CHPRIC */\r
+#define _DMA_CHPRIC_CHPRIC_SHIFT 0 /**< Shift value for DMA_CHPRIC */\r
+#define _DMA_CHPRIC_CHPRIC_MASK 0xFFUL /**< Bit mask for DMA_CHPRIC */\r
+#define DMA_CHPRIC_CHPRIC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
+#define _DMA_CHPRIC_CHPRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
+\r
+/** Bit fields for DMA ERRORC */\r
+#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
+#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
+#define DMA_ERRORC_ERRORC (1 << 0) /**< Bus Error Clear */\r
+#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
+#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
+#define DMA_ERRORC_ERRORC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
+#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
+\r
+/** Bit fields for DMA IF */\r
+#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
+#define _DMA_IF_MASK 0x800000FFUL /**< Mask for DMA_IF */\r
+#define _DMA_IF_DONE_SHIFT 0 /**< Shift value for DMA_DONE */\r
+#define _DMA_IF_DONE_MASK 0xFFUL /**< Bit mask for DMA_DONE */\r
+#define DMA_IF_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
+#define _DMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
+#define DMA_IF_ERR (1 << 31) /**< DMA Error Interrupt Flag */\r
+#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
+#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
+#define DMA_IF_ERR_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
+#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
+\r
+/** Bit fields for DMA IFS */\r
+#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
+#define _DMA_IFS_MASK 0x800000FFUL /**< Mask for DMA_IFS */\r
+#define _DMA_IFS_DONE_SHIFT 0 /**< Shift value for DMA_DONE */\r
+#define _DMA_IFS_DONE_MASK 0xFFUL /**< Bit mask for DMA_DONE */\r
+#define DMA_IFS_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
+#define _DMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
+#define DMA_IFS_ERR (1 << 31) /**< DMA Error Interrupt Flag Set */\r
+#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
+#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
+#define DMA_IFS_ERR_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
+#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
+\r
+/** Bit fields for DMA IFC */\r
+#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
+#define _DMA_IFC_MASK 0x800000FFUL /**< Mask for DMA_IFC */\r
+#define _DMA_IFC_DONE_SHIFT 0 /**< Shift value for DMA_DONE */\r
+#define _DMA_IFC_DONE_MASK 0xFFUL /**< Bit mask for DMA_DONE */\r
+#define DMA_IFC_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
+#define _DMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
+#define DMA_IFC_ERR (1 << 31) /**< DMA Error Interrupt Flag Clear */\r
+#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
+#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
+#define DMA_IFC_ERR_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
+#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
+\r
+/** Bit fields for DMA IEN */\r
+#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
+#define _DMA_IEN_MASK 0x800000FFUL /**< Mask for DMA_IEN */\r
+#define _DMA_IEN_DONE_SHIFT 0 /**< Shift value for DMA_DONE */\r
+#define _DMA_IEN_DONE_MASK 0xFFUL /**< Bit mask for DMA_DONE */\r
+#define DMA_IEN_DONE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
+#define _DMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
+#define DMA_IEN_ERR (1 << 31) /**< DMA Error Interrupt Flag Enable */\r
+#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
+#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
+#define DMA_IEN_ERR_DEFAULT (0x00000000UL << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
+#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
+\r
+/** Bit fields for DMA CH_CTRL */\r
+#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
+#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
+#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (0x00000000UL << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (0x00000000UL << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (0x00000000UL << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (0x00000000UL << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (0x00000000UL << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (0x00000000UL << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (0x00000000UL << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (0x00000000UL << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (0x00000000UL << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (0x00000000UL << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (0x00000000UL << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_UART0RXDATAV (0x00000000UL << 0) /**< Shifted mode UART0RXDATAV for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_MSCWDATA (0x00000000UL << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_AESDATAWR (0x00000000UL << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (0x00000001UL << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (0x00000001UL << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_USART0TXBL (0x00000001UL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_USART1TXBL (0x00000001UL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_USART2TXBL (0x00000001UL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (0x00000001UL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (0x00000001UL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (0x00000001UL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000001UL << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000001UL << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000001UL << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_UART0TXBL (0x00000001UL << 0) /**< Shifted mode UART0TXBL for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (0x00000001UL << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (0x00000002UL << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (0x00000002UL << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (0x00000002UL << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (0x00000002UL << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (0x00000002UL << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000002UL << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000002UL << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000002UL << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY (0x00000002UL << 0) /**< Shifted mode UART0TXEMPTY for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_AESDATARD (0x00000002UL << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000003UL << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000003UL << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000003UL << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SIGSEL_AESKEYWR (0x00000003UL << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000000UL /**< Mode UART0RXDATAV for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_UART0TXBL 0x00000001UL /**< Mode UART0TXBL for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_UART0TXEMPTY 0x00000002UL /**< Mode UART0TXEMPTY for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
+#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
+#define DMA_CH_CTRL_SOURCESEL_NONE (0x00000000UL << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SOURCESEL_ADC0 (0x00000008UL << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SOURCESEL_DAC0 (0x0000000AUL << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SOURCESEL_USART0 (0x0000000CUL << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SOURCESEL_USART1 (0x0000000DUL << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SOURCESEL_USART2 (0x0000000EUL << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SOURCESEL_LEUART0 (0x00000010UL << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SOURCESEL_LEUART1 (0x00000011UL << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SOURCESEL_I2C0 (0x00000014UL << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SOURCESEL_TIMER0 (0x00000018UL << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SOURCESEL_TIMER1 (0x00000019UL << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SOURCESEL_TIMER2 (0x0000001AUL << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SOURCESEL_UART0 (0x0000002CUL << 16) /**< Shifted mode UART0 for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SOURCESEL_IMEM (0x00000030UL << 16) /**< Shifted mode IMEM for DMA_CH_CTRL */\r
+#define DMA_CH_CTRL_SOURCESEL_AES (0x00000031UL << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_UART0 0x0000002CUL /**< Mode UART0 for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_IMEM 0x00000030UL /**< Mode IMEM for DMA_CH_CTRL */\r
+#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_VCMP\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for VCMP CTRL */\r
+#define _VCMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for VCMP_CTRL */\r
+#define _VCMP_CTRL_MASK 0x4F030715UL /**< Mask for VCMP_CTRL */\r
+#define VCMP_CTRL_EN (1 << 0) /**< Voltage Supply Comparator Enable */\r
+#define _VCMP_CTRL_EN_SHIFT 0 /**< Shift value for VCMP_EN */\r
+#define _VCMP_CTRL_EN_MASK 0x1UL /**< Bit mask for VCMP_EN */\r
+#define VCMP_CTRL_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for VCMP_CTRL */\r
+#define _VCMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */\r
+#define VCMP_CTRL_INACTVAL (1 << 2) /**< Inactive Value */\r
+#define _VCMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for VCMP_INACTVAL */\r
+#define _VCMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for VCMP_INACTVAL */\r
+#define VCMP_CTRL_INACTVAL_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for VCMP_CTRL */\r
+#define _VCMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */\r
+#define VCMP_CTRL_HYSTEN (1 << 4) /**< Hysteresis Enable */\r
+#define _VCMP_CTRL_HYSTEN_SHIFT 4 /**< Shift value for VCMP_HYSTEN */\r
+#define _VCMP_CTRL_HYSTEN_MASK 0x10UL /**< Bit mask for VCMP_HYSTEN */\r
+#define VCMP_CTRL_HYSTEN_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for VCMP_CTRL */\r
+#define _VCMP_CTRL_HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */\r
+#define _VCMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for VCMP_WARMTIME */\r
+#define _VCMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for VCMP_WARMTIME */\r
+#define VCMP_CTRL_WARMTIME_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for VCMP_CTRL */\r
+#define VCMP_CTRL_WARMTIME_4CYCLES (0x00000000UL << 8) /**< Shifted mode 4CYCLES for VCMP_CTRL */\r
+#define VCMP_CTRL_WARMTIME_8CYCLES (0x00000001UL << 8) /**< Shifted mode 8CYCLES for VCMP_CTRL */\r
+#define VCMP_CTRL_WARMTIME_16CYCLES (0x00000002UL << 8) /**< Shifted mode 16CYCLES for VCMP_CTRL */\r
+#define VCMP_CTRL_WARMTIME_32CYCLES (0x00000003UL << 8) /**< Shifted mode 32CYCLES for VCMP_CTRL */\r
+#define VCMP_CTRL_WARMTIME_64CYCLES (0x00000004UL << 8) /**< Shifted mode 64CYCLES for VCMP_CTRL */\r
+#define VCMP_CTRL_WARMTIME_128CYCLES (0x00000005UL << 8) /**< Shifted mode 128CYCLES for VCMP_CTRL */\r
+#define VCMP_CTRL_WARMTIME_256CYCLES (0x00000006UL << 8) /**< Shifted mode 256CYCLES for VCMP_CTRL */\r
+#define VCMP_CTRL_WARMTIME_512CYCLES (0x00000007UL << 8) /**< Shifted mode 512CYCLES for VCMP_CTRL */\r
+#define _VCMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */\r
+#define _VCMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for VCMP_CTRL */\r
+#define _VCMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for VCMP_CTRL */\r
+#define _VCMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for VCMP_CTRL */\r
+#define _VCMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for VCMP_CTRL */\r
+#define _VCMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for VCMP_CTRL */\r
+#define _VCMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for VCMP_CTRL */\r
+#define _VCMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for VCMP_CTRL */\r
+#define _VCMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for VCMP_CTRL */\r
+#define VCMP_CTRL_IRISE (1 << 16) /**< Rising Edge Interrupt Sense */\r
+#define _VCMP_CTRL_IRISE_SHIFT 16 /**< Shift value for VCMP_IRISE */\r
+#define _VCMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for VCMP_IRISE */\r
+#define VCMP_CTRL_IRISE_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for VCMP_CTRL */\r
+#define _VCMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */\r
+#define VCMP_CTRL_IFALL (1 << 17) /**< Falling Edge Interrupt Sense */\r
+#define _VCMP_CTRL_IFALL_SHIFT 17 /**< Shift value for VCMP_IFALL */\r
+#define _VCMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for VCMP_IFALL */\r
+#define VCMP_CTRL_IFALL_DEFAULT (0x00000000UL << 17) /**< Shifted mode DEFAULT for VCMP_CTRL */\r
+#define _VCMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */\r
+#define _VCMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for VCMP_BIASPROG */\r
+#define _VCMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for VCMP_BIASPROG */\r
+#define VCMP_CTRL_BIASPROG_DEFAULT (0x00000007UL << 24) /**< Shifted mode DEFAULT for VCMP_CTRL */\r
+#define _VCMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for VCMP_CTRL */\r
+#define VCMP_CTRL_HALFBIAS (1 << 30) /**< Half Bias Current */\r
+#define _VCMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for VCMP_HALFBIAS */\r
+#define _VCMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for VCMP_HALFBIAS */\r
+#define VCMP_CTRL_HALFBIAS_DEFAULT (0x00000001UL << 30) /**< Shifted mode DEFAULT for VCMP_CTRL */\r
+#define _VCMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VCMP_CTRL */\r
+\r
+/** Bit fields for VCMP INPUTSEL */\r
+#define _VCMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for VCMP_INPUTSEL */\r
+#define _VCMP_INPUTSEL_MASK 0x0000013FUL /**< Mask for VCMP_INPUTSEL */\r
+#define _VCMP_INPUTSEL_TRIGLEVEL_SHIFT 0 /**< Shift value for VCMP_TRIGLEVEL */\r
+#define _VCMP_INPUTSEL_TRIGLEVEL_MASK 0x3FUL /**< Bit mask for VCMP_TRIGLEVEL */\r
+#define VCMP_INPUTSEL_TRIGLEVEL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */\r
+#define _VCMP_INPUTSEL_TRIGLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */\r
+#define VCMP_INPUTSEL_LPREF (1 << 8) /**< Low Power Reference */\r
+#define _VCMP_INPUTSEL_LPREF_SHIFT 8 /**< Shift value for VCMP_LPREF */\r
+#define _VCMP_INPUTSEL_LPREF_MASK 0x100UL /**< Bit mask for VCMP_LPREF */\r
+#define VCMP_INPUTSEL_LPREF_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */\r
+#define _VCMP_INPUTSEL_LPREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */\r
+\r
+/** Bit fields for VCMP STATUS */\r
+#define _VCMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for VCMP_STATUS */\r
+#define _VCMP_STATUS_MASK 0x00000003UL /**< Mask for VCMP_STATUS */\r
+#define VCMP_STATUS_VCMPACT (1 << 0) /**< Voltage Supply Comparator Active */\r
+#define _VCMP_STATUS_VCMPACT_SHIFT 0 /**< Shift value for VCMP_VCMPACT */\r
+#define _VCMP_STATUS_VCMPACT_MASK 0x1UL /**< Bit mask for VCMP_VCMPACT */\r
+#define VCMP_STATUS_VCMPACT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for VCMP_STATUS */\r
+#define _VCMP_STATUS_VCMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */\r
+#define VCMP_STATUS_VCMPOUT (1 << 1) /**< Voltage Supply Comparator Output */\r
+#define _VCMP_STATUS_VCMPOUT_SHIFT 1 /**< Shift value for VCMP_VCMPOUT */\r
+#define _VCMP_STATUS_VCMPOUT_MASK 0x2UL /**< Bit mask for VCMP_VCMPOUT */\r
+#define VCMP_STATUS_VCMPOUT_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for VCMP_STATUS */\r
+#define _VCMP_STATUS_VCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */\r
+\r
+/** Bit fields for VCMP IEN */\r
+#define _VCMP_IEN_RESETVALUE 0x00000000UL /**< Default value for VCMP_IEN */\r
+#define _VCMP_IEN_MASK 0x00000003UL /**< Mask for VCMP_IEN */\r
+#define VCMP_IEN_EDGE (1 << 0) /**< Edge Trigger Interrupt Enable */\r
+#define _VCMP_IEN_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */\r
+#define _VCMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */\r
+#define VCMP_IEN_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for VCMP_IEN */\r
+#define _VCMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */\r
+#define VCMP_IEN_WARMUP (1 << 1) /**< Warm-up Interrupt Enable */\r
+#define _VCMP_IEN_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */\r
+#define _VCMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */\r
+#define VCMP_IEN_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for VCMP_IEN */\r
+#define _VCMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */\r
+\r
+/** Bit fields for VCMP IF */\r
+#define _VCMP_IF_RESETVALUE 0x00000000UL /**< Default value for VCMP_IF */\r
+#define _VCMP_IF_MASK 0x00000003UL /**< Mask for VCMP_IF */\r
+#define VCMP_IF_EDGE (1 << 0) /**< Edge Triggered Interrupt Flag */\r
+#define _VCMP_IF_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */\r
+#define _VCMP_IF_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */\r
+#define VCMP_IF_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for VCMP_IF */\r
+#define _VCMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */\r
+#define VCMP_IF_WARMUP (1 << 1) /**< Warm-up Interrupt Flag */\r
+#define _VCMP_IF_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */\r
+#define _VCMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */\r
+#define VCMP_IF_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for VCMP_IF */\r
+#define _VCMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */\r
+\r
+/** Bit fields for VCMP IFS */\r
+#define _VCMP_IFS_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFS */\r
+#define _VCMP_IFS_MASK 0x00000003UL /**< Mask for VCMP_IFS */\r
+#define VCMP_IFS_EDGE (1 << 0) /**< Edge Triggered Interrupt Flag Set */\r
+#define _VCMP_IFS_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */\r
+#define _VCMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */\r
+#define VCMP_IFS_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for VCMP_IFS */\r
+#define _VCMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */\r
+#define VCMP_IFS_WARMUP (1 << 1) /**< Warm-up Interrupt Flag Set */\r
+#define _VCMP_IFS_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */\r
+#define _VCMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */\r
+#define VCMP_IFS_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for VCMP_IFS */\r
+#define _VCMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */\r
+\r
+/** Bit fields for VCMP IFC */\r
+#define _VCMP_IFC_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFC */\r
+#define _VCMP_IFC_MASK 0x00000003UL /**< Mask for VCMP_IFC */\r
+#define VCMP_IFC_EDGE (1 << 0) /**< Edge Triggered Interrupt Flag Clear */\r
+#define _VCMP_IFC_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */\r
+#define _VCMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */\r
+#define VCMP_IFC_EDGE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for VCMP_IFC */\r
+#define _VCMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */\r
+#define VCMP_IFC_WARMUP (1 << 1) /**< Warm-up Interrupt Flag Clear */\r
+#define _VCMP_IFC_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */\r
+#define _VCMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */\r
+#define VCMP_IFC_WARMUP_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for VCMP_IFC */\r
+#define _VCMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_LCD\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for LCD CTRL */\r
+#define _LCD_CTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_CTRL */\r
+#define _LCD_CTRL_MASK 0x00000007UL /**< Mask for LCD_CTRL */\r
+#define LCD_CTRL_EN (1 << 0) /**< LCD Enable */\r
+#define _LCD_CTRL_EN_SHIFT 0 /**< Shift value for LCD_EN */\r
+#define _LCD_CTRL_EN_MASK 0x1UL /**< Bit mask for LCD_EN */\r
+#define LCD_CTRL_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_CTRL */\r
+#define _LCD_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */\r
+#define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */\r
+#define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */\r
+#define LCD_CTRL_UDCTRL_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LCD_CTRL */\r
+#define LCD_CTRL_UDCTRL_REGULAR (0x00000000UL << 1) /**< Shifted mode REGULAR for LCD_CTRL */\r
+#define LCD_CTRL_UDCTRL_LFCEVENT (0x00000001UL << 1) /**< Shifted mode LFCEVENT for LCD_CTRL */\r
+#define LCD_CTRL_UDCTRL_FRAMESTART (0x00000002UL << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */\r
+#define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */\r
+#define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */\r
+#define _LCD_CTRL_UDCTRL_LFCEVENT 0x00000001UL /**< Mode LFCEVENT for LCD_CTRL */\r
+#define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL /**< Mode FRAMESTART for LCD_CTRL */\r
+\r
+/** Bit fields for LCD DISPCTRL */\r
+#define _LCD_DISPCTRL_RESETVALUE 0x000C1F00UL /**< Default value for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_MASK 0x001D9F1FUL /**< Mask for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */\r
+#define _LCD_DISPCTRL_MUX_MASK 0x3UL /**< Bit mask for LCD_MUX */\r
+#define LCD_DISPCTRL_MUX_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_MUX_STATIC (0x00000000UL << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_MUX_DUPLEX (0x00000001UL << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_MUX_TRIPLEX (0x00000002UL << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_MUX_QUADRUPLEX (0x00000003UL << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_BIAS_SHIFT 2 /**< Shift value for LCD_BIAS */\r
+#define _LCD_DISPCTRL_BIAS_MASK 0xCUL /**< Bit mask for LCD_BIAS */\r
+#define LCD_DISPCTRL_BIAS_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_BIAS_STATIC (0x00000000UL << 2) /**< Shifted mode STATIC for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_BIAS_ONEHALF (0x00000001UL << 2) /**< Shifted mode ONEHALF for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_BIAS_ONETHIRD (0x00000002UL << 2) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_WAVE (1 << 4) /**< Waveform Selection */\r
+#define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */\r
+#define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */\r
+#define LCD_DISPCTRL_WAVE_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_WAVE_LOWPOWER (0x00000000UL << 4) /**< Shifted mode LOWPOWER for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_WAVE_NORMAL (0x00000001UL << 4) /**< Shifted mode NORMAL for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL /**< Mode LOWPOWER for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL /**< Mode NORMAL for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_CONLEV_SHIFT 8 /**< Shift value for LCD_CONLEV */\r
+#define _LCD_DISPCTRL_CONLEV_MASK 0x1F00UL /**< Bit mask for LCD_CONLEV */\r
+#define LCD_DISPCTRL_CONLEV_MIN (0x00000000UL << 8) /**< Shifted mode MIN for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_CONLEV_DEFAULT (0x0000001FUL << 8) /**< Shifted mode DEFAULT for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_CONLEV_MAX (0x0000001FUL << 8) /**< Shifted mode MAX for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_CONLEV_MIN 0x00000000UL /**< Mode MIN for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_CONLEV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_CONLEV_MAX 0x0000001FUL /**< Mode MAX for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_CONCONF (1 << 15) /**< Contrast Configuration */\r
+#define _LCD_DISPCTRL_CONCONF_SHIFT 15 /**< Shift value for LCD_CONCONF */\r
+#define _LCD_DISPCTRL_CONCONF_MASK 0x8000UL /**< Bit mask for LCD_CONCONF */\r
+#define LCD_DISPCTRL_CONCONF_DEFAULT (0x00000000UL << 15) /**< Shifted mode DEFAULT for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_CONCONF_VLCD (0x00000000UL << 15) /**< Shifted mode VLCD for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_CONCONF_GND (0x00000001UL << 15) /**< Shifted mode GND for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_CONCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_CONCONF_VLCD 0x00000000UL /**< Mode VLCD for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_CONCONF_GND 0x00000001UL /**< Mode GND for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_VLCDSEL (1 << 16) /**< VLCD Selection */\r
+#define _LCD_DISPCTRL_VLCDSEL_SHIFT 16 /**< Shift value for LCD_VLCDSEL */\r
+#define _LCD_DISPCTRL_VLCDSEL_MASK 0x10000UL /**< Bit mask for LCD_VLCDSEL */\r
+#define LCD_DISPCTRL_VLCDSEL_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_VLCDSEL_VDD (0x00000000UL << 16) /**< Shifted mode VDD for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (0x00000001UL << 16) /**< Shifted mode VEXTBOOST for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_VLCDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_VLCDSEL_VDD 0x00000000UL /**< Mode VDD for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_VLCDSEL_VEXTBOOST 0x00000001UL /**< Mode VEXTBOOST for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_VBLEV_SHIFT 18 /**< Shift value for LCD_VBLEV */\r
+#define _LCD_DISPCTRL_VBLEV_MASK 0x1C0000UL /**< Bit mask for LCD_VBLEV */\r
+#define LCD_DISPCTRL_VBLEV_3V00 (0x00000000UL << 18) /**< Shifted mode 3V00 for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_VBLEV_3V09 (0x00000001UL << 18) /**< Shifted mode 3V09 for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_VBLEV_3V17 (0x00000002UL << 18) /**< Shifted mode 3V17 for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_VBLEV_DEFAULT (0x00000003UL << 18) /**< Shifted mode DEFAULT for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_VBLEV_3V26 (0x00000003UL << 18) /**< Shifted mode 3V26 for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_VBLEV_3V34 (0x00000004UL << 18) /**< Shifted mode 3V34 for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_VBLEV_3V43 (0x00000005UL << 18) /**< Shifted mode 3V43 for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_VBLEV_3V51 (0x00000006UL << 18) /**< Shifted mode 3V51 for LCD_DISPCTRL */\r
+#define LCD_DISPCTRL_VBLEV_3V60 (0x00000007UL << 18) /**< Shifted mode 3V60 for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_VBLEV_3V00 0x00000000UL /**< Mode 3V00 for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_VBLEV_3V09 0x00000001UL /**< Mode 3V09 for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_VBLEV_3V17 0x00000002UL /**< Mode 3V17 for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_VBLEV_DEFAULT 0x00000003UL /**< Mode DEFAULT for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_VBLEV_3V26 0x00000003UL /**< Mode 3V26 for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_VBLEV_3V34 0x00000004UL /**< Mode 3V34 for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_VBLEV_3V43 0x00000005UL /**< Mode 3V43 for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_VBLEV_3V51 0x00000006UL /**< Mode 3V51 for LCD_DISPCTRL */\r
+#define _LCD_DISPCTRL_VBLEV_3V60 0x00000007UL /**< Mode 3V60 for LCD_DISPCTRL */\r
+\r
+/** Bit fields for LCD SEGEN */\r
+#define _LCD_SEGEN_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN */\r
+#define _LCD_SEGEN_MASK 0x000003FFUL /**< Mask for LCD_SEGEN */\r
+#define _LCD_SEGEN_SEGEN_SHIFT 0 /**< Shift value for LCD_SEGEN */\r
+#define _LCD_SEGEN_SEGEN_MASK 0x3FFUL /**< Bit mask for LCD_SEGEN */\r
+#define LCD_SEGEN_SEGEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGEN */\r
+#define _LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN */\r
+\r
+/** Bit fields for LCD BACTRL */\r
+#define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */\r
+#define _LCD_BACTRL_MASK 0x00FF01FFUL /**< Mask for LCD_BACTRL */\r
+#define LCD_BACTRL_BLINKEN (1 << 0) /**< Blink Enable */\r
+#define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */\r
+#define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */\r
+#define LCD_BACTRL_BLINKEN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */\r
+#define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */\r
+#define LCD_BACTRL_BLANK (1 << 1) /**< Blank Display */\r
+#define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */\r
+#define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */\r
+#define LCD_BACTRL_BLANK_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */\r
+#define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */\r
+#define LCD_BACTRL_AEN (1 << 2) /**< Animation Enable */\r
+#define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */\r
+#define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */\r
+#define LCD_BACTRL_AEN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */\r
+#define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */\r
+#define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */\r
+#define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */\r
+#define LCD_BACTRL_AREGASC_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */\r
+#define LCD_BACTRL_AREGASC_NOSHIFT (0x00000000UL << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */\r
+#define LCD_BACTRL_AREGASC_SHIFTLEFT (0x00000001UL << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */\r
+#define LCD_BACTRL_AREGASC_SHIFTRIGHT (0x00000002UL << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */\r
+#define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */\r
+#define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */\r
+#define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */\r
+#define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */\r
+#define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */\r
+#define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */\r
+#define LCD_BACTRL_AREGBSC_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */\r
+#define LCD_BACTRL_AREGBSC_NOSHIFT (0x00000000UL << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */\r
+#define LCD_BACTRL_AREGBSC_SHIFTLEFT (0x00000001UL << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */\r
+#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (0x00000002UL << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */\r
+#define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */\r
+#define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */\r
+#define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */\r
+#define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */\r
+#define LCD_BACTRL_ALOGSEL (1 << 7) /**< Animate Logic Function Select */\r
+#define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */\r
+#define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */\r
+#define LCD_BACTRL_ALOGSEL_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */\r
+#define LCD_BACTRL_ALOGSEL_AND (0x00000000UL << 7) /**< Shifted mode AND for LCD_BACTRL */\r
+#define LCD_BACTRL_ALOGSEL_OR (0x00000001UL << 7) /**< Shifted mode OR for LCD_BACTRL */\r
+#define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */\r
+#define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */\r
+#define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */\r
+#define LCD_BACTRL_FCEN (1 << 8) /**< Frame Counter Enable */\r
+#define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */\r
+#define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */\r
+#define LCD_BACTRL_FCEN_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */\r
+#define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */\r
+#define _LCD_BACTRL_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */\r
+#define _LCD_BACTRL_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */\r
+#define LCD_BACTRL_FCPRESC_DEFAULT (0x00000000UL << 16) /**< Shifted mode DEFAULT for LCD_BACTRL */\r
+#define LCD_BACTRL_FCPRESC_DIV1 (0x00000000UL << 16) /**< Shifted mode DIV1 for LCD_BACTRL */\r
+#define LCD_BACTRL_FCPRESC_DIV2 (0x00000001UL << 16) /**< Shifted mode DIV2 for LCD_BACTRL */\r
+#define LCD_BACTRL_FCPRESC_DIV4 (0x00000002UL << 16) /**< Shifted mode DIV4 for LCD_BACTRL */\r
+#define LCD_BACTRL_FCPRESC_DIV8 (0x00000003UL << 16) /**< Shifted mode DIV8 for LCD_BACTRL */\r
+#define _LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */\r
+#define _LCD_BACTRL_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACTRL */\r
+#define _LCD_BACTRL_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACTRL */\r
+#define _LCD_BACTRL_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACTRL */\r
+#define _LCD_BACTRL_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACTRL */\r
+#define _LCD_BACTRL_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */\r
+#define _LCD_BACTRL_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */\r
+#define LCD_BACTRL_FCTOP_DEFAULT (0x00000000UL << 18) /**< Shifted mode DEFAULT for LCD_BACTRL */\r
+#define _LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */\r
+\r
+/** Bit fields for LCD STATUS */\r
+#define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */\r
+#define _LCD_STATUS_MASK 0x0000010FUL /**< Mask for LCD_STATUS */\r
+#define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */\r
+#define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */\r
+#define LCD_STATUS_ASTATE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_STATUS */\r
+#define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */\r
+#define LCD_STATUS_BLINK (1 << 8) /**< Blink State */\r
+#define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */\r
+#define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */\r
+#define LCD_STATUS_BLINK_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LCD_STATUS */\r
+#define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */\r
+\r
+/** Bit fields for LCD AREGA */\r
+#define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */\r
+#define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */\r
+#define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */\r
+#define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */\r
+#define LCD_AREGA_AREGA_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_AREGA */\r
+#define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */\r
+\r
+/** Bit fields for LCD AREGB */\r
+#define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */\r
+#define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */\r
+#define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */\r
+#define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */\r
+#define LCD_AREGB_AREGB_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_AREGB */\r
+#define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */\r
+\r
+/** Bit fields for LCD IF */\r
+#define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */\r
+#define _LCD_IF_MASK 0x00000001UL /**< Mask for LCD_IF */\r
+#define LCD_IF_FC (1 << 0) /**< Frame Counter Interrupt Flag */\r
+#define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */\r
+#define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */\r
+#define LCD_IF_FC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_IF */\r
+#define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */\r
+\r
+/** Bit fields for LCD IFS */\r
+#define _LCD_IFS_RESETVALUE 0x00000000UL /**< Default value for LCD_IFS */\r
+#define _LCD_IFS_MASK 0x00000001UL /**< Mask for LCD_IFS */\r
+#define LCD_IFS_FC (1 << 0) /**< Frame Counter Interrupt Flag Set */\r
+#define _LCD_IFS_FC_SHIFT 0 /**< Shift value for LCD_FC */\r
+#define _LCD_IFS_FC_MASK 0x1UL /**< Bit mask for LCD_FC */\r
+#define LCD_IFS_FC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_IFS */\r
+#define _LCD_IFS_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFS */\r
+\r
+/** Bit fields for LCD IFC */\r
+#define _LCD_IFC_RESETVALUE 0x00000000UL /**< Default value for LCD_IFC */\r
+#define _LCD_IFC_MASK 0x00000001UL /**< Mask for LCD_IFC */\r
+#define LCD_IFC_FC (1 << 0) /**< Frame Counter Interrupt Flag Clear */\r
+#define _LCD_IFC_FC_SHIFT 0 /**< Shift value for LCD_FC */\r
+#define _LCD_IFC_FC_MASK 0x1UL /**< Bit mask for LCD_FC */\r
+#define LCD_IFC_FC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_IFC */\r
+#define _LCD_IFC_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFC */\r
+\r
+/** Bit fields for LCD IEN */\r
+#define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */\r
+#define _LCD_IEN_MASK 0x00000001UL /**< Mask for LCD_IEN */\r
+#define LCD_IEN_FC (1 << 0) /**< Frame Counter Interrupt Enable */\r
+#define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */\r
+#define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */\r
+#define LCD_IEN_FC_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_IEN */\r
+#define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */\r
+\r
+/** Bit fields for LCD SEGD0L */\r
+#define _LCD_SEGD0L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0L */\r
+#define _LCD_SEGD0L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD0L */\r
+#define _LCD_SEGD0L_SEGD0L_SHIFT 0 /**< Shift value for LCD_SEGD0L */\r
+#define _LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD0L */\r
+#define LCD_SEGD0L_SEGD0L_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD0L */\r
+#define _LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0L */\r
+\r
+/** Bit fields for LCD SEGD1L */\r
+#define _LCD_SEGD1L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1L */\r
+#define _LCD_SEGD1L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD1L */\r
+#define _LCD_SEGD1L_SEGD1L_SHIFT 0 /**< Shift value for LCD_SEGD1L */\r
+#define _LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD1L */\r
+#define LCD_SEGD1L_SEGD1L_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD1L */\r
+#define _LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1L */\r
+\r
+/** Bit fields for LCD SEGD2L */\r
+#define _LCD_SEGD2L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2L */\r
+#define _LCD_SEGD2L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD2L */\r
+#define _LCD_SEGD2L_SEGD2L_SHIFT 0 /**< Shift value for LCD_SEGD2L */\r
+#define _LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD2L */\r
+#define LCD_SEGD2L_SEGD2L_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD2L */\r
+#define _LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2L */\r
+\r
+/** Bit fields for LCD SEGD3L */\r
+#define _LCD_SEGD3L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3L */\r
+#define _LCD_SEGD3L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD3L */\r
+#define _LCD_SEGD3L_SEGD3L_SHIFT 0 /**< Shift value for LCD_SEGD3L */\r
+#define _LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD3L */\r
+#define LCD_SEGD3L_SEGD3L_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD3L */\r
+#define _LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3L */\r
+\r
+/** Bit fields for LCD SEGD0H */\r
+#define _LCD_SEGD0H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0H */\r
+#define _LCD_SEGD0H_MASK 0x000000FFUL /**< Mask for LCD_SEGD0H */\r
+#define _LCD_SEGD0H_SEGD0H_SHIFT 0 /**< Shift value for LCD_SEGD0H */\r
+#define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL /**< Bit mask for LCD_SEGD0H */\r
+#define LCD_SEGD0H_SEGD0H_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD0H */\r
+#define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0H */\r
+\r
+/** Bit fields for LCD SEGD1H */\r
+#define _LCD_SEGD1H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1H */\r
+#define _LCD_SEGD1H_MASK 0x000000FFUL /**< Mask for LCD_SEGD1H */\r
+#define _LCD_SEGD1H_SEGD1H_SHIFT 0 /**< Shift value for LCD_SEGD1H */\r
+#define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL /**< Bit mask for LCD_SEGD1H */\r
+#define LCD_SEGD1H_SEGD1H_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD1H */\r
+#define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1H */\r
+\r
+/** Bit fields for LCD SEGD2H */\r
+#define _LCD_SEGD2H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2H */\r
+#define _LCD_SEGD2H_MASK 0x000000FFUL /**< Mask for LCD_SEGD2H */\r
+#define _LCD_SEGD2H_SEGD2H_SHIFT 0 /**< Shift value for LCD_SEGD2H */\r
+#define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL /**< Bit mask for LCD_SEGD2H */\r
+#define LCD_SEGD2H_SEGD2H_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD2H */\r
+#define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2H */\r
+\r
+/** Bit fields for LCD SEGD3H */\r
+#define _LCD_SEGD3H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3H */\r
+#define _LCD_SEGD3H_MASK 0x000000FFUL /**< Mask for LCD_SEGD3H */\r
+#define _LCD_SEGD3H_SEGD3H_SHIFT 0 /**< Shift value for LCD_SEGD3H */\r
+#define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL /**< Bit mask for LCD_SEGD3H */\r
+#define LCD_SEGD3H_SEGD3H_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SEGD3H */\r
+#define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3H */\r
+\r
+/** Bit fields for LCD FREEZE */\r
+#define _LCD_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LCD_FREEZE */\r
+#define _LCD_FREEZE_MASK 0x00000001UL /**< Mask for LCD_FREEZE */\r
+#define LCD_FREEZE_REGFREEZE (1 << 0) /**< Register Update Freeze */\r
+#define _LCD_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LCD_REGFREEZE */\r
+#define _LCD_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LCD_REGFREEZE */\r
+#define LCD_FREEZE_REGFREEZE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_FREEZE */\r
+#define LCD_FREEZE_REGFREEZE_UPDATE (0x00000000UL << 0) /**< Shifted mode UPDATE for LCD_FREEZE */\r
+#define LCD_FREEZE_REGFREEZE_FREEZE (0x00000001UL << 0) /**< Shifted mode FREEZE for LCD_FREEZE */\r
+#define _LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */\r
+#define _LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LCD_FREEZE */\r
+#define _LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LCD_FREEZE */\r
+\r
+/** Bit fields for LCD SYNCBUSY */\r
+#define _LCD_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LCD_SYNCBUSY */\r
+#define _LCD_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for LCD_SYNCBUSY */\r
+#define LCD_SYNCBUSY_CTRL (1 << 0) /**< LCD_CTRL Register Busy */\r
+#define _LCD_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LCD_CTRL */\r
+#define _LCD_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LCD_CTRL */\r
+#define LCD_SYNCBUSY_CTRL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */\r
+#define _LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */\r
+#define LCD_SYNCBUSY_BACTRL (1 << 1) /**< LCD_BACTRL Register Busy */\r
+#define _LCD_SYNCBUSY_BACTRL_SHIFT 1 /**< Shift value for LCD_BACTRL */\r
+#define _LCD_SYNCBUSY_BACTRL_MASK 0x2UL /**< Bit mask for LCD_BACTRL */\r
+#define LCD_SYNCBUSY_BACTRL_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */\r
+#define _LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */\r
+#define LCD_SYNCBUSY_AREGA (1 << 2) /**< LCD_AREGA Register Busy */\r
+#define _LCD_SYNCBUSY_AREGA_SHIFT 2 /**< Shift value for LCD_AREGA */\r
+#define _LCD_SYNCBUSY_AREGA_MASK 0x4UL /**< Bit mask for LCD_AREGA */\r
+#define LCD_SYNCBUSY_AREGA_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */\r
+#define _LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */\r
+#define LCD_SYNCBUSY_AREGB (1 << 3) /**< LCD_AREGB Register Busy */\r
+#define _LCD_SYNCBUSY_AREGB_SHIFT 3 /**< Shift value for LCD_AREGB */\r
+#define _LCD_SYNCBUSY_AREGB_MASK 0x8UL /**< Bit mask for LCD_AREGB */\r
+#define LCD_SYNCBUSY_AREGB_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */\r
+#define _LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */\r
+#define LCD_SYNCBUSY_SEGD0L (1 << 4) /**< LCD_SEGD0L Register Busy */\r
+#define _LCD_SYNCBUSY_SEGD0L_SHIFT 4 /**< Shift value for LCD_SEGD0L */\r
+#define _LCD_SYNCBUSY_SEGD0L_MASK 0x10UL /**< Bit mask for LCD_SEGD0L */\r
+#define LCD_SYNCBUSY_SEGD0L_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */\r
+#define _LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */\r
+#define LCD_SYNCBUSY_SEGD1L (1 << 5) /**< LCD_SEGD1L Register Busy */\r
+#define _LCD_SYNCBUSY_SEGD1L_SHIFT 5 /**< Shift value for LCD_SEGD1L */\r
+#define _LCD_SYNCBUSY_SEGD1L_MASK 0x20UL /**< Bit mask for LCD_SEGD1L */\r
+#define LCD_SYNCBUSY_SEGD1L_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */\r
+#define _LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */\r
+#define LCD_SYNCBUSY_SEGD2L (1 << 6) /**< LCD_SEGD2L Register Busy */\r
+#define _LCD_SYNCBUSY_SEGD2L_SHIFT 6 /**< Shift value for LCD_SEGD2L */\r
+#define _LCD_SYNCBUSY_SEGD2L_MASK 0x40UL /**< Bit mask for LCD_SEGD2L */\r
+#define LCD_SYNCBUSY_SEGD2L_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */\r
+#define _LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */\r
+#define LCD_SYNCBUSY_SEGD3L (1 << 7) /**< LCD_SEGD3L Register Busy */\r
+#define _LCD_SYNCBUSY_SEGD3L_SHIFT 7 /**< Shift value for LCD_SEGD3L */\r
+#define _LCD_SYNCBUSY_SEGD3L_MASK 0x80UL /**< Bit mask for LCD_SEGD3L */\r
+#define LCD_SYNCBUSY_SEGD3L_DEFAULT (0x00000000UL << 7) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */\r
+#define _LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */\r
+#define LCD_SYNCBUSY_SEGD0H (1 << 8) /**< LCD_SEGD0H Register Busy */\r
+#define _LCD_SYNCBUSY_SEGD0H_SHIFT 8 /**< Shift value for LCD_SEGD0H */\r
+#define _LCD_SYNCBUSY_SEGD0H_MASK 0x100UL /**< Bit mask for LCD_SEGD0H */\r
+#define LCD_SYNCBUSY_SEGD0H_DEFAULT (0x00000000UL << 8) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */\r
+#define _LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */\r
+#define LCD_SYNCBUSY_SEGD1H (1 << 9) /**< LCD_SEGD1H Register Busy */\r
+#define _LCD_SYNCBUSY_SEGD1H_SHIFT 9 /**< Shift value for LCD_SEGD1H */\r
+#define _LCD_SYNCBUSY_SEGD1H_MASK 0x200UL /**< Bit mask for LCD_SEGD1H */\r
+#define LCD_SYNCBUSY_SEGD1H_DEFAULT (0x00000000UL << 9) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */\r
+#define _LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */\r
+#define LCD_SYNCBUSY_SEGD2H (1 << 10) /**< LCD_SEGD2H Register Busy */\r
+#define _LCD_SYNCBUSY_SEGD2H_SHIFT 10 /**< Shift value for LCD_SEGD2H */\r
+#define _LCD_SYNCBUSY_SEGD2H_MASK 0x400UL /**< Bit mask for LCD_SEGD2H */\r
+#define LCD_SYNCBUSY_SEGD2H_DEFAULT (0x00000000UL << 10) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */\r
+#define _LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */\r
+#define LCD_SYNCBUSY_SEGD3H (1 << 11) /**< LCD_SEGD3H Register Busy */\r
+#define _LCD_SYNCBUSY_SEGD3H_SHIFT 11 /**< Shift value for LCD_SEGD3H */\r
+#define _LCD_SYNCBUSY_SEGD3H_MASK 0x800UL /**< Bit mask for LCD_SEGD3H */\r
+#define LCD_SYNCBUSY_SEGD3H_DEFAULT (0x00000000UL << 11) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */\r
+#define _LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_RTC\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for RTC CTRL */\r
+#define _RTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTC_CTRL */\r
+#define _RTC_CTRL_MASK 0x00000007UL /**< Mask for RTC_CTRL */\r
+#define RTC_CTRL_EN (1 << 0) /**< RTC Enable */\r
+#define _RTC_CTRL_EN_SHIFT 0 /**< Shift value for RTC_EN */\r
+#define _RTC_CTRL_EN_MASK 0x1UL /**< Bit mask for RTC_EN */\r
+#define RTC_CTRL_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_CTRL */\r
+#define _RTC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */\r
+#define RTC_CTRL_DEBUGRUN (1 << 1) /**< Debug Mode Run Enable */\r
+#define _RTC_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for RTC_DEBUGRUN */\r
+#define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for RTC_DEBUGRUN */\r
+#define RTC_CTRL_DEBUGRUN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for RTC_CTRL */\r
+#define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */\r
+#define RTC_CTRL_COMP0TOP (1 << 2) /**< Compare Channel 0 is Top Value */\r
+#define _RTC_CTRL_COMP0TOP_SHIFT 2 /**< Shift value for RTC_COMP0TOP */\r
+#define _RTC_CTRL_COMP0TOP_MASK 0x4UL /**< Bit mask for RTC_COMP0TOP */\r
+#define RTC_CTRL_COMP0TOP_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for RTC_CTRL */\r
+#define RTC_CTRL_COMP0TOP_DISABLE (0x00000000UL << 2) /**< Shifted mode DISABLE for RTC_CTRL */\r
+#define RTC_CTRL_COMP0TOP_ENABLE (0x00000001UL << 2) /**< Shifted mode ENABLE for RTC_CTRL */\r
+#define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */\r
+#define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /**< Mode DISABLE for RTC_CTRL */\r
+#define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /**< Mode ENABLE for RTC_CTRL */\r
+\r
+/** Bit fields for RTC CNT */\r
+#define _RTC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTC_CNT */\r
+#define _RTC_CNT_MASK 0x00FFFFFFUL /**< Mask for RTC_CNT */\r
+#define _RTC_CNT_CNT_SHIFT 0 /**< Shift value for RTC_CNT */\r
+#define _RTC_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for RTC_CNT */\r
+#define RTC_CNT_CNT_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_CNT */\r
+#define _RTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CNT */\r
+\r
+/** Bit fields for RTC COMP0 */\r
+#define _RTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP0 */\r
+#define _RTC_COMP0_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP0 */\r
+#define _RTC_COMP0_COMP0_SHIFT 0 /**< Shift value for RTC_COMP0 */\r
+#define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP0 */\r
+#define RTC_COMP0_COMP0_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_COMP0 */\r
+#define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP0 */\r
+\r
+/** Bit fields for RTC COMP1 */\r
+#define _RTC_COMP1_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP1 */\r
+#define _RTC_COMP1_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP1 */\r
+#define _RTC_COMP1_COMP1_SHIFT 0 /**< Shift value for RTC_COMP1 */\r
+#define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP1 */\r
+#define RTC_COMP1_COMP1_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_COMP1 */\r
+#define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP1 */\r
+\r
+/** Bit fields for RTC IF */\r
+#define _RTC_IF_RESETVALUE 0x00000000UL /**< Default value for RTC_IF */\r
+#define _RTC_IF_MASK 0x00000007UL /**< Mask for RTC_IF */\r
+#define RTC_IF_OF (1 << 0) /**< Overflow Interrupt Flag */\r
+#define _RTC_IF_OF_SHIFT 0 /**< Shift value for RTC_OF */\r
+#define _RTC_IF_OF_MASK 0x1UL /**< Bit mask for RTC_OF */\r
+#define RTC_IF_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_IF */\r
+#define _RTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */\r
+#define RTC_IF_COMP0 (1 << 1) /**< Compare Match 0 Interrupt Flag */\r
+#define _RTC_IF_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */\r
+#define _RTC_IF_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */\r
+#define RTC_IF_COMP0_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for RTC_IF */\r
+#define _RTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */\r
+#define RTC_IF_COMP1 (1 << 2) /**< Compare Match 1 Interrupt Flag */\r
+#define _RTC_IF_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */\r
+#define _RTC_IF_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */\r
+#define RTC_IF_COMP1_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for RTC_IF */\r
+#define _RTC_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */\r
+\r
+/** Bit fields for RTC IFS */\r
+#define _RTC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTC_IFS */\r
+#define _RTC_IFS_MASK 0x00000007UL /**< Mask for RTC_IFS */\r
+#define RTC_IFS_OF (1 << 0) /**< Set Overflow Interrupt Flag */\r
+#define _RTC_IFS_OF_SHIFT 0 /**< Shift value for RTC_OF */\r
+#define _RTC_IFS_OF_MASK 0x1UL /**< Bit mask for RTC_OF */\r
+#define RTC_IFS_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_IFS */\r
+#define _RTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */\r
+#define RTC_IFS_COMP0 (1 << 1) /**< Set Compare match 0 Interrupt Flag */\r
+#define _RTC_IFS_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */\r
+#define _RTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */\r
+#define RTC_IFS_COMP0_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for RTC_IFS */\r
+#define _RTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */\r
+#define RTC_IFS_COMP1 (1 << 2) /**< Set Compare match 1 Interrupt Flag */\r
+#define _RTC_IFS_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */\r
+#define _RTC_IFS_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */\r
+#define RTC_IFS_COMP1_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for RTC_IFS */\r
+#define _RTC_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */\r
+\r
+/** Bit fields for RTC IFC */\r
+#define _RTC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTC_IFC */\r
+#define _RTC_IFC_MASK 0x00000007UL /**< Mask for RTC_IFC */\r
+#define RTC_IFC_OF (1 << 0) /**< Clear Overflow Interrupt Flag */\r
+#define _RTC_IFC_OF_SHIFT 0 /**< Shift value for RTC_OF */\r
+#define _RTC_IFC_OF_MASK 0x1UL /**< Bit mask for RTC_OF */\r
+#define RTC_IFC_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_IFC */\r
+#define _RTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */\r
+#define RTC_IFC_COMP0 (1 << 1) /**< Clear Compare match 0 Interrupt Flag */\r
+#define _RTC_IFC_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */\r
+#define _RTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */\r
+#define RTC_IFC_COMP0_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for RTC_IFC */\r
+#define _RTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */\r
+#define RTC_IFC_COMP1 (1 << 2) /**< Clear Compare match 1 Interrupt Flag */\r
+#define _RTC_IFC_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */\r
+#define _RTC_IFC_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */\r
+#define RTC_IFC_COMP1_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for RTC_IFC */\r
+#define _RTC_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */\r
+\r
+/** Bit fields for RTC IEN */\r
+#define _RTC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTC_IEN */\r
+#define _RTC_IEN_MASK 0x00000007UL /**< Mask for RTC_IEN */\r
+#define RTC_IEN_OF (1 << 0) /**< Overflow Interrupt Enable */\r
+#define _RTC_IEN_OF_SHIFT 0 /**< Shift value for RTC_OF */\r
+#define _RTC_IEN_OF_MASK 0x1UL /**< Bit mask for RTC_OF */\r
+#define RTC_IEN_OF_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_IEN */\r
+#define _RTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */\r
+#define RTC_IEN_COMP0 (1 << 1) /**< Compare Match 0 Interrupt Enable */\r
+#define _RTC_IEN_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */\r
+#define _RTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */\r
+#define RTC_IEN_COMP0_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for RTC_IEN */\r
+#define _RTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */\r
+#define RTC_IEN_COMP1 (1 << 2) /**< Compare Match 1 Interrupt Enable */\r
+#define _RTC_IEN_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */\r
+#define _RTC_IEN_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */\r
+#define RTC_IEN_COMP1_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for RTC_IEN */\r
+#define _RTC_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */\r
+\r
+/** Bit fields for RTC FREEZE */\r
+#define _RTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for RTC_FREEZE */\r
+#define _RTC_FREEZE_MASK 0x00000001UL /**< Mask for RTC_FREEZE */\r
+#define RTC_FREEZE_REGFREEZE (1 << 0) /**< Register Update Freeze */\r
+#define _RTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for RTC_REGFREEZE */\r
+#define _RTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for RTC_REGFREEZE */\r
+#define RTC_FREEZE_REGFREEZE_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_FREEZE */\r
+#define RTC_FREEZE_REGFREEZE_UPDATE (0x00000000UL << 0) /**< Shifted mode UPDATE for RTC_FREEZE */\r
+#define RTC_FREEZE_REGFREEZE_FREEZE (0x00000001UL << 0) /**< Shifted mode FREEZE for RTC_FREEZE */\r
+#define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_FREEZE */\r
+#define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for RTC_FREEZE */\r
+#define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for RTC_FREEZE */\r
+\r
+/** Bit fields for RTC SYNCBUSY */\r
+#define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTC_SYNCBUSY */\r
+#define _RTC_SYNCBUSY_MASK 0x00000007UL /**< Mask for RTC_SYNCBUSY */\r
+#define RTC_SYNCBUSY_CTRL (1 << 0) /**< RTC_CTRL Register Busy */\r
+#define _RTC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for RTC_CTRL */\r
+#define _RTC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for RTC_CTRL */\r
+#define RTC_SYNCBUSY_CTRL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */\r
+#define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */\r
+#define RTC_SYNCBUSY_COMP0 (1 << 1) /**< RTC_COMP0 Register Busy */\r
+#define _RTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */\r
+#define _RTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */\r
+#define RTC_SYNCBUSY_COMP0_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */\r
+#define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */\r
+#define RTC_SYNCBUSY_COMP1 (1 << 2) /**< RTC_COMP1 Register Busy */\r
+#define _RTC_SYNCBUSY_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */\r
+#define _RTC_SYNCBUSY_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */\r
+#define RTC_SYNCBUSY_COMP1_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */\r
+#define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_WDOG\r
+ * @{\r
+ */\r
+\r
+/** Bit fields for WDOG CTRL */\r
+#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */\r
+#define _WDOG_CTRL_MASK 0x00003F7FUL /**< Mask for WDOG_CTRL */\r
+#define WDOG_CTRL_EN (1 << 0) /**< Watchdog Timer Enable */\r
+#define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */\r
+#define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */\r
+#define WDOG_CTRL_EN_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_DEBUGRUN (1 << 1) /**< Debug Mode Run Enable */\r
+#define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */\r
+#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */\r
+#define WDOG_CTRL_DEBUGRUN_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_EM2RUN (1 << 2) /**< Energy Mode 2 Run Enable */\r
+#define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */\r
+#define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */\r
+#define WDOG_CTRL_EM2RUN_DEFAULT (0x00000000UL << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_EM3RUN (1 << 3) /**< Energy Mode 3 Run Enable */\r
+#define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */\r
+#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */\r
+#define WDOG_CTRL_EM3RUN_DEFAULT (0x00000000UL << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_LOCK (1 << 4) /**< Configuration lock */\r
+#define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */\r
+#define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */\r
+#define WDOG_CTRL_LOCK_DEFAULT (0x00000000UL << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_EM4BLOCK (1 << 5) /**< Energy Mode 4 Block */\r
+#define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */\r
+#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */\r
+#define WDOG_CTRL_EM4BLOCK_DEFAULT (0x00000000UL << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_SWOSCBLOCK (1 << 6) /**< Oscillator disabling by software block */\r
+#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */\r
+#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */\r
+#define WDOG_CTRL_SWOSCBLOCK_DEFAULT (0x00000000UL << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */\r
+#define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */\r
+#define WDOG_CTRL_PERSEL_DEFAULT (0x0000000FUL << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */\r
+#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */\r
+#define WDOG_CTRL_CLKSEL_DEFAULT (0x00000000UL << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */\r
+#define WDOG_CTRL_CLKSEL_1KHZ (0x00000000UL << 12) /**< Shifted mode 1KHZ for WDOG_CTRL */\r
+#define WDOG_CTRL_CLKSEL_LFRCO (0x00000001UL << 12) /**< Shifted mode LFRCO for WDOG_CTRL */\r
+#define WDOG_CTRL_CLKSEL_LFXO (0x00000002UL << 12) /**< Shifted mode LFXO for WDOG_CTRL */\r
+#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */\r
+#define _WDOG_CTRL_CLKSEL_1KHZ 0x00000000UL /**< Mode 1KHZ for WDOG_CTRL */\r
+#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */\r
+#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */\r
+\r
+/** Bit fields for WDOG CMD */\r
+#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */\r
+#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */\r
+#define WDOG_CMD_CLEAR (1 << 0) /**< Watchdog Timer Clear */\r
+#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */\r
+#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */\r
+#define WDOG_CMD_CLEAR_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for WDOG_CMD */\r
+#define WDOG_CMD_CLEAR_UNCHANGED (0x00000000UL << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */\r
+#define WDOG_CMD_CLEAR_CLEARED (0x00000001UL << 0) /**< Shifted mode CLEARED for WDOG_CMD */\r
+#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */\r
+#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */\r
+#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */\r
+\r
+/** Bit fields for WDOG SYNCBUSY */\r
+#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */\r
+#define _WDOG_SYNCBUSY_MASK 0x00000003UL /**< Mask for WDOG_SYNCBUSY */\r
+#define WDOG_SYNCBUSY_CTRL (1 << 0) /**< WDOG_CTRL Register Busy */\r
+#define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */\r
+#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */\r
+#define WDOG_SYNCBUSY_CTRL_DEFAULT (0x00000000UL << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */\r
+#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */\r
+#define WDOG_SYNCBUSY_CMD (1 << 1) /**< WDOG_CMD Register Busy */\r
+#define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */\r
+#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */\r
+#define WDOG_SYNCBUSY_CMD_DEFAULT (0x00000000UL << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */\r
+#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_DEVINFO\r
+ * @\{\r
+ */\r
+/** Bit fields for EFM32G890F128_DEVINFO */\r
+#define _DEVINFO_UNIQUEL_MASK (0xFFFFFFFFUL)\r
+#define _DEVINFO_UNIQUEL_SHIFT 0\r
+#define _DEVINFO_UNIQUEH_MASK (0xFFFFFFFFUL)\r
+#define _DEVINFO_UNIQUEH_SHIFT 0\r
+#define _DEVINFO_MSIZE_FLASH_MASK (0xFFFF0000UL)\r
+#define _DEVINFO_MSIZE_FLASH_SHIFT 16\r
+#define _DEVINFO_MSIZE_SRAM_MASK (0x0000FFFFUL)\r
+#define _DEVINFO_MSIZE_SRAM_SHIFT 0\r
+#define _DEVINFO_PART_DEVICE_FAMILY_MASK (0x00FF0000UL)\r
+#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16\r
+#define _DEVINFO_PART_DEVICE_NUMBER_MASK (0x0000FFFFUL)\r
+#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0\r
+\r
+/**\r
+ * @\}\r
+ */\r
+\r
+/**\r
+ * @addtogroup EFM32G890F128_CALIB\r
+ * @\{\r
+ */\r
+\r
+/** Bit fields for Calibration Special Registers */\r
+#define _HFRCO_CALIBH_28MHZ_MASK (0x000000FFUL)\r
+#define _HFRCO_CALIBH_28MHZ_SHIFT 0\r
+#define _HFRCO_CALIBL_21MHZ_MASK (0xFF000000UL)\r
+#define _HFRCO_CALIBL_21MHZ_SHIFT 24\r
+#define _HFRCO_CALIBL_11MHZ_MASK (0x00FF0000UL)\r
+#define _HFRCO_CALIBL_11MHZ_SHIFT 16\r
+#define _HFRCO_CALIBL_7MHZ_MASK (0x0000FF00UL)\r
+#define _HFRCO_CALIBL_7MHZ_SHIFT 8\r
+#define _HFRCO_CALIBL_1MHZ_MASK (0x000000FFUL)\r
+#define _HFRCO_CALIBL_1MHZ_SHIFT 0\r
+#define _ADC_CALIB_TEMP_MASK (0xFF000000UL)\r
+#define _ADC_CALIB_TEMP_SHIFT 24\r
+#define _ADC_CALIB_TUNING_MASK (0x00FFFFFFUL)\r
+#define _ADC_CALIB_TUNING_SHIFT 0\r
+\r
+/**\r
+ * @\}\r
+ */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * Unlock codes\r
+ *\r
+ *****************************************************************************/\r
+/** @addtogroup EFM32G890F128_MSC\r
+ * @{\r
+ */\r
+#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
+/**\r
+ * @}\r
+ *//** @addtogroup EFM32G890F128_EMU\r
+ * @{\r
+ */\r
+#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
+/**\r
+ * @}\r
+ *//** @addtogroup EFM32G890F128_CMU\r
+ * @{\r
+ */\r
+#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
+/**\r
+ * @}\r
+ *//** @addtogroup EFM32G890F128_GPIO\r
+ * @{\r
+ */\r
+#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
+/**\r
+ * @}\r
+ *//** @addtogroup EFM32G890F128_TIMER\r
+ * @{\r
+ */\r
+#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**************************************************************************//**\r
+ *\r
+ * @defgroup EFM32G890F128_Alternate_Function EFM32G890F128 Alternate Function\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32G890F128_AF_Channels EFM32G890F128 AF Channels\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/** AF channels connect the different on-chip peripherals with the af-mux */\r
+#define AFCHAN_MAX 79\r
+#define AFCHANLOC_MAX 4\r
+/** Analog AF channels */\r
+#define AFACHAN_MAX 37\r
+\r
+/** Peripheral Alternate Function (AF) channels */\r
+#define AF_CMU_CLKOUT0 0\r
+#define AF_CMU_CLKOUT1 1\r
+#define AF_EBI_ADDRDAT00 2\r
+#define AF_EBI_ADDRDAT01 3\r
+#define AF_EBI_ADDRDAT02 4\r
+#define AF_EBI_ADDRDAT03 5\r
+#define AF_EBI_ADDRDAT04 6\r
+#define AF_EBI_ADDRDAT05 7\r
+#define AF_EBI_ADDRDAT06 8\r
+#define AF_EBI_ADDRDAT07 9\r
+#define AF_EBI_ADDRDAT08 10\r
+#define AF_EBI_ADDRDAT09 11\r
+#define AF_EBI_ADDRDAT10 12\r
+#define AF_EBI_ADDRDAT11 13\r
+#define AF_EBI_ADDRDAT12 14\r
+#define AF_EBI_ADDRDAT13 15\r
+#define AF_EBI_ADDRDAT14 16\r
+#define AF_EBI_ADDRDAT15 17\r
+#define AF_EBI_CS0 18\r
+#define AF_EBI_CS1 19\r
+#define AF_EBI_CS2 20\r
+#define AF_EBI_CS3 21\r
+#define AF_EBI_WEn 22\r
+#define AF_EBI_REn 23\r
+#define AF_EBI_ARDY 24\r
+#define AF_EBI_ALE 25\r
+#define AF_TIMER0_CC0 26\r
+#define AF_TIMER0_CC1 27\r
+#define AF_TIMER0_CC2 28\r
+#define AF_TIMER0_CCC0 29\r
+#define AF_TIMER0_CCC1 30\r
+#define AF_TIMER0_CCC2 31\r
+#define AF_TIMER1_CC0 32\r
+#define AF_TIMER1_CC1 33\r
+#define AF_TIMER1_CC2 34\r
+#define AF_TIMER1_CCC0 35\r
+#define AF_TIMER1_CCC1 36\r
+#define AF_TIMER1_CCC2 37\r
+#define AF_TIMER2_CC0 38\r
+#define AF_TIMER2_CC1 39\r
+#define AF_TIMER2_CC2 40\r
+#define AF_TIMER2_CCC0 41\r
+#define AF_TIMER2_CCC1 42\r
+#define AF_TIMER2_CCC2 43\r
+#define AF_USART0_TX 44\r
+#define AF_USART0_RX 45\r
+#define AF_USART0_CLK 46\r
+#define AF_USART0_CS 47\r
+#define AF_USART1_TX 48\r
+#define AF_USART1_RX 49\r
+#define AF_USART1_CLK 50\r
+#define AF_USART1_CS 51\r
+#define AF_USART2_TX 52\r
+#define AF_USART2_RX 53\r
+#define AF_USART2_CLK 54\r
+#define AF_USART2_CS 55\r
+#define AF_UART0_TX 56\r
+#define AF_UART0_RX 57\r
+#define AF_UART0_CLK 58\r
+#define AF_UART0_CS 59\r
+#define AF_LEUART0_TX 60\r
+#define AF_LEUART0_RX 61\r
+#define AF_LEUART1_TX 62\r
+#define AF_LEUART1_RX 63\r
+#define AF_LETIMER0_OUT0 64\r
+#define AF_LETIMER0_OUT1 65\r
+#define AF_PCNT0_S0IN 66\r
+#define AF_PCNT0_S1IN 67\r
+#define AF_PCNT1_S0IN 68\r
+#define AF_PCNT1_S1IN 69\r
+#define AF_PCNT2_S0IN 70\r
+#define AF_PCNT2_S1IN 71\r
+#define AF_I2C0_SDA 72\r
+#define AF_I2C0_SCL 73\r
+#define AF_ACMP0_OUT 74\r
+#define AF_ACMP1_OUT 75\r
+#define AF_DBG_SWV 76\r
+#define AF_DBG_SWDITMS 77\r
+#define AF_DBG_SWCLKTCK 78\r
+\r
+/** Analog AF channels */\r
+#define AFA_MSC_TM0 0\r
+#define AFA_MSC_TM1 1\r
+#define AFA_MSC_TM2 2\r
+#define AFA_ADC0_CH0 3\r
+#define AFA_ADC0_CH1 4\r
+#define AFA_ADC0_CH2 5\r
+#define AFA_ADC0_CH3 6\r
+#define AFA_ADC0_CH4 7\r
+#define AFA_ADC0_CH5 8\r
+#define AFA_ADC0_CH6 9\r
+#define AFA_ADC0_CH7 10\r
+#define AFA_ADC0_VCM 11\r
+#define AFA_DAC0_OUT0 12\r
+#define AFA_DAC0_OUT1 13\r
+#define AFA_ACMP0_CH0 14\r
+#define AFA_ACMP0_CH1 15\r
+#define AFA_ACMP0_CH2 16\r
+#define AFA_ACMP0_CH3 17\r
+#define AFA_ACMP0_CH4 18\r
+#define AFA_ACMP0_CH5 19\r
+#define AFA_ACMP0_CH6 20\r
+#define AFA_ACMP0_CH7 21\r
+#define AFA_ACMP1_CH0 22\r
+#define AFA_ACMP1_CH1 23\r
+#define AFA_ACMP1_CH2 24\r
+#define AFA_ACMP1_CH3 25\r
+#define AFA_ACMP1_CH4 26\r
+#define AFA_ACMP1_CH5 27\r
+#define AFA_ACMP1_CH6 28\r
+#define AFA_ACMP1_CH7 29\r
+#define AFA_LCD_BCAP_P 30\r
+#define AFA_LCD_BCAP_N 31\r
+#define AFA_LCD_BEXT 32\r
+#define AFA_HFXTAL_P 33\r
+#define AFA_HFXTAL_N 34\r
+#define AFA_LFXTAL_P 35\r
+#define AFA_LFXTAL_N 36\r
+\r
+/** Digital AF */\r
+#define AF_TIMER_CC0(i) (i == 0 ? AF_TIMER0_CC0 : i == 1 ? AF_TIMER1_CC0 : i == 2 ? AF_TIMER2_CC0 : -1)\r
+#define AF_UART_CLK(i) (i == 0 ? AF_UART0_CLK : -1)\r
+#define AF_I2C_SDA(i) (i == 0 ? AF_I2C0_SDA : -1)\r
+#define AF_TIMER_CC1(i) (i == 0 ? AF_TIMER0_CC1 : i == 1 ? AF_TIMER1_CC1 : i == 2 ? AF_TIMER2_CC1 : -1)\r
+#define AF_USART_CS(i) (i == 0 ? AF_USART0_CS : i == 1 ? AF_USART1_CS : i == 2 ? AF_USART2_CS : -1)\r
+#define AF_I2C_SCL(i) (i == 0 ? AF_I2C0_SCL : -1)\r
+#define AF_TIMER_CC2(i) (i == 0 ? AF_TIMER0_CC2 : i == 1 ? AF_TIMER1_CC2 : i == 2 ? AF_TIMER2_CC2 : -1)\r
+#define AF_USART_CLK(i) (i == 0 ? AF_USART0_CLK : i == 1 ? AF_USART1_CLK : i == 2 ? AF_USART2_CLK : -1)\r
+#define AF_UART_RX(i) (i == 0 ? AF_UART0_RX : -1)\r
+#define AF_UART_TX(i) (i == 0 ? AF_UART0_TX : -1)\r
+#define AF_LETIMER_OUT1(i) (i == 0 ? AF_LETIMER0_OUT1 : -1)\r
+#define AF_LEUART_RX(i) (i == 0 ? AF_LEUART0_RX : i == 1 ? AF_LEUART1_RX : -1)\r
+#define AF_TIMER_CCC0(i) (i == 0 ? AF_TIMER0_CCC0 : i == 1 ? AF_TIMER1_CCC0 : i == 2 ? AF_TIMER2_CCC0 : -1)\r
+#define AF_PCNT_S1IN(i) (i == 0 ? AF_PCNT0_S1IN : i == 1 ? AF_PCNT1_S1IN : i == 2 ? AF_PCNT2_S1IN : -1)\r
+#define AF_LEUART_TX(i) (i == 0 ? AF_LEUART0_TX : i == 1 ? AF_LEUART1_TX : -1)\r
+#define AF_TIMER_CCC2(i) (i == 0 ? AF_TIMER0_CCC2 : i == 1 ? AF_TIMER1_CCC2 : i == 2 ? AF_TIMER2_CCC2 : -1)\r
+#define AF_TIMER_CCC1(i) (i == 0 ? AF_TIMER0_CCC1 : i == 1 ? AF_TIMER1_CCC1 : i == 2 ? AF_TIMER2_CCC1 : -1)\r
+#define AF_USART_TX(i) (i == 0 ? AF_USART0_TX : i == 1 ? AF_USART1_TX : i == 2 ? AF_USART2_TX : -1)\r
+#define AF_LETIMER_OUT0(i) (i == 0 ? AF_LETIMER0_OUT0 : -1)\r
+#define AF_ACMP_OUT(i) (i == 0 ? AF_ACMP0_OUT : i == 1 ? AF_ACMP1_OUT : -1)\r
+#define AF_USART_RX(i) (i == 0 ? AF_USART0_RX : i == 1 ? AF_USART1_RX : i == 2 ? AF_USART2_RX : -1)\r
+#define AF_UART_CS(i) (i == 0 ? AF_UART0_CS : -1)\r
+#define AF_PCNT_S0IN(i) (i == 0 ? AF_PCNT0_S0IN : i == 1 ? AF_PCNT1_S0IN : i == 2 ? AF_PCNT2_S0IN : -1)\r
+#define AFA_DAC_OUT1(i) (i == 0 ? AFA_DAC0_OUT1 : -1)\r
+#define AFA_DAC_OUT0(i) (i == 0 ? AFA_DAC0_OUT0 : -1)\r
+#define AFA_ADC_CH7(i) (i == 0 ? AFA_ADC0_CH7 : -1)\r
+#define AFA_ADC_VCM(i) (i == 0 ? AFA_ADC0_VCM : -1)\r
+#define AFA_ACMP_CH1(i) (i == 0 ? AFA_ACMP0_CH1 : i == 1 ? AFA_ACMP1_CH1 : -1)\r
+#define AFA_ADC_CH0(i) (i == 0 ? AFA_ADC0_CH0 : -1)\r
+#define AFA_ACMP_CH0(i) (i == 0 ? AFA_ACMP0_CH0 : i == 1 ? AFA_ACMP1_CH0 : -1)\r
+#define AFA_ACMP_CH3(i) (i == 0 ? AFA_ACMP0_CH3 : i == 1 ? AFA_ACMP1_CH3 : -1)\r
+#define AFA_ADC_CH1(i) (i == 0 ? AFA_ADC0_CH1 : -1)\r
+#define AFA_ACMP_CH2(i) (i == 0 ? AFA_ACMP0_CH2 : i == 1 ? AFA_ACMP1_CH2 : -1)\r
+#define AFA_ADC_CH2(i) (i == 0 ? AFA_ADC0_CH2 : -1)\r
+#define AFA_ADC_CH3(i) (i == 0 ? AFA_ADC0_CH3 : -1)\r
+#define AFA_ADC_CH4(i) (i == 0 ? AFA_ADC0_CH4 : -1)\r
+#define AFA_ADC_CH5(i) (i == 0 ? AFA_ADC0_CH5 : -1)\r
+#define AFA_ADC_CH6(i) (i == 0 ? AFA_ADC0_CH6 : -1)\r
+#define AFA_ACMP_CH5(i) (i == 0 ? AFA_ACMP0_CH5 : i == 1 ? AFA_ACMP1_CH5 : -1)\r
+#define AFA_ACMP_CH4(i) (i == 0 ? AFA_ACMP0_CH4 : i == 1 ? AFA_ACMP1_CH4 : -1)\r
+#define AFA_ACMP_CH7(i) (i == 0 ? AFA_ACMP0_CH7 : i == 1 ? AFA_ACMP1_CH7 : -1)\r
+#define AFA_ACMP_CH6(i) (i == 0 ? AFA_ACMP0_CH6 : i == 1 ? AFA_ACMP1_CH6 : -1)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32G890F128_AF_Ports EFM32G890F128 AF Ports\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/** AF port for function f */\r
+#define AF_CMU_CLKOUT0_PORT(f) (f == 0 ? 0 : f == 1 ? 2 : -1)\r
+#define AF_CMU_CLKOUT1_PORT(f) (f == 0 ? 0 : f == 1 ? 3 : -1)\r
+#define AF_EBI_ADDRDAT00_PORT(f) (f == 0 ? 4 : -1)\r
+#define AF_EBI_ADDRDAT01_PORT(f) (f == 0 ? 4 : -1)\r
+#define AF_EBI_ADDRDAT02_PORT(f) (f == 0 ? 4 : -1)\r
+#define AF_EBI_ADDRDAT03_PORT(f) (f == 0 ? 4 : -1)\r
+#define AF_EBI_ADDRDAT04_PORT(f) (f == 0 ? 4 : -1)\r
+#define AF_EBI_ADDRDAT05_PORT(f) (f == 0 ? 4 : -1)\r
+#define AF_EBI_ADDRDAT06_PORT(f) (f == 0 ? 4 : -1)\r
+#define AF_EBI_ADDRDAT07_PORT(f) (f == 0 ? 4 : -1)\r
+#define AF_EBI_ADDRDAT08_PORT(f) (f == 0 ? 0 : -1)\r
+#define AF_EBI_ADDRDAT09_PORT(f) (f == 0 ? 0 : -1)\r
+#define AF_EBI_ADDRDAT10_PORT(f) (f == 0 ? 0 : -1)\r
+#define AF_EBI_ADDRDAT11_PORT(f) (f == 0 ? 0 : -1)\r
+#define AF_EBI_ADDRDAT12_PORT(f) (f == 0 ? 0 : -1)\r
+#define AF_EBI_ADDRDAT13_PORT(f) (f == 0 ? 0 : -1)\r
+#define AF_EBI_ADDRDAT14_PORT(f) (f == 0 ? 0 : -1)\r
+#define AF_EBI_ADDRDAT15_PORT(f) (f == 0 ? 0 : -1)\r
+#define AF_EBI_CS0_PORT(f) (f == 0 ? 3 : -1)\r
+#define AF_EBI_CS1_PORT(f) (f == 0 ? 3 : -1)\r
+#define AF_EBI_CS2_PORT(f) (f == 0 ? 3 : -1)\r
+#define AF_EBI_CS3_PORT(f) (f == 0 ? 3 : -1)\r
+#define AF_EBI_WEn_PORT(f) (f == 0 ? 5 : -1)\r
+#define AF_EBI_REn_PORT(f) (f == 0 ? 5 : -1)\r
+#define AF_EBI_ARDY_PORT(f) (f == 0 ? 5 : -1)\r
+#define AF_EBI_ALE_PORT(f) (f == 0 ? 5 : -1)\r
+#define AF_TIMER0_CC0_PORT(f) (f == 0 ? 0 : f == 1 ? 0 : f == 2 ? 5 : f == 3 ? 3 : -1)\r
+#define AF_TIMER0_CC1_PORT(f) (f == 0 ? 0 : f == 1 ? 0 : f == 2 ? 5 : f == 3 ? 3 : -1)\r
+#define AF_TIMER0_CC2_PORT(f) (f == 0 ? 0 : f == 1 ? 0 : f == 2 ? 5 : f == 3 ? 3 : -1)\r
+#define AF_TIMER0_CCC0_PORT(f) (f == 0 ? 0 : f == 1 ? 2 : f == 2 ? 5 : f == 3 ? 2 : -1)\r
+#define AF_TIMER0_CCC1_PORT(f) (f == 0 ? 0 : f == 1 ? 2 : f == 2 ? 5 : f == 3 ? 2 : -1)\r
+#define AF_TIMER0_CCC2_PORT(f) (f == 0 ? 0 : f == 1 ? 2 : f == 2 ? 5 : f == 3 ? 2 : -1)\r
+#define AF_TIMER1_CC0_PORT(f) (f == 0 ? 2 : f == 1 ? 4 : f == 2 ? 1 : -1)\r
+#define AF_TIMER1_CC1_PORT(f) (f == 0 ? 2 : f == 1 ? 4 : f == 2 ? 1 : -1)\r
+#define AF_TIMER1_CC2_PORT(f) (f == 0 ? 2 : f == 1 ? 4 : f == 2 ? 1 : -1)\r
+#define AF_TIMER1_CCC0_PORT(f) (-1)\r
+#define AF_TIMER1_CCC1_PORT(f) (-1)\r
+#define AF_TIMER1_CCC2_PORT(f) (-1)\r
+#define AF_TIMER2_CC0_PORT(f) (f == 0 ? 0 : f == 1 ? 0 : f == 2 ? 2 : -1)\r
+#define AF_TIMER2_CC1_PORT(f) (f == 0 ? 0 : f == 1 ? 0 : f == 2 ? 2 : -1)\r
+#define AF_TIMER2_CC2_PORT(f) (f == 0 ? 0 : f == 1 ? 0 : f == 2 ? 2 : -1)\r
+#define AF_TIMER2_CCC0_PORT(f) (-1)\r
+#define AF_TIMER2_CCC1_PORT(f) (-1)\r
+#define AF_TIMER2_CCC2_PORT(f) (-1)\r
+#define AF_USART0_TX_PORT(f) (f == 0 ? 4 : f == 1 ? 4 : f == 2 ? 2 : -1)\r
+#define AF_USART0_RX_PORT(f) (f == 0 ? 4 : f == 1 ? 4 : f == 2 ? 2 : -1)\r
+#define AF_USART0_CLK_PORT(f) (f == 0 ? 4 : f == 1 ? 4 : f == 2 ? 2 : -1)\r
+#define AF_USART0_CS_PORT(f) (f == 0 ? 4 : f == 1 ? 4 : f == 2 ? 2 : -1)\r
+#define AF_USART1_TX_PORT(f) (f == 0 ? 2 : f == 1 ? 3 : -1)\r
+#define AF_USART1_RX_PORT(f) (f == 0 ? 2 : f == 1 ? 3 : -1)\r
+#define AF_USART1_CLK_PORT(f) (f == 0 ? 1 : f == 1 ? 3 : -1)\r
+#define AF_USART1_CS_PORT(f) (f == 0 ? 1 : f == 1 ? 3 : -1)\r
+#define AF_USART2_TX_PORT(f) (f == 0 ? 2 : f == 1 ? 1 : -1)\r
+#define AF_USART2_RX_PORT(f) (f == 0 ? 2 : f == 1 ? 1 : -1)\r
+#define AF_USART2_CLK_PORT(f) (f == 0 ? 2 : f == 1 ? 1 : -1)\r
+#define AF_USART2_CS_PORT(f) (f == 0 ? 2 : f == 1 ? 1 : -1)\r
+#define AF_UART0_TX_PORT(f) (f == 0 ? 5 : f == 1 ? 4 : f == 2 ? 0 : f == 3 ? 2 : -1)\r
+#define AF_UART0_RX_PORT(f) (f == 0 ? 5 : f == 1 ? 4 : f == 2 ? 0 : f == 3 ? 2 : -1)\r
+#define AF_UART0_CLK_PORT(f) (-1)\r
+#define AF_UART0_CS_PORT(f) (-1)\r
+#define AF_LEUART0_TX_PORT(f) (f == 0 ? 3 : f == 1 ? 1 : f == 2 ? 4 : -1)\r
+#define AF_LEUART0_RX_PORT(f) (f == 0 ? 3 : f == 1 ? 1 : f == 2 ? 4 : -1)\r
+#define AF_LEUART1_TX_PORT(f) (f == 0 ? 2 : f == 1 ? 0 : -1)\r
+#define AF_LEUART1_RX_PORT(f) (f == 0 ? 2 : f == 1 ? 0 : -1)\r
+#define AF_LETIMER0_OUT0_PORT(f) (f == 0 ? 3 : f == 1 ? 1 : f == 2 ? 5 : f == 3 ? 2 : -1)\r
+#define AF_LETIMER0_OUT1_PORT(f) (f == 0 ? 3 : f == 1 ? 1 : f == 2 ? 5 : f == 3 ? 2 : -1)\r
+#define AF_PCNT0_S0IN_PORT(f) (f == 0 ? 2 : f == 1 ? 4 : f == 2 ? 2 : -1)\r
+#define AF_PCNT0_S1IN_PORT(f) (f == 0 ? 2 : f == 1 ? 4 : f == 2 ? 2 : -1)\r
+#define AF_PCNT1_S0IN_PORT(f) (f == 0 ? 2 : f == 1 ? 1 : -1)\r
+#define AF_PCNT1_S1IN_PORT(f) (f == 0 ? 2 : f == 1 ? 1 : -1)\r
+#define AF_PCNT2_S0IN_PORT(f) (f == 0 ? 3 : f == 1 ? 4 : -1)\r
+#define AF_PCNT2_S1IN_PORT(f) (f == 0 ? 3 : f == 1 ? 4 : -1)\r
+#define AF_I2C0_SDA_PORT(f) (f == 0 ? 0 : f == 1 ? 3 : f == 2 ? 2 : f == 3 ? 3 : -1)\r
+#define AF_I2C0_SCL_PORT(f) (f == 0 ? 0 : f == 1 ? 3 : f == 2 ? 2 : f == 3 ? 3 : -1)\r
+#define AF_ACMP0_OUT_PORT(f) (f == 0 ? 4 : f == 1 ? 4 : -1)\r
+#define AF_ACMP1_OUT_PORT(f) (f == 0 ? 5 : f == 1 ? 4 : -1)\r
+#define AF_DBG_SWV_PORT(f) (f == 0 ? 5 : f == 1 ? 2 : -1)\r
+#define AF_DBG_SWDITMS_PORT(f) (f == 0 ? 5 : f == 1 ? 5 : -1)\r
+#define AF_DBG_SWCLKTCK_PORT(f) (f == 0 ? 5 : f == 1 ? 5 : -1)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**************************************************************************//**\r
+ * @defgroup EFM32G890F128_AF_Pins EFM32G890F128 AF Pins\r
+ * @{\r
+ *****************************************************************************/\r
+\r
+/** AF pin for function f */\r
+#define AF_CMU_CLKOUT0_PIN(f) (f == 0 ? 2 : f == 1 ? 12 : -1)\r
+#define AF_CMU_CLKOUT1_PIN(f) (f == 0 ? 1 : f == 1 ? 8 : -1)\r
+#define AF_EBI_ADDRDAT00_PIN(f) (f == 0 ? 8 : -1)\r
+#define AF_EBI_ADDRDAT01_PIN(f) (f == 0 ? 9 : -1)\r
+#define AF_EBI_ADDRDAT02_PIN(f) (f == 0 ? 10 : -1)\r
+#define AF_EBI_ADDRDAT03_PIN(f) (f == 0 ? 11 : -1)\r
+#define AF_EBI_ADDRDAT04_PIN(f) (f == 0 ? 12 : -1)\r
+#define AF_EBI_ADDRDAT05_PIN(f) (f == 0 ? 13 : -1)\r
+#define AF_EBI_ADDRDAT06_PIN(f) (f == 0 ? 14 : -1)\r
+#define AF_EBI_ADDRDAT07_PIN(f) (f == 0 ? 15 : -1)\r
+#define AF_EBI_ADDRDAT08_PIN(f) (f == 0 ? 15 : -1)\r
+#define AF_EBI_ADDRDAT09_PIN(f) (f == 0 ? 0 : -1)\r
+#define AF_EBI_ADDRDAT10_PIN(f) (f == 0 ? 1 : -1)\r
+#define AF_EBI_ADDRDAT11_PIN(f) (f == 0 ? 2 : -1)\r
+#define AF_EBI_ADDRDAT12_PIN(f) (f == 0 ? 3 : -1)\r
+#define AF_EBI_ADDRDAT13_PIN(f) (f == 0 ? 4 : -1)\r
+#define AF_EBI_ADDRDAT14_PIN(f) (f == 0 ? 5 : -1)\r
+#define AF_EBI_ADDRDAT15_PIN(f) (f == 0 ? 6 : -1)\r
+#define AF_EBI_CS0_PIN(f) (f == 0 ? 9 : -1)\r
+#define AF_EBI_CS1_PIN(f) (f == 0 ? 10 : -1)\r
+#define AF_EBI_CS2_PIN(f) (f == 0 ? 11 : -1)\r
+#define AF_EBI_CS3_PIN(f) (f == 0 ? 12 : -1)\r
+#define AF_EBI_WEn_PIN(f) (f == 0 ? 4 : -1)\r
+#define AF_EBI_REn_PIN(f) (f == 0 ? 5 : -1)\r
+#define AF_EBI_ARDY_PIN(f) (f == 0 ? 2 : -1)\r
+#define AF_EBI_ALE_PIN(f) (f == 0 ? 3 : -1)\r
+#define AF_TIMER0_CC0_PIN(f) (f == 0 ? 0 : f == 1 ? 0 : f == 2 ? 6 : f == 3 ? 1 : -1)\r
+#define AF_TIMER0_CC1_PIN(f) (f == 0 ? 1 : f == 1 ? 1 : f == 2 ? 7 : f == 3 ? 2 : -1)\r
+#define AF_TIMER0_CC2_PIN(f) (f == 0 ? 2 : f == 1 ? 2 : f == 2 ? 8 : f == 3 ? 3 : -1)\r
+#define AF_TIMER0_CCC0_PIN(f) (f == 0 ? 3 : f == 1 ? 13 : f == 2 ? 3 : f == 3 ? 13 : -1)\r
+#define AF_TIMER0_CCC1_PIN(f) (f == 0 ? 4 : f == 1 ? 14 : f == 2 ? 4 : f == 3 ? 14 : -1)\r
+#define AF_TIMER0_CCC2_PIN(f) (f == 0 ? 5 : f == 1 ? 15 : f == 2 ? 5 : f == 3 ? 15 : -1)\r
+#define AF_TIMER1_CC0_PIN(f) (f == 0 ? 13 : f == 1 ? 10 : f == 2 ? 0 : -1)\r
+#define AF_TIMER1_CC1_PIN(f) (f == 0 ? 14 : f == 1 ? 11 : f == 2 ? 1 : -1)\r
+#define AF_TIMER1_CC2_PIN(f) (f == 0 ? 15 : f == 1 ? 12 : f == 2 ? 2 : -1)\r
+#define AF_TIMER1_CCC0_PIN(f) (-1)\r
+#define AF_TIMER1_CCC1_PIN(f) (-1)\r
+#define AF_TIMER1_CCC2_PIN(f) (-1)\r
+#define AF_TIMER2_CC0_PIN(f) (f == 0 ? 8 : f == 1 ? 12 : f == 2 ? 8 : -1)\r
+#define AF_TIMER2_CC1_PIN(f) (f == 0 ? 9 : f == 1 ? 13 : f == 2 ? 9 : -1)\r
+#define AF_TIMER2_CC2_PIN(f) (f == 0 ? 10 : f == 1 ? 14 : f == 2 ? 10 : -1)\r
+#define AF_TIMER2_CCC0_PIN(f) (-1)\r
+#define AF_TIMER2_CCC1_PIN(f) (-1)\r
+#define AF_TIMER2_CCC2_PIN(f) (-1)\r
+#define AF_USART0_TX_PIN(f) (f == 0 ? 10 : f == 1 ? 7 : f == 2 ? 11 : -1)\r
+#define AF_USART0_RX_PIN(f) (f == 0 ? 11 : f == 1 ? 6 : f == 2 ? 10 : -1)\r
+#define AF_USART0_CLK_PIN(f) (f == 0 ? 12 : f == 1 ? 5 : f == 2 ? 9 : -1)\r
+#define AF_USART0_CS_PIN(f) (f == 0 ? 13 : f == 1 ? 4 : f == 2 ? 8 : -1)\r
+#define AF_USART1_TX_PIN(f) (f == 0 ? 0 : f == 1 ? 0 : -1)\r
+#define AF_USART1_RX_PIN(f) (f == 0 ? 1 : f == 1 ? 1 : -1)\r
+#define AF_USART1_CLK_PIN(f) (f == 0 ? 7 : f == 1 ? 2 : -1)\r
+#define AF_USART1_CS_PIN(f) (f == 0 ? 8 : f == 1 ? 3 : -1)\r
+#define AF_USART2_TX_PIN(f) (f == 0 ? 2 : f == 1 ? 3 : -1)\r
+#define AF_USART2_RX_PIN(f) (f == 0 ? 3 : f == 1 ? 4 : -1)\r
+#define AF_USART2_CLK_PIN(f) (f == 0 ? 4 : f == 1 ? 5 : -1)\r
+#define AF_USART2_CS_PIN(f) (f == 0 ? 5 : f == 1 ? 6 : -1)\r
+#define AF_UART0_TX_PIN(f) (f == 0 ? 6 : f == 1 ? 0 : f == 2 ? 3 : f == 3 ? 14 : -1)\r
+#define AF_UART0_RX_PIN(f) (f == 0 ? 7 : f == 1 ? 1 : f == 2 ? 4 : f == 3 ? 15 : -1)\r
+#define AF_UART0_CLK_PIN(f) (-1)\r
+#define AF_UART0_CS_PIN(f) (-1)\r
+#define AF_LEUART0_TX_PIN(f) (f == 0 ? 4 : f == 1 ? 13 : f == 2 ? 14 : -1)\r
+#define AF_LEUART0_RX_PIN(f) (f == 0 ? 5 : f == 1 ? 14 : f == 2 ? 15 : -1)\r
+#define AF_LEUART1_TX_PIN(f) (f == 0 ? 6 : f == 1 ? 5 : -1)\r
+#define AF_LEUART1_RX_PIN(f) (f == 0 ? 7 : f == 1 ? 6 : -1)\r
+#define AF_LETIMER0_OUT0_PIN(f) (f == 0 ? 6 : f == 1 ? 11 : f == 2 ? 0 : f == 3 ? 4 : -1)\r
+#define AF_LETIMER0_OUT1_PIN(f) (f == 0 ? 7 : f == 1 ? 12 : f == 2 ? 1 : f == 3 ? 5 : -1)\r
+#define AF_PCNT0_S0IN_PIN(f) (f == 0 ? 13 : f == 1 ? 0 : f == 2 ? 0 : -1)\r
+#define AF_PCNT0_S1IN_PIN(f) (f == 0 ? 14 : f == 1 ? 1 : f == 2 ? 1 : -1)\r
+#define AF_PCNT1_S0IN_PIN(f) (f == 0 ? 4 : f == 1 ? 3 : -1)\r
+#define AF_PCNT1_S1IN_PIN(f) (f == 0 ? 5 : f == 1 ? 4 : -1)\r
+#define AF_PCNT2_S0IN_PIN(f) (f == 0 ? 0 : f == 1 ? 8 : -1)\r
+#define AF_PCNT2_S1IN_PIN(f) (f == 0 ? 1 : f == 1 ? 9 : -1)\r
+#define AF_I2C0_SDA_PIN(f) (f == 0 ? 0 : f == 1 ? 6 : f == 2 ? 6 : f == 3 ? 14 : -1)\r
+#define AF_I2C0_SCL_PIN(f) (f == 0 ? 1 : f == 1 ? 7 : f == 2 ? 7 : f == 3 ? 15 : -1)\r
+#define AF_ACMP0_OUT_PIN(f) (f == 0 ? 13 : f == 1 ? 2 : -1)\r
+#define AF_ACMP1_OUT_PIN(f) (f == 0 ? 2 : f == 1 ? 3 : -1)\r
+#define AF_DBG_SWV_PIN(f) (f == 0 ? 2 : f == 1 ? 15 : -1)\r
+#define AF_DBG_SWDITMS_PIN(f) (f == 0 ? 1 : f == 1 ? 1 : -1)\r
+#define AF_DBG_SWCLKTCK_PIN(f) (f == 0 ? 0 : f == 1 ? 0 : -1)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** Grouped by channel c, function f */\r
+#define AF_PORT(c, f) ( \\r
+ c == 0 ? AF_CMU_CLKOUT0_PORT(f) : \\r
+ c == 1 ? AF_CMU_CLKOUT1_PORT(f) : \\r
+ c == 2 ? AF_EBI_ADDRDAT00_PORT(f) : \\r
+ c == 3 ? AF_EBI_ADDRDAT01_PORT(f) : \\r
+ c == 4 ? AF_EBI_ADDRDAT02_PORT(f) : \\r
+ c == 5 ? AF_EBI_ADDRDAT03_PORT(f) : \\r
+ c == 6 ? AF_EBI_ADDRDAT04_PORT(f) : \\r
+ c == 7 ? AF_EBI_ADDRDAT05_PORT(f) : \\r
+ c == 8 ? AF_EBI_ADDRDAT06_PORT(f) : \\r
+ c == 9 ? AF_EBI_ADDRDAT07_PORT(f) : \\r
+ c == 10 ? AF_EBI_ADDRDAT08_PORT(f) : \\r
+ c == 11 ? AF_EBI_ADDRDAT09_PORT(f) : \\r
+ c == 12 ? AF_EBI_ADDRDAT10_PORT(f) : \\r
+ c == 13 ? AF_EBI_ADDRDAT11_PORT(f) : \\r
+ c == 14 ? AF_EBI_ADDRDAT12_PORT(f) : \\r
+ c == 15 ? AF_EBI_ADDRDAT13_PORT(f) : \\r
+ c == 16 ? AF_EBI_ADDRDAT14_PORT(f) : \\r
+ c == 17 ? AF_EBI_ADDRDAT15_PORT(f) : \\r
+ c == 18 ? AF_EBI_CS0_PORT(f) : \\r
+ c == 19 ? AF_EBI_CS1_PORT(f) : \\r
+ c == 20 ? AF_EBI_CS2_PORT(f) : \\r
+ c == 21 ? AF_EBI_CS3_PORT(f) : \\r
+ c == 22 ? AF_EBI_WEn_PORT(f) : \\r
+ c == 23 ? AF_EBI_REn_PORT(f) : \\r
+ c == 24 ? AF_EBI_ARDY_PORT(f) : \\r
+ c == 25 ? AF_EBI_ALE_PORT(f) : \\r
+ c == 26 ? AF_TIMER0_CC0_PORT(f) : \\r
+ c == 27 ? AF_TIMER0_CC1_PORT(f) : \\r
+ c == 28 ? AF_TIMER0_CC2_PORT(f) : \\r
+ c == 29 ? AF_TIMER0_CCC0_PORT(f) : \\r
+ c == 30 ? AF_TIMER0_CCC1_PORT(f) : \\r
+ c == 31 ? AF_TIMER0_CCC2_PORT(f) : \\r
+ c == 32 ? AF_TIMER1_CC0_PORT(f) : \\r
+ c == 33 ? AF_TIMER1_CC1_PORT(f) : \\r
+ c == 34 ? AF_TIMER1_CC2_PORT(f) : \\r
+ c == 35 ? AF_TIMER1_CCC0_PORT(f) : \\r
+ c == 36 ? AF_TIMER1_CCC1_PORT(f) : \\r
+ c == 37 ? AF_TIMER1_CCC2_PORT(f) : \\r
+ c == 38 ? AF_TIMER2_CC0_PORT(f) : \\r
+ c == 39 ? AF_TIMER2_CC1_PORT(f) : \\r
+ c == 40 ? AF_TIMER2_CC2_PORT(f) : \\r
+ c == 41 ? AF_TIMER2_CCC0_PORT(f) : \\r
+ c == 42 ? AF_TIMER2_CCC1_PORT(f) : \\r
+ c == 43 ? AF_TIMER2_CCC2_PORT(f) : \\r
+ c == 44 ? AF_USART0_TX_PORT(f) : \\r
+ c == 45 ? AF_USART0_RX_PORT(f) : \\r
+ c == 46 ? AF_USART0_CLK_PORT(f) : \\r
+ c == 47 ? AF_USART0_CS_PORT(f) : \\r
+ c == 48 ? AF_USART1_TX_PORT(f) : \\r
+ c == 49 ? AF_USART1_RX_PORT(f) : \\r
+ c == 50 ? AF_USART1_CLK_PORT(f) : \\r
+ c == 51 ? AF_USART1_CS_PORT(f) : \\r
+ c == 52 ? AF_USART2_TX_PORT(f) : \\r
+ c == 53 ? AF_USART2_RX_PORT(f) : \\r
+ c == 54 ? AF_USART2_CLK_PORT(f) : \\r
+ c == 55 ? AF_USART2_CS_PORT(f) : \\r
+ c == 56 ? AF_UART0_TX_PORT(f) : \\r
+ c == 57 ? AF_UART0_RX_PORT(f) : \\r
+ c == 58 ? AF_UART0_CLK_PORT(f) : \\r
+ c == 59 ? AF_UART0_CS_PORT(f) : \\r
+ c == 60 ? AF_LEUART0_TX_PORT(f) : \\r
+ c == 61 ? AF_LEUART0_RX_PORT(f) : \\r
+ c == 62 ? AF_LEUART1_TX_PORT(f) : \\r
+ c == 63 ? AF_LEUART1_RX_PORT(f) : \\r
+ c == 64 ? AF_LETIMER0_OUT0_PORT(f) : \\r
+ c == 65 ? AF_LETIMER0_OUT1_PORT(f) : \\r
+ c == 66 ? AF_PCNT0_S0IN_PORT(f) : \\r
+ c == 67 ? AF_PCNT0_S1IN_PORT(f) : \\r
+ c == 68 ? AF_PCNT1_S0IN_PORT(f) : \\r
+ c == 69 ? AF_PCNT1_S1IN_PORT(f) : \\r
+ c == 70 ? AF_PCNT2_S0IN_PORT(f) : \\r
+ c == 71 ? AF_PCNT2_S1IN_PORT(f) : \\r
+ c == 72 ? AF_I2C0_SDA_PORT(f) : \\r
+ c == 73 ? AF_I2C0_SCL_PORT(f) : \\r
+ c == 74 ? AF_ACMP0_OUT_PORT(f) : \\r
+ c == 75 ? AF_ACMP1_OUT_PORT(f) : \\r
+ c == 76 ? AF_DBG_SWV_PORT(f) : \\r
+ c == 77 ? AF_DBG_SWDITMS_PORT(f) : \\r
+ c == 78 ? AF_DBG_SWCLKTCK_PORT(f) : \\r
+ -1)\r
+\r
+#define AF_PIN(c, f) ( \\r
+ c == 0 ? AF_CMU_CLKOUT0_PIN(f) : \\r
+ c == 1 ? AF_CMU_CLKOUT1_PIN(f) : \\r
+ c == 2 ? AF_EBI_ADDRDAT00_PIN(f) : \\r
+ c == 3 ? AF_EBI_ADDRDAT01_PIN(f) : \\r
+ c == 4 ? AF_EBI_ADDRDAT02_PIN(f) : \\r
+ c == 5 ? AF_EBI_ADDRDAT03_PIN(f) : \\r
+ c == 6 ? AF_EBI_ADDRDAT04_PIN(f) : \\r
+ c == 7 ? AF_EBI_ADDRDAT05_PIN(f) : \\r
+ c == 8 ? AF_EBI_ADDRDAT06_PIN(f) : \\r
+ c == 9 ? AF_EBI_ADDRDAT07_PIN(f) : \\r
+ c == 10 ? AF_EBI_ADDRDAT08_PIN(f) : \\r
+ c == 11 ? AF_EBI_ADDRDAT09_PIN(f) : \\r
+ c == 12 ? AF_EBI_ADDRDAT10_PIN(f) : \\r
+ c == 13 ? AF_EBI_ADDRDAT11_PIN(f) : \\r
+ c == 14 ? AF_EBI_ADDRDAT12_PIN(f) : \\r
+ c == 15 ? AF_EBI_ADDRDAT13_PIN(f) : \\r
+ c == 16 ? AF_EBI_ADDRDAT14_PIN(f) : \\r
+ c == 17 ? AF_EBI_ADDRDAT15_PIN(f) : \\r
+ c == 18 ? AF_EBI_CS0_PIN(f) : \\r
+ c == 19 ? AF_EBI_CS1_PIN(f) : \\r
+ c == 20 ? AF_EBI_CS2_PIN(f) : \\r
+ c == 21 ? AF_EBI_CS3_PIN(f) : \\r
+ c == 22 ? AF_EBI_WEn_PIN(f) : \\r
+ c == 23 ? AF_EBI_REn_PIN(f) : \\r
+ c == 24 ? AF_EBI_ARDY_PIN(f) : \\r
+ c == 25 ? AF_EBI_ALE_PIN(f) : \\r
+ c == 26 ? AF_TIMER0_CC0_PIN(f) : \\r
+ c == 27 ? AF_TIMER0_CC1_PIN(f) : \\r
+ c == 28 ? AF_TIMER0_CC2_PIN(f) : \\r
+ c == 29 ? AF_TIMER0_CCC0_PIN(f) : \\r
+ c == 30 ? AF_TIMER0_CCC1_PIN(f) : \\r
+ c == 31 ? AF_TIMER0_CCC2_PIN(f) : \\r
+ c == 32 ? AF_TIMER1_CC0_PIN(f) : \\r
+ c == 33 ? AF_TIMER1_CC1_PIN(f) : \\r
+ c == 34 ? AF_TIMER1_CC2_PIN(f) : \\r
+ c == 35 ? AF_TIMER1_CCC0_PIN(f) : \\r
+ c == 36 ? AF_TIMER1_CCC1_PIN(f) : \\r
+ c == 37 ? AF_TIMER1_CCC2_PIN(f) : \\r
+ c == 38 ? AF_TIMER2_CC0_PIN(f) : \\r
+ c == 39 ? AF_TIMER2_CC1_PIN(f) : \\r
+ c == 40 ? AF_TIMER2_CC2_PIN(f) : \\r
+ c == 41 ? AF_TIMER2_CCC0_PIN(f) : \\r
+ c == 42 ? AF_TIMER2_CCC1_PIN(f) : \\r
+ c == 43 ? AF_TIMER2_CCC2_PIN(f) : \\r
+ c == 44 ? AF_USART0_TX_PIN(f) : \\r
+ c == 45 ? AF_USART0_RX_PIN(f) : \\r
+ c == 46 ? AF_USART0_CLK_PIN(f) : \\r
+ c == 47 ? AF_USART0_CS_PIN(f) : \\r
+ c == 48 ? AF_USART1_TX_PIN(f) : \\r
+ c == 49 ? AF_USART1_RX_PIN(f) : \\r
+ c == 50 ? AF_USART1_CLK_PIN(f) : \\r
+ c == 51 ? AF_USART1_CS_PIN(f) : \\r
+ c == 52 ? AF_USART2_TX_PIN(f) : \\r
+ c == 53 ? AF_USART2_RX_PIN(f) : \\r
+ c == 54 ? AF_USART2_CLK_PIN(f) : \\r
+ c == 55 ? AF_USART2_CS_PIN(f) : \\r
+ c == 56 ? AF_UART0_TX_PIN(f) : \\r
+ c == 57 ? AF_UART0_RX_PIN(f) : \\r
+ c == 58 ? AF_UART0_CLK_PIN(f) : \\r
+ c == 59 ? AF_UART0_CS_PIN(f) : \\r
+ c == 60 ? AF_LEUART0_TX_PIN(f) : \\r
+ c == 61 ? AF_LEUART0_RX_PIN(f) : \\r
+ c == 62 ? AF_LEUART1_TX_PIN(f) : \\r
+ c == 63 ? AF_LEUART1_RX_PIN(f) : \\r
+ c == 64 ? AF_LETIMER0_OUT0_PIN(f) : \\r
+ c == 65 ? AF_LETIMER0_OUT1_PIN(f) : \\r
+ c == 66 ? AF_PCNT0_S0IN_PIN(f) : \\r
+ c == 67 ? AF_PCNT0_S1IN_PIN(f) : \\r
+ c == 68 ? AF_PCNT1_S0IN_PIN(f) : \\r
+ c == 69 ? AF_PCNT1_S1IN_PIN(f) : \\r
+ c == 70 ? AF_PCNT2_S0IN_PIN(f) : \\r
+ c == 71 ? AF_PCNT2_S1IN_PIN(f) : \\r
+ c == 72 ? AF_I2C0_SDA_PIN(f) : \\r
+ c == 73 ? AF_I2C0_SCL_PIN(f) : \\r
+ c == 74 ? AF_ACMP0_OUT_PIN(f) : \\r
+ c == 75 ? AF_ACMP1_OUT_PIN(f) : \\r
+ c == 76 ? AF_DBG_SWV_PIN(f) : \\r
+ c == 77 ? AF_DBG_SWDITMS_PIN(f) : \\r
+ c == 78 ? AF_DBG_SWCLKTCK_PIN(f) : \\r
+ -1)\r
+\r
+/** AF channel output count for channel c */\r
+#define AF_COUNT(c) ( \\r
+ c == 0 ? 2 : \\r
+ c == 1 ? 2 : \\r
+ c == 2 ? 1 : \\r
+ c == 3 ? 1 : \\r
+ c == 4 ? 1 : \\r
+ c == 5 ? 1 : \\r
+ c == 6 ? 1 : \\r
+ c == 7 ? 1 : \\r
+ c == 8 ? 1 : \\r
+ c == 9 ? 1 : \\r
+ c == 10 ? 1 : \\r
+ c == 11 ? 1 : \\r
+ c == 12 ? 1 : \\r
+ c == 13 ? 1 : \\r
+ c == 14 ? 1 : \\r
+ c == 15 ? 1 : \\r
+ c == 16 ? 1 : \\r
+ c == 17 ? 1 : \\r
+ c == 18 ? 1 : \\r
+ c == 19 ? 1 : \\r
+ c == 20 ? 1 : \\r
+ c == 21 ? 1 : \\r
+ c == 22 ? 1 : \\r
+ c == 23 ? 1 : \\r
+ c == 24 ? 1 : \\r
+ c == 25 ? 1 : \\r
+ c == 26 ? 4 : \\r
+ c == 27 ? 4 : \\r
+ c == 28 ? 4 : \\r
+ c == 29 ? 4 : \\r
+ c == 30 ? 4 : \\r
+ c == 31 ? 4 : \\r
+ c == 32 ? 3 : \\r
+ c == 33 ? 3 : \\r
+ c == 34 ? 3 : \\r
+ c == 35 ? 0 : \\r
+ c == 36 ? 0 : \\r
+ c == 37 ? 0 : \\r
+ c == 38 ? 3 : \\r
+ c == 39 ? 3 : \\r
+ c == 40 ? 3 : \\r
+ c == 41 ? 0 : \\r
+ c == 42 ? 0 : \\r
+ c == 43 ? 0 : \\r
+ c == 44 ? 3 : \\r
+ c == 45 ? 3 : \\r
+ c == 46 ? 3 : \\r
+ c == 47 ? 3 : \\r
+ c == 48 ? 2 : \\r
+ c == 49 ? 2 : \\r
+ c == 50 ? 2 : \\r
+ c == 51 ? 2 : \\r
+ c == 52 ? 2 : \\r
+ c == 53 ? 2 : \\r
+ c == 54 ? 2 : \\r
+ c == 55 ? 2 : \\r
+ c == 56 ? 4 : \\r
+ c == 57 ? 4 : \\r
+ c == 58 ? 0 : \\r
+ c == 59 ? 0 : \\r
+ c == 60 ? 3 : \\r
+ c == 61 ? 3 : \\r
+ c == 62 ? 2 : \\r
+ c == 63 ? 2 : \\r
+ c == 64 ? 4 : \\r
+ c == 65 ? 4 : \\r
+ c == 66 ? 3 : \\r
+ c == 67 ? 3 : \\r
+ c == 68 ? 2 : \\r
+ c == 69 ? 2 : \\r
+ c == 70 ? 2 : \\r
+ c == 71 ? 2 : \\r
+ c == 72 ? 4 : \\r
+ c == 73 ? 4 : \\r
+ c == 74 ? 2 : \\r
+ c == 75 ? 2 : \\r
+ c == 76 ? 2 : \\r
+ c == 77 ? 2 : \\r
+ c == 78 ? 2 : \\r
+ -1)\r
+\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Set the value of a bit field within a register.\r
+ *\r
+ * @param REG\r
+ * The register to update\r
+ * @param MASK\r
+ * The mask for the bit field to update\r
+ * @param VALUE\r
+ * The value to write to the bit field\r
+ * @param OFFSET\r
+ * The number of bits that the field is offset within the register.\r
+ * 0 (zero) means LSB.\r
+ */\r
+#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
+ REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
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