Correcting spelling mistakes in comments only.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2645 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
index 51924f0bea5c45ce9ef558827484ab14a580d27e..7a47e1efba4253df69cf145bddf976dba978139a 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
+++ b/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
@@ -75,7 +75,7 @@
 /* Save additional registers found on the Pulpino. */\r
 .macro portasmSAVE_ADDITIONAL_REGISTERS\r
        addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */\r
-       csrr t0, lpstart0                                                        /* Load additional registers into accessable temporary registers. */\r
+       csrr t0, lpstart0                                                        /* Load additional registers into accessible temporary registers. */\r
        csrr t1, lpend0\r
        csrr t2, lpcount0\r
        csrr t3, lpstart1\r
@@ -91,7 +91,7 @@
 \r
 /* Restore the additional registers found on the Pulpino. */\r
 .macro portasmRESTORE_ADDITIONAL_REGISTERS\r
-       lw t0, 1 * portWORD_SIZE( sp )                  /* Load additional registers into accessable temporary registers. */\r
+       lw t0, 1 * portWORD_SIZE( sp )                  /* Load additional registers into accessible temporary registers. */\r
        lw t1, 2 * portWORD_SIZE( sp )\r
        lw t2, 3 * portWORD_SIZE( sp )\r
        lw t3, 4 * portWORD_SIZE( sp )\r