{\r
extern unsigned long __SRAM_segment_start__[];\r
extern unsigned long __SRAM_segment_end__[];\r
+extern unsigned long __privileged_data_start__[];\r
+extern unsigned long __privileged_data_end__[];\r
long lIndex;\r
unsigned long ul;\r
\r
if( xRegions == NULL )\r
{\r
- /* No MPU regions are specified to allow access to all RAM. */\r
+ /* No MPU regions are specified so allow access to all RAM. */\r
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = \r
( ( unsigned long ) __SRAM_segment_start__ ) | /* Base address. */\r
( portMPU_REGION_VALID ) |\r
( prvGetMPURegionSizeSetting( ( unsigned long ) __SRAM_segment_end__ - ( unsigned long ) __SRAM_segment_start__ ) ) |\r
( portMPU_REGION_ENABLE );\r
\r
+ /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
+ just removed the privileged only parameters. */\r
+ xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress = \r
+ ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */\r
+ ( portMPU_REGION_VALID ) |\r
+ ( portSTACK_REGION + 1 );\r
+\r
+ xMPUSettings->xRegion[ 1 ].ulRegionAttribute = \r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
+ prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) |\r
+ ( portMPU_REGION_ENABLE );\r
+ \r
/* Invalidate all other regions. */\r
- for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
- {\r
+ for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
+ { \r
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID; \r
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
}\r