Prepare VIC20 startup for different start addresses

git-svn-id: svn://svn.cc65.org/cc65/trunk@1390 b7a2c559-68d2-44c3-8de9-860c34a00d81

diff --git a/libsrc/vic20/crt0.s b/libsrc/vic20/crt0.s
index 4a916f948be0f6f7d98be22ef23572e2f941aeec..189a9d71bc508a2d12623e331df4826058399ae7 100644 (file)
--- a/libsrc/vic20/crt0.s
+++ b/libsrc/vic20/crt0.s
@@ -8,29 +8,33 @@
        .import         initlib, donelib
                .import         zerobss, push0
        .import         _main
-       .import         __RAM_START__, __RAM_SIZE__     ; Linker generated
+       .import         __RAM_START__, __RAM_SIZE__     ; Linker generated
 
         .include        "zeropage.inc"
-       .include        "vic20.inc"
-       .include        "../cbm/cbm.inc"
-
-.code
+       .include        "vic20.inc"
+       .include        "../cbm/cbm.inc"
 
 ; ------------------------------------------------------------------------
 ; BASIC header with a SYS call
 
-       .org    $FFF
+.segment        "EXEHDR"
         .word   Head            ; Load address
 Head:   .word   @Next
         .word   1000            ; Line number
-        .byte   $9E,"4109"      ; SYS 4109
+        .byte   $9E             ; SYS token
+        .byte   <(((@Start / 1000) .mod 10) + $30)
+        .byte   <(((@Start /  100) .mod 10) + $30)
+        .byte   <(((@Start /   10) .mod 10) + $30)
+        .byte   <(((@Start /    1) .mod 10) + $30)
         .byte   $00             ; End of BASIC line
 @Next:  .word   0               ; BASIC end marker
-       .reloc
+@Start:
 
 ; ------------------------------------------------------------------------
 ; Actual code
 
+.code
+
        ldx     #zpspace-1
 L1:    lda     sp,x
        sta     zpsave,x        ; Save the zero page locations we need

diff --git a/src/ld65/cfg/vic20.cfg b/src/ld65/cfg/vic20.cfg
index c1804ad23ed91e25b52f148e9fab78a87d4393fd..dd8ba7b22f32bc23f23d2f952abafc589b66d890 100644 (file)
--- a/src/ld65/cfg/vic20.cfg
+++ b/src/ld65/cfg/vic20.cfg
@@ -3,6 +3,7 @@ MEMORY {
     RAM: start = $FFF, size = $0E01, define = yes, file = %O;
 }
 SEGMENTS {
+    EXEHDR: load = RAM , type = wprot;
     CODE: load = RAM, type = wprot;
     RODATA: load = RAM, type = wprot;
     DATA: load = RAM, type = rw;