-<SAV MODE="TREE" VIEW="BUSINTERFACE"/>
\ No newline at end of file
+<SAV MODE="TREE" VIEW="ADDRESS"/>
\ No newline at end of file
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
- <DateModified>2011-05-30T21:45:55</DateModified>
+ <DateModified>2011-05-30T21:58:15</DateModified>
<ModuleName>system</ModuleName>
- <SummaryTimeStamp>2011-05-30T21:45:55</SummaryTimeStamp>
+ <SummaryTimeStamp>2011-05-30T21:58:14</SummaryTimeStamp>
<SavedFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/__xps/ise/system.xreport</SavedFilePath>
<FilterFile>filter.filter</FilterFile>
<SavedFilterFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/__xps/ise</SavedFilterFilePath>
-
-<EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Mon May 30 21:45:54 2011">
+<EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Mon May 30 21:58:14 2011">
<SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45t" PACKAGE="fgg484" PART="xc6slx45tfgg484-3" SOURCE="C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/system.xmp" SPEEDGRADE="-3"/>
+ <EXTERNALPORTS>
+ <PORT DIR="I" MHS_INDEX="0" NAME="RESET" RSTPOLARITY="1" SIGIS="RST" SIGNAME="RESET"/>
+ <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK"/>
+ <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="2" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK"/>
+ <PORT DIR="O" MHS_INDEX="3" NAME="RS232_Uart_1_sout" SIGNAME="RS232_Uart_1_sout"/>
+ <PORT DIR="I" MHS_INDEX="4" NAME="RS232_Uart_1_sin" SIGNAME="RS232_Uart_1_sin"/>
+ <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="5" MSB="0" NAME="LEDs_4Bits_TRI_O" RIGHT="3" SIGNAME="LEDs_4Bits_TRI_O"/>
+ <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="6" MSB="3" NAME="Push_Buttons_4Bits_TRI_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I"/>
+ <PORT DIR="O" MHS_INDEX="7" NAME="mcbx_dram_clk" SIGNAME="mcbx_dram_clk"/>
+ <PORT DIR="O" MHS_INDEX="8" NAME="mcbx_dram_clk_n" SIGNAME="mcbx_dram_clk_n"/>
+ <PORT DIR="O" MHS_INDEX="9" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
+ <PORT DIR="O" MHS_INDEX="10" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
+ <PORT DIR="O" MHS_INDEX="11" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
+ <PORT DIR="O" MHS_INDEX="12" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
+ <PORT DIR="O" MHS_INDEX="13" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
+ <PORT DIR="O" MHS_INDEX="14" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
+ <PORT DIR="O" MHS_INDEX="15" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
+ <PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="16" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba"/>
+ <PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="17" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr"/>
+ <PORT DIR="O" MHS_INDEX="18" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
+ <PORT DIR="IO" ENDIAN="LITTLE" LEFT="15" LSB="0" MHS_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq"/>
+ <PORT DIR="IO" MHS_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
+ <PORT DIR="IO" MHS_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
+ <PORT DIR="IO" MHS_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
+ <PORT DIR="IO" MHS_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
+ <PORT DIR="IO" MHS_INDEX="24" NAME="rzq" SIGNAME="rzq"/>
+ <PORT DIR="IO" MHS_INDEX="25" NAME="zio" SIGNAME="zio"/>
+ <PORT DIR="IO" MHS_INDEX="26" NAME="Ethernet_Lite_MDIO" SIGNAME="Ethernet_Lite_MDIO"/>
+ <PORT DIR="O" MHS_INDEX="27" NAME="Ethernet_Lite_MDC" SIGNAME="Ethernet_Lite_MDC"/>
+ <PORT DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="28" MSB="3" NAME="Ethernet_Lite_TXD" RIGHT="0" SIGNAME="Ethernet_Lite_TXD"/>
+ <PORT DIR="O" MHS_INDEX="29" NAME="Ethernet_Lite_TX_EN" SIGNAME="Ethernet_Lite_TX_EN"/>
+ <PORT DIR="I" MHS_INDEX="30" NAME="Ethernet_Lite_TX_CLK" SIGNAME="Ethernet_Lite_TX_CLK"/>
+ <PORT DIR="I" MHS_INDEX="31" NAME="Ethernet_Lite_COL" SIGNAME="Ethernet_Lite_COL"/>
+ <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="32" MSB="3" NAME="Ethernet_Lite_RXD" RIGHT="0" SIGNAME="Ethernet_Lite_RXD"/>
+ <PORT DIR="I" MHS_INDEX="33" NAME="Ethernet_Lite_RX_ER" SIGNAME="Ethernet_Lite_RX_ER"/>
+ <PORT DIR="I" MHS_INDEX="34" NAME="Ethernet_Lite_RX_CLK" SIGNAME="Ethernet_Lite_RX_CLK"/>
+ <PORT DIR="I" MHS_INDEX="35" NAME="Ethernet_Lite_CRS" SIGNAME="Ethernet_Lite_CRS"/>
+ <PORT DIR="I" MHS_INDEX="36" NAME="Ethernet_Lite_RX_DV" SIGNAME="Ethernet_Lite_RX_DV"/>
+ <PORT DIR="O" MHS_INDEX="37" NAME="Ethernet_Lite_PHY_RST_N" SIGNAME="Ethernet_Lite_PHY_RST_N"/>
+ </EXTERNALPORTS>
+
<MODULES>
<MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4_0" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="0" MODCLASS="BUS" MODTYPE="axi_interconnect">
<DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
</MODULE>
<MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4lite_0" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="axi_interconnect">
<DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
</MODULE>
<MODULE HWVERSION="8.10.a" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="2" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE">
<DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_10_a/doc/microblaze.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="100000000"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/>
</PORTMAPS>
</BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="6" MPD_INDEX="5" NAME="M_AXI_IP" PROTOCOL="AXI4LITE" TYPE="MASTER">
+ <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" MPD_INDEX="5" NAME="M_AXI_IP" PROTOCOL="AXI4LITE" TYPE="MASTER">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="CLK"/>
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWID"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
- <INTERRUPTINFO TYPE="TARGET">
- <SOURCE INSTANCE="microblaze_0_intc" INTC_INDEX="0"/>
- </INTERRUPTINFO>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_d_bram_ctrl" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
<ACCESSROUTE>
<PERIPHERAL INSTANCE="microblaze_0_intc"/>
<PERIPHERAL INSTANCE="MCB_DDR3"/>
</PERIPHERALS>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+ <INTERRUPTINFO TYPE="TARGET">
+ <SOURCE INSTANCE="microblaze_0_intc" INTC_INDEX="0"/>
+ </INTERRUPTINFO>
</MODULE>
<MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_ilmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10">
<DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"/>
<PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
<IOINTERFACES>
<IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
</IOINTERFACES>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
</MODULE>
<MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_dlmb" IPTYPE="BUS" MHS_INDEX="4" MODCLASS="BUS" MODTYPE="lmb_v10">
<DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"/>
<PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
<IOINTERFACES>
<IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
</IOINTERFACES>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
</MODULE>
<MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_i_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
<DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
</MODULE>
<MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_d_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
<DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="microblaze_0_bram_block" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="MEMORY" MODTYPE="bram_block">
<DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x2000"/>
<PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
</MODULE>
<MODULE HWVERSION="3.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
<DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="t"/>
<PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4"/>
<IOINTERFACES>
<IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
</IOINTERFACES>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
</MODULE>
<MODULE HWVERSION="4.01.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="IP" MODTYPE="clock_generator">
<DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_01_a/doc/clock_generator.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="6slx45t"/>
<PORT DIR="O" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
</PORTS>
<BUSINTERFACES/>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
</MODULE>
<MODULE HWVERSION="2.00.b" INSTANCE="debug_module" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="DEBUG" MODTYPE="mdm">
<DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/doc/mdm.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
<PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
</MODULE>
<MODULE HWVERSION="1.01.a" INSTANCE="RS232_Uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="axi_uartlite">
<DESCRIPTION TYPE="SHORT">AXI UART (Lite)</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_uartlite_v1_01_a/doc/axi_uartlite_ds741.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/>
</PORTMAPS>
</IOINTERFACE>
</IOINTERFACES>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="0"/>
- </INTERRUPTINFO>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
<SLAVES>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+ <INTERRUPTINFO TYPE="SOURCE">
+ <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="0"/>
+ </INTERRUPTINFO>
</MODULE>
<MODULE HWVERSION="1.01.a" INSTANCE="LEDs_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
<DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40020000"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
</MODULE>
<MODULE HWVERSION="1.01.a" INSTANCE="Push_Buttons_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
<DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40000000"/>
</PORTMAPS>
</IOINTERFACE>
</IOINTERFACES>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="1"/>
- </INTERRUPTINFO>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
<SLAVES>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+ <INTERRUPTINFO TYPE="SOURCE">
+ <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="1"/>
+ </INTERRUPTINFO>
</MODULE>
<MODULE HWVERSION="1.02.a" INSTANCE="MCB_DDR3" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_s6_ddrx">
<DESCRIPTION TYPE="SHORT">AXI S6 Memory Controller(DDR/DDR2/DDR3)</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_s6_ddrx_v1_02_a/doc/axi_s6_ddrx.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER MPD_INDEX="0" NAME="C_MCB_LOC" VALUE="MEMC3"/>
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_MCB_RZQ_LOC" TYPE="STRING" VALUE="K7"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="Ethernet_Lite" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="axi_ethernetlite">
<DESCRIPTION TYPE="SHORT">AXI 10/100 Ethernet MAC Lite</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_ethernetlite_v1_00_a/doc/ds787_axi_ethernetlite.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
- <PARAMETER CHANGEDBY="SYSTEM" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" VALUE="AXI4LITE"/>
+ <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" VALUE="AXI4LITE"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40e00000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x40e0ffff"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_S_AXI_ACLK_PERIOD_PS" TYPE="INTEGER" VALUE="20000"/>
<PARAMETER MPD_INDEX="5" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER MPD_INDEX="6" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
- <PARAMETER CHANGEDBY="SYSTEM" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="7" NAME="C_S_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
+ <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="7" NAME="C_S_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
<PARAMETER MPD_INDEX="8" NAME="C_INCLUDE_MDIO" TYPE="INTEGER" VALUE="1"/>
<PARAMETER MPD_INDEX="9" NAME="C_INCLUDE_GLOBAL_BUFFERS" TYPE="INTEGER" VALUE="0"/>
<PARAMETER MPD_INDEX="10" NAME="C_INCLUDE_INTERNAL_LOOPBACK" TYPE="INTEGER" VALUE="0"/>
</PORTMAPS>
</IOINTERFACE>
</IOINTERFACES>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="2"/>
- </INTERRUPTINFO>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="1088421888" BASENAME="C_BASEADDR" BASEVALUE="0x40e00000" HIGHDECIMAL="1088487423" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40e0ffff" MEMTYPE="REGISTER" MINSIZE="0x02000" SIZE="65536" SIZEABRV="64K">
<SLAVES>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+ <INTERRUPTINFO TYPE="SOURCE">
+ <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="2"/>
+ </INTERRUPTINFO>
</MODULE>
<MODULE HWVERSION="1.01.a" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="PERIPHERAL" MODTYPE="axi_timer">
<DESCRIPTION TYPE="SHORT">AXI Timer/Counter</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_timer_v1_01_a/doc/axi_timer_ds764.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
- <INTERRUPTINFO TYPE="SOURCE">
- <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="3"/>
- </INTERRUPTINFO>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
<SLAVES>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+ <INTERRUPTINFO TYPE="SOURCE">
+ <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="3"/>
+ </INTERRUPTINFO>
</MODULE>
<MODULE HWVERSION="1.01.a" INSTANCE="microblaze_0_intc" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc">
<DESCRIPTION TYPE="SHORT">AXI Interrupt Controller</DESCRIPTION>
<DOCUMENTATION>
<DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_intc_v1_01_a/doc/ds747_axi_intc.pdf" TYPE="IP"/>
</DOCUMENTATION>
+ <LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41200000"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
- <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
- <SOURCE INSTANCE="RS232_Uart_1" PRIORITY="0" SIGNAME="RS232_Uart_1_Interrupt"/>
- <SOURCE INSTANCE="Push_Buttons_4Bits" PRIORITY="1" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
- <SOURCE INSTANCE="Ethernet_Lite" PRIORITY="2" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
- <SOURCE INSTANCE="axi_timer_0" PRIORITY="3" SIGNAME="axi_timer_0_Interrupt"/>
- <TARGET INSTANCE="microblaze_0"/>
- </INTERRUPTINFO>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
<SLAVES>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
- <LICENSEINFO ICON_NAME="ps_core_preferred"/>
+ <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
+ <SOURCE INSTANCE="RS232_Uart_1" PRIORITY="0" SIGNAME="RS232_Uart_1_Interrupt"/>
+ <SOURCE INSTANCE="Push_Buttons_4Bits" PRIORITY="1" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
+ <SOURCE INSTANCE="Ethernet_Lite" PRIORITY="2" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
+ <SOURCE INSTANCE="axi_timer_0" PRIORITY="3" SIGNAME="axi_timer_0_Interrupt"/>
+ <TARGET INSTANCE="microblaze_0"/>
+ </INTERRUPTINFO>
</MODULE>
</MODULES>
- <EXTERNALPORTS>
- <PORT DIR="I" MHS_INDEX="0" NAME="RESET" RSTPOLARITY="1" SIGIS="RST" SIGNAME="RESET"/>
- <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK"/>
- <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="2" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK"/>
- <PORT DIR="O" MHS_INDEX="3" NAME="RS232_Uart_1_sout" SIGNAME="RS232_Uart_1_sout"/>
- <PORT DIR="I" MHS_INDEX="4" NAME="RS232_Uart_1_sin" SIGNAME="RS232_Uart_1_sin"/>
- <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="5" MSB="0" NAME="LEDs_4Bits_TRI_O" RIGHT="3" SIGNAME="LEDs_4Bits_TRI_O"/>
- <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="6" MSB="3" NAME="Push_Buttons_4Bits_TRI_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I"/>
- <PORT DIR="O" MHS_INDEX="7" NAME="mcbx_dram_clk" SIGNAME="mcbx_dram_clk"/>
- <PORT DIR="O" MHS_INDEX="8" NAME="mcbx_dram_clk_n" SIGNAME="mcbx_dram_clk_n"/>
- <PORT DIR="O" MHS_INDEX="9" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
- <PORT DIR="O" MHS_INDEX="10" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
- <PORT DIR="O" MHS_INDEX="11" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
- <PORT DIR="O" MHS_INDEX="12" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
- <PORT DIR="O" MHS_INDEX="13" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
- <PORT DIR="O" MHS_INDEX="14" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
- <PORT DIR="O" MHS_INDEX="15" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
- <PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="16" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba"/>
- <PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="17" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr"/>
- <PORT DIR="O" MHS_INDEX="18" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
- <PORT DIR="IO" ENDIAN="LITTLE" LEFT="15" LSB="0" MHS_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq"/>
- <PORT DIR="IO" MHS_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
- <PORT DIR="IO" MHS_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
- <PORT DIR="IO" MHS_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
- <PORT DIR="IO" MHS_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
- <PORT DIR="IO" MHS_INDEX="24" NAME="rzq" SIGNAME="rzq"/>
- <PORT DIR="IO" MHS_INDEX="25" NAME="zio" SIGNAME="zio"/>
- <PORT DIR="IO" MHS_INDEX="26" NAME="Ethernet_Lite_MDIO" SIGNAME="Ethernet_Lite_MDIO"/>
- <PORT DIR="O" MHS_INDEX="27" NAME="Ethernet_Lite_MDC" SIGNAME="Ethernet_Lite_MDC"/>
- <PORT DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="28" MSB="3" NAME="Ethernet_Lite_TXD" RIGHT="0" SIGNAME="Ethernet_Lite_TXD"/>
- <PORT DIR="O" MHS_INDEX="29" NAME="Ethernet_Lite_TX_EN" SIGNAME="Ethernet_Lite_TX_EN"/>
- <PORT DIR="I" MHS_INDEX="30" NAME="Ethernet_Lite_TX_CLK" SIGNAME="Ethernet_Lite_TX_CLK"/>
- <PORT DIR="I" MHS_INDEX="31" NAME="Ethernet_Lite_COL" SIGNAME="Ethernet_Lite_COL"/>
- <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="32" MSB="3" NAME="Ethernet_Lite_RXD" RIGHT="0" SIGNAME="Ethernet_Lite_RXD"/>
- <PORT DIR="I" MHS_INDEX="33" NAME="Ethernet_Lite_RX_ER" SIGNAME="Ethernet_Lite_RX_ER"/>
- <PORT DIR="I" MHS_INDEX="34" NAME="Ethernet_Lite_RX_CLK" SIGNAME="Ethernet_Lite_RX_CLK"/>
- <PORT DIR="I" MHS_INDEX="35" NAME="Ethernet_Lite_CRS" SIGNAME="Ethernet_Lite_CRS"/>
- <PORT DIR="I" MHS_INDEX="36" NAME="Ethernet_Lite_RX_DV" SIGNAME="Ethernet_Lite_RX_DV"/>
- <PORT DIR="O" MHS_INDEX="37" NAME="Ethernet_Lite_PHY_RST_N" SIGNAME="Ethernet_Lite_PHY_RST_N"/>
- </EXTERNALPORTS>
-
</EDKSYSTEM>
\ No newline at end of file
-
<FILTERS>
<IDENTIFICATION VERSION="1.2" XTLVERSION="1.2"/>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>system Project Status</B></TD></TR>
+<TD ALIGN=CENTER COLSPAN='4'><B>Project Status (05/30/2011 - 22:14:08)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>system.xmp</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
-<TD>New</TD>
+<TD>Programming File Generated</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>system</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
-<TD> </TD>
+<TD>
+No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>EDK 13.1</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
-<TD> </TD>
+<TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/*.xmsgs?&DataKey=Warning'>151 Warnings (151 new)</A></TD>
</TR>
</TABLE>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>XPS Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD>Platgen Log File</TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\platgen.log'>Platgen Log File</A></TD><TD>Mon 30. May 22:03:50 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\__xps/ise/_xmsgs/platgen.xmsgs?&DataKey=Warning'>8 Warnings (8 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\__xps/ise/_xmsgs/platgen.xmsgs?&DataKey=Info'>35 Infos (35 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Libgen Log File</TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
<TR ALIGN=LEFT><TD>Simgen Log File</TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
<TR ALIGN=LEFT><TD>BitInit Log File</TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\system.log'>System Log File</A></TD><TD>Mon 30. May 21:45:55 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\system.log'>System Log File</A></TD><TD>Mon 30. May 22:14:06 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
</TABLE>
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>XPS Synthesis Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKSynthesisSumary"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report</B></TD><TD><B>Generated</B></TD><TD><B>Flip Flops Used</B></TD><TD><B>LUTs Used</B></TD><TD><B>BRAMS Used</B></TD><TD COLSPAN='2'><B>Errors</B></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\system_xst.srp'>system</A></TD><TD>Mon 30. May 22:04:22 2011</TD><TD ALIGN=RIGHT>8098</TD><TD ALIGN=RIGHT>8082</TD><TD ALIGN=RIGHT>26</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\microblaze_0_intc_wrapper_xst.srp'>microblaze_0_intc_wrapper</A></TD><TD>Mon 30. May 22:03:25 2011</TD><TD ALIGN=RIGHT>72</TD><TD ALIGN=RIGHT>88</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\axi_timer_0_wrapper_xst.srp'>axi_timer_0_wrapper</A></TD><TD>Mon 30. May 22:03:17 2011</TD><TD ALIGN=RIGHT>260</TD><TD ALIGN=RIGHT>272</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\ethernet_lite_wrapper_xst.srp'>ethernet_lite_wrapper</A></TD><TD>Mon 30. May 22:03:06 2011</TD><TD ALIGN=RIGHT>491</TD><TD ALIGN=RIGHT>701</TD><TD ALIGN=RIGHT>4</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD>ethernet_lite_wrapper_fifo_generator_v8_1_fifo_generator_v8_1_xst_1</TD><TD>Mon 30. May 22:02:50 2011</TD><TD ALIGN=RIGHT>71</TD><TD ALIGN=RIGHT>44</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\mcb_ddr3_wrapper_xst.srp'>mcb_ddr3_wrapper</A></TD><TD>Mon 30. May 22:01:44 2011</TD><TD ALIGN=RIGHT>372</TD><TD ALIGN=RIGHT>689</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\push_buttons_4bits_wrapper_xst.srp'>push_buttons_4bits_wrapper</A></TD><TD>Mon 30. May 22:01:21 2011</TD><TD ALIGN=RIGHT>72</TD><TD ALIGN=RIGHT>85</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\leds_4bits_wrapper_xst.srp'>leds_4bits_wrapper</A></TD><TD>Mon 30. May 22:01:11 2011</TD><TD ALIGN=RIGHT>33</TD><TD ALIGN=RIGHT>41</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\rs232_uart_1_wrapper_xst.srp'>rs232_uart_1_wrapper</A></TD><TD>Mon 30. May 22:01:01 2011</TD><TD ALIGN=RIGHT>84</TD><TD ALIGN=RIGHT>102</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\debug_module_wrapper_xst.srp'>debug_module_wrapper</A></TD><TD>Mon 30. May 22:00:52 2011</TD><TD ALIGN=RIGHT>131</TD><TD ALIGN=RIGHT>142</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\clock_generator_0_wrapper_xst.srp'>clock_generator_0_wrapper</A></TD><TD>Mon 30. May 22:00:44 2011</TD><TD> </TD><TD> </TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\proc_sys_reset_0_wrapper_xst.srp'>proc_sys_reset_0_wrapper</A></TD><TD>Mon 30. May 22:00:39 2011</TD><TD ALIGN=RIGHT>69</TD><TD ALIGN=RIGHT>55</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\microblaze_0_bram_block_wrapper_xst.srp'>microblaze_0_bram_block_wrapper</A></TD><TD>Mon 30. May 22:00:33 2011</TD><TD> </TD><TD> </TD><TD ALIGN=RIGHT>4</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\microblaze_0_d_bram_ctrl_wrapper_xst.srp'>microblaze_0_d_bram_ctrl_wrapper</A></TD><TD>Mon 30. May 22:00:27 2011</TD><TD ALIGN=RIGHT>2</TD><TD ALIGN=RIGHT>6</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\microblaze_0_i_bram_ctrl_wrapper_xst.srp'>microblaze_0_i_bram_ctrl_wrapper</A></TD><TD>Mon 30. May 22:00:22 2011</TD><TD ALIGN=RIGHT>2</TD><TD ALIGN=RIGHT>6</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\microblaze_0_dlmb_wrapper_xst.srp'>microblaze_0_dlmb_wrapper</A></TD><TD>Mon 30. May 22:00:16 2011</TD><TD ALIGN=RIGHT>1</TD><TD ALIGN=RIGHT>1</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\microblaze_0_ilmb_wrapper_xst.srp'>microblaze_0_ilmb_wrapper</A></TD><TD>Mon 30. May 22:00:11 2011</TD><TD ALIGN=RIGHT>1</TD><TD ALIGN=RIGHT>1</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\microblaze_0_wrapper_xst.srp'>microblaze_0_wrapper</A></TD><TD>Mon 30. May 22:00:06 2011</TD><TD ALIGN=RIGHT>2388</TD><TD ALIGN=RIGHT>3217</TD><TD ALIGN=RIGHT>18</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\axi4lite_0_wrapper_xst.srp'>axi4lite_0_wrapper</A></TD><TD>Mon 30. May 21:59:15 2011</TD><TD ALIGN=RIGHT>2720</TD><TD ALIGN=RIGHT>1760</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\axi4_0_wrapper_xst.srp'>axi4_0_wrapper</A></TD><TD>Mon 30. May 21:58:52 2011</TD><TD ALIGN=RIGHT>1258</TD><TD ALIGN=RIGHT>828</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+</TABLE>
+ <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary (actual values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
+<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
+<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
+<TD ALIGN=RIGHT>5,838</TD>
+<TD ALIGN=RIGHT>54,576</TD>
+<TD ALIGN=RIGHT>10%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD>
+<TD ALIGN=RIGHT>5,830</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latch-thrus</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as AND/OR logics</TD>
+<TD ALIGN=RIGHT>8</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
+<TD ALIGN=RIGHT>6,093</TD>
+<TD ALIGN=RIGHT>27,288</TD>
+<TD ALIGN=RIGHT>22%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
+<TD ALIGN=RIGHT>5,529</TD>
+<TD ALIGN=RIGHT>27,288</TD>
+<TD ALIGN=RIGHT>20%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
+<TD ALIGN=RIGHT>3,953</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
+<TD ALIGN=RIGHT>216</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
+<TD ALIGN=RIGHT>1,360</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ROM</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Memory</TD>
+<TD ALIGN=RIGHT>358</TD>
+<TD ALIGN=RIGHT>6,408</TD>
+<TD ALIGN=RIGHT>5%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Dual Port RAM</TD>
+<TD ALIGN=RIGHT>96</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
+<TD ALIGN=RIGHT>91</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Single Port RAM</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Shift Register</TD>
+<TD ALIGN=RIGHT>258</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
+<TD ALIGN=RIGHT>157</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
+<TD ALIGN=RIGHT>7</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
+<TD ALIGN=RIGHT>94</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used exclusively as route-thrus</TD>
+<TD ALIGN=RIGHT>206</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD>
+<TD ALIGN=RIGHT>195</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD>
+<TD ALIGN=RIGHT>11</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with other load</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
+<TD ALIGN=RIGHT>2,603</TD>
+<TD ALIGN=RIGHT>6,822</TD>
+<TD ALIGN=RIGHT>38%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
+<TD ALIGN=RIGHT>7,539</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD>
+<TD ALIGN=RIGHT>2,471</TD>
+<TD ALIGN=RIGHT>7,539</TD>
+<TD ALIGN=RIGHT>32%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD>
+<TD ALIGN=RIGHT>1,446</TD>
+<TD ALIGN=RIGHT>7,539</TD>
+<TD ALIGN=RIGHT>19%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD>
+<TD ALIGN=RIGHT>3,622</TD>
+<TD ALIGN=RIGHT>7,539</TD>
+<TD ALIGN=RIGHT>48%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD>
+<TD ALIGN=RIGHT>414</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD>
+<TD ALIGN=RIGHT>1,619</TD>
+<TD ALIGN=RIGHT>54,576</TD>
+<TD ALIGN=RIGHT>2%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\system_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
+<TD ALIGN=RIGHT>78</TD>
+<TD ALIGN=RIGHT>296</TD>
+<TD ALIGN=RIGHT>26%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of LOCed IOBs</TD>
+<TD ALIGN=RIGHT>78</TD>
+<TD ALIGN=RIGHT>78</TD>
+<TD ALIGN=RIGHT>100%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> IOB Flip Flops</TD>
+<TD ALIGN=RIGHT>18</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
+<TD ALIGN=RIGHT>26</TD>
+<TD ALIGN=RIGHT>116</TD>
+<TD ALIGN=RIGHT>22%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>232</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>32</TD>
+<TD ALIGN=RIGHT>3%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFIO2s</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFIO2_2CLKs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>32</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
+<TD ALIGN=RIGHT>3</TD>
+<TD ALIGN=RIGHT>16</TD>
+<TD ALIGN=RIGHT>18%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGs</TD>
+<TD ALIGN=RIGHT>3</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGMUX</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>8</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
+<TD ALIGN=RIGHT>10</TD>
+<TD ALIGN=RIGHT>376</TD>
+<TD ALIGN=RIGHT>2%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ILOGIC2s</TD>
+<TD ALIGN=RIGHT>10</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ISERDES2s</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
+<TD ALIGN=RIGHT>24</TD>
+<TD ALIGN=RIGHT>376</TD>
+<TD ALIGN=RIGHT>6%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as IODELAY2s</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as IODRP2s</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as IODRP2_MCBs</TD>
+<TD ALIGN=RIGHT>22</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
+<TD ALIGN=RIGHT>53</TD>
+<TD ALIGN=RIGHT>376</TD>
+<TD ALIGN=RIGHT>14%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as OLOGIC2s</TD>
+<TD ALIGN=RIGHT>7</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as OSERDES2s</TD>
+<TD ALIGN=RIGHT>46</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD ALIGN=RIGHT>25%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>256</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>8</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD ALIGN=RIGHT>25%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
+<TD ALIGN=RIGHT>8</TD>
+<TD ALIGN=RIGHT>58</TD>
+<TD ALIGN=RIGHT>13%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of GTPA1_DUALs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>50%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCIE_A1s</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD ALIGN=RIGHT>25%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'> </TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
+<TD ALIGN=RIGHT>3.78</TD>
+<TD> </TD>
+<TD> </TD>
+<TD COLSPAN='2'> </TD>
+</TR>
</TABLE>
-
-
+ <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
+<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
+<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
+<TD COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\system_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
+<A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\system.unroutes'>All Signals Completely Routed</A></TD>
+<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
+<TD COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\system_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
+<TD>
+<A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\system.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
+<TD BGCOLOR='#FFFF99'><B> </B></TD>
+<TD COLSPAN='2'> </TD>
+</TABLE>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
-<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
-<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
-<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
-<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\system.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon 30. May 22:05:37 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>72 Warnings (72 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/ngdbuild.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\system_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon 30. May 22:10:43 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/map.xmsgs?&DataKey=Warning'>26 Warnings (26 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/map.xmsgs?&DataKey=Info'>840 Infos (840 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\system.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon 30. May 22:12:50 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/par.xmsgs?&DataKey=Warning'>28 Warnings (28 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/par.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\system.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Mon 30. May 22:13:20 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\system.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Mon 30. May 22:14:07 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>25 Warnings (25 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon 30. May 22:14:08 2011</TD></TR>
</TABLE>
-<br><center><b>Date Generated:</b> 05/30/2011 - 21:45:55</center>
+<br><center><b>Date Generated:</b> 05/30/2011 - 22:14:08</center>
</BODY></HTML>
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+++ /dev/null
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 13.1 Build EDK_O.40d\r
-Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
-\r
-Generated Block Diagram.\r
-Diagram Controls\r
-Zoom In/Out = ALT + (Mouse + Left Button) or ARROW UP/DOWN.\r
-Pan = SHIFT + (Mouse + Left Button) or ARROW UP/DOWN/LEFT/RIGHT.\r
-Writing filter settings....\r
-Done writing filter settings to:\r
- C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_SP605\etc\system.filters\r
-Done writing Tab View settings to:\r
- C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_SP605\etc\system.gui\r
-Xilinx Platform Studio (XPS)\r
-Xilinx EDK 13.1 Build EDK_O.40d\r
-Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
-\r
-Generated Block Diagram.\r
-Diagram Controls\r
-Zoom In/Out = ALT + (Mouse + Left Button) or ARROW UP/DOWN.\r
-Pan = SHIFT + (Mouse + Left Button) or ARROW UP/DOWN/LEFT/RIGHT.\r
-ERROR:EDK:1405 - File not found in any repository 'bram_block_v1_00_a/hdl/vhdl/bram_block.vhd'\r
-Save project successfully\r
-Writing filter settings....\r
-Done writing filter settings to:\r
- C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_SP605\etc\system.filters\r
-Done writing Tab View settings to:\r
- C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_SP605\etc\system.gui\r
projects / freertos / commitdiff