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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="CTRL+K"/>\r\n<keyBinding contextId\="org.eclipse.ui.textEditorScope" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="CTRL+K"/>\r\n<keyBinding contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="CTRL+B"/>\r\n<keyBinding contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="CTRL+B"/>\r\n<keyBinding commandId\="org.eclipse.ui.project.buildAll" contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F7"/>\r\n<keyBinding contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="CTRL+F11"/>\r\n<keyBinding contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="CTRL+F11"/>\r\n<keyBinding commandId\="org.eclipse.debug.ui.commands.RunLast" contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F5"/>\r\n<keyBinding contextId\="org.eclipse.debug.ui.debugging" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F5"/>\r\n<keyBinding contextId\="org.eclipse.debug.ui.debugging" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F5"/>\r\n<keyBinding commandId\="org.eclipse.debug.ui.commands.StepInto" contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F11"/>\r\n<keyBinding contextId\="org.eclipse.debug.ui.debugging" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F6"/>\r\n<keyBinding contextId\="org.eclipse.debug.ui.debugging" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F6"/>\r\n<keyBinding commandId\="org.eclipse.debug.ui.commands.StepOver" contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F10"/>\r\n<keyBinding contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="CTRL+SHIFT+B"/>\r\n<keyBinding contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="CTRL+SHIFT+B"/>\r\n<keyBinding commandId\="org.eclipse.debug.ui.commands.ToggleBreakpoint" contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F9"/>\r\n<keyBinding contextId\="org.eclipse.cdt.make.ui.makefileEditorScope" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F3"/>\r\n<keyBinding contextId\="org.eclipse.cdt.make.ui.makefileEditorScope" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F3"/>\r\n<keyBinding contextId\="org.eclipse.cdt.ui.cEditorScope" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F3"/>\r\n<keyBinding contextId\="org.eclipse.cdt.ui.cEditorScope" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F3"/>\r\n<keyBinding contextId\="org.eclipse.cdt.ui.cViewScope" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F3"/>\r\n<keyBinding contextId\="org.eclipse.cdt.ui.cViewScope" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F3"/>\r\n<keyBinding contextId\="org.eclipse.cdt.ui.macroExpansionHoverScope" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F3"/>\r\n<keyBinding contextId\="org.eclipse.cdt.ui.macroExpansionHoverScope" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F3"/>\r\n<keyBinding contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F3"/>\r\n<keyBinding contextId\="org.eclipse.ui.contexts.window" keyConfigurationId\="org.eclipse.ui.defaultAcceleratorConfiguration" keySequence\="F3"/>\r\n</org.eclipse.ui.commands>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbremote.core.imageFileName" value="C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\ColdFire_MCF52233_Eclipse\RTOSDemo\bin\RTOSDemo.elf"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbremote.core.initCommands" value="target remote | m68k-elf-sprite pe: m52235evb"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbremote.core.ipAddress" value="localhost"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbremote.core.loadImage" value="false"/>\r
+<intAttribute key="org.eclipse.cdt.debug.gdbremote.core.portNumber" value="10000"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbremote.core.runCommands" value="b main jump __cs3_reset_m52235evb "/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbremote.core.useRemoteTarget" value="false"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="m68k-elf-gdb"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.GDB_INIT" value=""/>\r
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <registerGroups> <group memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;registerGroup enabled=&quot;true&quot; name=&quot;Main&quot;&gt;&#13;&#10;&lt;register name=&quot;d0&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;d1&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;d2&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;d3&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;d4&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;d5&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;d6&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;d7&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;a0&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;a1&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;a2&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;a3&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;a4&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;a5&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;fp&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;sp&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;ps&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;pc&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;/registerGroup&gt;&#13;&#10;"/> <group memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;registerGroup enabled=&quot;true&quot; name=&quot;New Group&quot;&gt;&#13;&#10;&lt;register name=&quot;d0&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;d1&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;d2&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;d3&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;d4&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;d5&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;d6&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;d7&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;a0&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;a1&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;a2&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;a3&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;a4&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;a5&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;fp&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;sp&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;ps&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;register name=&quot;pc&quot; originalGroupName=&quot;Main&quot;/&gt;&#13;&#10;&lt;/registerGroup&gt;&#13;&#10;"/> </registerGroups> "/>\r
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList><content id="us-main-(format)" val="4"/><content id="d0-(format)" val="4"/><content id="d1-(format)" val="4"/><content id="d4-(format)" val="4"/><content id="d7-(format)" val="4"/><content id="ps-(format)" val="4"/></contentList>"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/>\r
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList> <memoryBlockExpressionItem> <expression text="536890128"/> </memoryBlockExpressionItem> <memoryBlockExpressionItem> <expression text="536891648"/> </memoryBlockExpressionItem> </memoryBlockExpressionList> "/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="bin/RTOSDemo.elf"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RTOSDemo"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.1348192838"/>\r
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">\r
+<listEntry value="/RTOSDemo"/>\r
+</listAttribute>\r
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">\r
+<listEntry value="4"/>\r
+</listAttribute>\r
+</launchConfiguration>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<section name="Workbench">\r
+ <section name="org.eclipse.debug.ui.LAUNCH_CONFIGURATIONS_DIALOG_SECTION">\r
+ <item value="952" key="DIALOG_WIDTH"/>\r
+ <item value="140" key="DIALOG_Y_ORIGIN"/>\r
+ <item value=", org.eclipse.cdt.debug.gdbjtag.launchConfigurationType, " key="org.eclipse.debug.ui.EXPANDED_NODES"/>\r
+ <item value="199" key="DIALOG_X_ORIGIN"/>\r
+ <item value="640" key="DIALOG_HEIGHT"/>\r
+ <item value="237" key="org.eclipse.debug.ui.DIALOG_SASH_WEIGHTS_1"/>\r
+ <item value="762" key="org.eclipse.debug.ui.DIALOG_SASH_WEIGHTS_2"/>\r
+ <item value="1|Tahoma|8.25|0|WINDOWS|1|-11|0|0|0|400|0|0|0|1|0|0|0|0|Tahoma" key="DIALOG_FONT_NAME"/>\r
+ </section>\r
+</section>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<launchHistory>\r
+<launchGroup id="org.eclipse.ui.externaltools.launchGroup">\r
+<mruHistory/>\r
+<favorites/>\r
+</launchGroup>\r
+<launchGroup id="org.eclipse.debug.ui.launchGroup.profile">\r
+<mruHistory/>\r
+<favorites/>\r
+</launchGroup>\r
+<launchGroup id="org.eclipse.debug.ui.launchGroup.debug">\r
+<mruHistory>\r
+<launch memento="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <launchConfiguration local="true" path="RTOSDemo.launch"/> "/>\r
+</mruHistory>\r
+<favorites/>\r
+</launchGroup>\r
+<launchGroup id="org.eclipse.debug.ui.launchGroup.run">\r
+<mruHistory/>\r
+<favorites/>\r
+</launchGroup>\r
+</launchHistory>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<typeInfoHistroy/>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<qualifiedTypeNameHistroy/>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<section name="Workbench">\r
+ <section name="org.eclipse.jdt.internal.ui.packageview.PackageExplorerPart">\r
+ <item value="true" key="group_libraries"/>\r
+ <item value="false" key="linkWithEditor"/>\r
+ <item value="2" key="layout"/>\r
+ <item value="1" key="rootMode"/>\r
+ <item value="<?xml version="1.0" encoding="UTF-8"?>
<packageExplorer group_libraries="1" isWindowWorkingSet="true" layout="2" linkWithEditor="0" rootMode="1" workingSetName="">
<customFilters userDefinedPatternsEnabled="false">
<xmlDefinedFilters>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.LibraryFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.LocalTypesFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.StaticsFilter" isEnabled="false"/>
<child filterId="org.eclipse.pde.ui.ExternalPluginLibrariesFilter1" isEnabled="true"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.ClosedProjectsFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.NonSharedProjectsFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.NonJavaElementFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.ContainedLibraryFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.CuAndClassFileFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.NonJavaProjectsFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.internal.ui.PackageExplorer.EmptyInnerPackageFilter" isEnabled="true"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.PackageDeclarationFilter" isEnabled="true"/>
<child filterId="org.eclipse.jdt.internal.ui.PackageExplorer.EmptyPackageFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.ImportDeclarationFilter" isEnabled="true"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.FieldsFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.internal.ui.PackageExplorer.HideInnerClassFilesFilter" isEnabled="true"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.NonPublicFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer_patternFilterId_.*" isEnabled="true"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.EmptyLibraryContainerFilter" isEnabled="true"/>
<child filterId="org.eclipse.pde.ui.BinaryProjectFilter1" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.SyntheticMembersFilter" isEnabled="true"/>
</xmlDefinedFilters>
</customFilters>
</packageExplorer>" key="memento"/>\r
+ </section>\r
+ <section name="JavaElementSearchActions">\r
+ </section>\r
+</section>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<session version="1.0">\r
+<refactoring comment="Delete resource 'RTOSDemo/webserver/MCF5223x_Ethernet.c'" deleteContents="false" description="Delete resource 'RTOSDemo/webserver/MCF5223x_Ethernet.c'" element1="/RTOSDemo/webserver/MCF5223x_Ethernet.c" flags="7" id="org.eclipse.ltk.core.refactoring.delete.resources" resources="1" stamp="1226771144015"/>\r
+</session>
\ No newline at end of file
--- /dev/null
+1226771144015 Delete resource 'RTOSDemo/webserver/MCF5223x_Ethernet.c'
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<session version="1.0">\r
+<refactoring comment="Rename resource 'RTOSDemo/webserver/fec.h' to 'FEC.h'" description="Rename resource 'fec.h'" flags="7" id="org.eclipse.ltk.core.refactoring.rename.resource" input="webserver/fec.h" name="FEC.h" stamp="1226827901062" updateReferences="true"/>\r
+</session>
\ No newline at end of file
--- /dev/null
+1226827901062 Rename resource 'fec.h'
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<section name="Workbench">\r
+ <section name="RefactoringWizard.preview">\r
+ <item value="400" key="height"/>\r
+ <item value="600" key="width"/>\r
+ </section>\r
+</section>\r
--- /dev/null
+#Cached timestamps\r
+#Sun Nov 16 10:20:21 GMT 2008\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<section name="Workbench">\r
+ <section name="DialogBounds_SearchDialog">\r
+ <item value="519" key="DIALOG_WIDTH"/>\r
+ <item value="259" key="DIALOG_Y_ORIGIN"/>\r
+ <item value="385" key="DIALOG_HEIGHT"/>\r
+ <item value="445" key="DIALOG_X_ORIGIN"/>\r
+ <item value="1|Tahoma|8.25|0|WINDOWS|1|-11|0|0|0|400|0|0|0|1|0|0|0|0|Tahoma" key="DIALOG_FONT_NAME"/>\r
+ </section>\r
+ <section name="Search">\r
+ <list key="Search.processedPageIds">\r
+ <item value="org.eclipse.search.internal.ui.text.TextSearchPage"/>\r
+ <item value="org.eclipse.mylyn.tasks.ui.search.page"/>\r
+ <item value="org.eclipse.cdt.ui.pdomSearchPage"/>\r
+ <item value="org.eclipse.jdt.ui.JavaSearchPage"/>\r
+ <item value="org.eclipse.pde.internal.ui.search.SearchPage"/>\r
+ </list>\r
+ <list key="Search.enabledPageIds">\r
+ <item value="org.eclipse.search.internal.ui.text.TextSearchPage"/>\r
+ <item value="org.eclipse.mylyn.tasks.ui.search.page"/>\r
+ <item value="org.eclipse.cdt.ui.pdomSearchPage"/>\r
+ <item value="org.eclipse.jdt.ui.JavaSearchPage"/>\r
+ <item value="org.eclipse.pde.internal.ui.search.SearchPage"/>\r
+ </list>\r
+ </section>\r
+ <section name="org.eclipse.cdt.ui.pdomSearchViewPage">\r
+ </section>\r
+ <section name="SearchDialog.ScopePart">\r
+ <item value="0" key="scope"/>\r
+ </section>\r
+</section>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<section name="Workbench">\r
+ <section name="ChooseWorkspaceDialogSettings">\r
+ <item value="353" key="DIALOG_Y_ORIGIN"/>\r
+ <item value="547" key="DIALOG_X_ORIGIN"/>\r
+ </section>\r
+ <section name="WORKBENCH_SETTINGS">\r
+ <list key="ENABLED_TRANSFERS">\r
+ </list>\r
+ </section>\r
+ <section name="SaveAsDialogSettings">\r
+ <item value="438" key="DIALOG_WIDTH"/>\r
+ <item value="147" key="DIALOG_Y_ORIGIN"/>\r
+ <item value="625" key="DIALOG_X_ORIGIN"/>\r
+ <item value="553" key="DIALOG_HEIGHT"/>\r
+ <item value="1|Tahoma|8.25|0|WINDOWS|1|-11|0|0|0|400|0|0|0|1|0|0|0|0|Tahoma" key="DIALOG_FONT_NAME"/>\r
+ </section>\r
+ <section name="NewWizardAction">\r
+ <item value="org.eclipse.cdt.ui.wizards.NewCWizard2" key="NewWizardSelectionPage.STORE_SELECTED_ID"/>\r
+ <list key="NewWizardSelectionPage.STORE_EXPANDED_CATEGORIES_ID">\r
+ <item value="org.eclipse.cdt.ui.newCWizards"/>\r
+ </list>\r
+ </section>\r
+ <section name="CleanDialogSettings">\r
+ <item value="411" key="DIALOG_WIDTH"/>\r
+ <item value="false" key="BUILD_NOW"/>\r
+ <item value="275" key="DIALOG_Y_ORIGIN"/>\r
+ <item value="true" key="BUILD_ALL"/>\r
+ <item value="635" key="DIALOG_X_ORIGIN"/>\r
+ <item value="417" key="DIALOG_HEIGHT"/>\r
+ <item value="false" key="TOGGLE_SELECTED"/>\r
+ </section>\r
+</section>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<section name="Workbench">\r
+ <item value="1024" key="introLaunchBar.location"/>\r
+</section>\r
--- /dev/null
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--- /dev/null
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+ </natures>\r
+ <linkedResources>\r
+ <link>\r
+ <name>Demo_Source</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/Demo/Common</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/Source</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_uIP</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/Demo/Common/ethernet/FreeRTOS-uIP</locationURI>\r
+ </link>\r
+ </linkedResources>\r
+</projectDescription>\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include "MCF52235.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 100 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 90 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 15000 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_MUTEXES 1\r
+#define configCHECK_FOR_STACK_OVERFLOW 1\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 10\r
+#define configUSE_COUNTING_SEMAPHORES 0\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+\r
+#define configYIELD_INTERRUPT_VECTOR 16UL\r
+#define configKERNEL_INTERRUPT_PRIORITY 1\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4\r
+\r
+void vApplicationSetupInterrupts( void );\r
+\r
+\r
+/* Ethernet configuration. */\r
+#define configMAC_0 0x00\r
+#define configMAC_1 0x04\r
+#define configMAC_2 0x9F\r
+#define configMAC_3 0x00\r
+#define configMAC_4 0xAB\r
+#define configMAC_5 0x2B\r
+\r
+#define configIP_ADDR0 192\r
+#define configIP_ADDR1 168\r
+#define configIP_ADDR2 0\r
+#define configIP_ADDR3 11\r
+\r
+#define configGW_ADDR0 172\r
+#define configGW_ADDR1 25\r
+#define configGW_ADDR2 218\r
+#define configGW_ADDR3 3\r
+\r
+#define configNET_MASK0 255\r
+#define configNET_MASK1 255\r
+#define configNET_MASK2 255\r
+#define configNET_MASK3 0\r
+\r
+#define configNUM_FEC_TX_BUFFERS 1\r
+#define configNUM_FEC_RX_BUFFERS 3\r
+#define configFEC_BUFFER_SIZE 1520\r
+#define configUSE_PROMISCUOUS_MODE 0\r
+#define configETHERNET_INPUT_TASK_STACK_SIZE ( 320 )\r
+#define configFEC_INTERRUPT_PRIORITY configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+\r
+#define configPHY_ADDRESS 0\r
+\r
+#if ( configFEC_BUFFER_SIZE & 0x0F ) != 0\r
+ #error configFEC_BUFFER_SIZE must be a multiple of 16.\r
+#endif\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Constants used to configure the interrupts. */\r
+#define portPRESCALE_VALUE 64\r
+#define portPRESCALE_REG_SETTING ( 5 << 8 )\r
+#define portPIT_INTERRUPT_ENABLED ( 0x08 )\r
+#define configPIT0_INTERRUPT_VECTOR ( 55 )\r
+\r
+/*\r
+ * FreeRTOS.org requires two interrupts - a tick interrupt generated from a\r
+ * timer source, and a spare interrupt vector used for context switching.\r
+ * The configuration below uses PIT0 for the former, and vector 16 for the\r
+ * latter. **IF YOUR APPLICATION HAS BOTH OF THESE INTERRUPTS FREE THEN YOU DO\r
+ * NOT NEED TO CHANGE ANY OF THIS CODE** - otherwise instructions are provided\r
+ * here for using alternative interrupt sources.\r
+ *\r
+ * To change the tick interrupt source:\r
+ *\r
+ * 1) Modify vApplicationSetupInterrupts() below to be correct for whichever\r
+ * peripheral is to be used to generate the tick interrupt.\r
+ *\r
+ * 2) Change the name of the function __cs3_isr_interrupt_119() defined within\r
+ * this file to be correct for the interrupt vector used by the timer peripheral.\r
+ * The name of the function should contain the vector number, so by default vector\r
+ * number 119 is being used.\r
+ *\r
+ * 3) Make sure the tick interrupt is cleared within the interrupt handler function.\r
+ * Currently __cs3_isr_interrupt_119() clears the PIT0 interrupt.\r
+ *\r
+ * To change the spare interrupt source:\r
+ *\r
+ * 1) Modify vApplicationSetupInterrupts() below to be correct for whichever\r
+ * interrupt vector is to be used. Make sure you use a spare interrupt on interrupt\r
+ * controller 0, otherwise the register used to request context switches will also\r
+ * require modification. By default vector 16 is used which is free on most MCF52xxx\r
+ * devices.\r
+ *\r
+ * 2) Change the definition of configYIELD_INTERRUPT_VECTOR within FreeRTOSConfig.h\r
+ * to be correct for your chosen interrupt vector.\r
+ *\r
+ * 3) Change the name of the function __cs3_isr_interrupt_80() within portasm.S\r
+ * to be correct for whichever vector number is being used. By default interrupt\r
+ * controller 0 vector number 16 is used, which corresponds to vector number 80.\r
+ */\r
+void vApplicationSetupInterrupts( void )\r
+{\r
+const unsigned portSHORT usCompareMatchValue = ( ( configCPU_CLOCK_HZ / portPRESCALE_VALUE ) / configTICK_RATE_HZ );\r
+\r
+ /* Configure interrupt priority and level and unmask interrupt for PIT0. */\r
+ MCF_INTC0_ICR55 = ( 1 | ( configKERNEL_INTERRUPT_PRIORITY << 3 ) );\r
+ MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK55 );\r
+\r
+ /* Do the same for vector 16 (interrupt controller 0). I don't think the\r
+ write to MCF_INTC0_IMRH is actually required here but is included for\r
+ completeness. */\r
+ MCF_INTC0_ICR16 = ( 0 | ( configKERNEL_INTERRUPT_PRIORITY << 3 ) );\r
+ MCF_INTC0_IMRH &= ~( MCF_INTC_IPRL_INT16 );\r
+\r
+ /* Configure PIT0 to generate the RTOS tick. */\r
+ MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;\r
+ MCF_PIT0_PCSR = ( portPRESCALE_REG_SETTING | MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN );\r
+ MCF_PIT0_PMR = usCompareMatchValue;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_119( void )\r
+{\r
+unsigned portLONG ulSavedInterruptMask;\r
+\r
+ /* Clear the PIT0 interrupt. */\r
+ MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;\r
+\r
+ /* Increment the RTOS tick. */\r
+ ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ vTaskIncrementTick();\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );\r
+\r
+ /* If we are using the pre-emptive scheduler then also request a\r
+ context switch as incrementing the tick could have unblocked a task. */\r
+ #if configUSE_PREEMPTION == 1\r
+ {\r
+ taskYIELD();\r
+ }\r
+ #endif\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "IntQueueTimer.h"\r
+#include "IntQueue.h"\r
+\r
+#define timerINTERRUPT1_FREQUENCY ( 2000UL )\r
+#define timerINTERRUPT2_FREQUENCY ( 2001UL )\r
+#define timerPRESCALE_VALUE ( 2 )\r
+\r
+void vInitialiseTimerForIntQueueTest( void )\r
+{\r
+const unsigned portSHORT usCompareMatchValue1 = ( unsigned portSHORT ) ( ( configCPU_CLOCK_HZ / timerPRESCALE_VALUE ) / timerINTERRUPT1_FREQUENCY );\r
+const unsigned portSHORT usCompareMatchValue2 = ( unsigned portSHORT ) ( ( configCPU_CLOCK_HZ / timerPRESCALE_VALUE ) / timerINTERRUPT2_FREQUENCY );\r
+\r
+ /* Configure interrupt priority and level and unmask interrupt. */\r
+ MCF_INTC0_ICR56 = ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 1 ) << 3 );\r
+ MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK56 );\r
+\r
+ MCF_PIT1_PCSR |= MCF_PIT_PCSR_PIF;\r
+ MCF_PIT1_PCSR = ( MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN );\r
+ MCF_PIT1_PMR = usCompareMatchValue1;\r
+\r
+ MCF_INTC0_ICR57 = ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 3 );\r
+ MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK57 );\r
+\r
+// MCF_PIT2_PCSR |= MCF_PIT_PCSR_PIF;\r
+// MCF_PIT2_PCSR = ( MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN );\r
+// MCF_PIT2_PMR = usCompareMatchValue2;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_120( void )\r
+{\r
+ MCF_PIT1_PCSR |= MCF_PIT_PCSR_PIF;\r
+ portEND_SWITCHING_ISR( xFirstTimerHandler() );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_121( void )\r
+{\r
+//_RB_ MCF_PIT2_PCSR |= MCF_PIT_PCSR_PIF;\r
+ portEND_SWITCHING_ISR( xSecondTimerHandler() );\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and \r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety \r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting, \r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef INT_QUEUE_TIMER_H\r
+#define INT_QUEUE_TIMER_H\r
+\r
+void vInitialiseTimerForIntQueueTest( void );\r
+portBASE_TYPE xTimer0Handler( void );\r
+portBASE_TYPE xTimer1Handler( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT\r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT\r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING\r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY\r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+/* Standard library includes. */\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+xTaskHandle xEthIntTask;\r
+\r
+/* lwIP includes. */\r
+#include "lwip/def.h"\r
+#include "lwip/mem.h"\r
+#include "lwip/pbuf.h"\r
+#include "lwip/sys.h"\r
+#include "lwip/stats.h"\r
+#include "lwip/snmp.h"\r
+#include "netif/etharp.h"\r
+\r
+/* Hardware includes. */\r
+#include "fec.h"\r
+\r
+/* Delay to wait for a DMA buffer to become available if one is not already\r
+available. */\r
+#define netifBUFFER_WAIT_ATTEMPTS 10\r
+#define netifBUFFER_WAIT_DELAY (10 / portTICK_RATE_MS)\r
+\r
+/* Delay between polling the PHY to see if a link has been established. */\r
+#define netifLINK_DELAY ( 500 / portTICK_RATE_MS )\r
+\r
+/* Delay between looking for incoming packets. In ideal world this would be\r
+infinite. */\r
+#define netifBLOCK_TIME_WAITING_FOR_INPUT netifLINK_DELAY\r
+\r
+/* Name for the netif. */\r
+#define IFNAME0 'e'\r
+#define IFNAME1 'n'\r
+\r
+/* Hardware specific. */\r
+#define netifFIRST_FEC_VECTOR 23\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The DMA descriptors. This is a char array to allow us to align it correctly. */\r
+static unsigned portCHAR xFECTxDescriptors_unaligned[ ( configNUM_FEC_TX_BUFFERS * sizeof( FECBD ) ) + 16 ];\r
+static unsigned portCHAR xFECRxDescriptors_unaligned[ ( configNUM_FEC_RX_BUFFERS * sizeof( FECBD ) ) + 16 ];\r
+static FECBD *xFECTxDescriptors;\r
+static FECBD *xFECRxDescriptors;\r
+\r
+/* The DMA buffers. These are char arrays to allow them to be alligned correctly. */\r
+static unsigned portCHAR ucFECTxBuffers[ ( configNUM_FEC_TX_BUFFERS * configFEC_BUFFER_SIZE ) + 16 ];\r
+static unsigned portCHAR ucFECRxBuffers[ ( configNUM_FEC_RX_BUFFERS * configFEC_BUFFER_SIZE ) + 16 ];\r
+static unsigned portBASE_TYPE uxNextRxBuffer = 0, uxNextTxBuffer = 0;\r
+\r
+/* Semaphore used by the FEC interrupt handler to wake the handler task. */\r
+static xSemaphoreHandle xFecSemaphore;\r
+\r
+#pragma options align= packed\r
+struct ethernetif\r
+{\r
+ struct eth_addr *ethaddr;\r
+ /* Add whatever per-interface state that is needed here. */\r
+};\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Standard lwIP netif handlers. */\r
+static void prvInitialiseFECBuffers( void );\r
+static void low_level_init( struct netif *netif );\r
+static err_t low_level_output(struct netif *netif, struct pbuf *p);\r
+static struct pbuf *low_level_input(struct netif *netif);\r
+static void ethernetif_input( void *pParams );\r
+\r
+/* Functions adapted from Freescale provided code. */\r
+static int fec_mii_write( int phy_addr, int reg_addr, int data );\r
+static int fec_mii_read( int phy_addr, int reg_addr, uint16* data );\r
+static uint8 fec_hash_address( const uint8* addr );\r
+static void fec_set_address( const uint8 *pa );\r
+static void fec_irq_enable( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/********************************************************************/\r
+/*\r
+ * Write a value to a PHY's MII register.\r
+ *\r
+ * Parameters:\r
+ * ch FEC channel\r
+ * phy_addr Address of the PHY.\r
+ * reg_addr Address of the register in the PHY.\r
+ * data Data to be written to the PHY register.\r
+ *\r
+ * Return Values:\r
+ * 0 on failure\r
+ * 1 on success.\r
+ *\r
+ * Please refer to your PHY manual for registers and their meanings.\r
+ * mii_write() polls for the FEC's MII interrupt event and clears it. \r
+ * If after a suitable amount of time the event isn't triggered, a \r
+ * value of 0 is returned.\r
+ */\r
+static int fec_mii_write( int phy_addr, int reg_addr, int data )\r
+{\r
+int timeout;\r
+uint32 eimr;\r
+\r
+ /* Clear the MII interrupt bit */\r
+ MCF_FEC_EIR = MCF_FEC_EIR_MII;\r
+\r
+ /* Mask the MII interrupt */\r
+ eimr = MCF_FEC_EIMR;\r
+ MCF_FEC_EIMR &= ~MCF_FEC_EIMR_MII;\r
+\r
+ /* Write to the MII Management Frame Register to kick-off the MII write */\r
+ MCF_FEC_MMFR = MCF_FEC_MMFR_ST_01 | MCF_FEC_MMFR_OP_WRITE | MCF_FEC_MMFR_PA(phy_addr) | MCF_FEC_MMFR_RA(reg_addr) | MCF_FEC_MMFR_TA_10 | MCF_FEC_MMFR_DATA( data );\r
+\r
+ /* Poll for the MII interrupt (interrupt should be masked) */\r
+ for (timeout = 0; timeout < MII_TIMEOUT; timeout++)\r
+ {\r
+ if (MCF_FEC_EIR & MCF_FEC_EIR_MII)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ if( timeout == MII_TIMEOUT )\r
+ {\r
+ return 0;\r
+ }\r
+\r
+ /* Clear the MII interrupt bit */\r
+ MCF_FEC_EIR = MCF_FEC_EIR_MII;\r
+\r
+ /* Restore the EIMR */\r
+ MCF_FEC_EIMR = eimr;\r
+\r
+ return 1;\r
+}\r
+\r
+/********************************************************************/\r
+/*\r
+ * Read a value from a PHY's MII register.\r
+ *\r
+ * Parameters:\r
+ * ch FEC channel\r
+ * phy_addr Address of the PHY.\r
+ * reg_addr Address of the register in the PHY.\r
+ * data Pointer to storage for the Data to be read\r
+ * from the PHY register (passed by reference)\r
+ *\r
+ * Return Values:\r
+ * 0 on failure\r
+ * 1 on success.\r
+ *\r
+ * Please refer to your PHY manual for registers and their meanings.\r
+ * mii_read() polls for the FEC's MII interrupt event and clears it. \r
+ * If after a suitable amount of time the event isn't triggered, a \r
+ * value of 0 is returned.\r
+ */\r
+static int fec_mii_read( int phy_addr, int reg_addr, uint16* data )\r
+{\r
+int timeout;\r
+uint32 eimr;\r
+\r
+ /* Clear the MII interrupt bit */\r
+ MCF_FEC_EIR = MCF_FEC_EIR_MII;\r
+\r
+ /* Mask the MII interrupt */\r
+ eimr = MCF_FEC_EIMR;\r
+ MCF_FEC_EIMR &= ~MCF_FEC_EIMR_MII;\r
+\r
+ /* Write to the MII Management Frame Register to kick-off the MII read */\r
+ MCF_FEC_MMFR = MCF_FEC_MMFR_ST_01 | MCF_FEC_MMFR_OP_READ | MCF_FEC_MMFR_PA(phy_addr) | MCF_FEC_MMFR_RA(reg_addr) | MCF_FEC_MMFR_TA_10;\r
+\r
+ /* Poll for the MII interrupt (interrupt should be masked) */\r
+ for (timeout = 0; timeout < MII_TIMEOUT; timeout++)\r
+ {\r
+ if (MCF_FEC_EIR & MCF_FEC_EIR_MII)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ if(timeout == MII_TIMEOUT)\r
+ {\r
+ return 0;\r
+ }\r
+\r
+ /* Clear the MII interrupt bit */\r
+ MCF_FEC_EIR = MCF_FEC_EIR_MII;\r
+\r
+ /* Restore the EIMR */\r
+ MCF_FEC_EIMR = eimr;\r
+\r
+ *data = (uint16)(MCF_FEC_MMFR & 0x0000FFFF);\r
+\r
+ return 1;\r
+}\r
+\r
+\r
+/********************************************************************/\r
+/*\r
+ * Generate the hash table settings for the given address\r
+ *\r
+ * Parameters:\r
+ * addr 48-bit (6 byte) Address to generate the hash for\r
+ *\r
+ * Return Value:\r
+ * The 6 most significant bits of the 32-bit CRC result\r
+ */\r
+static uint8 fec_hash_address( const uint8* addr )\r
+{\r
+uint32 crc;\r
+uint8 byte;\r
+int i, j;\r
+\r
+ crc = 0xFFFFFFFF;\r
+ for(i=0; i<6; ++i)\r
+ {\r
+ byte = addr[i];\r
+ for(j=0; j<8; ++j)\r
+ {\r
+ if((byte & 0x01)^(crc & 0x01))\r
+ {\r
+ crc >>= 1;\r
+ crc = crc ^ 0xEDB88320;\r
+ }\r
+ else\r
+ {\r
+ crc >>= 1;\r
+ }\r
+\r
+ byte >>= 1;\r
+ }\r
+ }\r
+\r
+ return (uint8)(crc >> 26);\r
+}\r
+\r
+/********************************************************************/\r
+/*\r
+ * Set the Physical (Hardware) Address and the Individual Address\r
+ * Hash in the selected FEC\r
+ *\r
+ * Parameters:\r
+ * ch FEC channel\r
+ * pa Physical (Hardware) Address for the selected FEC\r
+ */\r
+static void fec_set_address( const uint8 *pa )\r
+{\r
+ uint8 crc;\r
+\r
+ /*\r
+ * Set the Physical Address\r
+ */\r
+ MCF_FEC_PALR = (uint32)((pa[0]<<24) | (pa[1]<<16) | (pa[2]<<8) | pa[3]);\r
+ MCF_FEC_PAUR = (uint32)((pa[4]<<24) | (pa[5]<<16));\r
+\r
+ /*\r
+ * Calculate and set the hash for given Physical Address\r
+ * in the Individual Address Hash registers\r
+ */\r
+ crc = fec_hash_address(pa);\r
+ if(crc >= 32)\r
+ {\r
+ MCF_FEC_IAUR |= (uint32)(1 << (crc - 32));\r
+ }\r
+ else\r
+ {\r
+ MCF_FEC_IALR |= (uint32)(1 << crc);\r
+ }\r
+}\r
+\r
+\r
+/********************************************************************/\r
+/*\r
+ * Enable interrupts on the selected FEC\r
+ *\r
+ */\r
+static void fec_irq_enable( void )\r
+{\r
+int fec_vbase;\r
+\r
+#if INTC_LVL_FEC > configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+ #error INTC_LVL_FEC must be less than or equal to configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+#endif\r
+\r
+ fec_vbase = 64 + netifFIRST_FEC_VECTOR;\r
+ \r
+ /* Enable FEC interrupts to the ColdFire core \r
+ * Setup each ICR with a unique interrupt level combination */\r
+ fec_vbase -= 64;\r
+\r
+ /* FEC Rx Frame */\r
+ MCF_INTC0_ICR(fec_vbase+4) = MCF_INTC_ICR_IL(INTC_LVL_FEC);\r
+\r
+ /* FEC Rx Buffer */ \r
+ MCF_INTC0_ICR(fec_vbase+5) = MCF_INTC_ICR_IL(INTC_LVL_FEC);\r
+\r
+ /* FEC FIFO Underrun */ \r
+ MCF_INTC0_ICR(fec_vbase+2) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);\r
+\r
+ /* FEC Collision Retry Limit */ \r
+ MCF_INTC0_ICR(fec_vbase+3) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);\r
+\r
+ /* FEC Late Collision */ \r
+ MCF_INTC0_ICR(fec_vbase+7) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);\r
+\r
+ /* FEC Heartbeat Error */ \r
+ MCF_INTC0_ICR(fec_vbase+8) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);\r
+\r
+ /* FEC Bus Error */ \r
+ MCF_INTC0_ICR(fec_vbase+10) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);\r
+\r
+ /* FEC Babbling Transmit */ \r
+ MCF_INTC0_ICR(fec_vbase+11) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);\r
+\r
+ /* FEC Babbling Receive */ \r
+ MCF_INTC0_ICR(fec_vbase+12) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1);\r
+ \r
+ /* Enable the FEC interrupts in the mask register */ \r
+ MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK33 | MCF_INTC_IMRH_INT_MASK34 | MCF_INTC_IMRH_INT_MASK35 );\r
+ MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK25 | MCF_INTC_IMRL_INT_MASK26 | MCF_INTC_IMRL_INT_MASK27 | MCF_INTC_IMRL_INT_MASK28 | MCF_INTC_IMRL_INT_MASK29 | MCF_INTC_IMRL_INT_MASK30 | MCF_INTC_IMRL_INT_MASK31 | MCF_INTC_IMRL_MASKALL );\r
+\r
+ /* Clear any pending FEC interrupt events */\r
+ MCF_FEC_EIR = MCF_FEC_EIR_CLEAR_ALL;\r
+\r
+ /* Unmask all FEC interrupts */\r
+ MCF_FEC_EIMR = MCF_FEC_EIMR_UNMASK_ALL;\r
+}\r
+\r
+/**\r
+ * In this function, the hardware should be initialized.\r
+ * Called from ethernetif_init().\r
+ *\r
+ * @param netif the already initialized lwip network interface structure\r
+ * for this ethernetif\r
+ */\r
+static void low_level_init( struct netif *netif )\r
+{\r
+unsigned portSHORT usData;\r
+const unsigned portCHAR ucMACAddress[6] = \r
+{\r
+ configMAC_0, configMAC_1,configMAC_2,configMAC_3,configMAC_4,configMAC_5\r
+};\r
+\r
+ prvInitialiseFECBuffers();\r
+ vSemaphoreCreateBinary( xFecSemaphore );\r
+ \r
+ for( usData = 0; usData < 6; usData++ )\r
+ {\r
+ netif->hwaddr[ usData ] = ucMACAddress[ usData ];\r
+ }\r
+\r
+ /* Set the Reset bit and clear the Enable bit */\r
+ MCF_FEC_ECR = MCF_FEC_ECR_RESET;\r
+\r
+ /* Wait at least 8 clock cycles */\r
+ for( usData = 0; usData < 10; usData++ )\r
+ {\r
+ asm( "NOP" );\r
+ }\r
+\r
+ /* Set MII speed to 2.5MHz. */\r
+ MCF_FEC_MSCR = MCF_FEC_MSCR_MII_SPEED( ( ( configCPU_CLOCK_HZ / 1000000 ) / 5 ) + 1 );\r
+\r
+ /*\r
+ * Make sure the external interface signals are enabled\r
+ */\r
+ MCF_GPIO_PNQPAR = MCF_GPIO_PNQPAR_IRQ3_FEC_MDIO | MCF_GPIO_PNQPAR_IRQ5_FEC_MDC;\r
+\r
+\r
+ MCF_GPIO_PTIPAR = MCF_GPIO_PTIPAR_FEC_COL_FEC_COL \r
+ | MCF_GPIO_PTIPAR_FEC_CRS_FEC_CRS \r
+ | MCF_GPIO_PTIPAR_FEC_RXCLK_FEC_RXCLK \r
+ | MCF_GPIO_PTIPAR_FEC_RXD0_FEC_RXD0 \r
+ | MCF_GPIO_PTIPAR_FEC_RXD1_FEC_RXD1 \r
+ | MCF_GPIO_PTIPAR_FEC_RXD2_FEC_RXD2 \r
+ | MCF_GPIO_PTIPAR_FEC_RXD3_FEC_RXD3 \r
+ | MCF_GPIO_PTIPAR_FEC_RXDV_FEC_RXDV; \r
+\r
+ MCF_GPIO_PTJPAR = MCF_GPIO_PTJPAR_FEC_RXER_FEC_RXER \r
+ | MCF_GPIO_PTJPAR_FEC_TXCLK_FEC_TXCLK \r
+ | MCF_GPIO_PTJPAR_FEC_TXD0_FEC_TXD0 \r
+ | MCF_GPIO_PTJPAR_FEC_TXD1_FEC_TXD1 \r
+ | MCF_GPIO_PTJPAR_FEC_TXD2_FEC_TXD2 \r
+ | MCF_GPIO_PTJPAR_FEC_TXD3_FEC_TXD3 \r
+ | MCF_GPIO_PTJPAR_FEC_TXEN_FEC_TXEN \r
+ | MCF_GPIO_PTJPAR_FEC_TXER_FEC_TXER; \r
+\r
+\r
+ /* Can we talk to the PHY? */\r
+ do\r
+ {\r
+ vTaskDelay( netifLINK_DELAY );\r
+ usData = 0;\r
+ fec_mii_read( configPHY_ADDRESS, PHY_PHYIDR1, &usData );\r
+\r
+ } while( ( usData == 0xffff ) || ( usData == 0 ) );\r
+\r
+ /* Start auto negotiate. */\r
+ fec_mii_write( configPHY_ADDRESS, PHY_BMCR, ( PHY_BMCR_AN_RESTART | PHY_BMCR_AN_ENABLE ) );\r
+\r
+ /* Wait for auto negotiate to complete. */\r
+ do\r
+ {\r
+ vTaskDelay( netifLINK_DELAY );\r
+ fec_mii_read( configPHY_ADDRESS, PHY_BMSR, &usData );\r
+\r
+ } while( !( usData & PHY_BMSR_AN_COMPLETE ) );\r
+\r
+ /* When we get here we have a link - find out what has been negotiated. */\r
+ fec_mii_read( configPHY_ADDRESS, PHY_ANLPAR, &usData );\r
+ \r
+ if( ( usData & PHY_ANLPAR_100BTX_FDX ) || ( usData & PHY_ANLPAR_100BTX ) )\r
+ {\r
+ /* Speed is 100. */\r
+ }\r
+ else\r
+ {\r
+ /* Speed is 10. */\r
+ }\r
+\r
+ if( ( usData & PHY_ANLPAR_100BTX_FDX ) || ( usData & PHY_ANLPAR_10BTX_FDX ) )\r
+ {\r
+ /* Full duplex. */\r
+ MCF_FEC_RCR &= (uint32)~MCF_FEC_RCR_DRT;\r
+ MCF_FEC_TCR |= MCF_FEC_TCR_FDEN;\r
+ }\r
+ else\r
+ {\r
+ MCF_FEC_RCR |= MCF_FEC_RCR_DRT;\r
+ MCF_FEC_TCR &= (uint32)~MCF_FEC_TCR_FDEN;\r
+ }\r
+ \r
+ /* Clear the Individual and Group Address Hash registers */\r
+ MCF_FEC_IALR = 0;\r
+ MCF_FEC_IAUR = 0;\r
+ MCF_FEC_GALR = 0;\r
+ MCF_FEC_GAUR = 0;\r
+\r
+ /* Set the Physical Address for the selected FEC */\r
+ fec_set_address( ucMACAddress );\r
+\r
+ /* Set Rx Buffer Size */\r
+ MCF_FEC_EMRBR = (uint16)configFEC_BUFFER_SIZE;\r
+\r
+ /* Point to the start of the circular Rx buffer descriptor queue */\r
+ MCF_FEC_ERDSR = ( volatile unsigned portLONG ) &( xFECRxDescriptors[ 0 ] );\r
+\r
+ /* Point to the start of the circular Tx buffer descriptor queue */\r
+ MCF_FEC_ETSDR = ( volatile unsigned portLONG ) &( xFECTxDescriptors[ 0 ] );\r
+\r
+ /* Mask all FEC interrupts */\r
+ MCF_FEC_EIMR = MCF_FEC_EIMR_MASK_ALL;\r
+\r
+ /* Clear all FEC interrupt events */\r
+ MCF_FEC_EIR = MCF_FEC_EIR_CLEAR_ALL;\r
+\r
+ /* Initialize the Receive Control Register */\r
+ MCF_FEC_RCR = MCF_FEC_RCR_MAX_FL(ETH_MAX_FRM) | MCF_FEC_RCR_FCE;\r
+\r
+ MCF_FEC_RCR |= MCF_FEC_RCR_MII_MODE;\r
+\r
+ #if( configUSE_PROMISCUOUS_MODE == 1 )\r
+ {\r
+ MCF_FEC_RCR |= MCF_FEC_RCR_PROM;\r
+ }\r
+ #endif\r
+\r
+ /* Create the task that handles the EMAC. */\r
+ xTaskCreate( ethernetif_input, ( signed portCHAR * ) "ETH_INT", configETHERNET_INPUT_TASK_STACK_SIZE, (void *)netif, configETHERNET_INPUT_TASK_PRIORITY, &xEthIntTask );\r
+ \r
+ fec_irq_enable();\r
+ MCF_FEC_ECR = MCF_FEC_ECR_ETHER_EN;\r
+ MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE; \r
+}\r
+\r
+/**\r
+ * This function should do the actual transmission of the packet. The packet is\r
+ * contained in the pbuf that is passed to the function. This pbuf\r
+ * might be chained.\r
+ *\r
+ * @param netif the lwip network interface structure for this ethernetif\r
+ * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)\r
+ * @return ERR_OK if the packet could be sent\r
+ * an err_t value if the packet couldn't be sent\r
+ *\r
+ * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to\r
+ * strange results. You might consider waiting for space in the DMA queue\r
+ * to become availale since the stack doesn't retry to send a packet\r
+ * dropped because of memory failure (except for the TCP timers).\r
+ */\r
+static err_t low_level_output(struct netif *netif, struct pbuf *p)\r
+{\r
+struct pbuf *q;\r
+u32_t l = 0;\r
+unsigned portCHAR *pcTxData = NULL;\r
+portBASE_TYPE i;\r
+\r
+ ( void ) netif;\r
+\r
+ #if ETH_PAD_SIZE\r
+ pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */\r
+ #endif\r
+\r
+ /* Get a DMA buffer into which we can write the data to send. */\r
+ for( i = 0; i < netifBUFFER_WAIT_ATTEMPTS; i++ )\r
+ {\r
+ if( xFECTxDescriptors[ uxNextTxBuffer ].status & TX_BD_R )\r
+ {\r
+ /* Wait for the buffer to become available. */\r
+ vTaskDelay( netifBUFFER_WAIT_DELAY );\r
+ }\r
+ else\r
+ {\r
+ pcTxData = xFECTxDescriptors[ uxNextTxBuffer ].data;\r
+ break;\r
+ }\r
+ }\r
+\r
+ if( pcTxData == NULL ) \r
+ {\r
+ /* For break point only. */\r
+ portNOP();\r
+\r
+ return ERR_BUF;\r
+ }\r
+ else \r
+ {\r
+ for( q = p; q != NULL; q = q->next ) \r
+ {\r
+ /* Send the data from the pbuf to the interface, one pbuf at a\r
+ time. The size of the data in each pbuf is kept in the ->len\r
+ variable. */\r
+ memcpy( &pcTxData[l], (u8_t*)q->payload, q->len );\r
+ l += q->len;\r
+ }\r
+ }\r
+\r
+ /* Setup the buffer descriptor for transmission */\r
+ xFECTxDescriptors[ uxNextTxBuffer ].length = l;//nbuf->length + ETH_HDR_LEN;\r
+ xFECTxDescriptors[ uxNextTxBuffer ].status |= (TX_BD_R | TX_BD_L);\r
+\r
+ /* Continue the Tx DMA task (in case it was waiting for a new TxBD) */\r
+ MCF_FEC_TDAR = MCF_FEC_TDAR_X_DES_ACTIVE;\r
+\r
+ uxNextTxBuffer++;\r
+ if( uxNextTxBuffer >= configNUM_FEC_TX_BUFFERS )\r
+ {\r
+ uxNextTxBuffer = 0;\r
+ }\r
+\r
+ #if ETH_PAD_SIZE\r
+ pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */\r
+ #endif\r
+\r
+ LINK_STATS_INC(link.xmit);\r
+\r
+ return ERR_OK;\r
+}\r
+\r
+/**\r
+ * Should allocate a pbuf and transfer the bytes of the incoming\r
+ * packet from the interface into the pbuf.\r
+ *\r
+ * @param netif the lwip network interface structure for this ethernetif\r
+ * @return a pbuf filled with the received packet (including MAC header)\r
+ * NULL on memory error\r
+ */\r
+static struct pbuf *low_level_input(struct netif *netif)\r
+{\r
+struct pbuf *p, *q;\r
+u16_t len, l;\r
+\r
+ ( void ) netif;\r
+\r
+ l = 0;\r
+ p = NULL;\r
+\r
+ /* Obtain the size of the packet and put it into the "len" variable. */\r
+ len = xFECRxDescriptors[ uxNextRxBuffer ].length;\r
+\r
+ if( ( len != 0 ) && ( ( xFECRxDescriptors[ uxNextRxBuffer ].status & RX_BD_E ) == 0 ) )\r
+ {\r
+ #if ETH_PAD_SIZE\r
+ len += ETH_PAD_SIZE; /* allow room for Ethernet padding */\r
+ #endif\r
+\r
+ /* We allocate a pbuf chain of pbufs from the pool. */\r
+ p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);\r
+\r
+ if (p != NULL) \r
+ {\r
+\r
+ #if ETH_PAD_SIZE\r
+ pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */\r
+ #endif\r
+\r
+ /* We iterate over the pbuf chain until we have read the entire\r
+ * packet into the pbuf. */\r
+ for(q = p; q != NULL; q = q->next) \r
+ {\r
+ /* Read enough bytes to fill this pbuf in the chain. The\r
+ * available data in the pbuf is given by the q->len\r
+ * variable. */\r
+ memcpy((u8_t*)q->payload, &(xFECRxDescriptors[ uxNextRxBuffer ].data[l]), q->len);\r
+ l = l + q->len;\r
+ }\r
+\r
+\r
+ #if ETH_PAD_SIZE\r
+ pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */\r
+ #endif\r
+\r
+ LINK_STATS_INC(link.recv);\r
+\r
+ } \r
+ else \r
+ {\r
+\r
+ LINK_STATS_INC(link.memerr);\r
+ LINK_STATS_INC(link.drop);\r
+\r
+ } /* End else */\r
+ \r
+ \r
+ /* Free the descriptor. */\r
+ xFECRxDescriptors[ uxNextRxBuffer ].status |= RX_BD_E;\r
+ MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;\r
+ \r
+ uxNextRxBuffer++;\r
+ if( uxNextRxBuffer >= configNUM_FEC_RX_BUFFERS )\r
+ {\r
+ uxNextRxBuffer = 0;\r
+ } \r
+ \r
+ } /* End if */\r
+\r
+ return p;\r
+}\r
+\r
+/**\r
+ * This function should be called when a packet is ready to be read\r
+ * from the interface. It uses the function low_level_input() that\r
+ * should handle the actual reception of bytes from the network\r
+ * interface.Then the type of the received packet is determined and\r
+ * the appropriate input function is called.\r
+ *\r
+ * @param netif the lwip network interface structure for this ethernetif\r
+ */\r
+\r
+static void ethernetif_input( void *pParams )\r
+{\r
+struct netif *netif;\r
+struct ethernetif *ethernetif;\r
+struct eth_hdr *ethhdr;\r
+struct pbuf *p;\r
+\r
+ netif = (struct netif*) pParams;\r
+ ethernetif = netif->state;\r
+\r
+ for( ;; )\r
+ {\r
+ do\r
+ {\r
+\r
+ /* move received packet into a new pbuf */\r
+ p = low_level_input( netif );\r
+\r
+ if( p == NULL )\r
+ {\r
+ /* No packet could be read. Wait a for an interrupt to tell us\r
+ there is more data available. */\r
+ xSemaphoreTake( xFecSemaphore, netifBLOCK_TIME_WAITING_FOR_INPUT );\r
+ }\r
+\r
+ } while( p == NULL );\r
+\r
+ /* points to packet payload, which starts with an Ethernet header */\r
+ ethhdr = p->payload;\r
+\r
+ switch (htons(ethhdr->type)) {\r
+ /* IP or ARP packet? */\r
+\r
+ case ETHTYPE_IP:\r
+\r
+ pbuf_header( p, (s16_t)-sizeof(struct eth_hdr) );\r
+\r
+ /* full packet send to tcpip_thread to process */\r
+ if (netif->input(p, netif) != ERR_OK)\r
+ {\r
+ LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n"));\r
+ pbuf_free(p);\r
+ p = NULL;\r
+ }\r
+ break;\r
+\r
+ case ETHTYPE_ARP:\r
+\r
+ #if ETHARP_TRUST_IP_MAC\r
+ etharp_ip_input(netif, p);\r
+ #endif\r
+\r
+ etharp_arp_input(netif, ethernetif->ethaddr, p);\r
+ break;\r
+\r
+ default:\r
+ pbuf_free(p);\r
+ p = NULL;\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * Should be called at the beginning of the program to set up the\r
+ * network interface. It calls the function low_level_init() to do the\r
+ * actual setup of the hardware.\r
+ *\r
+ * This function should be passed as a parameter to netif_add().\r
+ *\r
+ * @param netif the lwip network interface structure for this ethernetif\r
+ * @return ERR_OK if the loopif is initialized\r
+ * ERR_MEM if private data couldn't be allocated\r
+ * any other err_t on error\r
+ */\r
+err_t ethernetif_init(struct netif *netif)\r
+{\r
+ struct ethernetif *ethernetif;\r
+\r
+ LWIP_ASSERT("netif != NULL", (netif != NULL));\r
+\r
+ ethernetif = mem_malloc(sizeof(struct ethernetif));\r
+\r
+ if (ethernetif == NULL)\r
+ {\r
+ LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));\r
+ return ERR_MEM;\r
+ }\r
+\r
+ #if LWIP_NETIF_HOSTNAME\r
+ /* Initialize interface hostname */\r
+ netif->hostname = "lwip";\r
+ #endif /* LWIP_NETIF_HOSTNAME */\r
+\r
+ /*\r
+ * Initialize the snmp variables and counters inside the struct netif.\r
+ * The last argument should be replaced with your link speed, in units\r
+ * of bits per second.\r
+ */\r
+ NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 100);\r
+\r
+ netif->state = ethernetif;\r
+ netif->name[0] = IFNAME0;\r
+ netif->name[1] = IFNAME1;\r
+\r
+ /* We directly use etharp_output() here to save a function call.\r
+ * You can instead declare your own function an call etharp_output()\r
+ * from it if you have to do some checks before sending (e.g. if link\r
+ * is available...)\r
+ */\r
+ netif->output = etharp_output;\r
+ netif->linkoutput = low_level_output;\r
+\r
+ ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]);\r
+\r
+ low_level_init(netif);\r
+\r
+ return ERR_OK;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvInitialiseFECBuffers( void )\r
+{\r
+unsigned portBASE_TYPE ux;\r
+unsigned portCHAR *pcBufPointer;\r
+\r
+ pcBufPointer = &( xFECTxDescriptors_unaligned[ 0 ] );\r
+ while( ( ( unsigned portLONG ) pcBufPointer & 0x0fUL ) != 0 )\r
+ {\r
+ pcBufPointer++;\r
+ }\r
+ \r
+ xFECTxDescriptors = ( FECBD * ) pcBufPointer;\r
+ \r
+ pcBufPointer = &( xFECRxDescriptors_unaligned[ 0 ] );\r
+ while( ( ( unsigned portLONG ) pcBufPointer & 0x0fUL ) != 0 )\r
+ {\r
+ pcBufPointer++;\r
+ }\r
+ \r
+ xFECRxDescriptors = ( FECBD * ) pcBufPointer;\r
+\r
+\r
+ /* Setup the buffers and descriptors. */\r
+ pcBufPointer = &( ucFECTxBuffers[ 0 ] );\r
+ while( ( ( unsigned portLONG ) pcBufPointer & 0x0fUL ) != 0 )\r
+ {\r
+ pcBufPointer++;\r
+ }\r
+\r
+ for( ux = 0; ux < configNUM_FEC_TX_BUFFERS; ux++ )\r
+ {\r
+ xFECTxDescriptors[ ux ].status = TX_BD_TC;\r
+ xFECTxDescriptors[ ux ].data = pcBufPointer;\r
+ pcBufPointer += configFEC_BUFFER_SIZE;\r
+ xFECTxDescriptors[ ux ].length = 0;\r
+ }\r
+\r
+ pcBufPointer = &( ucFECRxBuffers[ 0 ] );\r
+ while( ( ( unsigned portLONG ) pcBufPointer & 0x0fUL ) != 0 )\r
+ {\r
+ pcBufPointer++;\r
+ }\r
+ \r
+ for( ux = 0; ux < configNUM_FEC_RX_BUFFERS; ux++ )\r
+ {\r
+ xFECRxDescriptors[ ux ].status = RX_BD_E;\r
+ xFECRxDescriptors[ ux ].length = configFEC_BUFFER_SIZE;\r
+ xFECRxDescriptors[ ux ].data = pcBufPointer;\r
+ pcBufPointer += configFEC_BUFFER_SIZE;\r
+ }\r
+\r
+ /* Set the wrap bit in the last descriptors to form a ring. */\r
+ xFECTxDescriptors[ configNUM_FEC_TX_BUFFERS - 1 ].status |= TX_BD_W;\r
+ xFECRxDescriptors[ configNUM_FEC_RX_BUFFERS - 1 ].status |= RX_BD_W;\r
+\r
+ uxNextRxBuffer = 0;\r
+ uxNextTxBuffer = 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__declspec(interrupt:0) void vFECISRHandler( void )\r
+{\r
+unsigned portLONG ulEvent;\r
+portBASE_TYPE xHighPriorityTaskWoken = pdFALSE;\r
+ \r
+ ulEvent = MCF_FEC_EIR & MCF_FEC_EIMR;\r
+ MCF_FEC_EIR = ulEvent;\r
+\r
+ if( ( ulEvent & MCF_FEC_EIR_RXB ) || ( ulEvent & MCF_FEC_EIR_RXF ) )\r
+ {\r
+ /* A packet has been received. Wake the handler task. */\r
+ xSemaphoreGiveFromISR( xFecSemaphore, &xHighPriorityTaskWoken );\r
+ }\r
+\r
+ if (ulEvent & ( MCF_FEC_EIR_UN | MCF_FEC_EIR_RL | MCF_FEC_EIR_LC | MCF_FEC_EIR_EBERR | MCF_FEC_EIR_BABT | MCF_FEC_EIR_BABR | MCF_FEC_EIR_HBERR ) )\r
+ {\r
+ /* Sledge hammer error handling. */\r
+ prvInitialiseFECBuffers();\r
+ MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;\r
+ }\r
+\r
+ portEND_SWITCHING_ISR( xHighPriorityTaskWoken );\r
+}\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_H__\r
+#define __MCF52235_H__\r
+\r
+//#include "common.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+typedef unsigned char uint8; /* 8 bits */\r
+typedef unsigned short int uint16; /* 16 bits */\r
+typedef unsigned long int uint32; /* 32 bits */\r
+\r
+typedef signed char int8; /* 8 bits */\r
+typedef signed short int int16; /* 16 bits */\r
+typedef signed long int int32; /* 32 bits */\r
+\r
+typedef volatile uint8 vuint8; /* 8 bits */\r
+typedef volatile uint16 vuint16; /* 16 bits */\r
+typedef volatile uint32 vuint32; /* 32 bits */\r
+\r
+#ifdef THESE_ARE_CODEWARRIOR_DEFINITIONS\r
+#pragma define_section system ".system" far_absolute RW\r
+\r
+/***\r
+ * MCF52235 Derivative Memory map definitions from linker command files:\r
+ * __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker\r
+ * symbols must be defined in the linker command file.\r
+ */\r
+\r
+ extern __declspec(system) uint8 __IPSBAR[];\r
+ extern __declspec(system) uint8 __RAMBAR[];\r
+ extern __declspec(system) uint8 __RAMBAR_SIZE[];\r
+ extern __declspec(system) uint8 __FLASHBAR[];\r
+ extern __declspec(system) uint8 __FLASHBAR_SIZE[];\r
+#endif\r
+\r
+#define __IPSBAR ( ( uint8 * ) 0x40000000 )\r
+#define __RAMBAR ( ( uint8 * ) 0x20000000 )\r
+\r
+#define IPSBAR_ADDRESS (uint32)__IPSBAR\r
+#define RAMBAR_ADDRESS (uint32)__RAMBAR\r
+#define RAMBAR_SIZE (uint32)__RAMBAR_SIZE\r
+#define FLASHBAR_ADDRESS (uint32)__FLASHBAR\r
+#define FLASHBAR_SIZE (uint32)__FLASHBAR_SIZE\r
+\r
+\r
+#include "MCF52235_SCM.h"\r
+#include "MCF52235_DMA.h"\r
+#include "MCF52235_UART.h"\r
+#include "MCF52235_I2C.h"\r
+#include "MCF52235_QSPI.h"\r
+#include "MCF52235_RTC.h"\r
+#include "MCF52235_DTIM.h"\r
+#include "MCF52235_INTC.h"\r
+#include "MCF52235_GIACR.h"\r
+#include "MCF52235_FEC.h"\r
+#include "MCF52235_GPIO.h"\r
+#include "MCF52235_PAD.h"\r
+#include "MCF52235_RCM.h"\r
+#include "MCF52235_CCM.h"\r
+#include "MCF52235_PMM.h"\r
+#include "MCF52235_CLOCK.h"\r
+#include "MCF52235_EPORT.h"\r
+#include "MCF52235_PIT.h"\r
+#include "MCF52235_ADC.h"\r
+#include "MCF52235_GPTA.h"\r
+#include "MCF52235_PWM.h"\r
+#include "MCF52235_FlexCAN.h"\r
+#include "MCF52235_CFM.h"\r
+#include "MCF52235_EPHY.h"\r
+#include "MCF52235_RNGA.h"\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __MCF52235_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_ADC_H__\r
+#define __MCF52235_ADC_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Analog-to-Digital Converter (ADC)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_ADC_CTRL1 (*(vuint16*)(&__IPSBAR[0x190000]))\r
+#define MCF_ADC_CTRL2 (*(vuint16*)(&__IPSBAR[0x190002]))\r
+#define MCF_ADC_ADZCC (*(vuint16*)(&__IPSBAR[0x190004]))\r
+#define MCF_ADC_ADLST1 (*(vuint16*)(&__IPSBAR[0x190006]))\r
+#define MCF_ADC_ADLST2 (*(vuint16*)(&__IPSBAR[0x190008]))\r
+#define MCF_ADC_ADSDIS (*(vuint16*)(&__IPSBAR[0x19000A]))\r
+#define MCF_ADC_ADSTAT (*(vuint16*)(&__IPSBAR[0x19000C]))\r
+#define MCF_ADC_ADLSTAT (*(vuint16*)(&__IPSBAR[0x19000E]))\r
+#define MCF_ADC_ADZCSTAT (*(vuint16*)(&__IPSBAR[0x190010]))\r
+#define MCF_ADC_ADRSLT0 (*(vuint16*)(&__IPSBAR[0x190012]))\r
+#define MCF_ADC_ADRSLT1 (*(vuint16*)(&__IPSBAR[0x190014]))\r
+#define MCF_ADC_ADRSLT2 (*(vuint16*)(&__IPSBAR[0x190016]))\r
+#define MCF_ADC_ADRSLT3 (*(vuint16*)(&__IPSBAR[0x190018]))\r
+#define MCF_ADC_ADRSLT4 (*(vuint16*)(&__IPSBAR[0x19001A]))\r
+#define MCF_ADC_ADRSLT5 (*(vuint16*)(&__IPSBAR[0x19001C]))\r
+#define MCF_ADC_ADRSLT6 (*(vuint16*)(&__IPSBAR[0x19001E]))\r
+#define MCF_ADC_ADRSLT7 (*(vuint16*)(&__IPSBAR[0x190020]))\r
+#define MCF_ADC_ADLLMT0 (*(vuint16*)(&__IPSBAR[0x190022]))\r
+#define MCF_ADC_ADLLMT1 (*(vuint16*)(&__IPSBAR[0x190024]))\r
+#define MCF_ADC_ADLLMT2 (*(vuint16*)(&__IPSBAR[0x190026]))\r
+#define MCF_ADC_ADLLMT3 (*(vuint16*)(&__IPSBAR[0x190028]))\r
+#define MCF_ADC_ADLLMT4 (*(vuint16*)(&__IPSBAR[0x19002A]))\r
+#define MCF_ADC_ADLLMT5 (*(vuint16*)(&__IPSBAR[0x19002C]))\r
+#define MCF_ADC_ADLLMT6 (*(vuint16*)(&__IPSBAR[0x19002E]))\r
+#define MCF_ADC_ADLLMT7 (*(vuint16*)(&__IPSBAR[0x190030]))\r
+#define MCF_ADC_ADHLMT0 (*(vuint16*)(&__IPSBAR[0x190032]))\r
+#define MCF_ADC_ADHLMT1 (*(vuint16*)(&__IPSBAR[0x190034]))\r
+#define MCF_ADC_ADHLMT2 (*(vuint16*)(&__IPSBAR[0x190036]))\r
+#define MCF_ADC_ADHLMT3 (*(vuint16*)(&__IPSBAR[0x190038]))\r
+#define MCF_ADC_ADHLMT4 (*(vuint16*)(&__IPSBAR[0x19003A]))\r
+#define MCF_ADC_ADHLMT5 (*(vuint16*)(&__IPSBAR[0x19003C]))\r
+#define MCF_ADC_ADHLMT6 (*(vuint16*)(&__IPSBAR[0x19003E]))\r
+#define MCF_ADC_ADHLMT7 (*(vuint16*)(&__IPSBAR[0x190040]))\r
+#define MCF_ADC_ADOFS0 (*(vuint16*)(&__IPSBAR[0x190042]))\r
+#define MCF_ADC_ADOFS1 (*(vuint16*)(&__IPSBAR[0x190044]))\r
+#define MCF_ADC_ADOFS2 (*(vuint16*)(&__IPSBAR[0x190046]))\r
+#define MCF_ADC_ADOFS3 (*(vuint16*)(&__IPSBAR[0x190048]))\r
+#define MCF_ADC_ADOFS4 (*(vuint16*)(&__IPSBAR[0x19004A]))\r
+#define MCF_ADC_ADOFS5 (*(vuint16*)(&__IPSBAR[0x19004C]))\r
+#define MCF_ADC_ADOFS6 (*(vuint16*)(&__IPSBAR[0x19004E]))\r
+#define MCF_ADC_ADOFS7 (*(vuint16*)(&__IPSBAR[0x190050]))\r
+#define MCF_ADC_POWER (*(vuint16*)(&__IPSBAR[0x190052]))\r
+#define MCF_ADC_CAL (*(vuint16*)(&__IPSBAR[0x190054]))\r
+#define MCF_ADC_ADRSLT(x) (*(vuint16*)(&__IPSBAR[0x190012 + ((x)*0x2)]))\r
+#define MCF_ADC_ADLLMT(x) (*(vuint16*)(&__IPSBAR[0x190022 + ((x)*0x2)]))\r
+#define MCF_ADC_ADHLMT(x) (*(vuint16*)(&__IPSBAR[0x190032 + ((x)*0x2)]))\r
+#define MCF_ADC_ADOFS(x) (*(vuint16*)(&__IPSBAR[0x190042 + ((x)*0x2)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_ADC_CTRL1 */\r
+#define MCF_ADC_CTRL1_SMODE(x) (((x)&0x7)<<0)\r
+#define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0xF)<<0x4)\r
+#define MCF_ADC_CTRL1_HLMTIE (0x100)\r
+#define MCF_ADC_CTRL1_LLMTIE (0x200)\r
+#define MCF_ADC_CTRL1_ZCIE (0x400)\r
+#define MCF_ADC_CTRL1_EOSIE0 (0x800)\r
+#define MCF_ADC_CTRL1_SYNC0 (0x1000)\r
+#define MCF_ADC_CTRL1_START0 (0x2000)\r
+#define MCF_ADC_CTRL1_STOP0 (0x4000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_CTRL2 */\r
+#define MCF_ADC_CTRL2_DIV(x) (((x)&0x1F)<<0)\r
+#define MCF_ADC_CTRL2_SIMULT (0x20)\r
+#define MCF_ADC_CTRL2_EOSIE1 (0x800)\r
+#define MCF_ADC_CTRL2_SYNC1 (0x1000)\r
+#define MCF_ADC_CTRL2_START1 (0x2000)\r
+#define MCF_ADC_CTRL2_STOP1 (0x4000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADZCC */\r
+#define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x3)<<0)\r
+#define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x3)<<0x2)\r
+#define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x3)<<0x4)\r
+#define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x3)<<0x6)\r
+#define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x3)<<0x8)\r
+#define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x3)<<0xA)\r
+#define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x3)<<0xC)\r
+#define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x3)<<0xE)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADLST1 */\r
+#define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x7)<<0)\r
+#define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x7)<<0x4)\r
+#define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x7)<<0x8)\r
+#define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x7)<<0xC)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADLST2 */\r
+#define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x7)<<0)\r
+#define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x7)<<0x4)\r
+#define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x7)<<0x8)\r
+#define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x7)<<0xC)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADSDIS */\r
+#define MCF_ADC_ADSDIS_DS0 (0x1)\r
+#define MCF_ADC_ADSDIS_DS1 (0x2)\r
+#define MCF_ADC_ADSDIS_DS2 (0x4)\r
+#define MCF_ADC_ADSDIS_DS3 (0x8)\r
+#define MCF_ADC_ADSDIS_DS4 (0x10)\r
+#define MCF_ADC_ADSDIS_DS5 (0x20)\r
+#define MCF_ADC_ADSDIS_DS6 (0x40)\r
+#define MCF_ADC_ADSDIS_DS7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADSTAT */\r
+#define MCF_ADC_ADSTAT_RDY0 (0x1)\r
+#define MCF_ADC_ADSTAT_RDY1 (0x2)\r
+#define MCF_ADC_ADSTAT_RDY2 (0x4)\r
+#define MCF_ADC_ADSTAT_RDY3 (0x8)\r
+#define MCF_ADC_ADSTAT_RDY4 (0x10)\r
+#define MCF_ADC_ADSTAT_RDY5 (0x20)\r
+#define MCF_ADC_ADSTAT_RDY6 (0x40)\r
+#define MCF_ADC_ADSTAT_RDY7 (0x80)\r
+#define MCF_ADC_ADSTAT_HLMTI (0x100)\r
+#define MCF_ADC_ADSTAT_LLMTI (0x200)\r
+#define MCF_ADC_ADSTAT_ZCI (0x400)\r
+#define MCF_ADC_ADSTAT_EOSI0 (0x800)\r
+#define MCF_ADC_ADSTAT_EOSI1 (0x1000)\r
+#define MCF_ADC_ADSTAT_CIP1 (0x4000)\r
+#define MCF_ADC_ADSTAT_CIP0 (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADLSTAT */\r
+#define MCF_ADC_ADLSTAT_LLS0 (0x1)\r
+#define MCF_ADC_ADLSTAT_LLS1 (0x2)\r
+#define MCF_ADC_ADLSTAT_LLS2 (0x4)\r
+#define MCF_ADC_ADLSTAT_LLS3 (0x8)\r
+#define MCF_ADC_ADLSTAT_LLS4 (0x10)\r
+#define MCF_ADC_ADLSTAT_LLS5 (0x20)\r
+#define MCF_ADC_ADLSTAT_LLS6 (0x40)\r
+#define MCF_ADC_ADLSTAT_LLS7 (0x80)\r
+#define MCF_ADC_ADLSTAT_HLS0 (0x100)\r
+#define MCF_ADC_ADLSTAT_HLS1 (0x200)\r
+#define MCF_ADC_ADLSTAT_HLS2 (0x400)\r
+#define MCF_ADC_ADLSTAT_HLS3 (0x800)\r
+#define MCF_ADC_ADLSTAT_HLS4 (0x1000)\r
+#define MCF_ADC_ADLSTAT_HLS5 (0x2000)\r
+#define MCF_ADC_ADLSTAT_HLS6 (0x4000)\r
+#define MCF_ADC_ADLSTAT_HLS7 (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADZCSTAT */\r
+#define MCF_ADC_ADZCSTAT_ZCS0 (0x1)\r
+#define MCF_ADC_ADZCSTAT_ZCS1 (0x2)\r
+#define MCF_ADC_ADZCSTAT_ZCS2 (0x4)\r
+#define MCF_ADC_ADZCSTAT_ZCS3 (0x8)\r
+#define MCF_ADC_ADZCSTAT_ZCS4 (0x10)\r
+#define MCF_ADC_ADZCSTAT_ZCS5 (0x20)\r
+#define MCF_ADC_ADZCSTAT_ZCS6 (0x40)\r
+#define MCF_ADC_ADZCSTAT_ZCS7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADRSLT */\r
+#define MCF_ADC_ADRSLT_RSLT(x) (((x)&0xFFF)<<0x3)\r
+#define MCF_ADC_ADRSLT_SEXT (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADLLMT */\r
+#define MCF_ADC_ADLLMT_LLMT(x) (((x)&0xFFF)<<0x3)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADHLMT */\r
+#define MCF_ADC_ADHLMT_HLMT(x) (((x)&0xFFF)<<0x3)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADOFS */\r
+#define MCF_ADC_ADOFS_OFFSET(x) (((x)&0xFFF)<<0x3)\r
+\r
+/* Bit definitions and macros for MCF_ADC_POWER */\r
+#define MCF_ADC_POWER_PD0 (0x1)\r
+#define MCF_ADC_POWER_PD1 (0x2)\r
+#define MCF_ADC_POWER_PD2 (0x4)\r
+#define MCF_ADC_POWER_APD (0x8)\r
+#define MCF_ADC_POWER_PUDELAY(x) (((x)&0x3F)<<0x4)\r
+#define MCF_ADC_POWER_PSTS0 (0x400)\r
+#define MCF_ADC_POWER_PSTS1 (0x800)\r
+#define MCF_ADC_POWER_PSTS2 (0x1000)\r
+#define MCF_ADC_POWER_ASB (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_CAL */\r
+#define MCF_ADC_CAL_SEL_VREFL (0x4000)\r
+#define MCF_ADC_CAL_SEL_VREFH (0x8000)\r
+\r
+\r
+#endif /* __MCF52235_ADC_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_CCM_H__\r
+#define __MCF52235_CCM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Chip Configuration Module (CCM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_CCM_CCR (*(vuint16*)(&__IPSBAR[0x110004]))\r
+#define MCF_CCM_RCON (*(vuint16*)(&__IPSBAR[0x110008]))\r
+#define MCF_CCM_CIR (*(vuint16*)(&__IPSBAR[0x11000A]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_CCM_CCR */\r
+#define MCF_CCM_CCR_BMT(x) (((x)&0x7)<<0)\r
+#define MCF_CCM_CCR_BMT_65536 (0)\r
+#define MCF_CCM_CCR_BMT_32768 (0x1)\r
+#define MCF_CCM_CCR_BMT_16384 (0x2)\r
+#define MCF_CCM_CCR_BMT_8192 (0x3)\r
+#define MCF_CCM_CCR_BMT_4096 (0x4)\r
+#define MCF_CCM_CCR_BMT_2048 (0x5)\r
+#define MCF_CCM_CCR_BMT_1024 (0x6)\r
+#define MCF_CCM_CCR_BMT_512 (0x7)\r
+#define MCF_CCM_CCR_BME (0x8)\r
+#define MCF_CCM_CCR_PSTEN (0x20)\r
+#define MCF_CCM_CCR_SZEN (0x40)\r
+\r
+/* Bit definitions and macros for MCF_CCM_RCON */\r
+#define MCF_CCM_RCON_MODE (0x1)\r
+#define MCF_CCM_RCON_RLOAD (0x20)\r
+\r
+/* Bit definitions and macros for MCF_CCM_CIR */\r
+#define MCF_CCM_CIR_PRN(x) (((x)&0x3F)<<0)\r
+#define MCF_CCM_CIR_PIN(x) (((x)&0x3FF)<<0x6)\r
+\r
+\r
+#endif /* __MCF52235_CCM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_CFM_H__\r
+#define __MCF52235_CFM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* ColdFire Flash Module (CFM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_CFM_CFMMCR (*(vuint16*)(&__IPSBAR[0x1D0000]))\r
+#define MCF_CFM_CFMCLKD (*(vuint8 *)(&__IPSBAR[0x1D0002]))\r
+#define MCF_CFM_CFMSEC (*(vuint32*)(&__IPSBAR[0x1D0008]))\r
+#define MCF_CFM_CFMPROT (*(vuint32*)(&__IPSBAR[0x1D0010]))\r
+#define MCF_CFM_CFMSACC (*(vuint32*)(&__IPSBAR[0x1D0014]))\r
+#define MCF_CFM_CFMDACC (*(vuint32*)(&__IPSBAR[0x1D0018]))\r
+#define MCF_CFM_CFMUSTAT (*(vuint8 *)(&__IPSBAR[0x1D0020]))\r
+#define MCF_CFM_CFMCMD (*(vuint8 *)(&__IPSBAR[0x1D0024]))\r
+#define MCF_CFM_CFMCLKSEL (*(vuint16*)(&__IPSBAR[0x1D004A]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMMCR */\r
+#define MCF_CFM_CFMMCR_KEYACC (0x20)\r
+#define MCF_CFM_CFMMCR_CCIE (0x40)\r
+#define MCF_CFM_CFMMCR_CBEIE (0x80)\r
+#define MCF_CFM_CFMMCR_AEIE (0x100)\r
+#define MCF_CFM_CFMMCR_PVIE (0x200)\r
+#define MCF_CFM_CFMMCR_LOCK (0x400)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMCLKD */\r
+#define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0)\r
+#define MCF_CFM_CFMCLKD_PRDIV8 (0x40)\r
+#define MCF_CFM_CFMCLKD_DIVLD (0x80)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMSEC */\r
+#define MCF_CFM_CFMSEC_SEC(x) (((x)&0xFFFF)<<0)\r
+#define MCF_CFM_CFMSEC_SECSTAT (0x40000000)\r
+#define MCF_CFM_CFMSEC_KEYEN (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMPROT */\r
+#define MCF_CFM_CFMPROT_PROTECT(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMSACC */\r
+#define MCF_CFM_CFMSACC_SUPV(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMDACC */\r
+#define MCF_CFM_CFMDACC_DACC(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMUSTAT */\r
+#define MCF_CFM_CFMUSTAT_BLANK (0x4)\r
+#define MCF_CFM_CFMUSTAT_ACCERR (0x10)\r
+#define MCF_CFM_CFMUSTAT_PVIOL (0x20)\r
+#define MCF_CFM_CFMUSTAT_CCIF (0x40)\r
+#define MCF_CFM_CFMUSTAT_CBEIF (0x80)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMCMD */\r
+#define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0)\r
+#define MCF_CFM_CFMCMD_BLANK_CHECK (0x5)\r
+#define MCF_CFM_CFMCMD_PAGE_ERASE_VERIFY (0x6)\r
+#define MCF_CFM_CFMCMD_WORD_PROGRAM (0x20)\r
+#define MCF_CFM_CFMCMD_PAGE_ERASE (0x40)\r
+#define MCF_CFM_CFMCMD_MASS_ERASE (0x41)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMCLKSEL */\r
+#define MCF_CFM_CFMCLKSEL_CLKSEL(x) (((x)&0x3)<<0)\r
+\r
+\r
+#endif /* __MCF52235_CFM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_CLOCK_H__\r
+#define __MCF52235_CLOCK_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Clock Module (CLOCK)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_CLOCK_SYNCR (*(vuint16*)(&__IPSBAR[0x120000]))\r
+#define MCF_CLOCK_SYNSR (*(vuint8 *)(&__IPSBAR[0x120002]))\r
+#define MCF_CLOCK_LPCR (*(vuint8 *)(&__IPSBAR[0x120007]))\r
+#define MCF_CLOCK_CCHR (*(vuint8 *)(&__IPSBAR[0x120008]))\r
+#define MCF_CLOCK_RTCDR (*(vuint32*)(&__IPSBAR[0x12000C]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_SYNCR */\r
+#define MCF_CLOCK_SYNCR_PLLEN (0x1)\r
+#define MCF_CLOCK_SYNCR_PLLMODE (0x2)\r
+#define MCF_CLOCK_SYNCR_CLKSRC (0x4)\r
+#define MCF_CLOCK_SYNCR_FWKUP (0x20)\r
+#define MCF_CLOCK_SYNCR_DISCLK (0x40)\r
+#define MCF_CLOCK_SYNCR_LOCEN (0x80)\r
+#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x7)<<0x8)\r
+#define MCF_CLOCK_SYNCR_LOCRE (0x800)\r
+#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x7)<<0xC)\r
+#define MCF_CLOCK_SYNCR_LOLRE (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_SYNSR */\r
+#define MCF_CLOCK_SYNSR_LOCS (0x4)\r
+#define MCF_CLOCK_SYNSR_LOCK (0x8)\r
+#define MCF_CLOCK_SYNSR_LOCKS (0x10)\r
+#define MCF_CLOCK_SYNSR_EXTOSC (0x80)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_LPCR */\r
+#define MCF_CLOCK_LPCR_LPD(x) (((x)&0xF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_CCHR */\r
+#define MCF_CLOCK_CCHR_CCHR(x) (((x)&0x7)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_RTCDR */\r
+#define MCF_CLOCK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52235_CLOCK_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_DMA_H__\r
+#define __MCF52235_DMA_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* DMA Controller (DMA)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_DMA0_SAR (*(vuint32*)(&__IPSBAR[0x100]))\r
+#define MCF_DMA0_DAR (*(vuint32*)(&__IPSBAR[0x104]))\r
+#define MCF_DMA0_DSR (*(vuint8 *)(&__IPSBAR[0x108]))\r
+#define MCF_DMA0_BCR (*(vuint32*)(&__IPSBAR[0x108]))\r
+#define MCF_DMA0_DCR (*(vuint32*)(&__IPSBAR[0x10C]))\r
+\r
+#define MCF_DMA1_SAR (*(vuint32*)(&__IPSBAR[0x110]))\r
+#define MCF_DMA1_DAR (*(vuint32*)(&__IPSBAR[0x114]))\r
+#define MCF_DMA1_DSR (*(vuint8 *)(&__IPSBAR[0x118]))\r
+#define MCF_DMA1_BCR (*(vuint32*)(&__IPSBAR[0x118]))\r
+#define MCF_DMA1_DCR (*(vuint32*)(&__IPSBAR[0x11C]))\r
+\r
+#define MCF_DMA2_SAR (*(vuint32*)(&__IPSBAR[0x120]))\r
+#define MCF_DMA2_DAR (*(vuint32*)(&__IPSBAR[0x124]))\r
+#define MCF_DMA2_DSR (*(vuint8 *)(&__IPSBAR[0x128]))\r
+#define MCF_DMA2_BCR (*(vuint32*)(&__IPSBAR[0x128]))\r
+#define MCF_DMA2_DCR (*(vuint32*)(&__IPSBAR[0x12C]))\r
+\r
+#define MCF_DMA3_SAR (*(vuint32*)(&__IPSBAR[0x130]))\r
+#define MCF_DMA3_DAR (*(vuint32*)(&__IPSBAR[0x134]))\r
+#define MCF_DMA3_DSR (*(vuint8 *)(&__IPSBAR[0x138]))\r
+#define MCF_DMA3_BCR (*(vuint32*)(&__IPSBAR[0x138]))\r
+#define MCF_DMA3_DCR (*(vuint32*)(&__IPSBAR[0x13C]))\r
+\r
+#define MCF_DMA_SAR(x) (*(vuint32*)(&__IPSBAR[0x100 + ((x)*0x10)]))\r
+#define MCF_DMA_DAR(x) (*(vuint32*)(&__IPSBAR[0x104 + ((x)*0x10)]))\r
+#define MCF_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x108 + ((x)*0x10)]))\r
+#define MCF_DMA_BCR(x) (*(vuint32*)(&__IPSBAR[0x108 + ((x)*0x10)]))\r
+#define MCF_DMA_DCR(x) (*(vuint32*)(&__IPSBAR[0x10C + ((x)*0x10)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_DMA_SAR */\r
+#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DMA_DAR */\r
+#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DMA_DSR */\r
+#define MCF_DMA_DSR_DONE (0x1)\r
+#define MCF_DMA_DSR_BSY (0x2)\r
+#define MCF_DMA_DSR_REQ (0x4)\r
+#define MCF_DMA_DSR_BED (0x10)\r
+#define MCF_DMA_DSR_BES (0x20)\r
+#define MCF_DMA_DSR_CE (0x40)\r
+\r
+/* Bit definitions and macros for MCF_DMA_BCR */\r
+#define MCF_DMA_BCR_BCR(x) (((x)&0xFFFFFF)<<0)\r
+#define MCF_DMA_BCR_DSR(x) (((x)&0xFF)<<0x18)\r
+\r
+/* Bit definitions and macros for MCF_DMA_DCR */\r
+#define MCF_DMA_DCR_LCH2(x) (((x)&0x3)<<0)\r
+#define MCF_DMA_DCR_LCH2_CH0 (0)\r
+#define MCF_DMA_DCR_LCH2_CH1 (0x1)\r
+#define MCF_DMA_DCR_LCH2_CH2 (0x2)\r
+#define MCF_DMA_DCR_LCH2_CH3 (0x3)\r
+#define MCF_DMA_DCR_LCH1(x) (((x)&0x3)<<0x2)\r
+#define MCF_DMA_DCR_LCH1_CH0 (0)\r
+#define MCF_DMA_DCR_LCH1_CH1 (0x1)\r
+#define MCF_DMA_DCR_LCH1_CH2 (0x2)\r
+#define MCF_DMA_DCR_LCH1_CH3 (0x3)\r
+#define MCF_DMA_DCR_LINKCC(x) (((x)&0x3)<<0x4)\r
+#define MCF_DMA_DCR_D_REQ (0x80)\r
+#define MCF_DMA_DCR_DMOD(x) (((x)&0xF)<<0x8)\r
+#define MCF_DMA_DCR_DMOD_DIS (0)\r
+#define MCF_DMA_DCR_DMOD_16 (0x1)\r
+#define MCF_DMA_DCR_DMOD_32 (0x2)\r
+#define MCF_DMA_DCR_DMOD_64 (0x3)\r
+#define MCF_DMA_DCR_DMOD_128 (0x4)\r
+#define MCF_DMA_DCR_DMOD_256 (0x5)\r
+#define MCF_DMA_DCR_DMOD_512 (0x6)\r
+#define MCF_DMA_DCR_DMOD_1K (0x7)\r
+#define MCF_DMA_DCR_DMOD_2K (0x8)\r
+#define MCF_DMA_DCR_DMOD_4K (0x9)\r
+#define MCF_DMA_DCR_DMOD_8K (0xA)\r
+#define MCF_DMA_DCR_DMOD_16K (0xB)\r
+#define MCF_DMA_DCR_DMOD_32K (0xC)\r
+#define MCF_DMA_DCR_DMOD_64K (0xD)\r
+#define MCF_DMA_DCR_DMOD_128K (0xE)\r
+#define MCF_DMA_DCR_DMOD_256K (0xF)\r
+#define MCF_DMA_DCR_SMOD(x) (((x)&0xF)<<0xC)\r
+#define MCF_DMA_DCR_SMOD_DIS (0)\r
+#define MCF_DMA_DCR_SMOD_16 (0x1)\r
+#define MCF_DMA_DCR_SMOD_32 (0x2)\r
+#define MCF_DMA_DCR_SMOD_64 (0x3)\r
+#define MCF_DMA_DCR_SMOD_128 (0x4)\r
+#define MCF_DMA_DCR_SMOD_256 (0x5)\r
+#define MCF_DMA_DCR_SMOD_512 (0x6)\r
+#define MCF_DMA_DCR_SMOD_1K (0x7)\r
+#define MCF_DMA_DCR_SMOD_2K (0x8)\r
+#define MCF_DMA_DCR_SMOD_4K (0x9)\r
+#define MCF_DMA_DCR_SMOD_8K (0xA)\r
+#define MCF_DMA_DCR_SMOD_16K (0xB)\r
+#define MCF_DMA_DCR_SMOD_32K (0xC)\r
+#define MCF_DMA_DCR_SMOD_64K (0xD)\r
+#define MCF_DMA_DCR_SMOD_128K (0xE)\r
+#define MCF_DMA_DCR_SMOD_256K (0xF)\r
+#define MCF_DMA_DCR_START (0x10000)\r
+#define MCF_DMA_DCR_DSIZE(x) (((x)&0x3)<<0x11)\r
+#define MCF_DMA_DCR_DSIZE_LONG (0)\r
+#define MCF_DMA_DCR_DSIZE_BYTE (0x1)\r
+#define MCF_DMA_DCR_DSIZE_WORD (0x2)\r
+#define MCF_DMA_DCR_DSIZE_LINE (0x3)\r
+#define MCF_DMA_DCR_DINC (0x80000)\r
+#define MCF_DMA_DCR_SSIZE(x) (((x)&0x3)<<0x14)\r
+#define MCF_DMA_DCR_SSIZE_LONG (0)\r
+#define MCF_DMA_DCR_SSIZE_BYTE (0x1)\r
+#define MCF_DMA_DCR_SSIZE_WORD (0x2)\r
+#define MCF_DMA_DCR_SSIZE_LINE (0x3)\r
+#define MCF_DMA_DCR_SINC (0x400000)\r
+#define MCF_DMA_DCR_BWC(x) (((x)&0x7)<<0x19)\r
+#define MCF_DMA_DCR_BWC_16K (0x1)\r
+#define MCF_DMA_DCR_BWC_32K (0x2)\r
+#define MCF_DMA_DCR_BWC_64K (0x3)\r
+#define MCF_DMA_DCR_BWC_128K (0x4)\r
+#define MCF_DMA_DCR_BWC_256K (0x5)\r
+#define MCF_DMA_DCR_BWC_512K (0x6)\r
+#define MCF_DMA_DCR_BWC_1024K (0x7)\r
+#define MCF_DMA_DCR_AA (0x10000000)\r
+#define MCF_DMA_DCR_CS (0x20000000)\r
+#define MCF_DMA_DCR_EEXT (0x40000000)\r
+#define MCF_DMA_DCR_INT (0x80000000)\r
+\r
+\r
+#endif /* __MCF52235_DMA_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_DTIM_H__\r
+#define __MCF52235_DTIM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* DMA Timers (DTIM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_DTIM0_DTMR (*(vuint16*)(&__IPSBAR[0x400]))\r
+#define MCF_DTIM0_DTXMR (*(vuint8 *)(&__IPSBAR[0x402]))\r
+#define MCF_DTIM0_DTER (*(vuint8 *)(&__IPSBAR[0x403]))\r
+#define MCF_DTIM0_DTRR (*(vuint32*)(&__IPSBAR[0x404]))\r
+#define MCF_DTIM0_DTCR (*(vuint32*)(&__IPSBAR[0x408]))\r
+#define MCF_DTIM0_DTCN (*(vuint32*)(&__IPSBAR[0x40C]))\r
+\r
+#define MCF_DTIM1_DTMR (*(vuint16*)(&__IPSBAR[0x440]))\r
+#define MCF_DTIM1_DTXMR (*(vuint8 *)(&__IPSBAR[0x442]))\r
+#define MCF_DTIM1_DTER (*(vuint8 *)(&__IPSBAR[0x443]))\r
+#define MCF_DTIM1_DTRR (*(vuint32*)(&__IPSBAR[0x444]))\r
+#define MCF_DTIM1_DTCR (*(vuint32*)(&__IPSBAR[0x448]))\r
+#define MCF_DTIM1_DTCN (*(vuint32*)(&__IPSBAR[0x44C]))\r
+\r
+#define MCF_DTIM2_DTMR (*(vuint16*)(&__IPSBAR[0x480]))\r
+#define MCF_DTIM2_DTXMR (*(vuint8 *)(&__IPSBAR[0x482]))\r
+#define MCF_DTIM2_DTER (*(vuint8 *)(&__IPSBAR[0x483]))\r
+#define MCF_DTIM2_DTRR (*(vuint32*)(&__IPSBAR[0x484]))\r
+#define MCF_DTIM2_DTCR (*(vuint32*)(&__IPSBAR[0x488]))\r
+#define MCF_DTIM2_DTCN (*(vuint32*)(&__IPSBAR[0x48C]))\r
+\r
+#define MCF_DTIM3_DTMR (*(vuint16*)(&__IPSBAR[0x4C0]))\r
+#define MCF_DTIM3_DTXMR (*(vuint8 *)(&__IPSBAR[0x4C2]))\r
+#define MCF_DTIM3_DTER (*(vuint8 *)(&__IPSBAR[0x4C3]))\r
+#define MCF_DTIM3_DTRR (*(vuint32*)(&__IPSBAR[0x4C4]))\r
+#define MCF_DTIM3_DTCR (*(vuint32*)(&__IPSBAR[0x4C8]))\r
+#define MCF_DTIM3_DTCN (*(vuint32*)(&__IPSBAR[0x4CC]))\r
+\r
+#define MCF_DTIM_DTMR(x) (*(vuint16*)(&__IPSBAR[0x400 + ((x)*0x40)]))\r
+#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x402 + ((x)*0x40)]))\r
+#define MCF_DTIM_DTER(x) (*(vuint8 *)(&__IPSBAR[0x403 + ((x)*0x40)]))\r
+#define MCF_DTIM_DTRR(x) (*(vuint32*)(&__IPSBAR[0x404 + ((x)*0x40)]))\r
+#define MCF_DTIM_DTCR(x) (*(vuint32*)(&__IPSBAR[0x408 + ((x)*0x40)]))\r
+#define MCF_DTIM_DTCN(x) (*(vuint32*)(&__IPSBAR[0x40C + ((x)*0x40)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTMR */\r
+#define MCF_DTIM_DTMR_RST (0x1)\r
+#define MCF_DTIM_DTMR_CLK(x) (((x)&0x3)<<0x1)\r
+#define MCF_DTIM_DTMR_CLK_STOP (0)\r
+#define MCF_DTIM_DTMR_CLK_DIV1 (0x2)\r
+#define MCF_DTIM_DTMR_CLK_DIV16 (0x4)\r
+#define MCF_DTIM_DTMR_CLK_DTIN (0x6)\r
+#define MCF_DTIM_DTMR_FRR (0x8)\r
+#define MCF_DTIM_DTMR_ORRI (0x10)\r
+#define MCF_DTIM_DTMR_OM (0x20)\r
+#define MCF_DTIM_DTMR_CE(x) (((x)&0x3)<<0x6)\r
+#define MCF_DTIM_DTMR_CE_NONE (0)\r
+#define MCF_DTIM_DTMR_CE_RISE (0x40)\r
+#define MCF_DTIM_DTMR_CE_FALL (0x80)\r
+#define MCF_DTIM_DTMR_CE_ANY (0xC0)\r
+#define MCF_DTIM_DTMR_PS(x) (((x)&0xFF)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTXMR */\r
+#define MCF_DTIM_DTXMR_MODE16 (0x1)\r
+#define MCF_DTIM_DTXMR_HALTED (0x40)\r
+#define MCF_DTIM_DTXMR_DMAEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTER */\r
+#define MCF_DTIM_DTER_CAP (0x1)\r
+#define MCF_DTIM_DTER_REF (0x2)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTRR */\r
+#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTCR */\r
+#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTCN */\r
+#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52235_DTIM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_EPHY_H__\r
+#define __MCF52235_EPHY_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Ethernet Physical Transceiver (EPHY)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_EPHY_EPHYCTL0 (*(vuint8 *)(&__IPSBAR[0x1E0000]))\r
+#define MCF_EPHY_EPHYCTL1 (*(vuint8 *)(&__IPSBAR[0x1E0001]))\r
+#define MCF_EPHY_EPHYSR (*(vuint8 *)(&__IPSBAR[0x1E0002]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_EPHY_EPHYCTL0 */\r
+#define MCF_EPHY_EPHYCTL0_EPHYIEN (0x1)\r
+#define MCF_EPHY_EPHYCTL0_EPHYWAI (0x4)\r
+#define MCF_EPHY_EPHYCTL0_LEDEN (0x8)\r
+#define MCF_EPHY_EPHYCTL0_DIS10 (0x10)\r
+#define MCF_EPHY_EPHYCTL0_DIS100 (0x20)\r
+#define MCF_EPHY_EPHYCTL0_ANDIS (0x40)\r
+#define MCF_EPHY_EPHYCTL0_EPHYEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPHY_EPHYCTL1 */\r
+#define MCF_EPHY_EPHYCTL1_PHYADD(x) (((x)&0x1F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_EPHY_EPHYSR */\r
+#define MCF_EPHY_EPHYSR_EPHYIF (0x1)\r
+#define MCF_EPHY_EPHYSR_10DIS (0x10)\r
+#define MCF_EPHY_EPHYSR_100DIS (0x20)\r
+\r
+\r
+#endif /* __MCF52235_EPHY_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_EPORT_H__\r
+#define __MCF52235_EPORT_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Edge Port Module (EPORT)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_EPORT0_EPPAR (*(vuint16*)(&__IPSBAR[0x130000]))\r
+#define MCF_EPORT0_EPDDR (*(vuint8 *)(&__IPSBAR[0x130002]))\r
+#define MCF_EPORT0_EPIER (*(vuint8 *)(&__IPSBAR[0x130003]))\r
+#define MCF_EPORT0_EPDR (*(vuint8 *)(&__IPSBAR[0x130004]))\r
+#define MCF_EPORT0_EPPDR (*(vuint8 *)(&__IPSBAR[0x130005]))\r
+#define MCF_EPORT0_EPFR (*(vuint8 *)(&__IPSBAR[0x130006]))\r
+\r
+#define MCF_EPORT1_EPPAR (*(vuint16*)(&__IPSBAR[0x140000]))\r
+#define MCF_EPORT1_EPDDR (*(vuint8 *)(&__IPSBAR[0x140002]))\r
+#define MCF_EPORT1_EPIER (*(vuint8 *)(&__IPSBAR[0x140003]))\r
+#define MCF_EPORT1_EPDR (*(vuint8 *)(&__IPSBAR[0x140004]))\r
+#define MCF_EPORT1_EPPDR (*(vuint8 *)(&__IPSBAR[0x140005]))\r
+#define MCF_EPORT1_EPFR (*(vuint8 *)(&__IPSBAR[0x140006]))\r
+\r
+#define MCF_EPORT_EPPAR(x) (*(vuint16*)(&__IPSBAR[0x130000 + ((x)*0x10000)]))\r
+#define MCF_EPORT_EPDDR(x) (*(vuint8 *)(&__IPSBAR[0x130002 + ((x)*0x10000)]))\r
+#define MCF_EPORT_EPIER(x) (*(vuint8 *)(&__IPSBAR[0x130003 + ((x)*0x10000)]))\r
+#define MCF_EPORT_EPDR(x) (*(vuint8 *)(&__IPSBAR[0x130004 + ((x)*0x10000)]))\r
+#define MCF_EPORT_EPPDR(x) (*(vuint8 *)(&__IPSBAR[0x130005 + ((x)*0x10000)]))\r
+#define MCF_EPORT_EPFR(x) (*(vuint8 *)(&__IPSBAR[0x130006 + ((x)*0x10000)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPPAR */\r
+#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)\r
+#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)\r
+#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)\r
+#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)\r
+#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)\r
+#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)\r
+#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)\r
+#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)\r
+#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)\r
+#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)\r
+#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)\r
+#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)\r
+#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)\r
+#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)\r
+#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)\r
+#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)\r
+#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)\r
+#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)\r
+#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)\r
+#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)\r
+#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)\r
+#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)\r
+#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)\r
+#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)\r
+#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)\r
+#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)\r
+#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)\r
+#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)\r
+#define MCF_EPORT_EPPAR_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_RISING (0x1)\r
+#define MCF_EPORT_EPPAR_FALLING (0x2)\r
+#define MCF_EPORT_EPPAR_BOTH (0x3)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPDDR */\r
+#define MCF_EPORT_EPDDR_EPDD1 (0x2)\r
+#define MCF_EPORT_EPDDR_EPDD2 (0x4)\r
+#define MCF_EPORT_EPDDR_EPDD3 (0x8)\r
+#define MCF_EPORT_EPDDR_EPDD4 (0x10)\r
+#define MCF_EPORT_EPDDR_EPDD5 (0x20)\r
+#define MCF_EPORT_EPDDR_EPDD6 (0x40)\r
+#define MCF_EPORT_EPDDR_EPDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPIER */\r
+#define MCF_EPORT_EPIER_EPIE1 (0x2)\r
+#define MCF_EPORT_EPIER_EPIE2 (0x4)\r
+#define MCF_EPORT_EPIER_EPIE3 (0x8)\r
+#define MCF_EPORT_EPIER_EPIE4 (0x10)\r
+#define MCF_EPORT_EPIER_EPIE5 (0x20)\r
+#define MCF_EPORT_EPIER_EPIE6 (0x40)\r
+#define MCF_EPORT_EPIER_EPIE7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPDR */\r
+#define MCF_EPORT_EPDR_EPD1 (0x2)\r
+#define MCF_EPORT_EPDR_EPD2 (0x4)\r
+#define MCF_EPORT_EPDR_EPD3 (0x8)\r
+#define MCF_EPORT_EPDR_EPD4 (0x10)\r
+#define MCF_EPORT_EPDR_EPD5 (0x20)\r
+#define MCF_EPORT_EPDR_EPD6 (0x40)\r
+#define MCF_EPORT_EPDR_EPD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPPDR */\r
+#define MCF_EPORT_EPPDR_EPPD1 (0x2)\r
+#define MCF_EPORT_EPPDR_EPPD2 (0x4)\r
+#define MCF_EPORT_EPPDR_EPPD3 (0x8)\r
+#define MCF_EPORT_EPPDR_EPPD4 (0x10)\r
+#define MCF_EPORT_EPPDR_EPPD5 (0x20)\r
+#define MCF_EPORT_EPPDR_EPPD6 (0x40)\r
+#define MCF_EPORT_EPPDR_EPPD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPFR */\r
+#define MCF_EPORT_EPFR_EPF1 (0x2)\r
+#define MCF_EPORT_EPFR_EPF2 (0x4)\r
+#define MCF_EPORT_EPFR_EPF3 (0x8)\r
+#define MCF_EPORT_EPFR_EPF4 (0x10)\r
+#define MCF_EPORT_EPFR_EPF5 (0x20)\r
+#define MCF_EPORT_EPFR_EPF6 (0x40)\r
+#define MCF_EPORT_EPFR_EPF7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPPAR */\r
+#define MCF_EPORT_EPPAR_EPPA8(x) (((x)&0x3)<<0)\r
+#define MCF_EPORT_EPPAR_EPPA8_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA8_RISING (0x1)\r
+#define MCF_EPORT_EPPAR_EPPA8_FALLING (0x2)\r
+#define MCF_EPORT_EPPAR_EPPA8_BOTH (0x3)\r
+#define MCF_EPORT_EPPAR_EPPA9(x) (((x)&0x3)<<0x2)\r
+#define MCF_EPORT_EPPAR_EPPA9_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA9_RISING (0x4)\r
+#define MCF_EPORT_EPPAR_EPPA9_FALLING (0x8)\r
+#define MCF_EPORT_EPPAR_EPPA9_BOTH (0xC)\r
+#define MCF_EPORT_EPPAR_EPPA10(x) (((x)&0x3)<<0x4)\r
+#define MCF_EPORT_EPPAR_EPPA10_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA10_RISING (0x10)\r
+#define MCF_EPORT_EPPAR_EPPA10_FALLING (0x20)\r
+#define MCF_EPORT_EPPAR_EPPA10_BOTH (0x30)\r
+#define MCF_EPORT_EPPAR_EPPA11(x) (((x)&0x3)<<0x6)\r
+#define MCF_EPORT_EPPAR_EPPA11_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA11_RISING (0x40)\r
+#define MCF_EPORT_EPPAR_EPPA11_FALLING (0x80)\r
+#define MCF_EPORT_EPPAR_EPPA11_BOTH (0xC0)\r
+#define MCF_EPORT_EPPAR_EPPA12(x) (((x)&0x3)<<0x8)\r
+#define MCF_EPORT_EPPAR_EPPA12_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA12_RISING (0x100)\r
+#define MCF_EPORT_EPPAR_EPPA12_FALLING (0x200)\r
+#define MCF_EPORT_EPPAR_EPPA12_BOTH (0x300)\r
+#define MCF_EPORT_EPPAR_EPPA13(x) (((x)&0x3)<<0xA)\r
+#define MCF_EPORT_EPPAR_EPPA13_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA13_RISING (0x400)\r
+#define MCF_EPORT_EPPAR_EPPA13_FALLING (0x800)\r
+#define MCF_EPORT_EPPAR_EPPA13_BOTH (0xC00)\r
+#define MCF_EPORT_EPPAR_EPPA14(x) (((x)&0x3)<<0xC)\r
+#define MCF_EPORT_EPPAR_EPPA14_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA14_RISING (0x1000)\r
+#define MCF_EPORT_EPPAR_EPPA14_FALLING (0x2000)\r
+#define MCF_EPORT_EPPAR_EPPA14_BOTH (0x3000)\r
+#define MCF_EPORT_EPPAR_EPPA15(x) (((x)&0x3)<<0xE)\r
+#define MCF_EPORT_EPPAR_EPPA15_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA15_RISING (0x4000)\r
+#define MCF_EPORT_EPPAR_EPPA15_FALLING (0x8000)\r
+#define MCF_EPORT_EPPAR_EPPA15_BOTH (0xC000)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPDDR */\r
+#define MCF_EPORT_EPDDR_EPDD8 (0x1)\r
+#define MCF_EPORT_EPDDR_EPDD9 (0x2)\r
+#define MCF_EPORT_EPDDR_EPDD10 (0x4)\r
+#define MCF_EPORT_EPDDR_EPDD11 (0x8)\r
+#define MCF_EPORT_EPDDR_EPDD12 (0x10)\r
+#define MCF_EPORT_EPDDR_EPDD13 (0x20)\r
+#define MCF_EPORT_EPDDR_EPDD14 (0x40)\r
+#define MCF_EPORT_EPDDR_EPDD15 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPIER */\r
+#define MCF_EPORT_EPIER_EPIE8 (0x1)\r
+#define MCF_EPORT_EPIER_EPIE9 (0x2)\r
+#define MCF_EPORT_EPIER_EPIE10 (0x4)\r
+#define MCF_EPORT_EPIER_EPIE11 (0x8)\r
+#define MCF_EPORT_EPIER_EPIE12 (0x10)\r
+#define MCF_EPORT_EPIER_EPIE13 (0x20)\r
+#define MCF_EPORT_EPIER_EPIE14 (0x40)\r
+#define MCF_EPORT_EPIER_EPIE15 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPDR */\r
+#define MCF_EPORT_EPDR_EPD8 (0x1)\r
+#define MCF_EPORT_EPDR_EPD9 (0x2)\r
+#define MCF_EPORT_EPDR_EPD10 (0x4)\r
+#define MCF_EPORT_EPDR_EPD11 (0x8)\r
+#define MCF_EPORT_EPDR_EPD12 (0x10)\r
+#define MCF_EPORT_EPDR_EPD13 (0x20)\r
+#define MCF_EPORT_EPDR_EPD14 (0x40)\r
+#define MCF_EPORT_EPDR_EPD15 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPPDR */\r
+#define MCF_EPORT_EPPDR_EPPD8 (0x1)\r
+#define MCF_EPORT_EPPDR_EPPD9 (0x2)\r
+#define MCF_EPORT_EPPDR_EPPD10 (0x4)\r
+#define MCF_EPORT_EPPDR_EPPD11 (0x8)\r
+#define MCF_EPORT_EPPDR_EPPD12 (0x10)\r
+#define MCF_EPORT_EPPDR_EPPD13 (0x20)\r
+#define MCF_EPORT_EPPDR_EPPD14 (0x40)\r
+#define MCF_EPORT_EPPDR_EPPD15 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPFR */\r
+#define MCF_EPORT_EPFR_EPF8 (0x1)\r
+#define MCF_EPORT_EPFR_EPF9 (0x2)\r
+#define MCF_EPORT_EPFR_EPF10 (0x4)\r
+#define MCF_EPORT_EPFR_EPF11 (0x8)\r
+#define MCF_EPORT_EPFR_EPF12 (0x10)\r
+#define MCF_EPORT_EPFR_EPF13 (0x20)\r
+#define MCF_EPORT_EPFR_EPF14 (0x40)\r
+#define MCF_EPORT_EPFR_EPF15 (0x80)\r
+\r
+\r
+#endif /* __MCF52235_EPORT_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_FEC_H__\r
+#define __MCF52235_FEC_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Fast Ethernet Controller(FEC)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_FEC_EIR (*(vuint32*)(&__IPSBAR[0x1004]))\r
+#define MCF_FEC_EIMR (*(vuint32*)(&__IPSBAR[0x1008]))\r
+#define MCF_FEC_RDAR (*(vuint32*)(&__IPSBAR[0x1010]))\r
+#define MCF_FEC_TDAR (*(vuint32*)(&__IPSBAR[0x1014]))\r
+#define MCF_FEC_ECR (*(vuint32*)(&__IPSBAR[0x1024]))\r
+#define MCF_FEC_MMFR (*(vuint32*)(&__IPSBAR[0x1040]))\r
+#define MCF_FEC_MSCR (*(vuint32*)(&__IPSBAR[0x1044]))\r
+#define MCF_FEC_MIBC (*(vuint32*)(&__IPSBAR[0x1064]))\r
+#define MCF_FEC_RCR (*(vuint32*)(&__IPSBAR[0x1084]))\r
+#define MCF_FEC_TCR (*(vuint32*)(&__IPSBAR[0x10C4]))\r
+#define MCF_FEC_PALR (*(vuint32*)(&__IPSBAR[0x10E4]))\r
+#define MCF_FEC_PAUR (*(vuint32*)(&__IPSBAR[0x10E8]))\r
+#define MCF_FEC_OPD (*(vuint32*)(&__IPSBAR[0x10EC]))\r
+#define MCF_FEC_IAUR (*(vuint32*)(&__IPSBAR[0x1118]))\r
+#define MCF_FEC_IALR (*(vuint32*)(&__IPSBAR[0x111C]))\r
+#define MCF_FEC_GAUR (*(vuint32*)(&__IPSBAR[0x1120]))\r
+#define MCF_FEC_GALR (*(vuint32*)(&__IPSBAR[0x1124]))\r
+#define MCF_FEC_TFWR (*(vuint32*)(&__IPSBAR[0x1144]))\r
+#define MCF_FEC_FRBR (*(vuint32*)(&__IPSBAR[0x114C]))\r
+#define MCF_FEC_FRSR (*(vuint32*)(&__IPSBAR[0x1150]))\r
+#define MCF_FEC_ERDSR (*(vuint32*)(&__IPSBAR[0x1180]))\r
+#define MCF_FEC_ETSDR (*(vuint32*)(&__IPSBAR[0x1184]))\r
+#define MCF_FEC_EMRBR (*(vuint32*)(&__IPSBAR[0x1188]))\r
+#define MCF_FEC_RMON_T_DROP (*(vuint32*)(&__IPSBAR[0x1200]))\r
+#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(&__IPSBAR[0x1204]))\r
+#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(&__IPSBAR[0x1208]))\r
+#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(&__IPSBAR[0x120C]))\r
+#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x1210]))\r
+#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x1214]))\r
+#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(&__IPSBAR[0x1218]))\r
+#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(&__IPSBAR[0x121C]))\r
+#define MCF_FEC_RMON_T_JAB (*(vuint32*)(&__IPSBAR[0x1220]))\r
+#define MCF_FEC_RMON_T_COL (*(vuint32*)(&__IPSBAR[0x1224]))\r
+#define MCF_FEC_RMON_T_P64 (*(vuint32*)(&__IPSBAR[0x1228]))\r
+#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(&__IPSBAR[0x122C]))\r
+#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(&__IPSBAR[0x1230]))\r
+#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(&__IPSBAR[0x1234]))\r
+#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(&__IPSBAR[0x1238]))\r
+#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(&__IPSBAR[0x123C]))\r
+#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x1240]))\r
+#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(&__IPSBAR[0x1244]))\r
+#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(&__IPSBAR[0x1248]))\r
+#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(&__IPSBAR[0x124C]))\r
+#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(&__IPSBAR[0x1250]))\r
+#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(&__IPSBAR[0x1254]))\r
+#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(&__IPSBAR[0x1258]))\r
+#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(&__IPSBAR[0x125C]))\r
+#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(&__IPSBAR[0x1260]))\r
+#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(&__IPSBAR[0x1264]))\r
+#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(&__IPSBAR[0x1268]))\r
+#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(&__IPSBAR[0x126C]))\r
+#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(&__IPSBAR[0x1270]))\r
+#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x1274]))\r
+#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(&__IPSBAR[0x1284]))\r
+#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(&__IPSBAR[0x1288]))\r
+#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(&__IPSBAR[0x128C]))\r
+#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x1290]))\r
+#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x1294]))\r
+#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(&__IPSBAR[0x1298]))\r
+#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(&__IPSBAR[0x129C]))\r
+#define MCF_FEC_RMON_R_JAB (*(vuint32*)(&__IPSBAR[0x12A0]))\r
+#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(&__IPSBAR[0x12A4]))\r
+#define MCF_FEC_RMON_R_P64 (*(vuint32*)(&__IPSBAR[0x12A8]))\r
+#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(&__IPSBAR[0x12AC]))\r
+#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(&__IPSBAR[0x12B0]))\r
+#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(&__IPSBAR[0x12B4]))\r
+#define MCF_FEC_RMON_R_P512TO1023 (*(vuint32*)(&__IPSBAR[0x12B8]))\r
+#define MCF_FEC_RMON_R_P1024TO2047 (*(vuint32*)(&__IPSBAR[0x12BC]))\r
+#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x12C0]))\r
+#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(&__IPSBAR[0x12C4]))\r
+#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(&__IPSBAR[0x12C8]))\r
+#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(&__IPSBAR[0x12CC]))\r
+#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(&__IPSBAR[0x12D0]))\r
+#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(&__IPSBAR[0x12D4]))\r
+#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(&__IPSBAR[0x12D8]))\r
+#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(&__IPSBAR[0x12DC]))\r
+#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x12E0]))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_FEC_EIR */\r
+#define MCF_FEC_EIR_UN (0x80000)\r
+#define MCF_FEC_EIR_RL (0x100000)\r
+#define MCF_FEC_EIR_LC (0x200000)\r
+#define MCF_FEC_EIR_EBERR (0x400000)\r
+#define MCF_FEC_EIR_MII (0x800000)\r
+#define MCF_FEC_EIR_RXB (0x1000000)\r
+#define MCF_FEC_EIR_RXF (0x2000000)\r
+#define MCF_FEC_EIR_TXB (0x4000000)\r
+#define MCF_FEC_EIR_TXF (0x8000000)\r
+#define MCF_FEC_EIR_GRA (0x10000000)\r
+#define MCF_FEC_EIR_BABT (0x20000000)\r
+#define MCF_FEC_EIR_BABR (0x40000000)\r
+#define MCF_FEC_EIR_HBERR (0x80000000)\r
+#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)\r
+\r
+/* Bit definitions and macros for MCF_FEC_EIMR */\r
+#define MCF_FEC_EIMR_UN (0x80000)\r
+#define MCF_FEC_EIMR_RL (0x100000)\r
+#define MCF_FEC_EIMR_LC (0x200000)\r
+#define MCF_FEC_EIMR_EBERR (0x400000)\r
+#define MCF_FEC_EIMR_MII (0x800000)\r
+#define MCF_FEC_EIMR_RXB (0x1000000)\r
+#define MCF_FEC_EIMR_RXF (0x2000000)\r
+#define MCF_FEC_EIMR_TXB (0x4000000)\r
+#define MCF_FEC_EIMR_TXF (0x8000000)\r
+#define MCF_FEC_EIMR_GRA (0x10000000)\r
+#define MCF_FEC_EIMR_BABT (0x20000000)\r
+#define MCF_FEC_EIMR_BABR (0x40000000)\r
+#define MCF_FEC_EIMR_HBERR (0x80000000)\r
+#define MCF_FEC_EIMR_MASK_ALL (0)\r
+#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RDAR */\r
+#define MCF_FEC_RDAR_R_DES_ACTIVE (0x1000000)\r
+\r
+/* Bit definitions and macros for MCF_FEC_TDAR */\r
+#define MCF_FEC_TDAR_X_DES_ACTIVE (0x1000000)\r
+\r
+/* Bit definitions and macros for MCF_FEC_ECR */\r
+#define MCF_FEC_ECR_RESET (0x1)\r
+#define MCF_FEC_ECR_ETHER_EN (0x2)\r
+\r
+/* Bit definitions and macros for MCF_FEC_MMFR */\r
+#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0)\r
+#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10)\r
+#define MCF_FEC_MMFR_TA_10 (0x20000)\r
+#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12)\r
+#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17)\r
+#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C)\r
+#define MCF_FEC_MMFR_OP_READ (0x20000000)\r
+#define MCF_FEC_MMFR_OP_WRITE (0x10000000)\r
+#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E)\r
+#define MCF_FEC_MMFR_ST_01 (0x40000000)\r
+\r
+/* Bit definitions and macros for MCF_FEC_MSCR */\r
+#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)\r
+#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80)\r
+\r
+/* Bit definitions and macros for MCF_FEC_MIBC */\r
+#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)\r
+#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RCR */\r
+#define MCF_FEC_RCR_LOOP (0x1)\r
+#define MCF_FEC_RCR_DRT (0x2)\r
+#define MCF_FEC_RCR_MII_MODE (0x4)\r
+#define MCF_FEC_RCR_PROM (0x8)\r
+#define MCF_FEC_RCR_BC_REJ (0x10)\r
+#define MCF_FEC_RCR_FCE (0x20)\r
+#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10)\r
+\r
+/* Bit definitions and macros for MCF_FEC_TCR */\r
+#define MCF_FEC_TCR_GTS (0x1)\r
+#define MCF_FEC_TCR_HBC (0x2)\r
+#define MCF_FEC_TCR_FDEN (0x4)\r
+#define MCF_FEC_TCR_TFC_PAUSE (0x8)\r
+#define MCF_FEC_TCR_RFC_PAUSE (0x10)\r
+\r
+/* Bit definitions and macros for MCF_FEC_PALR */\r
+#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_PAUR */\r
+#define MCF_FEC_PAUR_TYPE(x) (((x)&0xFFFF)<<0)\r
+#define MCF_FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<0x10)\r
+\r
+/* Bit definitions and macros for MCF_FEC_OPD */\r
+#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0)\r
+#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IAUR */\r
+#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IALR */\r
+#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_GAUR */\r
+#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_GALR */\r
+#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_TFWR */\r
+#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x3)<<0)\r
+#define MCF_FEC_TFWR_X_WMRK_64 (0)\r
+#define MCF_FEC_TFWR_X_WMRK_128 (0x2)\r
+#define MCF_FEC_TFWR_X_WMRK_192 (0x3)\r
+\r
+/* Bit definitions and macros for MCF_FEC_FRBR */\r
+#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<0x2)\r
+\r
+/* Bit definitions and macros for MCF_FEC_FRSR */\r
+#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<0x2)\r
+\r
+/* Bit definitions and macros for MCF_FEC_ERDSR */\r
+#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<0x2)\r
+\r
+/* Bit definitions and macros for MCF_FEC_ETSDR */\r
+#define MCF_FEC_ETSDR_X_DES_START(x) (((x)&0x3FFFFFFF)<<0x2)\r
+\r
+/* Bit definitions and macros for MCF_FEC_EMRBR */\r
+#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<0x4)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */\r
+#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */\r
+#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */\r
+#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */\r
+#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */\r
+#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */\r
+#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */\r
+#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */\r
+#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */\r
+#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_COL */\r
+#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */\r
+#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */\r
+#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */\r
+#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */\r
+#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */\r
+#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */\r
+#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */\r
+#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */\r
+#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */\r
+#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */\r
+#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */\r
+#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */\r
+#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */\r
+#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */\r
+#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */\r
+#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */\r
+#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */\r
+#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */\r
+#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */\r
+#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */\r
+#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */\r
+#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */\r
+#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */\r
+#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */\r
+#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */\r
+#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */\r
+#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */\r
+#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */\r
+#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */\r
+#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */\r
+#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */\r
+#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */\r
+#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */\r
+#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */\r
+#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */\r
+#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */\r
+#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */\r
+#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */\r
+#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */\r
+#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */\r
+#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */\r
+#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */\r
+#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */\r
+#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */\r
+#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52235_FEC_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_FlexCAN_H__\r
+#define __MCF52235_FlexCAN_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Flex Controller Area Network (FlexCAN)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_FlexCAN_CANMCR (*(vuint32*)(&__IPSBAR[0x1C0000]))\r
+#define MCF_FlexCAN_CANCTRL (*(vuint32*)(&__IPSBAR[0x1C0004]))\r
+#define MCF_FlexCAN_TIMER (*(vuint32*)(&__IPSBAR[0x1C0008]))\r
+#define MCF_FlexCAN_RXGMASK (*(vuint32*)(&__IPSBAR[0x1C0010]))\r
+#define MCF_FlexCAN_RX14MASK (*(vuint32*)(&__IPSBAR[0x1C0014]))\r
+#define MCF_FlexCAN_RX15MASK (*(vuint32*)(&__IPSBAR[0x1C0018]))\r
+#define MCF_FlexCAN_ERRCNT (*(vuint32*)(&__IPSBAR[0x1C001C]))\r
+#define MCF_FlexCAN_ERRSTAT (*(vuint32*)(&__IPSBAR[0x1C0020]))\r
+#define MCF_FlexCAN_IMASK (*(vuint32*)(&__IPSBAR[0x1C0028]))\r
+#define MCF_FlexCAN_IFLAG (*(vuint32*)(&__IPSBAR[0x1C0030]))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_CANMCR */\r
+#define MCF_FlexCAN_CANMCR_MAXMB(x) (((x)&0xF)<<0)\r
+#define MCF_FlexCAN_CANMCR_LPMACK (0x100000)\r
+#define MCF_FlexCAN_CANMCR_SUPV (0x800000)\r
+#define MCF_FlexCAN_CANMCR_FRZACK (0x1000000)\r
+#define MCF_FlexCAN_CANMCR_SOFTRST (0x2000000)\r
+#define MCF_FlexCAN_CANMCR_NOTRDY (0x8000000)\r
+#define MCF_FlexCAN_CANMCR_HALT (0x10000000)\r
+#define MCF_FlexCAN_CANMCR_FRZ (0x40000000)\r
+#define MCF_FlexCAN_CANMCR_MDIS (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_CANCTRL */\r
+#define MCF_FlexCAN_CANCTRL_PROPSEG(x) (((x)&0x7)<<0)\r
+#define MCF_FlexCAN_CANCTRL_LOM (0x8)\r
+#define MCF_FlexCAN_CANCTRL_LBUF (0x10)\r
+#define MCF_FlexCAN_CANCTRL_TSYNC (0x20)\r
+#define MCF_FlexCAN_CANCTRL_BOFFREC (0x40)\r
+#define MCF_FlexCAN_CANCTRL_SAMP (0x80)\r
+#define MCF_FlexCAN_CANCTRL_LPB (0x1000)\r
+#define MCF_FlexCAN_CANCTRL_CLK_SRC (0x2000)\r
+#define MCF_FlexCAN_CANCTRL_ERRMSK (0x4000)\r
+#define MCF_FlexCAN_CANCTRL_BOFFMSK (0x8000)\r
+#define MCF_FlexCAN_CANCTRL_PSEG2(x) (((x)&0x7)<<0x10)\r
+#define MCF_FlexCAN_CANCTRL_PSEG1(x) (((x)&0x7)<<0x13)\r
+#define MCF_FlexCAN_CANCTRL_RJW(x) (((x)&0x3)<<0x16)\r
+#define MCF_FlexCAN_CANCTRL_PRESDIV(x) (((x)&0xFF)<<0x18)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_TIMER */\r
+#define MCF_FlexCAN_TIMER_TIMER(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_RXGMASK */\r
+#define MCF_FlexCAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_RX14MASK */\r
+#define MCF_FlexCAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_RX15MASK */\r
+#define MCF_FlexCAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_ERRCNT */\r
+#define MCF_FlexCAN_ERRCNT_TXECTR(x) (((x)&0xFF)<<0)\r
+#define MCF_FlexCAN_ERRCNT_RXECTR(x) (((x)&0xFF)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_ERRSTAT */\r
+#define MCF_FlexCAN_ERRSTAT_ERRINT (0x2)\r
+#define MCF_FlexCAN_ERRSTAT_BOFFINT (0x4)\r
+#define MCF_FlexCAN_ERRSTAT_FLTCONF(x) (((x)&0x3)<<0x4)\r
+#define MCF_FlexCAN_ERRSTAT_FLTCONF_ACTIVE (0)\r
+#define MCF_FlexCAN_ERRSTAT_FLTCONF_PASSIVE (0x10)\r
+#define MCF_FlexCAN_ERRSTAT_FLTCONF_BUSOFF (0x20)\r
+#define MCF_FlexCAN_ERRSTAT_TXRX (0x40)\r
+#define MCF_FlexCAN_ERRSTAT_IDLE (0x80)\r
+#define MCF_FlexCAN_ERRSTAT_RXWRN (0x100)\r
+#define MCF_FlexCAN_ERRSTAT_TXWRN (0x200)\r
+#define MCF_FlexCAN_ERRSTAT_STFERR (0x400)\r
+#define MCF_FlexCAN_ERRSTAT_FRMERR (0x800)\r
+#define MCF_FlexCAN_ERRSTAT_CRCERR (0x1000)\r
+#define MCF_FlexCAN_ERRSTAT_ACKERR (0x2000)\r
+#define MCF_FlexCAN_ERRSTAT_BIT0ERR (0x4000)\r
+#define MCF_FlexCAN_ERRSTAT_BIT1ERR (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_IMASK */\r
+#define MCF_FlexCAN_IMASK_BUF0M (0x1)\r
+#define MCF_FlexCAN_IMASK_BUF1M (0x2)\r
+#define MCF_FlexCAN_IMASK_BUF2M (0x4)\r
+#define MCF_FlexCAN_IMASK_BUF3M (0x8)\r
+#define MCF_FlexCAN_IMASK_BUF4M (0x10)\r
+#define MCF_FlexCAN_IMASK_BUF5M (0x20)\r
+#define MCF_FlexCAN_IMASK_BUF6M (0x40)\r
+#define MCF_FlexCAN_IMASK_BUF7M (0x80)\r
+#define MCF_FlexCAN_IMASK_BUF8M (0x100)\r
+#define MCF_FlexCAN_IMASK_BUF9M (0x200)\r
+#define MCF_FlexCAN_IMASK_BUF10M (0x400)\r
+#define MCF_FlexCAN_IMASK_BUF11M (0x800)\r
+#define MCF_FlexCAN_IMASK_BUF12M (0x1000)\r
+#define MCF_FlexCAN_IMASK_BUF13M (0x2000)\r
+#define MCF_FlexCAN_IMASK_BUF14M (0x4000)\r
+#define MCF_FlexCAN_IMASK_BUF15M (0x8000)\r
+#define MCF_FlexCAN_IMASK_BUF(x) (0x1<<(x))\r
+\r
+/* Bit definitions and macros for MCF_FlexCAN_IFLAG */\r
+#define MCF_FlexCAN_IFLAG_BUF0I (0x1)\r
+#define MCF_FlexCAN_IFLAG_BUF1I (0x2)\r
+#define MCF_FlexCAN_IFLAG_BUF2I (0x4)\r
+#define MCF_FlexCAN_IFLAG_BUF3I (0x8)\r
+#define MCF_FlexCAN_IFLAG_BUF4I (0x10)\r
+#define MCF_FlexCAN_IFLAG_BUF5I (0x20)\r
+#define MCF_FlexCAN_IFLAG_BUF6I (0x40)\r
+#define MCF_FlexCAN_IFLAG_BUF7I (0x80)\r
+#define MCF_FlexCAN_IFLAG_BUF8I (0x100)\r
+#define MCF_FlexCAN_IFLAG_BUF9I (0x200)\r
+#define MCF_FlexCAN_IFLAG_BUF10I (0x400)\r
+#define MCF_FlexCAN_IFLAG_BUF11I (0x800)\r
+#define MCF_FlexCAN_IFLAG_BUF12I (0x1000)\r
+#define MCF_FlexCAN_IFLAG_BUF13I (0x2000)\r
+#define MCF_FlexCAN_IFLAG_BUF14I (0x4000)\r
+#define MCF_FlexCAN_IFLAG_BUF15I (0x8000)\r
+#define MCF_FlexCAN_IFLAG_BUF(x) (0x1<<(x))\r
+\r
+\r
+#endif /* __MCF52235_FlexCAN_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_GIACR_H__\r
+#define __MCF52235_GIACR_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Global Interrupt Acknowledge Control Registers Module (GIACR)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_GIACR_GSWIACK (*(vuint8 *)(&__IPSBAR[0xFE0]))\r
+#define MCF_GIACR_GL1IACK (*(vuint8 *)(&__IPSBAR[0xFE4]))\r
+#define MCF_GIACR_GL2IACK (*(vuint8 *)(&__IPSBAR[0xFE8]))\r
+#define MCF_GIACR_GL3IACK (*(vuint8 *)(&__IPSBAR[0xFEC]))\r
+#define MCF_GIACR_GL4IACK (*(vuint8 *)(&__IPSBAR[0xFF0]))\r
+#define MCF_GIACR_GL5IACK (*(vuint8 *)(&__IPSBAR[0xFF4]))\r
+#define MCF_GIACR_GL6IACK (*(vuint8 *)(&__IPSBAR[0xFF8]))\r
+#define MCF_GIACR_GL7IACK (*(vuint8 *)(&__IPSBAR[0xFFC]))\r
+#define MCF_GIACR_GLIACK(x) (*(vuint8 *)(&__IPSBAR[0xFE4 + ((x-1)*0x4)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_GIACR_GSWIACK */\r
+#define MCF_GIACR_GSWIACK_VECTOR(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GIACR_GLIACK */\r
+#define MCF_GIACR_GLIACK_VECTOR(x) (((x)&0xFF)<<0)\r
+\r
+\r
+#endif /* __MCF52235_GIACR_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_GPIO_H__\r
+#define __MCF52235_GPIO_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* General Purpose I/O (GPIO)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_GPIO_PORTNQ (*(vuint8 *)(&__IPSBAR[0x100008]))\r
+#define MCF_GPIO_DDRNQ (*(vuint8 *)(&__IPSBAR[0x100020]))\r
+#define MCF_GPIO_SETNQ (*(vuint8 *)(&__IPSBAR[0x100038]))\r
+#define MCF_GPIO_CLRNQ (*(vuint8 *)(&__IPSBAR[0x100050]))\r
+#define MCF_GPIO_PNQPAR (*(vuint16*)(&__IPSBAR[0x100068]))\r
+\r
+#define MCF_GPIO_PORTAN (*(vuint8 *)(&__IPSBAR[0x10000A]))\r
+#define MCF_GPIO_DDRAN (*(vuint8 *)(&__IPSBAR[0x100022]))\r
+#define MCF_GPIO_SETAN (*(vuint8 *)(&__IPSBAR[0x10003A]))\r
+#define MCF_GPIO_CLRAN (*(vuint8 *)(&__IPSBAR[0x100052]))\r
+#define MCF_GPIO_PANPAR (*(vuint8 *)(&__IPSBAR[0x10006A]))\r
+\r
+#define MCF_GPIO_PORTAS (*(vuint8 *)(&__IPSBAR[0x10000B]))\r
+#define MCF_GPIO_DDRAS (*(vuint8 *)(&__IPSBAR[0x100023]))\r
+#define MCF_GPIO_SETAS (*(vuint8 *)(&__IPSBAR[0x10003B]))\r
+#define MCF_GPIO_CLRAS (*(vuint8 *)(&__IPSBAR[0x100053]))\r
+#define MCF_GPIO_PASPAR (*(vuint8 *)(&__IPSBAR[0x10006B]))\r
+\r
+#define MCF_GPIO_PORTQS (*(vuint8 *)(&__IPSBAR[0x10000C]))\r
+#define MCF_GPIO_DDRQS (*(vuint8 *)(&__IPSBAR[0x100024]))\r
+#define MCF_GPIO_SETQS (*(vuint8 *)(&__IPSBAR[0x10003C]))\r
+#define MCF_GPIO_CLRQS (*(vuint8 *)(&__IPSBAR[0x100054]))\r
+#define MCF_GPIO_PQSPAR (*(vuint16*)(&__IPSBAR[0x10006C]))\r
+\r
+#define MCF_GPIO_PORTTA (*(vuint8 *)(&__IPSBAR[0x10000E]))\r
+#define MCF_GPIO_DDRTA (*(vuint8 *)(&__IPSBAR[0x100026]))\r
+#define MCF_GPIO_SETTA (*(vuint8 *)(&__IPSBAR[0x10003E]))\r
+#define MCF_GPIO_CLRTA (*(vuint8 *)(&__IPSBAR[0x100056]))\r
+#define MCF_GPIO_PTAPAR (*(vuint8 *)(&__IPSBAR[0x10006E]))\r
+\r
+#define MCF_GPIO_PORTTC (*(vuint8 *)(&__IPSBAR[0x10000F]))\r
+#define MCF_GPIO_DDRTC (*(vuint8 *)(&__IPSBAR[0x100027]))\r
+#define MCF_GPIO_SETTC (*(vuint8 *)(&__IPSBAR[0x10003F]))\r
+#define MCF_GPIO_CLRTC (*(vuint8 *)(&__IPSBAR[0x100057]))\r
+#define MCF_GPIO_PTCPAR (*(vuint8 *)(&__IPSBAR[0x10006F]))\r
+\r
+#define MCF_GPIO_PORTTD (*(vuint8 *)(&__IPSBAR[0x100010]))\r
+#define MCF_GPIO_DDRTD (*(vuint8 *)(&__IPSBAR[0x100028]))\r
+#define MCF_GPIO_SETTD (*(vuint8 *)(&__IPSBAR[0x100040]))\r
+#define MCF_GPIO_CLRTD (*(vuint8 *)(&__IPSBAR[0x100058]))\r
+#define MCF_GPIO_PTDPAR (*(vuint8 *)(&__IPSBAR[0x100070]))\r
+\r
+#define MCF_GPIO_PORTUA (*(vuint8 *)(&__IPSBAR[0x100011]))\r
+#define MCF_GPIO_DDRUA (*(vuint8 *)(&__IPSBAR[0x100029]))\r
+#define MCF_GPIO_SETUA (*(vuint8 *)(&__IPSBAR[0x100041]))\r
+#define MCF_GPIO_CLRUA (*(vuint8 *)(&__IPSBAR[0x100059]))\r
+#define MCF_GPIO_PUAPAR (*(vuint8 *)(&__IPSBAR[0x100071]))\r
+\r
+#define MCF_GPIO_PORTUB (*(vuint8 *)(&__IPSBAR[0x100012]))\r
+#define MCF_GPIO_DDRUB (*(vuint8 *)(&__IPSBAR[0x10002A]))\r
+#define MCF_GPIO_SETUB (*(vuint8 *)(&__IPSBAR[0x100042]))\r
+#define MCF_GPIO_CLRUB (*(vuint8 *)(&__IPSBAR[0x10005A]))\r
+#define MCF_GPIO_PUBPAR (*(vuint8 *)(&__IPSBAR[0x100072]))\r
+\r
+#define MCF_GPIO_PORTUC (*(vuint8 *)(&__IPSBAR[0x100013]))\r
+#define MCF_GPIO_DDRUC (*(vuint8 *)(&__IPSBAR[0x10002B]))\r
+#define MCF_GPIO_SETUC (*(vuint8 *)(&__IPSBAR[0x100043]))\r
+#define MCF_GPIO_CLRUC (*(vuint8 *)(&__IPSBAR[0x10005B]))\r
+#define MCF_GPIO_PUCPAR (*(vuint8 *)(&__IPSBAR[0x100073]))\r
+\r
+#define MCF_GPIO_PORTDD (*(vuint8 *)(&__IPSBAR[0x100014]))\r
+#define MCF_GPIO_DDRDD (*(vuint8 *)(&__IPSBAR[0x10002C]))\r
+#define MCF_GPIO_SETDD (*(vuint8 *)(&__IPSBAR[0x100044]))\r
+#define MCF_GPIO_CLRDD (*(vuint8 *)(&__IPSBAR[0x10005C]))\r
+#define MCF_GPIO_PDDPAR (*(vuint8 *)(&__IPSBAR[0x100074]))\r
+\r
+#define MCF_GPIO_PORTLD (*(vuint8 *)(&__IPSBAR[0x100015]))\r
+#define MCF_GPIO_DDRLD (*(vuint8 *)(&__IPSBAR[0x10002D]))\r
+#define MCF_GPIO_SETLD (*(vuint8 *)(&__IPSBAR[0x100045]))\r
+#define MCF_GPIO_CLRLD (*(vuint8 *)(&__IPSBAR[0x10005D]))\r
+#define MCF_GPIO_PLDPAR (*(vuint8 *)(&__IPSBAR[0x100075]))\r
+\r
+#define MCF_GPIO_PORTGP (*(vuint8 *)(&__IPSBAR[0x100016]))\r
+#define MCF_GPIO_DDRGP (*(vuint8 *)(&__IPSBAR[0x10002E]))\r
+#define MCF_GPIO_SETGP (*(vuint8 *)(&__IPSBAR[0x100046]))\r
+#define MCF_GPIO_CLRGP (*(vuint8 *)(&__IPSBAR[0x10005E]))\r
+#define MCF_GPIO_PGPPAR (*(vuint8 *)(&__IPSBAR[0x100076]))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTNQ */\r
+#define MCF_GPIO_PORTNQ_PORTNQ1 (0x2)\r
+#define MCF_GPIO_PORTNQ_PORTNQ2 (0x4)\r
+#define MCF_GPIO_PORTNQ_PORTNQ3 (0x8)\r
+#define MCF_GPIO_PORTNQ_PORTNQ4 (0x10)\r
+#define MCF_GPIO_PORTNQ_PORTNQ5 (0x20)\r
+#define MCF_GPIO_PORTNQ_PORTNQ6 (0x40)\r
+#define MCF_GPIO_PORTNQ_PORTNQ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRNQ */\r
+#define MCF_GPIO_DDRNQ_DDRNQ1 (0x2)\r
+#define MCF_GPIO_DDRNQ_DDRNQ2 (0x4)\r
+#define MCF_GPIO_DDRNQ_DDRNQ3 (0x8)\r
+#define MCF_GPIO_DDRNQ_DDRNQ4 (0x10)\r
+#define MCF_GPIO_DDRNQ_DDRNQ5 (0x20)\r
+#define MCF_GPIO_DDRNQ_DDRNQ6 (0x40)\r
+#define MCF_GPIO_DDRNQ_DDRNQ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETNQ */\r
+#define MCF_GPIO_SETNQ_SETNQ1 (0x2)\r
+#define MCF_GPIO_SETNQ_SETNQ2 (0x4)\r
+#define MCF_GPIO_SETNQ_SETNQ3 (0x8)\r
+#define MCF_GPIO_SETNQ_SETNQ4 (0x10)\r
+#define MCF_GPIO_SETNQ_SETNQ5 (0x20)\r
+#define MCF_GPIO_SETNQ_SETNQ6 (0x40)\r
+#define MCF_GPIO_SETNQ_SETNQ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRNQ */\r
+#define MCF_GPIO_CLRNQ_CLRNQ1 (0x2)\r
+#define MCF_GPIO_CLRNQ_CLRNQ2 (0x4)\r
+#define MCF_GPIO_CLRNQ_CLRNQ3 (0x8)\r
+#define MCF_GPIO_CLRNQ_CLRNQ4 (0x10)\r
+#define MCF_GPIO_CLRNQ_CLRNQ5 (0x20)\r
+#define MCF_GPIO_CLRNQ_CLRNQ6 (0x40)\r
+#define MCF_GPIO_CLRNQ_CLRNQ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PNQPAR */\r
+#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x4)\r
+#define MCF_GPIO_PNQPAR_IRQ1_SYNCA (0x8)\r
+#define MCF_GPIO_PNQPAR_IRQ1_PWM1 (0xC)\r
+#define MCF_GPIO_PNQPAR_PNQPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PNQPAR_IRQ2_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ2_IRQ2 (0x10)\r
+#define MCF_GPIO_PNQPAR_IRQ2_FEC_RXD3 (0x30)\r
+#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x40)\r
+#define MCF_GPIO_PNQPAR_IRQ3_FEC_RXD2 (0xC0)\r
+#define MCF_GPIO_PNQPAR_PNQPAR4(x) (((x)&0x3)<<0x8)\r
+#define MCF_GPIO_PNQPAR_IRQ4_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ4_IRQ4 (0x100)\r
+#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x3)<<0xA)\r
+#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x400)\r
+#define MCF_GPIO_PNQPAR_IRQ5_FEC_RXD1 (0xC00)\r
+#define MCF_GPIO_PNQPAR_PNQPAR6(x) (((x)&0x3)<<0xC)\r
+#define MCF_GPIO_PNQPAR_IRQ6_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ6_IRQ6 (0x1000)\r
+#define MCF_GPIO_PNQPAR_IRQ6_FEC_RXER (0x3000)\r
+#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x3)<<0xE)\r
+#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTAN */\r
+#define MCF_GPIO_PORTAN_PORTAN0 (0x1)\r
+#define MCF_GPIO_PORTAN_PORTAN1 (0x2)\r
+#define MCF_GPIO_PORTAN_PORTAN2 (0x4)\r
+#define MCF_GPIO_PORTAN_PORTAN3 (0x8)\r
+#define MCF_GPIO_PORTAN_PORTAN4 (0x10)\r
+#define MCF_GPIO_PORTAN_PORTAN5 (0x20)\r
+#define MCF_GPIO_PORTAN_PORTAN6 (0x40)\r
+#define MCF_GPIO_PORTAN_PORTAN7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRAN */\r
+#define MCF_GPIO_DDRAN_DDRAN0 (0x1)\r
+#define MCF_GPIO_DDRAN_DDRAN1 (0x2)\r
+#define MCF_GPIO_DDRAN_DDRAN2 (0x4)\r
+#define MCF_GPIO_DDRAN_DDRAN3 (0x8)\r
+#define MCF_GPIO_DDRAN_DDRAN4 (0x10)\r
+#define MCF_GPIO_DDRAN_DDRAN5 (0x20)\r
+#define MCF_GPIO_DDRAN_DDRAN6 (0x40)\r
+#define MCF_GPIO_DDRAN_DDRAN7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETAN */\r
+#define MCF_GPIO_SETAN_SETAN0 (0x1)\r
+#define MCF_GPIO_SETAN_SETAN1 (0x2)\r
+#define MCF_GPIO_SETAN_SETAN2 (0x4)\r
+#define MCF_GPIO_SETAN_SETAN3 (0x8)\r
+#define MCF_GPIO_SETAN_SETAN4 (0x10)\r
+#define MCF_GPIO_SETAN_SETAN5 (0x20)\r
+#define MCF_GPIO_SETAN_SETAN6 (0x40)\r
+#define MCF_GPIO_SETAN_SETAN7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRAN */\r
+#define MCF_GPIO_CLRAN_CLRAN0 (0x1)\r
+#define MCF_GPIO_CLRAN_CLRAN1 (0x2)\r
+#define MCF_GPIO_CLRAN_CLRAN2 (0x4)\r
+#define MCF_GPIO_CLRAN_CLRAN3 (0x8)\r
+#define MCF_GPIO_CLRAN_CLRAN4 (0x10)\r
+#define MCF_GPIO_CLRAN_CLRAN5 (0x20)\r
+#define MCF_GPIO_CLRAN_CLRAN6 (0x40)\r
+#define MCF_GPIO_CLRAN_CLRAN7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PANPAR */\r
+#define MCF_GPIO_PANPAR_PANPAR0 (0x1)\r
+#define MCF_GPIO_PANPAR_AN0_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN0_AN0 (0x1)\r
+#define MCF_GPIO_PANPAR_PANPAR1 (0x2)\r
+#define MCF_GPIO_PANPAR_AN1_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN1_AN1 (0x2)\r
+#define MCF_GPIO_PANPAR_PANPAR2 (0x4)\r
+#define MCF_GPIO_PANPAR_AN2_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN2_AN2 (0x4)\r
+#define MCF_GPIO_PANPAR_PANPAR3 (0x8)\r
+#define MCF_GPIO_PANPAR_AN3_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN3_AN3 (0x8)\r
+#define MCF_GPIO_PANPAR_PANPAR4 (0x10)\r
+#define MCF_GPIO_PANPAR_AN4_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN4_AN4 (0x10)\r
+#define MCF_GPIO_PANPAR_PANPAR5 (0x20)\r
+#define MCF_GPIO_PANPAR_AN5_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN5_AN5 (0x20)\r
+#define MCF_GPIO_PANPAR_PANPAR6 (0x40)\r
+#define MCF_GPIO_PANPAR_AN6_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN6_AN6 (0x40)\r
+#define MCF_GPIO_PANPAR_PANPAR7 (0x80)\r
+#define MCF_GPIO_PANPAR_AN7_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN7_AN7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTAS */\r
+#define MCF_GPIO_PORTAS_PORTAS0 (0x1)\r
+#define MCF_GPIO_PORTAS_PORTAS1 (0x2)\r
+#define MCF_GPIO_PORTAS_PORTAS2 (0x4)\r
+#define MCF_GPIO_PORTAS_PORTAS3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRAS */\r
+#define MCF_GPIO_DDRAS_DDRAS0 (0x1)\r
+#define MCF_GPIO_DDRAS_DDRAS1 (0x2)\r
+#define MCF_GPIO_DDRAS_DDRAS2 (0x4)\r
+#define MCF_GPIO_DDRAS_DDRAS3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETAS */\r
+#define MCF_GPIO_SETAS_SETAS0 (0x1)\r
+#define MCF_GPIO_SETAS_SETAS1 (0x2)\r
+#define MCF_GPIO_SETAS_SETAS2 (0x4)\r
+#define MCF_GPIO_SETAS_SETAS3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRAS */\r
+#define MCF_GPIO_CLRAS_CLRAS0 (0x1)\r
+#define MCF_GPIO_CLRAS_CLRAS1 (0x2)\r
+#define MCF_GPIO_CLRAS_CLRAS2 (0x4)\r
+#define MCF_GPIO_CLRAS_CLRAS3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PASPAR */\r
+#define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PASPAR_SCL_GPIO (0)\r
+#define MCF_GPIO_PASPAR_SCL_SCL (0x1)\r
+#define MCF_GPIO_PASPAR_SCL_CANTX (0x2)\r
+#define MCF_GPIO_PASPAR_SCL_UTXD2 (0x3)\r
+#define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PASPAR_SDA_GPIO (0)\r
+#define MCF_GPIO_PASPAR_SDA_SDA (0x4)\r
+#define MCF_GPIO_PASPAR_SDA_CANRX (0x8)\r
+#define MCF_GPIO_PASPAR_SDA_URXD2 (0xC)\r
+#define MCF_GPIO_PASPAR_PASPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PASPAR_SYNCB_GPIO (0)\r
+#define MCF_GPIO_PASPAR_SYNCB_SYNCB (0x10)\r
+#define MCF_GPIO_PASPAR_SYNCB_CANTX (0x20)\r
+#define MCF_GPIO_PASPAR_SYNCB_FEC_MDC (0x30)\r
+#define MCF_GPIO_PASPAR_PASPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PASPAR_SYNCA_GPIO (0)\r
+#define MCF_GPIO_PASPAR_SYNCA_SYNCA (0x40)\r
+#define MCF_GPIO_PASPAR_SYNCA_CANRX (0x80)\r
+#define MCF_GPIO_PASPAR_SYNC_FEC_MDIO (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTQS */\r
+#define MCF_GPIO_PORTQS_PORTQS0 (0x1)\r
+#define MCF_GPIO_PORTQS_PORTQS1 (0x2)\r
+#define MCF_GPIO_PORTQS_PORTQS2 (0x4)\r
+#define MCF_GPIO_PORTQS_PORTQS3 (0x8)\r
+#define MCF_GPIO_PORTQS_PORTQS4 (0x10)\r
+#define MCF_GPIO_PORTQS_PORTQS5 (0x20)\r
+#define MCF_GPIO_PORTQS_PORTQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRQS */\r
+#define MCF_GPIO_DDRQS_DDRQS0 (0x1)\r
+#define MCF_GPIO_DDRQS_DDRQS1 (0x2)\r
+#define MCF_GPIO_DDRQS_DDRQS2 (0x4)\r
+#define MCF_GPIO_DDRQS_DDRQS3 (0x8)\r
+#define MCF_GPIO_DDRQS_DDRQS4 (0x10)\r
+#define MCF_GPIO_DDRQS_DDRQS5 (0x20)\r
+#define MCF_GPIO_DDRQS_DDRQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETQS */\r
+#define MCF_GPIO_SETQS_SETQS0 (0x1)\r
+#define MCF_GPIO_SETQS_SETQS1 (0x2)\r
+#define MCF_GPIO_SETQS_SETQS2 (0x4)\r
+#define MCF_GPIO_SETQS_SETQS3 (0x8)\r
+#define MCF_GPIO_SETQS_SETQS4 (0x10)\r
+#define MCF_GPIO_SETQS_SETQS5 (0x20)\r
+#define MCF_GPIO_SETQS_SETQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRQS */\r
+#define MCF_GPIO_CLRQS_CLRQS0 (0x1)\r
+#define MCF_GPIO_CLRQS_CLRQS1 (0x2)\r
+#define MCF_GPIO_CLRQS_CLRQS2 (0x4)\r
+#define MCF_GPIO_CLRQS_CLRQS3 (0x8)\r
+#define MCF_GPIO_CLRQS_CLRQS4 (0x10)\r
+#define MCF_GPIO_CLRQS_CLRQS5 (0x20)\r
+#define MCF_GPIO_CLRQS_CLRQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PQSPAR */\r
+#define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PQSPAR_QSPI_DOUT_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_DOUT_DOUT (0x1)\r
+#define MCF_GPIO_PQSPAR_QSPI_DOUT_CANTX (0x2)\r
+#define MCF_GPIO_PQSPAR_QSPI_DOUT_UTXD1 (0x3)\r
+#define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PQSPAR_QSPI_DIN_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_DIN_DIN (0x4)\r
+#define MCF_GPIO_PQSPAR_QSPI_DIN_CANRX (0x8)\r
+#define MCF_GPIO_PQSPAR_QSPI_DIN_URXD1 (0xC)\r
+#define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PQSPAR_QSPI_CLK_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_CLK_CLK (0x10)\r
+#define MCF_GPIO_PQSPAR_QSPI_CLK_SCL (0x20)\r
+#define MCF_GPIO_PQSPAR_QSPI_CLK_URTS1 (0x30)\r
+#define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS0_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS0_CS0 (0x40)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS0_SDA (0x80)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS0_UCTS1 (0xC0)\r
+#define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x3)<<0x8)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS1_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS1_CS1 (0x100)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS1_FEC_TXEN (0x300)\r
+#define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x3)<<0xA)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS2_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS2_CS2 (0x400)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS2_FEC_TXCLK (0xC00)\r
+#define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x3)<<0xC)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS3_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS3_CS3 (0x1000)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS3_SYNCA (0x2000)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS3_SYNCB (0x3000)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTTA */\r
+#define MCF_GPIO_PORTTA_PORTTA0 (0x1)\r
+#define MCF_GPIO_PORTTA_PORTTA1 (0x2)\r
+#define MCF_GPIO_PORTTA_PORTTA2 (0x4)\r
+#define MCF_GPIO_PORTTA_PORTTA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRTA */\r
+#define MCF_GPIO_DDRTA_DDRTA0 (0x1)\r
+#define MCF_GPIO_DDRTA_DDRTA1 (0x2)\r
+#define MCF_GPIO_DDRTA_DDRTA2 (0x4)\r
+#define MCF_GPIO_DDRTA_DDRTA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETTA */\r
+#define MCF_GPIO_SETTA_SETTA0 (0x1)\r
+#define MCF_GPIO_SETTA_SETTA1 (0x2)\r
+#define MCF_GPIO_SETTA_SETTA2 (0x4)\r
+#define MCF_GPIO_SETTA_SETTA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRTA */\r
+#define MCF_GPIO_CLRTA_CLRTA0 (0x1)\r
+#define MCF_GPIO_CLRTA_CLRTA1 (0x2)\r
+#define MCF_GPIO_CLRTA_CLRTA2 (0x4)\r
+#define MCF_GPIO_CLRTA_CLRTA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PTAPAR */\r
+#define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PTAPAR_GPT0_GPIO (0)\r
+#define MCF_GPIO_PTAPAR_GPT0_GPT0 (0x1)\r
+#define MCF_GPIO_PTAPAR_GPT0_FEC_TXER (0x2)\r
+#define MCF_GPIO_PTAPAR_GPT0_PWM1 (0x3)\r
+#define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PTAPAR_GPT1_GPIO (0)\r
+#define MCF_GPIO_PTAPAR_GPT1_GPT1 (0x4)\r
+#define MCF_GPIO_PTAPAR_GPT1_FEC_TXD1 (0x8)\r
+#define MCF_GPIO_PTAPAR_GPT1_PWM3 (0xC)\r
+#define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PTAPAR_GPT2_GPIO (0)\r
+#define MCF_GPIO_PTAPAR_GPT2_GPT2 (0x10)\r
+#define MCF_GPIO_PTAPAR_GPT2_FEC_TXD2 (0x20)\r
+#define MCF_GPIO_PTAPAR_GPT2_PWM5 (0x30)\r
+#define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PTAPAR_GPT3_GPIO (0)\r
+#define MCF_GPIO_PTAPAR_GPT3_GPT3 (0x40)\r
+#define MCF_GPIO_PTAPAR_GPT3_FEC_TXD3 (0x80)\r
+#define MCF_GPIO_PTAPAR_GPT3_PWM7 (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTTC */\r
+#define MCF_GPIO_PORTTC_PORTTC0 (0x1)\r
+#define MCF_GPIO_PORTTC_PORTTC1 (0x2)\r
+#define MCF_GPIO_PORTTC_PORTTC2 (0x4)\r
+#define MCF_GPIO_PORTTC_PORTTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRTC */\r
+#define MCF_GPIO_DDRTC_DDRTC0 (0x1)\r
+#define MCF_GPIO_DDRTC_DDRTC1 (0x2)\r
+#define MCF_GPIO_DDRTC_DDRTC2 (0x4)\r
+#define MCF_GPIO_DDRTC_DDRTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETTC */\r
+#define MCF_GPIO_SETTC_SETTC0 (0x1)\r
+#define MCF_GPIO_SETTC_SETTC1 (0x2)\r
+#define MCF_GPIO_SETTC_SETTC2 (0x4)\r
+#define MCF_GPIO_SETTC_SETTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRTC */\r
+#define MCF_GPIO_CLRTC_CLRTC0 (0x1)\r
+#define MCF_GPIO_CLRTC_CLRTC1 (0x2)\r
+#define MCF_GPIO_CLRTC_CLRTC2 (0x4)\r
+#define MCF_GPIO_CLRTC_CLRTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PTCPAR */\r
+#define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PTCPAR_DTIN0_GPIO (0)\r
+#define MCF_GPIO_PTCPAR_DTIN0_DTIN0 (0x1)\r
+#define MCF_GPIO_PTCPAR_DTIN0_DTOUT0 (0x2)\r
+#define MCF_GPIO_PTCPAR_DTIN0_PWM0 (0x3)\r
+#define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PTCPAR_DTIN1_GPIO (0)\r
+#define MCF_GPIO_PTCPAR_DTIN1_DTIN1 (0x4)\r
+#define MCF_GPIO_PTCPAR_DTIN1_DTOUT1 (0x8)\r
+#define MCF_GPIO_PTCPAR_DTIN1_PWM2 (0xC)\r
+#define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PTCPAR_DTIN2_GPIO (0)\r
+#define MCF_GPIO_PTCPAR_DTIN2_DTIN2 (0x10)\r
+#define MCF_GPIO_PTCPAR_DTIN2_DTOUT2 (0x20)\r
+#define MCF_GPIO_PTCPAR_DTIN2_PWM4 (0x30)\r
+#define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PTCPAR_DTIN3_GPIO (0)\r
+#define MCF_GPIO_PTCPAR_DTIN3_DTIN3 (0x40)\r
+#define MCF_GPIO_PTCPAR_DTIN3_DTOUT3 (0x80)\r
+#define MCF_GPIO_PTCPAR_DTIN3_PWM6 (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTTD */\r
+#define MCF_GPIO_PORTTD_PORTTD0 (0x1)\r
+#define MCF_GPIO_PORTTD_PORTTD1 (0x2)\r
+#define MCF_GPIO_PORTTD_PORTTD2 (0x4)\r
+#define MCF_GPIO_PORTTD_PORTTD3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRTD */\r
+#define MCF_GPIO_DDRTD_DDRTD0 (0x1)\r
+#define MCF_GPIO_DDRTD_DDRTD1 (0x2)\r
+#define MCF_GPIO_DDRTD_DDRTD2 (0x4)\r
+#define MCF_GPIO_DDRTD_DDRTD3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETTD */\r
+#define MCF_GPIO_SETTD_SETTD0 (0x1)\r
+#define MCF_GPIO_SETTD_SETTD1 (0x2)\r
+#define MCF_GPIO_SETTD_SETTD2 (0x4)\r
+#define MCF_GPIO_SETTD_SETTD3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRTD */\r
+#define MCF_GPIO_CLRTD_CLRTD0 (0x1)\r
+#define MCF_GPIO_CLRTD_CLRTD1 (0x2)\r
+#define MCF_GPIO_CLRTD_CLRTD2 (0x4)\r
+#define MCF_GPIO_CLRTD_CLRTD3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PTDPAR */\r
+#define MCF_GPIO_PTDPAR_PTDPAR0 (0x1)\r
+#define MCF_GPIO_PTDPAR_PWM1_GPIO (0)\r
+#define MCF_GPIO_PTDPAR_PWM1_PWM1 (0x1)\r
+#define MCF_GPIO_PTDPAR_PTDPAR1 (0x2)\r
+#define MCF_GPIO_PTDPAR_PWM3_GPIO (0)\r
+#define MCF_GPIO_PTDPAR_PWM3_PWM3 (0x2)\r
+#define MCF_GPIO_PTDPAR_PTDPAR2 (0x4)\r
+#define MCF_GPIO_PTDPAR_PWM5_GPIO (0)\r
+#define MCF_GPIO_PTDPAR_PWM5_PWM5 (0x4)\r
+#define MCF_GPIO_PTDPAR_PTDPAR3 (0x8)\r
+#define MCF_GPIO_PTDPAR_PWM7_GPIO (0)\r
+#define MCF_GPIO_PTDPAR_PWM7_PWM7 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTUA */\r
+#define MCF_GPIO_PORTUA_PORTUA0 (0x1)\r
+#define MCF_GPIO_PORTUA_PORTUA1 (0x2)\r
+#define MCF_GPIO_PORTUA_PORTUA2 (0x4)\r
+#define MCF_GPIO_PORTUA_PORTUA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRUA */\r
+#define MCF_GPIO_DDRUA_DDRUA0 (0x1)\r
+#define MCF_GPIO_DDRUA_DDRUA1 (0x2)\r
+#define MCF_GPIO_DDRUA_DDRUA2 (0x4)\r
+#define MCF_GPIO_DDRUA_DDRUA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETUA */\r
+#define MCF_GPIO_SETUA_SETUA0 (0x1)\r
+#define MCF_GPIO_SETUA_SETUA1 (0x2)\r
+#define MCF_GPIO_SETUA_SETUA2 (0x4)\r
+#define MCF_GPIO_SETUA_SETUA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRUA */\r
+#define MCF_GPIO_CLRUA_CLRUA0 (0x1)\r
+#define MCF_GPIO_CLRUA_CLRUA1 (0x2)\r
+#define MCF_GPIO_CLRUA_CLRUA2 (0x4)\r
+#define MCF_GPIO_CLRUA_CLRUA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PUAPAR */\r
+#define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PUAPAR_UTXD0_GPIO (0)\r
+#define MCF_GPIO_PUAPAR_UTXD0_UTXD0 (0x1)\r
+#define MCF_GPIO_PUAPAR_UTXD0_FEC_CRS (0x3)\r
+#define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PUAPAR_URXD0_GPIO (0)\r
+#define MCF_GPIO_PUAPAR_URXD0_URXD0 (0x4)\r
+#define MCF_GPIO_PUAPAR_URXD0_FEC_RXD0 (0xC)\r
+#define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PUAPAR_URTS0_GPIO (0)\r
+#define MCF_GPIO_PUAPAR_URTS0_URTS0 (0x10)\r
+#define MCF_GPIO_PUAPAR_URTS0_CANTX (0x20)\r
+#define MCF_GPIO_PUAPAR_URTS0_FEC_RXDV (0x30)\r
+#define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PUAPAR_UCTS0_GPIO (0)\r
+#define MCF_GPIO_PUAPAR_UCTS0_UCTS0 (0x40)\r
+#define MCF_GPIO_PUAPAR_UCTS0_CANRX (0x80)\r
+#define MCF_GPIO_PUAPAR_UCTS0_FEC_RXCLK (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTUB */\r
+#define MCF_GPIO_PORTUB_PORTUB0 (0x1)\r
+#define MCF_GPIO_PORTUB_PORTUB1 (0x2)\r
+#define MCF_GPIO_PORTUB_PORTUB2 (0x4)\r
+#define MCF_GPIO_PORTUB_PORTUB3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRUB */\r
+#define MCF_GPIO_DDRUB_DDRUB0 (0x1)\r
+#define MCF_GPIO_DDRUB_DDRUB1 (0x2)\r
+#define MCF_GPIO_DDRUB_DDRUB2 (0x4)\r
+#define MCF_GPIO_DDRUB_DDRUB3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETUB */\r
+#define MCF_GPIO_SETUB_SETUB0 (0x1)\r
+#define MCF_GPIO_SETUB_SETUB1 (0x2)\r
+#define MCF_GPIO_SETUB_SETUB2 (0x4)\r
+#define MCF_GPIO_SETUB_SETUB3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRUB */\r
+#define MCF_GPIO_CLRUB_CLRUB0 (0x1)\r
+#define MCF_GPIO_CLRUB_CLRUB1 (0x2)\r
+#define MCF_GPIO_CLRUB_CLRUB2 (0x4)\r
+#define MCF_GPIO_CLRUB_CLRUB3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PUBPAR */\r
+#define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PUBPAR_UTXD1_GPIO (0)\r
+#define MCF_GPIO_PUBPAR_UTXD1_UTXD1 (0x1)\r
+#define MCF_GPIO_PUBPAR_UTXD1_FEC_COL (0x3)\r
+#define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PUBPAR_URXD1_GPIO (0)\r
+#define MCF_GPIO_PUBPAR_URXD1_URXD1 (0x4)\r
+#define MCF_GPIO_PUBPAR_URXD1_FEC_TXD0 (0xC)\r
+#define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PUBPAR_URTS1_GPIO (0)\r
+#define MCF_GPIO_PUBPAR_URTS1_URTS1 (0x10)\r
+#define MCF_GPIO_PUBPAR_URTS1_SYNCB (0x20)\r
+#define MCF_GPIO_PUBPAR_URTS1_UTXD2 (0x30)\r
+#define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PUBPAR_UCTS1_GPIO (0)\r
+#define MCF_GPIO_PUBPAR_UCTS1_UCTS1 (0x40)\r
+#define MCF_GPIO_PUBPAR_UCTS1_SYNCA (0x80)\r
+#define MCF_GPIO_PUBPAR_UCTS1_URXD2 (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTUC */\r
+#define MCF_GPIO_PORTUC_PORTUC0 (0x1)\r
+#define MCF_GPIO_PORTUC_PORTUC1 (0x2)\r
+#define MCF_GPIO_PORTUC_PORTUC2 (0x4)\r
+#define MCF_GPIO_PORTUC_PORTUC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRUC */\r
+#define MCF_GPIO_DDRUC_DDRUC0 (0x1)\r
+#define MCF_GPIO_DDRUC_DDRUC1 (0x2)\r
+#define MCF_GPIO_DDRUC_DDRUC2 (0x4)\r
+#define MCF_GPIO_DDRUC_DDRUC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETUC */\r
+#define MCF_GPIO_SETUC_SETUC0 (0x1)\r
+#define MCF_GPIO_SETUC_SETUC1 (0x2)\r
+#define MCF_GPIO_SETUC_SETUC2 (0x4)\r
+#define MCF_GPIO_SETUC_SETUC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRUC */\r
+#define MCF_GPIO_CLRUC_CLRUC0 (0x1)\r
+#define MCF_GPIO_CLRUC_CLRUC1 (0x2)\r
+#define MCF_GPIO_CLRUC_CLRUC2 (0x4)\r
+#define MCF_GPIO_CLRUC_CLRUC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PUCPAR */\r
+#define MCF_GPIO_PUCPAR_PUCPAR0 (0x1)\r
+#define MCF_GPIO_PUCPAR_UTXD2_GPIO (0)\r
+#define MCF_GPIO_PUCPAR_UTXD2_UTXD2 (0x1)\r
+#define MCF_GPIO_PUCPAR_PUCPAR1 (0x2)\r
+#define MCF_GPIO_PUCPAR_URXD2_GPIO (0)\r
+#define MCF_GPIO_PUCPAR_URXD2_URXD2 (0x2)\r
+#define MCF_GPIO_PUCPAR_PUCPAR2 (0x4)\r
+#define MCF_GPIO_PUCPAR_URTS2_GPIO (0)\r
+#define MCF_GPIO_PUCPAR_URTS2_URTS2 (0x4)\r
+#define MCF_GPIO_PUCPAR_PUCPAR3 (0x8)\r
+#define MCF_GPIO_PUCPAR_UCTS2_GPIO (0)\r
+#define MCF_GPIO_PUCPAR_UCTS2_UCTS2 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTDD */\r
+#define MCF_GPIO_PORTDD_PORTDD0 (0x1)\r
+#define MCF_GPIO_PORTDD_PORTDD1 (0x2)\r
+#define MCF_GPIO_PORTDD_PORTDD2 (0x4)\r
+#define MCF_GPIO_PORTDD_PORTDD3 (0x8)\r
+#define MCF_GPIO_PORTDD_PORTDD4 (0x10)\r
+#define MCF_GPIO_PORTDD_PORTDD5 (0x20)\r
+#define MCF_GPIO_PORTDD_PORTDD6 (0x40)\r
+#define MCF_GPIO_PORTDD_PORTDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRDD */\r
+#define MCF_GPIO_DDRDD_DDRDD0 (0x1)\r
+#define MCF_GPIO_DDRDD_DDRDD1 (0x2)\r
+#define MCF_GPIO_DDRDD_DDRDD2 (0x4)\r
+#define MCF_GPIO_DDRDD_DDRDD3 (0x8)\r
+#define MCF_GPIO_DDRDD_DDRDD4 (0x10)\r
+#define MCF_GPIO_DDRDD_DDRDD5 (0x20)\r
+#define MCF_GPIO_DDRDD_DDRDD6 (0x40)\r
+#define MCF_GPIO_DDRDD_DDRDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETDD */\r
+#define MCF_GPIO_SETDD_SETDD0 (0x1)\r
+#define MCF_GPIO_SETDD_SETDD1 (0x2)\r
+#define MCF_GPIO_SETDD_SETDD2 (0x4)\r
+#define MCF_GPIO_SETDD_SETDD3 (0x8)\r
+#define MCF_GPIO_SETDD_SETDD4 (0x10)\r
+#define MCF_GPIO_SETDD_SETDD5 (0x20)\r
+#define MCF_GPIO_SETDD_SETDD6 (0x40)\r
+#define MCF_GPIO_SETDD_SETDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRDD */\r
+#define MCF_GPIO_CLRDD_CLRDD0 (0x1)\r
+#define MCF_GPIO_CLRDD_CLRDD1 (0x2)\r
+#define MCF_GPIO_CLRDD_CLRDD2 (0x4)\r
+#define MCF_GPIO_CLRDD_CLRDD3 (0x8)\r
+#define MCF_GPIO_CLRDD_CLRDD4 (0x10)\r
+#define MCF_GPIO_CLRDD_CLRDD5 (0x20)\r
+#define MCF_GPIO_CLRDD_CLRDD6 (0x40)\r
+#define MCF_GPIO_CLRDD_CLRDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PDDPAR */\r
+#define MCF_GPIO_PDDPAR_PDDPAR0 (0x1)\r
+#define MCF_GPIO_PDDPAR_PDD0_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_PDD0_PST0 (0x1)\r
+#define MCF_GPIO_PDDPAR_PDDPAR1 (0x2)\r
+#define MCF_GPIO_PDDPAR_PDD1_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_PDD1_PST1 (0x2)\r
+#define MCF_GPIO_PDDPAR_PDDPAR2 (0x4)\r
+#define MCF_GPIO_PDDPAR_PDD2_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_PDD2_PST2 (0x4)\r
+#define MCF_GPIO_PDDPAR_PDDPAR3 (0x8)\r
+#define MCF_GPIO_PDDPAR_PDD3_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_PDD3_PST3 (0x8)\r
+#define MCF_GPIO_PDDPAR_PDDPAR4 (0x10)\r
+#define MCF_GPIO_PDDPAR_PDD4_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_PDD4_DDATA0 (0x10)\r
+#define MCF_GPIO_PDDPAR_PDDPAR5 (0x20)\r
+#define MCF_GPIO_PDDPAR_PDD5_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_PDD5_DDATA1 (0x20)\r
+#define MCF_GPIO_PDDPAR_PDDPAR6 (0x40)\r
+#define MCF_GPIO_PDDPAR_PDD6_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_PDD6_DDATA2 (0x40)\r
+#define MCF_GPIO_PDDPAR_PDDPAR7 (0x80)\r
+#define MCF_GPIO_PDDPAR_PDD7_GPIO (0)\r
+#define MCF_GPIO_PDDPAR_PDD7_DDATA3 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTLD */\r
+#define MCF_GPIO_PORTLD_PORTLD0 (0x1)\r
+#define MCF_GPIO_PORTLD_PORTLD1 (0x2)\r
+#define MCF_GPIO_PORTLD_PORTLD2 (0x4)\r
+#define MCF_GPIO_PORTLD_PORTLD3 (0x8)\r
+#define MCF_GPIO_PORTLD_PORTLD4 (0x10)\r
+#define MCF_GPIO_PORTLD_PORTLD5 (0x20)\r
+#define MCF_GPIO_PORTLD_PORTLD6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRLD */\r
+#define MCF_GPIO_DDRLD_DDRLD0 (0x1)\r
+#define MCF_GPIO_DDRLD_DDRLD1 (0x2)\r
+#define MCF_GPIO_DDRLD_DDRLD2 (0x4)\r
+#define MCF_GPIO_DDRLD_DDRLD3 (0x8)\r
+#define MCF_GPIO_DDRLD_DDRLD4 (0x10)\r
+#define MCF_GPIO_DDRLD_DDRLD5 (0x20)\r
+#define MCF_GPIO_DDRLD_DDRLD6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETLD */\r
+#define MCF_GPIO_SETLD_SETLD0 (0x1)\r
+#define MCF_GPIO_SETLD_SETLD1 (0x2)\r
+#define MCF_GPIO_SETLD_SETLD2 (0x4)\r
+#define MCF_GPIO_SETLD_SETLD3 (0x8)\r
+#define MCF_GPIO_SETLD_SETLD4 (0x10)\r
+#define MCF_GPIO_SETLD_SETLD5 (0x20)\r
+#define MCF_GPIO_SETLD_SETLD6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRLD */\r
+#define MCF_GPIO_CLRLD_CLRLD0 (0x1)\r
+#define MCF_GPIO_CLRLD_CLRLD1 (0x2)\r
+#define MCF_GPIO_CLRLD_CLRLD2 (0x4)\r
+#define MCF_GPIO_CLRLD_CLRLD3 (0x8)\r
+#define MCF_GPIO_CLRLD_CLRLD4 (0x10)\r
+#define MCF_GPIO_CLRLD_CLRLD5 (0x20)\r
+#define MCF_GPIO_CLRLD_CLRLD6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PLDPAR */\r
+#define MCF_GPIO_PLDPAR_PLDPAR0 (0x1)\r
+#define MCF_GPIO_PLDPAR_ACTLED_GPIO (0)\r
+#define MCF_GPIO_PLDPAR_ACTLED_ACTLED (0x1)\r
+#define MCF_GPIO_PLDPAR_PLDPAR1 (0x2)\r
+#define MCF_GPIO_PLDPAR_LINKLED_GPIO (0)\r
+#define MCF_GPIO_PLDPAR_LINKLED_LINKLED (0x2)\r
+#define MCF_GPIO_PLDPAR_PLDPAR2 (0x4)\r
+#define MCF_GPIO_PLDPAR_SPDLED_GPIO (0)\r
+#define MCF_GPIO_PLDPAR_SPDLED_SPDLED (0x4)\r
+#define MCF_GPIO_PLDPAR_PLDPAR3 (0x8)\r
+#define MCF_GPIO_PLDPAR_DUPLED_GPIO (0)\r
+#define MCF_GPIO_PLDPAR_DUPLED_DUPLED (0x8)\r
+#define MCF_GPIO_PLDPAR_PLDPAR4 (0x10)\r
+#define MCF_GPIO_PLDPAR_COLLED_GPIO (0)\r
+#define MCF_GPIO_PLDPAR_COLLED_COLLED (0x10)\r
+#define MCF_GPIO_PLDPAR_PLDPAR5 (0x20)\r
+#define MCF_GPIO_PLDPAR_RXLED_GPIO (0)\r
+#define MCF_GPIO_PLDPAR_RXLED_RXLED (0x20)\r
+#define MCF_GPIO_PLDPAR_PLDPAR6 (0x40)\r
+#define MCF_GPIO_PLDPAR_TXLED_GPIO (0)\r
+#define MCF_GPIO_PLDPAR_TXLED_TXLED (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTGP */\r
+#define MCF_GPIO_PORTGP_PORTGP0 (0x1)\r
+#define MCF_GPIO_PORTGP_PORTGP1 (0x2)\r
+#define MCF_GPIO_PORTGP_PORTGP2 (0x4)\r
+#define MCF_GPIO_PORTGP_PORTGP3 (0x8)\r
+#define MCF_GPIO_PORTGP_PORTGP4 (0x10)\r
+#define MCF_GPIO_PORTGP_PORTGP5 (0x20)\r
+#define MCF_GPIO_PORTGP_PORTGP6 (0x40)\r
+#define MCF_GPIO_PORTGP_PORTGP7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRGP */\r
+#define MCF_GPIO_DDRGP_DDRGP0 (0x1)\r
+#define MCF_GPIO_DDRGP_DDRGP1 (0x2)\r
+#define MCF_GPIO_DDRGP_DDRGP2 (0x4)\r
+#define MCF_GPIO_DDRGP_DDRGP3 (0x8)\r
+#define MCF_GPIO_DDRGP_DDRGP4 (0x10)\r
+#define MCF_GPIO_DDRGP_DDRGP5 (0x20)\r
+#define MCF_GPIO_DDRGP_DDRGP6 (0x40)\r
+#define MCF_GPIO_DDRGP_DDRGP7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETGP */\r
+#define MCF_GPIO_SETGP_SETGP0 (0x1)\r
+#define MCF_GPIO_SETGP_SETGP1 (0x2)\r
+#define MCF_GPIO_SETGP_SETGP2 (0x4)\r
+#define MCF_GPIO_SETGP_SETGP3 (0x8)\r
+#define MCF_GPIO_SETGP_SETGP4 (0x10)\r
+#define MCF_GPIO_SETGP_SETGP5 (0x20)\r
+#define MCF_GPIO_SETGP_SETGP6 (0x40)\r
+#define MCF_GPIO_SETGP_SETGP7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRGP */\r
+#define MCF_GPIO_CLRGP_CLRGP0 (0x1)\r
+#define MCF_GPIO_CLRGP_CLRGP1 (0x2)\r
+#define MCF_GPIO_CLRGP_CLRGP2 (0x4)\r
+#define MCF_GPIO_CLRGP_CLRGP3 (0x8)\r
+#define MCF_GPIO_CLRGP_CLRGP4 (0x10)\r
+#define MCF_GPIO_CLRGP_CLRGP5 (0x20)\r
+#define MCF_GPIO_CLRGP_CLRGP6 (0x40)\r
+#define MCF_GPIO_CLRGP_CLRGP7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PGPPAR */\r
+#define MCF_GPIO_PGPPAR_PGPPAR0 (0x1)\r
+#define MCF_GPIO_PGPPAR_IRQ8_GPIO (0)\r
+#define MCF_GPIO_PGPPAR_IRQ8_IRQ8 (0x1)\r
+#define MCF_GPIO_PGPPAR_PGPPAR1 (0x2)\r
+#define MCF_GPIO_PGPPAR_IRQ9_GPIO (0)\r
+#define MCF_GPIO_PGPPAR_IRQ9_IRQ9 (0x2)\r
+#define MCF_GPIO_PGPPAR_PGPPAR2 (0x4)\r
+#define MCF_GPIO_PGPPAR_IRQ10_GPIO (0)\r
+#define MCF_GPIO_PGPPAR_IRQ10_IRQ10 (0x4)\r
+#define MCF_GPIO_PGPPAR_PGPPAR3 (0x8)\r
+#define MCF_GPIO_PGPPAR_IRQ11_GPIO (0)\r
+#define MCF_GPIO_PGPPAR_IRQ11_IRQ11 (0x8)\r
+#define MCF_GPIO_PGPPAR_PGPPAR4 (0x10)\r
+#define MCF_GPIO_PGPPAR_IRQ12_GPIO (0)\r
+#define MCF_GPIO_PGPPAR_IRQ12_IRQ12 (0x10)\r
+#define MCF_GPIO_PGPPAR_PGPPAR5 (0x20)\r
+#define MCF_GPIO_PGPPAR_IRQ13_GPIO (0)\r
+#define MCF_GPIO_PGPPAR_IRQ13_IRQ13 (0x20)\r
+#define MCF_GPIO_PGPPAR_PGPPAR6 (0x40)\r
+#define MCF_GPIO_PGPPAR_IRQ14_GPIO (0)\r
+#define MCF_GPIO_PGPPAR_IRQ14_IRQ14 (0x40)\r
+#define MCF_GPIO_PGPPAR_PGPPAR7 (0x80)\r
+#define MCF_GPIO_PGPPAR_IRQ15_GPIO (0)\r
+#define MCF_GPIO_PGPPAR_IRQ15_IRQ15 (0x80)\r
+\r
+\r
+#endif /* __MCF52235_GPIO_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_GPTA_H__\r
+#define __MCF52235_GPTA_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* General Purpose Timer Module (GPT)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_GPTA_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1A0000]))\r
+#define MCF_GPTA_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1A0001]))\r
+#define MCF_GPTA_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1A0002]))\r
+#define MCF_GPTA_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1A0003]))\r
+#define MCF_GPTA_GPTCNT (*(vuint16*)(&__IPSBAR[0x1A0004]))\r
+#define MCF_GPTA_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1A0006]))\r
+#define MCF_GPTA_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1A0008]))\r
+#define MCF_GPTA_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1A0009]))\r
+#define MCF_GPTA_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1A000B]))\r
+#define MCF_GPTA_GPTIE (*(vuint8 *)(&__IPSBAR[0x1A000C]))\r
+#define MCF_GPTA_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1A000D]))\r
+#define MCF_GPTA_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1A000E]))\r
+#define MCF_GPTA_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1A000F]))\r
+#define MCF_GPTA_GPTC0 (*(vuint16*)(&__IPSBAR[0x1A0010]))\r
+#define MCF_GPTA_GPTC1 (*(vuint16*)(&__IPSBAR[0x1A0012]))\r
+#define MCF_GPTA_GPTC2 (*(vuint16*)(&__IPSBAR[0x1A0014]))\r
+#define MCF_GPTA_GPTC3 (*(vuint16*)(&__IPSBAR[0x1A0016]))\r
+#define MCF_GPTA_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1A0018]))\r
+#define MCF_GPTA_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1A0019]))\r
+#define MCF_GPTA_GPTPACNT (*(vuint16*)(&__IPSBAR[0x1A001A]))\r
+#define MCF_GPTA_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1A001D]))\r
+#define MCF_GPTA_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1A001E]))\r
+#define MCF_GPTA_GPTC(x) (*(vuint16*)(&__IPSBAR[0x1A0010 + ((x)*0x2)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTIOS */\r
+#define MCF_GPTA_GPTIOS_IOS0 (0x1)\r
+#define MCF_GPTA_GPTIOS_IOS1 (0x2)\r
+#define MCF_GPTA_GPTIOS_IOS2 (0x4)\r
+#define MCF_GPTA_GPTIOS_IOS3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTCFORC */\r
+#define MCF_GPTA_GPTCFORC_FOC0 (0x1)\r
+#define MCF_GPTA_GPTCFORC_FOC1 (0x2)\r
+#define MCF_GPTA_GPTCFORC_FOC2 (0x4)\r
+#define MCF_GPTA_GPTCFORC_FOC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTOC3M */\r
+#define MCF_GPTA_GPTOC3M_OC3M0 (0x1)\r
+#define MCF_GPTA_GPTOC3M_OC3M1 (0x2)\r
+#define MCF_GPTA_GPTOC3M_OC3M2 (0x4)\r
+#define MCF_GPTA_GPTOC3M_OC3M3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTOC3D */\r
+#define MCF_GPTA_GPTOC3D_OC3D0 (0x1)\r
+#define MCF_GPTA_GPTOC3D_OC3D1 (0x2)\r
+#define MCF_GPTA_GPTOC3D_OC3D2 (0x4)\r
+#define MCF_GPTA_GPTOC3D_OC3D3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTCNT */\r
+#define MCF_GPTA_GPTCNT_CNTR(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTSCR1 */\r
+#define MCF_GPTA_GPTSCR1_TFFCA (0x10)\r
+#define MCF_GPTA_GPTSCR1_GPTEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTTOV */\r
+#define MCF_GPTA_GPTTOV_TOV0 (0x1)\r
+#define MCF_GPTA_GPTTOV_TOV1 (0x2)\r
+#define MCF_GPTA_GPTTOV_TOV2 (0x4)\r
+#define MCF_GPTA_GPTTOV_TOV3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTCTL1 */\r
+#define MCF_GPTA_GPTCTL1_OL0 (0x1)\r
+#define MCF_GPTA_GPTCTL1_OM0 (0x2)\r
+#define MCF_GPTA_GPTCTL1_OL1 (0x4)\r
+#define MCF_GPTA_GPTCTL1_OM1 (0x8)\r
+#define MCF_GPTA_GPTCTL1_OL2 (0x10)\r
+#define MCF_GPTA_GPTCTL1_OM2 (0x20)\r
+#define MCF_GPTA_GPTCTL1_OL3 (0x40)\r
+#define MCF_GPTA_GPTCTL1_OM3 (0x80)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT0_NOTHING (0)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT0_TOGGLE (0x1)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT0_CLEAR (0x2)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT0_SET (0x3)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT1_NOTHING (0)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT1_TOGGLE (0x4)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT1_CLEAR (0x8)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT1_SET (0xC)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT2_NOTHING (0)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT2_TOGGLE (0x10)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT2_CLEAR (0x20)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT2_SET (0x30)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT3_NOTHING (0)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT3_TOGGLE (0x40)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT3_CLEAR (0x80)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT3_SET (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTCTL2 */\r
+#define MCF_GPTA_GPTCTL2_EDG0A (0x1)\r
+#define MCF_GPTA_GPTCTL2_EDG0B (0x2)\r
+#define MCF_GPTA_GPTCTL2_EDG1A (0x4)\r
+#define MCF_GPTA_GPTCTL2_EDG1B (0x8)\r
+#define MCF_GPTA_GPTCTL2_EDG2A (0x10)\r
+#define MCF_GPTA_GPTCTL2_EDG2B (0x20)\r
+#define MCF_GPTA_GPTCTL2_EDG3A (0x40)\r
+#define MCF_GPTA_GPTCTL2_EDG3B (0x80)\r
+#define MCF_GPTA_GPTCTL2_INPUT0_DISABLED (0)\r
+#define MCF_GPTA_GPTCTL2_INPUT0_RISING (0x1)\r
+#define MCF_GPTA_GPTCTL2_INPUT0_FALLING (0x2)\r
+#define MCF_GPTA_GPTCTL2_INPUT0_ANY (0x3)\r
+#define MCF_GPTA_GPTCTL2_INPUT1_DISABLED (0)\r
+#define MCF_GPTA_GPTCTL2_INPUT1_RISING (0x4)\r
+#define MCF_GPTA_GPTCTL2_INPUT1_FALLING (0x8)\r
+#define MCF_GPTA_GPTCTL2_INPUT1_ANY (0xC)\r
+#define MCF_GPTA_GPTCTL2_INPUT2_DISABLED (0)\r
+#define MCF_GPTA_GPTCTL2_INPUT2_RISING (0x10)\r
+#define MCF_GPTA_GPTCTL2_INPUT2_FALLING (0x20)\r
+#define MCF_GPTA_GPTCTL2_INPUT2_ANY (0x30)\r
+#define MCF_GPTA_GPTCTL2_INPUT3_DISABLED (0)\r
+#define MCF_GPTA_GPTCTL2_INPUT3_RISING (0x40)\r
+#define MCF_GPTA_GPTCTL2_INPUT3_FALLING (0x80)\r
+#define MCF_GPTA_GPTCTL2_INPUT3_ANY (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTIE */\r
+#define MCF_GPTA_GPTIE_CI0 (0x1)\r
+#define MCF_GPTA_GPTIE_CI1 (0x2)\r
+#define MCF_GPTA_GPTIE_CI2 (0x4)\r
+#define MCF_GPTA_GPTIE_CI3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTSCR2 */\r
+#define MCF_GPTA_GPTSCR2_PR(x) (((x)&0x7)<<0)\r
+#define MCF_GPTA_GPTSCR2_PR_1 (0)\r
+#define MCF_GPTA_GPTSCR2_PR_2 (0x1)\r
+#define MCF_GPTA_GPTSCR2_PR_4 (0x2)\r
+#define MCF_GPTA_GPTSCR2_PR_8 (0x3)\r
+#define MCF_GPTA_GPTSCR2_PR_16 (0x4)\r
+#define MCF_GPTA_GPTSCR2_PR_32 (0x5)\r
+#define MCF_GPTA_GPTSCR2_PR_64 (0x6)\r
+#define MCF_GPTA_GPTSCR2_PR_128 (0x7)\r
+#define MCF_GPTA_GPTSCR2_TCRE (0x8)\r
+#define MCF_GPTA_GPTSCR2_RDPT (0x10)\r
+#define MCF_GPTA_GPTSCR2_PUPT (0x20)\r
+#define MCF_GPTA_GPTSCR2_TOI (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTFLG1 */\r
+#define MCF_GPTA_GPTFLG1_CF0 (0x1)\r
+#define MCF_GPTA_GPTFLG1_CF1 (0x2)\r
+#define MCF_GPTA_GPTFLG1_CF2 (0x4)\r
+#define MCF_GPTA_GPTFLG1_CF3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTFLG2 */\r
+#define MCF_GPTA_GPTFLG2_TOF (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTC */\r
+#define MCF_GPTA_GPTC_CCNT(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTPACTL */\r
+#define MCF_GPTA_GPTPACTL_PAI (0x1)\r
+#define MCF_GPTA_GPTPACTL_PAOVI (0x2)\r
+#define MCF_GPTA_GPTPACTL_CLK(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPTA_GPTPACTL_CLK_GPTPR (0)\r
+#define MCF_GPTA_GPTPACTL_CLK_PACLK (0x1)\r
+#define MCF_GPTA_GPTPACTL_CLK_PACLK_256 (0x2)\r
+#define MCF_GPTA_GPTPACTL_CLK_PACLK_65536 (0x3)\r
+#define MCF_GPTA_GPTPACTL_PEDGE (0x10)\r
+#define MCF_GPTA_GPTPACTL_PAMOD (0x20)\r
+#define MCF_GPTA_GPTPACTL_PAE (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTPAFLG */\r
+#define MCF_GPTA_GPTPAFLG_PAIF (0x1)\r
+#define MCF_GPTA_GPTPAFLG_PAOVF (0x2)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTPACNT */\r
+#define MCF_GPTA_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTPORT */\r
+#define MCF_GPTA_GPTPORT_PORTT0 (0x1)\r
+#define MCF_GPTA_GPTPORT_PORTT1 (0x2)\r
+#define MCF_GPTA_GPTPORT_PORTT2 (0x4)\r
+#define MCF_GPTA_GPTPORT_PORTT3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTDDR */\r
+#define MCF_GPTA_GPTDDR_DDRT0 (0x1)\r
+#define MCF_GPTA_GPTDDR_DDRT1 (0x2)\r
+#define MCF_GPTA_GPTDDR_DDRT2 (0x4)\r
+#define MCF_GPTA_GPTDDR_DDRT3 (0x8)\r
+\r
+\r
+#endif /* __MCF52235_GPTA_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_I2C_H__\r
+#define __MCF52235_I2C_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* I2C Module (I2C)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_I2C_I2ADR (*(vuint8 *)(&__IPSBAR[0x300]))\r
+#define MCF_I2C_I2FDR (*(vuint8 *)(&__IPSBAR[0x304]))\r
+#define MCF_I2C_I2CR (*(vuint8 *)(&__IPSBAR[0x308]))\r
+#define MCF_I2C_I2SR (*(vuint8 *)(&__IPSBAR[0x30C]))\r
+#define MCF_I2C_I2DR (*(vuint8 *)(&__IPSBAR[0x310]))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2ADR */\r
+#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2FDR */\r
+#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2CR */\r
+#define MCF_I2C_I2CR_RSTA (0x4)\r
+#define MCF_I2C_I2CR_TXAK (0x8)\r
+#define MCF_I2C_I2CR_MTX (0x10)\r
+#define MCF_I2C_I2CR_MSTA (0x20)\r
+#define MCF_I2C_I2CR_IIEN (0x40)\r
+#define MCF_I2C_I2CR_IEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2SR */\r
+#define MCF_I2C_I2SR_RXAK (0x1)\r
+#define MCF_I2C_I2SR_IIF (0x2)\r
+#define MCF_I2C_I2SR_SRW (0x4)\r
+#define MCF_I2C_I2SR_IAL (0x10)\r
+#define MCF_I2C_I2SR_IBB (0x20)\r
+#define MCF_I2C_I2SR_IAAS (0x40)\r
+#define MCF_I2C_I2SR_ICF (0x80)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2DR */\r
+#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)\r
+\r
+\r
+#endif /* __MCF52235_I2C_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_INTC_H__\r
+#define __MCF52235_INTC_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Interrupt Controller (INTC)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_INTC0_IPRH (*(vuint32*)(&__IPSBAR[0xC00]))\r
+#define MCF_INTC0_IPRL (*(vuint32*)(&__IPSBAR[0xC04]))\r
+#define MCF_INTC0_IMRH (*(vuint32*)(&__IPSBAR[0xC08]))\r
+#define MCF_INTC0_IMRL (*(vuint32*)(&__IPSBAR[0xC0C]))\r
+#define MCF_INTC0_INTFRCH (*(vuint32*)(&__IPSBAR[0xC10]))\r
+#define MCF_INTC0_INTFRCL (*(vuint32*)(&__IPSBAR[0xC14]))\r
+#define MCF_INTC0_IRLR (*(vuint8 *)(&__IPSBAR[0xC18]))\r
+#define MCF_INTC0_IACKLPR (*(vuint8 *)(&__IPSBAR[0xC19]))\r
+#define MCF_INTC0_ICR01 (*(vuint8 *)(&__IPSBAR[0xC41]))\r
+#define MCF_INTC0_ICR02 (*(vuint8 *)(&__IPSBAR[0xC42]))\r
+#define MCF_INTC0_ICR03 (*(vuint8 *)(&__IPSBAR[0xC43]))\r
+#define MCF_INTC0_ICR04 (*(vuint8 *)(&__IPSBAR[0xC44]))\r
+#define MCF_INTC0_ICR05 (*(vuint8 *)(&__IPSBAR[0xC45]))\r
+#define MCF_INTC0_ICR06 (*(vuint8 *)(&__IPSBAR[0xC46]))\r
+#define MCF_INTC0_ICR07 (*(vuint8 *)(&__IPSBAR[0xC47]))\r
+#define MCF_INTC0_ICR08 (*(vuint8 *)(&__IPSBAR[0xC48]))\r
+#define MCF_INTC0_ICR09 (*(vuint8 *)(&__IPSBAR[0xC49]))\r
+#define MCF_INTC0_ICR10 (*(vuint8 *)(&__IPSBAR[0xC4A]))\r
+#define MCF_INTC0_ICR11 (*(vuint8 *)(&__IPSBAR[0xC4B]))\r
+#define MCF_INTC0_ICR12 (*(vuint8 *)(&__IPSBAR[0xC4C]))\r
+#define MCF_INTC0_ICR13 (*(vuint8 *)(&__IPSBAR[0xC4D]))\r
+#define MCF_INTC0_ICR14 (*(vuint8 *)(&__IPSBAR[0xC4E]))\r
+#define MCF_INTC0_ICR15 (*(vuint8 *)(&__IPSBAR[0xC4F]))\r
+#define MCF_INTC0_ICR16 (*(vuint8 *)(&__IPSBAR[0xC50]))\r
+#define MCF_INTC0_ICR17 (*(vuint8 *)(&__IPSBAR[0xC51]))\r
+#define MCF_INTC0_ICR18 (*(vuint8 *)(&__IPSBAR[0xC52]))\r
+#define MCF_INTC0_ICR19 (*(vuint8 *)(&__IPSBAR[0xC53]))\r
+#define MCF_INTC0_ICR20 (*(vuint8 *)(&__IPSBAR[0xC54]))\r
+#define MCF_INTC0_ICR21 (*(vuint8 *)(&__IPSBAR[0xC55]))\r
+#define MCF_INTC0_ICR22 (*(vuint8 *)(&__IPSBAR[0xC56]))\r
+#define MCF_INTC0_ICR23 (*(vuint8 *)(&__IPSBAR[0xC57]))\r
+#define MCF_INTC0_ICR24 (*(vuint8 *)(&__IPSBAR[0xC58]))\r
+#define MCF_INTC0_ICR25 (*(vuint8 *)(&__IPSBAR[0xC59]))\r
+#define MCF_INTC0_ICR26 (*(vuint8 *)(&__IPSBAR[0xC5A]))\r
+#define MCF_INTC0_ICR27 (*(vuint8 *)(&__IPSBAR[0xC5B]))\r
+#define MCF_INTC0_ICR28 (*(vuint8 *)(&__IPSBAR[0xC5C]))\r
+#define MCF_INTC0_ICR29 (*(vuint8 *)(&__IPSBAR[0xC5D]))\r
+#define MCF_INTC0_ICR30 (*(vuint8 *)(&__IPSBAR[0xC5E]))\r
+#define MCF_INTC0_ICR31 (*(vuint8 *)(&__IPSBAR[0xC5F]))\r
+#define MCF_INTC0_ICR32 (*(vuint8 *)(&__IPSBAR[0xC60]))\r
+#define MCF_INTC0_ICR33 (*(vuint8 *)(&__IPSBAR[0xC61]))\r
+#define MCF_INTC0_ICR34 (*(vuint8 *)(&__IPSBAR[0xC62]))\r
+#define MCF_INTC0_ICR35 (*(vuint8 *)(&__IPSBAR[0xC63]))\r
+#define MCF_INTC0_ICR36 (*(vuint8 *)(&__IPSBAR[0xC64]))\r
+#define MCF_INTC0_ICR37 (*(vuint8 *)(&__IPSBAR[0xC65]))\r
+#define MCF_INTC0_ICR38 (*(vuint8 *)(&__IPSBAR[0xC66]))\r
+#define MCF_INTC0_ICR39 (*(vuint8 *)(&__IPSBAR[0xC67]))\r
+#define MCF_INTC0_ICR40 (*(vuint8 *)(&__IPSBAR[0xC68]))\r
+#define MCF_INTC0_ICR41 (*(vuint8 *)(&__IPSBAR[0xC69]))\r
+#define MCF_INTC0_ICR42 (*(vuint8 *)(&__IPSBAR[0xC6A]))\r
+#define MCF_INTC0_ICR43 (*(vuint8 *)(&__IPSBAR[0xC6B]))\r
+#define MCF_INTC0_ICR44 (*(vuint8 *)(&__IPSBAR[0xC6C]))\r
+#define MCF_INTC0_ICR45 (*(vuint8 *)(&__IPSBAR[0xC6D]))\r
+#define MCF_INTC0_ICR46 (*(vuint8 *)(&__IPSBAR[0xC6E]))\r
+#define MCF_INTC0_ICR47 (*(vuint8 *)(&__IPSBAR[0xC6F]))\r
+#define MCF_INTC0_ICR48 (*(vuint8 *)(&__IPSBAR[0xC70]))\r
+#define MCF_INTC0_ICR49 (*(vuint8 *)(&__IPSBAR[0xC71]))\r
+#define MCF_INTC0_ICR50 (*(vuint8 *)(&__IPSBAR[0xC72]))\r
+#define MCF_INTC0_ICR51 (*(vuint8 *)(&__IPSBAR[0xC73]))\r
+#define MCF_INTC0_ICR52 (*(vuint8 *)(&__IPSBAR[0xC74]))\r
+#define MCF_INTC0_ICR53 (*(vuint8 *)(&__IPSBAR[0xC75]))\r
+#define MCF_INTC0_ICR54 (*(vuint8 *)(&__IPSBAR[0xC76]))\r
+#define MCF_INTC0_ICR55 (*(vuint8 *)(&__IPSBAR[0xC77]))\r
+#define MCF_INTC0_ICR56 (*(vuint8 *)(&__IPSBAR[0xC78]))\r
+#define MCF_INTC0_ICR57 (*(vuint8 *)(&__IPSBAR[0xC79]))\r
+#define MCF_INTC0_ICR58 (*(vuint8 *)(&__IPSBAR[0xC7A]))\r
+#define MCF_INTC0_ICR59 (*(vuint8 *)(&__IPSBAR[0xC7B]))\r
+#define MCF_INTC0_ICR60 (*(vuint8 *)(&__IPSBAR[0xC7C]))\r
+#define MCF_INTC0_ICR61 (*(vuint8 *)(&__IPSBAR[0xC7D]))\r
+#define MCF_INTC0_ICR62 (*(vuint8 *)(&__IPSBAR[0xC7E]))\r
+#define MCF_INTC0_ICR63 (*(vuint8 *)(&__IPSBAR[0xC7F]))\r
+#define MCF_INTC0_SWIACK (*(vuint8 *)(&__IPSBAR[0xCE0]))\r
+#define MCF_INTC0_L1IACK (*(vuint8 *)(&__IPSBAR[0xCE4]))\r
+#define MCF_INTC0_L2IACK (*(vuint8 *)(&__IPSBAR[0xCE8]))\r
+#define MCF_INTC0_L3IACK (*(vuint8 *)(&__IPSBAR[0xCEC]))\r
+#define MCF_INTC0_L4IACK (*(vuint8 *)(&__IPSBAR[0xCF0]))\r
+#define MCF_INTC0_L5IACK (*(vuint8 *)(&__IPSBAR[0xCF4]))\r
+#define MCF_INTC0_L6IACK (*(vuint8 *)(&__IPSBAR[0xCF8]))\r
+#define MCF_INTC0_L7IACK (*(vuint8 *)(&__IPSBAR[0xCFC]))\r
+#define MCF_INTC0_ICR(x) (*(vuint8 *)(&__IPSBAR[0xC41 + ((x-1)*0x1)]))\r
+#define MCF_INTC0_LIACK(x) (*(vuint8 *)(&__IPSBAR[0xCE4 + ((x-1)*0x4)]))\r
+\r
+#define MCF_INTC1_IPRH (*(vuint32*)(&__IPSBAR[0xD00]))\r
+#define MCF_INTC1_IPRL (*(vuint32*)(&__IPSBAR[0xD04]))\r
+#define MCF_INTC1_IMRH (*(vuint32*)(&__IPSBAR[0xD08]))\r
+#define MCF_INTC1_IMRL (*(vuint32*)(&__IPSBAR[0xD0C]))\r
+#define MCF_INTC1_INTFRCH (*(vuint32*)(&__IPSBAR[0xD10]))\r
+#define MCF_INTC1_INTFRCL (*(vuint32*)(&__IPSBAR[0xD14]))\r
+#define MCF_INTC1_IRLR (*(vuint8 *)(&__IPSBAR[0xD18]))\r
+#define MCF_INTC1_IACKLPR (*(vuint8 *)(&__IPSBAR[0xD19]))\r
+#define MCF_INTC1_ICR01 (*(vuint8 *)(&__IPSBAR[0xD41]))\r
+#define MCF_INTC1_ICR02 (*(vuint8 *)(&__IPSBAR[0xD42]))\r
+#define MCF_INTC1_ICR03 (*(vuint8 *)(&__IPSBAR[0xD43]))\r
+#define MCF_INTC1_ICR04 (*(vuint8 *)(&__IPSBAR[0xD44]))\r
+#define MCF_INTC1_ICR05 (*(vuint8 *)(&__IPSBAR[0xD45]))\r
+#define MCF_INTC1_ICR06 (*(vuint8 *)(&__IPSBAR[0xD46]))\r
+#define MCF_INTC1_ICR07 (*(vuint8 *)(&__IPSBAR[0xD47]))\r
+#define MCF_INTC1_ICR08 (*(vuint8 *)(&__IPSBAR[0xD48]))\r
+#define MCF_INTC1_ICR09 (*(vuint8 *)(&__IPSBAR[0xD49]))\r
+#define MCF_INTC1_ICR10 (*(vuint8 *)(&__IPSBAR[0xD4A]))\r
+#define MCF_INTC1_ICR11 (*(vuint8 *)(&__IPSBAR[0xD4B]))\r
+#define MCF_INTC1_ICR12 (*(vuint8 *)(&__IPSBAR[0xD4C]))\r
+#define MCF_INTC1_ICR13 (*(vuint8 *)(&__IPSBAR[0xD4D]))\r
+#define MCF_INTC1_ICR14 (*(vuint8 *)(&__IPSBAR[0xD4E]))\r
+#define MCF_INTC1_ICR15 (*(vuint8 *)(&__IPSBAR[0xD4F]))\r
+#define MCF_INTC1_ICR16 (*(vuint8 *)(&__IPSBAR[0xD50]))\r
+#define MCF_INTC1_ICR17 (*(vuint8 *)(&__IPSBAR[0xD51]))\r
+#define MCF_INTC1_ICR18 (*(vuint8 *)(&__IPSBAR[0xD52]))\r
+#define MCF_INTC1_ICR19 (*(vuint8 *)(&__IPSBAR[0xD53]))\r
+#define MCF_INTC1_ICR20 (*(vuint8 *)(&__IPSBAR[0xD54]))\r
+#define MCF_INTC1_ICR21 (*(vuint8 *)(&__IPSBAR[0xD55]))\r
+#define MCF_INTC1_ICR22 (*(vuint8 *)(&__IPSBAR[0xD56]))\r
+#define MCF_INTC1_ICR23 (*(vuint8 *)(&__IPSBAR[0xD57]))\r
+#define MCF_INTC1_ICR24 (*(vuint8 *)(&__IPSBAR[0xD58]))\r
+#define MCF_INTC1_ICR25 (*(vuint8 *)(&__IPSBAR[0xD59]))\r
+#define MCF_INTC1_ICR26 (*(vuint8 *)(&__IPSBAR[0xD5A]))\r
+#define MCF_INTC1_ICR27 (*(vuint8 *)(&__IPSBAR[0xD5B]))\r
+#define MCF_INTC1_ICR28 (*(vuint8 *)(&__IPSBAR[0xD5C]))\r
+#define MCF_INTC1_ICR29 (*(vuint8 *)(&__IPSBAR[0xD5D]))\r
+#define MCF_INTC1_ICR30 (*(vuint8 *)(&__IPSBAR[0xD5E]))\r
+#define MCF_INTC1_ICR31 (*(vuint8 *)(&__IPSBAR[0xD5F]))\r
+#define MCF_INTC1_ICR32 (*(vuint8 *)(&__IPSBAR[0xD60]))\r
+#define MCF_INTC1_ICR33 (*(vuint8 *)(&__IPSBAR[0xD61]))\r
+#define MCF_INTC1_ICR34 (*(vuint8 *)(&__IPSBAR[0xD62]))\r
+#define MCF_INTC1_ICR35 (*(vuint8 *)(&__IPSBAR[0xD63]))\r
+#define MCF_INTC1_ICR36 (*(vuint8 *)(&__IPSBAR[0xD64]))\r
+#define MCF_INTC1_ICR37 (*(vuint8 *)(&__IPSBAR[0xD65]))\r
+#define MCF_INTC1_ICR38 (*(vuint8 *)(&__IPSBAR[0xD66]))\r
+#define MCF_INTC1_ICR39 (*(vuint8 *)(&__IPSBAR[0xD67]))\r
+#define MCF_INTC1_ICR40 (*(vuint8 *)(&__IPSBAR[0xD68]))\r
+#define MCF_INTC1_ICR41 (*(vuint8 *)(&__IPSBAR[0xD69]))\r
+#define MCF_INTC1_ICR42 (*(vuint8 *)(&__IPSBAR[0xD6A]))\r
+#define MCF_INTC1_ICR43 (*(vuint8 *)(&__IPSBAR[0xD6B]))\r
+#define MCF_INTC1_ICR44 (*(vuint8 *)(&__IPSBAR[0xD6C]))\r
+#define MCF_INTC1_ICR45 (*(vuint8 *)(&__IPSBAR[0xD6D]))\r
+#define MCF_INTC1_ICR46 (*(vuint8 *)(&__IPSBAR[0xD6E]))\r
+#define MCF_INTC1_ICR47 (*(vuint8 *)(&__IPSBAR[0xD6F]))\r
+#define MCF_INTC1_ICR48 (*(vuint8 *)(&__IPSBAR[0xD70]))\r
+#define MCF_INTC1_ICR49 (*(vuint8 *)(&__IPSBAR[0xD71]))\r
+#define MCF_INTC1_ICR50 (*(vuint8 *)(&__IPSBAR[0xD72]))\r
+#define MCF_INTC1_ICR51 (*(vuint8 *)(&__IPSBAR[0xD73]))\r
+#define MCF_INTC1_ICR52 (*(vuint8 *)(&__IPSBAR[0xD74]))\r
+#define MCF_INTC1_ICR53 (*(vuint8 *)(&__IPSBAR[0xD75]))\r
+#define MCF_INTC1_ICR54 (*(vuint8 *)(&__IPSBAR[0xD76]))\r
+#define MCF_INTC1_ICR55 (*(vuint8 *)(&__IPSBAR[0xD77]))\r
+#define MCF_INTC1_ICR56 (*(vuint8 *)(&__IPSBAR[0xD78]))\r
+#define MCF_INTC1_ICR57 (*(vuint8 *)(&__IPSBAR[0xD79]))\r
+#define MCF_INTC1_ICR58 (*(vuint8 *)(&__IPSBAR[0xD7A]))\r
+#define MCF_INTC1_ICR59 (*(vuint8 *)(&__IPSBAR[0xD7B]))\r
+#define MCF_INTC1_ICR60 (*(vuint8 *)(&__IPSBAR[0xD7C]))\r
+#define MCF_INTC1_ICR61 (*(vuint8 *)(&__IPSBAR[0xD7D]))\r
+#define MCF_INTC1_ICR62 (*(vuint8 *)(&__IPSBAR[0xD7E]))\r
+#define MCF_INTC1_ICR63 (*(vuint8 *)(&__IPSBAR[0xD7F]))\r
+#define MCF_INTC1_SWIACK (*(vuint8 *)(&__IPSBAR[0xDE0]))\r
+#define MCF_INTC1_L1IACK (*(vuint8 *)(&__IPSBAR[0xDE4]))\r
+#define MCF_INTC1_L2IACK (*(vuint8 *)(&__IPSBAR[0xDE8]))\r
+#define MCF_INTC1_L3IACK (*(vuint8 *)(&__IPSBAR[0xDEC]))\r
+#define MCF_INTC1_L4IACK (*(vuint8 *)(&__IPSBAR[0xDF0]))\r
+#define MCF_INTC1_L5IACK (*(vuint8 *)(&__IPSBAR[0xDF4]))\r
+#define MCF_INTC1_L6IACK (*(vuint8 *)(&__IPSBAR[0xDF8]))\r
+#define MCF_INTC1_L7IACK (*(vuint8 *)(&__IPSBAR[0xDFC]))\r
+#define MCF_INTC1_ICR(x) (*(vuint8 *)(&__IPSBAR[0xD41 + ((x-1)*0x1)]))\r
+#define MCF_INTC1_LIACK(x) (*(vuint8 *)(&__IPSBAR[0xDE4 + ((x-1)*0x4)]))\r
+\r
+#define MCF_INTC_IPRH(x) (*(vuint32*)(&__IPSBAR[0xC00 + ((x)*0x100)]))\r
+#define MCF_INTC_IPRL(x) (*(vuint32*)(&__IPSBAR[0xC04 + ((x)*0x100)]))\r
+#define MCF_INTC_IMRH(x) (*(vuint32*)(&__IPSBAR[0xC08 + ((x)*0x100)]))\r
+#define MCF_INTC_IMRL(x) (*(vuint32*)(&__IPSBAR[0xC0C + ((x)*0x100)]))\r
+#define MCF_INTC_INTFRCH(x) (*(vuint32*)(&__IPSBAR[0xC10 + ((x)*0x100)]))\r
+#define MCF_INTC_INTFRCL(x) (*(vuint32*)(&__IPSBAR[0xC14 + ((x)*0x100)]))\r
+#define MCF_INTC_IRLR(x) (*(vuint8 *)(&__IPSBAR[0xC18 + ((x)*0x100)]))\r
+#define MCF_INTC_IACKLPR(x) (*(vuint8 *)(&__IPSBAR[0xC19 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR01(x) (*(vuint8 *)(&__IPSBAR[0xC41 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR02(x) (*(vuint8 *)(&__IPSBAR[0xC42 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR03(x) (*(vuint8 *)(&__IPSBAR[0xC43 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR04(x) (*(vuint8 *)(&__IPSBAR[0xC44 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR05(x) (*(vuint8 *)(&__IPSBAR[0xC45 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR06(x) (*(vuint8 *)(&__IPSBAR[0xC46 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR07(x) (*(vuint8 *)(&__IPSBAR[0xC47 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR08(x) (*(vuint8 *)(&__IPSBAR[0xC48 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR09(x) (*(vuint8 *)(&__IPSBAR[0xC49 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR10(x) (*(vuint8 *)(&__IPSBAR[0xC4A + ((x)*0x100)]))\r
+#define MCF_INTC_ICR11(x) (*(vuint8 *)(&__IPSBAR[0xC4B + ((x)*0x100)]))\r
+#define MCF_INTC_ICR12(x) (*(vuint8 *)(&__IPSBAR[0xC4C + ((x)*0x100)]))\r
+#define MCF_INTC_ICR13(x) (*(vuint8 *)(&__IPSBAR[0xC4D + ((x)*0x100)]))\r
+#define MCF_INTC_ICR14(x) (*(vuint8 *)(&__IPSBAR[0xC4E + ((x)*0x100)]))\r
+#define MCF_INTC_ICR15(x) (*(vuint8 *)(&__IPSBAR[0xC4F + ((x)*0x100)]))\r
+#define MCF_INTC_ICR16(x) (*(vuint8 *)(&__IPSBAR[0xC50 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR17(x) (*(vuint8 *)(&__IPSBAR[0xC51 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR18(x) (*(vuint8 *)(&__IPSBAR[0xC52 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR19(x) (*(vuint8 *)(&__IPSBAR[0xC53 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR20(x) (*(vuint8 *)(&__IPSBAR[0xC54 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR21(x) (*(vuint8 *)(&__IPSBAR[0xC55 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR22(x) (*(vuint8 *)(&__IPSBAR[0xC56 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR23(x) (*(vuint8 *)(&__IPSBAR[0xC57 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR24(x) (*(vuint8 *)(&__IPSBAR[0xC58 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR25(x) (*(vuint8 *)(&__IPSBAR[0xC59 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR26(x) (*(vuint8 *)(&__IPSBAR[0xC5A + ((x)*0x100)]))\r
+#define MCF_INTC_ICR27(x) (*(vuint8 *)(&__IPSBAR[0xC5B + ((x)*0x100)]))\r
+#define MCF_INTC_ICR28(x) (*(vuint8 *)(&__IPSBAR[0xC5C + ((x)*0x100)]))\r
+#define MCF_INTC_ICR29(x) (*(vuint8 *)(&__IPSBAR[0xC5D + ((x)*0x100)]))\r
+#define MCF_INTC_ICR30(x) (*(vuint8 *)(&__IPSBAR[0xC5E + ((x)*0x100)]))\r
+#define MCF_INTC_ICR31(x) (*(vuint8 *)(&__IPSBAR[0xC5F + ((x)*0x100)]))\r
+#define MCF_INTC_ICR32(x) (*(vuint8 *)(&__IPSBAR[0xC60 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR33(x) (*(vuint8 *)(&__IPSBAR[0xC61 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR34(x) (*(vuint8 *)(&__IPSBAR[0xC62 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR35(x) (*(vuint8 *)(&__IPSBAR[0xC63 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR36(x) (*(vuint8 *)(&__IPSBAR[0xC64 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR37(x) (*(vuint8 *)(&__IPSBAR[0xC65 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR38(x) (*(vuint8 *)(&__IPSBAR[0xC66 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR39(x) (*(vuint8 *)(&__IPSBAR[0xC67 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR40(x) (*(vuint8 *)(&__IPSBAR[0xC68 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR41(x) (*(vuint8 *)(&__IPSBAR[0xC69 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR42(x) (*(vuint8 *)(&__IPSBAR[0xC6A + ((x)*0x100)]))\r
+#define MCF_INTC_ICR43(x) (*(vuint8 *)(&__IPSBAR[0xC6B + ((x)*0x100)]))\r
+#define MCF_INTC_ICR44(x) (*(vuint8 *)(&__IPSBAR[0xC6C + ((x)*0x100)]))\r
+#define MCF_INTC_ICR45(x) (*(vuint8 *)(&__IPSBAR[0xC6D + ((x)*0x100)]))\r
+#define MCF_INTC_ICR46(x) (*(vuint8 *)(&__IPSBAR[0xC6E + ((x)*0x100)]))\r
+#define MCF_INTC_ICR47(x) (*(vuint8 *)(&__IPSBAR[0xC6F + ((x)*0x100)]))\r
+#define MCF_INTC_ICR48(x) (*(vuint8 *)(&__IPSBAR[0xC70 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR49(x) (*(vuint8 *)(&__IPSBAR[0xC71 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR50(x) (*(vuint8 *)(&__IPSBAR[0xC72 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR51(x) (*(vuint8 *)(&__IPSBAR[0xC73 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR52(x) (*(vuint8 *)(&__IPSBAR[0xC74 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR53(x) (*(vuint8 *)(&__IPSBAR[0xC75 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR54(x) (*(vuint8 *)(&__IPSBAR[0xC76 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR55(x) (*(vuint8 *)(&__IPSBAR[0xC77 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR56(x) (*(vuint8 *)(&__IPSBAR[0xC78 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR57(x) (*(vuint8 *)(&__IPSBAR[0xC79 + ((x)*0x100)]))\r
+#define MCF_INTC_ICR58(x) (*(vuint8 *)(&__IPSBAR[0xC7A + ((x)*0x100)]))\r
+#define MCF_INTC_ICR59(x) (*(vuint8 *)(&__IPSBAR[0xC7B + ((x)*0x100)]))\r
+#define MCF_INTC_ICR60(x) (*(vuint8 *)(&__IPSBAR[0xC7C + ((x)*0x100)]))\r
+#define MCF_INTC_ICR61(x) (*(vuint8 *)(&__IPSBAR[0xC7D + ((x)*0x100)]))\r
+#define MCF_INTC_ICR62(x) (*(vuint8 *)(&__IPSBAR[0xC7E + ((x)*0x100)]))\r
+#define MCF_INTC_ICR63(x) (*(vuint8 *)(&__IPSBAR[0xC7F + ((x)*0x100)]))\r
+#define MCF_INTC_SWIACK(x) (*(vuint8 *)(&__IPSBAR[0xCE0 + ((x)*0x100)]))\r
+#define MCF_INTC_L1IACK(x) (*(vuint8 *)(&__IPSBAR[0xCE4 + ((x)*0x100)]))\r
+#define MCF_INTC_L2IACK(x) (*(vuint8 *)(&__IPSBAR[0xCE8 + ((x)*0x100)]))\r
+#define MCF_INTC_L3IACK(x) (*(vuint8 *)(&__IPSBAR[0xCEC + ((x)*0x100)]))\r
+#define MCF_INTC_L4IACK(x) (*(vuint8 *)(&__IPSBAR[0xCF0 + ((x)*0x100)]))\r
+#define MCF_INTC_L5IACK(x) (*(vuint8 *)(&__IPSBAR[0xCF4 + ((x)*0x100)]))\r
+#define MCF_INTC_L6IACK(x) (*(vuint8 *)(&__IPSBAR[0xCF8 + ((x)*0x100)]))\r
+#define MCF_INTC_L7IACK(x) (*(vuint8 *)(&__IPSBAR[0xCFC + ((x)*0x100)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_INTC_IPRH */\r
+#define MCF_INTC_IPRH_INT32 (0x1)\r
+#define MCF_INTC_IPRH_INT33 (0x2)\r
+#define MCF_INTC_IPRH_INT34 (0x4)\r
+#define MCF_INTC_IPRH_INT35 (0x8)\r
+#define MCF_INTC_IPRH_INT36 (0x10)\r
+#define MCF_INTC_IPRH_INT37 (0x20)\r
+#define MCF_INTC_IPRH_INT38 (0x40)\r
+#define MCF_INTC_IPRH_INT39 (0x80)\r
+#define MCF_INTC_IPRH_INT40 (0x100)\r
+#define MCF_INTC_IPRH_INT41 (0x200)\r
+#define MCF_INTC_IPRH_INT42 (0x400)\r
+#define MCF_INTC_IPRH_INT43 (0x800)\r
+#define MCF_INTC_IPRH_INT44 (0x1000)\r
+#define MCF_INTC_IPRH_INT45 (0x2000)\r
+#define MCF_INTC_IPRH_INT46 (0x4000)\r
+#define MCF_INTC_IPRH_INT47 (0x8000)\r
+#define MCF_INTC_IPRH_INT48 (0x10000)\r
+#define MCF_INTC_IPRH_INT49 (0x20000)\r
+#define MCF_INTC_IPRH_INT50 (0x40000)\r
+#define MCF_INTC_IPRH_INT51 (0x80000)\r
+#define MCF_INTC_IPRH_INT52 (0x100000)\r
+#define MCF_INTC_IPRH_INT53 (0x200000)\r
+#define MCF_INTC_IPRH_INT54 (0x400000)\r
+#define MCF_INTC_IPRH_INT55 (0x800000)\r
+#define MCF_INTC_IPRH_INT56 (0x1000000)\r
+#define MCF_INTC_IPRH_INT57 (0x2000000)\r
+#define MCF_INTC_IPRH_INT58 (0x4000000)\r
+#define MCF_INTC_IPRH_INT59 (0x8000000)\r
+#define MCF_INTC_IPRH_INT60 (0x10000000)\r
+#define MCF_INTC_IPRH_INT61 (0x20000000)\r
+#define MCF_INTC_IPRH_INT62 (0x40000000)\r
+#define MCF_INTC_IPRH_INT63 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IPRL */\r
+#define MCF_INTC_IPRL_INT1 (0x2)\r
+#define MCF_INTC_IPRL_INT2 (0x4)\r
+#define MCF_INTC_IPRL_INT3 (0x8)\r
+#define MCF_INTC_IPRL_INT4 (0x10)\r
+#define MCF_INTC_IPRL_INT5 (0x20)\r
+#define MCF_INTC_IPRL_INT6 (0x40)\r
+#define MCF_INTC_IPRL_INT7 (0x80)\r
+#define MCF_INTC_IPRL_INT8 (0x100)\r
+#define MCF_INTC_IPRL_INT9 (0x200)\r
+#define MCF_INTC_IPRL_INT10 (0x400)\r
+#define MCF_INTC_IPRL_INT11 (0x800)\r
+#define MCF_INTC_IPRL_INT12 (0x1000)\r
+#define MCF_INTC_IPRL_INT13 (0x2000)\r
+#define MCF_INTC_IPRL_INT14 (0x4000)\r
+#define MCF_INTC_IPRL_INT15 (0x8000)\r
+#define MCF_INTC_IPRL_INT16 (0x10000)\r
+#define MCF_INTC_IPRL_INT17 (0x20000)\r
+#define MCF_INTC_IPRL_INT18 (0x40000)\r
+#define MCF_INTC_IPRL_INT19 (0x80000)\r
+#define MCF_INTC_IPRL_INT20 (0x100000)\r
+#define MCF_INTC_IPRL_INT21 (0x200000)\r
+#define MCF_INTC_IPRL_INT22 (0x400000)\r
+#define MCF_INTC_IPRL_INT23 (0x800000)\r
+#define MCF_INTC_IPRL_INT24 (0x1000000)\r
+#define MCF_INTC_IPRL_INT25 (0x2000000)\r
+#define MCF_INTC_IPRL_INT26 (0x4000000)\r
+#define MCF_INTC_IPRL_INT27 (0x8000000)\r
+#define MCF_INTC_IPRL_INT28 (0x10000000)\r
+#define MCF_INTC_IPRL_INT29 (0x20000000)\r
+#define MCF_INTC_IPRL_INT30 (0x40000000)\r
+#define MCF_INTC_IPRL_INT31 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IMRH */\r
+#define MCF_INTC_IMRH_INT_MASK32 (0x1)\r
+#define MCF_INTC_IMRH_INT_MASK33 (0x2)\r
+#define MCF_INTC_IMRH_INT_MASK34 (0x4)\r
+#define MCF_INTC_IMRH_INT_MASK35 (0x8)\r
+#define MCF_INTC_IMRH_INT_MASK36 (0x10)\r
+#define MCF_INTC_IMRH_INT_MASK37 (0x20)\r
+#define MCF_INTC_IMRH_INT_MASK38 (0x40)\r
+#define MCF_INTC_IMRH_INT_MASK39 (0x80)\r
+#define MCF_INTC_IMRH_INT_MASK40 (0x100)\r
+#define MCF_INTC_IMRH_INT_MASK41 (0x200)\r
+#define MCF_INTC_IMRH_INT_MASK42 (0x400)\r
+#define MCF_INTC_IMRH_INT_MASK43 (0x800)\r
+#define MCF_INTC_IMRH_INT_MASK44 (0x1000)\r
+#define MCF_INTC_IMRH_INT_MASK45 (0x2000)\r
+#define MCF_INTC_IMRH_INT_MASK46 (0x4000)\r
+#define MCF_INTC_IMRH_INT_MASK47 (0x8000)\r
+#define MCF_INTC_IMRH_INT_MASK48 (0x10000)\r
+#define MCF_INTC_IMRH_INT_MASK49 (0x20000)\r
+#define MCF_INTC_IMRH_INT_MASK50 (0x40000)\r
+#define MCF_INTC_IMRH_INT_MASK51 (0x80000)\r
+#define MCF_INTC_IMRH_INT_MASK52 (0x100000)\r
+#define MCF_INTC_IMRH_INT_MASK53 (0x200000)\r
+#define MCF_INTC_IMRH_INT_MASK54 (0x400000)\r
+#define MCF_INTC_IMRH_INT_MASK55 (0x800000)\r
+#define MCF_INTC_IMRH_INT_MASK56 (0x1000000)\r
+#define MCF_INTC_IMRH_INT_MASK57 (0x2000000)\r
+#define MCF_INTC_IMRH_INT_MASK58 (0x4000000)\r
+#define MCF_INTC_IMRH_INT_MASK59 (0x8000000)\r
+#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)\r
+#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)\r
+#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)\r
+#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IMRL */\r
+#define MCF_INTC_IMRL_MASKALL (0x1)\r
+#define MCF_INTC_IMRL_INT_MASK1 (0x2)\r
+#define MCF_INTC_IMRL_INT_MASK2 (0x4)\r
+#define MCF_INTC_IMRL_INT_MASK3 (0x8)\r
+#define MCF_INTC_IMRL_INT_MASK4 (0x10)\r
+#define MCF_INTC_IMRL_INT_MASK5 (0x20)\r
+#define MCF_INTC_IMRL_INT_MASK6 (0x40)\r
+#define MCF_INTC_IMRL_INT_MASK7 (0x80)\r
+#define MCF_INTC_IMRL_INT_MASK8 (0x100)\r
+#define MCF_INTC_IMRL_INT_MASK9 (0x200)\r
+#define MCF_INTC_IMRL_INT_MASK10 (0x400)\r
+#define MCF_INTC_IMRL_INT_MASK11 (0x800)\r
+#define MCF_INTC_IMRL_INT_MASK12 (0x1000)\r
+#define MCF_INTC_IMRL_INT_MASK13 (0x2000)\r
+#define MCF_INTC_IMRL_INT_MASK14 (0x4000)\r
+#define MCF_INTC_IMRL_INT_MASK15 (0x8000)\r
+#define MCF_INTC_IMRL_INT_MASK16 (0x10000)\r
+#define MCF_INTC_IMRL_INT_MASK17 (0x20000)\r
+#define MCF_INTC_IMRL_INT_MASK18 (0x40000)\r
+#define MCF_INTC_IMRL_INT_MASK19 (0x80000)\r
+#define MCF_INTC_IMRL_INT_MASK20 (0x100000)\r
+#define MCF_INTC_IMRL_INT_MASK21 (0x200000)\r
+#define MCF_INTC_IMRL_INT_MASK22 (0x400000)\r
+#define MCF_INTC_IMRL_INT_MASK23 (0x800000)\r
+#define MCF_INTC_IMRL_INT_MASK24 (0x1000000)\r
+#define MCF_INTC_IMRL_INT_MASK25 (0x2000000)\r
+#define MCF_INTC_IMRL_INT_MASK26 (0x4000000)\r
+#define MCF_INTC_IMRL_INT_MASK27 (0x8000000)\r
+#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)\r
+#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)\r
+#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)\r
+#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_INTFRCH */\r
+#define MCF_INTC_INTFRCH_INTFRC32 (0x1)\r
+#define MCF_INTC_INTFRCH_INTFRC33 (0x2)\r
+#define MCF_INTC_INTFRCH_INTFRC34 (0x4)\r
+#define MCF_INTC_INTFRCH_INTFRC35 (0x8)\r
+#define MCF_INTC_INTFRCH_INTFRC36 (0x10)\r
+#define MCF_INTC_INTFRCH_INTFRC37 (0x20)\r
+#define MCF_INTC_INTFRCH_INTFRC38 (0x40)\r
+#define MCF_INTC_INTFRCH_INTFRC39 (0x80)\r
+#define MCF_INTC_INTFRCH_INTFRC40 (0x100)\r
+#define MCF_INTC_INTFRCH_INTFRC41 (0x200)\r
+#define MCF_INTC_INTFRCH_INTFRC42 (0x400)\r
+#define MCF_INTC_INTFRCH_INTFRC43 (0x800)\r
+#define MCF_INTC_INTFRCH_INTFRC44 (0x1000)\r
+#define MCF_INTC_INTFRCH_INTFRC45 (0x2000)\r
+#define MCF_INTC_INTFRCH_INTFRC46 (0x4000)\r
+#define MCF_INTC_INTFRCH_INTFRC47 (0x8000)\r
+#define MCF_INTC_INTFRCH_INTFRC48 (0x10000)\r
+#define MCF_INTC_INTFRCH_INTFRC49 (0x20000)\r
+#define MCF_INTC_INTFRCH_INTFRC50 (0x40000)\r
+#define MCF_INTC_INTFRCH_INTFRC51 (0x80000)\r
+#define MCF_INTC_INTFRCH_INTFRC52 (0x100000)\r
+#define MCF_INTC_INTFRCH_INTFRC53 (0x200000)\r
+#define MCF_INTC_INTFRCH_INTFRC54 (0x400000)\r
+#define MCF_INTC_INTFRCH_INTFRC55 (0x800000)\r
+#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000)\r
+#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000)\r
+#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000)\r
+#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000)\r
+#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)\r
+#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)\r
+#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)\r
+#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_INTFRCL */\r
+#define MCF_INTC_INTFRCL_INTFRC1 (0x2)\r
+#define MCF_INTC_INTFRCL_INTFRC2 (0x4)\r
+#define MCF_INTC_INTFRCL_INTFRC3 (0x8)\r
+#define MCF_INTC_INTFRCL_INTFRC4 (0x10)\r
+#define MCF_INTC_INTFRCL_INTFRC5 (0x20)\r
+#define MCF_INTC_INTFRCL_INTFRC6 (0x40)\r
+#define MCF_INTC_INTFRCL_INTFRC7 (0x80)\r
+#define MCF_INTC_INTFRCL_INTFRC8 (0x100)\r
+#define MCF_INTC_INTFRCL_INTFRC9 (0x200)\r
+#define MCF_INTC_INTFRCL_INTFRC10 (0x400)\r
+#define MCF_INTC_INTFRCL_INTFRC11 (0x800)\r
+#define MCF_INTC_INTFRCL_INTFRC12 (0x1000)\r
+#define MCF_INTC_INTFRCL_INTFRC13 (0x2000)\r
+#define MCF_INTC_INTFRCL_INTFRC14 (0x4000)\r
+#define MCF_INTC_INTFRCL_INTFRC15 (0x8000)\r
+#define MCF_INTC_INTFRCL_INTFRC16 (0x10000)\r
+#define MCF_INTC_INTFRCL_INTFRC17 (0x20000)\r
+#define MCF_INTC_INTFRCL_INTFRC18 (0x40000)\r
+#define MCF_INTC_INTFRCL_INTFRC19 (0x80000)\r
+#define MCF_INTC_INTFRCL_INTFRC20 (0x100000)\r
+#define MCF_INTC_INTFRCL_INTFRC21 (0x200000)\r
+#define MCF_INTC_INTFRCL_INTFRC22 (0x400000)\r
+#define MCF_INTC_INTFRCL_INTFRC23 (0x800000)\r
+#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000)\r
+#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000)\r
+#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000)\r
+#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000)\r
+#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)\r
+#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)\r
+#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)\r
+#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IRLR */\r
+#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IACKLPR */\r
+#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0)\r
+#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4)\r
+\r
+/* Bit definitions and macros for MCF_INTC_ICR */\r
+#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0)\r
+#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3)\r
+\r
+/* Bit definitions and macros for MCF_INTC_SWIACK */\r
+#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_INTC_LIACK */\r
+#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)\r
+\r
+\r
+#endif /* __MCF52235_INTC_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_PAD_H__\r
+#define __MCF52235_PAD_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Common GPIO Registers\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_PAD_PWOR (*(vuint16*)(&__IPSBAR[0x100078]))\r
+#define MCF_PAD_PDSR1 (*(vuint16*)(&__IPSBAR[0x10007A]))\r
+#define MCF_PAD_PDSR0 (*(vuint32*)(&__IPSBAR[0x10007C]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_PAD_PWOR */\r
+#define MCF_PAD_PWOR_PWOR0 (0x1)\r
+#define MCF_PAD_PWOR_PWOR1 (0x2)\r
+#define MCF_PAD_PWOR_PWOR2 (0x4)\r
+#define MCF_PAD_PWOR_PWOR3 (0x8)\r
+#define MCF_PAD_PWOR_PWOR4 (0x10)\r
+#define MCF_PAD_PWOR_PWOR5 (0x20)\r
+#define MCF_PAD_PWOR_PWOR6 (0x40)\r
+#define MCF_PAD_PWOR_PWOR7 (0x80)\r
+#define MCF_PAD_PWOR_PWOR8 (0x100)\r
+#define MCF_PAD_PWOR_PWOR9 (0x200)\r
+#define MCF_PAD_PWOR_PWOR10 (0x400)\r
+#define MCF_PAD_PWOR_PWOR11 (0x800)\r
+#define MCF_PAD_PWOR_PWOR12 (0x1000)\r
+#define MCF_PAD_PWOR_PWOR13 (0x2000)\r
+#define MCF_PAD_PWOR_PWOR14 (0x4000)\r
+#define MCF_PAD_PWOR_PWOR15 (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PDSR1 */\r
+#define MCF_PAD_PDSR1_PDSR32 (0x1)\r
+#define MCF_PAD_PDSR1_PDSR33 (0x2)\r
+#define MCF_PAD_PDSR1_PDSR34 (0x4)\r
+#define MCF_PAD_PDSR1_PDSR35 (0x8)\r
+#define MCF_PAD_PDSR1_PDSR36 (0x10)\r
+#define MCF_PAD_PDSR1_PDSR37 (0x20)\r
+#define MCF_PAD_PDSR1_PDSR38 (0x40)\r
+#define MCF_PAD_PDSR1_PDSR39 (0x80)\r
+#define MCF_PAD_PDSR1_PDSR40 (0x100)\r
+#define MCF_PAD_PDSR1_PDSR41 (0x200)\r
+#define MCF_PAD_PDSR1_PDSR42 (0x400)\r
+#define MCF_PAD_PDSR1_PDSR43 (0x800)\r
+#define MCF_PAD_PDSR1_PDSR44 (0x1000)\r
+#define MCF_PAD_PDSR1_PDSR45 (0x2000)\r
+#define MCF_PAD_PDSR1_PDSR46 (0x4000)\r
+#define MCF_PAD_PDSR1_PDSR47 (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PDSR0 */\r
+#define MCF_PAD_PDSR0_PDSR0 (0x1)\r
+#define MCF_PAD_PDSR0_PDSR1 (0x2)\r
+#define MCF_PAD_PDSR0_PDSR2 (0x4)\r
+#define MCF_PAD_PDSR0_PDSR3 (0x8)\r
+#define MCF_PAD_PDSR0_PDSR4 (0x10)\r
+#define MCF_PAD_PDSR0_PDSR5 (0x20)\r
+#define MCF_PAD_PDSR0_PDSR6 (0x40)\r
+#define MCF_PAD_PDSR0_PDSR7 (0x80)\r
+#define MCF_PAD_PDSR0_PDSR8 (0x100)\r
+#define MCF_PAD_PDSR0_PDSR9 (0x200)\r
+#define MCF_PAD_PDSR0_PDSR10 (0x400)\r
+#define MCF_PAD_PDSR0_PDSR11 (0x800)\r
+#define MCF_PAD_PDSR0_PDSR12 (0x1000)\r
+#define MCF_PAD_PDSR0_PDSR13 (0x2000)\r
+#define MCF_PAD_PDSR0_PDSR14 (0x4000)\r
+#define MCF_PAD_PDSR0_PDSR15 (0x8000)\r
+#define MCF_PAD_PDSR0_PDSR16 (0x10000)\r
+#define MCF_PAD_PDSR0_PDSR17 (0x20000)\r
+#define MCF_PAD_PDSR0_PDSR18 (0x40000)\r
+#define MCF_PAD_PDSR0_PDSR19 (0x80000)\r
+#define MCF_PAD_PDSR0_PDSR20 (0x100000)\r
+#define MCF_PAD_PDSR0_PDSR21 (0x200000)\r
+#define MCF_PAD_PDSR0_PDSR22 (0x400000)\r
+#define MCF_PAD_PDSR0_PDSR23 (0x800000)\r
+#define MCF_PAD_PDSR0_PDSR24 (0x1000000)\r
+#define MCF_PAD_PDSR0_PDSR25 (0x2000000)\r
+#define MCF_PAD_PDSR0_PDSR26 (0x4000000)\r
+#define MCF_PAD_PDSR0_PDSR27 (0x8000000)\r
+#define MCF_PAD_PDSR0_PDSR28 (0x10000000)\r
+#define MCF_PAD_PDSR0_PDSR29 (0x20000000)\r
+#define MCF_PAD_PDSR0_PDSR30 (0x40000000)\r
+#define MCF_PAD_PDSR0_PDSR31 (0x80000000)\r
+\r
+\r
+#endif /* __MCF52235_PAD_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_PIT_H__\r
+#define __MCF52235_PIT_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Programmable Interrupt Timer (PIT)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_PIT0_PCSR (*(vuint16*)(&__IPSBAR[0x150000]))\r
+#define MCF_PIT0_PMR (*(vuint16*)(&__IPSBAR[0x150002]))\r
+#define MCF_PIT0_PCNTR (*(vuint16*)(&__IPSBAR[0x150004]))\r
+\r
+#define MCF_PIT1_PCSR (*(vuint16*)(&__IPSBAR[0x160000]))\r
+#define MCF_PIT1_PMR (*(vuint16*)(&__IPSBAR[0x160002]))\r
+#define MCF_PIT1_PCNTR (*(vuint16*)(&__IPSBAR[0x160004]))\r
+\r
+#define MCF_PIT_PCSR(x) (*(vuint16*)(&__IPSBAR[0x150000 + ((x)*0x10000)]))\r
+#define MCF_PIT_PMR(x) (*(vuint16*)(&__IPSBAR[0x150002 + ((x)*0x10000)]))\r
+#define MCF_PIT_PCNTR(x) (*(vuint16*)(&__IPSBAR[0x150004 + ((x)*0x10000)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_PIT_PCSR */\r
+#define MCF_PIT_PCSR_EN (0x1)\r
+#define MCF_PIT_PCSR_RLD (0x2)\r
+#define MCF_PIT_PCSR_PIF (0x4)\r
+#define MCF_PIT_PCSR_PIE (0x8)\r
+#define MCF_PIT_PCSR_OVW (0x10)\r
+#define MCF_PIT_PCSR_DBG (0x20)\r
+#define MCF_PIT_PCSR_DOZE (0x40)\r
+#define MCF_PIT_PCSR_PRE(x) (((x)&0xF)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_PIT_PMR */\r
+#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PIT_PCNTR */\r
+#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52235_PIT_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_PMM_H__\r
+#define __MCF52235_PMM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Power Management (PMM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_PMM_LPICR (*(vuint8 *)(&__IPSBAR[0x12]))\r
+#define MCF_PMM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_PMM_LPICR */\r
+#define MCF_PMM_LPICR_XLPM_IPL(x) (((x)&0x7)<<0x4)\r
+#define MCF_PMM_LPICR_ENBSTOP (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PMM_LPCR */\r
+#define MCF_PMM_LPCR_LVDSE (0x2)\r
+#define MCF_PMM_LPCR_STPMD(x) (((x)&0x3)<<0x3)\r
+#define MCF_PMM_LPCR_STPMD_SYS_DISABLED (0)\r
+#define MCF_PMM_LPCR_STPMD_SYS_CLKOUT_DISABLED (0x8)\r
+#define MCF_PMM_LPCR_STPMD_ONLY_OSC_ENABLED (0x10)\r
+#define MCF_PMM_LPCR_STPMD_ALL_DISABLED (0x18)\r
+#define MCF_PMM_LPCR_LPMD(x) (((x)&0x3)<<0x6)\r
+#define MCF_PMM_LPCR_LPMD_RUN (0)\r
+#define MCF_PMM_LPCR_LPMD_DOZE (0x40)\r
+#define MCF_PMM_LPCR_LPMD_WAIT (0x80)\r
+#define MCF_PMM_LPCR_LPMD_STOP (0xC0)\r
+\r
+\r
+#endif /* __MCF52235_PMM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_PWM_H__\r
+#define __MCF52235_PWM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Pulse Width Modulation (PWM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_PWM_PWME (*(vuint8 *)(&__IPSBAR[0x1B0000]))\r
+#define MCF_PWM_PWMPOL (*(vuint8 *)(&__IPSBAR[0x1B0001]))\r
+#define MCF_PWM_PWMCLK (*(vuint8 *)(&__IPSBAR[0x1B0002]))\r
+#define MCF_PWM_PWMPRCLK (*(vuint8 *)(&__IPSBAR[0x1B0003]))\r
+#define MCF_PWM_PWMCAE (*(vuint8 *)(&__IPSBAR[0x1B0004]))\r
+#define MCF_PWM_PWMCTL (*(vuint8 *)(&__IPSBAR[0x1B0005]))\r
+#define MCF_PWM_PWMSCLA (*(vuint8 *)(&__IPSBAR[0x1B0008]))\r
+#define MCF_PWM_PWMSCLB (*(vuint8 *)(&__IPSBAR[0x1B0009]))\r
+#define MCF_PWM_PWMCNT0 (*(vuint8 *)(&__IPSBAR[0x1B000C]))\r
+#define MCF_PWM_PWMCNT1 (*(vuint8 *)(&__IPSBAR[0x1B000D]))\r
+#define MCF_PWM_PWMCNT2 (*(vuint8 *)(&__IPSBAR[0x1B000E]))\r
+#define MCF_PWM_PWMCNT3 (*(vuint8 *)(&__IPSBAR[0x1B000F]))\r
+#define MCF_PWM_PWMCNT4 (*(vuint8 *)(&__IPSBAR[0x1B0010]))\r
+#define MCF_PWM_PWMCNT5 (*(vuint8 *)(&__IPSBAR[0x1B0011]))\r
+#define MCF_PWM_PWMCNT6 (*(vuint8 *)(&__IPSBAR[0x1B0012]))\r
+#define MCF_PWM_PWMCNT7 (*(vuint8 *)(&__IPSBAR[0x1B0013]))\r
+#define MCF_PWM_PWMPER0 (*(vuint8 *)(&__IPSBAR[0x1B0014]))\r
+#define MCF_PWM_PWMPER1 (*(vuint8 *)(&__IPSBAR[0x1B0015]))\r
+#define MCF_PWM_PWMPER2 (*(vuint8 *)(&__IPSBAR[0x1B0016]))\r
+#define MCF_PWM_PWMPER3 (*(vuint8 *)(&__IPSBAR[0x1B0017]))\r
+#define MCF_PWM_PWMPER4 (*(vuint8 *)(&__IPSBAR[0x1B0018]))\r
+#define MCF_PWM_PWMPER5 (*(vuint8 *)(&__IPSBAR[0x1B0019]))\r
+#define MCF_PWM_PWMPER6 (*(vuint8 *)(&__IPSBAR[0x1B001A]))\r
+#define MCF_PWM_PWMPER7 (*(vuint8 *)(&__IPSBAR[0x1B001B]))\r
+#define MCF_PWM_PWMDTY0 (*(vuint8 *)(&__IPSBAR[0x1B001C]))\r
+#define MCF_PWM_PWMDTY1 (*(vuint8 *)(&__IPSBAR[0x1B001D]))\r
+#define MCF_PWM_PWMDTY2 (*(vuint8 *)(&__IPSBAR[0x1B001E]))\r
+#define MCF_PWM_PWMDTY3 (*(vuint8 *)(&__IPSBAR[0x1B001F]))\r
+#define MCF_PWM_PWMDTY4 (*(vuint8 *)(&__IPSBAR[0x1B0020]))\r
+#define MCF_PWM_PWMDTY5 (*(vuint8 *)(&__IPSBAR[0x1B0021]))\r
+#define MCF_PWM_PWMDTY6 (*(vuint8 *)(&__IPSBAR[0x1B0022]))\r
+#define MCF_PWM_PWMDTY7 (*(vuint8 *)(&__IPSBAR[0x1B0023]))\r
+#define MCF_PWM_PWMSDN (*(vuint8 *)(&__IPSBAR[0x1B0024]))\r
+#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(&__IPSBAR[0x1B000C + ((x)*0x1)]))\r
+#define MCF_PWM_PWMPER(x) (*(vuint8 *)(&__IPSBAR[0x1B0014 + ((x)*0x1)]))\r
+#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(&__IPSBAR[0x1B001C + ((x)*0x1)]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWME */\r
+#define MCF_PWM_PWME_PWME0 (0x1)\r
+#define MCF_PWM_PWME_PWME1 (0x2)\r
+#define MCF_PWM_PWME_PWME2 (0x4)\r
+#define MCF_PWM_PWME_PWME3 (0x8)\r
+#define MCF_PWM_PWME_PWME4 (0x10)\r
+#define MCF_PWM_PWME_PWME5 (0x20)\r
+#define MCF_PWM_PWME_PWME6 (0x40)\r
+#define MCF_PWM_PWME_PWME7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMPOL */\r
+#define MCF_PWM_PWMPOL_PPOL0 (0x1)\r
+#define MCF_PWM_PWMPOL_PPOL1 (0x2)\r
+#define MCF_PWM_PWMPOL_PPOL2 (0x4)\r
+#define MCF_PWM_PWMPOL_PPOL3 (0x8)\r
+#define MCF_PWM_PWMPOL_PPOL4 (0x10)\r
+#define MCF_PWM_PWMPOL_PPOL5 (0x20)\r
+#define MCF_PWM_PWMPOL_PPOL6 (0x40)\r
+#define MCF_PWM_PWMPOL_PPOL7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMCLK */\r
+#define MCF_PWM_PWMCLK_PCLK0 (0x1)\r
+#define MCF_PWM_PWMCLK_PCLK1 (0x2)\r
+#define MCF_PWM_PWMCLK_PCLK2 (0x4)\r
+#define MCF_PWM_PWMCLK_PCLK3 (0x8)\r
+#define MCF_PWM_PWMCLK_PCLK4 (0x10)\r
+#define MCF_PWM_PWMCLK_PCLK5 (0x20)\r
+#define MCF_PWM_PWMCLK_PCLK6 (0x40)\r
+#define MCF_PWM_PWMCLK_PCLK7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMPRCLK */\r
+#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x7)<<0)\r
+#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x7)<<0x4)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMCAE */\r
+#define MCF_PWM_PWMCAE_CAE0 (0x1)\r
+#define MCF_PWM_PWMCAE_CAE1 (0x2)\r
+#define MCF_PWM_PWMCAE_CAE2 (0x4)\r
+#define MCF_PWM_PWMCAE_CAE3 (0x8)\r
+#define MCF_PWM_PWMCAE_CAE4 (0x10)\r
+#define MCF_PWM_PWMCAE_CAE5 (0x20)\r
+#define MCF_PWM_PWMCAE_CAE6 (0x40)\r
+#define MCF_PWM_PWMCAE_CAE7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMCTL */\r
+#define MCF_PWM_PWMCTL_PFRZ (0x4)\r
+#define MCF_PWM_PWMCTL_PSWAI (0x8)\r
+#define MCF_PWM_PWMCTL_CON01 (0x10)\r
+#define MCF_PWM_PWMCTL_CON23 (0x20)\r
+#define MCF_PWM_PWMCTL_CON45 (0x40)\r
+#define MCF_PWM_PWMCTL_CON67 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMSCLA */\r
+#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMSCLB */\r
+#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMCNT */\r
+#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMPER */\r
+#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMDTY */\r
+#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMSDN */\r
+#define MCF_PWM_PWMSDN_SDNEN (0x1)\r
+#define MCF_PWM_PWMSDN_PWM7IL (0x2)\r
+#define MCF_PWM_PWMSDN_PWM7IN (0x4)\r
+#define MCF_PWM_PWMSDN_LVL (0x10)\r
+#define MCF_PWM_PWMSDN_RESTART (0x20)\r
+#define MCF_PWM_PWMSDN_IE (0x40)\r
+#define MCF_PWM_PWMSDN_IF (0x80)\r
+\r
+\r
+#endif /* __MCF52235_PWM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_QSPI_H__\r
+#define __MCF52235_QSPI_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Queued Serial Peripheral Interface (QSPI)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_QSPI_QMR (*(vuint16*)(&__IPSBAR[0x340]))\r
+#define MCF_QSPI_QDLYR (*(vuint16*)(&__IPSBAR[0x344]))\r
+#define MCF_QSPI_QWR (*(vuint16*)(&__IPSBAR[0x348]))\r
+#define MCF_QSPI_QIR (*(vuint16*)(&__IPSBAR[0x34C]))\r
+#define MCF_QSPI_QAR (*(vuint16*)(&__IPSBAR[0x350]))\r
+#define MCF_QSPI_QDR (*(vuint16*)(&__IPSBAR[0x354]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QMR */\r
+#define MCF_QSPI_QMR_BAUD(x) (((x)&0xFF)<<0)\r
+#define MCF_QSPI_QMR_CPHA (0x100)\r
+#define MCF_QSPI_QMR_CPOL (0x200)\r
+#define MCF_QSPI_QMR_BITS(x) (((x)&0xF)<<0xA)\r
+#define MCF_QSPI_QMR_DOHIE (0x4000)\r
+#define MCF_QSPI_QMR_MSTR (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QDLYR */\r
+#define MCF_QSPI_QDLYR_DTL(x) (((x)&0xFF)<<0)\r
+#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x7F)<<0x8)\r
+#define MCF_QSPI_QDLYR_SPE (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QWR */\r
+#define MCF_QSPI_QWR_NEWQP(x) (((x)&0xF)<<0)\r
+#define MCF_QSPI_QWR_CPTQP(x) (((x)&0xF)<<0x4)\r
+#define MCF_QSPI_QWR_ENDQP(x) (((x)&0xF)<<0x8)\r
+#define MCF_QSPI_QWR_CSIV (0x1000)\r
+#define MCF_QSPI_QWR_WRTO (0x2000)\r
+#define MCF_QSPI_QWR_WREN (0x4000)\r
+#define MCF_QSPI_QWR_HALT (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QIR */\r
+#define MCF_QSPI_QIR_SPIF (0x1)\r
+#define MCF_QSPI_QIR_ABRT (0x4)\r
+#define MCF_QSPI_QIR_WCEF (0x8)\r
+#define MCF_QSPI_QIR_SPIFE (0x100)\r
+#define MCF_QSPI_QIR_ABRTE (0x400)\r
+#define MCF_QSPI_QIR_WCEFE (0x800)\r
+#define MCF_QSPI_QIR_ABRTL (0x1000)\r
+#define MCF_QSPI_QIR_ABRTB (0x4000)\r
+#define MCF_QSPI_QIR_WCEFB (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QAR */\r
+#define MCF_QSPI_QAR_ADDR(x) (((x)&0x3F)<<0)\r
+#define MCF_QSPI_QAR_TRANS (0)\r
+#define MCF_QSPI_QAR_RECV (0x10)\r
+#define MCF_QSPI_QAR_CMD (0x20)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QDR */\r
+#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0)\r
+#define MCF_QSPI_QDR_CONT (0x8000)\r
+#define MCF_QSPI_QDR_BITSE (0x4000)\r
+#define MCF_QSPI_QDR_DT (0x2000)\r
+#define MCF_QSPI_QDR_DSCK (0x1000)\r
+#define MCF_QSPI_QDR_QSPI_CS3 (0x800)\r
+#define MCF_QSPI_QDR_QSPI_CS2 (0x400)\r
+#define MCF_QSPI_QDR_QSPI_CS1 (0x200)\r
+#define MCF_QSPI_QDR_QSPI_CS0 (0x100)\r
+\r
+\r
+#endif /* __MCF52235_QSPI_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_RCM_H__\r
+#define __MCF52235_RCM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Reset Controller Module (RCM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_RCM_RCR (*(vuint8 *)(&__IPSBAR[0x110000]))\r
+#define MCF_RCM_RSR (*(vuint8 *)(&__IPSBAR[0x110001]))\r
+#define MCF_RCM_CCR (*(vuint16*)(&__IPSBAR[0x110004]))\r
+#define MCF_RCM_CIR (*(vuint16*)(&__IPSBAR[0x11000A]))\r
+\r
+/* Bit definitions and macros for MCF_RCM_RCR */\r
+#define MCF_RCM_RCR_LVDE (0x1)\r
+#define MCF_RCM_RCR_LVDRE (0x4)\r
+#define MCF_RCM_RCR_LVDIE (0x8)\r
+#define MCF_RCM_RCR_LVDF (0x10)\r
+#define MCF_RCM_RCR_FRCRSTOUT (0x40)\r
+#define MCF_RCM_RCR_SOFTRST (0x80)\r
+\r
+/* Bit definitions and macros for MCF_RCM_RSR */\r
+#define MCF_RCM_RSR_LOL (0x1)\r
+#define MCF_RCM_RSR_LOC (0x2)\r
+#define MCF_RCM_RSR_EXT (0x4)\r
+#define MCF_RCM_RSR_POR (0x8)\r
+#define MCF_RCM_RSR_WDR (0x10)\r
+#define MCF_RCM_RSR_SOFT (0x20)\r
+#define MCF_RCM_RSR_LVD (0x40)\r
+\r
+/* Bit definitions and macros for MCF_RCM_CCR */\r
+#define MCF_RCM_CCR_LOAD (0x8000)\r
+\r
+\r
+#endif /* __MCF52235_RCM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_RNGA_H__\r
+#define __MCF52235_RNGA_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Random Number Generator (RNG)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_RNGA_RNGCR (*(vuint32*)(&__IPSBAR[0x1F0000]))\r
+#define MCF_RNGA_RNGSR (*(vuint32*)(&__IPSBAR[0x1F0004]))\r
+#define MCF_RNGA_RNGER (*(vuint32*)(&__IPSBAR[0x1F0008]))\r
+#define MCF_RNGA_RNGOUT (*(vuint32*)(&__IPSBAR[0x1F000C]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_RNGA_RNGCR */\r
+#define MCF_RNGA_RNGCR_GO (0x1)\r
+#define MCF_RNGA_RNGCR_HA (0x2)\r
+#define MCF_RNGA_RNGCR_IM (0x4)\r
+#define MCF_RNGA_RNGCR_CI (0x8)\r
+#define MCF_RNGA_RNGCR_SLM (0x10)\r
+\r
+/* Bit definitions and macros for MCF_RNGA_RNGSR */\r
+#define MCF_RNGA_RNGSR_SV (0x1)\r
+#define MCF_RNGA_RNGSR_LRS (0x2)\r
+#define MCF_RNGA_RNGSR_OUF (0x4)\r
+#define MCF_RNGA_RNGSR_EI (0x8)\r
+#define MCF_RNGA_RNGSR_SLP (0x10)\r
+#define MCF_RNGA_RNGSR_ORL(x) (((x)&0xFF)<<0x8)\r
+#define MCF_RNGA_RNGSR_ORS(x) (((x)&0xFF)<<0x10)\r
+\r
+/* Bit definitions and macros for MCF_RNGA_RNGER */\r
+#define MCF_RNGA_RNGER_ENT(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RNGA_RNGOUT */\r
+#define MCF_RNGA_RNGOUT_RANDOM_OUTPUT(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52235_RNGA_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_RTC_H__\r
+#define __MCF52235_RTC_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Real-Time Clock (RTC)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_RTC_HOURMIN (*(vuint32*)(&__IPSBAR[0x3C0]))\r
+#define MCF_RTC_SECONDS (*(vuint32*)(&__IPSBAR[0x3C4]))\r
+#define MCF_RTC_ALRM_HM (*(vuint32*)(&__IPSBAR[0x3C8]))\r
+#define MCF_RTC_ALRM_SEC (*(vuint32*)(&__IPSBAR[0x3CC]))\r
+#define MCF_RTC_RTCCTL (*(vuint32*)(&__IPSBAR[0x3D0]))\r
+#define MCF_RTC_RTCISR (*(vuint32*)(&__IPSBAR[0x3D4]))\r
+#define MCF_RTC_RTCIENR (*(vuint32*)(&__IPSBAR[0x3D8]))\r
+#define MCF_RTC_STPWCH (*(vuint32*)(&__IPSBAR[0x3DC]))\r
+#define MCF_RTC_DAYS (*(vuint32*)(&__IPSBAR[0x3E0]))\r
+#define MCF_RTC_ALRM_DAY (*(vuint32*)(&__IPSBAR[0x3E4]))\r
+\r
+\r
+/* Bit definitions and macros for MCF_RTC_HOURMIN */\r
+#define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x3F)<<0)\r
+#define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x1F)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_RTC_SECONDS */\r
+#define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RTC_ALRM_HM */\r
+#define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x3F)<<0)\r
+#define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x1F)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_RTC_ALRM_SEC */\r
+#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RTC_RTCCTL */\r
+#define MCF_RTC_RTCCTL_SWR (0x1)\r
+#define MCF_RTC_RTCCTL_EN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_RTC_RTCISR */\r
+#define MCF_RTC_RTCISR_SW (0x1)\r
+#define MCF_RTC_RTCISR_MIN (0x2)\r
+#define MCF_RTC_RTCISR_ALM (0x4)\r
+#define MCF_RTC_RTCISR_DAY (0x8)\r
+#define MCF_RTC_RTCISR_1HZ (0x10)\r
+#define MCF_RTC_RTCISR_HR (0x20)\r
+\r
+/* Bit definitions and macros for MCF_RTC_RTCIENR */\r
+#define MCF_RTC_RTCIENR_SW (0x1)\r
+#define MCF_RTC_RTCIENR_MIN (0x2)\r
+#define MCF_RTC_RTCIENR_ALM (0x4)\r
+#define MCF_RTC_RTCIENR_DAY (0x8)\r
+#define MCF_RTC_RTCIENR_1HZ (0x10)\r
+#define MCF_RTC_RTCIENR_HR (0x20)\r
+\r
+/* Bit definitions and macros for MCF_RTC_STPWCH */\r
+#define MCF_RTC_STPWCH_CNT(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RTC_DAYS */\r
+#define MCF_RTC_DAYS_DAYS(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RTC_ALRM_DAY */\r
+#define MCF_RTC_ALRM_DAY_DAYSAL(x) (((x)&0xFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52235_RTC_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_SCM_H__\r
+#define __MCF52235_SCM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* System Control Module (SCM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_SCM_RAMBAR (*(vuint32*)(&__IPSBAR[0x8]))\r
+#define MCF_SCM_PPMRH (*(vuint32*)(&__IPSBAR[0xC]))\r
+#define MCF_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x10]))\r
+#define MCF_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x11]))\r
+#define MCF_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x13]))\r
+#define MCF_SCM_DMAREQC (*(vuint32*)(&__IPSBAR[0x14]))\r
+#define MCF_SCM_PPMRL (*(vuint32*)(&__IPSBAR[0x18]))\r
+#define MCF_SCM_MPARK (*(vuint32*)(&__IPSBAR[0x1C]))\r
+#define MCF_SCM_MPR (*(vuint8 *)(&__IPSBAR[0x20]))\r
+#define MCF_SCM_PPMRS (*(vuint8 *)(&__IPSBAR[0x21]))\r
+#define MCF_SCM_PPMRC (*(vuint8 *)(&__IPSBAR[0x22]))\r
+#define MCF_SCM_IPSBMT (*(vuint8 *)(&__IPSBAR[0x23]))\r
+#define MCF_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x24]))\r
+#define MCF_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x25]))\r
+#define MCF_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x26]))\r
+#define MCF_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x27]))\r
+#define MCF_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x28]))\r
+#define MCF_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x29]))\r
+#define MCF_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x2A]))\r
+#define MCF_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x2B]))\r
+#define MCF_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x2C]))\r
+#define MCF_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x30]))\r
+#define MCF_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x31]))\r
+#define MCF_SCM_PACR(x) (*(vuint8 *)(&__IPSBAR[0x24 + ((x)*0x1)]))\r
+#define MCF_SCM_GPACR(x) (*(vuint8 *)(&__IPSBAR[0x30 + ((x)*0x1)]))\r
+\r
+/* Other macros */\r
+#define MCF_SCM_IPSBAR (*(vuint32*)(&__IPSBAR[0x0]))\r
+#define MCF_SCM_IPSBAR_V (0x1)\r
+#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000)\r
+\r
+\r
+/* Bit definitions and macros for MCF_SCM_RAMBAR */\r
+#define MCF_SCM_RAMBAR_BDE (0x200)\r
+#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PPMRH */\r
+#define MCF_SCM_PPMRH_CDPORTS (0x1)\r
+#define MCF_SCM_PPMRH_CDEPORT (0x2)\r
+#define MCF_SCM_PPMRH_CDPIT0 (0x8)\r
+#define MCF_SCM_PPMRH_CDPIT1 (0x10)\r
+#define MCF_SCM_PPMRH_CDADC (0x80)\r
+#define MCF_SCM_PPMRH_CDGPT (0x100)\r
+#define MCF_SCM_PPMRH_CDPWM (0x200)\r
+#define MCF_SCM_PPMRH_CDFCAN (0x400)\r
+#define MCF_SCM_PPMRH_CDCFM (0x800)\r
+#define MCF_SCM_PPMRH_CDEPHY (0x1000)\r
+#define MCF_SCM_PPMRH_CDRNGA (0x2000)\r
+\r
+/* Bit definitions and macros for MCF_SCM_CRSR */\r
+#define MCF_SCM_CRSR_CWDR (0x20)\r
+#define MCF_SCM_CRSR_EXT (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_CWCR */\r
+#define MCF_SCM_CWCR_CWTIF (0x1)\r
+#define MCF_SCM_CWCR_CWTAVAL (0x2)\r
+#define MCF_SCM_CWCR_CWTA (0x4)\r
+#define MCF_SCM_CWCR_CWT(x) (((x)&0x7)<<0x3)\r
+#define MCF_SCM_CWCR_CWT_2_9 (0)\r
+#define MCF_SCM_CWCR_CWT_2_11 (0x8)\r
+#define MCF_SCM_CWCR_CWT_2_13 (0x10)\r
+#define MCF_SCM_CWCR_CWT_2_15 (0x18)\r
+#define MCF_SCM_CWCR_CWT_2_19 (0x20)\r
+#define MCF_SCM_CWCR_CWT_2_23 (0x28)\r
+#define MCF_SCM_CWCR_CWT_2_27 (0x30)\r
+#define MCF_SCM_CWCR_CWT_2_31 (0x38)\r
+#define MCF_SCM_CWCR_CWRI (0x40)\r
+#define MCF_SCM_CWCR_CWE (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_CWSR */\r
+#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_SCM_DMAREQC */\r
+#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0xF)<<0)\r
+#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0xF)<<0x4)\r
+#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0xF)<<0x8)\r
+#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0xF)<<0xC)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PPMRL */\r
+#define MCF_SCM_PPMRL_CDG (0x2)\r
+#define MCF_SCM_PPMRL_CDDMA (0x10)\r
+#define MCF_SCM_PPMRL_CDUART0 (0x20)\r
+#define MCF_SCM_PPMRL_CDUART1 (0x40)\r
+#define MCF_SCM_PPMRL_CDUART2 (0x80)\r
+#define MCF_SCM_PPMRL_CDI2C (0x200)\r
+#define MCF_SCM_PPMRL_CDQSPI (0x400)\r
+#define MCF_SCM_PPMRL_CDRTC (0x1000)\r
+#define MCF_SCM_PPMRL_CDTMR0 (0x2000)\r
+#define MCF_SCM_PPMRL_CDTMR1 (0x4000)\r
+#define MCF_SCM_PPMRL_CDTMR2 (0x8000)\r
+#define MCF_SCM_PPMRL_CDTMR3 (0x10000)\r
+#define MCF_SCM_PPMRL_CDINTC0 (0x20000)\r
+#define MCF_SCM_PPMRL_CDINTC1 (0x40000)\r
+#define MCF_SCM_PPMRL_CDFEC0 (0x200000)\r
+\r
+/* Bit definitions and macros for MCF_SCM_MPARK */\r
+#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0xF)<<0x8)\r
+#define MCF_SCM_MPARK_PRKLAST (0x1000)\r
+#define MCF_SCM_MPARK_TIMEOUT (0x2000)\r
+#define MCF_SCM_MPARK_FIXED (0x4000)\r
+#define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x3)<<0x10)\r
+#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x3)<<0x12)\r
+#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x3)<<0x14)\r
+#define MCF_SCM_MPARK_BCR24BIT (0x1000000)\r
+#define MCF_SCM_MPARK_M2_P_EN (0x2000000)\r
+\r
+/* Bit definitions and macros for MCF_SCM_MPR */\r
+#define MCF_SCM_MPR_MPR(x) (((x)&0xF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PPMRS */\r
+#define MCF_SCM_PPMRS_PPMRS(x) (((x)&0x7F)<<0)\r
+#define MCF_SCM_PPMRS_DISABLE_ALL (0x40)\r
+#define MCF_SCM_PPMRS_DISABLE_CFM (0x2B)\r
+#define MCF_SCM_PPMRS_DISABLE_CAN (0x2A)\r
+#define MCF_SCM_PPMRS_DISABLE_PWM (0x29)\r
+#define MCF_SCM_PPMRS_DISABLE_GPT (0x28)\r
+#define MCF_SCM_PPMRS_DISABLE_ADC (0x27)\r
+#define MCF_SCM_PPMRS_DISABLE_PIT1 (0x24)\r
+#define MCF_SCM_PPMRS_DISABLE_PIT0 (0x23)\r
+#define MCF_SCM_PPMRS_DISABLE_EPORT (0x21)\r
+#define MCF_SCM_PPMRS_DISABLE_PORTS (0x20)\r
+#define MCF_SCM_PPMRS_DISABLE_INTC (0x11)\r
+#define MCF_SCM_PPMRS_DISABLE_DTIM3 (0x10)\r
+#define MCF_SCM_PPMRS_DISABLE_DTIM2 (0xF)\r
+#define MCF_SCM_PPMRS_DISABLE_DTIM1 (0xE)\r
+#define MCF_SCM_PPMRS_DISABLE_DTIM0 (0xD)\r
+#define MCF_SCM_PPMRS_DISABLE_QSPI (0xA)\r
+#define MCF_SCM_PPMRS_DISABLE_I2C (0x9)\r
+#define MCF_SCM_PPMRS_DISABLE_UART2 (0x7)\r
+#define MCF_SCM_PPMRS_DISABLE_UART1 (0x6)\r
+#define MCF_SCM_PPMRS_DISABLE_UART0 (0x5)\r
+#define MCF_SCM_PPMRS_DISABLE_DMA (0x4)\r
+#define MCF_SCM_PPMRS_SET_CDG (0x1)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PPMRC */\r
+#define MCF_SCM_PPMRC_PPMRC(x) (((x)&0x7F)<<0)\r
+#define MCF_SCM_PPMRC_ENABLE_ALL (0x40)\r
+#define MCF_SCM_PPMRC_ENABLE_CFM (0x2B)\r
+#define MCF_SCM_PPMRC_ENABLE_CAN (0x2A)\r
+#define MCF_SCM_PPMRC_ENABLE_PWM (0x29)\r
+#define MCF_SCM_PPMRC_ENABLE_GPT (0x28)\r
+#define MCF_SCM_PPMRC_ENABLE_ADC (0x27)\r
+#define MCF_SCM_PPMRC_ENABLE_PIT1 (0x24)\r
+#define MCF_SCM_PPMRC_ENABLE_PIT0 (0x23)\r
+#define MCF_SCM_PPMRC_ENABLE_EPORT (0x21)\r
+#define MCF_SCM_PPMRC_ENABLE_PORTS (0x20)\r
+#define MCF_SCM_PPMRC_ENABLE_INTC (0x11)\r
+#define MCF_SCM_PPMRC_ENABLE_DTIM3 (0x10)\r
+#define MCF_SCM_PPMRC_ENABLE_DTIM2 (0xF)\r
+#define MCF_SCM_PPMRC_ENABLE_DTIM1 (0xE)\r
+#define MCF_SCM_PPMRC_ENABLE_DTIM0 (0xD)\r
+#define MCF_SCM_PPMRC_ENABLE_QSPI (0xA)\r
+#define MCF_SCM_PPMRC_ENABLE_I2C (0x9)\r
+#define MCF_SCM_PPMRC_ENABLE_UART2 (0x7)\r
+#define MCF_SCM_PPMRC_ENABLE_UART1 (0x6)\r
+#define MCF_SCM_PPMRC_ENABLE_UART0 (0x5)\r
+#define MCF_SCM_PPMRC_ENABLE_DMA (0x4)\r
+#define MCF_SCM_PPMRC_CLEAR_CDG (0x1)\r
+\r
+/* Bit definitions and macros for MCF_SCM_IPSBMT */\r
+#define MCF_SCM_IPSBMT_BMT(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_1024 (0)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_512 (0x1)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_256 (0x2)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_128 (0x3)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_64 (0x4)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_32 (0x5)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_16 (0x6)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_8 (0x7)\r
+#define MCF_SCM_IPSBMT_BME (0x8)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PACR */\r
+#define MCF_SCM_PACR_ACCESS_CTRL0(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_PACR_LOCK0 (0x8)\r
+#define MCF_SCM_PACR_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)\r
+#define MCF_SCM_PACR_LOCK1 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_GPACR */\r
+#define MCF_SCM_GPACR_ACCESS_CTRL(x) (((x)&0xF)<<0)\r
+#define MCF_SCM_GPACR_LOCK (0x80)\r
+\r
+\r
+#endif /* __MCF52235_SCM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2007/03/19 Revision: 0.91\r
+ */\r
+\r
+#ifndef __MCF52235_UART_H__\r
+#define __MCF52235_UART_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Universal Asynchronous Receiver Transmitter (UART)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_UART0_UMR1 (*(vuint8 *)(&__IPSBAR[0x200]))\r
+#define MCF_UART0_UMR2 (*(vuint8 *)(&__IPSBAR[0x200]))\r
+#define MCF_UART0_USR (*(vuint8 *)(&__IPSBAR[0x204]))\r
+#define MCF_UART0_UCSR (*(vuint8 *)(&__IPSBAR[0x204]))\r
+#define MCF_UART0_UCR (*(vuint8 *)(&__IPSBAR[0x208]))\r
+#define MCF_UART0_URB (*(vuint8 *)(&__IPSBAR[0x20C]))\r
+#define MCF_UART0_UTB (*(vuint8 *)(&__IPSBAR[0x20C]))\r
+#define MCF_UART0_UIPCR (*(vuint8 *)(&__IPSBAR[0x210]))\r
+#define MCF_UART0_UACR (*(vuint8 *)(&__IPSBAR[0x210]))\r
+#define MCF_UART0_UIMR (*(vuint8 *)(&__IPSBAR[0x214]))\r
+#define MCF_UART0_UISR (*(vuint8 *)(&__IPSBAR[0x214]))\r
+#define MCF_UART0_UBG1 (*(vuint8 *)(&__IPSBAR[0x218]))\r
+#define MCF_UART0_UBG2 (*(vuint8 *)(&__IPSBAR[0x21C]))\r
+#define MCF_UART0_UIP (*(vuint8 *)(&__IPSBAR[0x234]))\r
+#define MCF_UART0_UOP1 (*(vuint8 *)(&__IPSBAR[0x238]))\r
+#define MCF_UART0_UOP0 (*(vuint8 *)(&__IPSBAR[0x23C]))\r
+\r
+#define MCF_UART1_UMR1 (*(vuint8 *)(&__IPSBAR[0x240]))\r
+#define MCF_UART1_UMR2 (*(vuint8 *)(&__IPSBAR[0x240]))\r
+#define MCF_UART1_USR (*(vuint8 *)(&__IPSBAR[0x244]))\r
+#define MCF_UART1_UCSR (*(vuint8 *)(&__IPSBAR[0x244]))\r
+#define MCF_UART1_UCR (*(vuint8 *)(&__IPSBAR[0x248]))\r
+#define MCF_UART1_URB (*(vuint8 *)(&__IPSBAR[0x24C]))\r
+#define MCF_UART1_UTB (*(vuint8 *)(&__IPSBAR[0x24C]))\r
+#define MCF_UART1_UIPCR (*(vuint8 *)(&__IPSBAR[0x250]))\r
+#define MCF_UART1_UACR (*(vuint8 *)(&__IPSBAR[0x250]))\r
+#define MCF_UART1_UIMR (*(vuint8 *)(&__IPSBAR[0x254]))\r
+#define MCF_UART1_UISR (*(vuint8 *)(&__IPSBAR[0x254]))\r
+#define MCF_UART1_UBG1 (*(vuint8 *)(&__IPSBAR[0x258]))\r
+#define MCF_UART1_UBG2 (*(vuint8 *)(&__IPSBAR[0x25C]))\r
+#define MCF_UART1_UIP (*(vuint8 *)(&__IPSBAR[0x274]))\r
+#define MCF_UART1_UOP1 (*(vuint8 *)(&__IPSBAR[0x278]))\r
+#define MCF_UART1_UOP0 (*(vuint8 *)(&__IPSBAR[0x27C]))\r
+\r
+#define MCF_UART2_UMR1 (*(vuint8 *)(&__IPSBAR[0x280]))\r
+#define MCF_UART2_UMR2 (*(vuint8 *)(&__IPSBAR[0x280]))\r
+#define MCF_UART2_USR (*(vuint8 *)(&__IPSBAR[0x284]))\r
+#define MCF_UART2_UCSR (*(vuint8 *)(&__IPSBAR[0x284]))\r
+#define MCF_UART2_UCR (*(vuint8 *)(&__IPSBAR[0x288]))\r
+#define MCF_UART2_URB (*(vuint8 *)(&__IPSBAR[0x28C]))\r
+#define MCF_UART2_UTB (*(vuint8 *)(&__IPSBAR[0x28C]))\r
+#define MCF_UART2_UIPCR (*(vuint8 *)(&__IPSBAR[0x290]))\r
+#define MCF_UART2_UACR (*(vuint8 *)(&__IPSBAR[0x290]))\r
+#define MCF_UART2_UIMR (*(vuint8 *)(&__IPSBAR[0x294]))\r
+#define MCF_UART2_UISR (*(vuint8 *)(&__IPSBAR[0x294]))\r
+#define MCF_UART2_UBG1 (*(vuint8 *)(&__IPSBAR[0x298]))\r
+#define MCF_UART2_UBG2 (*(vuint8 *)(&__IPSBAR[0x29C]))\r
+#define MCF_UART2_UIP (*(vuint8 *)(&__IPSBAR[0x2B4]))\r
+#define MCF_UART2_UOP1 (*(vuint8 *)(&__IPSBAR[0x2B8]))\r
+#define MCF_UART2_UOP0 (*(vuint8 *)(&__IPSBAR[0x2BC]))\r
+\r
+#define MCF_UART_UMR(x) (*(vuint8 *)(&__IPSBAR[0x200 + ((x)*0x40)]))\r
+#define MCF_UART_USR(x) (*(vuint8 *)(&__IPSBAR[0x204 + ((x)*0x40)]))\r
+#define MCF_UART_UCSR(x) (*(vuint8 *)(&__IPSBAR[0x204 + ((x)*0x40)]))\r
+#define MCF_UART_UCR(x) (*(vuint8 *)(&__IPSBAR[0x208 + ((x)*0x40)]))\r
+#define MCF_UART_URB(x) (*(vuint8 *)(&__IPSBAR[0x20C + ((x)*0x40)]))\r
+#define MCF_UART_UTB(x) (*(vuint8 *)(&__IPSBAR[0x20C + ((x)*0x40)]))\r
+#define MCF_UART_UIPCR(x) (*(vuint8 *)(&__IPSBAR[0x210 + ((x)*0x40)]))\r
+#define MCF_UART_UACR(x) (*(vuint8 *)(&__IPSBAR[0x210 + ((x)*0x40)]))\r
+#define MCF_UART_UIMR(x) (*(vuint8 *)(&__IPSBAR[0x214 + ((x)*0x40)]))\r
+#define MCF_UART_UISR(x) (*(vuint8 *)(&__IPSBAR[0x214 + ((x)*0x40)]))\r
+#define MCF_UART_UBG1(x) (*(vuint8 *)(&__IPSBAR[0x218 + ((x)*0x40)]))\r
+#define MCF_UART_UBG2(x) (*(vuint8 *)(&__IPSBAR[0x21C + ((x)*0x40)]))\r
+#define MCF_UART_UIP(x) (*(vuint8 *)(&__IPSBAR[0x234 + ((x)*0x40)]))\r
+#define MCF_UART_UOP1(x) (*(vuint8 *)(&__IPSBAR[0x238 + ((x)*0x40)]))\r
+#define MCF_UART_UOP0(x) (*(vuint8 *)(&__IPSBAR[0x23C + ((x)*0x40)]))\r
+\r
+/* Bit definitions and macros for MCF_UART_UMR */\r
+#define MCF_UART_UMR_BC(x) (((x)&0x3)<<0)\r
+#define MCF_UART_UMR_BC_5 (0)\r
+#define MCF_UART_UMR_BC_6 (0x1)\r
+#define MCF_UART_UMR_BC_7 (0x2)\r
+#define MCF_UART_UMR_BC_8 (0x3)\r
+#define MCF_UART_UMR_PT (0x4)\r
+#define MCF_UART_UMR_PM(x) (((x)&0x3)<<0x3)\r
+#define MCF_UART_UMR_ERR (0x20)\r
+#define MCF_UART_UMR_RXIRQ (0x40)\r
+#define MCF_UART_UMR_RXRTS (0x80)\r
+#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)\r
+#define MCF_UART_UMR_PM_MULTI_DATA (0x18)\r
+#define MCF_UART_UMR_PM_NONE (0x10)\r
+#define MCF_UART_UMR_PM_FORCE_HI (0xC)\r
+#define MCF_UART_UMR_PM_FORCE_LO (0x8)\r
+#define MCF_UART_UMR_PM_ODD (0x4)\r
+#define MCF_UART_UMR_PM_EVEN (0)\r
+#define MCF_UART_UMR_SB(x) (((x)&0xF)<<0)\r
+#define MCF_UART_UMR_SB_STOP_BITS_1 (0x7)\r
+#define MCF_UART_UMR_SB_STOP_BITS_15 (0x8)\r
+#define MCF_UART_UMR_SB_STOP_BITS_2 (0xF)\r
+#define MCF_UART_UMR_TXCTS (0x10)\r
+#define MCF_UART_UMR_TXRTS (0x20)\r
+#define MCF_UART_UMR_CM(x) (((x)&0x3)<<0x6)\r
+#define MCF_UART_UMR_CM_NORMAL (0)\r
+#define MCF_UART_UMR_CM_ECHO (0x40)\r
+#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)\r
+#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_UART_USR */\r
+#define MCF_UART_USR_RXRDY (0x1)\r
+#define MCF_UART_USR_FFULL (0x2)\r
+#define MCF_UART_USR_TXRDY (0x4)\r
+#define MCF_UART_USR_TXEMP (0x8)\r
+#define MCF_UART_USR_OE (0x10)\r
+#define MCF_UART_USR_PE (0x20)\r
+#define MCF_UART_USR_FE (0x40)\r
+#define MCF_UART_USR_RB (0x80)\r
+\r
+/* Bit definitions and macros for MCF_UART_UCSR */\r
+#define MCF_UART_UCSR_TCS(x) (((x)&0xF)<<0)\r
+#define MCF_UART_UCSR_TCS_SYS_CLK (0xD)\r
+#define MCF_UART_UCSR_TCS_CTM16 (0xE)\r
+#define MCF_UART_UCSR_TCS_CTM (0xF)\r
+#define MCF_UART_UCSR_RCS(x) (((x)&0xF)<<0x4)\r
+#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)\r
+#define MCF_UART_UCSR_RCS_CTM16 (0xE0)\r
+#define MCF_UART_UCSR_RCS_CTM (0xF0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UCR */\r
+#define MCF_UART_UCR_RC(x) (((x)&0x3)<<0)\r
+#define MCF_UART_UCR_RX_ENABLED (0x1)\r
+#define MCF_UART_UCR_RX_DISABLED (0x2)\r
+#define MCF_UART_UCR_TC(x) (((x)&0x3)<<0x2)\r
+#define MCF_UART_UCR_TX_ENABLED (0x4)\r
+#define MCF_UART_UCR_TX_DISABLED (0x8)\r
+#define MCF_UART_UCR_MISC(x) (((x)&0x7)<<0x4)\r
+#define MCF_UART_UCR_NONE (0)\r
+#define MCF_UART_UCR_RESET_MR (0x10)\r
+#define MCF_UART_UCR_RESET_RX (0x20)\r
+#define MCF_UART_UCR_RESET_TX (0x30)\r
+#define MCF_UART_UCR_RESET_ERROR (0x40)\r
+#define MCF_UART_UCR_RESET_BKCHGINT (0x50)\r
+#define MCF_UART_UCR_START_BREAK (0x60)\r
+#define MCF_UART_UCR_STOP_BREAK (0x70)\r
+\r
+/* Bit definitions and macros for MCF_UART_URB */\r
+#define MCF_UART_URB_RB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UTB */\r
+#define MCF_UART_UTB_TB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UIPCR */\r
+#define MCF_UART_UIPCR_CTS (0x1)\r
+#define MCF_UART_UIPCR_COS (0x10)\r
+\r
+/* Bit definitions and macros for MCF_UART_UACR */\r
+#define MCF_UART_UACR_IEC (0x1)\r
+\r
+/* Bit definitions and macros for MCF_UART_UIMR */\r
+#define MCF_UART_UIMR_TXRDY (0x1)\r
+#define MCF_UART_UIMR_FFULL_RXRDY (0x2)\r
+#define MCF_UART_UIMR_DB (0x4)\r
+#define MCF_UART_UIMR_COS (0x80)\r
+\r
+/* Bit definitions and macros for MCF_UART_UISR */\r
+#define MCF_UART_UISR_TXRDY (0x1)\r
+#define MCF_UART_UISR_FFULL_RXRDY (0x2)\r
+#define MCF_UART_UISR_DB (0x4)\r
+#define MCF_UART_UISR_COS (0x80)\r
+\r
+/* Bit definitions and macros for MCF_UART_UBG1 */\r
+#define MCF_UART_UBG1_Divider_MSB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UBG2 */\r
+#define MCF_UART_UBG2_Divider_LSB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UIP */\r
+#define MCF_UART_UIP_CTS (0x1)\r
+\r
+/* Bit definitions and macros for MCF_UART_UOP1 */\r
+#define MCF_UART_UOP1_RTS (0x1)\r
+\r
+/* Bit definitions and macros for MCF_UART_UOP0 */\r
+#define MCF_UART_UOP0_RTS (0x1)\r
+\r
+\r
+#endif /* __MCF52235_UART_H__ */\r
--- /dev/null
+RM := rm -rf\r
+\r
+# Set the optimisation level - this should be set to 0, 1, 2, 3 or s (s for size).\r
+OPTIM=0\r
+\r
+###############################################################################\r
+# List the directories that contain files to be built.\r
+###############################################################################\r
+\r
+# These two directories contain the FreeRTOS.org kernel source files.\r
+FREERTOS_SOURCE_DIR=./../../../Source\r
+PORT_SOURCE_DIR=./../../../Source/portable/GCC/ColdFire_V2\r
+\r
+# This directory contains the standard demo files that get included in every\r
+# FreeRTOS.org demo. They define tasks that demonstrate the API usage and \r
+# test the FreeRTOS.org port.\r
+COMMON_DEMO_SOURCE_DIR=./../../Common/Minimal\r
+\r
+# This directory contains the modified uIP code\r
+FREERTOS_uIP_DIR=./../../Common/ethernet/FreeRTOS-uIP\r
+\r
+VPATH= $(FREERTOS_SOURCE_DIR) : \\r
+ $(PORT_SOURCE_DIR) : \\r
+ $(COMMON_DEMO_SOURCE_DIR) : \\r
+ $(FREERTOS_SOURCE_DIR)/portable/MemMang : \\r
+ $(FREERTOS_uIP_DIR) : \\r
+ . : \\r
+ ./webserver : \\r
+ ./ParTest : \\r
+ ./serial\r
+\r
+\r
+###############################################################################\r
+# Define a few constants to be used during the build.\r
+###############################################################################\r
+\r
+OUTPUT_DIR=./bin\r
+CPU=52235\r
+LINKER_SCRIPT=m52235evb-rom-hosted.ld\r
+SREC_FILENAME=RTOSDemo.s19\r
+ELF_FILENAME=RTOSDemo.elf\r
+CC=m68k-elf-gcc\r
+AS=m68K-elf-as\r
+OBJCOPY=m68K-elf-objcopy\r
+\r
+\r
+###############################################################################\r
+# List the files to include in the build. These files will be located from the\r
+# VPATH defined above.\r
+###############################################################################\r
+\r
+# The FreeRTOS.org source files.\r
+FreeRTOS_OBJS= $(OUTPUT_DIR)/portasm.o \\r
+ $(OUTPUT_DIR)/port.o \\r
+ $(OUTPUT_DIR)/list.o \\r
+ $(OUTPUT_DIR)/tasks.o \\r
+ $(OUTPUT_DIR)/queue.o \\r
+ $(OUTPUT_DIR)/heap_1.o\r
+\r
+# The demo app source files, including the basic WEB server.\r
+Demo_OBJS= $(OUTPUT_DIR)/main.o \\r
+ $(OUTPUT_DIR)/ParTest.o \\r
+ $(OUTPUT_DIR)/flash.o \\r
+ $(OUTPUT_DIR)/FreeRTOS_Tick_Setup.o \\r
+ $(OUTPUT_DIR)/BlockQ.o \\r
+ $(OUTPUT_DIR)/PollQ.o \\r
+ $(OUTPUT_DIR)/semtest.o \\r
+ $(OUTPUT_DIR)/GenQTest.o \\r
+ $(OUTPUT_DIR)/QPeek.o \\r
+ $(OUTPUT_DIR)/FEC.o\r
+\r
+HTTP_OBJS= $(OUTPUT_DIR)/uIP_Task.o \\r
+ $(OUTPUT_DIR)/httpd.o \\r
+ $(OUTPUT_DIR)/httpd-cgi.o \\r
+ $(OUTPUT_DIR)/httpd-fs.o \\r
+ $(OUTPUT_DIR)/http-strings.o\r
+\r
+# uIP source files\r
+uIP_OBJS= $(OUTPUT_DIR)/timer.o \\r
+ $(OUTPUT_DIR)/uip.o \\r
+ $(OUTPUT_DIR)/uip_arp.o \\r
+ $(OUTPUT_DIR)/uiplib.o \\r
+ $(OUTPUT_DIR)/uip-split.o \\r
+ $(OUTPUT_DIR)/psock.o\r
+\r
+OBJS = $(FreeRTOS_OBJS) $(Demo_OBJS) $(uIP_OBJS) $(HTTP_OBJS)\r
+ \r
+C_DEPS = $(OBJS:.o=.d)\r
+\r
+INCLUDE_PATHS= -I./webserver \\r
+ -I"$(FREERTOS_uIP_DIR)" \\r
+ -I"$(FREERTOS_SOURCE_DIR)/include" \\r
+ -I"include" \\r
+ -I"$(COMMON_DEMO_SOURCE_DIR)/../include" \\r
+ -I"$(PORT_SOURCE_DIR)" \\r
+ -I./MCF5223x \\r
+ -I.\r
+\r
+CFLAGS= $(INCLUDE_PATHS) \\r
+ -D COLDFIRE_V2_GCC \\r
+ -D PACK_STRUCT_END=__attribute\(\(packed\)\) \\r
+ -D ALIGN_STRUCT_END=__attribute\(\(aligned\(4\)\)\) \\r
+ -O$(OPTIM) \\r
+ -fno-strict-aliasing \\r
+ -g3 \\r
+ -gdwarf-2 \\r
+ -Wall \\r
+ -Wextra \\r
+ -c \\r
+ -ffunction-sections \\r
+ -fdata-sections \\r
+ -fmessage-length=0 \\r
+ -funsigned-char \\r
+ -Wextra \\r
+ -mcpu=$(CPU) \\r
+ -MMD \\r
+ -MP \\r
+ -MF"$(@:%.o=%.d)" \\r
+ -MT"$(@:%.o=%.d)"\r
+\r
+ASFLAGS= -m52235 \\r
+ -g3 \\r
+ --register-prefix-optional \\r
+ --bitwise-or\r
+\r
+LIBS=\r
+\r
+# Add inputs and outputs from these tool invocations to the build variables \r
+\r
+# All Target\r
+all: $(OUTPUT_DIR)/$(SREC_FILENAME)\r
+\r
+# Tool invocations \r
+$(OUTPUT_DIR)/$(SREC_FILENAME): $(OUTPUT_DIR)/$(ELF_FILENAME)\r
+ $(OBJCOPY) $(OUTPUT_DIR)/$(ELF_FILENAME) -O srec $(OUTPUT_DIR)/$(SREC_FILENAME)\r
+\r
+$(OUTPUT_DIR)/$(ELF_FILENAME): $(OBJS)\r
+ $(CC) -nostartfiles --gc-sections -Xlinker -Map=$(OUTPUT_DIR)/output.map -mcpu=$(CPU) -T $(LINKER_SCRIPT) -o"$(OUTPUT_DIR)/$(ELF_FILENAME)" $(OBJS) $(USER_OBJS) $(LIBS)\r
+\r
+$(OUTPUT_DIR)/%.o: %.c Makefile\r
+ $(CC) $(CFLAGS) -o"$@" "$<"\r
+\r
+$(OUTPUT_DIR)/%.o: %.S\r
+ $(AS) $(ASFLAGS) -o"$@" "$<"\r
+\r
+# Other Targets\r
+clean:\r
+ -$(RM) $(OBJS) $(C_DEPS) $(EXECUTABLES) $(OUTPUT_DIR)/$(ELF_FILENAME) $(OUTPUT_DIR)/$(SREC_FILENAME)\r
+ -@echo ' '\r
+\r
+#\r
+# The rule to create the target directory\r
+#\r
+$(OUTPUT_DIR):\r
+ @mkdir $(OUTPUT_DIR)\r
+\r
+\r
+.PHONY: all clean dependents\r
+.SECONDARY: post-build\r
+\r
+-include $(wildcard $(OUTPUT_DIR)/*.d) __dummy__\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "partest.h"\r
+\r
+#define partstNUM_LEDs 4\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Ensure LED outputs are set to GPIO */\r
+ MCF_GPIO_PTCPAR = MCF_GPIO_PTCPAR_DTIN3_GPIO | MCF_GPIO_PTCPAR_DTIN2_GPIO | MCF_GPIO_PTCPAR_DTIN1_GPIO | MCF_GPIO_PTCPAR_DTIN0_GPIO;\r
+\r
+ /* Set GPIO to outputs. */\r
+ MCF_GPIO_DDRTC = MCF_GPIO_DDRTC_DDRTC3 | MCF_GPIO_DDRTC_DDRTC2 | MCF_GPIO_DDRTC_DDRTC1 | MCF_GPIO_DDRTC_DDRTC0;\r
+\r
+ /* Start with all LEDs off. */\r
+ MCF_GPIO_PORTTC = 0x00;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ if( uxLED < partstNUM_LEDs )\r
+ {\r
+ if( xValue != 0 )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ MCF_GPIO_PORTTC |= ( 1 << uxLED );\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ taskENTER_CRITICAL();\r
+ MCF_GPIO_PORTTC &= ~( 1 << uxLED );\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED < partstNUM_LEDs )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( ( MCF_GPIO_PORTTC & ( 1 << uxLED ) ) == ( unsigned portCHAR ) 0 )\r
+ {\r
+ MCF_GPIO_PORTTC |= ( 1 << uxLED );\r
+ }\r
+ else\r
+ {\r
+ MCF_GPIO_PORTTC &= ~( 1 << uxLED );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*\r
+ * A sample implementation of pvPortMalloc() and vPortFree() that permits\r
+ * allocated blocks to be freed, but does not combine adjacent free blocks\r
+ * into a single larger block.\r
+ *\r
+ * See heap_1.c and heap_3.c for alternative implementations, and the memory\r
+ * management pages of http://www.FreeRTOS.org for more information.\r
+ */\r
+#include <stdlib.h>\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Setup the correct byte alignment mask for the defined byte alignment. */\r
+\r
+#if portBYTE_ALIGNMENT == 8\r
+ #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0007 )\r
+#endif\r
+\r
+#if portBYTE_ALIGNMENT == 4\r
+ #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 )\r
+#endif\r
+\r
+#if portBYTE_ALIGNMENT == 2\r
+ #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 )\r
+#endif\r
+\r
+#if portBYTE_ALIGNMENT == 1\r
+ #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 )\r
+#endif\r
+\r
+#ifndef heapBYTE_ALIGNMENT_MASK\r
+ #error "Invalid portBYTE_ALIGNMENT definition"\r
+#endif\r
+\r
+/* Definitions from linker file. */\r
+extern far unsigned portCHAR __SP_INIT[];\r
+extern far unsigned portCHAR __RAM_ADDRESS[];\r
+extern far unsigned portCHAR __RAM_SIZE[];\r
+extern far unsigned portCHAR __stack_size[];\r
+\r
+#define heapTOP_OF_RAM ( ( (unsigned portLONG) __RAM_ADDRESS + (unsigned portLONG ) __RAM_SIZE ) - 4 )\r
+#define heapTOTAL_SIZE ( (heapTOP_OF_RAM - (unsigned portLONG)__SP_INIT ) + 4 )\r
+\r
+/* Allocate the memory for the heap. The struct is used to force byte\r
+alignment without using any non-portable code. */\r
+typedef struct xRTOS_HEAP_t\r
+{\r
+ unsigned portLONG ulDummy;\r
+ unsigned portCHAR *ucHeap;\r
+} xHeapStruct;\r
+\r
+/* Define the linked list structure. This is used to link free blocks in order\r
+of their size. */\r
+typedef struct A_BLOCK_LINK\r
+{\r
+ struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */\r
+ size_t xBlockSize; /*<< The size of the free block. */\r
+} xBlockLink;\r
+\r
+\r
+static const unsigned portSHORT heapSTRUCT_SIZE = ( sizeof( xBlockLink ) + ( sizeof( xBlockLink ) % portBYTE_ALIGNMENT ) );\r
+#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )\r
+\r
+/* Create a couple of list links to mark the start and end of the list. */\r
+static xBlockLink xStart, xEnd;\r
+static xHeapStruct *xHeap = NULL;\r
+ \r
+/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */\r
+\r
+/*\r
+ * Insert a block into the list of free blocks - which is ordered by size of\r
+ * the block. Small blocks at the start of the list and large blocks at the end\r
+ * of the list.\r
+ */\r
+#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \\r
+{ \\r
+xBlockLink *pxIterator; \\r
+size_t xBlockSize; \\r
+ \\r
+ xBlockSize = pxBlockToInsert->xBlockSize; \\r
+ \\r
+ /* Iterate through the list until a block is found that has a larger size */ \\r
+ /* than the block we are inserting. */ \\r
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \\r
+ { \\r
+ /* There is nothing to do here - just iterate to the correct position. */ \\r
+ } \\r
+ \\r
+ /* Update the list to include the block being inserted in the correct */ \\r
+ /* position. */ \\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \\r
+ pxIterator->pxNextFreeBlock = pxBlockToInsert; \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#define prvHeapInit() \\r
+{ \\r
+xBlockLink *pxFirstFreeBlock; \\r
+ \\r
+ /* Point to the start of the heap. */ \\r
+ xHeap = ( void * ) ( ( unsigned portLONG ) __SP_INIT + 4UL ); \\r
+ xHeap->ucHeap = ( void * ) xHeap; \\r
+ \\r
+ /* xStart is used to hold a pointer to the first item in the list of free */ \\r
+ /* blocks. The void cast is used to prevent compiler warnings. */ \\r
+ xStart.pxNextFreeBlock = ( void * ) xHeap->ucHeap; \\r
+ xStart.xBlockSize = ( size_t ) 0; \\r
+ \\r
+ /* xEnd is used to mark the end of the list of free blocks. */ \\r
+ xEnd.xBlockSize = heapTOTAL_SIZE; \\r
+ xEnd.pxNextFreeBlock = NULL; \\r
+ \\r
+ /* To start with there is a single free block that is sized to take up the \\r
+ entire heap space. */ \\r
+ pxFirstFreeBlock = ( void * ) xHeap->ucHeap; \\r
+ pxFirstFreeBlock->xBlockSize = heapTOTAL_SIZE; \\r
+ pxFirstFreeBlock->pxNextFreeBlock = &xEnd; \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void *pvPortMalloc( size_t xWantedSize )\r
+{\r
+xBlockLink *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\r
+static portBASE_TYPE xHeapHasBeenInitialised = pdFALSE;\r
+void *pvReturn = NULL;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ /* If this is the first call to malloc then the heap will require\r
+ initialisation to setup the list of free blocks. */\r
+ if( xHeapHasBeenInitialised == pdFALSE )\r
+ {\r
+ prvHeapInit();\r
+ xHeapHasBeenInitialised = pdTRUE;\r
+ }\r
+\r
+ /* The wanted size is increased so it can contain a xBlockLink\r
+ structure in addition to the requested amount of bytes. */\r
+ if( xWantedSize > 0 )\r
+ {\r
+ xWantedSize += heapSTRUCT_SIZE;\r
+\r
+ /* Ensure that blocks are always aligned to the required number of bytes. */\r
+ if( xWantedSize & heapBYTE_ALIGNMENT_MASK )\r
+ {\r
+ /* Byte alignment required. */\r
+ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) );\r
+ }\r
+ }\r
+\r
+ if( ( xWantedSize > 0 ) && ( xWantedSize < heapTOTAL_SIZE ) )\r
+ {\r
+ /* Blocks are stored in byte order - traverse the list from the start\r
+ (smallest) block until one of adequate size is found. */\r
+ pxPreviousBlock = &xStart;\r
+ pxBlock = xStart.pxNextFreeBlock;\r
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock ) )\r
+ {\r
+ pxPreviousBlock = pxBlock;\r
+ pxBlock = pxBlock->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If we found the end marker then a block of adequate size was not found. */\r
+ if( pxBlock != &xEnd )\r
+ {\r
+ /* Return the memory space - jumping over the xBlockLink structure\r
+ at its start. */\r
+ pvReturn = ( void * ) ( ( ( unsigned portCHAR * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );\r
+\r
+ /* This block is being returned for use so must be taken our of the\r
+ list of free blocks. */\r
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
+\r
+ /* If the block is larger than required it can be split into two. */\r
+ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )\r
+ {\r
+ /* This block is to be split into two. Create a new block\r
+ following the number of bytes requested. The void cast is\r
+ used to prevent byte alignment warnings from the compiler. */\r
+ pxNewBlockLink = ( void * ) ( ( ( unsigned portCHAR * ) pxBlock ) + xWantedSize );\r
+\r
+ /* Calculate the sizes of two blocks split from the single\r
+ block. */\r
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\r
+ pxBlock->xBlockSize = xWantedSize;\r
+\r
+ /* Insert the new block into the list of free blocks. */\r
+ prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );\r
+ }\r
+ }\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ if( pvReturn == NULL )\r
+ {\r
+ asm volatile ("NOP");\r
+ }\r
+\r
+ return pvReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortFree( void *pv )\r
+{\r
+unsigned portCHAR *puc = ( unsigned portCHAR * ) pv;\r
+xBlockLink *pxLink;\r
+\r
+ if( pv )\r
+ {\r
+ /* The memory being freed will have an xBlockLink structure immediately\r
+ before it. */\r
+ puc -= heapSTRUCT_SIZE;\r
+\r
+ /* This casting is to keep the compiler from issuing warnings. */\r
+ pxLink = ( void * ) puc;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ /* Add this block to the list of free blocks. */\r
+ prvInsertBlockIntoFreeList( ( ( xBlockLink * ) pxLink ) );\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/* Linker script for m52235evb
+ *
+ * Version:Sourcery G++ Lite 4.2-125
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007, 2008 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_ARCH(m68k)
+ENTRY(_start)
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3coldfire)
+
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 256K
+ ipsbar (rw) : ORIGIN = 0x40000000, LENGTH = 2M
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_m52235evb)
+INCLUDE coldfire-names.inc
+EXTERN(__cs3_interrupt_vector_coldfire)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)
+EXTERN(_start)
+
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) / 20);
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __cs3_region_start_rom = .;
+ *(.cs3.region-head.rom)
+ ASSERT (. == __cs3_region_start_rom, ".cs3.region-head.rom not permitted");
+ __cs3_interrupt_vector = __cs3_interrupt_vector_coldfire;
+ *(.cs3.interrupt_vector)
+ /* Make sure we pulled in an interrupt vector. */
+ ASSERT (. != __cs3_interrupt_vector_coldfire, "No interrupt vector");
+
+ PROVIDE(__cs3_reset_m52235evb = _start);
+ __cs3_reset = __cs3_reset_m52235evb;
+ *(.cs3.reset)
+
+ *(.text .text.* .gnu.linkonce.t.*)
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.jcr))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))
+ KEEP (*crtend.o(.jcr))
+
+ . = ALIGN(0x4);
+ *(.gcc_except_table .gcc_except_table.*)
+ } >rom
+ .eh_frame_hdr : ALIGN (4)
+ {
+ KEEP (*(.eh_frame_hdr))
+ } >rom
+ .eh_frame : ALIGN (4)
+ {
+ KEEP (*(.eh_frame))
+ } >rom
+ .rodata : ALIGN (4)
+ {
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ . = ALIGN(4);
+ _init = .;
+ LONG (0x4e560000) /* linkw %fp,#0 */
+ KEEP(*(.init))
+ SHORT (0x4e5e) /* unlk %fp */
+ SHORT (0x4e75) /* rts */
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ _fini = .;
+ LONG (0x4e560000) /* linkw %fp,#0 */
+ KEEP(*(.fini))
+ SHORT (0x4e5e) /* unlk %fp */
+ SHORT (0x4e75) /* rts */
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ *(.lit)
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
+ __cs3_regions_end = .;
+
+ . = ALIGN (8);
+ . = ALIGN (8);
+ *(.rom)
+ *(.rom.b)
+ _etext = .;
+ } >rom
+ /* __cs3_region_end_rom is deprecated */
+ __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);
+ __cs3_region_size_rom = LENGTH(rom);
+
+ .cs3.ipsbar :
+ {
+ __cs3_region_start_ipsbar = .;
+ *(.cs3.region-head.ipsbar)
+ . = ALIGN (8);
+ } >ipsbar
+ /* __cs3_region_end_ipsbar is deprecated */
+ __cs3_region_end_ipsbar = __cs3_region_start_ipsbar + LENGTH(ipsbar);
+ __cs3_region_size_ipsbar = LENGTH(ipsbar);
+
+ .data : ALIGN (8)
+ {
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ . = ALIGN (8);
+ *(.ram)
+ _edata = .;
+ } >ram AT>rom
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN (8);
+ *(.ram.b)
+ _end = .;
+ __end = .;
+ } >ram AT>rom
+ /* __cs3_region_end_ram is deprecated */
+ __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_init_ram = LOADADDR (.data);
+ __cs3_region_init_size_ram = _edata - ADDR (.data);
+ __cs3_region_zero_size_ram = _end - _edata;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
--- /dev/null
+/* Linker script for m52235evb
+ *
+ * Version:Sourcery G++ Lite 4.2-125
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007, 2008 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_ARCH(m68k)
+ENTRY(_start)
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lcs3 -lcs3hosted -lcs3coldfire)
+
+MEMORY
+{
+ ram (rw) : ORIGIN = 0x20000000, LENGTH = 32K\r
+ vectorrom (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400\r
+ cfmprotrom (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000020
+ rom (rx) : ORIGIN = 0x00000420, LENGTH = 256K - 0x400 - 0x20
+ ipsbar (rw) : ORIGIN = 0x40000000, LENGTH = 2M
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_m52235evb)
+INCLUDE coldfire-names.inc
+EXTERN(__cs3_interrupt_vector_coldfire)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)
+EXTERN(_start)
+/* force exit to be picked up in a hosted or os environment */
+EXTERN(exit atexit)
+
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) / 20);
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+\r
+ .vectors_table :\r
+ {\r
+ CREATE_OBJECT_SYMBOLS\r
+ __cs3_region_start_rom = .;\r
+ *(.cs3.region-head.rom)\r
+ ASSERT (. == __cs3_region_start_rom, ".cs3.region-head.rom not permitted");\r
+ __cs3_interrupt_vector = __cs3_interrupt_vector_coldfire;\r
+ *(.cs3.interrupt_vector)\r
+ /* Make sure we pulled in an interrupt vector. */\r
+ ASSERT (. != __cs3_interrupt_vector_coldfire, "No interrupt vector");\r
+ } > vectorrom\r
+\r
+ .cfmprotect :\r
+ {\r
+ *(.cfmconfig)\r
+ . = ALIGN (0x4);\r
+ } > cfmprotrom\r
+\r
+
+ .text :
+ {
+
+ PROVIDE(__cs3_reset_m52235evb = _start);
+ __cs3_reset = __cs3_reset_m52235evb;
+ *(.cs3.reset)
+
+ *(.text .text.* .gnu.linkonce.t.*)
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.jcr))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .jcr))
+ KEEP (*crtend.o(.jcr))
+
+ . = ALIGN(0x4);
+ *(.gcc_except_table .gcc_except_table.*)
+ } >rom
+ .eh_frame_hdr : ALIGN (4)
+ {
+ KEEP (*(.eh_frame_hdr))
+ } >rom
+ .eh_frame : ALIGN (4)
+ {
+ KEEP (*(.eh_frame))
+ } >rom
+ .rodata : ALIGN (4)
+ {
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ . = ALIGN(4);
+ _init = .;
+ LONG (0x4e560000) /* linkw %fp,#0 */
+ KEEP(*(.init))
+ SHORT (0x4e5e) /* unlk %fp */
+ SHORT (0x4e75) /* rts */
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ _fini = .;
+ LONG (0x4e560000) /* linkw %fp,#0 */
+ KEEP(*(.fini))
+ SHORT (0x4e5e) /* unlk %fp */
+ SHORT (0x4e75) /* rts */
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ *(.lit)
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
+ __cs3_regions_end = .;
+
+ . = ALIGN (8);
+ . = ALIGN (8);
+ *(.rom)
+ *(.rom.b)
+ _etext = .;
+ } >rom
+ /* __cs3_region_end_rom is deprecated */
+ __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);
+ __cs3_region_size_rom = LENGTH(rom);
+
+ .cs3.ipsbar :
+ {
+ __cs3_region_start_ipsbar = .;
+ *(.cs3.region-head.ipsbar)
+ . = ALIGN (8);
+ } >ipsbar
+ /* __cs3_region_end_ipsbar is deprecated */
+ __cs3_region_end_ipsbar = __cs3_region_start_ipsbar + LENGTH(ipsbar);
+ __cs3_region_size_ipsbar = LENGTH(ipsbar);
+
+ .data : ALIGN (8)
+ {
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ . = ALIGN (8);
+ *(.ram)
+ _edata = .;
+ } >ram AT>rom
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN (8);
+ *(.ram.b)
+ _end = .;
+ __end = .;
+ } >ram AT>rom
+ /* __cs3_region_end_ram is deprecated */
+ __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_init_ram = LOADADDR (.data);
+ __cs3_region_init_size_ram = _edata - ADDR (.data);
+ __cs3_region_zero_size_ram = _end - _edata;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
--- /dev/null
+/*\r
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+unsigned char *uip_buf;\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the standard demo application tasks.\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Check" task - This only executes every five seconds but has a high priority\r
+ * to ensure it gets processor time. Its main function is to check that all the\r
+ * standard demo tasks are still operational. While no errors have been\r
+ * discovered the check task will toggle an LED every 5 seconds - the toggle\r
+ * rate increasing to 500ms being a visual indication that at least one task has\r
+ * reported unexpected behaviour.\r
+ *\r
+ * "Reg test" tasks - These fill the registers with known values, then check\r
+ * that each register still contains its expected value. Each task uses\r
+ * different values. The tasks run with very low priority so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app includes. */\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "semtest.h"\r
+#include "PollQ.h"\r
+#include "GenQTest.h"\r
+#include "QPeek.h"\r
+#include "IntQueue.h"\r
+#include "comtest2.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The time between cycles of the 'check' functionality - as described at the\r
+top of this file. */\r
+#define mainNO_ERROR_PERIOD ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+\r
+/* The rate at which the LED controlled by the 'check' task will flash should an\r
+error have been detected. */\r
+#define mainERROR_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+\r
+/* The LED controlled by the 'check' task. */\r
+#define mainCHECK_LED ( 3 )\r
+\r
+/* ComTest constants - there is no free LED for the comtest tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 19200 )\r
+#define mainCOM_TEST_LED ( 5 )\r
+\r
+/* Task priorities. */\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The WEB server task uses more stack than most other tasks because of its\r
+reliance on using sprintf(). */
+#define mainBASIC_WEB_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/*\r
+ * Configure the hardware for the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Implements the 'check' task functionality as described at the top of this\r
+ * file.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * The task that implements the WEB server.
+ */\r
+extern void vuIP_Task( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Setup the hardware ready for this demo. */\r
+ prvSetupHardware();\r
+\r
+ /* Create the WEB server task. */\r
+ xTaskCreate( vuIP_Task, ( signed portCHAR * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
+\r
+ /* Start the standard demo tasks. */\r
+ vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+ vStartQueuePeekTasks();\r
+\r
+ /* Create the check task. */\r
+ xTaskCreate( prvCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only get here if there was insufficient memory to create the idle\r
+ task. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+unsigned ulTicksToWait = mainNO_ERROR_PERIOD, ulError = 0;\r
+portTickType xLastExecutionTime;\r
+\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise the variable used to control our iteration rate prior to\r
+ its first use. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time to run the tests again. */\r
+ vTaskDelayUntil( &xLastExecutionTime, ulTicksToWait );\r
+\r
+ /* Has an error been found in any task? */\r
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x01UL;\r
+ }\r
+\r
+ if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x02UL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x04UL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x20UL;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x40UL;\r
+ }\r
+\r
+ /* If an error has been found then increase our cycle rate, and in so\r
+ going increase the rate at which the check task LED toggles. */\r
+ if( ulError != 0 )\r
+ {\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ }\r
+\r
+ /* Toggle the LED each itteration. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetupHardware( void )\r
+{\r
+__attribute__ ((section(".cfmconfig")))\r
+static const unsigned long _cfm[6] = {\r
+ 0, /* KEY_UPPER 0x00000400 */\r
+ 0, /* KEY_LOWER 0x00000404 */\r
+ 0, /* CFMPROT 0x00000408 */\r
+ 0, /* CFMSACC 0x0000040C */\r
+ 0, /* CFMDACC 0x00000410 */\r
+ 0, /* CFMSEC 0x00000414 */\r
+};\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) _cfm;\r
+\r
+ /* Ensure the watchdog is disabled. */\r
+ MCF_SCM_CWCR = 0;\r
+\r
+ /* Initialize IPSBAR (0x40000000). */\r
+ asm volatile(\r
+ "move.l #0x40000000,%d0 \n"\r
+ "andi.l #0xC0000000,%d0 \n"\r
+ "add.l #0x1,%d0 \n"\r
+ "move.l %d0,0x40000000 "\r
+ );\r
+\r
+ /* Initialize FLASHBAR (0x00) */\r
+ asm volatile(\r
+ "move.l #0x00,%d0 \n"\r
+ "andi.l #0xFFF80000,%d0 \n"\r
+ "add.l #0x41,%d0 \n"\r
+ "movec %d0,%FLASHBAR "\r
+ );\r
+\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ /* RAMBAR. */\r
+ MCF_SCM_RAMBAR = MCF_SCM_RAMBAR_BA( RAMBAR_ADDRESS ) | MCF_SCM_RAMBAR_BDE;\r
+\r
+ /* Multiply 25MHz crystal by 12 to get 60MHz clock. */\r
+ MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(4) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;\r
+ while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))\r
+ {\r
+ }\r
+\r
+ /* Setup the port used to toggle LEDs. */\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )\r
+{\r
+ /* This will get called if a stack overflow is detected during the context\r
+ switch. Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack\r
+ problems within nested interrupts, but only do this for debug purposes as\r
+ it will increase the context switch time. */\r
+\r
+ ( void ) pxTask;\r
+ ( void ) pcTaskName;\r
+\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.\r
+\r
+NOTE: This driver is primarily to test the scheduler functionality. It does\r
+not effectively use the buffers or DMA and is therefore not intended to be\r
+an example of an efficient driver. */\r
+\r
+/* Standard include file. */\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo app include files. */\r
+#include "serial.h"\r
+\r
+/* Hardware definitions. */\r
+#define serNO_PARITY ( ( unsigned portCHAR ) 0x02 << 3 )\r
+#define ser8DATA_BITS ( ( unsigned portCHAR ) 0x03 )\r
+#define ser1STOP_BIT ( ( unsigned portCHAR ) 0x07 )\r
+#define serSYSTEM_CLOCK ( ( unsigned portCHAR ) 0xdd )\r
+#define serTX_OUTPUT ( ( unsigned portCHAR ) 0x04 )\r
+#define serRX_INPUT ( ( unsigned portCHAR ) 0x08 )\r
+#define serTX_ENABLE ( ( unsigned portCHAR ) 0x04 )\r
+#define serRX_ENABLE ( ( unsigned portCHAR ) 0x01 )\r
+#define serTX_INT ( ( unsigned portCHAR ) 0x01 )\r
+#define serRX_INT ( ( unsigned portCHAR ) 0x02 )\r
+\r
+\r
+/* The queues used to communicate between tasks and ISR's. */\r
+static xQueueHandle xRxedChars;\r
+static xQueueHandle xCharsForTx;\r
+\r
+/* Flag used to indicate the tx status. */\r
+static portBASE_TYPE xTxHasEnded = pdTRUE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The UART interrupt handler. */\r
+void __attribute__( ( interrupt ) ) __cs3_isr_interrupt_78( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+const unsigned portLONG ulBaudRateDivisor = ( configCPU_CLOCK_HZ / ( 32UL * ulWantedBaud ) );\r
+\r
+ /* Create the queues used by the com test task. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ xTxHasEnded = pdTRUE;\r
+\r
+ /* Set the pins to UART mode. */\r
+//_RB_ MCF_PAD_PUASAR |= ( serTX_OUTPUT | serRX_INPUT );\r
+\r
+ /* Reset the peripheral. */\r
+ MCF_UART1_UCR = MCF_UART_UCR_RESET_RX;\r
+ MCF_UART1_UCR = MCF_UART_UCR_RESET_TX;\r
+ MCF_UART1_UCR = MCF_UART_UCR_RESET_ERROR;\r
+ MCF_UART1_UCR = MCF_UART_UCR_RESET_BKCHGINT;\r
+ MCF_UART1_UCR = MCF_UART_UCR_RESET_MR | MCF_UART_UCR_RX_DISABLED | MCF_UART_UCR_TX_DISABLED;\r
+\r
+ /* Configure the UART. */\r
+ MCF_UART1_UMR1 = serNO_PARITY | ser8DATA_BITS;\r
+ MCF_UART1_UMR2 = ser1STOP_BIT;\r
+ MCF_UART1_UCSR = serSYSTEM_CLOCK;\r
+\r
+ MCF_UART1_UBG1 = ( unsigned portCHAR ) ( ( ulBaudRateDivisor >> 8UL ) & 0xffUL );\r
+ MCF_UART1_UBG2 = ( unsigned portCHAR ) ( ulBaudRateDivisor & 0xffUL );\r
+\r
+ /* Turn it on. */\r
+ MCF_UART1_UCR = serTX_ENABLE | serRX_ENABLE;\r
+\r
+ /* Configure the interrupt controller. Run the UARTs above the kernel\r
+ interrupt priority for demo purposes. */\r
+ MCF_INTC0_ICR14 = ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 ) << 3 );\r
+ MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK14 | 0x01 );\r
+\r
+ /* The Tx interrupt is not enabled until there is data to send. */\r
+ MCF_UART1_UIMR = serRX_INT;\r
+\r
+ /* Only a single port is implemented so we don't need to return anything. */\r
+ return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* Only one port is supported. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+ /* Only one port is supported. */\r
+ ( void ) pxPort;\r
+\r
+ /* Return false if after the block time there is no room on the Tx queue. */\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ return pdFAIL;\r
+ }\r
+\r
+ /* A critical section should not be required as xTxHasEnded will not be\r
+ written to by the ISR if it is already 0 (is this correct?). */\r
+ if( xTxHasEnded != pdFALSE )\r
+ {\r
+ xTxHasEnded = pdFALSE;\r
+ MCF_UART1_UIMR = serRX_INT | serTX_INT;\r
+ }\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ ( void ) xPort;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void __cs3_isr_interrupt_78( void )\r
+{\r
+unsigned portCHAR ucChar;\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE, xDoneSomething = pdTRUE;\r
+\r
+ while( xDoneSomething != pdFALSE )\r
+ {\r
+ xDoneSomething = pdFALSE;\r
+\r
+ /* Does the tx buffer contain space? */\r
+ if( ( MCF_UART1_USR & MCF_UART_USR_TXRDY ) != 0x00 )\r
+ {\r
+ /* Are there any characters queued to be sent? */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &ucChar, &xHigherPriorityTaskWoken ) == pdTRUE )\r
+ {\r
+ /* Send the next char. */\r
+ MCF_UART1_UTB = ucChar;\r
+ xDoneSomething = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ /* Turn off the Tx interrupt until such time as another character\r
+ is being transmitted. */\r
+ MCF_UART1_UIMR = serRX_INT;\r
+ xTxHasEnded = pdTRUE;\r
+ }\r
+ }\r
+\r
+ if( MCF_UART1_USR & MCF_UART_USR_RXRDY )\r
+ {\r
+ ucChar = MCF_UART1_URB;\r
+ xQueueSendFromISR( xRxedChars, &ucChar, &xHigherPriorityTaskWoken );\r
+ xDoneSomething = pdTRUE;\r
+ }\r
+ }\r
+\r
+ portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "semphr.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "fecbd.h"\r
+#include "mii.h"\r
+#include "eth_phy.h"\r
+#include "eth.h"\r
+\r
+/* uIP includes. */\r
+#include "uip.h"\r
+#include "uip_arp.h"\r
+\r
+#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)\r
+#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10)\r
+\r
+/* Delay between polling the PHY to see if a link has been established. */\r
+#define fecLINK_DELAY ( 500 / portTICK_RATE_MS )\r
+\r
+/* Delay to wait for an MII access. */\r
+#define fecMII_DELAY ( 10 / portTICK_RATE_MS )\r
+#define fecMAX_POLLS ( 20 )\r
+\r
+/* Delay between looking for incoming packets. In ideal world this would be\r
+infinite. */\r
+#define netifBLOCK_TIME_WAITING_FOR_INPUT fecLINK_DELAY\r
+\r
+/* Constants used to delay while waiting for a tx descriptor to be free. */\r
+#define fecMAX_TX_WAIT_ATTEMPTS 4\r
+#define fecTX_BUFFER_WAIT ( 10 / portTICK_RATE_MS )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The semaphore used to wake the uIP task when data arrives. */\r
+xSemaphoreHandle xFECSemaphore = NULL;\r
+\r
+/* The buffer used by the uIP stack. In this case the pointer is used to\r
+point to one of the Rx buffers. */\r
+unsigned portCHAR *uip_buf;\r
+\r
+/* The DMA descriptors. This is a char array to allow us to align it correctly. */\r
+static unsigned portCHAR xFECTxDescriptors_unaligned[ ( configNUM_FEC_TX_BUFFERS * sizeof( FECBD ) ) + 16 ];\r
+static unsigned portCHAR xFECRxDescriptors_unaligned[ ( configNUM_FEC_RX_BUFFERS * sizeof( FECBD ) ) + 16 ];\r
+static FECBD *xFECTxDescriptors;\r
+static FECBD *xFECRxDescriptors;\r
+\r
+/* The DMA buffers. These are char arrays to allow them to be alligned correctly. */\r
+static unsigned portCHAR ucFECRxBuffers[ ( configNUM_FEC_RX_BUFFERS * configFEC_BUFFER_SIZE ) + 16 ];\r
+static unsigned portBASE_TYPE uxNextRxBuffer = 0, uxNextTxBuffer = 0, uxIndexToBufferOwner = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvEnableFECInterrupts( void );\r
+\r
+/********************************************************************/\r
+/*\r
+ * Write a value to a PHY's MII register.\r
+ *\r
+ * Parameters:\r
+ * ch FEC channel\r
+ * phy_addr Address of the PHY.\r
+ * reg_addr Address of the register in the PHY.\r
+ * data Data to be written to the PHY register.\r
+ *\r
+ * Return Values:\r
+ * 0 on failure\r
+ * 1 on success.\r
+ *\r
+ * Please refer to your PHY manual for registers and their meanings.\r
+ * mii_write() polls for the FEC's MII interrupt event and clears it.\r
+ * If after a suitable amount of time the event isn't triggered, a\r
+ * value of 0 is returned.\r
+ */\r
+static int fec_mii_write( int phy_addr, int reg_addr, int data )\r
+{\r
+int timeout, iReturn;\r
+uint32 eimr;\r
+\r
+ /* Clear the MII interrupt bit */\r
+ MCF_FEC_EIR = MCF_FEC_EIR_MII;\r
+\r
+ /* Mask the MII interrupt */\r
+ eimr = MCF_FEC_EIMR;\r
+ MCF_FEC_EIMR &= ~MCF_FEC_EIMR_MII;\r
+\r
+ /* Write to the MII Management Frame Register to kick-off the MII write */\r
+ MCF_FEC_MMFR = MCF_FEC_MMFR_ST_01 | MCF_FEC_MMFR_OP_WRITE | MCF_FEC_MMFR_PA(phy_addr) | MCF_FEC_MMFR_RA(reg_addr) | MCF_FEC_MMFR_TA_10 | MCF_FEC_MMFR_DATA( data );\r
+\r
+ /* Poll for the MII interrupt (interrupt should be masked) */\r
+ for( timeout = 0; timeout < fecMAX_POLLS; timeout++ )\r
+ {\r
+ if( MCF_FEC_EIR & MCF_FEC_EIR_MII )\r
+ {\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ vTaskDelay( fecMII_DELAY );\r
+ }\r
+ }\r
+\r
+ if( timeout == fecMAX_POLLS )\r
+ {\r
+ iReturn = 0;\r
+ }\r
+ else\r
+ {\r
+ iReturn = 1;\r
+ }\r
+\r
+ /* Clear the MII interrupt bit */\r
+ MCF_FEC_EIR = MCF_FEC_EIR_MII;\r
+\r
+ /* Restore the EIMR */\r
+ MCF_FEC_EIMR = eimr;\r
+\r
+ return iReturn;\r
+}\r
+\r
+/********************************************************************/\r
+/*\r
+ * Read a value from a PHY's MII register.\r
+ *\r
+ * Parameters:\r
+ * ch FEC channel\r
+ * phy_addr Address of the PHY.\r
+ * reg_addr Address of the register in the PHY.\r
+ * data Pointer to storage for the Data to be read\r
+ * from the PHY register (passed by reference)\r
+ *\r
+ * Return Values:\r
+ * 0 on failure\r
+ * 1 on success.\r
+ *\r
+ * Please refer to your PHY manual for registers and their meanings.\r
+ * mii_read() polls for the FEC's MII interrupt event and clears it.\r
+ * If after a suitable amount of time the event isn't triggered, a\r
+ * value of 0 is returned.\r
+ */\r
+static int fec_mii_read( int phy_addr, int reg_addr, unsigned portSHORT* data )\r
+{\r
+int timeout, iReturn;\r
+uint32 eimr;\r
+\r
+ /* Clear the MII interrupt bit */\r
+ MCF_FEC_EIR = MCF_FEC_EIR_MII;\r
+\r
+ /* Mask the MII interrupt */\r
+ eimr = MCF_FEC_EIMR;\r
+ MCF_FEC_EIMR &= ~MCF_FEC_EIMR_MII;\r
+\r
+ /* Write to the MII Management Frame Register to kick-off the MII read */\r
+ MCF_FEC_MMFR = MCF_FEC_MMFR_ST_01 | MCF_FEC_MMFR_OP_READ | MCF_FEC_MMFR_PA(phy_addr) | MCF_FEC_MMFR_RA(reg_addr) | MCF_FEC_MMFR_TA_10;\r
+\r
+ /* Poll for the MII interrupt (interrupt should be masked) */\r
+ for( timeout = 0; timeout < fecMAX_POLLS; timeout++ )\r
+ {\r
+ if (MCF_FEC_EIR & MCF_FEC_EIR_MII)\r
+ {\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ vTaskDelay( fecMII_DELAY );\r
+ }\r
+ }\r
+\r
+ if( timeout == fecMAX_POLLS )\r
+ {\r
+ iReturn = 0;\r
+ }\r
+ else\r
+ {\r
+ *data = (uint16)(MCF_FEC_MMFR & 0x0000FFFF);\r
+ iReturn = 1;\r
+ }\r
+\r
+ /* Clear the MII interrupt bit */\r
+ MCF_FEC_EIR = MCF_FEC_EIR_MII;\r
+\r
+ /* Restore the EIMR */\r
+ MCF_FEC_EIMR = eimr;\r
+\r
+ return iReturn;\r
+}\r
+\r
+\r
+/********************************************************************/\r
+/*\r
+ * Generate the hash table settings for the given address\r
+ *\r
+ * Parameters:\r
+ * addr 48-bit (6 byte) Address to generate the hash for\r
+ *\r
+ * Return Value:\r
+ * The 6 most significant bits of the 32-bit CRC result\r
+ */\r
+static unsigned portCHAR fec_hash_address( const unsigned portCHAR* addr )\r
+{\r
+unsigned portLONG crc;\r
+unsigned portCHAR byte;\r
+int i, j;\r
+\r
+ crc = 0xFFFFFFFF;\r
+ for(i=0; i<6; ++i)\r
+ {\r
+ byte = addr[i];\r
+ for(j=0; j<8; ++j)\r
+ {\r
+ if((byte & 0x01)^(crc & 0x01))\r
+ {\r
+ crc >>= 1;\r
+ crc = crc ^ 0xEDB88320;\r
+ }\r
+ else\r
+ {\r
+ crc >>= 1;\r
+ }\r
+\r
+ byte >>= 1;\r
+ }\r
+ }\r
+\r
+ return (unsigned portCHAR)(crc >> 26);\r
+}\r
+\r
+/********************************************************************/\r
+/*\r
+ * Set the Physical (Hardware) Address and the Individual Address\r
+ * Hash in the selected FEC\r
+ *\r
+ * Parameters:\r
+ * ch FEC channel\r
+ * pa Physical (Hardware) Address for the selected FEC\r
+ */\r
+static void fec_set_address( const unsigned portCHAR *pa )\r
+{\r
+ unsigned portCHAR crc;\r
+\r
+ /*\r
+ * Set the Physical Address\r
+ */\r
+ /* Set the source address for the controller */\r
+ MCF_FEC_PALR = ( pa[ 0 ] << 24 ) | ( pa[ 1 ] << 16 ) | ( pa[ 2 ] << 8 ) | ( pa[ 3 ] << 0 );\r
+ MCF_FEC_PAUR = ( pa[ 4 ] << 24 ) | ( pa[ 5 ] << 16 );\r
+\r
+ /*\r
+ * Calculate and set the hash for given Physical Address\r
+ * in the Individual Address Hash registers\r
+ */\r
+ crc = fec_hash_address( pa );\r
+ if( crc >= 32 )\r
+ {\r
+ MCF_FEC_IAUR |= (unsigned portLONG)(1 << (crc - 32));\r
+ }\r
+ else\r
+ {\r
+ MCF_FEC_IALR |= (unsigned portLONG)(1 << crc);\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvInitialiseFECBuffers( void )\r
+{\r
+unsigned portBASE_TYPE ux;\r
+unsigned portCHAR *pcBufPointer;\r
+\r
+ pcBufPointer = &( xFECTxDescriptors_unaligned[ 0 ] );\r
+ while( ( ( unsigned portLONG ) pcBufPointer & 0x0fUL ) != 0 )\r
+ {\r
+ pcBufPointer++;\r
+ }\r
+\r
+ xFECTxDescriptors = ( FECBD * ) pcBufPointer;\r
+\r
+ pcBufPointer = &( xFECRxDescriptors_unaligned[ 0 ] );\r
+ while( ( ( unsigned portLONG ) pcBufPointer & 0x0fUL ) != 0 )\r
+ {\r
+ pcBufPointer++;\r
+ }\r
+\r
+ xFECRxDescriptors = ( FECBD * ) pcBufPointer;\r
+\r
+\r
+ /* Setup the buffers and descriptors. The data member does not point\r
+ anywhere yet as there is not yet anything to send and a zero copy policy\r
+ is used. */
+ for( ux = 0; ux < configNUM_FEC_TX_BUFFERS; ux++ )\r
+ {\r
+ xFECTxDescriptors[ ux ].status = TX_BD_TC;\r
+ xFECTxDescriptors[ ux ].data = NULL;\r
+ xFECTxDescriptors[ ux ].length = 0;\r
+ }\r
+\r
+ pcBufPointer = &( ucFECRxBuffers[ 0 ] );\r
+ while( ( ( unsigned portLONG ) pcBufPointer & 0x0fUL ) != 0 )\r
+ {\r
+ pcBufPointer++;\r
+ }\r
+\r
+ for( ux = 0; ux < configNUM_FEC_RX_BUFFERS; ux++ )\r
+ {\r
+ xFECRxDescriptors[ ux ].status = RX_BD_E;\r
+ xFECRxDescriptors[ ux ].length = configFEC_BUFFER_SIZE;\r
+ xFECRxDescriptors[ ux ].data = pcBufPointer;\r
+ pcBufPointer += configFEC_BUFFER_SIZE;\r
+ }\r
+\r
+ /* Set the wrap bit in the last descriptors to form a ring. */\r
+ xFECTxDescriptors[ configNUM_FEC_TX_BUFFERS - 1 ].status |= TX_BD_W;\r
+ xFECRxDescriptors[ configNUM_FEC_RX_BUFFERS - 1 ].status |= RX_BD_W;\r
+\r
+ uxNextRxBuffer = 0;\r
+ uxNextTxBuffer = 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vInitFEC( void )\r
+{\r
+unsigned portSHORT usData;\r
+struct uip_eth_addr xAddr;\r
+const unsigned portCHAR ucMACAddress[6] =\r
+{\r
+ configMAC_0, configMAC_1,configMAC_2, configMAC_3, configMAC_4, configMAC_5\r
+};\r
+\r
+ /* Create the semaphore used by the ISR to wake the uIP task. */\r
+ vSemaphoreCreateBinary( xFECSemaphore );\r
+\r
+ prvInitialiseFECBuffers();\r
+\r
+ for( usData = 0; usData < 6; usData++ )\r
+ {\r
+ xAddr.addr[ usData ] = ucMACAddress[ usData ];\r
+ }\r
+ uip_setethaddr( xAddr );\r
+\r
+ /* Set the Reset bit and clear the Enable bit */\r
+ MCF_FEC_ECR = MCF_FEC_ECR_RESET;\r
+\r
+ /* Wait at least 8 clock cycles */\r
+ for( usData = 0; usData < 10; usData++ )\r
+ {\r
+ asm( "NOP" );\r
+ }\r
+\r
+ /* Set MII speed to 2.5MHz. */\r
+ MCF_FEC_MSCR = MCF_FEC_MSCR_MII_SPEED( ( ( ( configCPU_CLOCK_HZ / 1000000 ) / 5 ) + 1 ) );\r
+\r
+ /* Initialize PLDPAR to enable Ethernet LEDs. */\r
+ MCF_GPIO_PLDPAR = MCF_GPIO_PLDPAR_ACTLED_ACTLED | MCF_GPIO_PLDPAR_LINKLED_LINKLED | MCF_GPIO_PLDPAR_SPDLED_SPDLED\r
+ | MCF_GPIO_PLDPAR_DUPLED_DUPLED | MCF_GPIO_PLDPAR_COLLED_COLLED | MCF_GPIO_PLDPAR_RXLED_RXLED\r
+ | MCF_GPIO_PLDPAR_TXLED_TXLED;\r
+\r
+ /* Initialize Port TA to enable Axcel control. */\r
+ MCF_GPIO_PTAPAR = 0x00;\r
+ MCF_GPIO_DDRTA = 0x0F;\r
+ MCF_GPIO_PORTTA = 0x04;\r
+\r
+ /* Set phy address to zero. */\r
+ MCF_EPHY_EPHYCTL1 = MCF_EPHY_EPHYCTL1_PHYADD( 0 );\r
+\r
+ /* Enable EPHY module with PHY clocks disabled. Do not turn on PHY clocks\r
+ until both FEC and EPHY are completely setup (see Below). */\r
+ MCF_EPHY_EPHYCTL0 = (uint8)(MCF_EPHY_EPHYCTL0_DIS100 | MCF_EPHY_EPHYCTL0_DIS10);\r
+\r
+ /* Enable auto_neg at start-up */\r
+ MCF_EPHY_EPHYCTL0 = (uint8)(MCF_EPHY_EPHYCTL0 & (MCF_EPHY_EPHYCTL0_ANDIS));\r
+\r
+ /* Enable EPHY module. */\r
+ MCF_EPHY_EPHYCTL0 = (uint8)(MCF_EPHY_EPHYCTL0_EPHYEN | MCF_EPHY_EPHYCTL0);\r
+\r
+ /* Let PHY PLLs be determined by PHY. */\r
+ MCF_EPHY_EPHYCTL0 = (uint8)(MCF_EPHY_EPHYCTL0 & ~(MCF_EPHY_EPHYCTL0_DIS100 | MCF_EPHY_EPHYCTL0_DIS10));\r
+\r
+ /* Settle. */\r
+ vTaskDelay( fecLINK_DELAY );\r
+\r
+ /* Can we talk to the PHY? */\r
+ do\r
+ {\r
+ vTaskDelay( fecLINK_DELAY );\r
+ usData = 0;\r
+ fec_mii_read( configPHY_ADDRESS, PHY_PHYIDR1, &usData );\r
+\r
+ } while( usData == 0xffff );\r
+\r
+ do\r
+ {\r
+ /* Start auto negotiate. */\r
+ fec_mii_write( configPHY_ADDRESS, PHY_BMCR, ( PHY_BMCR_AN_RESTART | PHY_BMCR_AN_ENABLE ) );\r
+\r
+ /* Wait for auto negotiate to complete. */\r
+ do\r
+ {\r
+ vTaskDelay( fecLINK_DELAY );\r
+ fec_mii_read( configPHY_ADDRESS, PHY_BMSR, &usData );\r
+\r
+ } while( !( usData & PHY_BMSR_AN_COMPLETE ) );\r
+\r
+ } while( 0 ); //while( !( usData & PHY_BMSR_LINK ) );\r
+\r
+ /* When we get here we have a link - find out what has been negotiated. */\r
+ fec_mii_read( configPHY_ADDRESS, PHY_ANLPAR, &usData );\r
+\r
+ if( ( usData & PHY_ANLPAR_100BTX_FDX ) || ( usData & PHY_ANLPAR_100BTX ) )\r
+ {\r
+ /* Speed is 100. */\r
+ }\r
+ else\r
+ {\r
+ /* Speed is 10. */\r
+ }\r
+\r
+ if( ( usData & PHY_ANLPAR_100BTX_FDX ) || ( usData & PHY_ANLPAR_10BTX_FDX ) )\r
+ {\r
+ MCF_FEC_RCR &= (unsigned portLONG)~MCF_FEC_RCR_DRT;\r
+ MCF_FEC_TCR |= MCF_FEC_TCR_FDEN;\r
+ }\r
+ else\r
+ {\r
+ MCF_FEC_RCR |= MCF_FEC_RCR_DRT;\r
+ MCF_FEC_TCR &= (unsigned portLONG)~MCF_FEC_TCR_FDEN;\r
+ }\r
+\r
+ /* Clear the Individual and Group Address Hash registers */\r
+ MCF_FEC_IALR = 0;\r
+ MCF_FEC_IAUR = 0;\r
+ MCF_FEC_GALR = 0;\r
+ MCF_FEC_GAUR = 0;\r
+\r
+ /* Set the Physical Address for the selected FEC */\r
+ fec_set_address( ucMACAddress );\r
+\r
+ /* Set Rx Buffer Size */\r
+ MCF_FEC_EMRBR = (unsigned portSHORT)configFEC_BUFFER_SIZE;\r
+\r
+ /* Point to the start of the circular Rx buffer descriptor queue */\r
+ MCF_FEC_ERDSR = ( volatile unsigned portLONG ) &( xFECRxDescriptors[ 0 ] );\r
+\r
+ /* Point to the start of the circular Tx buffer descriptor queue */\r
+ MCF_FEC_ETSDR = ( volatile unsigned portLONG ) &( xFECTxDescriptors[ 0 ] );\r
+\r
+ /* Mask all FEC interrupts */\r
+ MCF_FEC_EIMR = ( unsigned portLONG ) -1;\r
+\r
+ /* Clear all FEC interrupt events */\r
+ MCF_FEC_EIR = ( unsigned portLONG ) -1;\r
+\r
+ /* Initialize the Receive Control Register */\r
+ MCF_FEC_RCR = MCF_FEC_RCR_MAX_FL(ETH_MAX_FRM) | MCF_FEC_RCR_FCE;\r
+\r
+ MCF_FEC_RCR |= MCF_FEC_RCR_MII_MODE;\r
+\r
+ #if( configUSE_PROMISCUOUS_MODE == 1 )\r
+ {\r
+ MCF_FEC_RCR |= MCF_FEC_RCR_PROM;\r
+ }\r
+ #endif\r
+\r
+ prvEnableFECInterrupts();\r
+\r
+ MCF_FEC_ECR = MCF_FEC_ECR_ETHER_EN;\r
+ MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvEnableFECInterrupts( void )\r
+{\r
+const unsigned portBASE_TYPE uxFirstFECVector = 23, uxLastFECVector = 35;\r
+unsigned portBASE_TYPE ux;\r
+\r
+#if configFEC_INTERRUPT_PRIORITY > configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+ #error configFEC_INTERRUPT_PRIORITY must be less than or equal to configMAX_SYSCALL_INTERRUPT_PRIORITY\r
+#endif\r
+\r
+ for( ux = uxFirstFECVector; ux <= uxLastFECVector; ux++ )\r
+ {\r
+ MCF_INTC0_ICR( ux ) = MCF_INTC_ICR_IL( configFEC_INTERRUPT_PRIORITY );\r
+ }\r
+\r
+ /* Enable the FEC interrupts in the mask register */\r
+ MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK33 | MCF_INTC_IMRH_INT_MASK34 | MCF_INTC_IMRH_INT_MASK35 );\r
+ MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK25 | MCF_INTC_IMRL_INT_MASK26 | MCF_INTC_IMRL_INT_MASK27\r
+ | MCF_INTC_IMRL_INT_MASK28 | MCF_INTC_IMRL_INT_MASK29 | MCF_INTC_IMRL_INT_MASK30\r
+ | MCF_INTC_IMRL_INT_MASK31 | MCF_INTC_IMRL_MASKALL );\r
+\r
+ /* Clear any pending FEC interrupt events */\r
+ MCF_FEC_EIR = MCF_FEC_EIR_CLEAR_ALL;\r
+\r
+ /* Unmask all FEC interrupts */\r
+ MCF_FEC_EIMR = MCF_FEC_EIMR_UNMASK_ALL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned short usGetFECRxData( void )\r
+{\r
+unsigned portSHORT usLen;\r
+\r
+ /* Obtain the size of the packet and put it into the "len" variable. */\r
+ usLen = xFECRxDescriptors[ uxNextRxBuffer ].length;\r
+\r
+ if( ( usLen != 0 ) && ( ( xFECRxDescriptors[ uxNextRxBuffer ].status & RX_BD_E ) == 0 ) )\r
+ {\r
+ uip_buf = xFECRxDescriptors[ uxNextRxBuffer ].data;\r
+ }\r
+ else\r
+ {\r
+ usLen = 0;\r
+ }\r
+\r
+ return usLen;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vDiscardRxData( void )\r
+{\r
+ /* Free the descriptor as the buffer it points to is no longer in use. */\r
+ xFECRxDescriptors[ uxNextRxBuffer ].status |= RX_BD_E;\r
+ MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;\r
+ uxNextRxBuffer++;\r
+ if( uxNextRxBuffer >= configNUM_FEC_RX_BUFFERS )\r
+ {\r
+ uxNextRxBuffer = 0;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSendBufferToFEC( void )\r
+{\r
+portLONG l;\r
+\r
+ /* Get a DMA buffer into which we can write the data to send. */\r
+ for( l = 0; l < fecMAX_TX_WAIT_ATTEMPTS; l++ )\r
+ {\r
+ if( xFECTxDescriptors[ uxNextTxBuffer ].status & TX_BD_R )\r
+ {\r
+ /* Wait for the buffer to become available. */\r
+ vTaskDelay( fecTX_BUFFER_WAIT );\r
+ }\r
+ else\r
+ {\r
+ /* Setup the buffer descriptor for transmission. The data being\r
+ sent is actually stored in one of the Rx descripter buffers,\r
+ pointed to by uip_buf. */\r
+ xFECTxDescriptors[ uxNextTxBuffer ].length = uip_len;\r
+ xFECTxDescriptors[ uxNextTxBuffer ].status |= (TX_BD_R | TX_BD_L);\r
+ xFECTxDescriptors[ uxNextTxBuffer ].data = uip_buf;\r
+\r
+ /* Continue the Tx DMA (in case it was waiting for a new TxBD) */\r
+ MCF_FEC_TDAR = MCF_FEC_TDAR_X_DES_ACTIVE;\r
+\r
+ /* Remember which Rx descriptor owns the buffer we are sending. */\r
+ uxIndexToBufferOwner = uxNextRxBuffer;\r
+\r
+ uxNextTxBuffer++;\r
+ if( uxNextTxBuffer >= configNUM_FEC_TX_BUFFERS )\r
+ {\r
+ uxNextTxBuffer = 0;\r
+ }\r
+\r
+ /* We have finished with this Rx descriptor now. */\r
+ uxNextRxBuffer++;\r
+ if( uxNextRxBuffer >= configNUM_FEC_RX_BUFFERS )\r
+ {\r
+ uxNextRxBuffer = 0;\r
+ }\r
+\r
+ break;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vFEC_ISR( void )\r
+{\r
+unsigned portLONG ulEvent;\r
+portBASE_TYPE xHighPriorityTaskWoken = pdFALSE;\r
+\r
+ ulEvent = MCF_FEC_EIR & MCF_FEC_EIMR;\r
+ MCF_FEC_EIR = ulEvent;\r
+\r
+ if( ( ulEvent & MCF_FEC_EIR_RXB ) || ( ulEvent & MCF_FEC_EIR_RXF ) )\r
+ {\r
+ /* A packet has been received. Wake the handler task. */\r
+ xSemaphoreGiveFromISR( xFECSemaphore, &xHighPriorityTaskWoken );\r
+ }\r
+\r
+ if( ulEvent & ( MCF_FEC_EIR_UN | MCF_FEC_EIR_RL | MCF_FEC_EIR_LC | MCF_FEC_EIR_EBERR | MCF_FEC_EIR_BABT | MCF_FEC_EIR_BABR | MCF_FEC_EIR_HBERR ) )\r
+ {\r
+ /* Sledge hammer error handling. */\r
+ prvInitialiseFECBuffers();\r
+ MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;\r
+ }\r
+\r
+ if( ( ulEvent & MCF_FEC_EIR_TXF ) || ( ulEvent & MCF_FEC_EIR_TXB ) )\r
+ {\r
+ /* The buffer being sent is pointed to by an Rx descriptor, now the\r
+ buffer has been sent we can mark the Rx descriptor as free again. */\r
+ xFECRxDescriptors[ uxIndexToBufferOwner ].status |= RX_BD_E;\r
+ MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;\r
+ }\r
+\r
+ portEND_SWITCHING_ISR( xHighPriorityTaskWoken );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_88( void ) { vFEC_ISR(); }\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_89( void ) { vFEC_ISR(); }\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_90( void ) { vFEC_ISR(); }\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_91( void ) { vFEC_ISR(); }\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_92( void ) { vFEC_ISR(); }\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_93( void ) { vFEC_ISR(); }\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_94( void ) { vFEC_ISR(); }\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_95( void ) { vFEC_ISR(); }\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_96( void ) { vFEC_ISR(); }\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_97( void ) { vFEC_ISR(); }\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_98( void ) { vFEC_ISR(); }\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_99( void ) { vFEC_ISR(); }\r
+void __attribute__ ((interrupt)) __cs3_isr_interrupt_100( void ) { vFEC_ISR(); }\r
+\r
--- /dev/null
+/*\r
+ * File: fec.h\r
+ * Purpose: Driver for the Fast Ethernet Controller (FEC)\r
+ *\r
+ * Notes:\r
+ */\r
+\r
+#ifndef _FEC_H_\r
+#define _FEC_H_\r
+\r
+#include "eth.h"\r
+#include "fecbd.h"\r
+#include "mii.h"\r
+#include "eth_phy.h"\r
+\r
+/********************************************************************/\r
+\r
+/* External Interface Modes */\r
+#define FEC_MODE_7WIRE 0 /* Old 7-wire (AMD) mode */\r
+#define FEC_MODE_MII 1 /* Media Independent Interface */\r
+#define FEC_MODE_RMII 2 /* Reduced MII */\r
+#define FEC_MODE_LOOPBACK 3 /* Internal Loopback */\r
+\r
+#define INTC_LVL_FEC 3\r
+/*\r
+ * FEC Configuration Parameters\r
+ */\r
+typedef struct\r
+{\r
+ uint8 ch; /* FEC channel */\r
+ uint8 mode; /* Transceiver mode */\r
+ MII_SPEED speed; /* Ethernet Speed */\r
+ MII_DUPLEX duplex; /* Ethernet Duplex */\r
+ uint8 prom; /* Promiscuous Mode? */\r
+ uint8 mac[6]; /* Ethernet Address */\r
+ uint8 phyaddr; /* PHY address */\r
+ uint8 initphy; /* Init PHY? */\r
+ int nrxbd; /* Number of RxBDs */\r
+ int ntxbd; /* Number of TxBDs */\r
+} FEC_CONFIG;\r
+#define YES 1\r
+#define NO 0\r
+/*\r
+ * FEC Event Log\r
+ */\r
+typedef struct {\r
+ int errors; /* total count of errors */\r
+ int hberr; /* heartbeat error */\r
+ int babr; /* babbling receiver */\r
+ int babt; /* babbling transmitter */\r
+ int gra; /* graceful stop complete */\r
+ int txf; /* transmit frame */\r
+ int txb; /* transmit buffer */\r
+ int rxf; /* receive frame */\r
+ int rxb; /* received buffer */\r
+ int mii; /* MII */\r
+ int eberr; /* FEC/DMA fatal bus error */\r
+ int lc; /* late collision */\r
+ int rl; /* collision retry limit */\r
+ int un; /* Tx FIFO underflow */\r
+ int rfsw_inv; /* Invalid bit in RFSW */\r
+ int rfsw_l; /* RFSW Last in Frame */\r
+ int rfsw_m; /* RFSW Miss */\r
+ int rfsw_bc; /* RFSW Broadcast */\r
+ int rfsw_mc; /* RFSW Multicast */\r
+ int rfsw_lg; /* RFSW Length Violation */\r
+ int rfsw_no; /* RFSW Non-octet */\r
+ int rfsw_cr; /* RFSW Bad CRC */\r
+ int rfsw_ov; /* RFSW Overflow */\r
+ int rfsw_tr; /* RFSW Truncated */\r
+} FEC_EVENT_LOG;\r
+\r
+void vInitFEC( void );\r
+unsigned short usGetFECRxData( void );\r
+void vSendBufferToFEC( void );\r
+void vDiscardRxData( void );\r
+\r
+/********************************************************************/\r
+\r
+#endif /* _FEC_H_ */\r
--- /dev/null
+/*! \r
+ * \file eth.h\r
+ * \brief Definitinos for Ethernet Frames\r
+ * \version $Revision: 1.2 $\r
+ * \author Michael Norman\r
+ */\r
+\r
+#ifndef _ETH_H\r
+#define _ETH_H\r
+\r
+/*******************************************************************/\r
+\r
+/* Ethernet standard lengths in bytes*/\r
+#define ETH_ADDR_LEN (6)\r
+#define ETH_TYPE_LEN (2)\r
+#define ETH_CRC_LEN (4)\r
+#define ETH_MAX_DATA (1500)\r
+#define ETH_MIN_DATA (46)\r
+#define ETH_HDR_LEN (ETH_ADDR_LEN * 2 + ETH_TYPE_LEN)\r
+\r
+/* Defined Ethernet Frame Types */\r
+#define ETH_FRM_IP (0x0800)\r
+#define ETH_FRM_ARP (0x0806)\r
+#define ETH_FRM_RARP (0x8035)\r
+#define ETH_FRM_TEST (0xA5A5)\r
+\r
+/* Maximum and Minimum Ethernet Frame Sizes */\r
+#define ETH_MAX_FRM (ETH_HDR_LEN + ETH_MAX_DATA + ETH_CRC_LEN)\r
+#define ETH_MIN_FRM (ETH_HDR_LEN + ETH_MIN_DATA + ETH_CRC_LEN)\r
+#define ETH_MTU (ETH_HDR_LEN + ETH_MAX_DATA)\r
+\r
+/* Ethernet Addresses */\r
+typedef uint8 ETH_ADDR[ETH_ADDR_LEN];\r
+\r
+/* 16-bit Ethernet Frame Type, ie. Protocol */\r
+typedef uint16 ETH_FRM_TYPE;\r
+\r
+/* Ethernet Frame Header definition */\r
+typedef struct\r
+{\r
+ ETH_ADDR dest;\r
+ ETH_ADDR src;\r
+ ETH_FRM_TYPE type;\r
+} ETH_HDR;\r
+\r
+/* Ethernet Frame definition */\r
+typedef struct\r
+{\r
+ ETH_HDR head;\r
+ uint8* data;\r
+} ETH_FRAME;\r
+\r
+/*******************************************************************/\r
+\r
+#endif /* _ETH_H */\r
--- /dev/null
+/*!\r
+ * \file eth.h\r
+ * \brief Definitions for Ethernet Physical Layer Interface\r
+ * \version $Revision: 1.3 $\r
+ * \author Michael Norman\r
+ */\r
+\r
+#ifndef _ETH_PHY_H\r
+#define _ETH_PHY_H\r
+\r
+/*******************************************************************/\r
+\r
+int\r
+eth_phy_autoneg(int phy_addr, MII_SPEED speed, MII_DUPLEX duplex);\r
+\r
+int \r
+eth_phy_manual(int phy_addr, MII_SPEED speed, MII_DUPLEX duplex, int loop);\r
+\r
+int \r
+eth_phy_get_speed(int, int*);\r
+\r
+int \r
+eth_phy_get_duplex(int, int*);\r
+\r
+int \r
+eth_phy_reg_dump(int);\r
+\r
+/*******************************************************************/\r
+\r
+/* MII Register Addresses */\r
+#define PHY_BMCR (0x00)\r
+#define PHY_BMSR (0x01)\r
+#define PHY_PHYIDR1 (0x02)\r
+#define PHY_PHYIDR2 (0x03)\r
+#define PHY_ANAR (0x04)\r
+#define PHY_ANLPAR (0x05)\r
+\r
+/* Bit definitions and macros for PHY_CTRL */\r
+#define PHY_BMCR_RESET (0x8000)\r
+#define PHY_BMCR_LOOP (0x4000)\r
+#define PHY_BMCR_SPEED (0x2000)\r
+#define PHY_BMCR_AN_ENABLE (0x1000)\r
+#define PHY_BMCR_POWERDOWN (0x0800)\r
+#define PHY_BMCR_ISOLATE (0x0400)\r
+#define PHY_BMCR_AN_RESTART (0x0200)\r
+#define PHY_BMCR_FDX (0x0100)\r
+#define PHY_BMCR_COL_TEST (0x0080)\r
+\r
+/* Bit definitions and macros for PHY_STAT */\r
+#define PHY_BMSR_100BT4 (0x8000)\r
+#define PHY_BMSR_100BTX_FDX (0x4000)\r
+#define PHY_BMSR_100BTX (0x2000)\r
+#define PHY_BMSR_10BT_FDX (0x1000)\r
+#define PHY_BMSR_10BT (0x0800)\r
+#define PHY_BMSR_NO_PREAMBLE (0x0040)\r
+#define PHY_BMSR_AN_COMPLETE (0x0020)\r
+#define PHY_BMSR_REMOTE_FAULT (0x0010)\r
+#define PHY_BMSR_AN_ABILITY (0x0008)\r
+#define PHY_BMSR_LINK (0x0004)\r
+#define PHY_BMSR_JABBER (0x0002)\r
+#define PHY_BMSR_EXTENDED (0x0001)\r
+\r
+/* Bit definitions and macros for PHY_AN_ADV */\r
+#define PHY_ANAR_NEXT_PAGE (0x8001)\r
+#define PHY_ANAR_REM_FAULT (0x2001)\r
+#define PHY_ANAR_PAUSE (0x0401)\r
+#define PHY_ANAR_100BT4 (0x0201)\r
+#define PHY_ANAR_100BTX_FDX (0x0101)\r
+#define PHY_ANAR_100BTX (0x0081)\r
+#define PHY_ANAR_10BT_FDX (0x0041)\r
+#define PHY_ANAR_10BT (0x0021)\r
+#define PHY_ANAR_802_3 (0x0001)\r
+\r
+/* Bit definitions and macros for PHY_AN_LINK_PAR */\r
+#define PHY_ANLPAR_NEXT_PAGE (0x8000)\r
+#define PHY_ANLPAR_ACK (0x4000)\r
+#define PHY_ANLPAR_REM_FAULT (0x2000)\r
+#define PHY_ANLPAR_PAUSE (0x0400)\r
+#define PHY_ANLPAR_100BT4 (0x0200)\r
+#define PHY_ANLPAR_100BTX_FDX (0x0100)\r
+#define PHY_ANLPAR_100BTX (0x0080)\r
+#define PHY_ANLPAR_10BTX_FDX (0x0040)\r
+#define PHY_ANLPAR_10BT (0x0020)\r
+\r
+/*******************************************************************/\r
+\r
+#endif /* _ETH_PHY_H */\r
--- /dev/null
+/*\r
+ * File: fecbd.h\r
+ * Purpose:\r
+ *\r
+ * Purpose: Provide a simple buffer management driver\r
+ */\r
+\r
+#ifndef _FECBD_H_\r
+#define _FECBD_H_\r
+\r
+/********************************************************************/\r
+\r
+#define Rx 1\r
+#define Tx 0\r
+\r
+/*\r
+ * Buffer sizes in bytes\r
+ */\r
+#ifndef RX_BUF_SZ\r
+#define RX_BUF_SZ 1520 //2048\r
+#endif\r
+#ifndef TX_BUF_SZ\r
+#define TX_BUF_SZ 1520\r
+#endif\r
+\r
+/*\r
+ * Buffer Descriptor Format\r
+ */\r
+typedef struct\r
+{\r
+ uint16 status; /* control and status */\r
+ uint16 length; /* transfer length */\r
+ uint8 *data; /* buffer address */\r
+} FECBD;\r
+\r
+/*\r
+ * Bit level definitions for status field of buffer descriptors\r
+ */\r
+#define TX_BD_R 0x8000\r
+#define TX_BD_TO1 0x4000\r
+#define TX_BD_W 0x2000\r
+#define TX_BD_TO2 0x1000\r
+#define TX_BD_INTERRUPT 0x1000 /* MCF547x/8x Only */\r
+#define TX_BD_L 0x0800\r
+#define TX_BD_TC 0x0400\r
+#define TX_BD_DEF 0x0200 /* MCF5272 Only */\r
+#define TX_BD_ABC 0x0200\r
+#define TX_BD_HB 0x0100 /* MCF5272 Only */\r
+#define TX_BD_LC 0x0080 /* MCF5272 Only */\r
+#define TX_BD_RL 0x0040 /* MCF5272 Only */\r
+#define TX_BD_UN 0x0002 /* MCF5272 Only */\r
+#define TX_BD_CSL 0x0001 /* MCF5272 Only */\r
+\r
+#define RX_BD_E 0x8000\r
+#define RX_BD_R01 0x4000\r
+#define RX_BD_W 0x2000\r
+#define RX_BD_R02 0x1000\r
+#define RX_BD_INTERRUPT 0x1000 /* MCF547x/8x Only */\r
+#define RX_BD_L 0x0800\r
+#define RX_BD_M 0x0100\r
+#define RX_BD_BC 0x0080\r
+#define RX_BD_MC 0x0040\r
+#define RX_BD_LG 0x0020\r
+#define RX_BD_NO 0x0010\r
+#define RX_BD_CR 0x0004\r
+#define RX_BD_OV 0x0002\r
+#define RX_BD_TR 0x0001\r
+#define RX_BD_ERROR (RX_BD_NO | RX_BD_CR | RX_BD_OV | RX_BD_TR)\r
+\r
+/*\r
+ * The following defines are provided by the MCF547x/8x\r
+ * DMA API. These are shown here to show their correlation\r
+ * to the other FEC buffer descriptor status bits\r
+ *\r
+ * #define MCD_FEC_BUF_READY 0x8000\r
+ * #define MCD_FEC_WRAP 0x2000\r
+ * #define MCD_FEC_INTERRUPT 0x1000\r
+ * #define MCD_FEC_END_FRAME 0x0800\r
+ */\r
+\r
+/*\r
+ * Functions provided in fec_bd.c\r
+ */\r
+int fecbd_init(int, int, int);\r
+void fecbd_flush(int);\r
+void fecbd_dump( void );\r
+uint32 fecbd_get_start(int, int);\r
+FECBD* fecbd_rx_alloc(int);\r
+FECBD* fecbd_tx_alloc(int);\r
+FECBD* fecbd_tx_free(int);\r
+\r
+/*\r
+ * Error codes\r
+ */\r
+#define ERR_MALLOC (-1)\r
+#define ERR_NBUFALLOC (-2)\r
+\r
+/*******************************************************************/\r
+\r
+#endif /* _FECBD_H_ */\r
--- /dev/null
+const char http_http[8] = \r
+/* "http://" */\r
+{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, };\r
+const char http_200[5] = \r
+/* "200 " */\r
+{0x32, 0x30, 0x30, 0x20, };\r
+const char http_301[5] = \r
+/* "301 " */\r
+{0x33, 0x30, 0x31, 0x20, };\r
+const char http_302[5] = \r
+/* "302 " */\r
+{0x33, 0x30, 0x32, 0x20, };\r
+const char http_get[5] = \r
+/* "GET " */\r
+{0x47, 0x45, 0x54, 0x20, };\r
+const char http_10[9] = \r
+/* "HTTP/1.0" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, };\r
+const char http_11[9] = \r
+/* "HTTP/1.1" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, };\r
+const char http_content_type[15] = \r
+/* "content-type: " */\r
+{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, };\r
+const char http_texthtml[10] = \r
+/* "text/html" */\r
+{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_location[11] = \r
+/* "location: " */\r
+{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, };\r
+const char http_host[7] = \r
+/* "host: " */\r
+{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, };\r
+const char http_crnl[3] = \r
+/* "\r\n" */\r
+{0xd, 0xa, };\r
+const char http_index_html[12] = \r
+/* "/index.html" */\r
+{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_404_html[10] = \r
+/* "/404.html" */\r
+{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_referer[9] = \r
+/* "Referer:" */\r
+{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, };\r
+const char http_header_200[84] = \r
+/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };\r
+const char http_header_404[91] = \r
+/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };\r
+const char http_content_type_plain[29] = \r
+/* "Content-type: text/plain\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_html[28] = \r
+/* "Content-type: text/html\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_css [27] = \r
+/* "Content-type: text/css\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_text[28] = \r
+/* "Content-type: text/text\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_png [28] = \r
+/* "Content-type: image/png\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_gif [28] = \r
+/* "Content-type: image/gif\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_jpg [29] = \r
+/* "Content-type: image/jpeg\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_binary[43] = \r
+/* "Content-type: application/octet-stream\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_html[6] = \r
+/* ".html" */\r
+{0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_shtml[7] = \r
+/* ".shtml" */\r
+{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_htm[5] = \r
+/* ".htm" */\r
+{0x2e, 0x68, 0x74, 0x6d, };\r
+const char http_css[5] = \r
+/* ".css" */\r
+{0x2e, 0x63, 0x73, 0x73, };\r
+const char http_png[5] = \r
+/* ".png" */\r
+{0x2e, 0x70, 0x6e, 0x67, };\r
+const char http_gif[5] = \r
+/* ".gif" */\r
+{0x2e, 0x67, 0x69, 0x66, };\r
+const char http_jpg[5] = \r
+/* ".jpg" */\r
+{0x2e, 0x6a, 0x70, 0x67, };\r
+const char http_text[5] = \r
+/* ".txt" */\r
+{0x2e, 0x74, 0x78, 0x74, };\r
+const char http_txt[5] = \r
+/* ".txt" */\r
+{0x2e, 0x74, 0x78, 0x74, };\r
--- /dev/null
+extern const char http_http[8];\r
+extern const char http_200[5];\r
+extern const char http_301[5];\r
+extern const char http_302[5];\r
+extern const char http_get[5];\r
+extern const char http_10[9];\r
+extern const char http_11[9];\r
+extern const char http_content_type[15];\r
+extern const char http_texthtml[10];\r
+extern const char http_location[11];\r
+extern const char http_host[7];\r
+extern const char http_crnl[3];\r
+extern const char http_index_html[12];\r
+extern const char http_404_html[10];\r
+extern const char http_referer[9];\r
+extern const char http_header_200[84];\r
+extern const char http_header_404[91];\r
+extern const char http_content_type_plain[29];\r
+extern const char http_content_type_html[28];\r
+extern const char http_content_type_css [27];\r
+extern const char http_content_type_text[28];\r
+extern const char http_content_type_png [28];\r
+extern const char http_content_type_gif [28];\r
+extern const char http_content_type_jpg [29];\r
+extern const char http_content_type_binary[43];\r
+extern const char http_html[6];\r
+extern const char http_shtml[7];\r
+extern const char http_htm[5];\r
+extern const char http_css[5];\r
+extern const char http_png[5];\r
+extern const char http_gif[5];\r
+extern const char http_jpg[5];\r
+extern const char http_text[5];\r
+extern const char http_txt[5];\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Web server script interface\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2006, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $\r
+ *\r
+ */\r
+\r
+#include "uip.h"\r
+#include "psock.h"\r
+#include "httpd.h"\r
+#include "httpd-cgi.h"\r
+#include "httpd-fs.h"\r
+\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+\r
+HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats );\r
+\r
+static const struct httpd_cgi_call *calls[] = { &rtos, NULL };\r
+\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(nullfunction(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+ ( void ) ptr;\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+httpd_cgifunction\r
+httpd_cgi(char *name)\r
+{\r
+ const struct httpd_cgi_call **f;\r
+\r
+ /* Find the matching name in the table, return the function. */\r
+ for(f = calls; *f != NULL; ++f) {\r
+ if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) {\r
+ return (*f)->function;\r
+ }\r
+ }\r
+ return nullfunction;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static const char closed[] = /* "CLOSED",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0};\r
+static const char syn_rcvd[] = /* "SYN-RCVD",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56,\r
+ 0x44, 0};\r
+static const char syn_sent[] = /* "SYN-SENT",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e,\r
+ 0x54, 0};\r
+static const char established[] = /* "ESTABLISHED",*/\r
+{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48,\r
+ 0x45, 0x44, 0};\r
+static const char fin_wait_1[] = /* "FIN-WAIT-1",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,\r
+ 0x54, 0x2d, 0x31, 0};\r
+static const char fin_wait_2[] = /* "FIN-WAIT-2",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,\r
+ 0x54, 0x2d, 0x32, 0};\r
+static const char closing[] = /* "CLOSING",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x49,\r
+ 0x4e, 0x47, 0};\r
+static const char time_wait[] = /* "TIME-WAIT,"*/\r
+{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41,\r
+ 0x49, 0x54, 0};\r
+static const char last_ack[] = /* "LAST-ACK"*/\r
+{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43,\r
+ 0x4b, 0};\r
+\r
+\r
+/*---------------------------------------------------------------------------*/\r
+\r
+extern void vTaskList( signed char *pcWriteBuffer );\r
+static char cCountBuf[ 32 ];\r
+long lRefreshCount = 0;\r
+\r
+static unsigned short\r
+generate_rtos_stats(void *arg)\r
+{\r
+ ( void ) arg;\r
+\r
+ lRefreshCount++;\r
+ sprintf( cCountBuf, "<p><br>Refresh count = %d", (int) lRefreshCount );\r
+ vTaskList( uip_appdata );\r
+ strcat( uip_appdata, cCountBuf );\r
+\r
+ return strlen( uip_appdata );\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+\r
+static\r
+PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+ ( void ) ptr;\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL);\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+\r
+/** @} */\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Web server script interface header file\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __HTTPD_CGI_H__\r
+#define __HTTPD_CGI_H__\r
+\r
+#include "psock.h"\r
+#include "httpd.h"\r
+\r
+typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *));\r
+\r
+httpd_cgifunction httpd_cgi(char *name);\r
+\r
+struct httpd_cgi_call {\r
+ const char *name;\r
+ const httpd_cgifunction function;\r
+};\r
+\r
+/**\r
+ * \brief HTTPD CGI function declaration\r
+ * \param name The C variable name of the function\r
+ * \param str The string name of the function, used in the script file\r
+ * \param function A pointer to the function that implements it\r
+ *\r
+ * This macro is used for declaring a HTTPD CGI\r
+ * function. This function is then added to the list of\r
+ * HTTPD CGI functions with the httpd_cgi_add() function.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define HTTPD_CGI_CALL(name, str, function) \\r
+static PT_THREAD(function(struct httpd_state *, char *)); \\r
+static const struct httpd_cgi_call name = {str, function}\r
+\r
+void httpd_cgi_init(void);\r
+#endif /* __HTTPD_CGI_H__ */\r
+\r
+/** @} */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+\r
+#include "httpd.h"\r
+#include "httpd-fs.h"\r
+#include "httpd-fsdata.h"\r
+\r
+#ifndef NULL\r
+#define NULL 0\r
+#endif /* NULL */\r
+\r
+#include "httpd-fsdata.c"\r
+\r
+#if HTTPD_FS_STATISTICS\r
+static u16_t count[HTTPD_FS_NUMFILES];\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+static u8_t\r
+httpd_fs_strcmp(const char *str1, const char *str2)\r
+{\r
+ u8_t i;\r
+ i = 0;\r
+ loop:\r
+\r
+ if(str2[i] == 0 ||\r
+ str1[i] == '\r' ||\r
+ str1[i] == '\n') {\r
+ return 0;\r
+ }\r
+\r
+ if(str1[i] != str2[i]) {\r
+ return 1;\r
+ }\r
+\r
+\r
+ ++i;\r
+ goto loop;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+int\r
+httpd_fs_open(const char *name, struct httpd_fs_file *file)\r
+{\r
+#if HTTPD_FS_STATISTICS\r
+ u16_t i = 0;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+ struct httpd_fsdata_file_noconst *f;\r
+\r
+ for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;\r
+ f != NULL;\r
+ f = (struct httpd_fsdata_file_noconst *)f->next) {\r
+\r
+ if(httpd_fs_strcmp(name, f->name) == 0) {\r
+ file->data = f->data;\r
+ file->len = f->len;\r
+#if HTTPD_FS_STATISTICS\r
+ ++count[i];\r
+#endif /* HTTPD_FS_STATISTICS */\r
+ return 1;\r
+ }\r
+#if HTTPD_FS_STATISTICS\r
+ ++i;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+ }\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+httpd_fs_init(void)\r
+{\r
+#if HTTPD_FS_STATISTICS\r
+ u16_t i;\r
+ for(i = 0; i < HTTPD_FS_NUMFILES; i++) {\r
+ count[i] = 0;\r
+ }\r
+#endif /* HTTPD_FS_STATISTICS */\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+#if HTTPD_FS_STATISTICS\r
+u16_t httpd_fs_count\r
+(char *name)\r
+{\r
+ struct httpd_fsdata_file_noconst *f;\r
+ u16_t i;\r
+\r
+ i = 0;\r
+ for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;\r
+ f != NULL;\r
+ f = (struct httpd_fsdata_file_noconst *)f->next) {\r
+\r
+ if(httpd_fs_strcmp(name, f->name) == 0) {\r
+ return count[i];\r
+ }\r
+ ++i;\r
+ }\r
+ return 0;\r
+}\r
+#endif /* HTTPD_FS_STATISTICS */\r
+/*-----------------------------------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+#ifndef __HTTPD_FS_H__\r
+#define __HTTPD_FS_H__\r
+\r
+#define HTTPD_FS_STATISTICS 0\r
+\r
+struct httpd_fs_file {\r
+ char *data;\r
+ int len;\r
+};\r
+\r
+/* file must be allocated by caller and will be filled in\r
+ by the function. */\r
+int httpd_fs_open(const char *name, struct httpd_fs_file *file);\r
+\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+u16_t httpd_fs_count(char *name);\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+void httpd_fs_init(void);\r
+\r
+#endif /* __HTTPD_FS_H__ */\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY onLoad="window.setTimeout("location.href='index.shtml'",100)"bgcolor="#CCCCff">\r
+<font face="arial">\r
+Loading index.shtml. Click <a href="index.shtml">here</a> if not automatically redirected.\r
+</font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+ <head>\r
+ <title>FreeRTOS.org uIP WEB server demo</title>\r
+ </head>\r
+ <BODY onLoad="window.setTimeout("location.href='index.shtml'",2000)"bgcolor="#CCCCff">\r
+<font face="arial">\r
+<br><p>\r
+<h2>Task statistics</h2>\r
+Page will refresh every 2 seconds.<p>\r
+<font face="courier"><pre>Task State Priority Stack #<br>************************************************<br>\r
+%! rtos-stats\r
+</pre></font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
--- /dev/null
+static const unsigned char data_index_html[] = {
+ /* /index.html */
+ 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,
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+ 0x6d, 0x6c, 0x27, 0x26, 0x71, 0x75, 0x6f, 0x74, 0x3b, 0x2c,
+ 0x31, 0x30, 0x30, 0x29, 0x22, 0x62, 0x67, 0x63, 0x6f, 0x6c,
+ 0x6f, 0x72, 0x3d, 0x22, 0x23, 0x43, 0x43, 0x43, 0x43, 0x66,
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+ 0x66, 0x3d, 0x22, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x73,
+ 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x68, 0x65, 0x72, 0x65,
+ 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x69, 0x66, 0x20, 0x6e, 0x6f,
+ 0x74, 0x20, 0x61, 0x75, 0x74, 0x6f, 0x6d, 0x61, 0x74, 0x69,
+ 0x63, 0x61, 0x6c, 0x6c, 0x79, 0x20, 0x72, 0x65, 0x64, 0x69,
+ 0x72, 0x65, 0x63, 0x74, 0x65, 0x64, 0x2e, 0xd, 0xa, 0x3c,
+ 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f,
+ 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62,
+ 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74,
+ 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0xd, 0xa, 0};
+
+static const unsigned char data_index_shtml[] = {
+ /* /index.shtml */
+ 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,
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+ 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f,
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+ 0x6b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x53, 0x74, 0x61, 0x74, 0x65, 0x20, 0x20, 0x50, 0x72,
+ 0x69, 0x6f, 0x72, 0x69, 0x74, 0x79, 0x20, 0x20, 0x53, 0x74,
+ 0x61, 0x63, 0x6b, 0x9, 0x23, 0x3c, 0x62, 0x72, 0x3e, 0x2a,
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a,
+ 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x3c, 0x62, 0x72,
+ 0x3e, 0xd, 0xa, 0x25, 0x21, 0x20, 0x72, 0x74, 0x6f, 0x73,
+ 0x2d, 0x73, 0x74, 0x61, 0x74, 0x73, 0xd, 0xa, 0x3c, 0x2f,
+ 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74,
+ 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e,
+ 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xd,
+ 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa,
+ 0xd, 0xa, 0};
+
+const struct httpd_fsdata_file file_index_html[] = {{NULL, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}};
+
+const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}};
+
+#define HTTPD_FS_ROOT file_index_shtml
+
+#define HTTPD_FS_NUMFILES 2
--- /dev/null
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+#ifndef __HTTPD_FSDATA_H__\r
+#define __HTTPD_FSDATA_H__\r
+\r
+#include "uip.h"\r
+\r
+struct httpd_fsdata_file {\r
+ const struct httpd_fsdata_file *next;\r
+ const unsigned char *name;\r
+ const unsigned char *data;\r
+ const int len;\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+ u16_t count;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+};\r
+\r
+struct httpd_fsdata_file_noconst {\r
+ struct httpd_fsdata_file *next;\r
+ char *name;\r
+ char *data;\r
+ int len;\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+ u16_t count;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+};\r
+\r
+#endif /* __HTTPD_FSDATA_H__ */\r
--- /dev/null
+/**\r
+ * \addtogroup apps\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \defgroup httpd Web server\r
+ * @{\r
+ * The uIP web server is a very simplistic implementation of an HTTP\r
+ * server. It can serve web pages and files from a read-only ROM\r
+ * filesystem, and provides a very small scripting language.\r
+\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * Web server\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ */\r
+\r
+\r
+/*\r
+ * Copyright (c) 2004, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ */\r
+\r
+#include "uip.h"\r
+#include "httpd.h"\r
+#include "httpd-fs.h"\r
+#include "httpd-cgi.h"\r
+#include "http-strings.h"\r
+\r
+#include <string.h>\r
+\r
+#define STATE_WAITING 0\r
+#define STATE_OUTPUT 1\r
+\r
+#define ISO_nl 0x0a\r
+#define ISO_space 0x20\r
+#define ISO_bang 0x21\r
+#define ISO_percent 0x25\r
+#define ISO_period 0x2e\r
+#define ISO_slash 0x2f\r
+#define ISO_colon 0x3a\r
+\r
+\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_part_of_file(void *state)\r
+{\r
+ struct httpd_state *s = (struct httpd_state *)state;\r
+\r
+ if(s->file.len > uip_mss()) {\r
+ s->len = uip_mss();\r
+ } else {\r
+ s->len = s->file.len;\r
+ }\r
+ memcpy(uip_appdata, s->file.data, s->len);\r
+\r
+ return s->len;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_file(struct httpd_state *s))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+ do {\r
+ PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s);\r
+ s->file.len -= s->len;\r
+ s->file.data += s->len;\r
+ } while(s->file.len > 0);\r
+\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_part_of_file(struct httpd_state *s))\r
+{\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+ PSOCK_SEND(&s->sout, s->file.data, s->len);\r
+\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static void\r
+next_scriptstate(struct httpd_state *s)\r
+{\r
+ char *p;\r
+ p = strchr(s->scriptptr, ISO_nl) + 1;\r
+ s->scriptlen -= (unsigned short)(p - s->scriptptr);\r
+ s->scriptptr = p;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_script(struct httpd_state *s))\r
+{\r
+ char *ptr;\r
+\r
+ PT_BEGIN(&s->scriptpt);\r
+\r
+\r
+ while(s->file.len > 0) {\r
+\r
+ /* Check if we should start executing a script. */\r
+ if(*s->file.data == ISO_percent &&\r
+ *(s->file.data + 1) == ISO_bang) {\r
+ s->scriptptr = s->file.data + 3;\r
+ s->scriptlen = s->file.len - 3;\r
+ if(*(s->scriptptr - 1) == ISO_colon) {\r
+ httpd_fs_open(s->scriptptr + 1, &s->file);\r
+ PT_WAIT_THREAD(&s->scriptpt, send_file(s));\r
+ } else {\r
+ PT_WAIT_THREAD(&s->scriptpt,\r
+ httpd_cgi(s->scriptptr)(s, s->scriptptr));\r
+ }\r
+ next_scriptstate(s);\r
+\r
+ /* The script is over, so we reset the pointers and continue\r
+ sending the rest of the file. */\r
+ s->file.data = s->scriptptr;\r
+ s->file.len = s->scriptlen;\r
+ } else {\r
+ /* See if we find the start of script marker in the block of HTML\r
+ to be sent. */\r
+\r
+ if(s->file.len > uip_mss()) {\r
+ s->len = uip_mss();\r
+ } else {\r
+ s->len = s->file.len;\r
+ }\r
+\r
+ if(*s->file.data == ISO_percent) {\r
+ ptr = strchr(s->file.data + 1, ISO_percent);\r
+ } else {\r
+ ptr = strchr(s->file.data, ISO_percent);\r
+ }\r
+ if(ptr != NULL &&\r
+ ptr != s->file.data) {\r
+ s->len = (int)(ptr - s->file.data);\r
+ if(s->len >= uip_mss()) {\r
+ s->len = uip_mss();\r
+ }\r
+ }\r
+ PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s));\r
+ s->file.data += s->len;\r
+ s->file.len -= s->len;\r
+\r
+ }\r
+ }\r
+\r
+ PT_END(&s->scriptpt);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr))\r
+{\r
+ char *ptr;\r
+\r
+ PSOCK_BEGIN(&s->sout);\r
+\r
+ PSOCK_SEND_STR(&s->sout, statushdr);\r
+\r
+ ptr = strrchr(s->filename, ISO_period);\r
+ if(ptr == NULL) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_binary);\r
+ } else if(strncmp(http_html, ptr, 5) == 0 ||\r
+ strncmp(http_shtml, ptr, 6) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_html);\r
+ } else if(strncmp(http_css, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_css);\r
+ } else if(strncmp(http_png, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_png);\r
+ } else if(strncmp(http_gif, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_gif);\r
+ } else if(strncmp(http_jpg, ptr, 4) == 0) {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_jpg);\r
+ } else {\r
+ PSOCK_SEND_STR(&s->sout, http_content_type_plain);\r
+ }\r
+ PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_output(struct httpd_state *s))\r
+{\r
+ char *ptr;\r
+\r
+ PT_BEGIN(&s->outputpt);\r
+\r
+ if(!httpd_fs_open(s->filename, &s->file)) {\r
+ httpd_fs_open(http_404_html, &s->file);\r
+ strcpy(s->filename, http_404_html);\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_headers(s,\r
+ http_header_404));\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_file(s));\r
+ } else {\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_headers(s,\r
+ http_header_200));\r
+ ptr = strchr(s->filename, ISO_period);\r
+ if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) {\r
+ PT_INIT(&s->scriptpt);\r
+ PT_WAIT_THREAD(&s->outputpt, handle_script(s));\r
+ } else {\r
+ PT_WAIT_THREAD(&s->outputpt,\r
+ send_file(s));\r
+ }\r
+ }\r
+ PSOCK_CLOSE(&s->sout);\r
+ PT_END(&s->outputpt);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_input(struct httpd_state *s))\r
+{\r
+ PSOCK_BEGIN(&s->sin);\r
+\r
+ PSOCK_READTO(&s->sin, ISO_space);\r
+\r
+\r
+ if(strncmp(s->inputbuf, http_get, 4) != 0) {\r
+ PSOCK_CLOSE_EXIT(&s->sin);\r
+ }\r
+ PSOCK_READTO(&s->sin, ISO_space);\r
+\r
+ if(s->inputbuf[0] != ISO_slash) {\r
+ PSOCK_CLOSE_EXIT(&s->sin);\r
+ }\r
+\r
+ if(s->inputbuf[1] == ISO_space) {\r
+ strncpy(s->filename, http_index_html, sizeof(s->filename));\r
+ } else {\r
+\r
+ s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0;\r
+\r
+ strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename));\r
+ }\r
+\r
+ /* httpd_log_file(uip_conn->ripaddr, s->filename);*/\r
+\r
+ s->state = STATE_OUTPUT;\r
+\r
+ while(1) {\r
+ PSOCK_READTO(&s->sin, ISO_nl);\r
+\r
+ if(strncmp(s->inputbuf, http_referer, 8) == 0) {\r
+ s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0;\r
+ /* httpd_log(&s->inputbuf[9]);*/\r
+ }\r
+ }\r
+\r
+ PSOCK_END(&s->sin);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static void\r
+handle_connection(struct httpd_state *s)\r
+{\r
+ handle_input(s);\r
+ if(s->state == STATE_OUTPUT) {\r
+ handle_output(s);\r
+ }\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+void\r
+httpd_appcall(void)\r
+{\r
+ struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate);\r
+\r
+ if(uip_closed() || uip_aborted() || uip_timedout()) {\r
+ } else if(uip_connected()) {\r
+ PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1);\r
+ PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1);\r
+ PT_INIT(&s->outputpt);\r
+ s->state = STATE_WAITING;\r
+ /* timer_set(&s->timer, CLOCK_SECOND * 100);*/\r
+ s->timer = 0;\r
+ handle_connection(s);\r
+ } else if(s != NULL) {\r
+ if(uip_poll()) {\r
+ ++s->timer;\r
+ if(s->timer >= 20) {\r
+ uip_abort();\r
+ }\r
+ } else {\r
+ s->timer = 0;\r
+ }\r
+ handle_connection(s);\r
+ } else {\r
+ uip_abort();\r
+ }\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+/**\r
+ * \brief Initialize the web server\r
+ *\r
+ * This function initializes the web server and should be\r
+ * called at system boot-up.\r
+ */\r
+void\r
+httpd_init(void)\r
+{\r
+ uip_listen(HTONS(80));\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+/** @} */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2005, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __HTTPD_H__\r
+#define __HTTPD_H__\r
+\r
+#include "psock.h"\r
+#include "httpd-fs.h"\r
+\r
+struct httpd_state {\r
+ unsigned char timer;\r
+ struct psock sin, sout;\r
+ struct pt outputpt, scriptpt;\r
+ char inputbuf[50];\r
+ char filename[20];\r
+ char state;\r
+ struct httpd_fs_file file;\r
+ int len;\r
+ char *scriptptr;\r
+ int scriptlen;\r
+ \r
+ unsigned short count;\r
+};\r
+\r
+void httpd_init(void);\r
+void httpd_appcall(void);\r
+\r
+void httpd_log(char *msg);\r
+void httpd_log_file(u16_t *requester, char *file);\r
+\r
+#endif /* __HTTPD_H__ */\r
--- /dev/null
+#!/usr/bin/perl\r
+\r
+open(OUTPUT, "> httpd-fsdata.c");\r
+\r
+chdir("httpd-fs");\r
+\r
+opendir(DIR, ".");\r
+@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);\r
+closedir(DIR);\r
+\r
+foreach $file (@files) { \r
+ \r
+ if(-d $file && $file !~ /^\./) {\r
+ print "Processing directory $file\n";\r
+ opendir(DIR, $file);\r
+ @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);\r
+ closedir(DIR);\r
+ printf "Adding files @newfiles\n";\r
+ @files = (@files, map { $_ = "$file/$_" } @newfiles);\r
+ next;\r
+ }\r
+}\r
+\r
+foreach $file (@files) {\r
+ if(-f $file) {\r
+ \r
+ print "Adding file $file\n";\r
+ \r
+ open(FILE, $file) || die "Could not open file $file\n";\r
+\r
+ $file =~ s-^-/-;\r
+ $fvar = $file;\r
+ $fvar =~ s-/-_-g;\r
+ $fvar =~ s-\.-_-g;\r
+ # for AVR, add PROGMEM here\r
+ print(OUTPUT "static const unsigned char data".$fvar."[] = {\n");\r
+ print(OUTPUT "\t/* $file */\n\t");\r
+ for($j = 0; $j < length($file); $j++) {\r
+ printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1)));\r
+ }\r
+ printf(OUTPUT "0,\n");\r
+ \r
+ \r
+ $i = 0; \r
+ while(read(FILE, $data, 1)) {\r
+ if($i == 0) {\r
+ print(OUTPUT "\t");\r
+ }\r
+ printf(OUTPUT "%#02x, ", unpack("C", $data));\r
+ $i++;\r
+ if($i == 10) {\r
+ print(OUTPUT "\n");\r
+ $i = 0;\r
+ }\r
+ }\r
+ print(OUTPUT "0};\n\n");\r
+ close(FILE);\r
+ push(@fvars, $fvar);\r
+ push(@pfiles, $file);\r
+ }\r
+}\r
+\r
+for($i = 0; $i < @fvars; $i++) {\r
+ $file = $pfiles[$i];\r
+ $fvar = $fvars[$i];\r
+\r
+ if($i == 0) {\r
+ $prevfile = "NULL";\r
+ } else {\r
+ $prevfile = "file" . $fvars[$i - 1];\r
+ }\r
+ print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, ");\r
+ print(OUTPUT "data$fvar + ". (length($file) + 1) .", ");\r
+ print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n");\r
+}\r
+\r
+print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n");\r
+print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n");\r
--- /dev/null
+/*!\r
+ * \file mii.h\r
+ * \brief Media Independent Interface (MII) driver\r
+ * \version $Revision: 1.3 $\r
+ * \author Michael Norman\r
+ * \r
+ * \warning This driver assumes that FEC0 is used for all MII management\r
+ * communications. For dual PHYs, etc., insure that FEC0_MDC and\r
+ * FEC0_MDIO are connected to the PHY's MDC and MDIO.\r
+ */\r
+\r
+#ifndef _MII_H_\r
+#define _MII_H_\r
+\r
+/*******************************************************************/\r
+\r
+int\r
+mii_write(int, int, uint16);\r
+\r
+int\r
+mii_read(int, int, uint16*);\r
+\r
+void\r
+mii_init(int);\r
+\r
+/* MII Speed Settings */\r
+typedef enum {\r
+ MII_10BASE_T, /*!< 10Base-T operation */\r
+ MII_100BASE_TX /*!< 100Base-TX operation */\r
+} MII_SPEED;\r
+\r
+/* MII Duplex Settings */\r
+typedef enum {\r
+ MII_HDX, /*!< half-duplex */\r
+ MII_FDX /*!< full-duplex */\r
+} MII_DUPLEX;\r
+\r
+#define MII_TIMEOUT 0x10000\r
+#define MII_LINK_TIMEOUT 0x10000\r
+\r
+/*******************************************************************/\r
+\r
+#endif /* _MII_H_ */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license\r
+ and contact details. Please ensure to read the configuration and relevant\r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* uip includes. */\r
+#include "uip.h"\r
+#include "uip_arp.h"\r
+#include "httpd.h"\r
+#include "timer.h"\r
+#include "clock-arch.h"\r
+\r
+/* Demo includes. */\r
+#include "FEC.h"\r
+#include "partest.h"\r
+\r
+//struct timer {\r
+// clock_time_t start;\r
+// clock_time_t interval;\r
+//};\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* How long to wait before attempting to connect the MAC again. */\r
+#define uipINIT_WAIT 100\r
+\r
+/* Shortcut to the header within the Rx buffer. */\r
+#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ])\r
+\r
+/* Standard constant. */\r
+#define uipTOTAL_FRAME_HEADER_SIZE 54\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Port functions required by the uIP stack.\r
+ */\r
+void clock_init( void );\r
+clock_time_t clock_time( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The semaphore used by the ISR to wake the uIP task. */\r
+extern xSemaphoreHandle xFECSemaphore;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void clock_init(void)\r
+{\r
+ /* This is done when the scheduler starts. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Define clock functions here to avoid header file name clash between uIP\r
+and the Luminary Micro driver library. */\r
+clock_time_t clock_time( void )\r
+{\r
+ return xTaskGetTickCount();\r
+}\r
+extern void timer_set(struct timer *t, clock_time_t interval);\r
+extern int timer_expired(struct timer *t);\r
+extern void timer_reset(struct timer *t);\r
+\r
+\r
+\r
+\r
+void vuIP_Task( void *pvParameters )\r
+{\r
+portBASE_TYPE i;\r
+uip_ipaddr_t xIPAddr;\r
+struct timer periodic_timer, arp_timer;\r
+extern void ( vEMAC_ISR )( void );\r
+\r
+ /* To prevent compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise the uIP stack. */\r
+ timer_set( &periodic_timer, configTICK_RATE_HZ / 2 );\r
+ timer_set( &arp_timer, configTICK_RATE_HZ * 10 );\r
+ uip_init();\r
+ uip_ipaddr( xIPAddr, configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 );\r
+ uip_sethostaddr( xIPAddr );\r
+ httpd_init();\r
+\r
+ vInitFEC();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Is there received data ready to be processed? */\r
+ uip_len = usGetFECRxData();\r
+\r
+ if( uip_len > 0 )\r
+ {\r
+ /* Standard uIP loop taken from the uIP manual. */\r
+\r
+ if( xHeader->type == htons( UIP_ETHTYPE_IP ) )\r
+ {\r
+ uip_arp_ipin();\r
+ uip_input();\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ uip_arp_out();\r
+ vSendBufferToFEC();\r
+ }\r
+ else\r
+ {\r
+ vDiscardRxData();\r
+ }\r
+ }\r
+ else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) )\r
+ {\r
+ uip_arp_arpin();\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ vSendBufferToFEC();\r
+ }\r
+ else\r
+ {\r
+ vDiscardRxData();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ vDiscardRxData();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if( timer_expired( &periodic_timer ) )\r
+ {\r
+ timer_reset( &periodic_timer );\r
+ for( i = 0; i < UIP_CONNS; i++ )\r
+ {\r
+ uip_periodic( i );\r
+\r
+ /* If the above function invocation resulted in data that\r
+ should be sent out on the network, the global variable\r
+ uip_len is set to a value > 0. */\r
+ if( uip_len > 0 )\r
+ {\r
+ uip_arp_out();\r
+ vSendBufferToFEC();\r
+ }\r
+ }\r
+\r
+ /* Call the ARP timer function every 10 seconds. */\r
+ if( timer_expired( &arp_timer ) )\r
+ {\r
+ timer_reset( &arp_timer );\r
+ uip_arp_timer();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* We did not receive a packet, and there was no periodic\r
+ processing to perform. Block for a fixed period. If a packet\r
+ is received during this period we will be woken by the ISR\r
+ giving us the Semaphore. */\r
+ xSemaphoreTake( xFECSemaphore, configTICK_RATE_HZ / 2 );\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationProcessFormInput( portCHAR *pcInputString )\r
+{\r
+char *c;\r
+\r
+ /* Process the form input sent by the IO page of the served HTML. */\r
+\r
+ c = strstr( pcInputString, "?" );\r
+\r
+ if( c )\r
+ {\r
+ /* Turn LED's on or off in accordance with the check box status. */\r
+ if( strstr( c, "LED0=1" ) != NULL )\r
+ {\r
+ vParTestSetLED( 0, 1 );\r
+ }\r
+ else\r
+ {\r
+ vParTestSetLED( 0, 0 );\r
+ }\r
+ }\r
+}\r
+\r
--- /dev/null
+/**\r
+ * \addtogroup uipopt\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Project-specific configuration options\r
+ * @{\r
+ *\r
+ * uIP has a number of configuration options that can be overridden\r
+ * for each project. These are kept in a project-specific uip-conf.h\r
+ * file and all configuration names have the prefix UIP_CONF.\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2006, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * An example uIP configuration file\r
+ * \author\r
+ * Adam Dunkels <adam@sics.se>\r
+ */\r
+\r
+#ifndef __UIP_CONF_H__\r
+#define __UIP_CONF_H__\r
+\r
+#include <stdint.h>\r
+\r
+/**\r
+ * 8 bit datatype\r
+ *\r
+ * This typedef defines the 8-bit type used throughout uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef uint8_t u8_t;\r
+\r
+/**\r
+ * 16 bit datatype\r
+ *\r
+ * This typedef defines the 16-bit type used throughout uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef uint16_t u16_t;\r
+\r
+/**\r
+ * Statistics datatype\r
+ *\r
+ * This typedef defines the dataype used for keeping statistics in\r
+ * uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef unsigned short uip_stats_t;\r
+\r
+/**\r
+ * Maximum number of TCP connections.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_MAX_CONNECTIONS 40\r
+\r
+/**\r
+ * Maximum number of listening TCP ports.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_MAX_LISTENPORTS 40\r
+\r
+/**\r
+ * uIP buffer size.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_BUFFER_SIZE 1500\r
+\r
+/**\r
+ * CPU byte order.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_BYTE_ORDER UIP_BIG_ENDIAN\r
+\r
+/**\r
+ * Logging on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_LOGGING 0\r
+\r
+/**\r
+ * UDP support on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_UDP 0\r
+\r
+/**\r
+ * UDP checksums on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_UDP_CHECKSUMS 1\r
+\r
+/**\r
+ * uIP statistics on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_STATISTICS 1\r
+\r
+/* Here we include the header file for the application(s) we use in\r
+ our project. */\r
+/*#include "smtp.h"*/\r
+/*#include "hello-world.h"*/\r
+/*#include "telnetd.h"*/\r
+#include "webserver.h"\r
+/*#include "dhcpc.h"*/\r
+/*#include "resolv.h"*/\r
+/*#include "webclient.h"*/\r
+\r
+#define UIP_CONF_EXTERNAL_BUFFER\r
+\r
+\r
+#define FRAME_MULTIPLE 1\r
+\r
+#endif /* __UIP_CONF_H__ */\r
+\r
+/** @} */\r
+/** @} */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2002, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above\r
+ * copyright notice, this list of conditions and the following\r
+ * disclaimer in the documentation and/or other materials provided\r
+ * with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ * products derived from this software without specific prior\r
+ * written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+#ifndef __WEBSERVER_H__\r
+#define __WEBSERVER_H__\r
+\r
+#include "httpd.h"\r
+\r
+typedef struct httpd_state uip_tcp_appstate_t;\r
+/* UIP_APPCALL: the name of the application function. This function\r
+ must return void and take no arguments (i.e., C type "void\r
+ appfunc(void)"). */\r
+#ifndef UIP_APPCALL\r
+#define UIP_APPCALL httpd_appcall\r
+#endif\r
+\r
+\r
+#endif /* __WEBSERVER_H__ */\r
projects / freertos / commitdiff