John McCarthy <jgmcc@magma.ca> two patches add a mips_m4k target option (ejtag_reset...

srst to a system reset (I believe it just goes to a GPIO).

git-svn-id: svn://svn.berlios.de/openocd/trunk@1050 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index be7f59ec8c38ab7e2bd334605985f110b59c14a9..04c9a1eff0ca83d64dbc1321a6e6b33e9e24ddea 100644 (file)
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -256,14 +256,21 @@ int mips_m4k_assert_reset(target_t *target)
                mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
        }
        
-       /* here we should issue a srst only, but we may have to assert trst as well */
-       if (jtag_reset_config & RESET_SRST_PULLS_TRST)
-       {
-               jtag_add_reset(1, 1);
-       }
-       else
-       {
-               jtag_add_reset(0, 1);
+       if (strcmp(target->variant, "ejtag_srst") == 0) {
+               u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
+               LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
+               mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       } else {
+               /* here we should issue a srst only, but we may have to assert trst as well */
+               if (jtag_reset_config & RESET_SRST_PULLS_TRST)
+               {
+                       jtag_add_reset(1, 1);
+               }
+               else
+               {
+                       jtag_add_reset(0, 1);
+               }
        }
        
        target->state = TARGET_RESET;